16,197 → 16,24 |
#ifndef LINUX_PCI_H |
#define LINUX_PCI_H |
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#include <linux/mod_devicetable.h> |
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#include <linux/types.h> |
#include <linux/init.h> |
#include <linux/ioport.h> |
#include <linux/list.h> |
#include <linux/compiler.h> |
#include <linux/errno.h> |
#include <linux/kobject.h> |
#include <linux/atomic.h> |
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#include <linux/pci_regs.h> /* The pci register defines */ |
#include <linux/ioport.h> |
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#include <linux/device.h> |
#include <linux/io.h> |
#include <linux/resource_ext.h> |
#include <uapi/linux/pci.h> |
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#if 0 |
struct device |
{ |
struct device *parent; |
void *driver_data; |
}; |
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#endif |
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#define PCI_CFG_SPACE_SIZE 256 |
#define PCI_CFG_SPACE_EXP_SIZE 4096 |
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#define PCI_ANY_ID (~0) |
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#define PCI_CLASS_NOT_DEFINED 0x0000 |
#define PCI_CLASS_NOT_DEFINED_VGA 0x0001 |
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#define PCI_BASE_CLASS_STORAGE 0x01 |
#define PCI_CLASS_STORAGE_SCSI 0x0100 |
#define PCI_CLASS_STORAGE_IDE 0x0101 |
#define PCI_CLASS_STORAGE_FLOPPY 0x0102 |
#define PCI_CLASS_STORAGE_IPI 0x0103 |
#define PCI_CLASS_STORAGE_RAID 0x0104 |
#define PCI_CLASS_STORAGE_SATA 0x0106 |
#define PCI_CLASS_STORAGE_SATA_AHCI 0x010601 |
#define PCI_CLASS_STORAGE_SAS 0x0107 |
#define PCI_CLASS_STORAGE_OTHER 0x0180 |
|
#define PCI_BASE_CLASS_NETWORK 0x02 |
#define PCI_CLASS_NETWORK_ETHERNET 0x0200 |
#define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 |
#define PCI_CLASS_NETWORK_FDDI 0x0202 |
#define PCI_CLASS_NETWORK_ATM 0x0203 |
#define PCI_CLASS_NETWORK_OTHER 0x0280 |
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#define PCI_BASE_CLASS_DISPLAY 0x03 |
#define PCI_CLASS_DISPLAY_VGA 0x0300 |
#define PCI_CLASS_DISPLAY_XGA 0x0301 |
#define PCI_CLASS_DISPLAY_3D 0x0302 |
#define PCI_CLASS_DISPLAY_OTHER 0x0380 |
|
#define PCI_BASE_CLASS_MULTIMEDIA 0x04 |
#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 |
#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 |
#define PCI_CLASS_MULTIMEDIA_PHONE 0x0402 |
#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 |
|
#define PCI_BASE_CLASS_MEMORY 0x05 |
#define PCI_CLASS_MEMORY_RAM 0x0500 |
#define PCI_CLASS_MEMORY_FLASH 0x0501 |
#define PCI_CLASS_MEMORY_OTHER 0x0580 |
|
#define PCI_BASE_CLASS_BRIDGE 0x06 |
#define PCI_CLASS_BRIDGE_HOST 0x0600 |
#define PCI_CLASS_BRIDGE_ISA 0x0601 |
#define PCI_CLASS_BRIDGE_EISA 0x0602 |
#define PCI_CLASS_BRIDGE_MC 0x0603 |
#define PCI_CLASS_BRIDGE_PCI 0x0604 |
#define PCI_CLASS_BRIDGE_PCMCIA 0x0605 |
#define PCI_CLASS_BRIDGE_NUBUS 0x0606 |
#define PCI_CLASS_BRIDGE_CARDBUS 0x0607 |
#define PCI_CLASS_BRIDGE_RACEWAY 0x0608 |
#define PCI_CLASS_BRIDGE_OTHER 0x0680 |
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#define PCI_BASE_CLASS_COMMUNICATION 0x07 |
#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 |
#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 |
#define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702 |
#define PCI_CLASS_COMMUNICATION_MODEM 0x0703 |
#define PCI_CLASS_COMMUNICATION_OTHER 0x0780 |
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#define PCI_BASE_CLASS_SYSTEM 0x08 |
#define PCI_CLASS_SYSTEM_PIC 0x0800 |
#define PCI_CLASS_SYSTEM_PIC_IOAPIC 0x080010 |
#define PCI_CLASS_SYSTEM_PIC_IOXAPIC 0x080020 |
#define PCI_CLASS_SYSTEM_DMA 0x0801 |
#define PCI_CLASS_SYSTEM_TIMER 0x0802 |
#define PCI_CLASS_SYSTEM_RTC 0x0803 |
#define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804 |
#define PCI_CLASS_SYSTEM_SDHCI 0x0805 |
#define PCI_CLASS_SYSTEM_OTHER 0x0880 |
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#define PCI_BASE_CLASS_INPUT 0x09 |
#define PCI_CLASS_INPUT_KEYBOARD 0x0900 |
#define PCI_CLASS_INPUT_PEN 0x0901 |
#define PCI_CLASS_INPUT_MOUSE 0x0902 |
#define PCI_CLASS_INPUT_SCANNER 0x0903 |
#define PCI_CLASS_INPUT_GAMEPORT 0x0904 |
#define PCI_CLASS_INPUT_OTHER 0x0980 |
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#define PCI_BASE_CLASS_DOCKING 0x0a |
#define PCI_CLASS_DOCKING_GENERIC 0x0a00 |
#define PCI_CLASS_DOCKING_OTHER 0x0a80 |
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#define PCI_BASE_CLASS_PROCESSOR 0x0b |
#define PCI_CLASS_PROCESSOR_386 0x0b00 |
#define PCI_CLASS_PROCESSOR_486 0x0b01 |
#define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 |
#define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 |
#define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 |
#define PCI_CLASS_PROCESSOR_MIPS 0x0b30 |
#define PCI_CLASS_PROCESSOR_CO 0x0b40 |
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#define PCI_BASE_CLASS_SERIAL 0x0c |
#define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 |
#define PCI_CLASS_SERIAL_FIREWIRE_OHCI 0x0c0010 |
#define PCI_CLASS_SERIAL_ACCESS 0x0c01 |
#define PCI_CLASS_SERIAL_SSA 0x0c02 |
#define PCI_CLASS_SERIAL_USB 0x0c03 |
#define PCI_CLASS_SERIAL_USB_UHCI 0x0c0300 |
#define PCI_CLASS_SERIAL_USB_OHCI 0x0c0310 |
#define PCI_CLASS_SERIAL_USB_EHCI 0x0c0320 |
#define PCI_CLASS_SERIAL_FIBER 0x0c04 |
#define PCI_CLASS_SERIAL_SMBUS 0x0c05 |
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#define PCI_BASE_CLASS_WIRELESS 0x0d |
#define PCI_CLASS_WIRELESS_RF_CONTROLLER 0x0d10 |
#define PCI_CLASS_WIRELESS_WHCI 0x0d1010 |
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#define PCI_BASE_CLASS_INTELLIGENT 0x0e |
#define PCI_CLASS_INTELLIGENT_I2O 0x0e00 |
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#define PCI_BASE_CLASS_SATELLITE 0x0f |
#define PCI_CLASS_SATELLITE_TV 0x0f00 |
#define PCI_CLASS_SATELLITE_AUDIO 0x0f01 |
#define PCI_CLASS_SATELLITE_VOICE 0x0f03 |
#define PCI_CLASS_SATELLITE_DATA 0x0f04 |
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#define PCI_BASE_CLASS_CRYPT 0x10 |
#define PCI_CLASS_CRYPT_NETWORK 0x1000 |
#define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1001 |
#define PCI_CLASS_CRYPT_OTHER 0x1080 |
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#define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11 |
#define PCI_CLASS_SP_DPIO 0x1100 |
#define PCI_CLASS_SP_OTHER 0x1180 |
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#define PCI_CLASS_OTHERS 0xff |
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#define PCI_MAP_IS_IO(b) ((b) & PCI_MAP_IO) |
#define PCI_MAP_IS_MEM(b) (!PCI_MAP_IS_IO(b)) |
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#define PCI_MAP_IS64BITMEM(b) \ |
(((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT) |
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#define PCIGETMEMORY(b) ((b) & PCI_MAP_MEMORY_ADDRESS_MASK) |
#define PCIGETMEMORY64HIGH(b) (*((CARD32*)&b + 1)) |
#define PCIGETMEMORY64(b) \ |
(PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32)) |
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#define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc |
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#define PCIGETIO(b) ((b) & PCI_MAP_IO_ADDRESS_MASK) |
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#define PCI_MAP_ROM_DECODE_ENABLE 0x00000001 |
#define PCI_MAP_ROM_ADDRESS_MASK 0xfffff800 |
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#define PCIGETROM(b) ((b) & PCI_MAP_ROM_ADDRESS_MASK) |
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#ifndef PCI_DOM_MASK |
# define PCI_DOM_MASK 0x0ffu |
#endif |
#define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu) |
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#define PCI_MAKE_TAG(b,d,f) ((((b) & (PCI_DOMBUS_MASK)) << 16) | \ |
(((d) & 0x00001fu) << 11) | \ |
(((f) & 0x000007u) << 8)) |
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#define PCI_BUS_FROM_TAG(tag) (((tag) >> 16) & (PCI_DOMBUS_MASK)) |
#define PCI_DEV_FROM_TAG(tag) (((tag) & 0x0000f800u) >> 11) |
#define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8) |
#define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00u) >> 8) |
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#include <linux/pci_ids.h> |
#include <syscall.h> |
/* |
* The PCI interface treats multi-function devices as independent |
* devices. The slot/function address of each device is encoded |
219,20 → 46,10 |
* In the interest of not exposing interfaces to user-space unnecessarily, |
* the following kernel-only defines are being added here. |
*/ |
#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
#define PCI_FUNC(devfn) ((devfn) & 0x07) |
#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) |
/* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ |
#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) |
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typedef unsigned int PCITAG; |
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extern inline PCITAG |
pciTag(int busnum, int devnum, int funcnum) |
{ |
return(PCI_MAKE_TAG(busnum,devnum,funcnum)); |
} |
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/* pci_slot represents a physical slot */ |
struct pci_slot { |
struct pci_bus *bus; /* The bus this slot is on */ |
239,6 → 56,7 |
struct list_head list; /* node in list of slots on this bus */ |
struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ |
unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ |
struct kobject kobj; |
}; |
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/* File state for mmap()s on /proc/bus/pci/X/Y */ |
323,6 → 141,49 |
/* PCI card is dead */ |
pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, |
}; |
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typedef unsigned int __bitwise pcie_reset_state_t; |
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enum pcie_reset_state { |
/* Reset is NOT asserted (Use to deassert reset) */ |
pcie_deassert_reset = (__force pcie_reset_state_t) 1, |
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/* Use #PERST to reset PCIe device */ |
pcie_warm_reset = (__force pcie_reset_state_t) 2, |
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/* Use PCIe Hot Reset to reset device */ |
pcie_hot_reset = (__force pcie_reset_state_t) 3 |
}; |
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typedef unsigned short __bitwise pci_dev_flags_t; |
enum pci_dev_flags { |
/* INTX_DISABLE in PCI_COMMAND register disables MSI |
* generation too. |
*/ |
PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), |
/* Device configuration is irrevocably lost if disabled into D3 */ |
PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), |
/* Provide indication device is assigned by a Virtual Machine Manager */ |
PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), |
/* Flag for quirk use to store if quirk-specific ACS is enabled */ |
PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), |
/* Flag to indicate the device uses dma_alias_devfn */ |
PCI_DEV_FLAGS_DMA_ALIAS_DEVFN = (__force pci_dev_flags_t) (1 << 4), |
/* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ |
PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), |
/* Do not use bus resets for device */ |
PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), |
/* Do not use PM reset even if device advertises NoSoftRst- */ |
PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), |
/* Get VPD from function 0 VPD */ |
PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), |
}; |
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enum pci_irq_reroute_variant { |
INTEL_IRQ_REROUTE_VARIANT = 1, |
MAX_IRQ_REROUTE_VARIANTS = 3 |
}; |
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typedef unsigned short __bitwise pci_bus_flags_t; |
enum pci_bus_flags { |
PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, |
406,13 → 267,15 |
unsigned int class; /* 3 bytes: (base,sub,prog-if) */ |
u8 revision; /* PCI revision, low byte of class word */ |
u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
u8 pcie_cap; /* PCI-E capability offset */ |
u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */ |
u8 pcie_cap; /* PCIe capability offset */ |
u8 msi_cap; /* MSI capability offset */ |
u8 msix_cap; /* MSI-X capability offset */ |
u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ |
u8 rom_base_reg; /* which config register controls the ROM */ |
u8 pin; /* which interrupt pin this device uses */ |
u16 pcie_flags_reg; /* cached PCI-E Capabilities Register */ |
u16 pcie_flags_reg; /* cached PCIe Capabilities Register */ |
u8 dma_alias_devfn;/* devfn of DMA alias, if any */ |
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// struct pci_driver *driver; /* which driver has allocated this device */ |
u64 dma_mask; /* Mask of the bits of bus address this |
device implements. Normally this is |
0xffffffff. You only need to change |
419,7 → 282,6 |
this if your device has broken DMA |
or supports 64-bit transfers. */ |
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// struct device_dma_parameters dma_parms; |
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pci_power_t current_state; /* Current operating state. In ACPI-speak, |
this is D0-D3, D0 being fully functional, |
476,6 → 338,7 |
unsigned int msi_enabled:1; |
unsigned int msix_enabled:1; |
unsigned int ari_enabled:1; /* ARI forwarding */ |
unsigned int ats_enabled:1; /* Address Translation Service */ |
unsigned int is_managed:1; |
unsigned int needs_freset:1; /* Dev requires fundamental reset */ |
unsigned int state_saved:1; |
487,24 → 350,97 |
unsigned int __aer_firmware_first:1; |
unsigned int broken_intx_masking:1; |
unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ |
// pci_dev_flags_t dev_flags; |
unsigned int irq_managed:1; |
unsigned int has_secondary_link:1; |
pci_dev_flags_t dev_flags; |
atomic_t enable_cnt; /* pci_enable_device has been called */ |
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u32 saved_config_space[16]; /* config space saved at suspend time */ |
struct hlist_head saved_cap_space; |
struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ |
int rom_attr_enabled; /* has display of the rom attribute been enabled? */ |
#ifdef CONFIG_PCI_MSI |
const struct attribute_group **msi_irq_groups; |
#endif |
#ifdef CONFIG_PCI_ATS |
union { |
struct pci_sriov *sriov; /* SR-IOV capability related */ |
struct pci_dev *physfn; /* the PF this VF is associated with */ |
}; |
u16 ats_cap; /* ATS Capability offset */ |
u8 ats_stu; /* ATS Smallest Translation Unit */ |
atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */ |
#endif |
phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */ |
size_t romlen; /* Length of ROM if it's not from the BAR */ |
char *driver_override; /* Driver name to force a match */ |
}; |
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static inline struct pci_dev *pci_physfn(struct pci_dev *dev) |
{ |
#ifdef CONFIG_PCI_IOV |
if (dev->is_virtfn) |
dev = dev->physfn; |
#endif |
return dev; |
} |
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struct pci_dev *pci_alloc_dev(struct pci_bus *bus); |
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#define to_pci_dev(n) container_of(n, struct pci_dev, dev) |
#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) |
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static inline int pci_channel_offline(struct pci_dev *pdev) |
{ |
return (pdev->error_state != pci_channel_io_normal); |
} |
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struct pci_host_bridge { |
struct device dev; |
struct pci_bus *bus; /* root bus */ |
struct list_head windows; /* resource_entry */ |
void (*release_fn)(struct pci_host_bridge *); |
void *release_data; |
unsigned int ignore_reset_delay:1; /* for entire hierarchy */ |
/* Resource alignment requirements */ |
resource_size_t (*align_resource)(struct pci_dev *dev, |
const struct resource *res, |
resource_size_t start, |
resource_size_t size, |
resource_size_t align); |
}; |
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#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) |
#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) |
#define pci_resource_len(dev,bar) \ |
((pci_resource_start((dev), (bar)) == 0 && \ |
pci_resource_end((dev), (bar)) == \ |
pci_resource_start((dev), (bar))) ? 0 : \ |
\ |
(pci_resource_end((dev), (bar)) - \ |
pci_resource_start((dev), (bar)) + 1)) |
#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) |
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struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); |
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void pci_set_host_bridge_release(struct pci_host_bridge *bridge, |
void (*release_fn)(struct pci_host_bridge *), |
void *release_data); |
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int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); |
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/* |
* The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond |
* to P2P or CardBus bridge windows) go in a table. Additional ones (for |
* buses below host bridges or subtractive decode bridges) go in the list. |
* Use pci_bus_for_each_resource() to iterate through all the resources. |
*/ |
|
/* |
* PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly |
* and there's no way to program the bridge with the details of the window. |
* This does not apply to ACPI _CRS windows, even with the _DEC subtractive- |
* decode bit set, because they are explicit and can be programmed with _SRS. |
*/ |
#define PCI_SUBTRACTIVE_DECODE 0x1 |
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struct pci_bus_resource { |
struct list_head list; |
struct resource *res; |
unsigned int flags; |
}; |
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#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ |
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struct pci_bus { |
513,12 → 449,14 |
struct list_head children; /* list of child buses */ |
struct list_head devices; /* list of devices on this bus */ |
struct pci_dev *self; /* bridge device as seen by parent */ |
struct list_head slots; /* list of slots on this bus */ |
struct list_head slots; /* list of slots on this bus; |
protected by pci_slot_mutex */ |
struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; |
struct list_head resources; /* address space routed to this bus */ |
struct resource busn_res; /* bus numbers routed to this bus */ |
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struct pci_ops *ops; /* configuration access functions */ |
struct msi_controller *msi; /* MSI controller */ |
void *sysdata; /* hook for sys-specific extension */ |
struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ |
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526,6 → 464,9 |
unsigned char primary; /* number of primary bridge */ |
unsigned char max_bus_speed; /* enum pci_bus_speed */ |
unsigned char cur_bus_speed; /* enum pci_bus_speed */ |
#ifdef CONFIG_PCI_DOMAINS_GENERIC |
int domain_nr; |
#endif |
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char name[48]; |
|
538,25 → 479,8 |
unsigned int is_added:1; |
}; |
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#define pci_bus_b(n) list_entry(n, struct pci_bus, node) |
#define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
#define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list) |
#define to_pci_dev(n) container_of(n, struct pci_dev, dev) |
#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) |
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/* Low-level architecture-dependent routines */ |
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struct pci_sysdata { |
int domain; /* PCI domain */ |
int node; /* NUMA node */ |
}; |
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#define pci_bus_b(n) list_entry(n, struct pci_bus, node) |
#define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
|
/* |
* Returns true if the PCI bus is root (behind host-PCI bridge), |
* false otherwise |
570,10 → 494,40 |
return !(pbus->parent); |
} |
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struct pci_bus * |
pci_find_next_bus(const struct pci_bus *from); |
/** |
* pci_is_bridge - check if the PCI device is a bridge |
* @dev: PCI device |
* |
* Return true if the PCI device is bridge whether it has subordinate |
* or not. |
*/ |
static inline bool pci_is_bridge(struct pci_dev *dev) |
{ |
return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || |
dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; |
} |
|
static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) |
{ |
dev = pci_physfn(dev); |
if (pci_is_root_bus(dev->bus)) |
return NULL; |
|
return dev->bus->self; |
} |
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struct device *pci_get_host_bridge_device(struct pci_dev *dev); |
void pci_put_host_bridge_device(struct device *dev); |
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#ifdef CONFIG_PCI_MSI |
static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) |
{ |
return pci_dev->msi_enabled || pci_dev->msix_enabled; |
} |
#else |
static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } |
#endif |
|
/* |
* Error values that may be returned by PCI functions. |
*/ |
614,6 → 568,7 |
/* Low-level architecture-dependent routines */ |
|
struct pci_ops { |
void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); |
int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); |
int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); |
}; |
627,38 → 582,1193 |
int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, |
int reg, int len, u32 val); |
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#ifdef CONFIG_PCI_BUS_ADDR_T_64BIT |
typedef u64 pci_bus_addr_t; |
#else |
typedef u32 pci_bus_addr_t; |
#endif |
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struct pci_bus_region { |
dma_addr_t start; |
dma_addr_t end; |
pci_bus_addr_t start; |
pci_bus_addr_t end; |
}; |
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enum pci_bar_type { |
pci_bar_unknown, /* Standard PCI BAR probe */ |
pci_bar_io, /* An io port BAR */ |
pci_bar_mem32, /* A 32-bit memory BAR */ |
pci_bar_mem64, /* A 64-bit memory BAR */ |
struct pci_dynids { |
spinlock_t lock; /* protects list, index */ |
struct list_head list; /* for IDs added at runtime */ |
}; |
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/* |
* PCI Error Recovery System (PCI-ERS). If a PCI device driver provides |
* a set of callbacks in struct pci_error_handlers, that device driver |
* will be notified of PCI bus errors, and will be driven to recovery |
* when an error occurs. |
*/ |
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typedef unsigned int __bitwise pci_ers_result_t; |
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enum pci_ers_result { |
/* no result/none/not supported in device driver */ |
PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, |
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/* Device driver can recover without slot reset */ |
PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, |
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/* Device driver wants slot to be reset. */ |
PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, |
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/* Device has completely failed, is unrecoverable */ |
PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, |
|
/* Device driver is fully recovered and operational */ |
PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, |
|
/* No AER capabilities registered for the driver */ |
PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, |
}; |
|
/* PCI bus error event callbacks */ |
struct pci_error_handlers { |
/* PCI bus error detected on this device */ |
pci_ers_result_t (*error_detected)(struct pci_dev *dev, |
enum pci_channel_state error); |
|
/* MMIO has been re-enabled, but not DMA */ |
pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); |
|
/* PCI Express link has been reset */ |
pci_ers_result_t (*link_reset)(struct pci_dev *dev); |
|
/* PCI slot has been reset */ |
pci_ers_result_t (*slot_reset)(struct pci_dev *dev); |
|
/* PCI function reset prepare or completed */ |
void (*reset_notify)(struct pci_dev *dev, bool prepare); |
|
/* Device driver may resume normal operations */ |
void (*resume)(struct pci_dev *dev); |
}; |
|
|
struct module; |
struct pci_driver { |
struct list_head node; |
const char *name; |
const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ |
int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ |
void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ |
int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ |
int (*suspend_late) (struct pci_dev *dev, pm_message_t state); |
int (*resume_early) (struct pci_dev *dev); |
int (*resume) (struct pci_dev *dev); /* Device woken up */ |
void (*shutdown) (struct pci_dev *dev); |
int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */ |
const struct pci_error_handlers *err_handler; |
struct device_driver driver; |
struct pci_dynids dynids; |
}; |
|
#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) |
|
/** |
* DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table |
* @_table: device table name |
* |
* This macro is deprecated and should not be used in new code. |
*/ |
#define DEFINE_PCI_DEVICE_TABLE(_table) \ |
const struct pci_device_id _table[] |
|
/** |
* PCI_DEVICE - macro used to describe a specific pci device |
* @vend: the 16 bit PCI Vendor ID |
* @dev: the 16 bit PCI Device ID |
* |
* This macro is used to create a struct pci_device_id that matches a |
* specific device. The subvendor and subdevice fields will be set to |
* PCI_ANY_ID. |
*/ |
#define PCI_DEVICE(vend,dev) \ |
.vendor = (vend), .device = (dev), \ |
.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID |
|
/** |
* PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem |
* @vend: the 16 bit PCI Vendor ID |
* @dev: the 16 bit PCI Device ID |
* @subvend: the 16 bit PCI Subvendor ID |
* @subdev: the 16 bit PCI Subdevice ID |
* |
* This macro is used to create a struct pci_device_id that matches a |
* specific device with subsystem information. |
*/ |
#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ |
.vendor = (vend), .device = (dev), \ |
.subvendor = (subvend), .subdevice = (subdev) |
|
/** |
* PCI_DEVICE_CLASS - macro used to describe a specific pci device class |
* @dev_class: the class, subclass, prog-if triple for this device |
* @dev_class_mask: the class mask for this device |
* |
* This macro is used to create a struct pci_device_id that matches a |
* specific PCI class. The vendor, device, subvendor, and subdevice |
* fields will be set to PCI_ANY_ID. |
*/ |
#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ |
.class = (dev_class), .class_mask = (dev_class_mask), \ |
.vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ |
.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID |
|
/** |
* PCI_VDEVICE - macro used to describe a specific pci device in short form |
* @vend: the vendor name |
* @dev: the 16 bit PCI Device ID |
* |
* This macro is used to create a struct pci_device_id that matches a |
* specific PCI device. The subvendor, and subdevice fields will be set |
* to PCI_ANY_ID. The macro allows the next field to follow as the device |
* private data. |
*/ |
|
#define PCI_VDEVICE(vend, dev) \ |
.vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ |
.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 |
|
/* these external functions are only available when PCI support is enabled */ |
#ifdef CONFIG_PCI |
|
void pcie_bus_configure_settings(struct pci_bus *bus); |
|
enum pcie_bus_config_types { |
PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */ |
PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */ |
PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */ |
PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */ |
PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */ |
}; |
|
extern enum pcie_bus_config_types pcie_bus_config; |
|
extern struct bus_type pci_bus_type; |
|
/* Do NOT directly access these two variables, unless you are arch-specific PCI |
* code, or PCI core code. */ |
extern struct list_head pci_root_buses; /* list of all known PCI buses */ |
/* Some device drivers need know if PCI is initiated */ |
int no_pci_devices(void); |
|
void pcibios_resource_survey_bus(struct pci_bus *bus); |
void pcibios_add_bus(struct pci_bus *bus); |
void pcibios_remove_bus(struct pci_bus *bus); |
void pcibios_fixup_bus(struct pci_bus *); |
int __must_check pcibios_enable_device(struct pci_dev *, int mask); |
/* Architecture-specific versions may override this (weak) */ |
char *pcibios_setup(char *str); |
|
/* Used only when drivers/pci/setup.c is used */ |
resource_size_t pcibios_align_resource(void *, const struct resource *, |
resource_size_t, |
resource_size_t); |
void pcibios_update_irq(struct pci_dev *, int irq); |
|
/* Weak but can be overriden by arch */ |
void pci_fixup_cardbus(struct pci_bus *); |
|
/* Generic PCI functions used internally */ |
|
void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, |
struct resource *res); |
void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, |
struct pci_bus_region *region); |
void pcibios_scan_specific_bus(int busn); |
struct pci_bus *pci_find_bus(int domain, int busnr); |
void pci_bus_add_devices(const struct pci_bus *bus); |
struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); |
struct pci_bus *pci_create_root_bus(struct device *parent, int bus, |
struct pci_ops *ops, void *sysdata, |
struct list_head *resources); |
int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); |
int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); |
void pci_bus_release_busn_res(struct pci_bus *b); |
struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus, |
struct pci_ops *ops, void *sysdata, |
struct list_head *resources, |
struct msi_controller *msi); |
struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, |
struct pci_ops *ops, void *sysdata, |
struct list_head *resources); |
struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, |
int busnr); |
void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); |
struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, |
const char *name, |
struct hotplug_slot *hotplug); |
void pci_destroy_slot(struct pci_slot *slot); |
#ifdef CONFIG_SYSFS |
void pci_dev_assign_slot(struct pci_dev *dev); |
#else |
static inline void pci_dev_assign_slot(struct pci_dev *dev) { } |
#endif |
int pci_scan_slot(struct pci_bus *bus, int devfn); |
struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); |
void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); |
unsigned int pci_scan_child_bus(struct pci_bus *bus); |
void pci_bus_add_device(struct pci_dev *dev); |
void pci_read_bridge_bases(struct pci_bus *child); |
struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
struct resource *res); |
struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev); |
u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); |
int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); |
u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); |
struct pci_dev *pci_dev_get(struct pci_dev *dev); |
void pci_dev_put(struct pci_dev *dev); |
void pci_remove_bus(struct pci_bus *b); |
void pci_stop_and_remove_bus_device(struct pci_dev *dev); |
void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); |
void pci_stop_root_bus(struct pci_bus *bus); |
void pci_remove_root_bus(struct pci_bus *bus); |
void pci_setup_cardbus(struct pci_bus *bus); |
void pci_sort_breadthfirst(void); |
#define dev_is_pci(d) ((d)->bus == &pci_bus_type) |
#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) |
#define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0)) |
|
/* Generic PCI functions exported to card drivers */ |
|
enum pci_lost_interrupt_reason { |
PCI_LOST_IRQ_NO_INFORMATION = 0, |
PCI_LOST_IRQ_DISABLE_MSI, |
PCI_LOST_IRQ_DISABLE_MSIX, |
PCI_LOST_IRQ_DISABLE_ACPI, |
}; |
enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); |
int pci_find_capability(struct pci_dev *dev, int cap); |
int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); |
int pci_find_ext_capability(struct pci_dev *dev, int cap); |
int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); |
int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); |
int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); |
struct pci_bus *pci_find_next_bus(const struct pci_bus *from); |
|
struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, |
struct pci_dev *from); |
struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, |
unsigned int ss_vendor, unsigned int ss_device, |
struct pci_dev *from); |
struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); |
struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, |
unsigned int devfn); |
static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, |
unsigned int devfn) |
{ |
return pci_get_domain_bus_and_slot(0, bus, devfn); |
} |
struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); |
int pci_dev_present(const struct pci_device_id *ids); |
|
int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, |
int where, u8 *val); |
int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, |
int where, u16 *val); |
int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, |
int where, u32 *val); |
int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, |
int where, u8 val); |
int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, |
int where, u16 val); |
int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, |
int where, u32 val); |
|
int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, |
int where, int size, u32 *val); |
int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, |
int where, int size, u32 val); |
int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, |
int where, int size, u32 *val); |
int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, |
int where, int size, u32 val); |
|
struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); |
|
static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val) |
{ |
*val = PciRead8(dev->busnr, dev->devfn, where); |
return 1; |
} |
static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val) |
{ |
*val = PciRead16(dev->busnr, dev->devfn, where); |
return 1; |
} |
static inline int pci_read_config_dword(const struct pci_dev *dev, int where, |
u32 *val) |
{ |
*val = PciRead32(dev->busnr, dev->devfn, where); |
return 1; |
} |
static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val) |
{ |
PciWrite8(dev->busnr, dev->devfn, where, val); |
return 1; |
} |
static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val) |
{ |
PciWrite16(dev->busnr, dev->devfn, where, val); |
return 1; |
} |
static inline int pci_write_config_dword(const struct pci_dev *dev, int where, |
u32 val) |
{ |
PciWrite32(dev->busnr, dev->devfn, where, val); |
return 1; |
} |
|
int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); |
int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); |
int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); |
int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); |
int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, |
u16 clear, u16 set); |
int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, |
u32 clear, u32 set); |
|
static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, |
u16 set) |
{ |
return pcie_capability_clear_and_set_word(dev, pos, 0, set); |
} |
|
static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, |
u32 set) |
{ |
return pcie_capability_clear_and_set_dword(dev, pos, 0, set); |
} |
|
static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, |
u16 clear) |
{ |
return pcie_capability_clear_and_set_word(dev, pos, clear, 0); |
} |
|
static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, |
u32 clear) |
{ |
return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); |
} |
|
/* user-space driven config access */ |
int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); |
int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); |
int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); |
int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); |
int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); |
int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); |
|
int __must_check pci_enable_device(struct pci_dev *dev); |
int __must_check pci_enable_device_io(struct pci_dev *dev); |
int __must_check pci_enable_device_mem(struct pci_dev *dev); |
int __must_check pci_reenable_device(struct pci_dev *); |
int __must_check pcim_enable_device(struct pci_dev *pdev); |
void pcim_pin_device(struct pci_dev *pdev); |
|
static inline int pci_is_enabled(struct pci_dev *pdev) |
{ |
return (atomic_read(&pdev->enable_cnt) > 0); |
} |
|
static inline int pci_is_managed(struct pci_dev *pdev) |
{ |
return pdev->is_managed; |
} |
|
static inline void pci_set_managed_irq(struct pci_dev *pdev, unsigned int irq) |
{ |
pdev->irq = irq; |
pdev->irq_managed = 1; |
} |
|
static inline void pci_reset_managed_irq(struct pci_dev *pdev) |
{ |
pdev->irq = 0; |
pdev->irq_managed = 0; |
} |
|
static inline bool pci_has_managed_irq(struct pci_dev *pdev) |
{ |
return pdev->irq_managed && pdev->irq > 0; |
} |
|
void pci_disable_device(struct pci_dev *dev); |
|
extern unsigned int pcibios_max_latency; |
void pci_set_master(struct pci_dev *dev); |
void pci_clear_master(struct pci_dev *dev); |
|
int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); |
int pci_set_cacheline_size(struct pci_dev *dev); |
#define HAVE_PCI_SET_MWI |
int __must_check pci_set_mwi(struct pci_dev *dev); |
int pci_try_set_mwi(struct pci_dev *dev); |
void pci_clear_mwi(struct pci_dev *dev); |
void pci_intx(struct pci_dev *dev, int enable); |
bool pci_intx_mask_supported(struct pci_dev *dev); |
bool pci_check_and_mask_intx(struct pci_dev *dev); |
bool pci_check_and_unmask_intx(struct pci_dev *dev); |
int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size); |
int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask); |
int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); |
int pci_wait_for_pending_transaction(struct pci_dev *dev); |
int pcix_get_max_mmrbc(struct pci_dev *dev); |
int pcix_get_mmrbc(struct pci_dev *dev); |
int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); |
int pcie_get_readrq(struct pci_dev *dev); |
int pcie_set_readrq(struct pci_dev *dev, int rq); |
int pcie_get_mps(struct pci_dev *dev); |
int pcie_set_mps(struct pci_dev *dev, int mps); |
int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, |
enum pcie_link_width *width); |
int __pci_reset_function(struct pci_dev *dev); |
int __pci_reset_function_locked(struct pci_dev *dev); |
int pci_reset_function(struct pci_dev *dev); |
int pci_try_reset_function(struct pci_dev *dev); |
int pci_probe_reset_slot(struct pci_slot *slot); |
int pci_reset_slot(struct pci_slot *slot); |
int pci_try_reset_slot(struct pci_slot *slot); |
int pci_probe_reset_bus(struct pci_bus *bus); |
int pci_reset_bus(struct pci_bus *bus); |
int pci_try_reset_bus(struct pci_bus *bus); |
void pci_reset_secondary_bus(struct pci_dev *dev); |
void pcibios_reset_secondary_bus(struct pci_dev *dev); |
void pci_reset_bridge_secondary_bus(struct pci_dev *dev); |
void pci_update_resource(struct pci_dev *dev, int resno); |
int __must_check pci_assign_resource(struct pci_dev *dev, int i); |
int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); |
int pci_select_bars(struct pci_dev *dev, unsigned long flags); |
bool pci_device_is_present(struct pci_dev *pdev); |
void pci_ignore_hotplug(struct pci_dev *dev); |
|
/* ROM control related routines */ |
int pci_enable_rom(struct pci_dev *pdev); |
void pci_disable_rom(struct pci_dev *pdev); |
void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); |
void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); |
size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); |
void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); |
|
/* Power management related routines */ |
int pci_save_state(struct pci_dev *dev); |
void pci_restore_state(struct pci_dev *dev); |
struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); |
int pci_load_saved_state(struct pci_dev *dev, |
struct pci_saved_state *state); |
int pci_load_and_free_saved_state(struct pci_dev *dev, |
struct pci_saved_state **state); |
struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); |
struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, |
u16 cap); |
int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); |
int pci_add_ext_cap_save_buffer(struct pci_dev *dev, |
u16 cap, unsigned int size); |
int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); |
int pci_set_power_state(struct pci_dev *dev, pci_power_t state); |
pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); |
bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); |
void pci_pme_active(struct pci_dev *dev, bool enable); |
int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
bool runtime, bool enable); |
int pci_wake_from_d3(struct pci_dev *dev, bool enable); |
int pci_prepare_to_sleep(struct pci_dev *dev); |
int pci_back_from_sleep(struct pci_dev *dev); |
bool pci_dev_run_wake(struct pci_dev *dev); |
bool pci_check_pme_status(struct pci_dev *dev); |
void pci_pme_wakeup_bus(struct pci_bus *bus); |
|
static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
bool enable) |
{ |
return __pci_enable_wake(dev, state, false, enable); |
} |
|
/* PCI Virtual Channel */ |
int pci_save_vc_state(struct pci_dev *dev); |
void pci_restore_vc_state(struct pci_dev *dev); |
void pci_allocate_vc_save_buffers(struct pci_dev *dev); |
|
/* For use by arch with custom probe code */ |
void set_pcie_port_type(struct pci_dev *pdev); |
void set_pcie_hotplug_bridge(struct pci_dev *pdev); |
|
/* Functions for PCI Hotplug drivers to use */ |
int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); |
unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); |
unsigned int pci_rescan_bus(struct pci_bus *bus); |
void pci_lock_rescan_remove(void); |
void pci_unlock_rescan_remove(void); |
|
/* Vital product data routines */ |
ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); |
ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); |
|
/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ |
resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); |
void pci_bus_assign_resources(const struct pci_bus *bus); |
void pci_bus_size_bridges(struct pci_bus *bus); |
int pci_claim_resource(struct pci_dev *, int); |
int pci_claim_bridge_resource(struct pci_dev *bridge, int i); |
void pci_assign_unassigned_resources(void); |
void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); |
void pci_assign_unassigned_bus_resources(struct pci_bus *bus); |
void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); |
void pdev_enable_device(struct pci_dev *); |
int pci_enable_resources(struct pci_dev *, int mask); |
void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), |
int (*)(const struct pci_dev *, u8, u8)); |
#define HAVE_PCI_REQ_REGIONS 2 |
int __must_check pci_request_regions(struct pci_dev *, const char *); |
int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); |
void pci_release_regions(struct pci_dev *); |
int __must_check pci_request_region(struct pci_dev *, int, const char *); |
int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); |
void pci_release_region(struct pci_dev *, int); |
int pci_request_selected_regions(struct pci_dev *, int, const char *); |
int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); |
void pci_release_selected_regions(struct pci_dev *, int); |
|
/* drivers/pci/bus.c */ |
struct pci_bus *pci_bus_get(struct pci_bus *bus); |
void pci_bus_put(struct pci_bus *bus); |
void pci_add_resource(struct list_head *resources, struct resource *res); |
void pci_add_resource_offset(struct list_head *resources, struct resource *res, |
resource_size_t offset); |
void pci_free_resource_list(struct list_head *resources); |
void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags); |
struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); |
void pci_bus_remove_resources(struct pci_bus *bus); |
|
#define pci_bus_for_each_resource(bus, res, i) \ |
for (i = 0; \ |
(res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ |
i++) |
|
int __must_check pci_bus_alloc_resource(struct pci_bus *bus, |
struct resource *res, resource_size_t size, |
resource_size_t align, resource_size_t min, |
unsigned long type_mask, |
resource_size_t (*alignf)(void *, |
const struct resource *, |
resource_size_t, |
resource_size_t), |
void *alignf_data); |
|
|
int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); |
|
static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) |
{ |
struct pci_bus_region region; |
|
pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); |
return region.start; |
} |
|
/* Proper probing supporting hot-pluggable devices */ |
int __must_check __pci_register_driver(struct pci_driver *, struct module *, |
const char *mod_name); |
|
/* |
* pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded |
*/ |
#define pci_register_driver(driver) \ |
__pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) |
|
void pci_unregister_driver(struct pci_driver *dev); |
|
/** |
* module_pci_driver() - Helper macro for registering a PCI driver |
* @__pci_driver: pci_driver struct |
* |
* Helper macro for PCI drivers which do not do anything special in module |
* init/exit. This eliminates a lot of boilerplate. Each module may only |
* use this macro once, and calling it replaces module_init() and module_exit() |
*/ |
#define module_pci_driver(__pci_driver) \ |
module_driver(__pci_driver, pci_register_driver, \ |
pci_unregister_driver) |
|
/** |
* builtin_pci_driver() - Helper macro for registering a PCI driver |
* @__pci_driver: pci_driver struct |
* |
* Helper macro for PCI drivers which do not do anything special in their |
* init code. This eliminates a lot of boilerplate. Each driver may only |
* use this macro once, and calling it replaces device_initcall(...) |
*/ |
#define builtin_pci_driver(__pci_driver) \ |
builtin_driver(__pci_driver, pci_register_driver) |
|
struct pci_driver *pci_dev_driver(const struct pci_dev *dev); |
int pci_add_dynid(struct pci_driver *drv, |
unsigned int vendor, unsigned int device, |
unsigned int subvendor, unsigned int subdevice, |
unsigned int class, unsigned int class_mask, |
unsigned long driver_data); |
const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, |
struct pci_dev *dev); |
int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, |
int pass); |
|
void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), |
void *userdata); |
int pci_cfg_space_size(struct pci_dev *dev); |
unsigned char pci_bus_max_busnr(struct pci_bus *bus); |
void pci_setup_bridge(struct pci_bus *bus); |
resource_size_t pcibios_window_alignment(struct pci_bus *bus, |
unsigned long type); |
resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); |
|
#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) |
#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) |
|
int pci_set_vga_state(struct pci_dev *pdev, bool decode, |
unsigned int command_bits, u32 flags); |
/* kmem_cache style wrapper around pci_alloc_consistent() */ |
|
#include <linux/pci-dma.h> |
#include <linux/dmapool.h> |
|
#define pci_pool dma_pool |
#define pci_pool_create(name, pdev, size, align, allocation) \ |
dma_pool_create(name, &pdev->dev, size, align, allocation) |
#define pci_pool_destroy(pool) dma_pool_destroy(pool) |
#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) |
#define pci_pool_zalloc(pool, flags, handle) \ |
dma_pool_zalloc(pool, flags, handle) |
#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) |
|
struct msix_entry { |
u32 vector; /* kernel uses to write allocated vector */ |
u16 entry; /* driver uses to specify entry, OS writes */ |
}; |
|
void pci_msi_setup_pci_dev(struct pci_dev *dev); |
|
#ifdef CONFIG_PCI_MSI |
int pci_msi_vec_count(struct pci_dev *dev); |
void pci_msi_shutdown(struct pci_dev *dev); |
void pci_disable_msi(struct pci_dev *dev); |
int pci_msix_vec_count(struct pci_dev *dev); |
int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec); |
void pci_msix_shutdown(struct pci_dev *dev); |
void pci_disable_msix(struct pci_dev *dev); |
void pci_restore_msi_state(struct pci_dev *dev); |
int pci_msi_enabled(void); |
int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec); |
static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec) |
{ |
int rc = pci_enable_msi_range(dev, nvec, nvec); |
if (rc < 0) |
return rc; |
return 0; |
} |
int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, |
int minvec, int maxvec); |
static inline int pci_enable_msix_exact(struct pci_dev *dev, |
struct msix_entry *entries, int nvec) |
{ |
int rc = pci_enable_msix_range(dev, entries, nvec, nvec); |
if (rc < 0) |
return rc; |
return 0; |
} |
#else |
static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } |
static inline void pci_msi_shutdown(struct pci_dev *dev) { } |
static inline void pci_disable_msi(struct pci_dev *dev) { } |
static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } |
static inline int pci_enable_msix(struct pci_dev *dev, |
struct msix_entry *entries, int nvec) |
{ return -ENOSYS; } |
static inline void pci_msix_shutdown(struct pci_dev *dev) { } |
static inline void pci_disable_msix(struct pci_dev *dev) { } |
static inline void pci_restore_msi_state(struct pci_dev *dev) { } |
static inline int pci_msi_enabled(void) { return 0; } |
static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec, |
int maxvec) |
{ return -ENOSYS; } |
static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec) |
{ return -ENOSYS; } |
static inline int pci_enable_msix_range(struct pci_dev *dev, |
struct msix_entry *entries, int minvec, int maxvec) |
{ return -ENOSYS; } |
static inline int pci_enable_msix_exact(struct pci_dev *dev, |
struct msix_entry *entries, int nvec) |
{ return -ENOSYS; } |
#endif |
|
#ifdef CONFIG_PCIEPORTBUS |
extern bool pcie_ports_disabled; |
extern bool pcie_ports_auto; |
#else |
#define pcie_ports_disabled true |
#define pcie_ports_auto false |
#endif |
|
#ifdef CONFIG_PCIEASPM |
bool pcie_aspm_support_enabled(void); |
#else |
static inline bool pcie_aspm_support_enabled(void) { return false; } |
#endif |
|
#ifdef CONFIG_PCIEAER |
void pci_no_aer(void); |
bool pci_aer_available(void); |
#else |
static inline void pci_no_aer(void) { } |
static inline bool pci_aer_available(void) { return false; } |
#endif |
|
#ifdef CONFIG_PCIE_ECRC |
void pcie_set_ecrc_checking(struct pci_dev *dev); |
void pcie_ecrc_get_policy(char *str); |
#else |
static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } |
static inline void pcie_ecrc_get_policy(char *str) { } |
#endif |
|
#define pci_enable_msi(pdev) pci_enable_msi_exact(pdev, 1) |
|
#ifdef CONFIG_HT_IRQ |
/* The functions a driver should call */ |
int ht_create_irq(struct pci_dev *dev, int idx); |
void ht_destroy_irq(unsigned int irq); |
#endif /* CONFIG_HT_IRQ */ |
|
#ifdef CONFIG_PCI_ATS |
/* Address Translation Service */ |
void pci_ats_init(struct pci_dev *dev); |
int pci_enable_ats(struct pci_dev *dev, int ps); |
void pci_disable_ats(struct pci_dev *dev); |
int pci_ats_queue_depth(struct pci_dev *dev); |
#else |
static inline void pci_ats_init(struct pci_dev *d) { } |
static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; } |
static inline void pci_disable_ats(struct pci_dev *d) { } |
static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; } |
#endif |
|
void pci_cfg_access_lock(struct pci_dev *dev); |
bool pci_cfg_access_trylock(struct pci_dev *dev); |
void pci_cfg_access_unlock(struct pci_dev *dev); |
|
/* |
* PCI domain support. Sometimes called PCI segment (eg by ACPI), |
* a PCI domain is defined to be a set of PCI busses which share |
* a PCI domain is defined to be a set of PCI buses which share |
* configuration space. |
*/ |
#ifdef CONFIG_PCI_DOMAINS |
extern int pci_domains_supported; |
int pci_get_new_domain_nr(void); |
#else |
enum { pci_domains_supported = 0 }; |
static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } |
static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } |
static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } |
#endif /* CONFIG_PCI_DOMAINS */ |
|
/* |
* Generic implementation for PCI domain support. If your |
* architecture does not need custom management of PCI |
* domains then this implementation will be used |
*/ |
#ifdef CONFIG_PCI_DOMAINS_GENERIC |
static inline int pci_domain_nr(struct pci_bus *bus) |
{ |
return 0; |
return bus->domain_nr; |
} |
void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent); |
#else |
static inline void pci_bus_assign_domain_nr(struct pci_bus *bus, |
struct device *parent) |
{ |
} |
#endif |
|
static inline int pci_proc_domain(struct pci_bus *bus) |
/* some architectures require additional setup to direct VGA traffic */ |
typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, |
unsigned int command_bits, u32 flags); |
void pci_register_set_vga_state(arch_set_vga_state_t func); |
|
#else /* CONFIG_PCI is not enabled */ |
|
/* |
* If the system does not have PCI, clearly these return errors. Define |
* these as simple inline functions to avoid hair in drivers. |
*/ |
|
#define _PCI_NOP(o, s, t) \ |
static inline int pci_##o##_config_##s(struct pci_dev *dev, \ |
int where, t val) \ |
{ return PCIBIOS_FUNC_NOT_SUPPORTED; } |
|
#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ |
_PCI_NOP(o, word, u16 x) \ |
_PCI_NOP(o, dword, u32 x) |
_PCI_NOP_ALL(read, *) |
_PCI_NOP_ALL(write,) |
|
static inline struct pci_dev *pci_get_device(unsigned int vendor, |
unsigned int device, |
struct pci_dev *from) |
{ return NULL; } |
|
static inline struct pci_dev *pci_get_subsys(unsigned int vendor, |
unsigned int device, |
unsigned int ss_vendor, |
unsigned int ss_device, |
struct pci_dev *from) |
{ return NULL; } |
|
static inline struct pci_dev *pci_get_class(unsigned int class, |
struct pci_dev *from) |
{ return NULL; } |
|
#define pci_dev_present(ids) (0) |
#define no_pci_devices() (1) |
#define pci_dev_put(dev) do { } while (0) |
|
static inline void pci_set_master(struct pci_dev *dev) { } |
static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } |
static inline void pci_disable_device(struct pci_dev *dev) { } |
static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) |
{ return -EIO; } |
static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) |
{ return -EIO; } |
static inline int pci_set_dma_max_seg_size(struct pci_dev *dev, |
unsigned int size) |
{ return -EIO; } |
static inline int pci_set_dma_seg_boundary(struct pci_dev *dev, |
unsigned long mask) |
{ return -EIO; } |
static inline int pci_assign_resource(struct pci_dev *dev, int i) |
{ return -EBUSY; } |
static inline int __pci_register_driver(struct pci_driver *drv, |
struct module *owner) |
{ return 0; } |
static inline int pci_register_driver(struct pci_driver *drv) |
{ return 0; } |
static inline void pci_unregister_driver(struct pci_driver *drv) { } |
static inline int pci_find_capability(struct pci_dev *dev, int cap) |
{ return 0; } |
static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, |
int cap) |
{ return 0; } |
static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) |
{ return 0; } |
|
/* Power management related routines */ |
static inline int pci_save_state(struct pci_dev *dev) { return 0; } |
static inline void pci_restore_state(struct pci_dev *dev) { } |
static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) |
{ return 0; } |
static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) |
{ return 0; } |
static inline pci_power_t pci_choose_state(struct pci_dev *dev, |
pm_message_t state) |
{ return PCI_D0; } |
static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
int enable) |
{ return 0; } |
|
static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) |
{ return -EIO; } |
static inline void pci_release_regions(struct pci_dev *dev) { } |
|
static inline void pci_block_cfg_access(struct pci_dev *dev) { } |
static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) |
{ return 0; } |
static inline void pci_unblock_cfg_access(struct pci_dev *dev) { } |
|
static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) |
{ return NULL; } |
static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, |
unsigned int devfn) |
{ return NULL; } |
static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, |
unsigned int devfn) |
{ return NULL; } |
|
static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } |
static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } |
static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } |
|
#define dev_is_pci(d) (false) |
#define dev_is_pf(d) (false) |
#define dev_num_vf(d) (0) |
#endif /* CONFIG_PCI */ |
|
/* Include architecture-dependent settings and functions */ |
|
#include <asm/pci.h> |
|
/* these helpers provide future and backwards compatibility |
* for accessing popular PCI BAR info */ |
#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) |
#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) |
#define pci_resource_len(dev,bar) \ |
((pci_resource_start((dev), (bar)) == 0 && \ |
pci_resource_end((dev), (bar)) == \ |
pci_resource_start((dev), (bar))) ? 0 : \ |
\ |
(pci_resource_end((dev), (bar)) - \ |
pci_resource_start((dev), (bar)) + 1)) |
|
/* Similar to the helpers above, these manipulate per-pci_dev |
* driver-specific data. They are really just a wrapper around |
* the generic device structure functions of these calls. |
*/ |
static inline void *pci_get_drvdata(struct pci_dev *pdev) |
{ |
return 0; |
return dev_get_drvdata(&pdev->dev); |
} |
#endif /* CONFIG_PCI_DOMAINS */ |
|
static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) |
{ |
dev_set_drvdata(&pdev->dev, data); |
} |
|
/* If you want to know what to call your pci_dev, ask this function. |
* Again, it's a wrapper around the generic device. |
*/ |
static inline const char *pci_name(const struct pci_dev *pdev) |
{ |
return dev_name(&pdev->dev); |
} |
|
|
/* Some archs don't want to expose struct resource to userland as-is |
* in sysfs and /proc |
*/ |
#ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER |
static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, |
const struct resource *rsrc, resource_size_t *start, |
resource_size_t *end) |
{ |
*start = rsrc->start; |
*end = rsrc->end; |
} |
#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ |
|
|
/* |
* The world is not perfect and supplies us with broken PCI devices. |
* For at least a part of these bugs we need a work-around, so both |
* generic (drivers/pci/quirks.c) and per-architecture code can define |
* fixup hooks to be called for particular buggy devices. |
*/ |
|
struct pci_fixup { |
u16 vendor; /* You can use PCI_ANY_ID here of course */ |
u16 device; /* You can use PCI_ANY_ID here of course */ |
u32 class; /* You can use PCI_ANY_ID here too */ |
unsigned int class_shift; /* should be 0, 8, 16 */ |
void (*hook)(struct pci_dev *dev); |
}; |
|
enum pci_fixup_pass { |
pci_fixup_early, /* Before probing BARs */ |
pci_fixup_header, /* After reading configuration header */ |
pci_fixup_final, /* Final phase of device fixups */ |
pci_fixup_enable, /* pci_enable_device() time */ |
pci_fixup_resume, /* pci_device_resume() */ |
pci_fixup_suspend, /* pci_device_suspend() */ |
pci_fixup_resume_early, /* pci_device_resume_early() */ |
pci_fixup_suspend_late, /* pci_device_suspend_late() */ |
}; |
|
/* Anonymous variables would be nice... */ |
#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ |
class_shift, hook) \ |
static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ |
__attribute__((__section__(#section), aligned((sizeof(void *))))) \ |
= { vendor, device, class, class_shift, hook }; |
|
#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ |
class_shift, hook) \ |
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ |
hook, vendor, device, class, class_shift, hook) |
#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ |
class_shift, hook) \ |
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ |
hook, vendor, device, class, class_shift, hook) |
#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ |
class_shift, hook) \ |
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ |
hook, vendor, device, class, class_shift, hook) |
#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ |
class_shift, hook) \ |
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ |
hook, vendor, device, class, class_shift, hook) |
#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ |
class_shift, hook) \ |
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ |
resume##hook, vendor, device, class, \ |
class_shift, hook) |
#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ |
class_shift, hook) \ |
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ |
resume_early##hook, vendor, device, \ |
class, class_shift, hook) |
#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ |
class_shift, hook) \ |
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ |
suspend##hook, vendor, device, class, \ |
class_shift, hook) |
#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ |
class_shift, hook) \ |
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ |
suspend_late##hook, vendor, device, \ |
class, class_shift, hook) |
|
#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ |
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ |
hook, vendor, device, PCI_ANY_ID, 0, hook) |
#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ |
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ |
hook, vendor, device, PCI_ANY_ID, 0, hook) |
#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ |
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ |
hook, vendor, device, PCI_ANY_ID, 0, hook) |
#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ |
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ |
hook, vendor, device, PCI_ANY_ID, 0, hook) |
#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ |
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ |
resume##hook, vendor, device, \ |
PCI_ANY_ID, 0, hook) |
#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ |
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ |
resume_early##hook, vendor, device, \ |
PCI_ANY_ID, 0, hook) |
#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ |
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ |
suspend##hook, vendor, device, \ |
PCI_ANY_ID, 0, hook) |
#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ |
DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ |
suspend_late##hook, vendor, device, \ |
PCI_ANY_ID, 0, hook) |
|
#ifdef CONFIG_PCI_QUIRKS |
void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); |
int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); |
void pci_dev_specific_enable_acs(struct pci_dev *dev); |
#else |
static inline void pci_fixup_device(enum pci_fixup_pass pass, |
struct pci_dev *dev) { } |
static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, |
u16 acs_flags) |
{ |
return -ENOTTY; |
} |
static inline void pci_dev_specific_enable_acs(struct pci_dev *dev) { } |
#endif |
|
void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); |
void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); |
void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); |
int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); |
int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, |
const char *name); |
void pcim_iounmap_regions(struct pci_dev *pdev, int mask); |
|
extern int pci_pci_problems; |
#define PCIPCI_FAIL 1 /* No PCI PCI DMA */ |
#define PCIPCI_TRITON 2 |
#define PCIPCI_NATOMA 4 |
#define PCIPCI_VIAETBF 8 |
#define PCIPCI_VSFX 16 |
#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ |
#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ |
|
extern unsigned long pci_cardbus_io_size; |
extern unsigned long pci_cardbus_mem_size; |
extern u8 pci_dfl_cache_line_size; |
extern u8 pci_cache_line_size; |
|
extern unsigned long pci_hotplug_io_size; |
extern unsigned long pci_hotplug_mem_size; |
|
/* Architecture-specific versions may override these (weak) */ |
void pcibios_disable_device(struct pci_dev *dev); |
void pcibios_set_master(struct pci_dev *dev); |
int pcibios_set_pcie_reset_state(struct pci_dev *dev, |
enum pcie_reset_state state); |
int pcibios_add_device(struct pci_dev *dev); |
void pcibios_release_device(struct pci_dev *dev); |
void pcibios_penalize_isa_irq(int irq, int active); |
int pcibios_alloc_irq(struct pci_dev *dev); |
void pcibios_free_irq(struct pci_dev *dev); |
|
#ifdef CONFIG_HIBERNATE_CALLBACKS |
extern struct dev_pm_ops pcibios_pm_ops; |
#endif |
|
#ifdef CONFIG_PCI_MMCONFIG |
void __init pci_mmcfg_early_init(void); |
void __init pci_mmcfg_late_init(void); |
#else |
static inline void pci_mmcfg_early_init(void) { } |
static inline void pci_mmcfg_late_init(void) { } |
#endif |
|
int pci_ext_cfg_avail(void); |
|
void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); |
void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); |
|
#ifdef CONFIG_PCI_IOV |
int pci_iov_virtfn_bus(struct pci_dev *dev, int id); |
int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); |
|
int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); |
void pci_disable_sriov(struct pci_dev *dev); |
int pci_num_vf(struct pci_dev *dev); |
int pci_vfs_assigned(struct pci_dev *dev); |
int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); |
int pci_sriov_get_totalvfs(struct pci_dev *dev); |
resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); |
#else |
static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) |
{ |
return -ENOSYS; |
} |
static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) |
{ |
return -ENOSYS; |
} |
static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) |
{ return -ENODEV; } |
static inline void pci_disable_sriov(struct pci_dev *dev) { } |
static inline int pci_num_vf(struct pci_dev *dev) { return 0; } |
static inline int pci_vfs_assigned(struct pci_dev *dev) |
{ return 0; } |
static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) |
{ return 0; } |
static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) |
{ return 0; } |
static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) |
{ return 0; } |
#endif |
|
#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) |
void pci_hp_create_module_link(struct pci_slot *pci_slot); |
void pci_hp_remove_module_link(struct pci_slot *pci_slot); |
#endif |
|
/** |
* pci_pcie_cap - get the saved PCIe capability offset |
* @dev: PCI device |
683,65 → 1793,191 |
*/ |
static inline bool pci_is_pcie(struct pci_dev *dev) |
{ |
return !!pci_pcie_cap(dev); |
return pci_pcie_cap(dev); |
} |
|
/** |
* pcie_caps_reg - get the PCIe Capabilities Register |
* @dev: PCI device |
*/ |
static inline u16 pcie_caps_reg(const struct pci_dev *dev) |
{ |
return dev->pcie_flags_reg; |
} |
|
/** |
* pci_pcie_type - get the PCIe device/port type |
* @dev: PCI device |
*/ |
static inline int pci_pcie_type(const struct pci_dev *dev) |
{ |
return (dev->pcie_flags_reg & PCI_EXP_FLAGS_TYPE) >> 4; |
return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; |
} |
|
void pci_request_acs(void); |
bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); |
bool pci_acs_path_enabled(struct pci_dev *start, |
struct pci_dev *end, u16 acs_flags); |
|
static inline int pci_iov_init(struct pci_dev *dev) |
#define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ |
#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) |
|
/* Large Resource Data Type Tag Item Names */ |
#define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ |
#define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ |
#define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ |
|
#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) |
#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) |
#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) |
|
/* Small Resource Data Type Tag Item Names */ |
#define PCI_VPD_STIN_END 0x78 /* End */ |
|
#define PCI_VPD_SRDT_END PCI_VPD_STIN_END |
|
#define PCI_VPD_SRDT_TIN_MASK 0x78 |
#define PCI_VPD_SRDT_LEN_MASK 0x07 |
|
#define PCI_VPD_LRDT_TAG_SIZE 3 |
#define PCI_VPD_SRDT_TAG_SIZE 1 |
|
#define PCI_VPD_INFO_FLD_HDR_SIZE 3 |
|
#define PCI_VPD_RO_KEYWORD_PARTNO "PN" |
#define PCI_VPD_RO_KEYWORD_MFR_ID "MN" |
#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" |
#define PCI_VPD_RO_KEYWORD_CHKSUM "RV" |
|
/** |
* pci_vpd_lrdt_size - Extracts the Large Resource Data Type length |
* @lrdt: Pointer to the beginning of the Large Resource Data Type tag |
* |
* Returns the extracted Large Resource Data Type length. |
*/ |
static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) |
{ |
return -ENODEV; |
return (u16)lrdt[1] + ((u16)lrdt[2] << 8); |
} |
static inline void pci_iov_release(struct pci_dev *dev) |
|
{} |
/** |
* pci_vpd_srdt_size - Extracts the Small Resource Data Type length |
* @lrdt: Pointer to the beginning of the Small Resource Data Type tag |
* |
* Returns the extracted Small Resource Data Type length. |
*/ |
static inline u8 pci_vpd_srdt_size(const u8 *srdt) |
{ |
return (*srdt) & PCI_VPD_SRDT_LEN_MASK; |
} |
|
static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno, |
enum pci_bar_type *type) |
/** |
* pci_vpd_info_field_size - Extracts the information field length |
* @lrdt: Pointer to the beginning of an information field header |
* |
* Returns the extracted information field length. |
*/ |
static inline u8 pci_vpd_info_field_size(const u8 *info_field) |
{ |
return 0; |
return info_field[2]; |
} |
static inline void pci_restore_iov_state(struct pci_dev *dev) |
|
/** |
* pci_vpd_find_tag - Locates the Resource Data Type tag provided |
* @buf: Pointer to buffered vpd data |
* @off: The offset into the buffer at which to begin the search |
* @len: The length of the vpd buffer |
* @rdt: The Resource Data Type to search for |
* |
* Returns the index where the Resource Data Type was found or |
* -ENOENT otherwise. |
*/ |
int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); |
|
/** |
* pci_vpd_find_info_keyword - Locates an information field keyword in the VPD |
* @buf: Pointer to buffered vpd data |
* @off: The offset into the buffer at which to begin the search |
* @len: The length of the buffer area, relative to off, in which to search |
* @kw: The keyword to search for |
* |
* Returns the index where the information field keyword was found or |
* -ENOENT otherwise. |
*/ |
int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, |
unsigned int len, const char *kw); |
|
/* PCI <-> OF binding helpers */ |
#ifdef CONFIG_OF |
struct device_node; |
struct irq_domain; |
void pci_set_of_node(struct pci_dev *dev); |
void pci_release_of_node(struct pci_dev *dev); |
void pci_set_bus_of_node(struct pci_bus *bus); |
void pci_release_bus_of_node(struct pci_bus *bus); |
struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); |
|
/* Arch may override this (weak) */ |
struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); |
|
static inline struct device_node * |
pci_device_to_OF_node(const struct pci_dev *pdev) |
{ |
return pdev ? pdev->dev.of_node : NULL; |
} |
static inline int pci_iov_bus_range(struct pci_bus *bus) |
|
static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) |
{ |
return 0; |
return bus ? bus->dev.of_node : NULL; |
} |
|
static inline int pci_enable_ats(struct pci_dev *dev, int ps) |
#else /* CONFIG_OF */ |
static inline void pci_set_of_node(struct pci_dev *dev) { } |
static inline void pci_release_of_node(struct pci_dev *dev) { } |
static inline void pci_set_bus_of_node(struct pci_bus *bus) { } |
static inline void pci_release_bus_of_node(struct pci_bus *bus) { } |
static inline struct device_node * |
pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; } |
static inline struct irq_domain * |
pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } |
#endif /* CONFIG_OF */ |
|
#ifdef CONFIG_EEH |
static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) |
{ |
return -ENODEV; |
return pdev->dev.archdata.edev; |
} |
static inline void pci_disable_ats(struct pci_dev *dev) |
#endif |
|
int pci_for_each_dma_alias(struct pci_dev *pdev, |
int (*fn)(struct pci_dev *pdev, |
u16 alias, void *data), void *data); |
|
/* helper functions for operation of device flag */ |
static inline void pci_set_dev_assigned(struct pci_dev *pdev) |
{ |
pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; |
} |
static inline int pci_ats_queue_depth(struct pci_dev *dev) |
static inline void pci_clear_dev_assigned(struct pci_dev *pdev) |
{ |
return -ENODEV; |
pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; |
} |
static inline int pci_ats_enabled(struct pci_dev *dev) |
static inline bool pci_is_dev_assigned(struct pci_dev *pdev) |
{ |
return 0; |
return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; |
} |
|
int pci_setup_device(struct pci_dev *dev); |
int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, |
struct resource *res, unsigned int reg); |
int pci_resource_bar(struct pci_dev *dev, int resno, |
enum pci_bar_type *type); |
int pci_bus_add_child(struct pci_bus *bus); |
unsigned int pci_scan_child_bus(struct pci_bus *bus); |
/** |
* pci_ari_enabled - query ARI forwarding status |
* @bus: the PCI bus |
* |
* Returns true if ARI forwarding is enabled. |
*/ |
static inline bool pci_ari_enabled(struct pci_bus *bus) |
{ |
return bus->self && bus->self->ari_enabled; |
} |
|
|
typedef struct |
{ |
struct list_head link; |
753,23 → 1989,4 |
const struct pci_device_id* |
find_pci_device(pci_dev_t* pdev, const struct pci_device_id *idlist); |
|
#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) |
|
#define pci_set_dma_mask(a, b) 0 |
#define pci_set_consistent_dma_mask(a, b) |
|
struct pci_dev *pci_get_bus_and_slot(unsigned int bus, unsigned int devfn); |
struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); |
|
void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size); |
|
#define pci_name(x) "radeon" |
|
static inline dma_addr_t pci_bus_address(struct pci_dev *pdev, int bar) |
{ |
return pdev->resource[bar].start; |
} |
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#endif //__PCI__H__ |
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#endif /* LINUX_PCI_H */ |