| 550,6 → 550,7 |
|---|
| #define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling) |
| #define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling) |
| #define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy) |
| #define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va) |
| |
| typedef struct drm_radeon_init { |
| enum { |
| 872,9 → 873,40 |
|---|
| uint64_t data_ptr; |
| }; |
| |
| #define RADEON_VA_MAP 1 |
| #define RADEON_VA_UNMAP 2 |
| |
| #define RADEON_VA_RESULT_OK 0 |
| #define RADEON_VA_RESULT_ERROR 1 |
| #define RADEON_VA_RESULT_VA_EXIST 2 |
| |
| #define RADEON_VM_PAGE_VALID (1 << 0) |
| #define RADEON_VM_PAGE_READABLE (1 << 1) |
| #define RADEON_VM_PAGE_WRITEABLE (1 << 2) |
| #define RADEON_VM_PAGE_SYSTEM (1 << 3) |
| #define RADEON_VM_PAGE_SNOOPED (1 << 4) |
| |
| struct drm_radeon_gem_va { |
| uint32_t handle; |
| uint32_t operation; |
| uint32_t vm_id; |
| uint32_t flags; |
| uint64_t offset; |
| }; |
| |
| #define RADEON_CHUNK_ID_RELOCS 0x01 |
| #define RADEON_CHUNK_ID_IB 0x02 |
| #define RADEON_CHUNK_ID_FLAGS 0x03 |
| |
| /* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */ |
| #define RADEON_CS_KEEP_TILING_FLAGS 0x01 |
| #define RADEON_CS_USE_VM 0x02 |
| /* The second dword of RADEON_CHUNK_ID_FLAGS is a uint32 that sets the ring type */ |
| #define RADEON_CS_RING_GFX 0 |
| #define RADEON_CS_RING_COMPUTE 1 |
| /* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */ |
| /* 0 = normal, + = higher priority, - = lower priority */ |
| |
| struct drm_radeon_cs_chunk { |
| uint32_t chunk_id; |
| uint32_t length_dw; |
| 881,6 → 913,9 |
|---|
| uint64_t chunk_data; |
| }; |
| |
| /* drm_radeon_cs_reloc.flags */ |
| #define RADEON_RELOC_DONT_SYNC 0x01 |
| |
| struct drm_radeon_cs_reloc { |
| uint32_t handle; |
| uint32_t read_domains; |
| 912,6 → 947,10 |
|---|
| #define RADEON_INFO_NUM_TILE_PIPES 0x0b /* tile pipes for r600+ */ |
| #define RADEON_INFO_FUSION_GART_WORKING 0x0c /* fusion writes to GTT were broken before this */ |
| #define RADEON_INFO_BACKEND_MAP 0x0d /* pipe to backend map, needed by mesa */ |
| /* virtual address start, va < start are reserved by the kernel */ |
| #define RADEON_INFO_VA_START 0x0e |
| /* maximum size of ib using the virtual memory cs */ |
| #define RADEON_INFO_IB_VM_MAX_SIZE 0x0f |
| |
| struct drm_radeon_info { |
| uint32_t request; |