| 5,26 → 5,8 |
|---|
| |
| struct agp_bridge_data; |
| |
| struct intel_gtt { |
| /* Size of memory reserved for graphics by the BIOS */ |
| unsigned int stolen_size; |
| /* Total number of gtt entries. */ |
| unsigned int gtt_total_entries; |
| /* Part of the gtt that is mappable by the cpu, for those chips where |
| * this is not the full gtt. */ |
| unsigned int gtt_mappable_entries; |
| /* Whether i915 needs to use the dmar apis or not. */ |
| unsigned int needs_dmar : 1; |
| /* Whether we idle the gpu before mapping/unmapping */ |
| unsigned int do_idle_maps : 1; |
| /* Share the scratch page dma with ppgtts. */ |
| dma_addr_t scratch_page_dma; |
| struct page *scratch_page; |
| /* for ppgtt PDE access */ |
| u32 __iomem *gtt; |
| /* needed for ioremap in drm/i915 */ |
| phys_addr_t gma_bus_addr; |
| } *intel_gtt_get(void); |
| void intel_gtt_get(size_t *gtt_total, size_t *stolen_size, |
| phys_addr_t *mappable_base, unsigned long *mappable_end); |
| |
| int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, |
| struct agp_bridge_data *bridge); |
| 42,10 → 24,6 |
|---|
| #define AGP_DCACHE_MEMORY 1 |
| #define AGP_PHYS_MEMORY 2 |
| |
| /* New caching attributes for gen6/sandybridge */ |
| #define AGP_USER_CACHED_MEMORY_LLC_MLC (AGP_USER_TYPES + 2) |
| #define AGP_USER_UNCACHED_MEMORY (AGP_USER_TYPES + 4) |
| |
| /* flag for GFDT type */ |
| #define AGP_USER_CACHED_MEMORY_GFDT (1 << 3) |
| |