| 41,22 → 41,22 |
|---|
| * 1.2 formally includes both eDP and DPI definitions. |
| */ |
| |
| #define AUX_NATIVE_WRITE 0x8 |
| #define AUX_NATIVE_READ 0x9 |
| #define AUX_I2C_WRITE 0x0 |
| #define AUX_I2C_READ 0x1 |
| #define AUX_I2C_STATUS 0x2 |
| #define AUX_I2C_MOT 0x4 |
| #define DP_AUX_I2C_WRITE 0x0 |
| #define DP_AUX_I2C_READ 0x1 |
| #define DP_AUX_I2C_STATUS 0x2 |
| #define DP_AUX_I2C_MOT 0x4 |
| #define DP_AUX_NATIVE_WRITE 0x8 |
| #define DP_AUX_NATIVE_READ 0x9 |
| |
| #define AUX_NATIVE_REPLY_ACK (0x0 << 4) |
| #define AUX_NATIVE_REPLY_NACK (0x1 << 4) |
| #define AUX_NATIVE_REPLY_DEFER (0x2 << 4) |
| #define AUX_NATIVE_REPLY_MASK (0x3 << 4) |
| #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) |
| #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) |
| #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) |
| #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) |
| |
| #define AUX_I2C_REPLY_ACK (0x0 << 6) |
| #define AUX_I2C_REPLY_NACK (0x1 << 6) |
| #define AUX_I2C_REPLY_DEFER (0x2 << 6) |
| #define AUX_I2C_REPLY_MASK (0x3 << 6) |
| #define DP_AUX_I2C_REPLY_ACK (0x0 << 2) |
| #define DP_AUX_I2C_REPLY_NACK (0x1 << 2) |
| #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) |
| #define DP_AUX_I2C_REPLY_MASK (0x3 << 2) |
| |
| /* AUX CH addresses */ |
| /* DPCD */ |
| 77,10 → 77,10 |
|---|
| #define DP_DOWNSTREAMPORT_PRESENT 0x005 |
| # define DP_DWN_STRM_PORT_PRESENT (1 << 0) |
| # define DP_DWN_STRM_PORT_TYPE_MASK 0x06 |
| /* 00b = DisplayPort */ |
| /* 01b = Analog */ |
| /* 10b = TMDS or HDMI */ |
| /* 11b = Other */ |
| # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) |
| # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) |
| # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) |
| # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) |
| # define DP_FORMAT_CONVERSION (1 << 3) |
| # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ |
| |
| 266,9 → 266,10 |
|---|
| |
| #define DP_TEST_REQUEST 0x218 |
| # define DP_TEST_LINK_TRAINING (1 << 0) |
| # define DP_TEST_LINK_PATTERN (1 << 1) |
| # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1) |
| # define DP_TEST_LINK_EDID_READ (1 << 2) |
| # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ |
| # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */ |
| |
| #define DP_TEST_LINK_RATE 0x219 |
| # define DP_LINK_RATE_162 (0x6) |
| 333,20 → 334,20 |
|---|
| |
| |
| #define DP_LINK_STATUS_SIZE 6 |
| bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE], |
| bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
| int lane_count); |
| bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE], |
| bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
| int lane_count); |
| u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE], |
| u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], |
| int lane); |
| u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE], |
| u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], |
| int lane); |
| |
| #define DP_RECEIVER_CAP_SIZE 0xf |
| #define EDP_PSR_RECEIVER_CAP_SIZE 2 |
| |
| void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]); |
| void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]); |
| void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); |
| void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); |
| |
| u8 drm_dp_link_rate_to_bw_code(int link_rate); |
| int drm_dp_bw_code_to_link_rate(u8 link_bw); |
| 379,15 → 380,22 |
|---|
| #define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2) |
| |
| static inline int |
| drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
| drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
| { |
| return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); |
| } |
| |
| static inline u8 |
| drm_dp_max_lane_count(u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
| drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
| { |
| return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; |
| } |
| |
| static inline bool |
| drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
| { |
| return dpcd[DP_DPCD_REV] >= 0x11 && |
| (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); |
| } |
| |
| #endif /* _DRM_DP_HELPER_H_ */ |