0,0 → 1,207 |
#ifndef _ASM_X86_SPECIAL_INSNS_H |
#define _ASM_X86_SPECIAL_INSNS_H |
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#ifdef __KERNEL__ |
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static inline void native_clts(void) |
{ |
asm volatile("clts"); |
} |
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/* |
* Volatile isn't enough to prevent the compiler from reordering the |
* read/write functions for the control registers and messing everything up. |
* A memory clobber would solve the problem, but would prevent reordering of |
* all loads stores around it, which can hurt performance. Solution is to |
* use a variable and mimic reads and writes to it to enforce serialization |
*/ |
extern unsigned long __force_order; |
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static inline unsigned long native_read_cr0(void) |
{ |
unsigned long val; |
asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order)); |
return val; |
} |
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static inline void native_write_cr0(unsigned long val) |
{ |
asm volatile("mov %0,%%cr0": : "r" (val), "m" (__force_order)); |
} |
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static inline unsigned long native_read_cr2(void) |
{ |
unsigned long val; |
asm volatile("mov %%cr2,%0\n\t" : "=r" (val), "=m" (__force_order)); |
return val; |
} |
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static inline void native_write_cr2(unsigned long val) |
{ |
asm volatile("mov %0,%%cr2": : "r" (val), "m" (__force_order)); |
} |
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static inline unsigned long native_read_cr3(void) |
{ |
unsigned long val; |
asm volatile("mov %%cr3,%0\n\t" : "=r" (val), "=m" (__force_order)); |
return val; |
} |
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static inline void native_write_cr3(unsigned long val) |
{ |
asm volatile("mov %0,%%cr3": : "r" (val), "m" (__force_order)); |
} |
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static inline unsigned long native_read_cr4(void) |
{ |
unsigned long val; |
asm volatile("mov %%cr4,%0\n\t" : "=r" (val), "=m" (__force_order)); |
return val; |
} |
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static inline unsigned long native_read_cr4_safe(void) |
{ |
unsigned long val; |
/* This could fault if %cr4 does not exist. In x86_64, a cr4 always |
* exists, so it will never fail. */ |
#ifdef CONFIG_X86_32 |
asm volatile("1: mov %%cr4, %0\n" |
"2:\n" |
_ASM_EXTABLE(1b, 2b) |
: "=r" (val), "=m" (__force_order) : "0" (0)); |
#else |
val = native_read_cr4(); |
#endif |
return val; |
} |
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static inline void native_write_cr4(unsigned long val) |
{ |
asm volatile("mov %0,%%cr4": : "r" (val), "m" (__force_order)); |
} |
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#ifdef CONFIG_X86_64 |
static inline unsigned long native_read_cr8(void) |
{ |
unsigned long cr8; |
asm volatile("movq %%cr8,%0" : "=r" (cr8)); |
return cr8; |
} |
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static inline void native_write_cr8(unsigned long val) |
{ |
asm volatile("movq %0,%%cr8" :: "r" (val) : "memory"); |
} |
#endif |
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static inline void native_wbinvd(void) |
{ |
asm volatile("wbinvd": : :"memory"); |
} |
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extern asmlinkage void native_load_gs_index(unsigned); |
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#ifdef CONFIG_PARAVIRT |
#include <asm/paravirt.h> |
#else |
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static inline unsigned long read_cr0(void) |
{ |
return native_read_cr0(); |
} |
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static inline void write_cr0(unsigned long x) |
{ |
native_write_cr0(x); |
} |
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static inline unsigned long read_cr2(void) |
{ |
return native_read_cr2(); |
} |
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static inline void write_cr2(unsigned long x) |
{ |
native_write_cr2(x); |
} |
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static inline unsigned long read_cr3(void) |
{ |
return native_read_cr3(); |
} |
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static inline void write_cr3(unsigned long x) |
{ |
native_write_cr3(x); |
} |
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static inline unsigned long read_cr4(void) |
{ |
return native_read_cr4(); |
} |
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static inline unsigned long read_cr4_safe(void) |
{ |
return native_read_cr4_safe(); |
} |
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static inline void write_cr4(unsigned long x) |
{ |
native_write_cr4(x); |
} |
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static inline void wbinvd(void) |
{ |
native_wbinvd(); |
} |
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#ifdef CONFIG_X86_64 |
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static inline unsigned long read_cr8(void) |
{ |
return native_read_cr8(); |
} |
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static inline void write_cr8(unsigned long x) |
{ |
native_write_cr8(x); |
} |
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static inline void load_gs_index(unsigned selector) |
{ |
native_load_gs_index(selector); |
} |
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#endif |
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/* Clear the 'TS' bit */ |
static inline void clts(void) |
{ |
native_clts(); |
} |
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#endif/* CONFIG_PARAVIRT */ |
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#define stts() write_cr0(read_cr0() | X86_CR0_TS) |
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static inline void clflush(volatile void *__p) |
{ |
asm volatile("clflush %0" : "+m" (*(volatile char __force *)__p)); |
} |
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static inline void clflushopt(volatile void *__p) |
{ |
alternative_io(".byte " __stringify(NOP_DS_PREFIX) "; clflush %P0", |
".byte 0x66; clflush %P0", |
X86_FEATURE_CLFLUSHOPT, |
"+m" (*(volatile char __force *)__p)); |
} |
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#define nop() asm volatile ("nop") |
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#endif /* __KERNEL__ */ |
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#endif /* _ASM_X86_SPECIAL_INSNS_H */ |