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#ifndef _ASM_X86_MSR_H |
#define _ASM_X86_MSR_H |
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#include <uapi/asm/msr.h> |
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#ifndef __ASSEMBLY__ |
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#include <asm/asm.h> |
#include <asm/errno.h> |
#include <asm/cpumask.h> |
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struct msr { |
union { |
struct { |
u32 l; |
u32 h; |
}; |
u64 q; |
}; |
}; |
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struct msr_info { |
u32 msr_no; |
struct msr reg; |
struct msr *msrs; |
int err; |
}; |
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struct msr_regs_info { |
u32 *regs; |
int err; |
}; |
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static inline unsigned long long native_read_tscp(unsigned int *aux) |
{ |
unsigned long low, high; |
asm volatile(".byte 0x0f,0x01,0xf9" |
: "=a" (low), "=d" (high), "=c" (*aux)); |
return low | ((u64)high << 32); |
} |
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/* |
* both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A" |
* constraint has different meanings. For i386, "A" means exactly |
* edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead, |
* it means rax *or* rdx. |
*/ |
#ifdef CONFIG_X86_64 |
#define DECLARE_ARGS(val, low, high) unsigned low, high |
#define EAX_EDX_VAL(val, low, high) ((low) | ((u64)(high) << 32)) |
#define EAX_EDX_ARGS(val, low, high) "a" (low), "d" (high) |
#define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) |
#else |
#define DECLARE_ARGS(val, low, high) unsigned long long val |
#define EAX_EDX_VAL(val, low, high) (val) |
#define EAX_EDX_ARGS(val, low, high) "A" (val) |
#define EAX_EDX_RET(val, low, high) "=A" (val) |
#endif |
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static inline unsigned long long native_read_msr(unsigned int msr) |
{ |
DECLARE_ARGS(val, low, high); |
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asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr)); |
return EAX_EDX_VAL(val, low, high); |
} |
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static inline unsigned long long native_read_msr_safe(unsigned int msr, |
int *err) |
{ |
DECLARE_ARGS(val, low, high); |
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asm volatile("2: rdmsr ; xor %[err],%[err]\n" |
"1:\n\t" |
".section .fixup,\"ax\"\n\t" |
"3: mov %[fault],%[err] ; jmp 1b\n\t" |
".previous\n\t" |
_ASM_EXTABLE(2b, 3b) |
: [err] "=r" (*err), EAX_EDX_RET(val, low, high) |
: "c" (msr), [fault] "i" (-EIO)); |
return EAX_EDX_VAL(val, low, high); |
} |
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static inline void native_write_msr(unsigned int msr, |
unsigned low, unsigned high) |
{ |
asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory"); |
} |
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/* Can be uninlined because referenced by paravirt */ |
notrace static inline int native_write_msr_safe(unsigned int msr, |
unsigned low, unsigned high) |
{ |
int err; |
asm volatile("2: wrmsr ; xor %[err],%[err]\n" |
"1:\n\t" |
".section .fixup,\"ax\"\n\t" |
"3: mov %[fault],%[err] ; jmp 1b\n\t" |
".previous\n\t" |
_ASM_EXTABLE(2b, 3b) |
: [err] "=a" (err) |
: "c" (msr), "0" (low), "d" (high), |
[fault] "i" (-EIO) |
: "memory"); |
return err; |
} |
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extern unsigned long long native_read_tsc(void); |
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extern int rdmsr_safe_regs(u32 regs[8]); |
extern int wrmsr_safe_regs(u32 regs[8]); |
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static __always_inline unsigned long long __native_read_tsc(void) |
{ |
DECLARE_ARGS(val, low, high); |
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asm volatile("rdtsc" : EAX_EDX_RET(val, low, high)); |
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return EAX_EDX_VAL(val, low, high); |
} |
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static inline unsigned long long native_read_pmc(int counter) |
{ |
DECLARE_ARGS(val, low, high); |
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asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter)); |
return EAX_EDX_VAL(val, low, high); |
} |
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#ifdef CONFIG_PARAVIRT |
#include <asm/paravirt.h> |
#else |
#include <linux/errno.h> |
/* |
* Access to machine-specific registers (available on 586 and better only) |
* Note: the rd* operations modify the parameters directly (without using |
* pointer indirection), this allows gcc to optimize better |
*/ |
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#define rdmsr(msr, low, high) \ |
do { \ |
u64 __val = native_read_msr((msr)); \ |
(void)((low) = (u32)__val); \ |
(void)((high) = (u32)(__val >> 32)); \ |
} while (0) |
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static inline void wrmsr(unsigned msr, unsigned low, unsigned high) |
{ |
native_write_msr(msr, low, high); |
} |
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#define rdmsrl(msr, val) \ |
((val) = native_read_msr((msr))) |
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#define wrmsrl(msr, val) \ |
native_write_msr((msr), (u32)((u64)(val)), (u32)((u64)(val) >> 32)) |
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/* wrmsr with exception handling */ |
static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high) |
{ |
return native_write_msr_safe(msr, low, high); |
} |
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/* rdmsr with exception handling */ |
#define rdmsr_safe(msr, low, high) \ |
({ \ |
int __err; \ |
u64 __val = native_read_msr_safe((msr), &__err); \ |
(*low) = (u32)__val; \ |
(*high) = (u32)(__val >> 32); \ |
__err; \ |
}) |
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static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) |
{ |
int err; |
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*p = native_read_msr_safe(msr, &err); |
return err; |
} |
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#define rdtscl(low) \ |
((low) = (u32)__native_read_tsc()) |
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#define rdtscll(val) \ |
((val) = __native_read_tsc()) |
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#define rdpmc(counter, low, high) \ |
do { \ |
u64 _l = native_read_pmc((counter)); \ |
(low) = (u32)_l; \ |
(high) = (u32)(_l >> 32); \ |
} while (0) |
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#define rdpmcl(counter, val) ((val) = native_read_pmc(counter)) |
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#define rdtscp(low, high, aux) \ |
do { \ |
unsigned long long _val = native_read_tscp(&(aux)); \ |
(low) = (u32)_val; \ |
(high) = (u32)(_val >> 32); \ |
} while (0) |
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#define rdtscpll(val, aux) (val) = native_read_tscp(&(aux)) |
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#endif /* !CONFIG_PARAVIRT */ |
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#define wrmsrl_safe(msr, val) wrmsr_safe((msr), (u32)(val), \ |
(u32)((val) >> 32)) |
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#define write_tsc(low, high) wrmsr(MSR_IA32_TSC, (low), (high)) |
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#define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0) |
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struct msr *msrs_alloc(void); |
void msrs_free(struct msr *msrs); |
int msr_set_bit(u32 msr, u8 bit); |
int msr_clear_bit(u32 msr, u8 bit); |
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#ifdef CONFIG_SMP |
int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); |
int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); |
int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); |
int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q); |
void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); |
void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); |
int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); |
int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); |
int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); |
int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q); |
int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); |
int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); |
#else /* CONFIG_SMP */ |
static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) |
{ |
rdmsr(msr_no, *l, *h); |
return 0; |
} |
static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) |
{ |
wrmsr(msr_no, l, h); |
return 0; |
} |
static inline int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) |
{ |
rdmsrl(msr_no, *q); |
return 0; |
} |
static inline int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q) |
{ |
wrmsrl(msr_no, q); |
return 0; |
} |
static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no, |
struct msr *msrs) |
{ |
rdmsr_on_cpu(0, msr_no, &(msrs[0].l), &(msrs[0].h)); |
} |
static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no, |
struct msr *msrs) |
{ |
wrmsr_on_cpu(0, msr_no, msrs[0].l, msrs[0].h); |
} |
static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, |
u32 *l, u32 *h) |
{ |
return rdmsr_safe(msr_no, l, h); |
} |
static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) |
{ |
return wrmsr_safe(msr_no, l, h); |
} |
static inline int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) |
{ |
return rdmsrl_safe(msr_no, q); |
} |
static inline int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q) |
{ |
return wrmsrl_safe(msr_no, q); |
} |
static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) |
{ |
return rdmsr_safe_regs(regs); |
} |
static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) |
{ |
return wrmsr_safe_regs(regs); |
} |
#endif /* CONFIG_SMP */ |
#endif /* __ASSEMBLY__ */ |
#endif /* _ASM_X86_MSR_H */ |