| /drivers/include/link.h |
|---|
| 0,0 → 1,60 |
| typedef struct link |
| { |
| struct link *prev; |
| struct link *next; |
| }link_t; |
| #define LIST_INITIALIZE(name) \ |
| link_t name = { .prev = &name, .next = &name } |
| #define list_get_instance(link, type, member) \ |
| ((type *)(((u8_t *)(link)) - ((u8_t *)&(((type *)NULL)->member)))) |
| static inline void link_initialize(link_t *link) |
| { |
| link->prev = NULL; |
| link->next = NULL; |
| } |
| static inline void list_initialize(link_t *head) |
| { |
| head->prev = head; |
| head->next = head; |
| } |
| static inline void list_append(link_t *link, link_t *head) |
| { |
| link->prev = head->prev; |
| link->next = head; |
| head->prev->next = link; |
| head->prev = link; |
| } |
| static inline void list_remove(link_t *link) |
| { |
| link->next->prev = link->prev; |
| link->prev->next = link->next; |
| link_initialize(link); |
| } |
| static inline Bool list_empty(link_t *head) |
| { |
| return head->next == head ? TRUE : FALSE; |
| } |
| static inline void list_prepend(link_t *link, link_t *head) |
| { |
| link->next = head->next; |
| link->prev = head; |
| head->next->prev = link; |
| head->next = link; |
| } |
| static inline list_insert(link_t *new, link_t *old) |
| { |
| new->prev = old->prev; |
| new->next = old; |
| new->prev->next = new; |
| old->prev = new; |
| } |
| /drivers/include/pci.h |
|---|
| 0,0 → 1,183 |
| #pragma pack(push, 1) |
| typedef struct |
| { |
| u16_t device; |
| u16_t ChipSet; |
| }PciChipset_t; |
| #pragma pack(pop) |
| #define VENDOR_ATI 0x1002 |
| #define PCI_CLASS_DISPLAY_VGA 0x0300 |
| /* |
| * Under PCI, each device has 256 bytes of configuration address space, |
| * of which the first 64 bytes are standardized as follows: |
| */ |
| #define PCI_VENDOR_ID 0x000 /* 16 bits */ |
| #define PCI_DEVICE_ID 0x002 /* 16 bits */ |
| #define PCI_COMMAND 0x004 /* 16 bits */ |
| #define PCI_COMMAND_IO 0x001 /* Enable response in I/O space */ |
| #define PCI_COMMAND_MEMORY 0x002 /* Enable response in Memory space */ |
| #define PCI_COMMAND_MASTER 0x004 /* Enable bus mastering */ |
| #define PCI_COMMAND_SPECIAL 0x008 /* Enable response to special cycles */ |
| #define PCI_COMMAND_INVALIDATE 0x010 /* Use memory write and invalidate */ |
| #define PCI_COMMAND_VGA_PALETTE 0x020 /* Enable palette snooping */ |
| #define PCI_COMMAND_PARITY 0x040 /* Enable parity checking */ |
| #define PCI_COMMAND_WAIT 0x080 /* Enable address/data stepping */ |
| #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ |
| #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ |
| #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ |
| #define PCI_STATUS 0x006 /* 16 bits */ |
| #define PCI_STATUS_CAP_LIST 0x010 /* Support Capability List */ |
| #define PCI_STATUS_66MHZ 0x020 /* Support 66 Mhz PCI 2.1 bus */ |
| #define PCI_STATUS_UDF 0x040 /* Support User Definable Features [obsolete] */ |
| #define PCI_STATUS_FAST_BACK 0x080 /* Accept fast-back to back */ |
| #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ |
| #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ |
| #define PCI_STATUS_DEVSEL_FAST 0x000 |
| #define PCI_STATUS_DEVSEL_MEDIUM 0x200 |
| #define PCI_STATUS_DEVSEL_SLOW 0x400 |
| #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ |
| #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ |
| #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ |
| #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ |
| #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ |
| #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */ |
| #define PCI_REVISION_ID 0x08 /* Revision ID */ |
| #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ |
| #define PCI_CLASS_DEVICE 0x0a /* Device class */ |
| #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ |
| #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ |
| #define PCI_HEADER_TYPE 0x0e /* 8 bits */ |
| #define PCI_HEADER_TYPE_NORMAL 0 |
| #define PCI_HEADER_TYPE_BRIDGE 1 |
| #define PCI_HEADER_TYPE_CARDBUS 2 |
| #define PCI_BIST 0x0f /* 8 bits */ |
| #define PCI_BIST_CODE_MASK 0x0f /* Return result */ |
| #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ |
| #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ |
| #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ |
| #define PCI_CB_CAPABILITY_LIST 0x14 |
| /* Capability lists */ |
| #define PCI_CAP_LIST_ID 0 /* Capability ID */ |
| #define PCI_CAP_ID_PM 0x01 /* Power Management */ |
| #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ |
| #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ |
| #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ |
| #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ |
| #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ |
| #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ |
| #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ |
| #define PCI_CAP_ID_VNDR 0x09 /* Vendor specific capability */ |
| #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ |
| #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ |
| #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ |
| #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ |
| #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ |
| #define PCI_CAP_SIZEOF 4 |
| /* AGP registers */ |
| #define PCI_AGP_VERSION 2 /* BCD version number */ |
| #define PCI_AGP_RFU 3 /* Rest of capability flags */ |
| #define PCI_AGP_STATUS 4 /* Status register */ |
| #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ |
| #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ |
| #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ |
| #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ |
| #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ |
| #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ |
| #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ |
| #define PCI_AGP_COMMAND 8 /* Control register */ |
| #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ |
| #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ |
| #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ |
| #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ |
| #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ |
| #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ |
| #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */ |
| #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */ |
| #define PCI_AGP_SIZEOF 12 |
| #define PCI_MAP_REG_START 0x10 |
| #define PCI_MAP_REG_END 0x28 |
| #define PCI_MAP_ROM_REG 0x30 |
| #define PCI_MAP_MEMORY 0x00000000 |
| #define PCI_MAP_IO 0x00000001 |
| #define PCI_MAP_MEMORY_TYPE 0x00000007 |
| #define PCI_MAP_IO_TYPE 0x00000003 |
| #define PCI_MAP_MEMORY_TYPE_32BIT 0x00000000 |
| #define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002 |
| #define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004 |
| #define PCI_MAP_MEMORY_TYPE_MASK 0x00000006 |
| #define PCI_MAP_MEMORY_CACHABLE 0x00000008 |
| #define PCI_MAP_MEMORY_ATTR_MASK 0x0000000e |
| #define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0 |
| #define PCI_MAP_IO_ATTR_MASK 0x00000003 |
| #define PCI_MAP_IS_IO(b) ((b) & PCI_MAP_IO) |
| #define PCI_MAP_IS_MEM(b) (!PCI_MAP_IS_IO(b)) |
| #define PCI_MAP_IS64BITMEM(b) \ |
| (((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT) |
| #define PCIGETMEMORY(b) ((b) & PCI_MAP_MEMORY_ADDRESS_MASK) |
| #define PCIGETMEMORY64HIGH(b) (*((CARD32*)&b + 1)) |
| #define PCIGETMEMORY64(b) \ |
| (PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32)) |
| #define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc |
| #define PCIGETIO(b) ((b) & PCI_MAP_IO_ADDRESS_MASK) |
| #define PCI_MAP_ROM_DECODE_ENABLE 0x00000001 |
| #define PCI_MAP_ROM_ADDRESS_MASK 0xfffff800 |
| #define PCIGETROM(b) ((b) & PCI_MAP_ROM_ADDRESS_MASK) |
| #ifndef PCI_DOM_MASK |
| # define PCI_DOM_MASK 0x0ffu |
| #endif |
| #define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu) |
| #define PCI_MAKE_TAG(b,d,f) ((((b) & (PCI_DOMBUS_MASK)) << 16) | \ |
| (((d) & 0x00001fu) << 11) | \ |
| (((f) & 0x000007u) << 8)) |
| #define PCI_BUS_FROM_TAG(tag) (((tag) >> 16) & (PCI_DOMBUS_MASK)) |
| #define PCI_DEV_FROM_TAG(tag) (((tag) & 0x0000f800u) >> 11) |
| #define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8) |
| #define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00u) >> 8) |
| #define PCI_CMD_STAT_REG 0x04 |
| typedef unsigned int PCITAG; |
| extern inline PCITAG |
| pciTag(int busnum, int devnum, int funcnum) |
| { |
| return(PCI_MAKE_TAG(busnum,devnum,funcnum)); |
| } |
| const PciChipset_t *PciDevMatch(u16_t dev,const PciChipset_t *list); |
| u32_t pciGetBaseSize(int bus, int devfn, int index, Bool destructive, Bool *min); |
| /drivers/include/syscall.h |
|---|
| 0,0 → 1,316 |
| #define OS_BASE 0x80000000 |
| typedef struct |
| { |
| u32_t handle; |
| u32_t io_code; |
| void *input; |
| int inp_size; |
| void *output; |
| int out_size; |
| }ioctl_t; |
| typedef int (__stdcall *srv_proc_t)(ioctl_t *); |
| #define ERR_OK 0 |
| #define ERR_PARAM -1 |
| u32_t __stdcall drvEntry(int)__asm__("_drvEntry"); |
| /////////////////////////////////////////////////////////////////////////////// |
| #define STDCALL __attribute__ ((stdcall)) __attribute__ ((dllimport)) |
| #define IMPORT __attribute__ ((dllimport)) |
| /////////////////////////////////////////////////////////////////////////////// |
| #define SysMsgBoardStr __SysMsgBoardStr |
| #define PciApi __PciApi |
| //#define RegService __RegService |
| #define CreateObject __CreateObject |
| #define DestroyObject __DestroyObject |
| /////////////////////////////////////////////////////////////////////////////// |
| #define PG_SW 0x003 |
| #define PG_NOCACHE 0x018 |
| void* STDCALL AllocKernelSpace(size_t size)__asm__("AllocKernelSpace"); |
| void* STDCALL KernelAlloc(size_t size)__asm__("KernelAlloc"); |
| void* STDCALL KernelFree(void *mem)__asm__("KernelFree"); |
| void* STDCALL UserAlloc(size_t size)__asm__("UserAlloc"); |
| int STDCALL UserFree(void *mem)__asm__("UserFree"); |
| addr_t STDCALL AllocPages(count_t count)__asm__("AllocPages"); |
| void* STDCALL CreateRingBuffer(size_t size, u32_t map)__asm__("CreateRingBuffer"); |
| u32_t STDCALL RegService(char *name, srv_proc_t proc)__asm__("RegService"); |
| int STDCALL AttachIntHandler(int irq, void *handler, u32_t access) __asm__("AttachIntHandler"); |
| //void *CreateObject(u32 pid, size_t size); |
| //void *DestroyObject(void *obj); |
| addr_t STDCALL MapIoMem(addr_t base, size_t size, u32_t flags)__asm__("MapIoMem"); |
| /////////////////////////////////////////////////////////////////////////////// |
| void STDCALL SetMouseData(int btn, int x, int y, |
| int z, int h)__asm__("SetMouseData"); |
| static u32_t PciApi(int cmd); |
| u8_t STDCALL PciRead8 (u32_t bus, u32_t devfn, u32_t reg)__asm__("PciRead8"); |
| u16_t STDCALL PciRead16(u32_t bus, u32_t devfn, u32_t reg)__asm__("PciRead16"); |
| u32_t STDCALL PciRead32(u32_t bus, u32_t devfn, u32_t reg)__asm__("PciRead32"); |
| u32_t STDCALL PciWrite8 (u32_t bus, u32_t devfn, u32_t reg,u8_t val) __asm__("PciWrite8"); |
| u32_t STDCALL PciWrite16(u32_t bus, u32_t devfn, u32_t reg,u16_t val)__asm__("PciWrite16"); |
| u32_t STDCALL PciWrite32(u32_t bus, u32_t devfn, u32_t reg,u32_t val)__asm__("PciWrite32"); |
| #define pciReadByte(tag, reg) \ |
| PciRead8(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg)) |
| #define pciReadWord(tag, reg) \ |
| PciRead16(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg)) |
| #define pciReadLong(tag, reg) \ |
| PciRead32(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg)) |
| #define pciWriteByte(tag, reg, val) \ |
| PciWrite8(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg),(val)) |
| #define pciWriteWord(tag, reg, val) \ |
| PciWrite16(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg),(val)) |
| #define pciWriteLong(tag, reg, val) \ |
| PciWrite32(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg),(val)) |
| /////////////////////////////////////////////////////////////////////////////// |
| int dbg_open(char *path); |
| int dbgprintf(const char* format, ...); |
| /////////////////////////////////////////////////////////////////////////////// |
| extern inline int GetScreenSize() |
| { |
| int retval; |
| asm("int $0x40" |
| :"=a"(retval) |
| :"a"(61), "b"(1)); |
| return retval; |
| } |
| extern inline int GetScreenBpp() |
| { |
| int retval; |
| asm("int $0x40" |
| :"=a"(retval) |
| :"a"(61), "b"(2)); |
| return retval; |
| } |
| extern inline int GetScreenPitch() |
| { |
| int retval; |
| asm("int $0x40" |
| :"=a"(retval) |
| :"a"(61), "b"(3)); |
| return retval; |
| } |
| extern inline u32_t GetPgAddr(void *mem) |
| { |
| u32_t retval; |
| __asm__ __volatile__ ( |
| "call *__imp__GetPgAddr \n\t" |
| :"=eax" (retval) |
| :"a" (mem) ); |
| return retval; |
| }; |
| extern inline void CommitPages(void *mem, u32_t page, u32_t size) |
| { |
| size = (size+4095) & ~4095; |
| __asm__ __volatile__ ( |
| "call *__imp__CommitPages" |
| ::"a" (page), "b"(mem),"c"(size>>12) |
| :"edx" ); |
| __asm__ __volatile__ ("":::"eax","ebx","ecx"); |
| }; |
| extern inline void UnmapPages(void *mem, size_t size) |
| { |
| size = (size+4095) & ~4095; |
| __asm__ __volatile__ ( |
| "call *__imp__UnmapPages" |
| ::"a" (mem), "c"(size>>12) |
| :"edx"); |
| __asm__ __volatile__ ("":::"eax","ecx"); |
| }; |
| extern inline void usleep(u32_t delay) |
| { |
| if( !delay ) |
| delay++; |
| delay*=1000; |
| while(delay--) |
| __asm__ __volatile__ ( |
| "xorl %%eax, %%eax \n\t" |
| "cpuid \n\t" |
| :::"eax","ebx","ecx","edx"); |
| }; |
| extern inline u32_t __PciApi(int cmd) |
| { |
| u32_t retval; |
| __asm__ __volatile__ ( |
| "call *__imp__PciApi" |
| :"=a" (retval) |
| :"a" (cmd) |
| :"memory"); |
| return retval; |
| }; |
| extern inline void* __CreateObject(u32_t pid, size_t size) |
| { |
| void *retval; |
| __asm__ __volatile__ ( |
| "call *__imp__CreateObject \n\t" |
| :"=a" (retval) |
| :"a" (size),"b"(pid) |
| :"esi","edi", "memory"); |
| return retval; |
| } |
| extern inline void *__DestroyObject(void *obj) |
| { |
| __asm__ __volatile__ ( |
| "call *__imp__DestroyObject" |
| : |
| :"a" (obj) |
| :"ebx","edx","esi","edi", "memory"); |
| } |
| /* |
| u32 __RegService(char *name, srv_proc_t proc) |
| { |
| u32 retval; |
| asm __volatile__ |
| ( |
| "pushl %%eax \n\t" |
| "pushl %%ebx \n\t" |
| "call *__imp__RegService \n\t" |
| :"=eax" (retval) |
| :"a" (proc), "b" (name) |
| :"memory" |
| ); |
| return retval; |
| }; |
| */ |
| extern inline u32_t safe_cli(void) |
| { |
| u32_t ifl; |
| __asm__ __volatile__ ( |
| "pushf\n\t" |
| "popl %0\n\t" |
| "cli\n" |
| : "=r" (ifl)); |
| return ifl; |
| } |
| extern inline void safe_sti(u32_t ifl) |
| { |
| __asm__ __volatile__ ( |
| "pushl %0\n\t" |
| "popf\n" |
| : : "r" (ifl) |
| ); |
| } |
| extern inline void __clear (void * dst, unsigned len) |
| { |
| u32_t tmp; |
| __asm__ __volatile__ ( |
| // "xorl %%eax, %%eax \n\t" |
| "cld \n\t" |
| "rep stosb \n" |
| :"=c"(tmp),"=D"(tmp) |
| :"a"(0),"c"(len),"D"(dst)); |
| __asm__ __volatile__ ("":::"ecx","edi"); |
| }; |
| extern inline void out8(const u16_t port, const u8_t val) |
| { |
| __asm__ __volatile__ |
| ("outb %1, %0\n" : : "dN"(port), "a"(val)); |
| } |
| extern inline void out16(const u16_t port, const u16_t val) |
| { |
| __asm__ __volatile__ |
| ("outw %1, %0\n" : : "dN"(port), "a"(val)); |
| } |
| extern inline void out32(const u16_t port, const u32_t val) |
| { |
| __asm__ __volatile__ |
| ("outl %1, %0\n" : : "dN"(port), "a"(val)); |
| } |
| extern inline u8_t in8(const u16_t port) |
| { |
| u8_t tmp; |
| __asm__ __volatile__ |
| ("inb %1, %0\n" : "=a"(tmp) : "dN"(port)); |
| return tmp; |
| }; |
| extern inline u16_t in16(const u16_t port) |
| { |
| u16_t tmp; |
| __asm__ __volatile__ |
| ("inw %1, %0\n" : "=a"(tmp) : "dN"(port)); |
| return tmp; |
| }; |
| extern inline u32_t in32(const u16_t port) |
| { |
| u32_t tmp; |
| __asm__ __volatile__ |
| ("inl %1, %0\n" : "=a"(tmp) : "dN"(port)); |
| return tmp; |
| }; |
| extern inline void delay(int time) |
| { |
| __asm__ __volatile__ ( |
| "call *__imp__Delay" |
| ::"b" (time)); |
| __asm__ __volatile__ ( |
| "":::"ebx"); |
| } |
| extern inline void change_task() |
| { |
| __asm__ __volatile__ ( |
| "call *__imp__ChangeTask"); |
| } |
| /drivers/include/types.h |
|---|
| 0,0 → 1,24 |
| #define NULL (void*)0 |
| typedef unsigned char u8_t; |
| typedef unsigned short int u16_t; |
| typedef unsigned int u32_t; |
| typedef unsigned long long u64_t; |
| typedef signed char i8_t; |
| typedef signed short int i16_t; |
| typedef unsigned int addr_t; |
| typedef unsigned int size_t; |
| typedef unsigned int count_t; |
| typedef unsigned int eflags_t; |
| typedef unsigned int Bool; |
| #define TRUE (Bool)1 |
| #define FALSE (Bool)0 |