| /contrib/toolchain/binutils/include/opcode/ChangeLog |
|---|
| 1,3 → 1,452 |
| 2015-12-15 Matthew Wahab <matthew.wahab@arm.com> |
| * aarch64.h (enum aarch64_opnd_qualifier): Add |
| AARCH64_OPND_QLF_V_2H. |
| 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> |
| * aarch64.h (aarch64_opnd): Add AARCH64_OPND_BARRIER_PSB. |
| * aarch64-asm-2.c: Regenerate. |
| * aarch64-dis-2.c: Regenerate. |
| * aarch64-opc-2.c: Regenerate. |
| * aarch64-opc.c (aarch64_hint_options): Add "csync". |
| (aarch64_print_operands): Handle AARCH64_OPND_BARRIER_PSB. |
| * aarch64-tbl.h (aarch64_feature_stat_profile): New. |
| (STAT_PROFILE): New. |
| (aarch64_opcode_table): Add "psb". |
| (AARCH64_OPERANDS): Add "BARRIER_PSB". |
| 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> |
| * aarch64.h (aarch64_hint_options): Declare. |
| (aarch64_opnd_info): Add field hint_option. |
| 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> |
| * aarch64.h (AARCH64_FEATURE_PROFILE): New. |
| 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> |
| * aarch64.h (aarch64_sys_ins_reg_supported_p): Declare. |
| 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> |
| * aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags. |
| (aarch64_sys_ins_reg_has_xt): Declare. |
| 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> |
| * aarch64.h (AARCH64_FEATURE_RAS): New. |
| (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS. |
| 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> |
| * aarch64.h (AARCH64_FEATURE_F16): Fix clash with |
| AARCH64_FEATURE_V8_1. |
| (AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC. |
| (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and |
| AARCH64_FEATURE_V8_1. |
| 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> |
| * aarch64.h (AARCH64_FEATURE_F16): New. |
| (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_F16 to ARMv8.2 |
| features. |
| 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> |
| * aarch64.h (aarch64_op): Add OP_BFC. |
| 2015-12-09 Matthew Wahab <matthew.wahab@arm.com> |
| * aarch64.h (AARCH64_FEATURE_V8_2): New. |
| (AARCH64_ARCH_V8_2): New. |
| 2015-12-08 Matthew Wahab <matthew.wahab@arm.com> |
| * aarch64.h (AARCH64_FEATURE_V8_1): New. |
| (AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1. |
| 2015-11-11 Alan Modra <amodra@gmail.com> |
| Peter Bergner <bergner@vnet.ibm.com> |
| * ppc.h (PPC_OPCODE_POWER9): New define. |
| (PPC_OPCODE_VSX3): Likewise. |
| 2015-11-02 Nick Clifton <nickc@redhat.com> |
| * rx.h (enum RX_Opcode_ID): Add more NOP opcodes. |
| 2015-11-02 Nick Clifton <nickc@redhat.com> |
| * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect. |
| 2015-10-28 Yao Qi <yao.qi@linaro.org> |
| * aarch64.h (aarch64_decode_insn): Update declaration. |
| 2015-10-07 Yao Qi <yao.qi@linaro.org> |
| * aarch64.h (aarch64_sys_ins_reg) <template>: Removed. |
| <name>: New field. |
| 2015-10-07 Yao Qi <yao.qi@linaro.org> |
| * aarch64.h [__cplusplus]: Wrap in extern "C". |
| 2015-10-07 Claudiu Zissulescu <claziss@synopsys.com> |
| Cupertino Miranda <cmiranda@synopsys.com> |
| * arc-func.h: New file. |
| * arc.h: Likewise. |
| 2015-10-02 Yao Qi <yao.qi@linaro.org> |
| * aarch64.h (aarch64_zero_register_p): Move the declaration |
| to column one. |
| 2015-10-02 Yao Qi <yao.qi@linaro.org> |
| * aarch64.h (aarch64_decode_insn): Declare it. |
| 2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com> |
| * s390.h (S390_INSTR_FLAG_HTM): New flag. |
| (S390_INSTR_FLAG_VX): New flag. |
| (S390_INSTR_FLAG_FACILITY_MASK): New flag mask. |
| 2015-09-23 Nick Clifton <nickc@redhat.com> |
| * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left |
| shifting. |
| 2015-09-22 Nick Clifton <nickc@redhat.com> |
| * rx.h (enum RX_Size): Add RX_Bad_Size entry. |
| 2015-09-09 Daniel Santos <daniel.santos@pobox.com> |
| * visium.h (gen_reg_table): Make static. |
| (fp_reg_table): Likewise. |
| (cc_table): Likewise. |
| 2015-07-20 Matthew Wahab <matthew.wahab@arm.com> |
| * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ. |
| (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2. |
| (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ. |
| (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2. |
| 2015-07-03 Alan Modra <amodra@gmail.com> |
| * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define. |
| 2015-07-01 Sandra Loosemore <sandra@codesourcery.com> |
| Cesar Philippidis <cesar@codesourcery.com> |
| * nios2.h (enum iw_format_type): Add R2 formats. |
| (enum overflow_type): Add signed_immed12_overflow and |
| enumeration_overflow for R2. |
| (struct nios2_opcode): Document new argument letters for R2. |
| (REG_3BIT, REG_LDWM, REG_POP): Define. |
| (includes): Include nios2r2.h. |
| (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare. |
| (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare. |
| (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare. |
| (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare. |
| (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare. |
| (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): |
| Declare. |
| * nios2r2.h: New file. |
| 2015-06-19 Peter Bergner <bergner@vnet.ibm.com> |
| * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New. |
| (ppc_optional_operand_value): New inline function. |
| 2015-06-04 Matthew Wahab <matthew.wahab@arm.com> |
| * aarch64.h (AARCH64_V8_1): New. |
| 2015-06-03 Matthew Wahab <matthew.wahab@arm.com> |
| * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New. |
| (ARM_ARCH_V8_1A): New. |
| (ARM_ARCH_V8_1A_FP): New. |
| (ARM_ARCH_V8_1A_SIMD): New. |
| (ARM_ARCH_V8_1A_CRYPTOV1): New. |
| (ARM_FEATURE_CORE): New. |
| 2015-06-02 Matthew Wahab <matthew.wahab@arm.com> |
| * arm.h (ARM_EXT2_PAN): New. |
| (ARM_FEATURE_CORE_HIGH): New. |
| 2015-06-02 Matthew Wahab <matthew.wahab@arm.com> |
| * arm.h (ARM_FEATURE_ALL): New. |
| 2015-06-02 Matthew Wahab <matthew.wahab@arm.com> |
| * aarch64.h (AARCH64_FEATURE_RDMA): New. |
| 2015-06-02 Matthew Wahab <matthew.wahab@arm.com> |
| * aarch64.h (AARCH64_FEATURE_LOR): New. |
| 2015-06-01 Matthew Wahab <matthew.wahab@arm.com> |
| * aarch64.h (AARCH64_FEATURE_PAN): New. |
| (aarch64_sys_reg_supported_p): Declare. |
| (aarch64_pstatefield_supported_p): Declare. |
| 2015-04-30 DJ Delorie <dj@redhat.com> |
| * rl78.h (RL78_Dis_Isa): New. |
| (rl78_decode_opcode): Add ISA parameter. |
| 2015-03-24 Terry Guo <terry.guo@arm.com> |
| * arm.h (arm_feature_set): Extended to provide more available bits. |
| (ARM_ANY): Updated to follow above new definition. |
| (ARM_CPU_HAS_FEATURE): Likewise. |
| (ARM_CPU_IS_ANY): Likewise. |
| (ARM_MERGE_FEATURE_SETS): Likewise. |
| (ARM_CLEAR_FEATURE): Likewise. |
| (ARM_FEATURE): Likewise. |
| (ARM_FEATURE_COPY): New macro. |
| (ARM_FEATURE_EQUAL): Likewise. |
| (ARM_FEATURE_ZERO): Likewise. |
| (ARM_FEATURE_CORE_EQUAL): Likewise. |
| (ARM_FEATURE_LOW): Likewise. |
| (ARM_FEATURE_CORE_LOW): Likewise. |
| (ARM_FEATURE_CORE_COPROC): Likewise. |
| 2015-02-19 Pedro Alves <palves@redhat.com> |
| * cgen.h [__cplusplus]: Wrap in extern "C". |
| * msp430-decode.h [__cplusplus]: Likewise. |
| * nios2.h [__cplusplus]: Likewise. |
| * rl78.h [__cplusplus]: Likewise. |
| * rx.h [__cplusplus]: Likewise. |
| * tilegx.h [__cplusplus]: Likewise. |
| 2015-01-28 James Bowman <james.bowman@ftdichip.com> |
| * ft32.h: New file. |
| 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
| * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13. |
| 2015-01-01 Alan Modra <amodra@gmail.com> |
| Update year range in copyright notice of all files. |
| 2014-12-27 Anthony Green <green@moxielogic.com> |
| * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from |
| MOXIE_F1_AiB4 and MOXIE_F1_ABi2. |
| 2014-12-06 Eric Botcazou <ebotcazou@adacore.com> |
| * visium.h: New file. |
| 2014-11-28 Sandra Loosemore <sandra@codesourcery.com> |
| * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete. |
| (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete. |
| (NIOS2_INSN_OPTARG): Renumber. |
| 2014-11-06 Sandra Loosemore <sandra@codesourcery.com> |
| * nios2.h (nios2_find_opcode_hash): Add mach parameter to |
| declaration. Fix obsolete comment. |
| 2014-10-23 Sandra Loosemore <sandra@codesourcery.com> |
| * nios2.h (enum iw_format_type): New. |
| (struct nios2_opcode): Update comments. Add size and format fields. |
| (NIOS2_INSN_OPTARG): New. |
| (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New. |
| (struct nios2_reg): Add regtype field. |
| (GET_INSN_FIELD, SET_INSN_FIELD): Delete. |
| (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete. |
| (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete. |
| (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete. |
| (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete. |
| (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete. |
| (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete. |
| (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete. |
| (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete. |
| (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete. |
| (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete. |
| (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete. |
| (OP_MASK_OP, OP_SH_OP): Delete. |
| (OP_MASK_IOP, OP_SH_IOP): Delete. |
| (OP_MASK_IRD, OP_SH_IRD): Delete. |
| (OP_MASK_IRT, OP_SH_IRT): Delete. |
| (OP_MASK_IRS, OP_SH_IRS): Delete. |
| (OP_MASK_ROP, OP_SH_ROP): Delete. |
| (OP_MASK_RRD, OP_SH_RRD): Delete. |
| (OP_MASK_RRT, OP_SH_RRT): Delete. |
| (OP_MASK_RRS, OP_SH_RRS): Delete. |
| (OP_MASK_JOP, OP_SH_JOP): Delete. |
| (OP_MASK_IMM26, OP_SH_IMM26): Delete. |
| (OP_MASK_RCTL, OP_SH_RCTL): Delete. |
| (OP_MASK_IMM5, OP_SH_IMM5): Delete. |
| (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete. |
| (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete. |
| (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete. |
| (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete. |
| (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete. |
| (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete. |
| (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete. |
| (OP_MASK_<insn>, OP_MASK): Delete. |
| (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete. |
| (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete. |
| Include nios2r1.h to define new instruction opcode constants |
| and accessors. |
| (nios2_builtin_opcodes): Rename to nios2_r1_opcodes. |
| (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes. |
| (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes. |
| (NUMOPCODES, NUMREGISTERS): Delete. |
| * nios2r1.h: New file. |
| 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com> |
| * sparc.h (HWCAP2_VIS3B): Documentation improved. |
| 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com> |
| * sparc.h (sparc_opcode): new field `hwcaps2'. |
| (HWCAP2_FJATHPLUS): New define. |
| (HWCAP2_VIS3B): Likewise. |
| (HWCAP2_ADP): Likewise. |
| (HWCAP2_SPARC5): Likewise. |
| (HWCAP2_MWAIT): Likewise. |
| (HWCAP2_XMPMUL): Likewise. |
| (HWCAP2_XMONT): Likewise. |
| (HWCAP2_NSEC): Likewise. |
| (HWCAP2_FJATHHPC): Likewise. |
| (HWCAP2_FJDES): Likewise. |
| (HWCAP2_FJAES): Likewise. |
| Document the new operand kind `{', corresponding to the mcdper |
| ancillary state register. |
| Document the new operand kind }, which represents frsd floating |
| point registers (double precision) which must be the same than |
| frs1 in its containing instruction. |
| 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com> |
| * nds32.h: Add new opcode declaration. |
| 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com> |
| Matthew Fortune <matthew.fortune@imgtec.com> |
| * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT, |
| OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6 |
| instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B, |
| +I, +O, +R, +:, +\, +", +; |
| (mips_check_prev_operand): New struct. |
| (INSN2_FORBIDDEN_SLOT): New define. |
| (INSN_ISA32R6): New define. |
| (INSN_ISA64R6): New define. |
| (INSN_UPTO32R6): New define. |
| (INSN_UPTO64R6): New define. |
| (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6. |
| (ISA_MIPS32R6): New define. |
| (ISA_MIPS64R6): New define. |
| (CPU_MIPS32R6): New define. |
| (CPU_MIPS64R6): New define. |
| (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6. |
| 2014-09-03 Jiong Wang <jiong.wang@arm.com> |
| * aarch64.h (AARCH64_FEATURE_LSE): New feature added. |
| (aarch64_opnd): Add AARCH64_OPND_PAIRREG. |
| (aarch64_insn_class): Add lse_atomic. |
| (F_LSE_SZ): New field added. |
| (opcode_has_special_coder): Recognize F_LSE_SZ. |
| 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com> |
| * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B' |
| over to `+J'. |
| 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com> |
| * mips.h (INSN_LOAD_COPROC_DELAY): Rename to... |
| (INSN_LOAD_COPROC): New define. |
| (INSN_COPROC_MOVE_DELAY): Rename to... |
| (INSN_COPROC_MOVE): New define. |
| 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm> |
| Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com> |
| Pitchumani Sivanupandi <pitchumani.s@atmel.com> |
| Soundararajan <Sounderarajan.D@atmel.com> |
| * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA. |
| (AVR_ISA_2xxxa): Define ISA without LPM. |
| (AVR_ISA_AVRTINY): Define avrtiny arch ISA. |
| Add doc for contraint used in 16 bit lds/sts. |
| Adjust ISA group for icall, ijmp, pop and push. |
| Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints. |
| 2014-05-19 Nick Clifton <nickc@redhat.com> |
| * msp430.h (struct msp430_operand_s): Add vshift field. |
| 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com> |
| * mips.h (INSN_ISA_MASK): Updated. |
| (INSN_ISA32R3): New define. |
| (INSN_ISA32R5): New define. |
| (INSN_ISA64R3): New define. |
| (INSN_ISA64R5): New define. |
| (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32 |
| INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered. |
| (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and |
| mips64r5. |
| (INSN_UPTO32R3): New define. |
| (INSN_UPTO32R5): New define. |
| (INSN_UPTO64R3): New define. |
| (INSN_UPTO64R5): New define. |
| (ISA_MIPS32R3): New define. |
| (ISA_MIPS32R5): New define. |
| (ISA_MIPS64R3): New define. |
| (ISA_MIPS64R5): New define. |
| (CPU_MIPS32R3): New define. |
| (CPU_MIPS32R5): New define. |
| (CPU_MIPS64R3): New define. |
| (CPU_MIPS64R5): New define. |
| 2014-05-01 Richard Sandiford <rdsandiford@googlemail.com> |
| * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values. |
| 2014-04-22 Christian Svensson <blue@cmd.nu> |
| * or32.h: Delete. |
| 2014-03-05 Alan Modra <amodra@gmail.com> |
| Update copyright years. |
| 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com> |
| * mips.h: Updated description of +o, +u, +v and +w for MIPS and |
| microMIPS. |
| 2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com> |
| Wei-Cheng Wang <cole945@gmail.com> |
| * nds32.h: New file for Andes NDS32. |
| 2013-12-07 Mike Frysinger <vapier@gentoo.org> |
| * bfin.h: Remove +x file mode. |
| 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com> |
| * aarch64.h (aarch64_pstatefields): Change element type to |
| 34,6 → 483,19 |
| * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND. |
| (enum aarch64_opnd): Add AARCH64_OPND_COND1. |
| 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com> |
| * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX. |
| (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL. |
| For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, |
| +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|. |
| For MIPS, update extension character sequences after +. |
| (ASE_MSA): New define. |
| (ASE_MSA64): New define. |
| For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, |
| +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|. |
| For microMIPS, update extension character sequences after +. |
| 2013-08-23 Yuri Chornoivan <yurchor@ukr.net> |
| PR binutils/15834 |
| 1925,7 → 2387,7 |
| For older changes see ChangeLog-9103 |
| Copyright (C) 2004-2012 Free Software Foundation, Inc. |
| Copyright (C) 2004-2015 Free Software Foundation, Inc. |
| Copying and distribution of this file, with or without modification, |
| are permitted in any medium without royalty provided the copyright |
| /contrib/toolchain/binutils/include/opcode/aarch64.h |
|---|
| 1,6 → 1,6 |
| /* AArch64 assembler/disassembler support. |
| Copyright 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc. |
| Copyright (C) 2009-2015 Free Software Foundation, Inc. |
| Contributed by ARM Ltd. |
| This file is part of GNU Binutils. |
| 27,6 → 27,10 |
| #include <assert.h> |
| #include <stdlib.h> |
| #ifdef __cplusplus |
| extern "C" { |
| #endif |
| /* The offset for pc-relative addressing is currently defined to be 0. */ |
| #define AARCH64_PCREL_OFFSET 0 |
| 34,15 → 38,46 |
| /* The following bitmasks control CPU features. */ |
| #define AARCH64_FEATURE_V8 0x00000001 /* All processors. */ |
| #define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */ |
| #define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */ |
| #define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */ |
| #define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */ |
| #define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */ |
| #define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */ |
| #define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */ |
| #define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */ |
| #define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */ |
| #define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */ |
| #define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */ |
| #define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */ |
| #define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */ |
| /* Architectures are the sum of the base and extensions. */ |
| #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ |
| AARCH64_FEATURE_FP \ |
| | AARCH64_FEATURE_SIMD) |
| #define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ |
| AARCH64_FEATURE_FP \ |
| | AARCH64_FEATURE_SIMD \ |
| | AARCH64_FEATURE_CRC \ |
| | AARCH64_FEATURE_V8_1 \ |
| | AARCH64_FEATURE_LSE \ |
| | AARCH64_FEATURE_PAN \ |
| | AARCH64_FEATURE_LOR \ |
| | AARCH64_FEATURE_RDMA) |
| #define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ |
| AARCH64_FEATURE_V8_2 \ |
| | AARCH64_FEATURE_F16 \ |
| | AARCH64_FEATURE_RAS \ |
| | AARCH64_FEATURE_FP \ |
| | AARCH64_FEATURE_SIMD \ |
| | AARCH64_FEATURE_CRC \ |
| | AARCH64_FEATURE_V8_1 \ |
| | AARCH64_FEATURE_LSE \ |
| | AARCH64_FEATURE_PAN \ |
| | AARCH64_FEATURE_LOR \ |
| | AARCH64_FEATURE_RDMA) |
| #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) |
| #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */ |
| 106,6 → 141,7 |
| AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */ |
| AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */ |
| AARCH64_OPND_PAIRREG, /* Paired register operand. */ |
| AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */ |
| AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */ |
| 201,6 → 237,7 |
| AARCH64_OPND_BARRIER, /* Barrier operand. */ |
| AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */ |
| AARCH64_OPND_PRFOP, /* Prefetch operation. */ |
| AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */ |
| }; |
| /* Qualifier constrains an operand. It either specifies a variant of an |
| 245,6 → 282,7 |
| constraint qualifiers for immediate operands wherever possible. */ |
| AARCH64_OPND_QLF_V_8B, |
| AARCH64_OPND_QLF_V_16B, |
| AARCH64_OPND_QLF_V_2H, |
| AARCH64_OPND_QLF_V_4H, |
| AARCH64_OPND_QLF_V_8H, |
| AARCH64_OPND_QLF_V_2S, |
| 340,6 → 378,7 |
| loadlit, |
| log_imm, |
| log_shift, |
| lse_atomic, |
| movewide, |
| pcreladdr, |
| ic_system, |
| 407,6 → 446,7 |
| OP_SBFX, |
| OP_SBFIZ, |
| OP_BFI, |
| OP_BFC, /* ARMv8.2. */ |
| OP_UBFIZ, |
| OP_UXTB, |
| OP_UXTH, |
| 550,7 → 590,9 |
| #define F_N (1 << 23) |
| /* Opcode dependent field. */ |
| #define F_OD(X) (((X) & 0x7) << 24) |
| /* Next bit is 27. */ |
| /* Instruction has the field of 'sz'. */ |
| #define F_LSE_SZ (1 << 27) |
| /* Next bit is 28. */ |
| static inline bfd_boolean |
| alias_opcode_p (const aarch64_opcode *opcode) |
| 599,7 → 641,7 |
| static inline bfd_boolean |
| opcode_has_special_coder (const aarch64_opcode *opcode) |
| { |
| return (opcode->flags & (F_SF | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T |
| return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T |
| | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE |
| : FALSE; |
| } |
| 613,6 → 655,7 |
| extern const struct aarch64_name_value_pair aarch64_operand_modifiers []; |
| extern const struct aarch64_name_value_pair aarch64_barrier_options [16]; |
| extern const struct aarch64_name_value_pair aarch64_prfops [32]; |
| extern const struct aarch64_name_value_pair aarch64_hint_options []; |
| typedef struct |
| { |
| 624,14 → 667,23 |
| extern const aarch64_sys_reg aarch64_sys_regs []; |
| extern const aarch64_sys_reg aarch64_pstatefields []; |
| extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *); |
| extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set, |
| const aarch64_sys_reg *); |
| extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set, |
| const aarch64_sys_reg *); |
| typedef struct |
| { |
| const char *template; |
| const char *name; |
| uint32_t value; |
| int has_xt; |
| uint32_t flags ; |
| } aarch64_sys_ins_reg; |
| extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *); |
| extern bfd_boolean |
| aarch64_sys_ins_reg_supported_p (const aarch64_feature_set, |
| const aarch64_sys_ins_reg *); |
| extern const aarch64_sys_ins_reg aarch64_sys_regs_ic []; |
| extern const aarch64_sys_ins_reg aarch64_sys_regs_dc []; |
| extern const aarch64_sys_ins_reg aarch64_sys_regs_at []; |
| 737,6 → 789,7 |
| aarch64_insn pstatefield; |
| const aarch64_sys_ins_reg *sysins_op; |
| const struct aarch64_name_value_pair *barrier; |
| const struct aarch64_name_value_pair *hint_option; |
| const struct aarch64_name_value_pair *prfop; |
| }; |
| 901,9 → 954,12 |
| extern int |
| aarch64_stack_pointer_p (const aarch64_opnd_info *); |
| extern |
| int aarch64_zero_register_p (const aarch64_opnd_info *); |
| extern int |
| aarch64_zero_register_p (const aarch64_opnd_info *); |
| extern int |
| aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean); |
| /* Given an operand qualifier, return the expected data element size |
| of a qualified operand. */ |
| extern unsigned char |
| 940,4 → 996,8 |
| #define DEBUG_TRACE_IF(C, M, ...) ; |
| #endif /* DEBUG_AARCH64 */ |
| #ifdef __cplusplus |
| } |
| #endif |
| #endif /* OPCODE_AARCH64_H */ |
| /contrib/toolchain/binutils/include/opcode/alpha.h |
|---|
| 1,5 → 1,5 |
| /* alpha.h -- Header file for Alpha opcode table |
| Copyright 1996, 1999, 2001, 2003, 2010 Free Software Foundation, Inc. |
| Copyright (C) 1996-2015 Free Software Foundation, Inc. |
| Contributed by Richard Henderson <rth@tamu.edu>, |
| patterned after the PPC opcode table written by Ian Lance Taylor. |
| /contrib/toolchain/binutils/include/opcode/arc-func.h |
|---|
| 0,0 → 1,236 |
| /* Replace functions for the ARC relocs. |
| Copyright 2015 |
| Free Software Foundation, Inc. |
| This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and |
| the GNU Binutils. |
| GAS/GDB is free software; you can redistribute it and/or modify |
| it under the terms of the GNU General Public License as published by |
| the Free Software Foundation; either version 3, or (at your option) |
| any later version. |
| GAS/GDB is distributed in the hope that it will be useful, |
| but WITHOUT ANY WARRANTY; without even the implied warranty of |
| MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| GNU General Public License for more details. |
| You should have received a copy of the GNU General Public License |
| along with GAS or GDB; see the file COPYING3. If not, write to |
| the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
| MA 02110-1301, USA. */ |
| /* mask = 00000000000000000000000000000000. */ |
| #ifndef REPLACE_none |
| #define REPLACE_none |
| ATTRIBUTE_UNUSED static unsigned |
| replace_none (unsigned insn, int value ATTRIBUTE_UNUSED) |
| { |
| return insn; |
| } |
| #endif /* REPLACE_none */ |
| /* mask = 11111111. */ |
| #ifndef REPLACE_bits8 |
| #define REPLACE_bits8 |
| ATTRIBUTE_UNUSED static unsigned |
| replace_bits8 (unsigned insn, int value ATTRIBUTE_UNUSED) |
| { |
| insn |= ((value >> 0) & 0x00ff) << 0; |
| return insn; |
| } |
| #endif /* REPLACE_bits8 */ |
| /* mask = 1111111111111111. */ |
| #ifndef REPLACE_bits16 |
| #define REPLACE_bits16 |
| ATTRIBUTE_UNUSED static unsigned |
| replace_bits16 (unsigned insn, int value ATTRIBUTE_UNUSED) |
| { |
| insn |= ((value >> 0) & 0xffff) << 0; |
| return insn; |
| } |
| #endif /* REPLACE_bits16 */ |
| /* mask = 111111111111111111111111. */ |
| #ifndef REPLACE_bits24 |
| #define REPLACE_bits24 |
| ATTRIBUTE_UNUSED static unsigned |
| replace_bits24 (unsigned insn, int value ATTRIBUTE_UNUSED) |
| { |
| insn |= ((value >> 0) & 0xffffff) << 0; |
| return insn; |
| } |
| #endif /* REPLACE_bits24 */ |
| /* mask = 11111111111111111111111111111111. */ |
| #ifndef REPLACE_word32 |
| #define REPLACE_word32 |
| ATTRIBUTE_UNUSED static unsigned |
| replace_word32 (unsigned insn, int value ATTRIBUTE_UNUSED) |
| { |
| insn |= ((value >> 0) & 0xffffffff) << 0; |
| return insn; |
| } |
| #endif /* REPLACE_word32 */ |
| /* mask = 0000000000000000000000000000000011111111111111111111111111111111. */ |
| #ifndef REPLACE_limm |
| #define REPLACE_limm |
| ATTRIBUTE_UNUSED static unsigned |
| replace_limm (unsigned insn, int value ATTRIBUTE_UNUSED) |
| { |
| insn |= ((value >> 0) & 0xffffffff) << 0; |
| return insn; |
| } |
| #endif /* REPLACE_limm */ |
| /* mask = 000000000000000011111111111111111111111111111111. */ |
| #ifndef REPLACE_limms |
| #define REPLACE_limms |
| ATTRIBUTE_UNUSED static unsigned |
| replace_limms (unsigned insn, int value ATTRIBUTE_UNUSED) |
| { |
| insn |= ((value >> 0) & 0xffffffff) << 0; |
| return insn; |
| } |
| #endif /* REPLACE_limms */ |
| /* mask = 00000111111111102222222222000000. */ |
| #ifndef REPLACE_disp21h |
| #define REPLACE_disp21h |
| ATTRIBUTE_UNUSED static unsigned |
| replace_disp21h (unsigned insn, int value ATTRIBUTE_UNUSED) |
| { |
| insn |= ((value >> 0) & 0x03ff) << 17; |
| insn |= ((value >> 10) & 0x03ff) << 6; |
| return insn; |
| } |
| #endif /* REPLACE_disp21h */ |
| /* mask = 00000111111111002222222222000000. */ |
| #ifndef REPLACE_disp21w |
| #define REPLACE_disp21w |
| ATTRIBUTE_UNUSED static unsigned |
| replace_disp21w (unsigned insn, int value ATTRIBUTE_UNUSED) |
| { |
| insn |= ((value >> 0) & 0x01ff) << 18; |
| insn |= ((value >> 9) & 0x03ff) << 6; |
| return insn; |
| } |
| #endif /* REPLACE_disp21w */ |
| /* mask = 00000111111111102222222222003333. */ |
| #ifndef REPLACE_disp25h |
| #define REPLACE_disp25h |
| ATTRIBUTE_UNUSED static unsigned |
| replace_disp25h (unsigned insn, int value ATTRIBUTE_UNUSED) |
| { |
| insn |= ((value >> 0) & 0x03ff) << 17; |
| insn |= ((value >> 10) & 0x03ff) << 6; |
| insn |= ((value >> 20) & 0x000f) << 0; |
| return insn; |
| } |
| #endif /* REPLACE_disp25h */ |
| /* mask = 00000111111111002222222222003333. */ |
| #ifndef REPLACE_disp25w |
| #define REPLACE_disp25w |
| ATTRIBUTE_UNUSED static unsigned |
| replace_disp25w (unsigned insn, int value ATTRIBUTE_UNUSED) |
| { |
| insn |= ((value >> 0) & 0x01ff) << 18; |
| insn |= ((value >> 9) & 0x03ff) << 6; |
| insn |= ((value >> 19) & 0x000f) << 0; |
| return insn; |
| } |
| #endif /* REPLACE_disp25w */ |
| /* mask = 00000000000000000000000111111111. */ |
| #ifndef REPLACE_disp9 |
| #define REPLACE_disp9 |
| ATTRIBUTE_UNUSED static unsigned |
| replace_disp9 (unsigned insn, int value ATTRIBUTE_UNUSED) |
| { |
| insn |= ((value >> 0) & 0x01ff) << 0; |
| return insn; |
| } |
| #endif /* REPLACE_disp9 */ |
| /* mask = 00000000111111112000000000000000. */ |
| #ifndef REPLACE_disp9ls |
| #define REPLACE_disp9ls |
| ATTRIBUTE_UNUSED static unsigned |
| replace_disp9ls (unsigned insn, int value ATTRIBUTE_UNUSED) |
| { |
| insn |= ((value >> 0) & 0x00ff) << 16; |
| insn |= ((value >> 8) & 0x0001) << 15; |
| return insn; |
| } |
| #endif /* REPLACE_disp9ls */ |
| /* mask = 0000000111111111. */ |
| #ifndef REPLACE_disp9s |
| #define REPLACE_disp9s |
| ATTRIBUTE_UNUSED static unsigned |
| replace_disp9s (unsigned insn, int value ATTRIBUTE_UNUSED) |
| { |
| insn |= ((value >> 0) & 0x01ff) << 0; |
| return insn; |
| } |
| #endif /* REPLACE_disp9s */ |
| /* mask = 0000011111111111. */ |
| #ifndef REPLACE_disp13s |
| #define REPLACE_disp13s |
| ATTRIBUTE_UNUSED static unsigned |
| replace_disp13s (unsigned insn, int value ATTRIBUTE_UNUSED) |
| { |
| insn |= ((value >> 0) & 0x07ff) << 0; |
| return insn; |
| } |
| #endif /* REPLACE_disp13s */ |
| /* mask = 0000022222200111. */ |
| #ifndef REPLACE_disp9s1 |
| #define REPLACE_disp9s1 |
| ATTRIBUTE_UNUSED static unsigned |
| replace_disp9s1 (unsigned insn, int value ATTRIBUTE_UNUSED) |
| { |
| insn |= ((value >> 0) & 0x0007) << 0; |
| insn |= ((value >> 3) & 0x003f) << 5; |
| return insn; |
| } |
| #endif /* REPLACE_disp9s1 */ |
| /contrib/toolchain/binutils/include/opcode/arc.h |
|---|
| 1,8 → 1,8 |
| /* Opcode table for the ARC. |
| Copyright 1994, 1995, 1997, 2001, 2002, 2003, 2010 |
| Free Software Foundation, Inc. |
| Contributed by Doug Evans (dje@cygnus.com). |
| Copyright 1994-2015 Free Software Foundation, Inc. |
| Contributed by Claudiu Zissulescu (claziss@synopsys.com) |
| This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and |
| the GNU Binutils. |
| 21,201 → 21,182 |
| the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
| MA 02110-1301, USA. */ |
| /* List of the various cpu types. |
| The tables currently use bit masks to say whether the instruction or |
| whatever is supported by a particular cpu. This lets us have one entry |
| apply to several cpus. |
| #ifndef OPCODE_ARC_H |
| #define OPCODE_ARC_H |
| The `base' cpu must be 0. The cpu type is treated independently of |
| endianness. The complete `mach' number includes endianness. |
| These values are internal to opcodes/bfd/binutils/gas. */ |
| #define ARC_MACH_5 0 |
| #define ARC_MACH_6 1 |
| #define ARC_MACH_7 2 |
| #define ARC_MACH_8 4 |
| #define MAX_INSN_ARGS 6 |
| #define MAX_INSN_FLGS 3 |
| /* Additional cpu values can be inserted here and ARC_MACH_BIG moved down. */ |
| #define ARC_MACH_BIG 16 |
| /* Instruction Class. */ |
| typedef enum |
| { |
| ARITH, |
| AUXREG, |
| BRANCH, |
| CONTROL, |
| DSP, |
| FLOAT, |
| INVALID, |
| JUMP, |
| KERNEL, |
| LOGICAL, |
| MEMORY, |
| } insn_class_t; |
| /* Mask of number of bits necessary to record cpu type. */ |
| #define ARC_MACH_CPU_MASK (ARC_MACH_BIG - 1) |
| /* Instruction Subclass. */ |
| typedef enum |
| { |
| NONE, |
| CVT, |
| BTSCN, |
| CD1, |
| CD2, |
| DIV, |
| DP, |
| MPY1E, |
| MPY6E, |
| MPY7E, |
| MPY8E, |
| MPY9E, |
| SHFT1, |
| SHFT2, |
| SWAP, |
| SP |
| } insn_subclass_t; |
| /* Mask of number of bits necessary to record cpu type + endianness. */ |
| #define ARC_MACH_MASK ((ARC_MACH_BIG << 1) - 1) |
| /* Flags class. */ |
| typedef enum |
| { |
| FNONE, |
| CND, /* Conditional flags. */ |
| WBM, /* Write-back modes. */ |
| FLG, /* F Flag. */ |
| SBP, /* Static branch prediction. */ |
| DLY, /* Delay slot. */ |
| DIF, /* Bypass caches. */ |
| SGX, /* Sign extend modes. */ |
| SZM /* Data size modes. */ |
| } flag_class_t; |
| /* Type to denote an ARC instruction (at least a 32 bit unsigned int). */ |
| /* The opcode table is an array of struct arc_opcode. */ |
| struct arc_opcode |
| { |
| /* The opcode name. */ |
| const char *name; |
| typedef unsigned int arc_insn; |
| /* The opcode itself. Those bits which will be filled in with |
| operands are zeroes. */ |
| unsigned opcode; |
| struct arc_opcode { |
| char *syntax; /* syntax of insn */ |
| unsigned long mask, value; /* recognize insn if (op&mask) == value */ |
| int flags; /* various flag bits */ |
| /* The opcode mask. This is used by the disassembler. This is a |
| mask containing ones indicating those bits which must match the |
| opcode field, and zeroes indicating those bits which need not |
| match (and are presumably filled in by operands). */ |
| unsigned mask; |
| /* Values for `flags'. */ |
| /* One bit flags for the opcode. These are primarily used to |
| indicate specific processors and environments support the |
| instructions. The defined values are listed below. */ |
| unsigned cpu; |
| /* Return CPU number, given flag bits. */ |
| #define ARC_OPCODE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) |
| /* The instruction class. This is used by gdb. */ |
| insn_class_t class; |
| /* Return MACH number, given flag bits. */ |
| #define ARC_OPCODE_MACH(bits) ((bits) & ARC_MACH_MASK) |
| /* The instruction subclass. */ |
| insn_subclass_t subclass; |
| /* First opcode flag bit available after machine mask. */ |
| #define ARC_OPCODE_FLAG_START (ARC_MACH_MASK + 1) |
| /* An array of operand codes. Each code is an index into the |
| operand table. They appear in the order which the operands must |
| appear in assembly code, and are terminated by a zero. */ |
| unsigned char operands[MAX_INSN_ARGS + 1]; |
| /* This insn is a conditional branch. */ |
| #define ARC_OPCODE_COND_BRANCH (ARC_OPCODE_FLAG_START) |
| #define SYNTAX_3OP (ARC_OPCODE_COND_BRANCH << 1) |
| #define SYNTAX_LENGTH (SYNTAX_3OP ) |
| #define SYNTAX_2OP (SYNTAX_3OP << 1) |
| #define OP1_MUST_BE_IMM (SYNTAX_2OP << 1) |
| #define OP1_IMM_IMPLIED (OP1_MUST_BE_IMM << 1) |
| #define SYNTAX_VALID (OP1_IMM_IMPLIED << 1) |
| #define I(x) (((x) & 31) << 27) |
| #define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA) |
| #define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB) |
| #define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC) |
| #define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */ |
| /* These values are used to optimize assembly and disassembly. Each insn |
| is on a list of related insns (same first letter for assembly, same |
| insn code for disassembly). */ |
| struct arc_opcode *next_asm; /* Next instr to try during assembly. */ |
| struct arc_opcode *next_dis; /* Next instr to try during disassembly. */ |
| /* Macros to create the hash values for the lists. */ |
| #define ARC_HASH_OPCODE(string) \ |
| ((string)[0] >= 'a' && (string)[0] <= 'z' ? (string)[0] - 'a' : 26) |
| #define ARC_HASH_ICODE(insn) \ |
| ((unsigned int) (insn) >> 27) |
| /* Macros to access `next_asm', `next_dis' so users needn't care about the |
| underlying mechanism. */ |
| #define ARC_OPCODE_NEXT_ASM(op) ((op)->next_asm) |
| #define ARC_OPCODE_NEXT_DIS(op) ((op)->next_dis) |
| /* An array of flag codes. Each code is an index into the flag |
| table. They appear in the order which the flags must appear in |
| assembly code, and are terminated by a zero. */ |
| unsigned char flags[MAX_INSN_FLGS + 1]; |
| }; |
| /* this is an "insert at front" linked list per Metaware spec |
| that new definitions override older ones. */ |
| extern struct arc_opcode *arc_ext_opcodes; |
| /* The table itself is sorted by major opcode number, and is otherwise |
| in the order in which the disassembler should consider |
| instructions. */ |
| extern const struct arc_opcode arc_opcodes[]; |
| extern const unsigned arc_num_opcodes; |
| struct arc_operand_value { |
| char *name; /* eg: "eq" */ |
| short value; /* eg: 1 */ |
| unsigned char type; /* index into `arc_operands' */ |
| unsigned char flags; /* various flag bits */ |
| /* CPU Availability. */ |
| #define ARC_OPCODE_ARC600 0x0001 /* ARC 600 specific insns. */ |
| #define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */ |
| #define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */ |
| #define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */ |
| /* Values for `flags'. */ |
| /* CPU extensions. */ |
| #define ARC_EA 0x0001 |
| #define ARC_CD 0x0001 /* Mutual exclusive with EA. */ |
| #define ARC_LLOCK 0x0002 |
| #define ARC_ATOMIC 0x0002 /* Mutual exclusive with LLOCK. */ |
| #define ARC_MPY 0x0004 |
| #define ARC_MULT 0x0004 |
| /* Return CPU number, given flag bits. */ |
| #define ARC_OPVAL_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) |
| /* Return MACH number, given flag bits. */ |
| #define ARC_OPVAL_MACH(bits) ((bits) & ARC_MACH_MASK) |
| }; |
| /* Floating point support. */ |
| #define ARC_DPFP 0x0010 |
| #define ARC_SPFP 0x0020 |
| #define ARC_FPU 0x0030 |
| struct arc_ext_operand_value { |
| struct arc_ext_operand_value *next; |
| struct arc_operand_value operand; |
| }; |
| /* NORM & SWAP. */ |
| #define ARC_SWAP 0x0100 |
| #define ARC_NORM 0x0200 |
| #define ARC_BSCAN 0x0200 |
| extern struct arc_ext_operand_value *arc_ext_operands; |
| /* A7 specific. */ |
| #define ARC_UIX 0x1000 |
| #define ARC_TSTAMP 0x1000 |
| struct arc_operand { |
| /* One of the insn format chars. */ |
| unsigned char fmt; |
| /* A6 specific. */ |
| #define ARC_VBFDW 0x1000 |
| #define ARC_BARREL 0x1000 |
| #define ARC_DSPA 0x1000 |
| /* The number of bits in the operand (may be unused for a modifier). */ |
| unsigned char bits; |
| /* EM specific. */ |
| #define ARC_SHIFT 0x1000 |
| /* How far the operand is left shifted in the instruction, or |
| the modifier's flag bit (may be unused for a modifier. */ |
| unsigned char shift; |
| /* V2 specific. */ |
| #define ARC_INTR 0x1000 |
| #define ARC_DIV 0x1000 |
| /* Various flag bits. */ |
| int flags; |
| /* V1 specific. */ |
| #define ARC_XMAC 0x1000 |
| #define ARC_CRC 0x1000 |
| /* Values for `flags'. */ |
| /* Base architecture -- all cpus. */ |
| #define ARC_OPCODE_BASE \ |
| (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \ |
| | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS) |
| /* This operand is a suffix to the opcode. */ |
| #define ARC_OPERAND_SUFFIX 1 |
| /* A macro to check for short instructions. */ |
| #define ARC_SHORT(mask) \ |
| (((mask) & 0xFFFF0000) ? 0 : 1) |
| /* This operand is a relative branch displacement. The disassembler |
| prints these symbolically if possible. */ |
| #define ARC_OPERAND_RELATIVE_BRANCH 2 |
| /* The operands table is an array of struct arc_operand. */ |
| struct arc_operand |
| { |
| /* The number of bits in the operand. */ |
| unsigned int bits; |
| /* This operand is an absolute branch address. The disassembler |
| prints these symbolically if possible. */ |
| #define ARC_OPERAND_ABSOLUTE_BRANCH 4 |
| /* How far the operand is left shifted in the instruction. */ |
| unsigned int shift; |
| /* This operand is an address. The disassembler |
| prints these symbolically if possible. */ |
| #define ARC_OPERAND_ADDRESS 8 |
| /* The default relocation type for this operand. */ |
| signed int default_reloc; |
| /* This operand is a long immediate value. */ |
| #define ARC_OPERAND_LIMM 0x10 |
| /* One bit syntax flags. */ |
| unsigned int flags; |
| /* This operand takes signed values. */ |
| #define ARC_OPERAND_SIGNED 0x20 |
| /* This operand takes signed values, but also accepts a full positive |
| range of values. That is, if bits is 16, it takes any value from |
| -0x8000 to 0xffff. */ |
| #define ARC_OPERAND_SIGNOPT 0x40 |
| /* This operand should be regarded as a negative number for the |
| purposes of overflow checking (i.e., the normal most negative |
| number is disallowed and one more than the normal most positive |
| number is allowed). This flag will only be set for a signed |
| operand. */ |
| #define ARC_OPERAND_NEGATIVE 0x80 |
| /* This operand doesn't really exist. The program uses these operands |
| in special ways. */ |
| #define ARC_OPERAND_FAKE 0x100 |
| /* separate flags operand for j and jl instructions */ |
| #define ARC_OPERAND_JUMPFLAGS 0x200 |
| /* allow warnings and errors to be issued after call to insert_xxxxxx */ |
| #define ARC_OPERAND_WARN 0x400 |
| #define ARC_OPERAND_ERROR 0x800 |
| /* this is a load operand */ |
| #define ARC_OPERAND_LOAD 0x8000 |
| /* this is a store operand */ |
| #define ARC_OPERAND_STORE 0x10000 |
| /* Modifier values. */ |
| /* A dot is required before a suffix. Eg: .le */ |
| #define ARC_MOD_DOT 0x1000 |
| /* A normal register is allowed (not used, but here for completeness). */ |
| #define ARC_MOD_REG 0x2000 |
| /* An auxiliary register name is expected. */ |
| #define ARC_MOD_AUXREG 0x4000 |
| /* Sum of all ARC_MOD_XXX bits. */ |
| #define ARC_MOD_BITS 0x7000 |
| /* Non-zero if the operand type is really a modifier. */ |
| #define ARC_MOD_P(X) ((X) & ARC_MOD_BITS) |
| /* enforce read/write only register restrictions */ |
| #define ARC_REGISTER_READONLY 0x01 |
| #define ARC_REGISTER_WRITEONLY 0x02 |
| #define ARC_REGISTER_NOSHORT_CUT 0x04 |
| /* Insertion function. This is used by the assembler. To insert an |
| operand value into an instruction, check this field. |
| If it is NULL, execute |
| i |= (p & ((1 << o->bits) - 1)) << o->shift; |
| (I is the instruction which we are filling in, O is a pointer to |
| this structure, and OP is the opcode value; this assumes twos |
| i |= (op & ((1 << o->bits) - 1)) << o->shift; |
| (i is the instruction which we are filling in, o is a pointer to |
| this structure, and op is the opcode value; this assumes twos |
| complement arithmetic). |
| If this field is not NULL, then simply call it with the |
| 223,14 → 204,10 |
| of the instruction. If the ERRMSG argument is not NULL, then if |
| the operand value is illegal, *ERRMSG will be set to a warning |
| string (the operand will be inserted in any case). If the |
| operand value is legal, *ERRMSG will be unchanged. |
| operand value is legal, *ERRMSG will be unchanged (most operands |
| can accept any value). */ |
| unsigned (*insert) (unsigned instruction, int op, const char **errmsg); |
| REG is non-NULL when inserting a register value. */ |
| arc_insn (*insert) |
| (arc_insn insn, const struct arc_operand *operand, int mods, |
| const struct arc_operand_value *reg, long value, const char **errmsg); |
| /* Extraction function. This is used by the disassembler. To |
| extract this operand type from an instruction, check this field. |
| 239,84 → 216,198 |
| if ((o->flags & ARC_OPERAND_SIGNED) != 0 |
| && (op & (1 << (o->bits - 1))) != 0) |
| op -= 1 << o->bits; |
| (I is the instruction, O is a pointer to this structure, and OP |
| (i is the instruction, o is a pointer to this structure, and op |
| is the result; this assumes twos complement arithmetic). |
| If this field is not NULL, then simply call it with the |
| instruction value. It will return the value of the operand. If |
| the INVALID argument is not NULL, *INVALID will be set to |
| non-zero if this operand type can not actually be extracted from |
| TRUE if this operand type can not actually be extracted from |
| this operand (i.e., the instruction does not match). If the |
| operand is valid, *INVALID will not be changed. |
| operand is valid, *INVALID will not be changed. */ |
| int (*extract) (unsigned instruction, bfd_boolean *invalid); |
| }; |
| INSN is a pointer to an array of two `arc_insn's. The first element is |
| the insn, the second is the limm if present. |
| /* Elements in the table are retrieved by indexing with values from |
| the operands field of the arc_opcodes table. */ |
| extern const struct arc_operand arc_operands[]; |
| extern const unsigned arc_num_operands; |
| extern const unsigned arc_Toperand; |
| extern const unsigned arc_NToperand; |
| Operands that have a printable form like registers and suffixes have |
| their struct arc_operand_value pointer stored in OPVAL. */ |
| /* Values defined for the flags field of a struct arc_operand. */ |
| long (*extract) |
| (arc_insn *insn, const struct arc_operand *operand, int mods, |
| const struct arc_operand_value **opval, int *invalid); |
| /* This operand does not actually exist in the assembler input. This |
| is used to support extended mnemonics, for which two operands fields |
| are identical. The assembler should call the insert function with |
| any op value. The disassembler should call the extract function, |
| ignore the return value, and check the value placed in the invalid |
| argument. */ |
| #define ARC_OPERAND_FAKE 0x0001 |
| /* This operand names an integer register. */ |
| #define ARC_OPERAND_IR 0x0002 |
| /* This operand takes signed values. */ |
| #define ARC_OPERAND_SIGNED 0x0004 |
| /* This operand takes unsigned values. This exists primarily so that |
| a flags value of 0 can be treated as end-of-arguments. */ |
| #define ARC_OPERAND_UNSIGNED 0x0008 |
| /* This operand takes long immediate values. */ |
| #define ARC_OPERAND_LIMM 0x0010 |
| /* This operand is identical like the previous one. */ |
| #define ARC_OPERAND_DUPLICATE 0x0020 |
| /* This operand is PC relative. Used for internal relocs. */ |
| #define ARC_OPERAND_PCREL 0x0040 |
| /* This operand is truncated. The truncation is done accordingly to |
| operand alignment attribute. */ |
| #define ARC_OPERAND_TRUNCATE 0x0080 |
| /* This operand is 16bit aligned. */ |
| #define ARC_OPERAND_ALIGNED16 0x0100 |
| /* This operand is 32bit aligned. */ |
| #define ARC_OPERAND_ALIGNED32 0x0200 |
| /* This operand can be ignored by matching process if it is not |
| present. */ |
| #define ARC_OPERAND_IGNORE 0x0400 |
| /* Don't check the range when matching. */ |
| #define ARC_OPERAND_NCHK 0x0800 |
| /* Mark the braket possition. */ |
| #define ARC_OPERAND_BRAKET 0x1000 |
| /* Mask for selecting the type for typecheck purposes. */ |
| #define ARC_OPERAND_TYPECHECK_MASK \ |
| (ARC_OPERAND_IR | \ |
| ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | \ |
| ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET) |
| /* The flags structure. */ |
| struct arc_flag_operand |
| { |
| /* The flag name. */ |
| const char *name; |
| /* The flag code. */ |
| unsigned code; |
| /* The number of bits in the operand. */ |
| unsigned int bits; |
| /* How far the operand is left shifted in the instruction. */ |
| unsigned int shift; |
| /* Available for disassembler. */ |
| unsigned char favail; |
| }; |
| /* Bits that say what version of cpu we have. These should be passed to |
| arc_init_opcode_tables. At present, all there is is the cpu type. */ |
| /* The flag operands table. */ |
| extern const struct arc_flag_operand arc_flag_operands[]; |
| extern const unsigned arc_num_flag_operands; |
| /* CPU number, given value passed to `arc_init_opcode_tables'. */ |
| #define ARC_HAVE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) |
| /* MACH number, given value passed to `arc_init_opcode_tables'. */ |
| #define ARC_HAVE_MACH(bits) ((bits) & ARC_MACH_MASK) |
| /* The flag's class structure. */ |
| struct arc_flag_class |
| { |
| /* Flag class. */ |
| flag_class_t class; |
| /* Special register values: */ |
| #define ARC_REG_SHIMM_UPDATE 61 |
| #define ARC_REG_SHIMM 63 |
| #define ARC_REG_LIMM 62 |
| /* List of valid flags (codes). */ |
| unsigned flags[256]; |
| }; |
| /* Non-zero if REG is a constant marker. */ |
| #define ARC_REG_CONSTANT_P(REG) ((REG) >= 61) |
| extern const struct arc_flag_class arc_flag_classes[]; |
| /* Positions and masks of various fields: */ |
| #define ARC_SHIFT_REGA 21 |
| #define ARC_SHIFT_REGB 15 |
| #define ARC_SHIFT_REGC 9 |
| #define ARC_MASK_REG 63 |
| /* Structure for special cases. */ |
| struct arc_flag_special |
| { |
| /* Name of special case instruction. */ |
| const char *name; |
| /* Delay slot types. */ |
| #define ARC_DELAY_NONE 0 /* no delay slot */ |
| #define ARC_DELAY_NORMAL 1 /* delay slot in both cases */ |
| #define ARC_DELAY_JUMP 2 /* delay slot only if branch taken */ |
| /* List of flags applicable for special case instruction. */ |
| unsigned flags[32]; |
| }; |
| /* Non-zero if X will fit in a signed 9 bit field. */ |
| #define ARC_SHIMM_CONST_P(x) ((long) (x) >= -256 && (long) (x) <= 255) |
| extern const struct arc_flag_special arc_flag_special_cases[]; |
| extern const unsigned arc_num_flag_special; |
| extern const struct arc_operand arc_operands[]; |
| extern const int arc_operand_count; |
| extern struct arc_opcode arc_opcodes[]; |
| extern const int arc_opcodes_count; |
| extern const struct arc_operand_value arc_suffixes[]; |
| extern const int arc_suffixes_count; |
| extern const struct arc_operand_value arc_reg_names[]; |
| extern const int arc_reg_names_count; |
| extern unsigned char arc_operand_map[]; |
| /* Relocation equivalence structure. */ |
| struct arc_reloc_equiv_tab |
| { |
| const char * name; /* String to lookup. */ |
| const char * mnemonic; /* Extra matching condition. */ |
| unsigned flagcode; /* Extra matching condition. */ |
| signed int oldreloc; /* Old relocation. */ |
| signed int newreloc; /* New relocation. */ |
| }; |
| /* Utility fns in arc-opc.c. */ |
| int arc_get_opcode_mach (int, int); |
| extern const struct arc_reloc_equiv_tab arc_reloc_equiv[]; |
| extern const unsigned arc_num_equiv_tab; |
| /* `arc_opcode_init_tables' must be called before `arc_xxx_supported'. */ |
| void arc_opcode_init_tables (int); |
| void arc_opcode_init_insert (void); |
| void arc_opcode_init_extract (void); |
| const struct arc_opcode *arc_opcode_lookup_asm (const char *); |
| const struct arc_opcode *arc_opcode_lookup_dis (unsigned int); |
| int arc_opcode_limm_p (long *); |
| const struct arc_operand_value *arc_opcode_lookup_suffix |
| (const struct arc_operand *type, int value); |
| int arc_opcode_supported (const struct arc_opcode *); |
| int arc_opval_supported (const struct arc_operand_value *); |
| int arc_limm_fixup_adjust (arc_insn); |
| int arc_insn_is_j (arc_insn); |
| int arc_insn_not_jl (arc_insn); |
| int arc_operand_type (int); |
| struct arc_operand_value *get_ext_suffix (char *); |
| int arc_get_noshortcut_flag (void); |
| /* Structure for operand operations for pseudo/alias instructions. */ |
| struct arc_operand_operation |
| { |
| /* The index for operand from operand array. */ |
| unsigned operand_idx; |
| /* Defines if it needs the operand inserted by the assembler or |
| whether this operand comes from the pseudo instruction's |
| operands. */ |
| unsigned char needs_insert; |
| /* Count we have to add to the operand. Use negative number to |
| subtract from the operand. Also use this number to add to 0 if |
| the operand needs to be inserted (i.e. needs_insert == 1). */ |
| int count; |
| /* Index of the operand to swap with. To be done AFTER applying |
| inc_count. */ |
| unsigned swap_operand_idx; |
| }; |
| /* Structure for pseudo/alias instructions. */ |
| struct arc_pseudo_insn |
| { |
| /* Mnemonic for pseudo/alias insn. */ |
| const char *mnemonic_p; |
| /* Mnemonic for real instruction. */ |
| const char *mnemonic_r; |
| /* Flag that will have to be added (if any). */ |
| const char *flag_r; |
| /* Amount of operands. */ |
| unsigned operand_cnt; |
| /* Array of operand operations. */ |
| struct arc_operand_operation operand[6]; |
| }; |
| extern const struct arc_pseudo_insn arc_pseudo_insns[]; |
| extern const unsigned arc_num_pseudo_insn; |
| /* Structure for AUXILIARY registers. */ |
| struct arc_aux_reg |
| { |
| /* Register address. */ |
| int address; |
| /* Register name. */ |
| const char *name; |
| /* Size of the string. */ |
| size_t length; |
| }; |
| extern const struct arc_aux_reg arc_aux_regs[]; |
| extern const unsigned arc_num_aux_regs; |
| #endif /* OPCODE_ARC_H */ |
| /contrib/toolchain/binutils/include/opcode/arm.h |
|---|
| 1,5 → 1,5 |
| /* ARM assembler/disassembler support. |
| Copyright 2004, 2010, 2011 Free Software Foundation, Inc. |
| Copyright (C) 2004-2015 Free Software Foundation, Inc. |
| This file is part of GDB and GAS. |
| 57,6 → 57,8 |
| state. */ |
| #define ARM_EXT_VIRT 0x80000000 /* Virtualization extensions. */ |
| #define ARM_EXT2_PAN 0x00000001 /* PAN extension. */ |
| /* Co-processor space extensions. */ |
| #define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */ |
| #define ARM_CEXT_MAVERICK 0x00000002 /* Use Cirrus/DSP coprocessor. */ |
| 78,10 → 80,12 |
| #define FPU_VFP_EXT_FP16 0x00100000 /* Half-precision extensions. */ |
| #define FPU_NEON_EXT_FMA 0x00080000 /* Neon fused multiply-add */ |
| #define FPU_VFP_EXT_FMA 0x00040000 /* VFP fused multiply-add */ |
| #define FPU_VFP_EXT_ARMV8 0x00020000 /* FP for ARMv8. */ |
| #define FPU_VFP_EXT_ARMV8 0x00020000 /* Double-precision FP for ARMv8. */ |
| #define FPU_NEON_EXT_ARMV8 0x00010000 /* Neon for ARMv8. */ |
| #define FPU_CRYPTO_EXT_ARMV8 0x00008000 /* Crypto for ARMv8. */ |
| #define CRC_EXT_ARMV8 0x00004000 /* CRC32 for ARMv8. */ |
| #define FPU_VFP_EXT_ARMV8xD 0x00002000 /* Single-precision FP for ARMv8. */ |
| #define FPU_NEON_EXT_RDMA 0x00001000 /* v8.1 Adv.SIMD extensions. */ |
| /* Architectures are the sum of the base and extensions. The ARM ARM (rev E) |
| defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T, |
| 107,13 → 111,13 |
| #define ARM_AEXT_V6 (ARM_AEXT_V5TEJ | ARM_EXT_V6) |
| #define ARM_AEXT_V6K (ARM_AEXT_V6 | ARM_EXT_V6K) |
| #define ARM_AEXT_V6Z (ARM_AEXT_V6K | ARM_EXT_SEC) |
| #define ARM_AEXT_V6ZK (ARM_AEXT_V6K | ARM_EXT_SEC) |
| #define ARM_AEXT_V6KZ (ARM_AEXT_V6K | ARM_EXT_SEC) |
| #define ARM_AEXT_V6T2 (ARM_AEXT_V6 \ |
| | ARM_EXT_V6T2 | ARM_EXT_V6_NOTM | ARM_EXT_THUMB_MSR \ |
| | ARM_EXT_V6_DSP ) |
| #define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K) |
| #define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_SEC) |
| #define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_SEC) |
| #define ARM_AEXT_V6KZT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_SEC) |
| #define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 | ARM_EXT_V7 | ARM_EXT_BARRIER) |
| #define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A) |
| #define ARM_AEXT_V7VE (ARM_AEXT_V7A | ARM_EXT_DIV | ARM_EXT_ADIV \ |
| 138,11 → 142,12 |
| | ARM_EXT_VIRT | ARM_EXT_V8) |
| /* Processors with specific extensions in the co-processor space. */ |
| #define ARM_ARCH_XSCALE ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE) |
| #define ARM_ARCH_XSCALE ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE) |
| #define ARM_ARCH_IWMMXT \ |
| ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT) |
| ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT) |
| #define ARM_ARCH_IWMMXT2 \ |
| ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT | ARM_CEXT_IWMMXT2) |
| ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT \ |
| | ARM_CEXT_IWMMXT2) |
| #define FPU_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE) |
| #define FPU_VFP_V1 (FPU_VFP_V1xD | FPU_VFP_EXT_V1) |
| 153,7 → 158,9 |
| #define FPU_VFP_V4D16 (FPU_VFP_V3D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) |
| #define FPU_VFP_V4 (FPU_VFP_V3 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) |
| #define FPU_VFP_V4_SP_D16 (FPU_VFP_V3xD | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) |
| #define FPU_VFP_ARMV8 (FPU_VFP_V4 | FPU_VFP_EXT_ARMV8) |
| #define FPU_VFP_V5D16 (FPU_VFP_V4D16 | FPU_VFP_EXT_ARMV8xD | FPU_VFP_EXT_ARMV8) |
| #define FPU_VFP_V5_SP_D16 (FPU_VFP_V4_SP_D16 | FPU_VFP_EXT_ARMV8xD) |
| #define FPU_VFP_ARMV8 (FPU_VFP_V4 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD) |
| #define FPU_NEON_ARMV8 (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA | FPU_NEON_EXT_ARMV8) |
| #define FPU_CRYPTO_ARMV8 (FPU_CRYPTO_EXT_ARMV8) |
| #define FPU_VFP_HARD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \ |
| 162,126 → 169,183 |
| #define FPU_FPA (FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2) |
| /* Deprecated. */ |
| #define FPU_ARCH_VFP ARM_FEATURE (0, FPU_ENDIAN_PURE) |
| #define FPU_ARCH_VFP ARM_FEATURE_COPROC (FPU_ENDIAN_PURE) |
| #define FPU_ARCH_FPE ARM_FEATURE (0, FPU_FPA_EXT_V1) |
| #define FPU_ARCH_FPA ARM_FEATURE (0, FPU_FPA) |
| #define FPU_ARCH_FPE ARM_FEATURE_COPROC (FPU_FPA_EXT_V1) |
| #define FPU_ARCH_FPA ARM_FEATURE_COPROC (FPU_FPA) |
| #define FPU_ARCH_VFP_V1xD ARM_FEATURE (0, FPU_VFP_V1xD) |
| #define FPU_ARCH_VFP_V1 ARM_FEATURE (0, FPU_VFP_V1) |
| #define FPU_ARCH_VFP_V2 ARM_FEATURE (0, FPU_VFP_V2) |
| #define FPU_ARCH_VFP_V3D16 ARM_FEATURE (0, FPU_VFP_V3D16) |
| #define FPU_ARCH_VFP_V1xD ARM_FEATURE_COPROC (FPU_VFP_V1xD) |
| #define FPU_ARCH_VFP_V1 ARM_FEATURE_COPROC (FPU_VFP_V1) |
| #define FPU_ARCH_VFP_V2 ARM_FEATURE_COPROC (FPU_VFP_V2) |
| #define FPU_ARCH_VFP_V3D16 ARM_FEATURE_COPROC (FPU_VFP_V3D16) |
| #define FPU_ARCH_VFP_V3D16_FP16 \ |
| ARM_FEATURE (0, FPU_VFP_V3D16 | FPU_VFP_EXT_FP16) |
| #define FPU_ARCH_VFP_V3 ARM_FEATURE (0, FPU_VFP_V3) |
| #define FPU_ARCH_VFP_V3_FP16 ARM_FEATURE (0, FPU_VFP_V3 | FPU_VFP_EXT_FP16) |
| #define FPU_ARCH_VFP_V3xD ARM_FEATURE (0, FPU_VFP_V3xD) |
| #define FPU_ARCH_VFP_V3xD_FP16 ARM_FEATURE (0, FPU_VFP_V3xD | FPU_VFP_EXT_FP16) |
| #define FPU_ARCH_NEON_V1 ARM_FEATURE (0, FPU_NEON_EXT_V1) |
| ARM_FEATURE_COPROC (FPU_VFP_V3D16 | FPU_VFP_EXT_FP16) |
| #define FPU_ARCH_VFP_V3 ARM_FEATURE_COPROC (FPU_VFP_V3) |
| #define FPU_ARCH_VFP_V3_FP16 ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_VFP_EXT_FP16) |
| #define FPU_ARCH_VFP_V3xD ARM_FEATURE_COPROC (FPU_VFP_V3xD) |
| #define FPU_ARCH_VFP_V3xD_FP16 ARM_FEATURE_COPROC (FPU_VFP_V3xD \ |
| | FPU_VFP_EXT_FP16) |
| #define FPU_ARCH_NEON_V1 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1) |
| #define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \ |
| ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1) |
| ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1) |
| #define FPU_ARCH_NEON_FP16 \ |
| ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_FP16) |
| #define FPU_ARCH_VFP_HARD ARM_FEATURE (0, FPU_VFP_HARD) |
| #define FPU_ARCH_VFP_V4 ARM_FEATURE(0, FPU_VFP_V4) |
| #define FPU_ARCH_VFP_V4D16 ARM_FEATURE(0, FPU_VFP_V4D16) |
| #define FPU_ARCH_VFP_V4_SP_D16 ARM_FEATURE(0, FPU_VFP_V4_SP_D16) |
| ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_FP16) |
| #define FPU_ARCH_VFP_HARD ARM_FEATURE_COPROC (FPU_VFP_HARD) |
| #define FPU_ARCH_VFP_V4 ARM_FEATURE_COPROC (FPU_VFP_V4) |
| #define FPU_ARCH_VFP_V4D16 ARM_FEATURE_COPROC (FPU_VFP_V4D16) |
| #define FPU_ARCH_VFP_V4_SP_D16 ARM_FEATURE_COPROC (FPU_VFP_V4_SP_D16) |
| #define FPU_ARCH_VFP_V5D16 ARM_FEATURE_COPROC (FPU_VFP_V5D16) |
| #define FPU_ARCH_VFP_V5_SP_D16 ARM_FEATURE_COPROC (FPU_VFP_V5_SP_D16) |
| #define FPU_ARCH_NEON_VFP_V4 \ |
| ARM_FEATURE(0, FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA) |
| #define FPU_ARCH_VFP_ARMV8 ARM_FEATURE(0, FPU_VFP_ARMV8) |
| #define FPU_ARCH_NEON_VFP_ARMV8 ARM_FEATURE(0, FPU_NEON_ARMV8 | FPU_VFP_ARMV8) |
| ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA) |
| #define FPU_ARCH_VFP_ARMV8 ARM_FEATURE_COPROC (FPU_VFP_ARMV8) |
| #define FPU_ARCH_NEON_VFP_ARMV8 ARM_FEATURE_COPROC (FPU_NEON_ARMV8 \ |
| | FPU_VFP_ARMV8) |
| #define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8 \ |
| ARM_FEATURE(0, FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8) |
| #define ARCH_CRC_ARMV8 ARM_FEATURE(0, CRC_EXT_ARMV8) |
| ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8) |
| #define ARCH_CRC_ARMV8 ARM_FEATURE_COPROC (CRC_EXT_ARMV8) |
| #define FPU_ARCH_NEON_VFP_ARMV8_1 \ |
| ARM_FEATURE_COPROC (FPU_NEON_ARMV8 \ |
| | FPU_VFP_ARMV8 \ |
| | FPU_NEON_EXT_RDMA) |
| #define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1 \ |
| ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8 \ |
| | FPU_NEON_EXT_RDMA) |
| #define FPU_ARCH_ENDIAN_PURE ARM_FEATURE (0, FPU_ENDIAN_PURE) |
| #define FPU_ARCH_MAVERICK ARM_FEATURE (0, FPU_MAVERICK) |
| #define FPU_ARCH_ENDIAN_PURE ARM_FEATURE_COPROC (FPU_ENDIAN_PURE) |
| #define ARM_ARCH_V1 ARM_FEATURE (ARM_AEXT_V1, 0) |
| #define ARM_ARCH_V2 ARM_FEATURE (ARM_AEXT_V2, 0) |
| #define ARM_ARCH_V2S ARM_FEATURE (ARM_AEXT_V2S, 0) |
| #define ARM_ARCH_V3 ARM_FEATURE (ARM_AEXT_V3, 0) |
| #define ARM_ARCH_V3M ARM_FEATURE (ARM_AEXT_V3M, 0) |
| #define ARM_ARCH_V4xM ARM_FEATURE (ARM_AEXT_V4xM, 0) |
| #define ARM_ARCH_V4 ARM_FEATURE (ARM_AEXT_V4, 0) |
| #define ARM_ARCH_V4TxM ARM_FEATURE (ARM_AEXT_V4TxM, 0) |
| #define ARM_ARCH_V4T ARM_FEATURE (ARM_AEXT_V4T, 0) |
| #define ARM_ARCH_V5xM ARM_FEATURE (ARM_AEXT_V5xM, 0) |
| #define ARM_ARCH_V5 ARM_FEATURE (ARM_AEXT_V5, 0) |
| #define ARM_ARCH_V5TxM ARM_FEATURE (ARM_AEXT_V5TxM, 0) |
| #define ARM_ARCH_V5T ARM_FEATURE (ARM_AEXT_V5T, 0) |
| #define ARM_ARCH_V5TExP ARM_FEATURE (ARM_AEXT_V5TExP, 0) |
| #define ARM_ARCH_V5TE ARM_FEATURE (ARM_AEXT_V5TE, 0) |
| #define ARM_ARCH_V5TEJ ARM_FEATURE (ARM_AEXT_V5TEJ, 0) |
| #define ARM_ARCH_V6 ARM_FEATURE (ARM_AEXT_V6, 0) |
| #define ARM_ARCH_V6K ARM_FEATURE (ARM_AEXT_V6K, 0) |
| #define ARM_ARCH_V6Z ARM_FEATURE (ARM_AEXT_V6Z, 0) |
| #define ARM_ARCH_V6ZK ARM_FEATURE (ARM_AEXT_V6ZK, 0) |
| #define ARM_ARCH_V6T2 ARM_FEATURE (ARM_AEXT_V6T2, 0) |
| #define ARM_ARCH_V6KT2 ARM_FEATURE (ARM_AEXT_V6KT2, 0) |
| #define ARM_ARCH_V6ZT2 ARM_FEATURE (ARM_AEXT_V6ZT2, 0) |
| #define ARM_ARCH_V6ZKT2 ARM_FEATURE (ARM_AEXT_V6ZKT2, 0) |
| #define ARM_ARCH_V6M ARM_FEATURE (ARM_AEXT_V6M, 0) |
| #define ARM_ARCH_V6SM ARM_FEATURE (ARM_AEXT_V6SM, 0) |
| #define ARM_ARCH_V7 ARM_FEATURE (ARM_AEXT_V7, 0) |
| #define ARM_ARCH_V7A ARM_FEATURE (ARM_AEXT_V7A, 0) |
| #define ARM_ARCH_V7VE ARM_FEATURE (ARM_AEXT_V7VE, 0) |
| #define ARM_ARCH_V7R ARM_FEATURE (ARM_AEXT_V7R, 0) |
| #define ARM_ARCH_V7M ARM_FEATURE (ARM_AEXT_V7M, 0) |
| #define ARM_ARCH_V7EM ARM_FEATURE (ARM_AEXT_V7EM, 0) |
| #define ARM_ARCH_V8A ARM_FEATURE (ARM_AEXT_V8A, 0) |
| #define FPU_ARCH_MAVERICK ARM_FEATURE_COPROC (FPU_MAVERICK) |
| #define ARM_ARCH_V1 ARM_FEATURE_CORE_LOW (ARM_AEXT_V1) |
| #define ARM_ARCH_V2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V2) |
| #define ARM_ARCH_V2S ARM_FEATURE_CORE_LOW (ARM_AEXT_V2S) |
| #define ARM_ARCH_V3 ARM_FEATURE_CORE_LOW (ARM_AEXT_V3) |
| #define ARM_ARCH_V3M ARM_FEATURE_CORE_LOW (ARM_AEXT_V3M) |
| #define ARM_ARCH_V4xM ARM_FEATURE_CORE_LOW (ARM_AEXT_V4xM) |
| #define ARM_ARCH_V4 ARM_FEATURE_CORE_LOW (ARM_AEXT_V4) |
| #define ARM_ARCH_V4TxM ARM_FEATURE_CORE_LOW (ARM_AEXT_V4TxM) |
| #define ARM_ARCH_V4T ARM_FEATURE_CORE_LOW (ARM_AEXT_V4T) |
| #define ARM_ARCH_V5xM ARM_FEATURE_CORE_LOW (ARM_AEXT_V5xM) |
| #define ARM_ARCH_V5 ARM_FEATURE_CORE_LOW (ARM_AEXT_V5) |
| #define ARM_ARCH_V5TxM ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TxM) |
| #define ARM_ARCH_V5T ARM_FEATURE_CORE_LOW (ARM_AEXT_V5T) |
| #define ARM_ARCH_V5TExP ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TExP) |
| #define ARM_ARCH_V5TE ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TE) |
| #define ARM_ARCH_V5TEJ ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TEJ) |
| #define ARM_ARCH_V6 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6) |
| #define ARM_ARCH_V6K ARM_FEATURE_CORE_LOW (ARM_AEXT_V6K) |
| #define ARM_ARCH_V6Z ARM_FEATURE_CORE_LOW (ARM_AEXT_V6Z) |
| #define ARM_ARCH_V6KZ ARM_FEATURE_CORE_LOW (ARM_AEXT_V6KZ) |
| #define ARM_ARCH_V6T2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6T2) |
| #define ARM_ARCH_V6KT2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6KT2) |
| #define ARM_ARCH_V6ZT2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6ZT2) |
| #define ARM_ARCH_V6KZT2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6KZT2) |
| #define ARM_ARCH_V6M ARM_FEATURE_CORE_LOW (ARM_AEXT_V6M) |
| #define ARM_ARCH_V6SM ARM_FEATURE_CORE_LOW (ARM_AEXT_V6SM) |
| #define ARM_ARCH_V7 ARM_FEATURE_CORE_LOW (ARM_AEXT_V7) |
| #define ARM_ARCH_V7A ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A) |
| #define ARM_ARCH_V7VE ARM_FEATURE_CORE_LOW (ARM_AEXT_V7VE) |
| #define ARM_ARCH_V7R ARM_FEATURE_CORE_LOW (ARM_AEXT_V7R) |
| #define ARM_ARCH_V7M ARM_FEATURE_CORE_LOW (ARM_AEXT_V7M) |
| #define ARM_ARCH_V7EM ARM_FEATURE_CORE_LOW (ARM_AEXT_V7EM) |
| #define ARM_ARCH_V8A ARM_FEATURE_CORE_LOW (ARM_AEXT_V8A) |
| #define ARM_ARCH_V8_1A ARM_FEATURE_CORE (ARM_AEXT_V8A, ARM_EXT2_PAN) |
| /* Some useful combinations: */ |
| #define ARM_ARCH_NONE ARM_FEATURE (0, 0) |
| #define FPU_NONE ARM_FEATURE (0, 0) |
| #define ARM_ANY ARM_FEATURE (-1, 0) /* Any basic core. */ |
| #define FPU_ANY_HARD ARM_FEATURE (0, FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK) |
| #define ARM_ARCH_THUMB2 ARM_FEATURE (ARM_EXT_V6T2 | ARM_EXT_V7 | ARM_EXT_V7A | ARM_EXT_V7R | ARM_EXT_V7M | ARM_EXT_DIV, 0) |
| #define ARM_ARCH_NONE ARM_FEATURE_LOW (0, 0) |
| #define FPU_NONE ARM_FEATURE_LOW (0, 0) |
| #define ARM_ANY ARM_FEATURE (-1, -1, 0) /* Any basic core. */ |
| #define ARM_FEATURE_ALL ARM_FEATURE (-1, -1, -1)/* All CPU and FPU features. */ |
| #define FPU_ANY_HARD ARM_FEATURE_COPROC (FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK) |
| #define ARM_ARCH_THUMB2 ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2 | ARM_EXT_V7 \ |
| | ARM_EXT_V7A | ARM_EXT_V7R \ |
| | ARM_EXT_V7M | ARM_EXT_DIV \ |
| | ARM_EXT_V8) |
| /* v7-a+sec. */ |
| #define ARM_ARCH_V7A_SEC ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_SEC, 0) |
| #define ARM_ARCH_V7A_SEC ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A | ARM_EXT_SEC) |
| /* v7-a+mp+sec. */ |
| #define ARM_ARCH_V7A_MP_SEC \ |
| ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, \ |
| 0) |
| ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC) |
| /* v7-r+idiv. */ |
| #define ARM_ARCH_V7R_IDIV ARM_FEATURE (ARM_AEXT_V7R | ARM_EXT_ADIV, 0) |
| #define ARM_ARCH_V7R_IDIV ARM_FEATURE_CORE_LOW (ARM_AEXT_V7R | ARM_EXT_ADIV) |
| /* Features that are present in v6M and v6S-M but not other v6 cores. */ |
| #define ARM_ARCH_V6M_ONLY ARM_FEATURE (ARM_AEXT_V6M_ONLY, 0) |
| #define ARM_ARCH_V6M_ONLY ARM_FEATURE_CORE_LOW (ARM_AEXT_V6M_ONLY) |
| /* v8-a+fp. */ |
| #define ARM_ARCH_V8A_FP ARM_FEATURE (ARM_AEXT_V8A, FPU_ARCH_VFP_ARMV8) |
| #define ARM_ARCH_V8A_FP ARM_FEATURE_LOW (ARM_AEXT_V8A, FPU_ARCH_VFP_ARMV8) |
| /* v8-a+simd (implies fp). */ |
| #define ARM_ARCH_V8A_SIMD ARM_FEATURE (ARM_AEXT_V8A, \ |
| #define ARM_ARCH_V8A_SIMD ARM_FEATURE_LOW (ARM_AEXT_V8A, \ |
| FPU_ARCH_NEON_VFP_ARMV8) |
| /* v8-a+crypto (implies simd+fp). */ |
| #define ARM_ARCH_V8A_CRYPTOV1 ARM_FEATURE (ARM_AEXT_V8A, \ |
| #define ARM_ARCH_V8A_CRYPTOV1 ARM_FEATURE_LOW (ARM_AEXT_V8A, \ |
| FPU_ARCH_CRYPTO_NEON_VFP_ARMV8) |
| /* v8.1-a+fp. */ |
| #define ARM_ARCH_V8_1A_FP ARM_FEATURE (ARM_AEXT_V8A, ARM_EXT2_PAN, \ |
| FPU_ARCH_VFP_ARMV8) |
| /* v8.1-a+simd (implies fp). */ |
| #define ARM_ARCH_V8_1A_SIMD ARM_FEATURE (ARM_AEXT_V8A, ARM_EXT2_PAN, \ |
| FPU_ARCH_NEON_VFP_ARMV8_1) |
| /* v8.1-a+crypto (implies simd+fp). */ |
| #define ARM_ARCH_V8_1A_CRYPTOV1 ARM_FEATURE (ARM_AEXT_V8A, ARM_EXT2_PAN, \ |
| FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1) |
| /* There are too many feature bits to fit in a single word, so use a |
| structure. For simplicity we put all core features in one word and |
| everything else in the other. */ |
| structure. For simplicity we put all core features in array CORE |
| and everything else in the other. All the bits in element core[0] |
| have been occupied, so new feature should use bit in element core[1] |
| and use macro ARM_FEATURE to initialize the feature set variable. */ |
| typedef struct |
| { |
| unsigned long core; |
| unsigned long core[2]; |
| unsigned long coproc; |
| } arm_feature_set; |
| #define ARM_CPU_HAS_FEATURE(CPU,FEAT) \ |
| (((CPU).core & (FEAT).core) != 0 || ((CPU).coproc & (FEAT).coproc) != 0) |
| (((CPU).core[0] & (FEAT).core[0]) != 0 \ |
| || ((CPU).core[1] & (FEAT).core[1]) != 0 \ |
| || ((CPU).coproc & (FEAT).coproc) != 0) |
| #define ARM_CPU_IS_ANY(CPU) \ |
| ((CPU).core == ((arm_feature_set)ARM_ANY).core) |
| ((CPU).core[0] == ((arm_feature_set)ARM_ANY).core[0] \ |
| && (CPU).core[1] == ((arm_feature_set)ARM_ANY).core[1]) |
| #define ARM_MERGE_FEATURE_SETS(TARG,F1,F2) \ |
| do { \ |
| (TARG).core = (F1).core | (F2).core; \ |
| (TARG).core[0] = (F1).core[0] | (F2).core[0];\ |
| (TARG).core[1] = (F1).core[1] | (F2).core[1];\ |
| (TARG).coproc = (F1).coproc | (F2).coproc; \ |
| } while (0) |
| #define ARM_CLEAR_FEATURE(TARG,F1,F2) \ |
| do { \ |
| (TARG).core = (F1).core &~ (F2).core; \ |
| (TARG).core[0] = (F1).core[0] &~ (F2).core[0];\ |
| (TARG).core[1] = (F1).core[1] &~ (F2).core[1];\ |
| (TARG).coproc = (F1).coproc &~ (F2).coproc; \ |
| } while (0) |
| #define ARM_FEATURE(core, coproc) {(core), (coproc)} |
| #define ARM_FEATURE_COPY(F1, F2) \ |
| do { \ |
| (F1).core[0] = (F2).core[0]; \ |
| (F1).core[1] = (F2).core[1]; \ |
| (F1).coproc = (F2).coproc; \ |
| } while (0) |
| #define ARM_FEATURE_EQUAL(T1,T2) \ |
| ((T1).core[0] == (T2).core[0] \ |
| && (T1).core[1] == (T2).core[1] \ |
| && (T1).coproc == (T2).coproc) |
| #define ARM_FEATURE_ZERO(T) \ |
| ((T).core[0] == 0 && (T).core[1] == 0 && (T).coproc == 0) |
| #define ARM_FEATURE_CORE_EQUAL(T1, T2) \ |
| ((T1).core[0] == (T2).core[0] && (T1).core[1] == (T2).core[1]) |
| #define ARM_FEATURE_LOW(core, coproc) {{(core), 0}, (coproc)} |
| #define ARM_FEATURE_CORE(core1, core2) {{(core1), (core2)}, 0} |
| #define ARM_FEATURE_CORE_LOW(core) {{(core), 0}, 0} |
| #define ARM_FEATURE_CORE_HIGH(core) {{0, (core)}, 0} |
| #define ARM_FEATURE_COPROC(coproc) {{0, 0}, (coproc)} |
| #define ARM_FEATURE(core1, core2, coproc) {{(core1), (core2)}, (coproc)} |
| /contrib/toolchain/binutils/include/opcode/avr.h |
|---|
| 1,6 → 1,6 |
| /* Opcode table for the Atmel AVR micro controllers. |
| Copyright 2000, 2001, 2004, 2006, 2008, 2010, 2012 Free Software Foundation, Inc. |
| Copyright (C) 2000-2015 Free Software Foundation, Inc. |
| Contributed by Denis Chertykov <denisc@overta.ru> |
| This program is free software; you can redistribute it and/or modify |
| 22,6 → 22,7 |
| #define AVR_ISA_LPM 0x0002 /* device has LPM */ |
| #define AVR_ISA_LPMX 0x0004 /* device has LPM Rd,Z[+] */ |
| #define AVR_ISA_SRAM 0x0008 /* device has SRAM (LD, ST, PUSH, POP, ...) */ |
| #define AVR_ISA_TINY 0x0010 /* device has Tiny core specific encodings */ |
| #define AVR_ISA_MEGA 0x0020 /* device has >8K program memory (JMP and CALL |
| supported, no 8K wrap on RJMP and RCALL) */ |
| #define AVR_ISA_MUL 0x0040 /* device has new core (MUL, FMUL, ...) */ |
| 37,6 → 38,7 |
| #define AVR_ISA_TINY1 (AVR_ISA_1200 | AVR_ISA_LPM) |
| #define AVR_ISA_2xxx (AVR_ISA_TINY1 | AVR_ISA_SRAM) |
| #define AVR_ISA_2xxxa (AVR_ISA_1200 | AVR_ISA_SRAM) |
| /* For the attiny26 which is missing LPM Rd,Z+. */ |
| #define AVR_ISA_2xxe (AVR_ISA_2xxx | AVR_ISA_LPMX) |
| #define AVR_ISA_RF401 (AVR_ISA_2xxx | AVR_ISA_MOVW | AVR_ISA_LPMX) |
| 72,6 → 74,9 |
| AVR_ISA_ELPM | AVR_ISA_ELPMX | AVR_ISA_SPM | \ |
| AVR_ISA_BRK | AVR_ISA_EIND | AVR_ISA_MOVW) |
| #define AVR_ISA_AVRTINY (AVR_ISA_1200 | AVR_ISA_BRK | AVR_ISA_SRAM | \ |
| AVR_ISA_TINY) |
| #define REGISTER_P(x) ((x) == 'r' \ |
| || (x) == 'd' \ |
| || (x) == 'w' \ |
| 94,7 → 99,7 |
| `ld r,b' or `st b,r' respectively - next opcode entry)? */ |
| #define AVR_DISP0_P(x) (((x) & 0xFC07) == 0x8000) |
| /* constraint letters |
| /* Constraint letters: |
| r - any register |
| d - `ldi' register (r16-r31) |
| v - `movw' even register (r0, r2, ..., r28, r30) |
| 110,6 → 115,7 |
| p - Port address value from 0 to 31. (cbi, sbi, sbic, sbis) |
| K - immediate value from 0 to 63 (used in `adiw', `sbiw') |
| i - immediate value |
| j - 7 bit immediate value from 0x40 to 0xBF (for 16-bit 'lds'/'sts') |
| l - signed pc relative offset from -64 to 63 |
| L - signed pc relative offset from -2048 to 2047 |
| h - absolute code address (call, jmp) |
| 160,8 → 166,8 |
| AVR_INSN (bclr, "S", "100101001SSS1000", 1, AVR_ISA_1200, 0x9488) |
| AVR_INSN (bset, "S", "100101000SSS1000", 1, AVR_ISA_1200, 0x9408) |
| AVR_INSN (icall,"", "1001010100001001", 1, AVR_ISA_2xxx, 0x9509) |
| AVR_INSN (ijmp, "", "1001010000001001", 1, AVR_ISA_2xxx, 0x9409) |
| AVR_INSN (icall,"", "1001010100001001", 1, AVR_ISA_2xxxa,0x9509) |
| AVR_INSN (ijmp, "", "1001010000001001", 1, AVR_ISA_2xxxa,0x9409) |
| AVR_INSN (lpm, "?", "1001010111001000", 1, AVR_ISA_TINY1,0x95c8) |
| AVR_INSN (lpm, "r,z", "1001000ddddd010+", 1, AVR_ISA_LPMX, 0x9004) |
| 261,8 → 267,8 |
| AVR_INSN (inc, "r", "1001010rrrrr0011", 1, AVR_ISA_1200, 0x9403) |
| AVR_INSN (lsr, "r", "1001010rrrrr0110", 1, AVR_ISA_1200, 0x9406) |
| AVR_INSN (neg, "r", "1001010rrrrr0001", 1, AVR_ISA_1200, 0x9401) |
| AVR_INSN (pop, "r", "1001000rrrrr1111", 1, AVR_ISA_2xxx, 0x900f) |
| AVR_INSN (push, "r", "1001001rrrrr1111", 1, AVR_ISA_2xxx, 0x920f) |
| AVR_INSN (pop, "r", "1001000rrrrr1111", 1, AVR_ISA_2xxxa,0x900f) |
| AVR_INSN (push, "r", "1001001rrrrr1111", 1, AVR_ISA_2xxxa,0x920f) |
| AVR_INSN (ror, "r", "1001010rrrrr0111", 1, AVR_ISA_1200, 0x9407) |
| AVR_INSN (swap, "r", "1001010rrrrr0010", 1, AVR_ISA_1200, 0x9402) |
| 280,7 → 286,9 |
| AVR_INSN (fmuls,"a,a", "000000111ddd0rrr", 1, AVR_ISA_MUL, 0x0380) |
| AVR_INSN (fmulsu,"a,a","000000111ddd1rrr", 1, AVR_ISA_MUL, 0x0388) |
| AVR_INSN (sts, "j,d", "10101kkkddddkkkk", 1, AVR_ISA_TINY, 0xA800) |
| AVR_INSN (sts, "i,r", "1001001ddddd0000", 2, AVR_ISA_2xxx, 0x9200) |
| AVR_INSN (lds, "d,j", "10100kkkddddkkkk", 1, AVR_ISA_TINY, 0xA000) |
| AVR_INSN (lds, "r,i", "1001000ddddd0000", 2, AVR_ISA_2xxx, 0x9000) |
| /* Special case for b+0, `e' must be next entry after `b', |
| 295,6 → 303,6 |
| AVR_INSN (eicall, "", "1001010100011001", 1, AVR_ISA_EIND, 0x9519) |
| AVR_INSN (eijmp, "", "1001010000011001", 1, AVR_ISA_EIND, 0x9419) |
| /* DES instruction for encryption and decryption */ |
| /* DES instruction for encryption and decryption. */ |
| AVR_INSN (des, "E", "10010100EEEE1011", 1, AVR_ISA_DES, 0x940B) |
| /contrib/toolchain/binutils/include/opcode/bfin.h |
|---|
| 1,5 → 1,5 |
| /* bfin.h -- Header file for ADI Blackfin opcode table |
| Copyright 2005, 2010, 2011 Free Software Foundation, Inc. |
| Copyright (C) 2005-2015 Free Software Foundation, Inc. |
| This file is part of GDB, GAS, and the GNU binutils. |
| /contrib/toolchain/binutils/include/opcode/cgen.h |
|---|
| 1,7 → 1,6 |
| /* Header file for targets using CGEN: Cpu tools GENerator. |
| Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2009, 2010 |
| Free Software Foundation, Inc. |
| Copyright (C) 1996-2015 Free Software Foundation, Inc. |
| This file is part of GDB, the GNU debugger, and the GNU Binutils. |
| 28,6 → 27,10 |
| /* ??? IWBN to replace bfd in the name. */ |
| #include "bfd_stdint.h" |
| #ifdef __cplusplus |
| extern "C" { |
| #endif |
| /* ??? This file requires bfd.h but only to get bfd_vma. |
| Seems like an awful lot to require just to get such a fundamental type. |
| Perhaps the definition of bfd_vma can be moved outside of bfd.h. |
| 1477,4 → 1480,8 |
| /* Will an error message be generated if a signed field in an instruction overflows ? */ |
| extern unsigned int cgen_signed_overflow_ok_p (CGEN_CPU_DESC); |
| #ifdef __cplusplus |
| } |
| #endif |
| #endif /* OPCODE_CGEN_H */ |
| /contrib/toolchain/binutils/include/opcode/convex.h |
|---|
| 1,5 → 1,5 |
| /* Information for instruction disassembly on the Convex. |
| Copyright 1989, 1993, 2002, 2010 Free Software Foundation, Inc. |
| Copyright (C) 1989-2015 Free Software Foundation, Inc. |
| This file is part of GDB. |
| /contrib/toolchain/binutils/include/opcode/cr16.h |
|---|
| 1,5 → 1,5 |
| /* cr16.h -- Header file for CR16 opcode and register tables. |
| Copyright 2007, 2008, 2010, 2013 Free Software Foundation, Inc. |
| Copyright (C) 2007-2015 Free Software Foundation, Inc. |
| Contributed by M R Swami Reddy |
| This file is part of GAS, GDB and the GNU binutils. |
| /contrib/toolchain/binutils/include/opcode/cris.h |
|---|
| 1,5 → 1,5 |
| /* cris.h -- Header file for CRIS opcode and register tables. |
| Copyright (C) 2000, 2001, 2004, 2010 Free Software Foundation, Inc. |
| Copyright (C) 2000-2015 Free Software Foundation, Inc. |
| Contributed by Axis Communications AB, Lund, Sweden. |
| Originally written for GAS 1.38.1 by Mikael Asker. |
| Updated, BFDized and GNUified by Hans-Peter Nilsson. |
| /contrib/toolchain/binutils/include/opcode/crx.h |
|---|
| 1,5 → 1,5 |
| /* crx.h -- Header file for CRX opcode and register tables. |
| Copyright 2004, 2010, 2012 Free Software Foundation, Inc. |
| Copyright (C) 2004-2015 Free Software Foundation, Inc. |
| Contributed by Tomer Levi, NSC, Israel. |
| Originally written for GAS 2.12 by Tomer Levi, NSC, Israel. |
| Updates, BFDizing, GNUifying and ELF support by Tomer Levi. |
| /contrib/toolchain/binutils/include/opcode/d10v.h |
|---|
| 1,6 → 1,5 |
| /* d10v.h -- Header file for D10V opcode table |
| Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2010 |
| Free Software Foundation, Inc. |
| Copyright (C) 1996-2015 Free Software Foundation, Inc. |
| Written by Martin Hunt (hunt@cygnus.com), Cygnus Support |
| This file is part of GDB, GAS, and the GNU binutils. |
| /contrib/toolchain/binutils/include/opcode/d30v.h |
|---|
| 1,6 → 1,5 |
| /* d30v.h -- Header file for D30V opcode table |
| Copyright 1997, 1998, 1999, 2000, 2001, 2003, 2010 |
| Free Software Foundation, Inc. |
| Copyright (C) 1997-2015 Free Software Foundation, Inc. |
| Written by Martin Hunt (hunt@cygnus.com), Cygnus Solutions |
| This file is part of GDB, GAS, and the GNU binutils. |
| /contrib/toolchain/binutils/include/opcode/dlx.h |
|---|
| 1,5 → 1,5 |
| /* Table of opcodes for the DLX microprocess. |
| Copyright 2002, 2010 Free Software Foundation, Inc. |
| Copyright (C) 2002-2015 Free Software Foundation, Inc. |
| This file is part of GDB and GAS. |
| /contrib/toolchain/binutils/include/opcode/ft32.h |
|---|
| 0,0 → 1,106 |
| /* Definitions for decoding the ft32 opcode table. |
| Copyright (C) 2013-2015 Free Software Foundation, Inc. |
| Contributed by FTDI (support@ftdichip.com) |
| This program is free software; you can redistribute it and/or modify |
| it under the terms of the GNU General Public License as published by |
| the Free Software Foundation; either version 2 of the License, or |
| (at your option) any later version. |
| This program is distributed in the hope that it will be useful, |
| but WITHOUT ANY WARRANTY; without even the implied warranty of |
| MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| GNU General Public License for more details. |
| You should have received a copy of the GNU General Public License |
| along with this program; if not, write to the Free Software |
| Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA |
| 02110-1301, USA. */ |
| typedef struct ft32_opc_info_t |
| { |
| const char *name; |
| int dw; |
| unsigned int mask; |
| unsigned int bits; |
| int fields; |
| } ft32_opc_info_t; |
| #define FT32_PAT_ALUOP 0x08 |
| #define FT32_PAT_LDA 0x18 |
| #define FT32_PAT_TOCI 0x01 |
| #define FT32_PAT_CMPOP 0x0b |
| #define FT32_PAT_STA 0x17 |
| #define FT32_PAT_EXA 0x07 |
| #define FT32_PAT_LDK 0x0c |
| #define FT32_PAT_FFUOP 0x1e |
| #define FT32_PAT_LDI 0x15 |
| #define FT32_PAT_STI 0x16 |
| #define FT32_PAT_EXI 0x1d |
| #define FT32_PAT_POP 0x11 |
| #define FT32_PAT_LPM 0x0d |
| #define FT32_PAT_LINK 0x12 |
| #define FT32_PAT_TOC 0x00 |
| #define FT32_PAT_PUSH 0x10 |
| #define FT32_PAT_RETURN 0x14 |
| #define FT32_PAT_UNLINK 0x13 |
| #define FT32_PAT_LPMI 0x19 |
| #define FT32_FLD_CBCRCV (1 << 0) |
| #define FT32_FLD_INT (1 << 1) |
| #define FT32_FLD_INT_BIT 26 |
| #define FT32_FLD_INT_SIZ 1 |
| #define FT32_FLD_DW (1 << 2) |
| #define FT32_FLD_DW_BIT 25 |
| #define FT32_FLD_DW_SIZ 2 |
| #define FT32_FLD_CB (1 << 3) |
| #define FT32_FLD_CB_BIT 22 |
| #define FT32_FLD_CB_SIZ 5 |
| #define FT32_FLD_R_D (1 << 4) |
| #define FT32_FLD_R_D_BIT 20 |
| #define FT32_FLD_R_D_SIZ 5 |
| #define FT32_FLD_CR (1 << 5) |
| #define FT32_FLD_CR_BIT 20 |
| #define FT32_FLD_CR_SIZ 2 |
| #define FT32_FLD_CV (1 << 6) |
| #define FT32_FLD_CV_BIT 19 |
| #define FT32_FLD_CV_SIZ 1 |
| #define FT32_FLD_BT (1 << 7) |
| #define FT32_FLD_BT_BIT 18 |
| #define FT32_FLD_BT_SIZ 1 |
| #define FT32_FLD_R_1 (1 << 8) |
| #define FT32_FLD_R_1_BIT 15 |
| #define FT32_FLD_R_1_SIZ 5 |
| #define FT32_FLD_RIMM (1 << 9) |
| #define FT32_FLD_RIMM_BIT 4 |
| #define FT32_FLD_RIMM_SIZ 11 |
| #define FT32_FLD_R_2 (1 << 10) |
| #define FT32_FLD_R_2_BIT 4 |
| #define FT32_FLD_R_2_SIZ 5 |
| #define FT32_FLD_K20 (1 << 11) |
| #define FT32_FLD_K20_BIT 0 |
| #define FT32_FLD_K20_SIZ 20 |
| #define FT32_FLD_PA (1 << 12) |
| #define FT32_FLD_PA_BIT 0 |
| #define FT32_FLD_PA_SIZ 18 |
| #define FT32_FLD_AA (1 << 13) |
| #define FT32_FLD_AA_BIT 0 |
| #define FT32_FLD_AA_SIZ 17 |
| #define FT32_FLD_K16 (1 << 14) |
| #define FT32_FLD_K16_BIT 0 |
| #define FT32_FLD_K16_SIZ 16 |
| #define FT32_FLD_K8 (1 << 15) |
| #define FT32_FLD_K8_BIT 0 |
| #define FT32_FLD_K8_SIZ 8 |
| #define FT32_FLD_AL (1 << 16) |
| #define FT32_FLD_AL_BIT 0 |
| #define FT32_FLD_AL_SIZ 4 |
| #define FT32_IS_CALL(inst) (((inst) & 0xfffc0000) == 0x00340000) |
| #define FT32_IS_PUSH(inst) (((inst) & 0xfff00000) == 0x84000000) |
| #define FT32_PUSH_REG(inst) (((inst) >> 15) & 0x1f) |
| #define FT32_IS_LINK(inst) (((inst) & 0xffff0000) == 0x95d00000) |
| #define FT32_LINK_SIZE(inst) ((inst) & 0xffff) |
| #define FT32_FLD_R_D_POST (1 << 17) |
| #define FT32_FLD_R_1_POST (1 << 18) |
| /contrib/toolchain/binutils/include/opcode/h8300.h |
|---|
| 1,5 → 1,5 |
| /* Opcode table for the H8/300 |
| Copyright 1991-2013 Free Software Foundation, Inc. |
| Copyright (C) 1991-2015 Free Software Foundation, Inc. |
| Written by Steve Chamberlain <sac@cygnus.com>. |
| This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler. |
| /contrib/toolchain/binutils/include/opcode/hppa.h |
|---|
| 1,7 → 1,5 |
| /* Table of opcodes for the PA-RISC. |
| Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, |
| 2001, 2002, 2003, 2004, 2005, 2006, 2009, 2010 |
| Free Software Foundation, Inc. |
| Copyright (C) 1990-2015 Free Software Foundation, Inc. |
| Contributed by the Center for Software Science at the |
| University of Utah (pa-gdb-bugs@cs.utah.edu). |
| /contrib/toolchain/binutils/include/opcode/i370.h |
|---|
| 1,6 → 1,5 |
| /* i370.h -- Header file for S/390 opcode table |
| Copyright 1994, 1995, 1998, 1999, 2000, 2003, 2010 |
| Free Software Foundation, Inc. |
| Copyright (C) 1994-2015 Free Software Foundation, Inc. |
| PowerPC version written by Ian Lance Taylor, Cygnus Support |
| Rewritten for i370 ESA/390 support, Linas Vepstas <linas@linas.org> |
| /contrib/toolchain/binutils/include/opcode/i386.h |
|---|
| 1,7 → 1,5 |
| /* opcode/i386.h -- Intel 80386 opcode macros |
| Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
| 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 |
| Free Software Foundation, Inc. |
| Copyright (C) 1989-2015 Free Software Foundation, Inc. |
| This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. |
| /contrib/toolchain/binutils/include/opcode/i860.h |
|---|
| 1,6 → 1,5 |
| /* Table of opcodes for the i860. |
| Copyright 1989, 1991, 2000, 2002, 2003, 2010 |
| Free Software Foundation, Inc. |
| Copyright (C) 1989-2015 Free Software Foundation, Inc. |
| This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. |
| /contrib/toolchain/binutils/include/opcode/i960.h |
|---|
| 1,6 → 1,6 |
| /* Basic 80960 instruction formats. |
| Copyright 2001-2013 Free Software Foundation, Inc. |
| Copyright (C) 2001-2015 Free Software Foundation, Inc. |
| This program is free software; you can redistribute it and/or modify |
| it under the terms of the GNU General Public License as published by |
| /contrib/toolchain/binutils/include/opcode/ia64.h |
|---|
| 1,6 → 1,5 |
| /* ia64.h -- Header file for ia64 opcode table |
| Copyright (C) 1998, 1999, 2000, 2002, 2005, 2006, 2010 |
| Free Software Foundation, Inc. |
| Copyright (C) 1998-2015 Free Software Foundation, Inc. |
| Contributed by David Mosberger-Tang <davidm@hpl.hp.com> |
| This file is part of BFD, the Binary File Descriptor library. |
| /contrib/toolchain/binutils/include/opcode/m68hc11.h |
|---|
| 1,6 → 1,5 |
| /* m68hc11.h -- Header file for Motorola 68HC11 & 68HC12 opcode table |
| Copyright 1999, 2000, 2002, 2003, 2010, 2012 |
| Free Software Foundation, Inc. |
| Copyright (C) 1999-2015 Free Software Foundation, Inc. |
| Written by Stephane Carrez (stcarrez@nerim.fr) |
| This file is part of GDB, GAS, and the GNU binutils. |
| /contrib/toolchain/binutils/include/opcode/m68k.h |
|---|
| 1,6 → 1,5 |
| /* Opcode table header for m680[01234]0/m6888[12]/m68851. |
| Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001, |
| 2003, 2004, 2006, 2010 Free Software Foundation, Inc. |
| Copyright (C) 1989-2015 Free Software Foundation, Inc. |
| This file is part of GDB, GAS, and the GNU binutils. |
| /contrib/toolchain/binutils/include/opcode/m88k.h |
|---|
| 1,6 → 1,5 |
| /* Table of opcodes for the Motorola M88k family. |
| Copyright 1989, 1990, 1991, 1993, 2001, 2002, 2010 |
| Free Software Foundation, Inc. |
| Copyright (C) 1989-2015 Free Software Foundation, Inc. |
| This file is part of GDB and GAS. |
| /contrib/toolchain/binutils/include/opcode/metag.h |
|---|
| 1,5 → 1,5 |
| /* Imagination Technologies Meta opcode table. |
| Copyright (C) 2013 Free Software Foundation, Inc. |
| Copyright (C) 2013-2015 Free Software Foundation, Inc. |
| Contributed by Imagination Technologies Ltd. |
| This file is part of GDB and GAS. |
| /contrib/toolchain/binutils/include/opcode/mips.h |
|---|
| 1,7 → 1,5 |
| /* mips.h. Mips opcode list for GDB, the GNU debugger. |
| Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
| 2003, 2004, 2005, 2008, 2009, 2010, 2013 |
| Free Software Foundation, Inc. |
| Copyright (C) 1993-2015 Free Software Foundation, Inc. |
| Contributed by Ralph Campbell and OSF |
| Commented and modified by Ian Lance Taylor, Cygnus Support |
| 413,7 → 411,23 |
| /* Like OP_VU0_SUFFIX, but used when the operand's value has already |
| been set. Any suffix used here must match the previous value. */ |
| OP_VU0_MATCH_SUFFIX |
| OP_VU0_MATCH_SUFFIX, |
| /* An index selected by an integer, e.g. [1]. */ |
| OP_IMM_INDEX, |
| /* An index selected by a register, e.g. [$2]. */ |
| OP_REG_INDEX, |
| /* The operand spans two 5-bit register fields, both of which must be set to |
| the source register. */ |
| OP_SAME_RS_RT, |
| /* Described by mips_prev_operand. */ |
| OP_CHECK_PREV, |
| /* A register operand that must not be zero. */ |
| OP_NON_ZERO_REG |
| }; |
| /* Enumerates the types of MIPS register. */ |
| 454,7 → 468,13 |
| OP_REG_R5900_I, |
| OP_REG_R5900_Q, |
| OP_REG_R5900_R, |
| OP_REG_R5900_ACC |
| OP_REG_R5900_ACC, |
| /* MSA registers $w0-$w31. */ |
| OP_REG_MSA, |
| /* MSA control registers $0-$31. */ |
| OP_REG_MSA_CTRL |
| }; |
| /* Base class for all operands. */ |
| 543,6 → 563,18 |
| const unsigned char *reg_map; |
| }; |
| /* Describes an operand that which must match a condition based on the |
| previous operand. */ |
| struct mips_check_prev_operand |
| { |
| struct mips_operand root; |
| bfd_boolean greater_than_ok; |
| bfd_boolean less_than_ok; |
| bfd_boolean equal_ok; |
| bfd_boolean zero_ok; |
| }; |
| /* Describes an operand that encodes a pair of registers. */ |
| struct mips_reg_pair_operand |
| { |
| 891,6 → 923,54 |
| Enhanced VA Scheme: |
| "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET) |
| MSA Extension: |
| "+d" 5-bit MSA register (FD) |
| "+e" 5-bit MSA register (FS) |
| "+h" 5-bit MSA register (FT) |
| "+k" 5-bit GPR at bit 6 |
| "+l" 5-bit MSA control register at bit 6 |
| "+n" 5-bit MSA control register at bit 11 |
| "+o" 4-bit vector element index at bit 16 |
| "+u" 3-bit vector element index at bit 16 |
| "+v" 2-bit vector element index at bit 16 |
| "+w" 1-bit vector element index at bit 16 |
| "+T" (-512 .. 511) << 0 at bit 16 |
| "+U" (-512 .. 511) << 1 at bit 16 |
| "+V" (-512 .. 511) << 2 at bit 16 |
| "+W" (-512 .. 511) << 3 at bit 16 |
| "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6 |
| "+!" 3 bit unsigned bit position at bit 16 |
| "+@" 4 bit unsigned bit position at bit 16 |
| "+#" 6 bit unsigned bit position at bit 16 |
| "+$" 5 bit unsigned immediate at bit 16 |
| "+%" 5 bit signed immediate at bit 16 |
| "+^" 10 bit signed immediate at bit 11 |
| "+&" 0 vector element index |
| "+*" 5-bit register vector element index at bit 16 |
| "+|" 8-bit mask at bit 16 |
| MIPS R6: |
| "+:" 11-bit mask at bit 0 |
| "+'" 26 bit PC relative branch target address |
| "+"" 21 bit PC relative branch target address |
| "+;" 5 bit same register in both OP_*_RS and OP_*_RT |
| "+I" 2bit unsigned bit position at bit 6 |
| "+O" 3bit unsigned bit position at bit 6 |
| "+R" must be program counter |
| "-a" (-262144 .. 262143) << 2 at bit 0 |
| "-b" (-131072 .. 131071) << 3 at bit 0 |
| "-d" Same as destination register GP |
| "-s" 5 bit source register specifier (OP_*_RS) not $0 |
| "-t" 5 bit source register specifier (OP_*_RT) not $0 |
| "-u" 5 bit source register specifier (OP_*_RT) greater than OP_*_RS |
| "-v" 5 bit source register specifier (OP_*_RT) not $0 not OP_*_RS |
| "-w" 5 bit source register specifier (OP_*_RT) less than or equal to OP_*_RS |
| "-x" 5 bit source register specifier (OP_*_RT) greater than or |
| equal to OP_*_RS |
| "-y" 5 bit source register specifier (OP_*_RT) not $0 less than OP_*_RS |
| "-A" symbolic offset (-262144 .. 262143) << 2 at bit 0 |
| "-B" symbolic offset (-131072 .. 131071) << 3 at bit 0 |
| Other: |
| "()" parens surrounding optional value |
| "," separates operands |
| 898,7 → 978,7 |
| Characters used so far, for quick reference when adding more: |
| "1234567890" |
| "%[]<>(),+:'@!#$*&\~" |
| "%[]<>(),+-:'@!#$*&\~" |
| "ABCDEFGHIJKLMNOPQRSTUVWXYZ" |
| "abcdefghijklopqrstuvwxz" |
| 905,8 → 985,14 |
| Extension character sequences used so far ("+" followed by the |
| following), for quick reference when adding more: |
| "1234567890" |
| "ABCEFGHJKLMNPQSXZ" |
| "abcfgijmpqrstxyz" |
| "~!@#$%^&*|:'";" |
| "ABCEFGHIJKLMNOPQRSTUVWXZ" |
| "abcdefghijklmnopqrstuvwxyz" |
| Extension character sequences used so far ("-" followed by the |
| following), for quick reference when adding more: |
| "AB" |
| "abdstuvwxy" |
| */ |
| /* These are the bits which may be set in the pinfo field of an |
| 934,10 → 1020,10 |
| #define INSN_TLB 0x00000200 |
| /* Reads coprocessor register other than floating point register. */ |
| #define INSN_COP 0x00000400 |
| /* Instruction loads value from memory, requiring delay. */ |
| #define INSN_LOAD_MEMORY_DELAY 0x00000800 |
| /* Instruction loads value from coprocessor, requiring delay. */ |
| #define INSN_LOAD_COPROC_DELAY 0x00001000 |
| /* Instruction loads value from memory. */ |
| #define INSN_LOAD_MEMORY 0x00000800 |
| /* Instruction loads value from coprocessor, (may require delay). */ |
| #define INSN_LOAD_COPROC 0x00001000 |
| /* Instruction has unconditional branch delay slot. */ |
| #define INSN_UNCOND_BRANCH_DELAY 0x00002000 |
| /* Instruction has conditional branch delay slot. */ |
| 944,8 → 1030,8 |
| #define INSN_COND_BRANCH_DELAY 0x00004000 |
| /* Conditional branch likely: if branch not taken, insn nullified. */ |
| #define INSN_COND_BRANCH_LIKELY 0x00008000 |
| /* Moves to coprocessor register, requiring delay. */ |
| #define INSN_COPROC_MOVE_DELAY 0x00010000 |
| /* Moves to coprocessor register, (may require delay). */ |
| #define INSN_COPROC_MOVE 0x00010000 |
| /* Loads coprocessor register from memory, requiring delay. */ |
| #define INSN_COPROC_MEMORY_DELAY 0x00020000 |
| /* Reads the HI register. */ |
| 1014,6 → 1100,8 |
| #define INSN2_READ_GPR_16 0x00002000 |
| /* Has an "\.x?y?z?w?" suffix based on mips_vu0_channel_mask. */ |
| #define INSN2_VU0_CHANNEL_SUFFIX 0x00004000 |
| /* Instruction has a forbidden slot. */ |
| #define INSN2_FORBIDDEN_SLOT 0x00008000 |
| /* Masks used to mark instructions to indicate which MIPS ISA level |
| they were introduced in. INSN_ISA_MASK masks an enumeration that |
| 1021,7 → 1109,7 |
| word constructed using these macros is a bitmask of the remaining |
| INSN_* values below. */ |
| #define INSN_ISA_MASK 0x0000000ful |
| #define INSN_ISA_MASK 0x0000001ful |
| /* We cannot start at zero due to ISA_UNKNOWN below. */ |
| #define INSN_ISA1 1 |
| 1031,29 → 1119,76 |
| #define INSN_ISA5 5 |
| #define INSN_ISA32 6 |
| #define INSN_ISA32R2 7 |
| #define INSN_ISA64 8 |
| #define INSN_ISA64R2 9 |
| #define INSN_ISA32R3 8 |
| #define INSN_ISA32R5 9 |
| #define INSN_ISA32R6 10 |
| #define INSN_ISA64 11 |
| #define INSN_ISA64R2 12 |
| #define INSN_ISA64R3 13 |
| #define INSN_ISA64R5 14 |
| #define INSN_ISA64R6 15 |
| /* Below this point the INSN_* values correspond to combinations of ISAs. |
| They are only for use in the opcodes table to indicate membership of |
| a combination of ISAs that cannot be expressed using the usual inclusion |
| ordering on the above INSN_* values. */ |
| #define INSN_ISA3_32 10 |
| #define INSN_ISA3_32R2 11 |
| #define INSN_ISA4_32 12 |
| #define INSN_ISA4_32R2 13 |
| #define INSN_ISA5_32R2 14 |
| #define INSN_ISA3_32 16 |
| #define INSN_ISA3_32R2 17 |
| #define INSN_ISA4_32 18 |
| #define INSN_ISA4_32R2 19 |
| #define INSN_ISA5_32R2 20 |
| /* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through |
| INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2, |
| this table describes whether at least one of the ISAs described by X |
| is/are implemented by ISA Y. (Think of Y as the ISA level supported by |
| a particular core and X as the ISA level(s) at which a certain instruction |
| is defined.) The ISA(s) described by X is/are implemented by Y iff |
| (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1 |
| is non-zero. */ |
| static const unsigned int mips_isa_table[] = |
| { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff }; |
| /* The R6 definitions shown below state that they support all previous ISAs. |
| This is not actually true as some instructions are removed in R6. |
| The problem is that the removed instructions in R6 come from different |
| ISAs. One approach to solve this would be to describe in the membership |
| field of the opcode table the different ISAs an instruction belongs to. |
| This would require us to create a large amount of different ISA |
| combinations which is hard to manage. A cleaner approach (which is |
| implemented here) is to say that R6 is an extension of R5 and then to |
| deal with the removed instructions by adding instruction exclusions |
| for R6 in the opcode table. */ |
| /* Bit INSN_ISA<X> - 1 of INSN_UPTO<Y> is set if ISA Y includes ISA X. */ |
| #define ISAF(X) (1 << (INSN_ISA##X - 1)) |
| #define INSN_UPTO1 ISAF(1) |
| #define INSN_UPTO2 INSN_UPTO1 | ISAF(2) |
| #define INSN_UPTO3 INSN_UPTO2 | ISAF(3) | ISAF(3_32) | ISAF(3_32R2) |
| #define INSN_UPTO4 INSN_UPTO3 | ISAF(4) | ISAF(4_32) | ISAF(4_32R2) |
| #define INSN_UPTO5 INSN_UPTO4 | ISAF(5) | ISAF(5_32R2) |
| #define INSN_UPTO32 INSN_UPTO2 | ISAF(32) | ISAF(3_32) | ISAF(4_32) |
| #define INSN_UPTO32R2 INSN_UPTO32 | ISAF(32R2) \ |
| | ISAF(3_32R2) | ISAF(4_32R2) | ISAF(5_32R2) |
| #define INSN_UPTO32R3 INSN_UPTO32R2 | ISAF(32R3) |
| #define INSN_UPTO32R5 INSN_UPTO32R3 | ISAF(32R5) |
| #define INSN_UPTO32R6 INSN_UPTO32R5 | ISAF(32R6) |
| #define INSN_UPTO64 INSN_UPTO5 | ISAF(64) | ISAF(32) |
| #define INSN_UPTO64R2 INSN_UPTO64 | ISAF(64R2) | ISAF(32R2) |
| #define INSN_UPTO64R3 INSN_UPTO64R2 | ISAF(64R3) | ISAF(32R3) |
| #define INSN_UPTO64R5 INSN_UPTO64R3 | ISAF(64R5) | ISAF(32R5) |
| #define INSN_UPTO64R6 INSN_UPTO64R5 | ISAF(64R6) | ISAF(32R6) |
| /* The same information in table form: bit INSN_ISA<X> - 1 of index |
| INSN_UPTO<Y> - 1 is set if ISA Y includes ISA X. */ |
| static const unsigned int mips_isa_table[] = { |
| INSN_UPTO1, |
| INSN_UPTO2, |
| INSN_UPTO3, |
| INSN_UPTO4, |
| INSN_UPTO5, |
| INSN_UPTO32, |
| INSN_UPTO32R2, |
| INSN_UPTO32R3, |
| INSN_UPTO32R5, |
| INSN_UPTO32R6, |
| INSN_UPTO64, |
| INSN_UPTO64R2, |
| INSN_UPTO64R3, |
| INSN_UPTO64R5, |
| INSN_UPTO64R6 |
| }; |
| #undef ISAF |
| /* Masks used for Chip specific instructions. */ |
| #define INSN_CHIP_MASK 0xc3ff0f20 |
| 1061,6 → 1196,7 |
| #define INSN_OCTEON 0x00000800 |
| #define INSN_OCTEONP 0x00000200 |
| #define INSN_OCTEON2 0x00000100 |
| #define INSN_OCTEON3 0x00000040 |
| /* MIPS R5900 instruction */ |
| #define INSN_5900 0x00004000 |
| 1115,6 → 1251,11 |
| /* Virtualization ASE */ |
| #define ASE_VIRT 0x00000200 |
| #define ASE_VIRT64 0x00000400 |
| /* MSA Extension */ |
| #define ASE_MSA 0x00000800 |
| #define ASE_MSA64 0x00001000 |
| /* eXtended Physical Address (XPA) Extension. */ |
| #define ASE_XPA 0x00002000 |
| /* MIPS ISA defines, use instead of hardcoding ISA level. */ |
| 1129,8 → 1270,14 |
| #define ISA_MIPS64 INSN_ISA64 |
| #define ISA_MIPS32R2 INSN_ISA32R2 |
| #define ISA_MIPS32R3 INSN_ISA32R3 |
| #define ISA_MIPS32R5 INSN_ISA32R5 |
| #define ISA_MIPS64R2 INSN_ISA64R2 |
| #define ISA_MIPS64R3 INSN_ISA64R3 |
| #define ISA_MIPS64R5 INSN_ISA64R5 |
| #define ISA_MIPS32R6 INSN_ISA32R6 |
| #define ISA_MIPS64R6 INSN_ISA64R6 |
| /* CPU defines, use instead of hardcoding processor number. Keep this |
| in sync with bfd/archures.c in order for machine selection to work. */ |
| 1161,9 → 1308,15 |
| #define CPU_MIPS16 16 |
| #define CPU_MIPS32 32 |
| #define CPU_MIPS32R2 33 |
| #define CPU_MIPS32R3 34 |
| #define CPU_MIPS32R5 36 |
| #define CPU_MIPS32R6 37 |
| #define CPU_MIPS5 5 |
| #define CPU_MIPS64 64 |
| #define CPU_MIPS64R2 65 |
| #define CPU_MIPS64R3 66 |
| #define CPU_MIPS64R5 68 |
| #define CPU_MIPS64R6 69 |
| #define CPU_SB1 12310201 /* octal 'SB', 01. */ |
| #define CPU_LOONGSON_2E 3001 |
| #define CPU_LOONGSON_2F 3002 |
| 1171,6 → 1324,7 |
| #define CPU_OCTEON 6501 |
| #define CPU_OCTEONP 6601 |
| #define CPU_OCTEON2 6502 |
| #define CPU_OCTEON3 6503 |
| #define CPU_XLR 887682 /* decimal 'XLR' */ |
| /* Return true if the given CPU is included in INSN_* mask MASK. */ |
| 1236,9 → 1390,19 |
| case CPU_OCTEON2: |
| return (mask & INSN_OCTEON2) != 0; |
| case CPU_OCTEON3: |
| return (mask & INSN_OCTEON3) != 0; |
| case CPU_XLR: |
| return (mask & INSN_XLR) != 0; |
| case CPU_MIPS32R6: |
| return (mask & INSN_ISA_MASK) == INSN_ISA32R6; |
| case CPU_MIPS64R6: |
| return ((mask & INSN_ISA_MASK) == INSN_ISA32R6) |
| || ((mask & INSN_ISA_MASK) == INSN_ISA64R6); |
| default: |
| return FALSE; |
| } |
| 1976,7 → 2140,6 |
| "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3) |
| "z" must be zero register |
| "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ) |
| "B" 10-bit syscall/wait function code (MICROMIPSOP_*_CODE10) |
| "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS) |
| "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes |
| 2001,6 → 2164,8 |
| "+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD). |
| Requires that "+A" or "+E" occur first to set position. |
| Enforces: 32 < (pos+size) <= 64. |
| "+J" 10-bit SYSCALL/WAIT/SDBBP/HYPCALL function code |
| (MICROMIPSOP_*_CODE10) |
| PC-relative addition (ADDIUPC) instruction: |
| "mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ) |
| 2044,6 → 2209,33 |
| microMIPS Enhanced VA Scheme: |
| "+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET) |
| MSA Extension: |
| "+d" 5-bit MSA register (FD) |
| "+e" 5-bit MSA register (FS) |
| "+h" 5-bit MSA register (FT) |
| "+k" 5-bit GPR at bit 6 |
| "+l" 5-bit MSA control register at bit 6 |
| "+n" 5-bit MSA control register at bit 11 |
| "+o" 4-bit vector element index at bit 16 |
| "+u" 3-bit vector element index at bit 16 |
| "+v" 2-bit vector element index at bit 16 |
| "+w" 1-bit vector element index at bit 16 |
| "+x" 5-bit shift amount at bit 16 |
| "+T" (-512 .. 511) << 0 at bit 16 |
| "+U" (-512 .. 511) << 1 at bit 16 |
| "+V" (-512 .. 511) << 2 at bit 16 |
| "+W" (-512 .. 511) << 3 at bit 16 |
| "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6 |
| "+!" 3 bit unsigned bit position at bit 16 |
| "+@" 4 bit unsigned bit position at bit 16 |
| "+#" 6 bit unsigned bit position at bit 16 |
| "+$" 5 bit unsigned immediate at bit 16 |
| "+%" 5 bit signed immediate at bit 16 |
| "+^" 10 bit signed immediate at bit 11 |
| "+&" 0 vector element index |
| "+*" 5-bit register vector element index at bit 16 |
| "+|" 8-bit mask at bit 16 |
| Other: |
| "()" parens surrounding optional value |
| "," separates operands |
| 2052,7 → 2244,7 |
| Characters used so far, for quick reference when adding more: |
| "12345678 0" |
| "<>(),+.@\^|~" |
| "<>(),+-.@\^|~" |
| "ABCDEFGHI KLMN RST V " |
| "abcd f hijklmnopqrstuvw yz" |
| 2059,9 → 2251,9 |
| Extension character sequences used so far ("+" followed by the |
| following), for quick reference when adding more: |
| "" |
| "" |
| "ABCEFGH" |
| "ij" |
| "~!@#$%^&*|" |
| "ABCEFGHJTUVW" |
| "dehijklnouvwx" |
| Extension character sequences used so far ("m" followed by the |
| following), for quick reference when adding more: |
| 2069,6 → 2261,12 |
| "" |
| " BCDEFGHIJ LMNOPQ U WXYZ" |
| " bcdefghij lmn pq st xyz" |
| Extension character sequences used so far ("-" followed by the |
| following), for quick reference when adding more: |
| "" |
| "" |
| <none so far> |
| */ |
| extern const struct mips_operand *decode_micromips_operand (const char *); |
| /contrib/toolchain/binutils/include/opcode/mmix.h |
|---|
| 1,5 → 1,5 |
| /* mmix.h -- Header file for MMIX opcode table |
| Copyright (C) 2001, 2003, 2010 Free Software Foundation, Inc. |
| Copyright (C) 2001-2015 Free Software Foundation, Inc. |
| Written by Hans-Peter Nilsson (hp@bitrange.com) |
| This file is part of GDB, GAS, and the GNU binutils. |
| /contrib/toolchain/binutils/include/opcode/mn10200.h |
|---|
| 1,5 → 1,5 |
| /* mn10200.h -- Header file for Matsushita 10200 opcode table |
| Copyright 1996, 1997, 2010 Free Software Foundation, Inc. |
| Copyright (C) 1996-2015 Free Software Foundation, Inc. |
| Written by Jeff Law, Cygnus Support |
| This file is part of GDB, GAS, and the GNU binutils. |
| /contrib/toolchain/binutils/include/opcode/mn10300.h |
|---|
| 1,5 → 1,5 |
| /* mn10300.h -- Header file for Matsushita 10300 opcode table |
| Copyright 1996, 1997, 1998, 1999, 2003, 2010 Free Software Foundation, Inc. |
| Copyright (C) 1996-2015 Free Software Foundation, Inc. |
| Written by Jeff Law, Cygnus Support |
| This file is part of GDB, GAS, and the GNU binutils. |
| /contrib/toolchain/binutils/include/opcode/moxie.h |
|---|
| 1,5 → 1,5 |
| /* Definitions for decoding the moxie opcode table. |
| Copyright 2009 Free Software Foundation, Inc. |
| Copyright (C) 2009-2015 Free Software Foundation, Inc. |
| Contributed by Anthony Green (green@moxielogic.com). |
| This program is free software; you can redistribute it and/or modify |
| 28,8 → 28,8 |
| Some use B and an indirect A (MOXIE_F1_AiB) |
| Some use A and an indirect B (MOXIE_F1_ABi) |
| Some consume a 4 byte immediate value and use X (MOXIE_F1_4A) |
| Some use B and an indirect A plus 4 bytes (MOXIE_F1_AiB4) |
| Some use A and an indirect B plus 4 bytes (MOXIE_F1_ABi4) |
| Some use B and an indirect A plus 2 byte offset (MOXIE_F1_AiB2) |
| Some use A and an indirect B plus 2 byte offset (MOXIE_F1_ABi2) |
| Form 2 instructions also come in different flavors: |
| 50,8 → 50,8 |
| #define MOXIE_F1_AiB 0x106 |
| #define MOXIE_F1_ABi 0x107 |
| #define MOXIE_F1_4A 0x108 |
| #define MOXIE_F1_AiB4 0x109 |
| #define MOXIE_F1_ABi4 0x10a |
| #define MOXIE_F1_AiB2 0x109 |
| #define MOXIE_F1_ABi2 0x10a |
| #define MOXIE_F1_M 0x10b |
| #define MOXIE_F2_NARG 0x200 |
| /contrib/toolchain/binutils/include/opcode/msp430-decode.h |
|---|
| 1,5 → 1,5 |
| /* Opcode decoder for the TI MSP430 |
| Copyright 2012-2013 Free Software Foundation, Inc. |
| Copyright (C) 2012-2015 Free Software Foundation, Inc. |
| Written by DJ Delorie <dj@redhat.com> |
| This file is part of GDB, the GNU Debugger. |
| 19,6 → 19,10 |
| Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA |
| 02110-1301, USA. */ |
| #ifdef __cplusplus |
| extern "C" { |
| #endif |
| typedef enum |
| { |
| MSO_unknown, |
| 128,3 → 132,7 |
| } MSP430_Opcode_Decoded; |
| int msp430_decode_opcode (unsigned long, MSP430_Opcode_Decoded *, int (*)(void *), void *); |
| #ifdef __cplusplus |
| } |
| #endif |
| /contrib/toolchain/binutils/include/opcode/msp430.h |
|---|
| 1,6 → 1,6 |
| /* Opcode table for the TI MSP430 microcontrollers |
| Copyright 2002-2013 Free Software Foundation, Inc. |
| Copyright (C) 2002-2015 Free Software Foundation, Inc. |
| Contributed by Dmitry Diky <diwil@mail.ru> |
| This program is free software; you can redistribute it and/or modify |
| 26,7 → 26,8 |
| int ol; /* Operand length words. */ |
| int am; /* Addr mode. */ |
| int reg; /* Register. */ |
| int mode; /* Pperand mode. */ |
| int mode; /* Operand mode. */ |
| int vshift; /* Number of bytes to shift operand down. */ |
| #define OP_REG 0 |
| #define OP_EXP 1 |
| #ifndef DASM_SECTION |
| /contrib/toolchain/binutils/include/opcode/nds32.h |
|---|
| 0,0 → 1,831 |
| /* nds32.h -- Header file for nds32 opcode table |
| Copyright (C) 2012-2015 Free Software Foundation, Inc. |
| Contributed by Andes Technology Corporation. |
| This program is free software; you can redistribute it and/or modify |
| it under the terms of the GNU General Public License as published by |
| the Free Software Foundation; either version 3, or (at your option) |
| any later version. |
| This program is distributed in the hope that it will be useful, |
| but WITHOUT ANY WARRANTY; without even the implied warranty of |
| MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| GNU General Public License for more details. |
| You should have received a copy of the GNU General Public License |
| along with this program; if not, write to the Free Software |
| Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA |
| 02110-1301, USA. */ |
| #ifndef OPCODE_NDS32_H |
| #define OPCODE_NDS32_H |
| /* Registers. */ |
| #define REG_R5 5 |
| #define REG_R8 8 |
| #define REG_R10 10 |
| #define REG_R12 12 |
| #define REG_R15 15 |
| #define REG_R16 16 |
| #define REG_R20 20 |
| #define REG_TA 15 |
| #define REG_TP 27 |
| #define REG_FP 28 |
| #define REG_GP 29 |
| #define REG_LP 30 |
| #define REG_SP 31 |
| /* Macros for extracting fields or making an instruction. */ |
| static const int nds32_r45map[] = |
| { |
| 0, 1, 2, 3, 4, 5, 6, 7, |
| 8, 9, 10, 11, 16, 17, 18, 19 |
| }; |
| static const int nds32_r54map[] = |
| { |
| 0, 1, 2, 3, 4, 5, 6, 7, |
| 8, 9, 10, 11, -1, -1, -1, -1, |
| 12, 13, 14, 15, -1, -1, -1, -1, |
| -1, -1, -1, -1, -1, -1, -1, -1 |
| }; |
| #define __BIT(n) (1 << (n)) |
| #define __MASK(n) (__BIT (n) - 1) |
| #define __MF(v, off, bs) (((v) & __MASK (bs)) << (off)) |
| #define __GF(v, off, bs) (((v) >> off) & __MASK (bs)) |
| #define __SEXT(v, bs) ((((v) & ((1 << (bs)) - 1)) ^ (1 << ((bs) - 1))) - (1 << ((bs) - 1))) |
| /* Make nds32 instructions. */ |
| #define N32_TYPE4(op6, rt5, ra5, rb5, rd5, sub5) \ |
| (__MF (N32_OP6_##op6, 25, 6) | __MF (rt5, 20, 5) \ |
| | __MF (ra5, 15, 5) | __MF (rb5, 10, 5) \ |
| | __MF (rd5, 5, 5) | __MF (sub5, 0, 5)) |
| #define N32_TYPE3(op6, rt5, ra5, rb5, sub10) \ |
| (N32_TYPE4 (op6, rt5, ra5, rb5, 0, 0) \ |
| | __MF (sub10, 0, 10)) |
| #define N32_TYPE2(op6, rt5, ra5, imm15) \ |
| (N32_TYPE3 (op6, rt5, ra5, 0, 0) | __MF (imm15, 0, 15)) |
| #define N32_TYPE1(op6, rt5, imm20) \ |
| (N32_TYPE2 (op6, rt5, 0, 0) | __MF (imm20, 0, 20)) |
| #define N32_TYPE0(op6, imm25) \ |
| (N32_TYPE1 (op6, 0, 0) | __MF (imm25, 0, 25)) |
| #define N32_ALU1(sub, rt, ra, rb) \ |
| N32_TYPE4 (ALU1, rt, ra, rb, 0, N32_ALU1_##sub) |
| #define N32_ALU1_SH(sub, rt, ra, rb, rd) \ |
| N32_TYPE4 (ALU1, rt, ra, rb, rd, N32_ALU1_##sub) |
| #define N32_ALU2(sub, rt, ra, rb) \ |
| N32_TYPE3 (ALU2, rt, ra, rb, N32_ALU2_##sub) |
| #define N32_BR1(sub, rt, ra, imm14s) \ |
| N32_TYPE2 (BR1, rt, ra, (N32_BR1_##sub << 14) | (imm14s & __MASK (14))) |
| #define N32_BR2(sub, rt, imm16s) \ |
| N32_TYPE1 (BR2, rt, (N32_BR2_##sub << 16) | (imm16s & __MASK (16))) |
| #define N32_BR3(sub, rt, imm11s, imm8s) \ |
| N32_TYPE1 (BR3, rt, (N32_BR3_##sub << 19) \ |
| | ((imm11s & __MASK (11)) << 8) \ |
| | (imm8s & __MASK (8))) |
| #define N32_JI(sub, imm24s) \ |
| N32_TYPE0 (JI, (N32_JI_##sub << 24) | (imm24s & __MASK (24))) |
| #define N32_JREG(sub, rt, rb, dtit, hint) \ |
| N32_TYPE4(JREG, rt, 0, rb, (dtit << 3) | (hint & 7), N32_JREG_##sub) |
| #define N32_MEM(sub, rt, ra, rb, sv) \ |
| N32_TYPE3 (MEM, rt, ra, rb, (sv << 8) | N32_MEM_##sub) |
| #define N16_TYPE55(op5, rt5, ra5) \ |
| (0x8000 | __MF (N16_T55_##op5, 10, 5) | __MF (rt5, 5, 5) \ |
| | __MF (ra5, 0, 5)) |
| #define N16_TYPE45(op6, rt4, ra5) \ |
| (0x8000 | __MF (N16_T45_##op6, 9, 6) | __MF (rt4, 5, 4) \ |
| | __MF (ra5, 0, 5)) |
| #define N16_TYPE333(op6, rt3, ra3, rb3) \ |
| (0x8000 | __MF (N16_T333_##op6, 9, 6) | __MF (rt3, 6, 3) \ |
| | __MF (ra3, 3, 3) | __MF (rb3, 0, 3)) |
| #define N16_TYPE36(op6, rt3, imm6) \ |
| (0x8000 | __MF (N16_T36_##op6, 9, 6) | __MF (rt3, 6, 3) \ |
| | __MF (imm6, 0, 6)) |
| #define N16_TYPE38(op4, rt3, imm8) \ |
| (0x8000 | __MF (N16_T38_##op4, 11, 4) | __MF (rt3, 8, 3) \ |
| | __MF (imm8, 0, 8)) |
| #define N16_TYPE37(op4, rt3, ls, imm7) \ |
| (0x8000 | __MF (N16_T37_##op4, 11, 4) | __MF (rt3, 8, 3) \ |
| | __MF (imm7, 0, 7) | __MF (ls, 7, 1)) |
| #define N16_TYPE5(op10, imm5) \ |
| (0x8000 | __MF (N16_T5_##op10, 5, 10) | __MF (imm5, 0, 5)) |
| #define N16_TYPE8(op7, imm8) \ |
| (0x8000 | __MF (N16_T8_##op7, 8, 7) | __MF (imm8, 0, 8)) |
| #define N16_TYPE9(op6, imm9) \ |
| (0x8000 | __MF (N16_T9_##op6, 9, 6) | __MF (imm9, 0, 9)) |
| #define N16_TYPE10(op5, imm10) \ |
| (0x8000 | __MF (N16_T10_##op5, 10, 5) | __MF (imm10, 0, 10)) |
| #define N16_TYPE25(op8, re, imm5) \ |
| (0x8000 | __MF (N16_T25_##op8, 7, 8) | __MF (re, 5, 2) \ |
| | __MF (imm5, 0, 5)) |
| #define N16_MISC33(sub, rt, ra) \ |
| N16_TYPE333 (MISC33, rt, ra, N16_MISC33_##sub) |
| #define N16_BFMI333(sub, rt, ra) \ |
| N16_TYPE333 (BFMI333, rt, ra, N16_BFMI333_##sub) |
| /* Get instruction fields. |
| Macros used for handling 32-bit and 16-bit instructions are |
| prefixed with N32_ and N16_ respectively. */ |
| #define N32_OP6(insn) (((insn) >> 25) & 0x3f) |
| #define N32_RT5(insn) (((insn) >> 20) & 0x1f) |
| #define N32_RT53(insn) (N32_RT5 (insn) & 0x7) |
| #define N32_RT54(insn) nds32_r54map[N32_RT5 (insn)] |
| #define N32_RA5(insn) (((insn) >> 15) & 0x1f) |
| #define N32_RA53(insn) (N32_RA5 (insn) & 0x7) |
| #define N32_RA54(insn) nds32_r54map[N32_RA5 (insn)] |
| #define N32_RB5(insn) (((insn) >> 10) & 0x1f) |
| #define N32_UB5(insn) (((insn) >> 10) & 0x1f) |
| #define N32_RB53(insn) (N32_RB5 (insn) & 0x7) |
| #define N32_RB54(insn) nds32_r54map[N32_RB5 (insn)] |
| #define N32_RD5(insn) (((insn) >> 5) & 0x1f) |
| #define N32_SH5(insn) (((insn) >> 5) & 0x1f) |
| #define N32_SUB5(insn) (((insn) >> 0) & 0x1f) |
| #define N32_SWID(insn) (((insn) >> 5) & 0x3ff) |
| #define N32_IMMU(insn, bs) ((insn) & __MASK (bs)) |
| #define N32_IMMS(insn, bs) ((signed) __SEXT (((insn) & __MASK (bs)), bs)) |
| #define N32_IMM5U(insn) N32_IMMU (insn, 5) |
| #define N32_IMM12S(insn) N32_IMMS (insn, 12) |
| #define N32_IMM14S(insn) N32_IMMS (insn, 14) |
| #define N32_IMM15U(insn) N32_IMMU (insn, 15) |
| #define N32_IMM15S(insn) N32_IMMS (insn, 15) |
| #define N32_IMM16S(insn) N32_IMMS (insn, 16) |
| #define N32_IMM17S(insn) N32_IMMS (insn, 17) |
| #define N32_IMM20S(insn) N32_IMMS (insn, 20) |
| #define N32_IMM20U(insn) N32_IMMU (insn, 20) |
| #define N32_IMM24S(insn) N32_IMMS (insn, 24) |
| #define N16_RT5(insn) (((insn) >> 5) & 0x1f) |
| #define N16_RT4(insn) nds32_r45map[(((insn) >> 5) & 0xf)] |
| #define N16_RT3(insn) (((insn) >> 6) & 0x7) |
| #define N16_RT38(insn) (((insn) >> 8) & 0x7) |
| #define N16_RT8(insn) (((insn) >> 8) & 0x7) |
| #define N16_RA5(insn) ((insn) & 0x1f) |
| #define N16_RA3(insn) (((insn) >> 3) & 0x7) |
| #define N16_RB3(insn) ((insn) & 0x7) |
| #define N16_IMM3U(insn) N32_IMMU (insn, 3) |
| #define N16_IMM5U(insn) N32_IMMU (insn, 5) |
| #define N16_IMM5S(insn) N32_IMMS (insn, 5) |
| #define N16_IMM6U(insn) N32_IMMU (insn, 6) |
| #define N16_IMM7U(insn) N32_IMMU (insn, 7) |
| #define N16_IMM8S(insn) N32_IMMS (insn, 8) |
| #define N16_IMM9U(insn) N32_IMMU (insn, 9) |
| #define N16_IMM10S(insn) N32_IMMS (insn, 10) |
| #define IS_WITHIN_U(v, n) (((v) >> n) == 0) |
| #define IS_WITHIN_S(v, n) IS_WITHIN_U ((v) + (1 << ((n) - 1)), n) |
| /* Get fields for specific instruction. */ |
| #define N32_JREG_T(insn) (((insn) >> 8) & 0x3) |
| #define N32_JREG_HINT(insn) (((insn) >> 5) & 0x7) |
| #define N32_BR2_SUB(insn) (((insn) >> 16) & 0xf) |
| #define N32_COP_SUB(insn) ((insn) & 0xf) |
| #define N32_COP_CP(insn) (((insn) >> 4) & 0x3) |
| /* Check fields. */ |
| #define N32_IS_RT3(insn) (N32_RT5 (insn) < 8) |
| #define N32_IS_RA3(insn) (N32_RA5 (insn) < 8) |
| #define N32_IS_RB3(insn) (N32_RB5 (insn) < 8) |
| #define N32_IS_RT4(insn) (nds32_r54map[N32_RT5 (insn)] != -1) |
| #define N32_IS_RA4(insn) (nds32_r54map[N32_RA5 (insn)] != -1) |
| #define N32_IS_RB4(insn) (nds32_r54map[N32_RB5 (insn)] != -1) |
| /* These are opcodes for Nxx_TYPE macros. |
| They are prefixed by corresponding TYPE to avoid misusing. */ |
| enum n32_opcodes |
| { |
| /* Main opcodes (OP6). */ |
| N32_OP6_LBI = 0x0, |
| N32_OP6_LHI, |
| N32_OP6_LWI, |
| N32_OP6_LDI, |
| N32_OP6_LBI_BI, |
| N32_OP6_LHI_BI, |
| N32_OP6_LWI_BI, |
| N32_OP6_LDI_BI, |
| N32_OP6_SBI = 0x8, |
| N32_OP6_SHI, |
| N32_OP6_SWI, |
| N32_OP6_SDI, |
| N32_OP6_SBI_BI, |
| N32_OP6_SHI_BI, |
| N32_OP6_SWI_BI, |
| N32_OP6_SDI_BI, |
| N32_OP6_LBSI = 0x10, |
| N32_OP6_LHSI, |
| N32_OP6_LWSI, |
| N32_OP6_DPREFI, |
| N32_OP6_LBSI_BI, |
| N32_OP6_LHSI_BI, |
| N32_OP6_LWSI_BI, |
| N32_OP6_LBGP, |
| N32_OP6_LWC = 0x18, |
| N32_OP6_SWC, |
| N32_OP6_LDC, |
| N32_OP6_SDC, |
| N32_OP6_MEM, |
| N32_OP6_LSMW, |
| N32_OP6_HWGP, |
| N32_OP6_SBGP, |
| N32_OP6_ALU1 = 0x20, |
| N32_OP6_ALU2, |
| N32_OP6_MOVI, |
| N32_OP6_SETHI, |
| N32_OP6_JI, |
| N32_OP6_JREG, |
| N32_OP6_BR1, |
| N32_OP6_BR2, |
| N32_OP6_ADDI = 0x28, |
| N32_OP6_SUBRI, |
| N32_OP6_ANDI, |
| N32_OP6_XORI, |
| N32_OP6_ORI, |
| N32_OP6_BR3, |
| N32_OP6_SLTI, |
| N32_OP6_SLTSI, |
| N32_OP6_AEXT = 0x30, |
| N32_OP6_CEXT, |
| N32_OP6_MISC, |
| N32_OP6_BITCI, |
| N32_OP6_0x34, |
| N32_OP6_COP, |
| N32_OP6_0x36, |
| N32_OP6_0x37, |
| N32_OP6_SIMD = 0x38, |
| /* Sub-opcodes of specific opcode. */ |
| /* bit-24 */ |
| N32_BR1_BEQ = 0, |
| N32_BR1_BNE = 1, |
| /* bit[16:19] */ |
| N32_BR2_IFCALL = 0, |
| N32_BR2_BEQZ = 2, |
| N32_BR2_BNEZ = 3, |
| N32_BR2_BGEZ = 4, |
| N32_BR2_BLTZ = 5, |
| N32_BR2_BGTZ = 6, |
| N32_BR2_BLEZ = 7, |
| N32_BR2_BGEZAL = 0xc, |
| N32_BR2_BLTZAL = 0xd, |
| /* bit-19 */ |
| N32_BR3_BEQC = 0, |
| N32_BR3_BNEC = 1, |
| /* bit-24 */ |
| N32_JI_J = 0, |
| N32_JI_JAL = 1, |
| /* bit[0:4] */ |
| N32_JREG_JR = 0, |
| N32_JREG_JRAL = 1, |
| N32_JREG_JRNEZ = 2, |
| N32_JREG_JRALNEZ = 3, |
| /* bit[0:4] */ |
| N32_ALU1_ADD_SLLI = 0x0, |
| N32_ALU1_SUB_SLLI, |
| N32_ALU1_AND_SLLI, |
| N32_ALU1_XOR_SLLI, |
| N32_ALU1_OR_SLLI, |
| N32_ALU1_ADD = 0x0, |
| N32_ALU1_SUB, |
| N32_ALU1_AND, |
| N32_ALU1_XOR, |
| N32_ALU1_OR, |
| N32_ALU1_NOR, |
| N32_ALU1_SLT, |
| N32_ALU1_SLTS, |
| N32_ALU1_SLLI = 0x8, |
| N32_ALU1_SRLI, |
| N32_ALU1_SRAI, |
| N32_ALU1_ROTRI, |
| N32_ALU1_SLL, |
| N32_ALU1_SRL, |
| N32_ALU1_SRA, |
| N32_ALU1_ROTR, |
| N32_ALU1_SEB = 0x10, |
| N32_ALU1_SEH, |
| N32_ALU1_BITC, |
| N32_ALU1_ZEH, |
| N32_ALU1_WSBH, |
| N32_ALU1_OR_SRLI, |
| N32_ALU1_DIVSR, |
| N32_ALU1_DIVR, |
| N32_ALU1_SVA = 0x18, |
| N32_ALU1_SVS, |
| N32_ALU1_CMOVZ, |
| N32_ALU1_CMOVN, |
| N32_ALU1_ADD_SRLI, |
| N32_ALU1_SUB_SRLI, |
| N32_ALU1_AND_SRLI, |
| N32_ALU1_XOR_SRLI, |
| /* bit[0:5], where bit[6:9] == 0 */ |
| N32_ALU2_MAX = 0, |
| N32_ALU2_MIN, |
| N32_ALU2_AVE, |
| N32_ALU2_ABS, |
| N32_ALU2_CLIPS, |
| N32_ALU2_CLIP, |
| N32_ALU2_CLO, |
| N32_ALU2_CLZ, |
| N32_ALU2_BSET = 0x8, |
| N32_ALU2_BCLR, |
| N32_ALU2_BTGL, |
| N32_ALU2_BTST, |
| N32_ALU2_BSE, |
| N32_ALU2_BSP, |
| N32_ALU2_FFB, |
| N32_ALU2_FFMISM, |
| N32_ALU2_ADD_SC = 0x10, |
| N32_ALU2_SUB_SC, |
| N32_ALU2_ADD_WC, |
| N32_ALU2_SUB_WC, |
| N32_ALU2_KMxy, |
| N32_ALU2_0x15, |
| N32_ALU2_0x16, |
| N32_ALU2_FFZMISM, |
| N32_ALU2_KADD = 0x18, |
| N32_ALU2_KSUB, |
| N32_ALU2_KSLRA, |
| N32_ALU2_MFUSR = 0x20, |
| N32_ALU2_MTUSR, |
| N32_ALU2_0x22, |
| N32_ALU2_0x23, |
| N32_ALU2_MUL, |
| N32_ALU2_0x25, |
| N32_ALU2_0x26, |
| N32_ALU2_MULTS64 = 0x28, |
| N32_ALU2_MULT64, |
| N32_ALU2_MADDS64, |
| N32_ALU2_MADD64, |
| N32_ALU2_MSUBS64, |
| N32_ALU2_MSUB64, |
| N32_ALU2_DIVS, |
| N32_ALU2_DIV, |
| N32_ALU2_0x30 = 0x30, |
| N32_ALU2_MULT32, |
| N32_ALU2_0x32, |
| N32_ALU2_MADD32, |
| N32_ALU2_0x34, |
| N32_ALU2_MSUB32, |
| /* bit[0:5], where bit[6:9] != 0 */ |
| N32_ALU2_FFBI = 0xe, |
| N32_ALU2_FLMISM = 0xf, |
| N32_ALU2_MULSR64 = 0x28, |
| N32_ALU2_MULR64 = 0x29, |
| N32_ALU2_MADDR32 = 0x33, |
| N32_ALU2_MSUBR32 = 0x35, |
| /* bit[0:5] */ |
| N32_MEM_LB = 0, |
| N32_MEM_LH, |
| N32_MEM_LW, |
| N32_MEM_LD, |
| N32_MEM_LB_BI, |
| N32_MEM_LH_BI, |
| N32_MEM_LW_BI, |
| N32_MEM_LD_BI, |
| N32_MEM_SB, |
| N32_MEM_SH, |
| N32_MEM_SW, |
| N32_MEM_SD, |
| N32_MEM_SB_BI, |
| N32_MEM_SH_BI, |
| N32_MEM_SW_BI, |
| N32_MEM_SD_BI, |
| N32_MEM_LBS, |
| N32_MEM_LHS, |
| N32_MEM_LWS, /* Not used. */ |
| N32_MEM_DPREF, |
| N32_MEM_LBS_BI, |
| N32_MEM_LHS_BI, |
| N32_MEM_LWS_BI, /* Not used. */ |
| N32_MEM_0x17, /* Not used. */ |
| N32_MEM_LLW, |
| N32_MEM_SCW, |
| N32_MEM_LBUP = 0x20, |
| N32_MEM_LWUP = 0x22, |
| N32_MEM_SBUP = 0x28, |
| N32_MEM_SWUP = 0x2a, |
| /* bit[0:1] */ |
| N32_LSMW_LSMW = 0, |
| N32_LSMW_LSMWA, |
| N32_LSMW_LSMWZB, |
| /* bit[2:4] */ |
| N32_LSMW_BI = 0, |
| N32_LSMW_BIM, |
| N32_LSMW_BD, |
| N32_LSMW_BDM, |
| N32_LSMW_AI, |
| N32_LSMW_AIM, |
| N32_LSMW_AD, |
| N32_LSMW_ADM, |
| /* bit[0:4] */ |
| N32_MISC_STANDBY = 0, |
| N32_MISC_CCTL, |
| N32_MISC_MFSR, |
| N32_MISC_MTSR, |
| N32_MISC_IRET, |
| N32_MISC_TRAP, |
| N32_MISC_TEQZ, |
| N32_MISC_TNEZ, |
| N32_MISC_DSB = 0x8, |
| N32_MISC_ISB, |
| N32_MISC_BREAK, |
| N32_MISC_SYSCALL, |
| N32_MISC_MSYNC, |
| N32_MISC_ISYNC, |
| N32_MISC_TLBOP, |
| N32_MISC_0xf, |
| /* bit[0:4] */ |
| N32_SIMD_PBSAD = 0, |
| N32_SIMD_PBSADA = 1, |
| /* bit[0:3] */ |
| N32_COP_CPE1 = 0, |
| N32_COP_MFCP, |
| N32_COP_CPLW, |
| N32_COP_CPLD, |
| N32_COP_CPE2, |
| N32_COP_CPE3 = 8, |
| N32_COP_MTCP, |
| N32_COP_CPSW, |
| N32_COP_CPSD, |
| N32_COP_CPE4, |
| /* cop/0 b[3:0] */ |
| N32_FPU_FS1 = 0, |
| N32_FPU_MFCP, |
| N32_FPU_FLS, |
| N32_FPU_FLD, |
| N32_FPU_FS2, |
| N32_FPU_FD1 = 8, |
| N32_FPU_MTCP, |
| N32_FPU_FSS, |
| N32_FPU_FSD, |
| N32_FPU_FD2, |
| /* FS1 b[9:6] */ |
| N32_FPU_FS1_FADDS = 0, |
| N32_FPU_FS1_FSUBS, |
| N32_FPU_FS1_FCPYNSS, |
| N32_FPU_FS1_FCPYSS, |
| N32_FPU_FS1_FMADDS, |
| N32_FPU_FS1_FMSUBS, |
| N32_FPU_FS1_FCMOVNS, |
| N32_FPU_FS1_FCMOVZS, |
| N32_FPU_FS1_FNMADDS, |
| N32_FPU_FS1_FNMSUBS, |
| N32_FPU_FS1_10, |
| N32_FPU_FS1_11, |
| N32_FPU_FS1_FMULS = 12, |
| N32_FPU_FS1_FDIVS, |
| N32_FPU_FS1_14, |
| N32_FPU_FS1_F2OP = 15, |
| /* FS1/F2OP b[14:10] */ |
| N32_FPU_FS1_F2OP_FS2D = 0x00, |
| N32_FPU_FS1_F2OP_FSQRTS = 0x01, |
| N32_FPU_FS1_F2OP_FABSS = 0x05, |
| N32_FPU_FS1_F2OP_FUI2S = 0x08, |
| N32_FPU_FS1_F2OP_FSI2S = 0x0c, |
| N32_FPU_FS1_F2OP_FS2UI = 0x10, |
| N32_FPU_FS1_F2OP_FS2UI_Z = 0x14, |
| N32_FPU_FS1_F2OP_FS2SI = 0x18, |
| N32_FPU_FS1_F2OP_FS2SI_Z = 0x1c, |
| /* FS2 b[9:6] */ |
| N32_FPU_FS2_FCMPEQS = 0x0, |
| N32_FPU_FS2_FCMPLTS = 0x2, |
| N32_FPU_FS2_FCMPLES = 0x4, |
| N32_FPU_FS2_FCMPUNS = 0x6, |
| N32_FPU_FS2_FCMPEQS_E = 0x1, |
| N32_FPU_FS2_FCMPLTS_E = 0x3, |
| N32_FPU_FS2_FCMPLES_E = 0x5, |
| N32_FPU_FS2_FCMPUNS_E = 0x7, |
| /* FD1 b[9:6] */ |
| N32_FPU_FD1_FADDD = 0, |
| N32_FPU_FD1_FSUBD, |
| N32_FPU_FD1_FCPYNSD, |
| N32_FPU_FD1_FCPYSD, |
| N32_FPU_FD1_FMADDD, |
| N32_FPU_FD1_FMSUBD, |
| N32_FPU_FD1_FCMOVND, |
| N32_FPU_FD1_FCMOVZD, |
| N32_FPU_FD1_FNMADDD, |
| N32_FPU_FD1_FNMSUBD, |
| N32_FPU_FD1_10, |
| N32_FPU_FD1_11, |
| N32_FPU_FD1_FMULD = 12, |
| N32_FPU_FD1_FDIVD, |
| N32_FPU_FD1_14, |
| N32_FPU_FD1_F2OP = 15, |
| /* FD1/F2OP b[14:10] */ |
| N32_FPU_FD1_F2OP_FD2S = 0x00, |
| N32_FPU_FD1_F2OP_FSQRTD = 0x01, |
| N32_FPU_FD1_F2OP_FABSD = 0x05, |
| N32_FPU_FD1_F2OP_FUI2D = 0x08, |
| N32_FPU_FD1_F2OP_FSI2D = 0x0c, |
| N32_FPU_FD1_F2OP_FD2UI = 0x10, |
| N32_FPU_FD1_F2OP_FD2UI_Z = 0x14, |
| N32_FPU_FD1_F2OP_FD2SI = 0x18, |
| N32_FPU_FD1_F2OP_FD2SI_Z = 0x1c, |
| /* FD2 b[9:6] */ |
| N32_FPU_FD2_FCMPEQD = 0x0, |
| N32_FPU_FD2_FCMPLTD = 0x2, |
| N32_FPU_FD2_FCMPLED = 0x4, |
| N32_FPU_FD2_FCMPUND = 0x6, |
| N32_FPU_FD2_FCMPEQD_E = 0x1, |
| N32_FPU_FD2_FCMPLTD_E = 0x3, |
| N32_FPU_FD2_FCMPLED_E = 0x5, |
| N32_FPU_FD2_FCMPUND_E = 0x7, |
| /* MFCP b[9:6] */ |
| N32_FPU_MFCP_FMFSR = 0x0, |
| N32_FPU_MFCP_FMFDR = 0x1, |
| N32_FPU_MFCP_XR = 0xc, |
| /* MFCP/XR b[14:10] */ |
| N32_FPU_MFCP_XR_FMFCFG = 0x0, |
| N32_FPU_MFCP_XR_FMFCSR = 0x1, |
| /* MTCP b[9:6] */ |
| N32_FPU_MTCP_FMTSR = 0x0, |
| N32_FPU_MTCP_FMTDR = 0x1, |
| N32_FPU_MTCP_XR = 0xc, |
| /* MTCP/XR b[14:10] */ |
| N32_FPU_MTCP_XR_FMTCSR = 0x1 |
| }; |
| enum n16_opcodes |
| { |
| N16_T55_MOV55 = 0x0, |
| N16_T55_MOVI55 = 0x1, |
| N16_T45_0 = 0, |
| N16_T45_ADD45 = 0x4, |
| N16_T45_SUB45 = 0x5, |
| N16_T45_ADDI45 = 0x6, |
| N16_T45_SUBI45 = 0x7, |
| N16_T45_SRAI45 = 0x8, |
| N16_T45_SRLI45 = 0x9, |
| N16_T45_LWI45_FE = 0x19, |
| N16_T45_LWI450 = 0x1a, |
| N16_T45_SWI450 = 0x1b, |
| N16_T45_SLTS45 = 0x30, |
| N16_T45_SLT45 = 0x31, |
| N16_T45_SLTSI45 = 0x32, |
| N16_T45_SLTI45 = 0x33, |
| N16_T45_MOVPI45 = 0x3d, |
| N15_T44_MOVD44 = 0x7d, |
| N16_T333_0 = 0, |
| N16_T333_SLLI333 = 0xa, |
| N16_T333_BFMI333 = 0xb, |
| N16_T333_ADD333 = 0xc, |
| N16_T333_SUB333 = 0xd, |
| N16_T333_ADDI333 = 0xe, |
| N16_T333_SUBI333 = 0xf, |
| N16_T333_LWI333 = 0x10, |
| N16_T333_LWI333_BI = 0x11, |
| N16_T333_LHI333 = 0x12, |
| N16_T333_LBI333 = 0x13, |
| N16_T333_SWI333 = 0x14, |
| N16_T333_SWI333_BI = 0x15, |
| N16_T333_SHI333 = 0x16, |
| N16_T333_SBI333 = 0x17, |
| N16_T333_MISC33 = 0x3f, |
| N16_T36_ADDRI36_SP = 0x18, |
| N16_T37_XWI37 = 0x7, |
| N16_T37_XWI37SP = 0xe, |
| N16_T38_BEQZ38 = 0x8, |
| N16_T38_BNEZ38 = 0x9, |
| N16_T38_BEQS38 = 0xa, |
| N16_T38_BNES38 = 0xb, |
| N16_T5_JR5 = 0x2e8, |
| N16_T5_JRAL5 = 0x2e9, |
| N16_T5_EX9IT = 0x2ea, |
| /* 0x2eb reserved. */ |
| N16_T5_RET5 = 0x2ec, |
| N16_T5_ADD5PC = 0x2ed, |
| /* 0x2e[ef] reserved. */ |
| N16_T5_BREAK16 = 0x350, |
| N16_T8_J8 = 0x55, |
| N16_T8_BEQZS8 = 0x68, |
| N16_T8_BNEZS8 = 0x69, |
| /* N16_T9_BREAK16 = 0x35 |
| Since v3, SWID of BREAK16 above 32 are used for encoding EX9.IT. */ |
| N16_T9_EX9IT = 0x35, |
| N16_T9_IFCALL9 = 0x3c, |
| N16_T10_ADDI10S = 0x1b, |
| N16_T25_PUSH25 = 0xf8, |
| N16_T25_POP25 = 0xf9, |
| /* Sub-opcodes. */ |
| N16_MISC33_0 = 0, |
| N16_MISC33_1 = 1, |
| N16_MISC33_NEG33 = 2, |
| N16_MISC33_NOT33 = 3, |
| N16_MISC33_MUL33 = 4, |
| N16_MISC33_XOR33 = 5, |
| N16_MISC33_AND33 = 6, |
| N16_MISC33_OR33 = 7, |
| N16_BFMI333_ZEB33 = 0, |
| N16_BFMI333_ZEH33 = 1, |
| N16_BFMI333_SEB33 = 2, |
| N16_BFMI333_SEH33 = 3, |
| N16_BFMI333_XLSB33 = 4, |
| N16_BFMI333_X11B33 = 5, |
| N16_BFMI333_BMSKI33 = 6, |
| N16_BFMI333_FEXTI33 = 7 |
| }; |
| /* These macros a deprecated. DO NOT use them anymore. |
| And please help rewrite code used them. */ |
| /* 32-bit instructions without operands. */ |
| #define INSN_SETHI 0x46000000 |
| #define INSN_ORI 0x58000000 |
| #define INSN_JR 0x4a000000 |
| #define INSN_RET 0x4a000020 |
| #define INSN_JAL 0x49000000 |
| #define INSN_J 0x48000000 |
| #define INSN_JRAL 0x4a000001 |
| #define INSN_BGEZAL 0x4e0c0000 |
| #define INSN_BLTZAL 0x4e0d0000 |
| #define INSN_BEQ 0x4c000000 |
| #define INSN_BNE 0x4c004000 |
| #define INSN_BEQZ 0x4e020000 |
| #define INSN_BNEZ 0x4e030000 |
| #define INSN_BGEZ 0x4e040000 |
| #define INSN_BLTZ 0x4e050000 |
| #define INSN_BGTZ 0x4e060000 |
| #define INSN_BLEZ 0x4e070000 |
| #define INSN_MOVI 0x44000000 |
| #define INSN_ADDI 0x50000000 |
| #define INSN_ANDI 0x54000000 |
| #define INSN_LDI 0x06000000 |
| #define INSN_SDI 0x16000000 |
| #define INSN_LWI 0x04000000 |
| #define INSN_LWSI 0x24000000 |
| #define INSN_LWIP 0x0c000000 |
| #define INSN_LHI 0x02000000 |
| #define INSN_LHSI 0x22000000 |
| #define INSN_LBI 0x00000000 |
| #define INSN_LBSI 0x20000000 |
| #define INSN_SWI 0x14000000 |
| #define INSN_SWIP 0x1c000000 |
| #define INSN_SHI 0x12000000 |
| #define INSN_SBI 0x10000000 |
| #define INSN_SLTI 0x5c000000 |
| #define INSN_SLTSI 0x5e000000 |
| #define INSN_ADD 0x40000000 |
| #define INSN_SUB 0x40000001 |
| #define INSN_SLT 0x40000006 |
| #define INSN_SLTS 0x40000007 |
| #define INSN_SLLI 0x40000008 |
| #define INSN_SRLI 0x40000009 |
| #define INSN_SRAI 0x4000000a |
| #define INSN_SEB 0x40000010 |
| #define INSN_SEH 0x40000011 |
| #define INSN_ZEB INSN_ANDI + 0xFF |
| #define INSN_ZEH 0x40000013 |
| #define INSN_BREAK 0x6400000a |
| #define INSN_NOP 0x40000009 |
| #define INSN_FLSI 0x30000000 |
| #define INSN_FSSI 0x32000000 |
| #define INSN_FLDI 0x34000000 |
| #define INSN_FSDI 0x36000000 |
| #define INSN_BEQC 0x5a000000 |
| #define INSN_BNEC 0x5a080000 |
| #define INSN_DSB 0x64000008 |
| #define INSN_IFCALL 0x4e000000 |
| #define INSN_IFRET 0x4a000060 |
| #define INSN_BR1 0x4c000000 |
| #define INSN_BR2 0x4e000000 |
| /* 16-bit instructions without operand. */ |
| #define INSN_MOV55 0x8000 |
| #define INSN_MOVI55 0x8400 |
| #define INSN_ADD45 0x8800 |
| #define INSN_SUB45 0x8a00 |
| #define INSN_ADDI45 0x8c00 |
| #define INSN_SUBI45 0x8e00 |
| #define INSN_SRAI45 0x9000 |
| #define INSN_SRLI45 0x9200 |
| #define INSN_SLLI333 0x9400 |
| #define INSN_BFMI333 0x9600 |
| #define INSN_ADD333 0x9800 |
| #define INSN_SUB333 0x9a00 |
| #define INSN_ADDI333 0x9c00 |
| #define INSN_SUBI333 0x9e00 |
| #define INSN_LWI333 0xa000 |
| #define INSN_LWI333P 0xa200 |
| #define INSN_LHI333 0xa400 |
| #define INSN_LBI333 0xa600 |
| #define INSN_SWI333 0xa800 |
| #define INSN_SWI333P 0xaa00 |
| #define INSN_SHI333 0xac00 |
| #define INSN_SBI333 0xae00 |
| #define INSN_RSV01 0xb000 |
| #define INSN_RSV02 0xb200 |
| #define INSN_LWI450 0xb400 |
| #define INSN_SWI450 0xb600 |
| #define INSN_LWI37 0xb800 |
| #define INSN_SWI37 0xb880 |
| #define INSN_BEQZ38 0xc000 |
| #define INSN_BNEZ38 0xc800 |
| #define INSN_BEQS38 0xd000 |
| #define INSN_J8 0xd500 |
| #define INSN_BNES38 0xd800 |
| #define INSN_JR5 0xdd00 |
| #define INSN_RET5 0xdd80 |
| #define INSN_JRAL5 0xdd20 |
| #define INSN_EX9_IT_2 0xdd40 |
| #define INSN_SLTS45 0xe000 |
| #define INSN_SLT45 0xe200 |
| #define INSN_SLTSI45 0xe400 |
| #define INSN_SLTI45 0xe600 |
| #define INSN_BEQZS8 0xe800 |
| #define INSN_BNEZS8 0xe900 |
| #define INSN_BREAK16 0xea00 |
| #define INSN_EX9_IT_1 0xea00 |
| #define INSN_NOP16 0x9200 |
| /* 16-bit version 2. */ |
| #define INSN_ADDI10_SP 0xec00 |
| #define INSN_LWI37SP 0xf000 |
| #define INSN_SWI37SP 0xf080 |
| /* 16-bit version 3. */ |
| #define INSN_IFRET16 0x83ff |
| #define INSN_ADDRI36_SP 0xb000 |
| #define INSN_LWI45_FE 0xb200 |
| #define INSN_IFCALL9 0xf800 |
| #define INSN_MISC33 0xfe00 |
| /* Instruction with specific operands. */ |
| #define INSN_ADDI_GP_TO_FP 0x51cd8000 /* BASELINE_V1. */ |
| #define INSN_ADDIGP_TO_FP 0x3fc80000 /* BASELINE_V2. */ |
| #define INSN_MOVI_TO_FP 0x45c00000 |
| #define INSN_MFUSR_PC 0x420F8020 |
| #define INSN_MFUSR_PC_MASK 0xFE0FFFFF |
| /* Instructions use $ta register as operand. */ |
| #define INSN_SETHI_TA (INSN_SETHI | (REG_TA << 20)) |
| #define INSN_ORI_TA (INSN_ORI | (REG_TA << 20) | (REG_TA << 15)) |
| #define INSN_ADD_TA (INSN_ADD | (REG_TA << 20)) |
| #define INSN_ADD45_TA (INSN_ADD45 | (REG_TA << 5)) |
| #define INSN_JR5_TA (INSN_JR5 | (REG_TA << 0)) |
| #define INSN_RET5_TA (INSN_RET5 | (REG_TA << 0)) |
| #define INSN_JR_TA (INSN_JR | (REG_TA << 10)) |
| #define INSN_RET_TA (INSN_RET | (REG_TA << 10)) |
| #define INSN_JRAL_TA (INSN_JRAL | (REG_LP << 20) | (REG_TA << 10)) |
| #define INSN_JRAL5_TA (INSN_JRAL5 | (REG_TA << 0)) |
| #define INSN_BEQZ_TA (INSN_BEQZ | (REG_TA << 20)) |
| #define INSN_BNEZ_TA (INSN_BNEZ | (REG_TA << 20)) |
| #define INSN_MOVI_TA (INSN_MOVI | (REG_TA << 20)) |
| #define INSN_BEQ_TA (INSN_BEQ | (REG_TA << 15)) |
| #define INSN_BNE_TA (INSN_BNE | (REG_TA << 15)) |
| /* Instructions use $r5 register as operand. */ |
| #define INSN_BNE_R5 (INSN_BNE | (REG_R5 << 15)) |
| #define INSN_BEQ_R5 (INSN_BEQ | (REG_R5 << 15)) |
| #endif |
| /contrib/toolchain/binutils/include/opcode/nios2.h |
|---|
| 1,5 → 1,5 |
| /* Nios II opcode list for GAS, the GNU assembler. |
| Copyright (C) 2012, 2013 Free Software Foundation, Inc. |
| Copyright (C) 2012-2015 Free Software Foundation, Inc. |
| Contributed by Nigel Gray (ngray@altera.com). |
| Contributed by Mentor Graphics, Inc. |
| 25,6 → 25,10 |
| #include "bfd.h" |
| #ifdef __cplusplus |
| extern "C" { |
| #endif |
| /**************************************************************************** |
| * This file contains structures, bit masks and shift counts used |
| * by the GNU toolchain to define the Nios II instruction set and |
| 31,6 → 35,42 |
| * access various opcode fields. |
| ****************************************************************************/ |
| /* Instruction encoding formats. */ |
| enum iw_format_type { |
| /* R1 formats. */ |
| iw_i_type, |
| iw_r_type, |
| iw_j_type, |
| iw_custom_type, |
| /* 32-bit R2 formats. */ |
| iw_L26_type, |
| iw_F2I16_type, |
| iw_F2X4I12_type, |
| iw_F1X4I12_type, |
| iw_F1X4L17_type, |
| iw_F3X6L5_type, |
| iw_F2X6L10_type, |
| iw_F3X6_type, |
| iw_F3X8_type, |
| /* 16-bit R2 formats. */ |
| iw_I10_type, |
| iw_T1I7_type, |
| iw_T2I4_type, |
| iw_T1X1I6_type, |
| iw_X1I7_type, |
| iw_L5I4X1_type, |
| iw_T2X1L3_type, |
| iw_T2X1I3_type, |
| iw_T3X1_type, |
| iw_T2X3_type, |
| iw_F1X1_type, |
| iw_X2L5_type, |
| iw_F1I5_type, |
| iw_F2_type |
| }; |
| /* Identify different overflow situations for error messages. */ |
| enum overflow_type |
| { |
| 40,7 → 80,9 |
| signed_immed16_overflow, |
| unsigned_immed16_overflow, |
| unsigned_immed5_overflow, |
| signed_immed12_overflow, |
| custom_opcode_overflow, |
| enumeration_overflow, |
| no_overflow |
| }; |
| 52,16 → 94,38 |
| d - a 5-bit destination register index |
| s - a 5-bit left source register index |
| t - a 5-bit right source register index |
| D - a 3-bit encoded destination register |
| S - a 3-bit encoded left source register |
| T - a 3-bit encoded right source register |
| i - a 16-bit signed immediate |
| u - a 16-bit unsigned immediate |
| o - a 16-bit signed program counter relative offset |
| j - a 5-bit unsigned immediate |
| b - a 5-bit break instruction constant |
| k - a (second) 5-bit unsigned immediate |
| l - a 8-bit custom instruction constant |
| m - a 26-bit unsigned immediate |
| o - a 16-bit signed pc-relative offset |
| u - a 16-bit unsigned immediate |
| I - a 12-bit signed immediate |
| M - a 6-bit unsigned immediate |
| N - a 6-bit unsigned immediate with 2-bit shift |
| O - a 10-bit signed pc-relative offset with 1-bit shift |
| P - a 7-bit signed pc-relative offset with 1-bit shift |
| U - a 7-bit unsigned immediate with 2-bit shift |
| V - a 5-bit unsigned immediate with 2-bit shift |
| W - a 4-bit unsigned immediate with 2-bit shift |
| X - a 4-bit unsigned immediate with 1-bit shift |
| Y - a 4-bit unsigned immediate |
| e - an immediate coded as an enumeration for addi.n/subi.n |
| f - an immediate coded as an enumeration for slli.n/srli.n |
| g - an immediate coded as an enumeration for andi.n |
| h - an immediate coded as an enumeration for movi.n |
| R - a reglist for ldwm/stwm or push.n/pop.n |
| B - a base register specifier and option list for ldwm/stwm |
| Literal ',', '(', and ')' characters may also appear in the args as |
| delimiters. |
| Note that the args describe the semantics and assembly-language syntax |
| of the operands, not their encoding into the instruction word. |
| The pinfo field is INSN_MACRO for a macro. Otherwise, it is a collection |
| of bits describing the instruction, notably any relevant hazard |
| information. |
| 84,6 → 148,8 |
| the expected opcode. */ |
| unsigned long num_args; /* The number of arguments the instruction |
| takes. */ |
| unsigned size; /* Size in bytes of the instruction. */ |
| enum iw_format_type format; /* Instruction format. */ |
| unsigned long match; /* The basic opcode for the instruction. */ |
| unsigned long mask; /* Mask for the opcode field of the |
| instruction. */ |
| 107,403 → 173,34 |
| #define NIOS2_INSN_CBRANCH 0x00000020 |
| #define NIOS2_INSN_CALL 0x00000040 |
| #define NIOS2_INSN_ADDI 0x00000080 |
| #define NIOS2_INSN_ANDI 0x00000100 |
| #define NIOS2_INSN_ORI 0x00000200 |
| #define NIOS2_INSN_XORI 0x00000400 |
| #define NIOS2_INSN_OPTARG 0x00000080 |
| /* Register attributes. */ |
| #define REG_NORMAL (1<<0) /* Normal registers. */ |
| #define REG_CONTROL (1<<1) /* Control registers. */ |
| #define REG_COPROCESSOR (1<<2) /* For custom instructions. */ |
| #define REG_3BIT (1<<3) /* For R2 CDX instructions. */ |
| #define REG_LDWM (1<<4) /* For R2 ldwm/stwm. */ |
| #define REG_POP (1<<5) /* For R2 pop.n/push.n. */ |
| /* Associates a register name ($6) with a 5-bit index (eg 6). */ |
| struct nios2_reg |
| { |
| const char *name; |
| const int index; |
| unsigned long regtype; |
| }; |
| /* Pull in the instruction field accessors, opcodes, and masks. */ |
| #include "nios2r1.h" |
| #include "nios2r2.h" |
| /* These are bit masks and shift counts for accessing the various |
| fields of a Nios II instruction. */ |
| /* Macros for getting and setting an instruction field. */ |
| #define GET_INSN_FIELD(X, i) \ |
| (((i) & OP_MASK_##X) >> OP_SH_##X) |
| #define SET_INSN_FIELD(X, i, j) \ |
| ((i) = (((i) & ~OP_MASK_##X) | (((j) << OP_SH_##X) & OP_MASK_##X))) |
| /* Instruction field definitions. */ |
| #define IW_A_LSB 27 |
| #define IW_A_MSB 31 |
| #define IW_A_SZ 5 |
| #define IW_A_MASK 0x1f |
| #define IW_B_LSB 22 |
| #define IW_B_MSB 26 |
| #define IW_B_SZ 5 |
| #define IW_B_MASK 0x1f |
| #define IW_C_LSB 17 |
| #define IW_C_MSB 21 |
| #define IW_C_SZ 5 |
| #define IW_C_MASK 0x1f |
| #define IW_IMM16_LSB 6 |
| #define IW_IMM16_MSB 21 |
| #define IW_IMM16_SZ 16 |
| #define IW_IMM16_MASK 0xffff |
| #define IW_IMM26_LSB 6 |
| #define IW_IMM26_MSB 31 |
| #define IW_IMM26_SZ 26 |
| #define IW_IMM26_MASK 0x3ffffff |
| #define IW_OP_LSB 0 |
| #define IW_OP_MSB 5 |
| #define IW_OP_SZ 6 |
| #define IW_OP_MASK 0x3f |
| #define IW_OPX_LSB 11 |
| #define IW_OPX_MSB 16 |
| #define IW_OPX_SZ 6 |
| #define IW_OPX_MASK 0x3f |
| #define IW_SHIFT_IMM5_LSB 6 |
| #define IW_SHIFT_IMM5_MSB 10 |
| #define IW_SHIFT_IMM5_SZ 5 |
| #define IW_SHIFT_IMM5_MASK 0x1f |
| #define IW_CONTROL_REGNUM_LSB 6 |
| #define IW_CONTROL_REGNUM_MSB 9 |
| #define IW_CONTROL_REGNUM_SZ 4 |
| #define IW_CONTROL_REGNUM_MASK 0xf |
| /* Operator mask and shift. */ |
| #define OP_MASK_OP (IW_OP_MASK << IW_OP_LSB) |
| #define OP_SH_OP IW_OP_LSB |
| /* Masks and shifts for I-type instructions. */ |
| #define OP_MASK_IOP (IW_OP_MASK << IW_OP_LSB) |
| #define OP_SH_IOP IW_OP_LSB |
| #define OP_MASK_IMM16 (IW_IMM16_MASK << IW_IMM16_LSB) |
| #define OP_SH_IMM16 IW_IMM16_LSB |
| #define OP_MASK_IRD (IW_B_MASK << IW_B_LSB) |
| #define OP_SH_IRD IW_B_LSB /* The same as T for I-type. */ |
| #define OP_MASK_IRT (IW_B_MASK << IW_B_LSB) |
| #define OP_SH_IRT IW_B_LSB |
| #define OP_MASK_IRS (IW_A_MASK << IW_A_LSB) |
| #define OP_SH_IRS IW_A_LSB |
| /* Masks and shifts for R-type instructions. */ |
| #define OP_MASK_ROP (IW_OP_MASK << IW_OP_LSB) |
| #define OP_SH_ROP IW_OP_LSB |
| #define OP_MASK_ROPX (IW_OPX_MASK << IW_OPX_LSB) |
| #define OP_SH_ROPX IW_OPX_LSB |
| #define OP_MASK_RRD (IW_C_MASK << IW_C_LSB) |
| #define OP_SH_RRD IW_C_LSB |
| #define OP_MASK_RRT (IW_B_MASK << IW_B_LSB) |
| #define OP_SH_RRT IW_B_LSB |
| #define OP_MASK_RRS (IW_A_MASK << IW_A_LSB) |
| #define OP_SH_RRS IW_A_LSB |
| /* Masks and shifts for J-type instructions. */ |
| #define OP_MASK_JOP (IW_OP_MASK << IW_OP_LSB) |
| #define OP_SH_JOP IW_OP_LSB |
| #define OP_MASK_IMM26 (IW_IMM26_MASK << IW_IMM26_LSB) |
| #define OP_SH_IMM26 IW_IMM26_LSB |
| /* Masks and shifts for CTL instructions. */ |
| #define OP_MASK_RCTL 0x000007c0 |
| #define OP_SH_RCTL 6 |
| /* Break instruction imm5 field. */ |
| #define OP_MASK_TRAP_IMM5 0x000007c0 |
| #define OP_SH_TRAP_IMM5 6 |
| /* Instruction imm5 field. */ |
| #define OP_MASK_IMM5 (IW_SHIFT_IMM5_MASK << IW_SHIFT_IMM5_LSB) |
| #define OP_SH_IMM5 IW_SHIFT_IMM5_LSB |
| /* Cache operation fields (type j,i(s)). */ |
| #define OP_MASK_CACHE_OPX (IW_B_MASK << IW_B_LSB) |
| #define OP_SH_CACHE_OPX IW_B_LSB |
| #define OP_MASK_CACHE_RRS (IW_A_MASK << IW_A_LSB) |
| #define OP_SH_CACHE_RRS IW_A_LSB |
| /* Custom instruction masks. */ |
| #define OP_MASK_CUSTOM_A 0x00010000 |
| #define OP_SH_CUSTOM_A 16 |
| #define OP_MASK_CUSTOM_B 0x00008000 |
| #define OP_SH_CUSTOM_B 15 |
| #define OP_MASK_CUSTOM_C 0x00004000 |
| #define OP_SH_CUSTOM_C 14 |
| #define OP_MASK_CUSTOM_N 0x00003fc0 |
| #define OP_SH_CUSTOM_N 6 |
| #define OP_MAX_CUSTOM_N 255 |
| /* OP instruction values. */ |
| #define OP_ADDI 4 |
| #define OP_ANDHI 44 |
| #define OP_ANDI 12 |
| #define OP_BEQ 38 |
| #define OP_BGE 14 |
| #define OP_BGEU 46 |
| #define OP_BLT 22 |
| #define OP_BLTU 54 |
| #define OP_BNE 30 |
| #define OP_BR 6 |
| #define OP_CALL 0 |
| #define OP_CMPEQI 32 |
| #define OP_CMPGEI 8 |
| #define OP_CMPGEUI 40 |
| #define OP_CMPLTI 16 |
| #define OP_CMPLTUI 48 |
| #define OP_CMPNEI 24 |
| #define OP_CUSTOM 50 |
| #define OP_FLUSHD 59 |
| #define OP_FLUSHDA 27 |
| #define OP_INITD 51 |
| #define OP_INITDA 19 |
| #define OP_JMPI 1 |
| #define OP_LDB 7 |
| #define OP_LDBIO 39 |
| #define OP_LDBU 3 |
| #define OP_LDBUIO 35 |
| #define OP_LDH 15 |
| #define OP_LDHIO 47 |
| #define OP_LDHU 11 |
| #define OP_LDHUIO 43 |
| #define OP_LDL 31 |
| #define OP_LDW 23 |
| #define OP_LDWIO 55 |
| #define OP_MULI 36 |
| #define OP_OPX 58 |
| #define OP_ORHI 52 |
| #define OP_ORI 20 |
| #define OP_RDPRS 56 |
| #define OP_STB 5 |
| #define OP_STBIO 37 |
| #define OP_STC 29 |
| #define OP_STH 13 |
| #define OP_STHIO 45 |
| #define OP_STW 21 |
| #define OP_STWIO 53 |
| #define OP_XORHI 60 |
| #define OP_XORI 28 |
| /* OPX instruction values. */ |
| #define OPX_ADD 49 |
| #define OPX_AND 14 |
| #define OPX_BREAK 52 |
| #define OPX_BRET 9 |
| #define OPX_CALLR 29 |
| #define OPX_CMPEQ 32 |
| #define OPX_CMPGE 8 |
| #define OPX_CMPGEU 40 |
| #define OPX_CMPLT 16 |
| #define OPX_CMPLTU 48 |
| #define OPX_CMPNE 24 |
| #define OPX_CRST 62 |
| #define OPX_DIV 37 |
| #define OPX_DIVU 36 |
| #define OPX_ERET 1 |
| #define OPX_FLUSHI 12 |
| #define OPX_FLUSHP 4 |
| #define OPX_HBREAK 53 |
| #define OPX_INITI 41 |
| #define OPX_INTR 61 |
| #define OPX_JMP 13 |
| #define OPX_MUL 39 |
| #define OPX_MULXSS 31 |
| #define OPX_MULXSU 23 |
| #define OPX_MULXUU 7 |
| #define OPX_NEXTPC 28 |
| #define OPX_NOR 6 |
| #define OPX_OR 22 |
| #define OPX_RDCTL 38 |
| #define OPX_RET 5 |
| #define OPX_ROL 3 |
| #define OPX_ROLI 2 |
| #define OPX_ROR 11 |
| #define OPX_SLL 19 |
| #define OPX_SLLI 18 |
| #define OPX_SRA 59 |
| #define OPX_SRAI 58 |
| #define OPX_SRL 27 |
| #define OPX_SRLI 26 |
| #define OPX_SUB 57 |
| #define OPX_SYNC 54 |
| #define OPX_TRAP 45 |
| #define OPX_WRCTL 46 |
| #define OPX_WRPRS 20 |
| #define OPX_XOR 30 |
| /* The following macros define the opcode matches for each |
| instruction code & OP_MASK_INST == OP_MATCH_INST. */ |
| /* OP instruction matches. */ |
| #define OP_MATCH_ADDI OP_ADDI |
| #define OP_MATCH_ANDHI OP_ANDHI |
| #define OP_MATCH_ANDI OP_ANDI |
| #define OP_MATCH_BEQ OP_BEQ |
| #define OP_MATCH_BGE OP_BGE |
| #define OP_MATCH_BGEU OP_BGEU |
| #define OP_MATCH_BLT OP_BLT |
| #define OP_MATCH_BLTU OP_BLTU |
| #define OP_MATCH_BNE OP_BNE |
| #define OP_MATCH_BR OP_BR |
| #define OP_MATCH_FLUSHD OP_FLUSHD |
| #define OP_MATCH_FLUSHDA OP_FLUSHDA |
| #define OP_MATCH_INITD OP_INITD |
| #define OP_MATCH_INITDA OP_INITDA |
| #define OP_MATCH_CALL OP_CALL |
| #define OP_MATCH_CMPEQI OP_CMPEQI |
| #define OP_MATCH_CMPGEI OP_CMPGEI |
| #define OP_MATCH_CMPGEUI OP_CMPGEUI |
| #define OP_MATCH_CMPLTI OP_CMPLTI |
| #define OP_MATCH_CMPLTUI OP_CMPLTUI |
| #define OP_MATCH_CMPNEI OP_CMPNEI |
| #define OP_MATCH_JMPI OP_JMPI |
| #define OP_MATCH_LDB OP_LDB |
| #define OP_MATCH_LDBIO OP_LDBIO |
| #define OP_MATCH_LDBU OP_LDBU |
| #define OP_MATCH_LDBUIO OP_LDBUIO |
| #define OP_MATCH_LDH OP_LDH |
| #define OP_MATCH_LDHIO OP_LDHIO |
| #define OP_MATCH_LDHU OP_LDHU |
| #define OP_MATCH_LDHUIO OP_LDHUIO |
| #define OP_MATCH_LDL OP_LDL |
| #define OP_MATCH_LDW OP_LDW |
| #define OP_MATCH_LDWIO OP_LDWIO |
| #define OP_MATCH_MULI OP_MULI |
| #define OP_MATCH_OPX OP_OPX |
| #define OP_MATCH_ORHI OP_ORHI |
| #define OP_MATCH_ORI OP_ORI |
| #define OP_MATCH_RDPRS OP_RDPRS |
| #define OP_MATCH_STB OP_STB |
| #define OP_MATCH_STBIO OP_STBIO |
| #define OP_MATCH_STC OP_STC |
| #define OP_MATCH_STH OP_STH |
| #define OP_MATCH_STHIO OP_STHIO |
| #define OP_MATCH_STW OP_STW |
| #define OP_MATCH_STWIO OP_STWIO |
| #define OP_MATCH_CUSTOM OP_CUSTOM |
| #define OP_MATCH_XORHI OP_XORHI |
| #define OP_MATCH_XORI OP_XORI |
| #define OP_MATCH_OPX OP_OPX |
| /* OPX instruction values. */ |
| #define OPX_MATCH(code) ((code << IW_OPX_LSB) | OP_OPX) |
| #define OP_MATCH_ADD OPX_MATCH (OPX_ADD) |
| #define OP_MATCH_AND OPX_MATCH (OPX_AND) |
| #define OP_MATCH_BREAK ((0x1e << 17) | OPX_MATCH (OPX_BREAK)) |
| #define OP_MATCH_BRET (0xf0000000 | OPX_MATCH (OPX_BRET)) |
| #define OP_MATCH_CALLR ((0x1f << 17) | OPX_MATCH (OPX_CALLR)) |
| #define OP_MATCH_CMPEQ OPX_MATCH (OPX_CMPEQ) |
| #define OP_MATCH_CMPGE OPX_MATCH (OPX_CMPGE) |
| #define OP_MATCH_CMPGEU OPX_MATCH (OPX_CMPGEU) |
| #define OP_MATCH_CMPLT OPX_MATCH (OPX_CMPLT) |
| #define OP_MATCH_CMPLTU OPX_MATCH (OPX_CMPLTU) |
| #define OP_MATCH_CMPNE OPX_MATCH (OPX_CMPNE) |
| #define OP_MATCH_DIV OPX_MATCH (OPX_DIV) |
| #define OP_MATCH_DIVU OPX_MATCH (OPX_DIVU) |
| #define OP_MATCH_JMP OPX_MATCH (OPX_JMP) |
| #define OP_MATCH_MUL OPX_MATCH (OPX_MUL) |
| #define OP_MATCH_MULXSS OPX_MATCH (OPX_MULXSS) |
| #define OP_MATCH_MULXSU OPX_MATCH (OPX_MULXSU) |
| #define OP_MATCH_MULXUU OPX_MATCH (OPX_MULXUU) |
| #define OP_MATCH_NEXTPC OPX_MATCH (OPX_NEXTPC) |
| #define OP_MATCH_NOR OPX_MATCH (OPX_NOR) |
| #define OP_MATCH_OR OPX_MATCH (OPX_OR) |
| #define OP_MATCH_RDCTL OPX_MATCH (OPX_RDCTL) |
| #define OP_MATCH_RET (0xf8000000 | OPX_MATCH (OPX_RET)) |
| #define OP_MATCH_ROL OPX_MATCH (OPX_ROL) |
| #define OP_MATCH_ROLI OPX_MATCH (OPX_ROLI) |
| #define OP_MATCH_ROR OPX_MATCH (OPX_ROR) |
| #define OP_MATCH_SLL OPX_MATCH (OPX_SLL) |
| #define OP_MATCH_SLLI OPX_MATCH (OPX_SLLI) |
| #define OP_MATCH_SRA OPX_MATCH (OPX_SRA) |
| #define OP_MATCH_SRAI OPX_MATCH (OPX_SRAI) |
| #define OP_MATCH_SRL OPX_MATCH (OPX_SRL) |
| #define OP_MATCH_SRLI OPX_MATCH (OPX_SRLI) |
| #define OP_MATCH_SUB OPX_MATCH (OPX_SUB) |
| #define OP_MATCH_SYNC OPX_MATCH (OPX_SYNC) |
| #define OP_MATCH_TRAP ((0x1d << 17) | OPX_MATCH (OPX_TRAP)) |
| #define OP_MATCH_ERET (0xef800000 | OPX_MATCH (OPX_ERET)) |
| #define OP_MATCH_WRCTL OPX_MATCH (OPX_WRCTL) |
| #define OP_MATCH_WRPRS OPX_MATCH (OPX_WRPRS) |
| #define OP_MATCH_XOR OPX_MATCH (OPX_XOR) |
| #define OP_MATCH_FLUSHI OPX_MATCH (OPX_FLUSHI) |
| #define OP_MATCH_FLUSHP OPX_MATCH (OPX_FLUSHP) |
| #define OP_MATCH_INITI OPX_MATCH (OPX_INITI) |
| /* Some unusual op masks. */ |
| #define OP_MASK_BREAK ((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_RRD \ |
| | OP_MASK_ROPX | OP_MASK_OP) \ |
| & 0xfffff03f) |
| #define OP_MASK_CALLR ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \ |
| | OP_MASK_OP)) |
| #define OP_MASK_JMP ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \ |
| | OP_MASK_OP)) |
| #define OP_MASK_SYNC ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \ |
| | OP_MASK_OP)) |
| #define OP_MASK_TRAP ((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_RRD \ |
| | OP_MASK_ROPX | OP_MASK_OP) \ |
| & 0xfffff83f) |
| #define OP_MASK_WRCTL ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \ |
| | OP_MASK_OP)) /*& 0xfffff83f */ |
| #define OP_MASK_NEXTPC ((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_ROPX \ |
| | OP_MASK_OP)) |
| #define OP_MASK_FLUSHI ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \ |
| | OP_MASK_OP)) |
| #define OP_MASK_INITI ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \ |
| | OP_MASK_OP)) |
| #define OP_MASK_ROLI ((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP)) |
| #define OP_MASK_SLLI ((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP)) |
| #define OP_MASK_SRAI ((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP)) |
| #define OP_MASK_SRLI ((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP)) |
| #define OP_MASK_RDCTL ((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_ROPX \ |
| | OP_MASK_OP)) /*& 0xfffff83f */ |
| #ifndef OP_MASK |
| #define OP_MASK 0xffffffff |
| #endif |
| /* These convenience macros to extract instruction fields are used by GDB. */ |
| #define GET_IW_A(Iw) \ |
| (((Iw) >> IW_A_LSB) & IW_A_MASK) |
| #define GET_IW_B(Iw) \ |
| (((Iw) >> IW_B_LSB) & IW_B_MASK) |
| #define GET_IW_C(Iw) \ |
| (((Iw) >> IW_C_LSB) & IW_C_MASK) |
| #define GET_IW_CONTROL_REGNUM(Iw) \ |
| (((Iw) >> IW_CONTROL_REGNUM_LSB) & IW_CONTROL_REGNUM_MASK) |
| #define GET_IW_IMM16(Iw) \ |
| (((Iw) >> IW_IMM16_LSB) & IW_IMM16_MASK) |
| #define GET_IW_IMM26(Iw) \ |
| (((Iw) >> IW_IMM26_LSB) & IW_IMM26_MASK) |
| #define GET_IW_OP(Iw) \ |
| (((Iw) >> IW_OP_LSB) & IW_OP_MASK) |
| #define GET_IW_OPX(Iw) \ |
| (((Iw) >> IW_OPX_LSB) & IW_OPX_MASK) |
| /* These are the data structures we use to hold the instruction information. */ |
| extern const struct nios2_opcode nios2_builtin_opcodes[]; |
| extern const int bfd_nios2_num_builtin_opcodes; |
| /* These are the data structures used to hold the instruction information. */ |
| extern const struct nios2_opcode nios2_r1_opcodes[]; |
| extern const int nios2_num_r1_opcodes; |
| extern const struct nios2_opcode nios2_r2_opcodes[]; |
| extern const int nios2_num_r2_opcodes; |
| extern struct nios2_opcode *nios2_opcodes; |
| extern int bfd_nios2_num_opcodes; |
| extern int nios2_num_opcodes; |
| /* These are the data structures used to hold the register information. */ |
| extern const struct nios2_reg nios2_builtin_regs[]; |
| 511,12 → 208,28 |
| extern const int nios2_num_builtin_regs; |
| extern int nios2_num_regs; |
| /* Machine-independent macro for number of opcodes. */ |
| #define NUMOPCODES bfd_nios2_num_opcodes |
| #define NUMREGISTERS nios2_num_regs; |
| /* Return the opcode descriptor for a single instruction. */ |
| extern const struct nios2_opcode * |
| nios2_find_opcode_hash (unsigned long, unsigned long); |
| /* This is made extern so that the assembler can use it to find out |
| what instruction caused an error. */ |
| extern const struct nios2_opcode *nios2_find_opcode_hash (unsigned long); |
| /* Lookup tables for R2 immediate decodings. */ |
| extern unsigned int nios2_r2_asi_n_mappings[]; |
| extern const int nios2_num_r2_asi_n_mappings; |
| extern unsigned int nios2_r2_shi_n_mappings[]; |
| extern const int nios2_num_r2_shi_n_mappings; |
| extern unsigned int nios2_r2_andi_n_mappings[]; |
| extern const int nios2_num_r2_andi_n_mappings; |
| /* Lookup table for 3-bit register decodings. */ |
| extern int nios2_r2_reg3_mappings[]; |
| extern const int nios2_num_r2_reg3_mappings; |
| /* Lookup table for REG_RANGE value list decodings. */ |
| extern unsigned long nios2_r2_reg_range_mappings[]; |
| extern const int nios2_num_r2_reg_range_mappings; |
| #ifdef __cplusplus |
| } |
| #endif |
| #endif /* _NIOS2_H */ |
| /contrib/toolchain/binutils/include/opcode/nios2r1.h |
|---|
| 0,0 → 1,474 |
| /* Nios II R1 opcode list for GAS, the GNU assembler. |
| Copyright (C) 2013-2015 Free Software Foundation, Inc. |
| Contributed by Mentor Graphics, Inc. |
| This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. |
| GAS/GDB is free software; you can redistribute it and/or modify |
| it under the terms of the GNU General Public License as published by |
| the Free Software Foundation; either version 3, or (at your option) |
| any later version. |
| GAS/GDB is distributed in the hope that it will be useful, |
| but WITHOUT ANY WARRANTY; without even the implied warranty of |
| MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| GNU General Public License for more details. |
| You should have received a copy of the GNU General Public License |
| along with GAS or GDB; see the file COPYING3. If not, write to |
| the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
| Boston, MA 02110-1301, USA. */ |
| #ifndef _NIOS2R1_H_ |
| #define _NIOS2R1_H_ |
| /* R1 fields. */ |
| #define IW_R1_OP_LSB 0 |
| #define IW_R1_OP_SIZE 6 |
| #define IW_R1_OP_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R1_OP_SIZE)) |
| #define IW_R1_OP_SHIFTED_MASK (IW_R1_OP_UNSHIFTED_MASK << IW_R1_OP_LSB) |
| #define GET_IW_R1_OP(W) (((W) >> IW_R1_OP_LSB) & IW_R1_OP_UNSHIFTED_MASK) |
| #define SET_IW_R1_OP(V) (((V) & IW_R1_OP_UNSHIFTED_MASK) << IW_R1_OP_LSB) |
| #define IW_I_A_LSB 27 |
| #define IW_I_A_SIZE 5 |
| #define IW_I_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_I_A_SIZE)) |
| #define IW_I_A_SHIFTED_MASK (IW_I_A_UNSHIFTED_MASK << IW_I_A_LSB) |
| #define GET_IW_I_A(W) (((W) >> IW_I_A_LSB) & IW_I_A_UNSHIFTED_MASK) |
| #define SET_IW_I_A(V) (((V) & IW_I_A_UNSHIFTED_MASK) << IW_I_A_LSB) |
| #define IW_I_B_LSB 22 |
| #define IW_I_B_SIZE 5 |
| #define IW_I_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_I_B_SIZE)) |
| #define IW_I_B_SHIFTED_MASK (IW_I_B_UNSHIFTED_MASK << IW_I_B_LSB) |
| #define GET_IW_I_B(W) (((W) >> IW_I_B_LSB) & IW_I_B_UNSHIFTED_MASK) |
| #define SET_IW_I_B(V) (((V) & IW_I_B_UNSHIFTED_MASK) << IW_I_B_LSB) |
| #define IW_I_IMM16_LSB 6 |
| #define IW_I_IMM16_SIZE 16 |
| #define IW_I_IMM16_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_I_IMM16_SIZE)) |
| #define IW_I_IMM16_SHIFTED_MASK (IW_I_IMM16_UNSHIFTED_MASK << IW_I_IMM16_LSB) |
| #define GET_IW_I_IMM16(W) (((W) >> IW_I_IMM16_LSB) & IW_I_IMM16_UNSHIFTED_MASK) |
| #define SET_IW_I_IMM16(V) (((V) & IW_I_IMM16_UNSHIFTED_MASK) << IW_I_IMM16_LSB) |
| #define IW_R_A_LSB 27 |
| #define IW_R_A_SIZE 5 |
| #define IW_R_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R_A_SIZE)) |
| #define IW_R_A_SHIFTED_MASK (IW_R_A_UNSHIFTED_MASK << IW_R_A_LSB) |
| #define GET_IW_R_A(W) (((W) >> IW_R_A_LSB) & IW_R_A_UNSHIFTED_MASK) |
| #define SET_IW_R_A(V) (((V) & IW_R_A_UNSHIFTED_MASK) << IW_R_A_LSB) |
| #define IW_R_B_LSB 22 |
| #define IW_R_B_SIZE 5 |
| #define IW_R_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R_B_SIZE)) |
| #define IW_R_B_SHIFTED_MASK (IW_R_B_UNSHIFTED_MASK << IW_R_B_LSB) |
| #define GET_IW_R_B(W) (((W) >> IW_R_B_LSB) & IW_R_B_UNSHIFTED_MASK) |
| #define SET_IW_R_B(V) (((V) & IW_R_B_UNSHIFTED_MASK) << IW_R_B_LSB) |
| #define IW_R_C_LSB 17 |
| #define IW_R_C_SIZE 5 |
| #define IW_R_C_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R_C_SIZE)) |
| #define IW_R_C_SHIFTED_MASK (IW_R_C_UNSHIFTED_MASK << IW_R_C_LSB) |
| #define GET_IW_R_C(W) (((W) >> IW_R_C_LSB) & IW_R_C_UNSHIFTED_MASK) |
| #define SET_IW_R_C(V) (((V) & IW_R_C_UNSHIFTED_MASK) << IW_R_C_LSB) |
| #define IW_R_OPX_LSB 11 |
| #define IW_R_OPX_SIZE 6 |
| #define IW_R_OPX_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R_OPX_SIZE)) |
| #define IW_R_OPX_SHIFTED_MASK (IW_R_OPX_UNSHIFTED_MASK << IW_R_OPX_LSB) |
| #define GET_IW_R_OPX(W) (((W) >> IW_R_OPX_LSB) & IW_R_OPX_UNSHIFTED_MASK) |
| #define SET_IW_R_OPX(V) (((V) & IW_R_OPX_UNSHIFTED_MASK) << IW_R_OPX_LSB) |
| #define IW_R_IMM5_LSB 6 |
| #define IW_R_IMM5_SIZE 5 |
| #define IW_R_IMM5_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R_IMM5_SIZE)) |
| #define IW_R_IMM5_SHIFTED_MASK (IW_R_IMM5_UNSHIFTED_MASK << IW_R_IMM5_LSB) |
| #define GET_IW_R_IMM5(W) (((W) >> IW_R_IMM5_LSB) & IW_R_IMM5_UNSHIFTED_MASK) |
| #define SET_IW_R_IMM5(V) (((V) & IW_R_IMM5_UNSHIFTED_MASK) << IW_R_IMM5_LSB) |
| #define IW_J_IMM26_LSB 6 |
| #define IW_J_IMM26_SIZE 26 |
| #define IW_J_IMM26_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_J_IMM26_SIZE)) |
| #define IW_J_IMM26_SHIFTED_MASK (IW_J_IMM26_UNSHIFTED_MASK << IW_J_IMM26_LSB) |
| #define GET_IW_J_IMM26(W) (((W) >> IW_J_IMM26_LSB) & IW_J_IMM26_UNSHIFTED_MASK) |
| #define SET_IW_J_IMM26(V) (((V) & IW_J_IMM26_UNSHIFTED_MASK) << IW_J_IMM26_LSB) |
| #define IW_CUSTOM_A_LSB 27 |
| #define IW_CUSTOM_A_SIZE 5 |
| #define IW_CUSTOM_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_CUSTOM_A_SIZE)) |
| #define IW_CUSTOM_A_SHIFTED_MASK (IW_CUSTOM_A_UNSHIFTED_MASK << IW_CUSTOM_A_LSB) |
| #define GET_IW_CUSTOM_A(W) (((W) >> IW_CUSTOM_A_LSB) & IW_CUSTOM_A_UNSHIFTED_MASK) |
| #define SET_IW_CUSTOM_A(V) (((V) & IW_CUSTOM_A_UNSHIFTED_MASK) << IW_CUSTOM_A_LSB) |
| #define IW_CUSTOM_B_LSB 22 |
| #define IW_CUSTOM_B_SIZE 5 |
| #define IW_CUSTOM_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_CUSTOM_B_SIZE)) |
| #define IW_CUSTOM_B_SHIFTED_MASK (IW_CUSTOM_B_UNSHIFTED_MASK << IW_CUSTOM_B_LSB) |
| #define GET_IW_CUSTOM_B(W) (((W) >> IW_CUSTOM_B_LSB) & IW_CUSTOM_B_UNSHIFTED_MASK) |
| #define SET_IW_CUSTOM_B(V) (((V) & IW_CUSTOM_B_UNSHIFTED_MASK) << IW_CUSTOM_B_LSB) |
| #define IW_CUSTOM_C_LSB 17 |
| #define IW_CUSTOM_C_SIZE 5 |
| #define IW_CUSTOM_C_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_CUSTOM_C_SIZE)) |
| #define IW_CUSTOM_C_SHIFTED_MASK (IW_CUSTOM_C_UNSHIFTED_MASK << IW_CUSTOM_C_LSB) |
| #define GET_IW_CUSTOM_C(W) (((W) >> IW_CUSTOM_C_LSB) & IW_CUSTOM_C_UNSHIFTED_MASK) |
| #define SET_IW_CUSTOM_C(V) (((V) & IW_CUSTOM_C_UNSHIFTED_MASK) << IW_CUSTOM_C_LSB) |
| #define IW_CUSTOM_READA_LSB 16 |
| #define IW_CUSTOM_READA_SIZE 1 |
| #define IW_CUSTOM_READA_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_CUSTOM_READA_SIZE)) |
| #define IW_CUSTOM_READA_SHIFTED_MASK (IW_CUSTOM_READA_UNSHIFTED_MASK << IW_CUSTOM_READA_LSB) |
| #define GET_IW_CUSTOM_READA(W) (((W) >> IW_CUSTOM_READA_LSB) & IW_CUSTOM_READA_UNSHIFTED_MASK) |
| #define SET_IW_CUSTOM_READA(V) (((V) & IW_CUSTOM_READA_UNSHIFTED_MASK) << IW_CUSTOM_READA_LSB) |
| #define IW_CUSTOM_READB_LSB 15 |
| #define IW_CUSTOM_READB_SIZE 1 |
| #define IW_CUSTOM_READB_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_CUSTOM_READB_SIZE)) |
| #define IW_CUSTOM_READB_SHIFTED_MASK (IW_CUSTOM_READB_UNSHIFTED_MASK << IW_CUSTOM_READB_LSB) |
| #define GET_IW_CUSTOM_READB(W) (((W) >> IW_CUSTOM_READB_LSB) & IW_CUSTOM_READB_UNSHIFTED_MASK) |
| #define SET_IW_CUSTOM_READB(V) (((V) & IW_CUSTOM_READB_UNSHIFTED_MASK) << IW_CUSTOM_READB_LSB) |
| #define IW_CUSTOM_READC_LSB 14 |
| #define IW_CUSTOM_READC_SIZE 1 |
| #define IW_CUSTOM_READC_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_CUSTOM_READC_SIZE)) |
| #define IW_CUSTOM_READC_SHIFTED_MASK (IW_CUSTOM_READC_UNSHIFTED_MASK << IW_CUSTOM_READC_LSB) |
| #define GET_IW_CUSTOM_READC(W) (((W) >> IW_CUSTOM_READC_LSB) & IW_CUSTOM_READC_UNSHIFTED_MASK) |
| #define SET_IW_CUSTOM_READC(V) (((V) & IW_CUSTOM_READC_UNSHIFTED_MASK) << IW_CUSTOM_READC_LSB) |
| #define IW_CUSTOM_N_LSB 6 |
| #define IW_CUSTOM_N_SIZE 8 |
| #define IW_CUSTOM_N_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_CUSTOM_N_SIZE)) |
| #define IW_CUSTOM_N_SHIFTED_MASK (IW_CUSTOM_N_UNSHIFTED_MASK << IW_CUSTOM_N_LSB) |
| #define GET_IW_CUSTOM_N(W) (((W) >> IW_CUSTOM_N_LSB) & IW_CUSTOM_N_UNSHIFTED_MASK) |
| #define SET_IW_CUSTOM_N(V) (((V) & IW_CUSTOM_N_UNSHIFTED_MASK) << IW_CUSTOM_N_LSB) |
| /* R1 opcodes. */ |
| #define R1_OP_CALL 0 |
| #define R1_OP_JMPI 1 |
| #define R1_OP_LDBU 3 |
| #define R1_OP_ADDI 4 |
| #define R1_OP_STB 5 |
| #define R1_OP_BR 6 |
| #define R1_OP_LDB 7 |
| #define R1_OP_CMPGEI 8 |
| #define R1_OP_LDHU 11 |
| #define R1_OP_ANDI 12 |
| #define R1_OP_STH 13 |
| #define R1_OP_BGE 14 |
| #define R1_OP_LDH 15 |
| #define R1_OP_CMPLTI 16 |
| #define R1_OP_INITDA 19 |
| #define R1_OP_ORI 20 |
| #define R1_OP_STW 21 |
| #define R1_OP_BLT 22 |
| #define R1_OP_LDW 23 |
| #define R1_OP_CMPNEI 24 |
| #define R1_OP_FLUSHDA 27 |
| #define R1_OP_XORI 28 |
| #define R1_OP_BNE 30 |
| #define R1_OP_CMPEQI 32 |
| #define R1_OP_LDBUIO 35 |
| #define R1_OP_MULI 36 |
| #define R1_OP_STBIO 37 |
| #define R1_OP_BEQ 38 |
| #define R1_OP_LDBIO 39 |
| #define R1_OP_CMPGEUI 40 |
| #define R1_OP_LDHUIO 43 |
| #define R1_OP_ANDHI 44 |
| #define R1_OP_STHIO 45 |
| #define R1_OP_BGEU 46 |
| #define R1_OP_LDHIO 47 |
| #define R1_OP_CMPLTUI 48 |
| #define R1_OP_CUSTOM 50 |
| #define R1_OP_INITD 51 |
| #define R1_OP_ORHI 52 |
| #define R1_OP_STWIO 53 |
| #define R1_OP_BLTU 54 |
| #define R1_OP_LDWIO 55 |
| #define R1_OP_RDPRS 56 |
| #define R1_OP_OPX 58 |
| #define R1_OP_FLUSHD 59 |
| #define R1_OP_XORHI 60 |
| #define R1_OPX_ERET 1 |
| #define R1_OPX_ROLI 2 |
| #define R1_OPX_ROL 3 |
| #define R1_OPX_FLUSHP 4 |
| #define R1_OPX_RET 5 |
| #define R1_OPX_NOR 6 |
| #define R1_OPX_MULXUU 7 |
| #define R1_OPX_CMPGE 8 |
| #define R1_OPX_BRET 9 |
| #define R1_OPX_ROR 11 |
| #define R1_OPX_FLUSHI 12 |
| #define R1_OPX_JMP 13 |
| #define R1_OPX_AND 14 |
| #define R1_OPX_CMPLT 16 |
| #define R1_OPX_SLLI 18 |
| #define R1_OPX_SLL 19 |
| #define R1_OPX_WRPRS 20 |
| #define R1_OPX_OR 22 |
| #define R1_OPX_MULXSU 23 |
| #define R1_OPX_CMPNE 24 |
| #define R1_OPX_SRLI 26 |
| #define R1_OPX_SRL 27 |
| #define R1_OPX_NEXTPC 28 |
| #define R1_OPX_CALLR 29 |
| #define R1_OPX_XOR 30 |
| #define R1_OPX_MULXSS 31 |
| #define R1_OPX_CMPEQ 32 |
| #define R1_OPX_DIVU 36 |
| #define R1_OPX_DIV 37 |
| #define R1_OPX_RDCTL 38 |
| #define R1_OPX_MUL 39 |
| #define R1_OPX_CMPGEU 40 |
| #define R1_OPX_INITI 41 |
| #define R1_OPX_TRAP 45 |
| #define R1_OPX_WRCTL 46 |
| #define R1_OPX_CMPLTU 48 |
| #define R1_OPX_ADD 49 |
| #define R1_OPX_BREAK 52 |
| #define R1_OPX_SYNC 54 |
| #define R1_OPX_SUB 57 |
| #define R1_OPX_SRAI 58 |
| #define R1_OPX_SRA 59 |
| /* Some convenience macros for R1 encodings, for use in instruction tables. |
| MATCH_R1_OPX0(NAME) and MASK_R1_OPX0 are used for R-type instructions |
| with 3 register operands and constant 0 in the immediate field. |
| The general forms are MATCH_R1_OPX(NAME, A, B, C) where the arguments specify |
| constant values and MASK_R1_OPX(A, B, C, N) where the arguments are booleans |
| that are true if the field should be included in the mask. |
| */ |
| #define MATCH_R1_OP(NAME) \ |
| (SET_IW_R1_OP (R1_OP_##NAME)) |
| #define MASK_R1_OP \ |
| IW_R1_OP_SHIFTED_MASK |
| #define MATCH_R1_OPX0(NAME) \ |
| (SET_IW_R1_OP (R1_OP_OPX) | SET_IW_R_OPX (R1_OPX_##NAME)) |
| #define MASK_R1_OPX0 \ |
| (IW_R1_OP_SHIFTED_MASK | IW_R_OPX_SHIFTED_MASK | IW_R_IMM5_SHIFTED_MASK) |
| #define MATCH_R1_OPX(NAME, A, B, C) \ |
| (MATCH_R1_OPX0 (NAME) | SET_IW_R_A (A) | SET_IW_R_B (B) | SET_IW_R_C (C)) |
| #define MASK_R1_OPX(A, B, C, N) \ |
| (IW_R1_OP_SHIFTED_MASK | IW_R_OPX_SHIFTED_MASK \ |
| | (A ? IW_R_A_SHIFTED_MASK : 0) \ |
| | (B ? IW_R_B_SHIFTED_MASK : 0) \ |
| | (C ? IW_R_C_SHIFTED_MASK : 0) \ |
| | (N ? IW_R_IMM5_SHIFTED_MASK : 0)) |
| /* And here's the match/mask macros for the R1 instruction set. */ |
| #define MATCH_R1_ADD MATCH_R1_OPX0 (ADD) |
| #define MASK_R1_ADD MASK_R1_OPX0 |
| #define MATCH_R1_ADDI MATCH_R1_OP (ADDI) |
| #define MASK_R1_ADDI MASK_R1_OP |
| #define MATCH_R1_AND MATCH_R1_OPX0 (AND) |
| #define MASK_R1_AND MASK_R1_OPX0 |
| #define MATCH_R1_ANDHI MATCH_R1_OP (ANDHI) |
| #define MASK_R1_ANDHI MASK_R1_OP |
| #define MATCH_R1_ANDI MATCH_R1_OP (ANDI) |
| #define MASK_R1_ANDI MASK_R1_OP |
| #define MATCH_R1_BEQ MATCH_R1_OP (BEQ) |
| #define MASK_R1_BEQ MASK_R1_OP |
| #define MATCH_R1_BGE MATCH_R1_OP (BGE) |
| #define MASK_R1_BGE MASK_R1_OP |
| #define MATCH_R1_BGEU MATCH_R1_OP (BGEU) |
| #define MASK_R1_BGEU MASK_R1_OP |
| #define MATCH_R1_BGT MATCH_R1_OP (BLT) |
| #define MASK_R1_BGT MASK_R1_OP |
| #define MATCH_R1_BGTU MATCH_R1_OP (BLTU) |
| #define MASK_R1_BGTU MASK_R1_OP |
| #define MATCH_R1_BLE MATCH_R1_OP (BGE) |
| #define MASK_R1_BLE MASK_R1_OP |
| #define MATCH_R1_BLEU MATCH_R1_OP (BGEU) |
| #define MASK_R1_BLEU MASK_R1_OP |
| #define MATCH_R1_BLT MATCH_R1_OP (BLT) |
| #define MASK_R1_BLT MASK_R1_OP |
| #define MATCH_R1_BLTU MATCH_R1_OP (BLTU) |
| #define MASK_R1_BLTU MASK_R1_OP |
| #define MATCH_R1_BNE MATCH_R1_OP (BNE) |
| #define MASK_R1_BNE MASK_R1_OP |
| #define MATCH_R1_BR MATCH_R1_OP (BR) |
| #define MASK_R1_BR MASK_R1_OP | IW_I_A_SHIFTED_MASK | IW_I_B_SHIFTED_MASK |
| #define MATCH_R1_BREAK MATCH_R1_OPX (BREAK, 0, 0, 0x1e) |
| #define MASK_R1_BREAK MASK_R1_OPX (1, 1, 1, 0) |
| #define MATCH_R1_BRET MATCH_R1_OPX (BRET, 0x1e, 0, 0) |
| #define MASK_R1_BRET MASK_R1_OPX (1, 1, 1, 1) |
| #define MATCH_R1_CALL MATCH_R1_OP (CALL) |
| #define MASK_R1_CALL MASK_R1_OP |
| #define MATCH_R1_CALLR MATCH_R1_OPX (CALLR, 0, 0, 0x1f) |
| #define MASK_R1_CALLR MASK_R1_OPX (0, 1, 1, 1) |
| #define MATCH_R1_CMPEQ MATCH_R1_OPX0 (CMPEQ) |
| #define MASK_R1_CMPEQ MASK_R1_OPX0 |
| #define MATCH_R1_CMPEQI MATCH_R1_OP (CMPEQI) |
| #define MASK_R1_CMPEQI MASK_R1_OP |
| #define MATCH_R1_CMPGE MATCH_R1_OPX0 (CMPGE) |
| #define MASK_R1_CMPGE MASK_R1_OPX0 |
| #define MATCH_R1_CMPGEI MATCH_R1_OP (CMPGEI) |
| #define MASK_R1_CMPGEI MASK_R1_OP |
| #define MATCH_R1_CMPGEU MATCH_R1_OPX0 (CMPGEU) |
| #define MASK_R1_CMPGEU MASK_R1_OPX0 |
| #define MATCH_R1_CMPGEUI MATCH_R1_OP (CMPGEUI) |
| #define MASK_R1_CMPGEUI MASK_R1_OP |
| #define MATCH_R1_CMPGT MATCH_R1_OPX0 (CMPLT) |
| #define MASK_R1_CMPGT MASK_R1_OPX0 |
| #define MATCH_R1_CMPGTI MATCH_R1_OP (CMPGEI) |
| #define MASK_R1_CMPGTI MASK_R1_OP |
| #define MATCH_R1_CMPGTU MATCH_R1_OPX0 (CMPLTU) |
| #define MASK_R1_CMPGTU MASK_R1_OPX0 |
| #define MATCH_R1_CMPGTUI MATCH_R1_OP (CMPGEUI) |
| #define MASK_R1_CMPGTUI MASK_R1_OP |
| #define MATCH_R1_CMPLE MATCH_R1_OPX0 (CMPGE) |
| #define MASK_R1_CMPLE MASK_R1_OPX0 |
| #define MATCH_R1_CMPLEI MATCH_R1_OP (CMPLTI) |
| #define MASK_R1_CMPLEI MASK_R1_OP |
| #define MATCH_R1_CMPLEU MATCH_R1_OPX0 (CMPGEU) |
| #define MASK_R1_CMPLEU MASK_R1_OPX0 |
| #define MATCH_R1_CMPLEUI MATCH_R1_OP (CMPLTUI) |
| #define MASK_R1_CMPLEUI MASK_R1_OP |
| #define MATCH_R1_CMPLT MATCH_R1_OPX0 (CMPLT) |
| #define MASK_R1_CMPLT MASK_R1_OPX0 |
| #define MATCH_R1_CMPLTI MATCH_R1_OP (CMPLTI) |
| #define MASK_R1_CMPLTI MASK_R1_OP |
| #define MATCH_R1_CMPLTU MATCH_R1_OPX0 (CMPLTU) |
| #define MASK_R1_CMPLTU MASK_R1_OPX0 |
| #define MATCH_R1_CMPLTUI MATCH_R1_OP (CMPLTUI) |
| #define MASK_R1_CMPLTUI MASK_R1_OP |
| #define MATCH_R1_CMPNE MATCH_R1_OPX0 (CMPNE) |
| #define MASK_R1_CMPNE MASK_R1_OPX0 |
| #define MATCH_R1_CMPNEI MATCH_R1_OP (CMPNEI) |
| #define MASK_R1_CMPNEI MASK_R1_OP |
| #define MATCH_R1_CUSTOM MATCH_R1_OP (CUSTOM) |
| #define MASK_R1_CUSTOM MASK_R1_OP |
| #define MATCH_R1_DIV MATCH_R1_OPX0 (DIV) |
| #define MASK_R1_DIV MASK_R1_OPX0 |
| #define MATCH_R1_DIVU MATCH_R1_OPX0 (DIVU) |
| #define MASK_R1_DIVU MASK_R1_OPX0 |
| #define MATCH_R1_ERET MATCH_R1_OPX (ERET, 0x1d, 0x1e, 0) |
| #define MASK_R1_ERET MASK_R1_OPX (1, 1, 1, 1) |
| #define MATCH_R1_FLUSHD MATCH_R1_OP (FLUSHD) | SET_IW_I_B (0) |
| #define MASK_R1_FLUSHD MASK_R1_OP | IW_I_B_SHIFTED_MASK |
| #define MATCH_R1_FLUSHDA MATCH_R1_OP (FLUSHDA) | SET_IW_I_B (0) |
| #define MASK_R1_FLUSHDA MASK_R1_OP | IW_I_B_SHIFTED_MASK |
| #define MATCH_R1_FLUSHI MATCH_R1_OPX (FLUSHI, 0, 0, 0) |
| #define MASK_R1_FLUSHI MASK_R1_OPX (0, 1, 1, 1) |
| #define MATCH_R1_FLUSHP MATCH_R1_OPX (FLUSHP, 0, 0, 0) |
| #define MASK_R1_FLUSHP MASK_R1_OPX (1, 1, 1, 1) |
| #define MATCH_R1_INITD MATCH_R1_OP (INITD) | SET_IW_I_B (0) |
| #define MASK_R1_INITD MASK_R1_OP | IW_I_B_SHIFTED_MASK |
| #define MATCH_R1_INITDA MATCH_R1_OP (INITDA) | SET_IW_I_B (0) |
| #define MASK_R1_INITDA MASK_R1_OP | IW_I_B_SHIFTED_MASK |
| #define MATCH_R1_INITI MATCH_R1_OPX (INITI, 0, 0, 0) |
| #define MASK_R1_INITI MASK_R1_OPX (0, 1, 1, 1) |
| #define MATCH_R1_JMP MATCH_R1_OPX (JMP, 0, 0, 0) |
| #define MASK_R1_JMP MASK_R1_OPX (0, 1, 1, 1) |
| #define MATCH_R1_JMPI MATCH_R1_OP (JMPI) |
| #define MASK_R1_JMPI MASK_R1_OP |
| #define MATCH_R1_LDB MATCH_R1_OP (LDB) |
| #define MASK_R1_LDB MASK_R1_OP |
| #define MATCH_R1_LDBIO MATCH_R1_OP (LDBIO) |
| #define MASK_R1_LDBIO MASK_R1_OP |
| #define MATCH_R1_LDBU MATCH_R1_OP (LDBU) |
| #define MASK_R1_LDBU MASK_R1_OP |
| #define MATCH_R1_LDBUIO MATCH_R1_OP (LDBUIO) |
| #define MASK_R1_LDBUIO MASK_R1_OP |
| #define MATCH_R1_LDH MATCH_R1_OP (LDH) |
| #define MASK_R1_LDH MASK_R1_OP |
| #define MATCH_R1_LDHIO MATCH_R1_OP (LDHIO) |
| #define MASK_R1_LDHIO MASK_R1_OP |
| #define MATCH_R1_LDHU MATCH_R1_OP (LDHU) |
| #define MASK_R1_LDHU MASK_R1_OP |
| #define MATCH_R1_LDHUIO MATCH_R1_OP (LDHUIO) |
| #define MASK_R1_LDHUIO MASK_R1_OP |
| #define MATCH_R1_LDW MATCH_R1_OP (LDW) |
| #define MASK_R1_LDW MASK_R1_OP |
| #define MATCH_R1_LDWIO MATCH_R1_OP (LDWIO) |
| #define MASK_R1_LDWIO MASK_R1_OP |
| #define MATCH_R1_MOV MATCH_R1_OPX (ADD, 0, 0, 0) |
| #define MASK_R1_MOV MASK_R1_OPX (0, 1, 0, 1) |
| #define MATCH_R1_MOVHI MATCH_R1_OP (ORHI) | SET_IW_I_A (0) |
| #define MASK_R1_MOVHI MASK_R1_OP | IW_I_A_SHIFTED_MASK |
| #define MATCH_R1_MOVI MATCH_R1_OP (ADDI) | SET_IW_I_A (0) |
| #define MASK_R1_MOVI MASK_R1_OP | IW_I_A_SHIFTED_MASK |
| #define MATCH_R1_MOVUI MATCH_R1_OP (ORI) | SET_IW_I_A (0) |
| #define MASK_R1_MOVUI MASK_R1_OP | IW_I_A_SHIFTED_MASK |
| #define MATCH_R1_MUL MATCH_R1_OPX0 (MUL) |
| #define MASK_R1_MUL MASK_R1_OPX0 |
| #define MATCH_R1_MULI MATCH_R1_OP (MULI) |
| #define MASK_R1_MULI MASK_R1_OP |
| #define MATCH_R1_MULXSS MATCH_R1_OPX0 (MULXSS) |
| #define MASK_R1_MULXSS MASK_R1_OPX0 |
| #define MATCH_R1_MULXSU MATCH_R1_OPX0 (MULXSU) |
| #define MASK_R1_MULXSU MASK_R1_OPX0 |
| #define MATCH_R1_MULXUU MATCH_R1_OPX0 (MULXUU) |
| #define MASK_R1_MULXUU MASK_R1_OPX0 |
| #define MATCH_R1_NEXTPC MATCH_R1_OPX (NEXTPC, 0, 0, 0) |
| #define MASK_R1_NEXTPC MASK_R1_OPX (1, 1, 0, 1) |
| #define MATCH_R1_NOP MATCH_R1_OPX (ADD, 0, 0, 0) |
| #define MASK_R1_NOP MASK_R1_OPX (1, 1, 1, 1) |
| #define MATCH_R1_NOR MATCH_R1_OPX0 (NOR) |
| #define MASK_R1_NOR MASK_R1_OPX0 |
| #define MATCH_R1_OR MATCH_R1_OPX0 (OR) |
| #define MASK_R1_OR MASK_R1_OPX0 |
| #define MATCH_R1_ORHI MATCH_R1_OP (ORHI) |
| #define MASK_R1_ORHI MASK_R1_OP |
| #define MATCH_R1_ORI MATCH_R1_OP (ORI) |
| #define MASK_R1_ORI MASK_R1_OP |
| #define MATCH_R1_RDCTL MATCH_R1_OPX (RDCTL, 0, 0, 0) |
| #define MASK_R1_RDCTL MASK_R1_OPX (1, 1, 0, 0) |
| #define MATCH_R1_RDPRS MATCH_R1_OP (RDPRS) |
| #define MASK_R1_RDPRS MASK_R1_OP |
| #define MATCH_R1_RET MATCH_R1_OPX (RET, 0x1f, 0, 0) |
| #define MASK_R1_RET MASK_R1_OPX (1, 1, 1, 1) |
| #define MATCH_R1_ROL MATCH_R1_OPX0 (ROL) |
| #define MASK_R1_ROL MASK_R1_OPX0 |
| #define MATCH_R1_ROLI MATCH_R1_OPX (ROLI, 0, 0, 0) |
| #define MASK_R1_ROLI MASK_R1_OPX (0, 1, 0, 0) |
| #define MATCH_R1_ROR MATCH_R1_OPX0 (ROR) |
| #define MASK_R1_ROR MASK_R1_OPX0 |
| #define MATCH_R1_SLL MATCH_R1_OPX0 (SLL) |
| #define MASK_R1_SLL MASK_R1_OPX0 |
| #define MATCH_R1_SLLI MATCH_R1_OPX (SLLI, 0, 0, 0) |
| #define MASK_R1_SLLI MASK_R1_OPX (0, 1, 0, 0) |
| #define MATCH_R1_SRA MATCH_R1_OPX0 (SRA) |
| #define MASK_R1_SRA MASK_R1_OPX0 |
| #define MATCH_R1_SRAI MATCH_R1_OPX (SRAI, 0, 0, 0) |
| #define MASK_R1_SRAI MASK_R1_OPX (0, 1, 0, 0) |
| #define MATCH_R1_SRL MATCH_R1_OPX0 (SRL) |
| #define MASK_R1_SRL MASK_R1_OPX0 |
| #define MATCH_R1_SRLI MATCH_R1_OPX (SRLI, 0, 0, 0) |
| #define MASK_R1_SRLI MASK_R1_OPX (0, 1, 0, 0) |
| #define MATCH_R1_STB MATCH_R1_OP (STB) |
| #define MASK_R1_STB MASK_R1_OP |
| #define MATCH_R1_STBIO MATCH_R1_OP (STBIO) |
| #define MASK_R1_STBIO MASK_R1_OP |
| #define MATCH_R1_STH MATCH_R1_OP (STH) |
| #define MASK_R1_STH MASK_R1_OP |
| #define MATCH_R1_STHIO MATCH_R1_OP (STHIO) |
| #define MASK_R1_STHIO MASK_R1_OP |
| #define MATCH_R1_STW MATCH_R1_OP (STW) |
| #define MASK_R1_STW MASK_R1_OP |
| #define MATCH_R1_STWIO MATCH_R1_OP (STWIO) |
| #define MASK_R1_STWIO MASK_R1_OP |
| #define MATCH_R1_SUB MATCH_R1_OPX0 (SUB) |
| #define MASK_R1_SUB MASK_R1_OPX0 |
| #define MATCH_R1_SUBI MATCH_R1_OP (ADDI) |
| #define MASK_R1_SUBI MASK_R1_OP |
| #define MATCH_R1_SYNC MATCH_R1_OPX (SYNC, 0, 0, 0) |
| #define MASK_R1_SYNC MASK_R1_OPX (1, 1, 1, 1) |
| #define MATCH_R1_TRAP MATCH_R1_OPX (TRAP, 0, 0, 0x1d) |
| #define MASK_R1_TRAP MASK_R1_OPX (1, 1, 1, 0) |
| #define MATCH_R1_WRCTL MATCH_R1_OPX (WRCTL, 0, 0, 0) |
| #define MASK_R1_WRCTL MASK_R1_OPX (0, 1, 1, 0) |
| #define MATCH_R1_WRPRS MATCH_R1_OPX (WRPRS, 0, 0, 0) |
| #define MASK_R1_WRPRS MASK_R1_OPX (0, 1, 0, 1) |
| #define MATCH_R1_XOR MATCH_R1_OPX0 (XOR) |
| #define MASK_R1_XOR MASK_R1_OPX0 |
| #define MATCH_R1_XORHI MATCH_R1_OP (XORHI) |
| #define MASK_R1_XORHI MASK_R1_OP |
| #define MATCH_R1_XORI MATCH_R1_OP (XORI) |
| #define MASK_R1_XORI MASK_R1_OP |
| #endif /* _NIOS2R1_H */ |
| /contrib/toolchain/binutils/include/opcode/nios2r2.h |
|---|
| 0,0 → 1,1081 |
| /* Nios II R2 opcode list for GAS, the GNU assembler. |
| Copyright (C) 2013-2015 Free Software Foundation, Inc. |
| Contributed by Mentor Graphics, Inc. |
| This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. |
| GAS/GDB is free software; you can redistribute it and/or modify |
| it under the terms of the GNU General Public License as published by |
| the Free Software Foundation; either version 3, or (at your option) |
| any later version. |
| GAS/GDB is distributed in the hope that it will be useful, |
| but WITHOUT ANY WARRANTY; without even the implied warranty of |
| MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| GNU General Public License for more details. |
| You should have received a copy of the GNU General Public License |
| along with GAS or GDB; see the file COPYING3. If not, write to |
| the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
| Boston, MA 02110-1301, USA. */ |
| #ifndef _NIOS2R2_H_ |
| #define _NIOS2R2_H_ |
| /* Fields for 32-bit R2 instructions. */ |
| #define IW_R2_OP_LSB 0 |
| #define IW_R2_OP_SIZE 6 |
| #define IW_R2_OP_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R2_OP_SIZE)) |
| #define IW_R2_OP_SHIFTED_MASK (IW_R2_OP_UNSHIFTED_MASK << IW_R2_OP_LSB) |
| #define GET_IW_R2_OP(W) (((W) >> IW_R2_OP_LSB) & IW_R2_OP_UNSHIFTED_MASK) |
| #define SET_IW_R2_OP(V) (((V) & IW_R2_OP_UNSHIFTED_MASK) << IW_R2_OP_LSB) |
| #define IW_L26_IMM26_LSB 6 |
| #define IW_L26_IMM26_SIZE 26 |
| #define IW_L26_IMM26_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_L26_IMM26_SIZE)) |
| #define IW_L26_IMM26_SHIFTED_MASK (IW_L26_IMM26_UNSHIFTED_MASK << IW_L26_IMM26_LSB) |
| #define GET_IW_L26_IMM26(W) (((W) >> IW_L26_IMM26_LSB) & IW_L26_IMM26_UNSHIFTED_MASK) |
| #define SET_IW_L26_IMM26(V) (((V) & IW_L26_IMM26_UNSHIFTED_MASK) << IW_L26_IMM26_LSB) |
| #define IW_F2I16_A_LSB 6 |
| #define IW_F2I16_A_SIZE 5 |
| #define IW_F2I16_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2I16_A_SIZE)) |
| #define IW_F2I16_A_SHIFTED_MASK (IW_F2I16_A_UNSHIFTED_MASK << IW_F2I16_A_LSB) |
| #define GET_IW_F2I16_A(W) (((W) >> IW_F2I16_A_LSB) & IW_F2I16_A_UNSHIFTED_MASK) |
| #define SET_IW_F2I16_A(V) (((V) & IW_F2I16_A_UNSHIFTED_MASK) << IW_F2I16_A_LSB) |
| #define IW_F2I16_B_LSB 11 |
| #define IW_F2I16_B_SIZE 5 |
| #define IW_F2I16_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2I16_B_SIZE)) |
| #define IW_F2I16_B_SHIFTED_MASK (IW_F2I16_B_UNSHIFTED_MASK << IW_F2I16_B_LSB) |
| #define GET_IW_F2I16_B(W) (((W) >> IW_F2I16_B_LSB) & IW_F2I16_B_UNSHIFTED_MASK) |
| #define SET_IW_F2I16_B(V) (((V) & IW_F2I16_B_UNSHIFTED_MASK) << IW_F2I16_B_LSB) |
| #define IW_F2I16_IMM16_LSB 16 |
| #define IW_F2I16_IMM16_SIZE 16 |
| #define IW_F2I16_IMM16_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2I16_IMM16_SIZE)) |
| #define IW_F2I16_IMM16_SHIFTED_MASK (IW_F2I16_IMM16_UNSHIFTED_MASK << IW_F2I16_IMM16_LSB) |
| #define GET_IW_F2I16_IMM16(W) (((W) >> IW_F2I16_IMM16_LSB) & IW_F2I16_IMM16_UNSHIFTED_MASK) |
| #define SET_IW_F2I16_IMM16(V) (((V) & IW_F2I16_IMM16_UNSHIFTED_MASK) << IW_F2I16_IMM16_LSB) |
| /* Common to all three I12-group formats F2X4I12, F1X4I12, F1X4L17. */ |
| #define IW_I12_X_LSB 28 |
| #define IW_I12_X_SIZE 4 |
| #define IW_I12_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_I12_X_SIZE)) |
| #define IW_I12_X_SHIFTED_MASK (IW_I12_X_UNSHIFTED_MASK << IW_I12_X_LSB) |
| #define GET_IW_I12_X(W) (((W) >> IW_I12_X_LSB) & IW_I12_X_UNSHIFTED_MASK) |
| #define SET_IW_I12_X(V) (((V) & IW_I12_X_UNSHIFTED_MASK) << IW_I12_X_LSB) |
| #define IW_F2X4I12_A_LSB 6 |
| #define IW_F2X4I12_A_SIZE 5 |
| #define IW_F2X4I12_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2X4I12_A_SIZE)) |
| #define IW_F2X4I12_A_SHIFTED_MASK (IW_F2X4I12_A_UNSHIFTED_MASK << IW_F2X4I12_A_LSB) |
| #define GET_IW_F2X4I12_A(W) (((W) >> IW_F2X4I12_A_LSB) & IW_F2X4I12_A_UNSHIFTED_MASK) |
| #define SET_IW_F2X4I12_A(V) (((V) & IW_F2X4I12_A_UNSHIFTED_MASK) << IW_F2X4I12_A_LSB) |
| #define IW_F2X4I12_B_LSB 11 |
| #define IW_F2X4I12_B_SIZE 5 |
| #define IW_F2X4I12_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2X4I12_B_SIZE)) |
| #define IW_F2X4I12_B_SHIFTED_MASK (IW_F2X4I12_B_UNSHIFTED_MASK << IW_F2X4I12_B_LSB) |
| #define GET_IW_F2X4I12_B(W) (((W) >> IW_F2X4I12_B_LSB) & IW_F2X4I12_B_UNSHIFTED_MASK) |
| #define SET_IW_F2X4I12_B(V) (((V) & IW_F2X4I12_B_UNSHIFTED_MASK) << IW_F2X4I12_B_LSB) |
| #define IW_F2X4I12_IMM12_LSB 16 |
| #define IW_F2X4I12_IMM12_SIZE 12 |
| #define IW_F2X4I12_IMM12_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2X4I12_IMM12_SIZE)) |
| #define IW_F2X4I12_IMM12_SHIFTED_MASK (IW_F2X4I12_IMM12_UNSHIFTED_MASK << IW_F2X4I12_IMM12_LSB) |
| #define GET_IW_F2X4I12_IMM12(W) (((W) >> IW_F2X4I12_IMM12_LSB) & IW_F2X4I12_IMM12_UNSHIFTED_MASK) |
| #define SET_IW_F2X4I12_IMM12(V) (((V) & IW_F2X4I12_IMM12_UNSHIFTED_MASK) << IW_F2X4I12_IMM12_LSB) |
| #define IW_F1X4I12_A_LSB 6 |
| #define IW_F1X4I12_A_SIZE 5 |
| #define IW_F1X4I12_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4I12_A_SIZE)) |
| #define IW_F1X4I12_A_SHIFTED_MASK (IW_F1X4I12_A_UNSHIFTED_MASK << IW_F1X4I12_A_LSB) |
| #define GET_IW_F1X4I12_A(W) (((W) >> IW_F1X4I12_A_LSB) & IW_F1X4I12_A_UNSHIFTED_MASK) |
| #define SET_IW_F1X4I12_A(V) (((V) & IW_F1X4I12_A_UNSHIFTED_MASK) << IW_F1X4I12_A_LSB) |
| #define IW_F1X4I12_X_LSB 11 |
| #define IW_F1X4I12_X_SIZE 5 |
| #define IW_F1X4I12_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4I12_X_SIZE)) |
| #define IW_F1X4I12_X_SHIFTED_MASK (IW_F1X4I12_X_UNSHIFTED_MASK << IW_F1X4I12_X_LSB) |
| #define GET_IW_F1X4I12_X(W) (((W) >> IW_F1X4I12_X_LSB) & IW_F1X4I12_X_UNSHIFTED_MASK) |
| #define SET_IW_F1X4I12_X(V) (((V) & IW_F1X4I12_X_UNSHIFTED_MASK) << IW_F1X4I12_X_LSB) |
| #define IW_F1X4I12_IMM12_LSB 16 |
| #define IW_F1X4I12_IMM12_SIZE 12 |
| #define IW_F1X4I12_IMM12_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4I12_IMM12_SIZE)) |
| #define IW_F1X4I12_IMM12_SHIFTED_MASK (IW_F1X4I12_IMM12_UNSHIFTED_MASK << IW_F1X4I12_IMM12_LSB) |
| #define GET_IW_F1X4I12_IMM12(W) (((W) >> IW_F1X4I12_IMM12_LSB) & IW_F1X4I12_IMM12_UNSHIFTED_MASK) |
| #define SET_IW_F1X4I12_IMM12(V) (((V) & IW_F1X4I12_IMM12_UNSHIFTED_MASK) << IW_F1X4I12_IMM12_LSB) |
| #define IW_F1X4L17_A_LSB 6 |
| #define IW_F1X4L17_A_SIZE 5 |
| #define IW_F1X4L17_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4L17_A_SIZE)) |
| #define IW_F1X4L17_A_SHIFTED_MASK (IW_F1X4L17_A_UNSHIFTED_MASK << IW_F1X4L17_A_LSB) |
| #define GET_IW_F1X4L17_A(W) (((W) >> IW_F1X4L17_A_LSB) & IW_F1X4L17_A_UNSHIFTED_MASK) |
| #define SET_IW_F1X4L17_A(V) (((V) & IW_F1X4L17_A_UNSHIFTED_MASK) << IW_F1X4L17_A_LSB) |
| #define IW_F1X4L17_ID_LSB 11 |
| #define IW_F1X4L17_ID_SIZE 1 |
| #define IW_F1X4L17_ID_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4L17_ID_SIZE)) |
| #define IW_F1X4L17_ID_SHIFTED_MASK (IW_F1X4L17_ID_UNSHIFTED_MASK << IW_F1X4L17_ID_LSB) |
| #define GET_IW_F1X4L17_ID(W) (((W) >> IW_F1X4L17_ID_LSB) & IW_F1X4L17_ID_UNSHIFTED_MASK) |
| #define SET_IW_F1X4L17_ID(V) (((V) & IW_F1X4L17_ID_UNSHIFTED_MASK) << IW_F1X4L17_ID_LSB) |
| #define IW_F1X4L17_WB_LSB 12 |
| #define IW_F1X4L17_WB_SIZE 1 |
| #define IW_F1X4L17_WB_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4L17_WB_SIZE)) |
| #define IW_F1X4L17_WB_SHIFTED_MASK (IW_F1X4L17_WB_UNSHIFTED_MASK << IW_F1X4L17_WB_LSB) |
| #define GET_IW_F1X4L17_WB(W) (((W) >> IW_F1X4L17_WB_LSB) & IW_F1X4L17_WB_UNSHIFTED_MASK) |
| #define SET_IW_F1X4L17_WB(V) (((V) & IW_F1X4L17_WB_UNSHIFTED_MASK) << IW_F1X4L17_WB_LSB) |
| #define IW_F1X4L17_RS_LSB 13 |
| #define IW_F1X4L17_RS_SIZE 1 |
| #define IW_F1X4L17_RS_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4L17_RS_SIZE)) |
| #define IW_F1X4L17_RS_SHIFTED_MASK (IW_F1X4L17_RS_UNSHIFTED_MASK << IW_F1X4L17_RS_LSB) |
| #define GET_IW_F1X4L17_RS(W) (((W) >> IW_F1X4L17_RS_LSB) & IW_F1X4L17_RS_UNSHIFTED_MASK) |
| #define SET_IW_F1X4L17_RS(V) (((V) & IW_F1X4L17_RS_UNSHIFTED_MASK) << IW_F1X4L17_RS_LSB) |
| #define IW_F1X4L17_PC_LSB 14 |
| #define IW_F1X4L17_PC_SIZE 1 |
| #define IW_F1X4L17_PC_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4L17_PC_SIZE)) |
| #define IW_F1X4L17_PC_SHIFTED_MASK (IW_F1X4L17_PC_UNSHIFTED_MASK << IW_F1X4L17_PC_LSB) |
| #define GET_IW_F1X4L17_PC(W) (((W) >> IW_F1X4L17_PC_LSB) & IW_F1X4L17_PC_UNSHIFTED_MASK) |
| #define SET_IW_F1X4L17_PC(V) (((V) & IW_F1X4L17_PC_UNSHIFTED_MASK) << IW_F1X4L17_PC_LSB) |
| #define IW_F1X4L17_RSV_LSB 15 |
| #define IW_F1X4L17_RSV_SIZE 1 |
| #define IW_F1X4L17_RSV_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4L17_RSV_SIZE)) |
| #define IW_F1X4L17_RSV_SHIFTED_MASK (IW_F1X4L17_RSV_UNSHIFTED_MASK << IW_F1X4L17_RSV_LSB) |
| #define GET_IW_F1X4L17_RSV(W) (((W) >> IW_F1X4L17_RSV_LSB) & IW_F1X4L17_RSV_UNSHIFTED_MASK) |
| #define SET_IW_F1X4L17_RSV(V) (((V) & IW_F1X4L17_RSV_UNSHIFTED_MASK) << IW_F1X4L17_RSV_LSB) |
| #define IW_F1X4L17_REGMASK_LSB 16 |
| #define IW_F1X4L17_REGMASK_SIZE 12 |
| #define IW_F1X4L17_REGMASK_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4L17_REGMASK_SIZE)) |
| #define IW_F1X4L17_REGMASK_SHIFTED_MASK (IW_F1X4L17_REGMASK_UNSHIFTED_MASK << IW_F1X4L17_REGMASK_LSB) |
| #define GET_IW_F1X4L17_REGMASK(W) (((W) >> IW_F1X4L17_REGMASK_LSB) & IW_F1X4L17_REGMASK_UNSHIFTED_MASK) |
| #define SET_IW_F1X4L17_REGMASK(V) (((V) & IW_F1X4L17_REGMASK_UNSHIFTED_MASK) << IW_F1X4L17_REGMASK_LSB) |
| /* Shared by OPX-group formats F3X6L5, F2X6L10, F3X6. */ |
| #define IW_OPX_X_LSB 26 |
| #define IW_OPX_X_SIZE 6 |
| #define IW_OPX_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_OPX_X_SIZE)) |
| #define IW_OPX_X_SHIFTED_MASK (IW_OPX_X_UNSHIFTED_MASK << IW_OPX_X_LSB) |
| #define GET_IW_OPX_X(W) (((W) >> IW_OPX_X_LSB) & IW_OPX_X_UNSHIFTED_MASK) |
| #define SET_IW_OPX_X(V) (((V) & IW_OPX_X_UNSHIFTED_MASK) << IW_OPX_X_LSB) |
| /* F3X6L5 accessors are also used for F3X6 formats. */ |
| #define IW_F3X6L5_A_LSB 6 |
| #define IW_F3X6L5_A_SIZE 5 |
| #define IW_F3X6L5_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X6L5_A_SIZE)) |
| #define IW_F3X6L5_A_SHIFTED_MASK (IW_F3X6L5_A_UNSHIFTED_MASK << IW_F3X6L5_A_LSB) |
| #define GET_IW_F3X6L5_A(W) (((W) >> IW_F3X6L5_A_LSB) & IW_F3X6L5_A_UNSHIFTED_MASK) |
| #define SET_IW_F3X6L5_A(V) (((V) & IW_F3X6L5_A_UNSHIFTED_MASK) << IW_F3X6L5_A_LSB) |
| #define IW_F3X6L5_B_LSB 11 |
| #define IW_F3X6L5_B_SIZE 5 |
| #define IW_F3X6L5_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X6L5_B_SIZE)) |
| #define IW_F3X6L5_B_SHIFTED_MASK (IW_F3X6L5_B_UNSHIFTED_MASK << IW_F3X6L5_B_LSB) |
| #define GET_IW_F3X6L5_B(W) (((W) >> IW_F3X6L5_B_LSB) & IW_F3X6L5_B_UNSHIFTED_MASK) |
| #define SET_IW_F3X6L5_B(V) (((V) & IW_F3X6L5_B_UNSHIFTED_MASK) << IW_F3X6L5_B_LSB) |
| #define IW_F3X6L5_C_LSB 16 |
| #define IW_F3X6L5_C_SIZE 5 |
| #define IW_F3X6L5_C_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X6L5_C_SIZE)) |
| #define IW_F3X6L5_C_SHIFTED_MASK (IW_F3X6L5_C_UNSHIFTED_MASK << IW_F3X6L5_C_LSB) |
| #define GET_IW_F3X6L5_C(W) (((W) >> IW_F3X6L5_C_LSB) & IW_F3X6L5_C_UNSHIFTED_MASK) |
| #define SET_IW_F3X6L5_C(V) (((V) & IW_F3X6L5_C_UNSHIFTED_MASK) << IW_F3X6L5_C_LSB) |
| #define IW_F3X6L5_IMM5_LSB 21 |
| #define IW_F3X6L5_IMM5_SIZE 5 |
| #define IW_F3X6L5_IMM5_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X6L5_IMM5_SIZE)) |
| #define IW_F3X6L5_IMM5_SHIFTED_MASK (IW_F3X6L5_IMM5_UNSHIFTED_MASK << IW_F3X6L5_IMM5_LSB) |
| #define GET_IW_F3X6L5_IMM5(W) (((W) >> IW_F3X6L5_IMM5_LSB) & IW_F3X6L5_IMM5_UNSHIFTED_MASK) |
| #define SET_IW_F3X6L5_IMM5(V) (((V) & IW_F3X6L5_IMM5_UNSHIFTED_MASK) << IW_F3X6L5_IMM5_LSB) |
| #define IW_F2X6L10_A_LSB 6 |
| #define IW_F2X6L10_A_SIZE 5 |
| #define IW_F2X6L10_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2X6L10_A_SIZE)) |
| #define IW_F2X6L10_A_SHIFTED_MASK (IW_F2X6L10_A_UNSHIFTED_MASK << IW_F2X6L10_A_LSB) |
| #define GET_IW_F2X6L10_A(W) (((W) >> IW_F2X6L10_A_LSB) & IW_F2X6L10_A_UNSHIFTED_MASK) |
| #define SET_IW_F2X6L10_A(V) (((V) & IW_F2X6L10_A_UNSHIFTED_MASK) << IW_F2X6L10_A_LSB) |
| #define IW_F2X6L10_B_LSB 11 |
| #define IW_F2X6L10_B_SIZE 5 |
| #define IW_F2X6L10_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2X6L10_B_SIZE)) |
| #define IW_F2X6L10_B_SHIFTED_MASK (IW_F2X6L10_B_UNSHIFTED_MASK << IW_F2X6L10_B_LSB) |
| #define GET_IW_F2X6L10_B(W) (((W) >> IW_F2X6L10_B_LSB) & IW_F2X6L10_B_UNSHIFTED_MASK) |
| #define SET_IW_F2X6L10_B(V) (((V) & IW_F2X6L10_B_UNSHIFTED_MASK) << IW_F2X6L10_B_LSB) |
| #define IW_F2X6L10_LSB_LSB 16 |
| #define IW_F2X6L10_LSB_SIZE 5 |
| #define IW_F2X6L10_LSB_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2X6L10_LSB_SIZE)) |
| #define IW_F2X6L10_LSB_SHIFTED_MASK (IW_F2X6L10_LSB_UNSHIFTED_MASK << IW_F2X6L10_LSB_LSB) |
| #define GET_IW_F2X6L10_LSB(W) (((W) >> IW_F2X6L10_LSB_LSB) & IW_F2X6L10_LSB_UNSHIFTED_MASK) |
| #define SET_IW_F2X6L10_LSB(V) (((V) & IW_F2X6L10_LSB_UNSHIFTED_MASK) << IW_F2X6L10_LSB_LSB) |
| #define IW_F2X6L10_MSB_LSB 21 |
| #define IW_F2X6L10_MSB_SIZE 5 |
| #define IW_F2X6L10_MSB_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2X6L10_MSB_SIZE)) |
| #define IW_F2X6L10_MSB_SHIFTED_MASK (IW_F2X6L10_MSB_UNSHIFTED_MASK << IW_F2X6L10_MSB_LSB) |
| #define GET_IW_F2X6L10_MSB(W) (((W) >> IW_F2X6L10_MSB_LSB) & IW_F2X6L10_MSB_UNSHIFTED_MASK) |
| #define SET_IW_F2X6L10_MSB(V) (((V) & IW_F2X6L10_MSB_UNSHIFTED_MASK) << IW_F2X6L10_MSB_LSB) |
| #define IW_F3X8_A_LSB 6 |
| #define IW_F3X8_A_SIZE 5 |
| #define IW_F3X8_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X8_A_SIZE)) |
| #define IW_F3X8_A_SHIFTED_MASK (IW_F3X8_A_UNSHIFTED_MASK << IW_F3X8_A_LSB) |
| #define GET_IW_F3X8_A(W) (((W) >> IW_F3X8_A_LSB) & IW_F3X8_A_UNSHIFTED_MASK) |
| #define SET_IW_F3X8_A(V) (((V) & IW_F3X8_A_UNSHIFTED_MASK) << IW_F3X8_A_LSB) |
| #define IW_F3X8_B_LSB 11 |
| #define IW_F3X8_B_SIZE 5 |
| #define IW_F3X8_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X8_B_SIZE)) |
| #define IW_F3X8_B_SHIFTED_MASK (IW_F3X8_B_UNSHIFTED_MASK << IW_F3X8_B_LSB) |
| #define GET_IW_F3X8_B(W) (((W) >> IW_F3X8_B_LSB) & IW_F3X8_B_UNSHIFTED_MASK) |
| #define SET_IW_F3X8_B(V) (((V) & IW_F3X8_B_UNSHIFTED_MASK) << IW_F3X8_B_LSB) |
| #define IW_F3X8_C_LSB 16 |
| #define IW_F3X8_C_SIZE 5 |
| #define IW_F3X8_C_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X8_C_SIZE)) |
| #define IW_F3X8_C_SHIFTED_MASK (IW_F3X8_C_UNSHIFTED_MASK << IW_F3X8_C_LSB) |
| #define GET_IW_F3X8_C(W) (((W) >> IW_F3X8_C_LSB) & IW_F3X8_C_UNSHIFTED_MASK) |
| #define SET_IW_F3X8_C(V) (((V) & IW_F3X8_C_UNSHIFTED_MASK) << IW_F3X8_C_LSB) |
| #define IW_F3X8_READA_LSB 21 |
| #define IW_F3X8_READA_SIZE 1 |
| #define IW_F3X8_READA_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X8_READA_SIZE)) |
| #define IW_F3X8_READA_SHIFTED_MASK (IW_F3X8_READA_UNSHIFTED_MASK << IW_F3X8_READA_LSB) |
| #define GET_IW_F3X8_READA(W) (((W) >> IW_F3X8_READA_LSB) & IW_F3X8_READA_UNSHIFTED_MASK) |
| #define SET_IW_F3X8_READA(V) (((V) & IW_F3X8_READA_UNSHIFTED_MASK) << IW_F3X8_READA_LSB) |
| #define IW_F3X8_READB_LSB 22 |
| #define IW_F3X8_READB_SIZE 1 |
| #define IW_F3X8_READB_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X8_READB_SIZE)) |
| #define IW_F3X8_READB_SHIFTED_MASK (IW_F3X8_READB_UNSHIFTED_MASK << IW_F3X8_READB_LSB) |
| #define GET_IW_F3X8_READB(W) (((W) >> IW_F3X8_READB_LSB) & IW_F3X8_READB_UNSHIFTED_MASK) |
| #define SET_IW_F3X8_READB(V) (((V) & IW_F3X8_READB_UNSHIFTED_MASK) << IW_F3X8_READB_LSB) |
| #define IW_F3X8_READC_LSB 23 |
| #define IW_F3X8_READC_SIZE 1 |
| #define IW_F3X8_READC_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X8_READC_SIZE)) |
| #define IW_F3X8_READC_SHIFTED_MASK (IW_F3X8_READC_UNSHIFTED_MASK << IW_F3X8_READC_LSB) |
| #define GET_IW_F3X8_READC(W) (((W) >> IW_F3X8_READC_LSB) & IW_F3X8_READC_UNSHIFTED_MASK) |
| #define SET_IW_F3X8_READC(V) (((V) & IW_F3X8_READC_UNSHIFTED_MASK) << IW_F3X8_READC_LSB) |
| #define IW_F3X8_N_LSB 24 |
| #define IW_F3X8_N_SIZE 8 |
| #define IW_F3X8_N_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X8_N_SIZE)) |
| #define IW_F3X8_N_SHIFTED_MASK (IW_F3X8_N_UNSHIFTED_MASK << IW_F3X8_N_LSB) |
| #define GET_IW_F3X8_N(W) (((W) >> IW_F3X8_N_LSB) & IW_F3X8_N_UNSHIFTED_MASK) |
| #define SET_IW_F3X8_N(V) (((V) & IW_F3X8_N_UNSHIFTED_MASK) << IW_F3X8_N_LSB) |
| /* 16-bit R2 fields. */ |
| #define IW_I10_IMM10_LSB 6 |
| #define IW_I10_IMM10_SIZE 10 |
| #define IW_I10_IMM10_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_I10_IMM10_SIZE)) |
| #define IW_I10_IMM10_SHIFTED_MASK (IW_I10_IMM10_UNSHIFTED_MASK << IW_I10_IMM10_LSB) |
| #define GET_IW_I10_IMM10(W) (((W) >> IW_I10_IMM10_LSB) & IW_I10_IMM10_UNSHIFTED_MASK) |
| #define SET_IW_I10_IMM10(V) (((V) & IW_I10_IMM10_UNSHIFTED_MASK) << IW_I10_IMM10_LSB) |
| #define IW_T1I7_A3_LSB 6 |
| #define IW_T1I7_A3_SIZE 3 |
| #define IW_T1I7_A3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T1I7_A3_SIZE)) |
| #define IW_T1I7_A3_SHIFTED_MASK (IW_T1I7_A3_UNSHIFTED_MASK << IW_T1I7_A3_LSB) |
| #define GET_IW_T1I7_A3(W) (((W) >> IW_T1I7_A3_LSB) & IW_T1I7_A3_UNSHIFTED_MASK) |
| #define SET_IW_T1I7_A3(V) (((V) & IW_T1I7_A3_UNSHIFTED_MASK) << IW_T1I7_A3_LSB) |
| #define IW_T1I7_IMM7_LSB 9 |
| #define IW_T1I7_IMM7_SIZE 7 |
| #define IW_T1I7_IMM7_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T1I7_IMM7_SIZE)) |
| #define IW_T1I7_IMM7_SHIFTED_MASK (IW_T1I7_IMM7_UNSHIFTED_MASK << IW_T1I7_IMM7_LSB) |
| #define GET_IW_T1I7_IMM7(W) (((W) >> IW_T1I7_IMM7_LSB) & IW_T1I7_IMM7_UNSHIFTED_MASK) |
| #define SET_IW_T1I7_IMM7(V) (((V) & IW_T1I7_IMM7_UNSHIFTED_MASK) << IW_T1I7_IMM7_LSB) |
| #define IW_T2I4_A3_LSB 6 |
| #define IW_T2I4_A3_SIZE 3 |
| #define IW_T2I4_A3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2I4_A3_SIZE)) |
| #define IW_T2I4_A3_SHIFTED_MASK (IW_T2I4_A3_UNSHIFTED_MASK << IW_T2I4_A3_LSB) |
| #define GET_IW_T2I4_A3(W) (((W) >> IW_T2I4_A3_LSB) & IW_T2I4_A3_UNSHIFTED_MASK) |
| #define SET_IW_T2I4_A3(V) (((V) & IW_T2I4_A3_UNSHIFTED_MASK) << IW_T2I4_A3_LSB) |
| #define IW_T2I4_B3_LSB 9 |
| #define IW_T2I4_B3_SIZE 3 |
| #define IW_T2I4_B3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2I4_B3_SIZE)) |
| #define IW_T2I4_B3_SHIFTED_MASK (IW_T2I4_B3_UNSHIFTED_MASK << IW_T2I4_B3_LSB) |
| #define GET_IW_T2I4_B3(W) (((W) >> IW_T2I4_B3_LSB) & IW_T2I4_B3_UNSHIFTED_MASK) |
| #define SET_IW_T2I4_B3(V) (((V) & IW_T2I4_B3_UNSHIFTED_MASK) << IW_T2I4_B3_LSB) |
| #define IW_T2I4_IMM4_LSB 12 |
| #define IW_T2I4_IMM4_SIZE 4 |
| #define IW_T2I4_IMM4_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2I4_IMM4_SIZE)) |
| #define IW_T2I4_IMM4_SHIFTED_MASK (IW_T2I4_IMM4_UNSHIFTED_MASK << IW_T2I4_IMM4_LSB) |
| #define GET_IW_T2I4_IMM4(W) (((W) >> IW_T2I4_IMM4_LSB) & IW_T2I4_IMM4_UNSHIFTED_MASK) |
| #define SET_IW_T2I4_IMM4(V) (((V) & IW_T2I4_IMM4_UNSHIFTED_MASK) << IW_T2I4_IMM4_LSB) |
| #define IW_T1X1I6_A3_LSB 6 |
| #define IW_T1X1I6_A3_SIZE 3 |
| #define IW_T1X1I6_A3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T1X1I6_A3_SIZE)) |
| #define IW_T1X1I6_A3_SHIFTED_MASK (IW_T1X1I6_A3_UNSHIFTED_MASK << IW_T1X1I6_A3_LSB) |
| #define GET_IW_T1X1I6_A3(W) (((W) >> IW_T1X1I6_A3_LSB) & IW_T1X1I6_A3_UNSHIFTED_MASK) |
| #define SET_IW_T1X1I6_A3(V) (((V) & IW_T1X1I6_A3_UNSHIFTED_MASK) << IW_T1X1I6_A3_LSB) |
| #define IW_T1X1I6_IMM6_LSB 9 |
| #define IW_T1X1I6_IMM6_SIZE 6 |
| #define IW_T1X1I6_IMM6_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T1X1I6_IMM6_SIZE)) |
| #define IW_T1X1I6_IMM6_SHIFTED_MASK (IW_T1X1I6_IMM6_UNSHIFTED_MASK << IW_T1X1I6_IMM6_LSB) |
| #define GET_IW_T1X1I6_IMM6(W) (((W) >> IW_T1X1I6_IMM6_LSB) & IW_T1X1I6_IMM6_UNSHIFTED_MASK) |
| #define SET_IW_T1X1I6_IMM6(V) (((V) & IW_T1X1I6_IMM6_UNSHIFTED_MASK) << IW_T1X1I6_IMM6_LSB) |
| #define IW_T1X1I6_X_LSB 15 |
| #define IW_T1X1I6_X_SIZE 1 |
| #define IW_T1X1I6_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T1X1I6_X_SIZE)) |
| #define IW_T1X1I6_X_SHIFTED_MASK (IW_T1X1I6_X_UNSHIFTED_MASK << IW_T1X1I6_X_LSB) |
| #define GET_IW_T1X1I6_X(W) (((W) >> IW_T1X1I6_X_LSB) & IW_T1X1I6_X_UNSHIFTED_MASK) |
| #define SET_IW_T1X1I6_X(V) (((V) & IW_T1X1I6_X_UNSHIFTED_MASK) << IW_T1X1I6_X_LSB) |
| #define IW_X1I7_IMM7_LSB 6 |
| #define IW_X1I7_IMM7_SIZE 7 |
| #define IW_X1I7_IMM7_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_X1I7_IMM7_SIZE)) |
| #define IW_X1I7_IMM7_SHIFTED_MASK (IW_X1I7_IMM7_UNSHIFTED_MASK << IW_X1I7_IMM7_LSB) |
| #define GET_IW_X1I7_IMM7(W) (((W) >> IW_X1I7_IMM7_LSB) & IW_X1I7_IMM7_UNSHIFTED_MASK) |
| #define SET_IW_X1I7_IMM7(V) (((V) & IW_X1I7_IMM7_UNSHIFTED_MASK) << IW_X1I7_IMM7_LSB) |
| #define IW_X1I7_RSV_LSB 13 |
| #define IW_X1I7_RSV_SIZE 2 |
| #define IW_X1I7_RSV_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_X1I7_RSV_SIZE)) |
| #define IW_X1I7_RSV_SHIFTED_MASK (IW_X1I7_RSV_UNSHIFTED_MASK << IW_X1I7_RSV_LSB) |
| #define GET_IW_X1I7_RSV(W) (((W) >> IW_X1I7_RSV_LSB) & IW_X1I7_RSV_UNSHIFTED_MASK) |
| #define SET_IW_X1I7_RSV(V) (((V) & IW_X1I7_RSV_UNSHIFTED_MASK) << IW_X1I7_RSV_LSB) |
| #define IW_X1I7_X_LSB 15 |
| #define IW_X1I7_X_SIZE 1 |
| #define IW_X1I7_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_X1I7_X_SIZE)) |
| #define IW_X1I7_X_SHIFTED_MASK (IW_X1I7_X_UNSHIFTED_MASK << IW_X1I7_X_LSB) |
| #define GET_IW_X1I7_X(W) (((W) >> IW_X1I7_X_LSB) & IW_X1I7_X_UNSHIFTED_MASK) |
| #define SET_IW_X1I7_X(V) (((V) & IW_X1I7_X_UNSHIFTED_MASK) << IW_X1I7_X_LSB) |
| #define IW_L5I4X1_IMM4_LSB 6 |
| #define IW_L5I4X1_IMM4_SIZE 4 |
| #define IW_L5I4X1_IMM4_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_L5I4X1_IMM4_SIZE)) |
| #define IW_L5I4X1_IMM4_SHIFTED_MASK (IW_L5I4X1_IMM4_UNSHIFTED_MASK << IW_L5I4X1_IMM4_LSB) |
| #define GET_IW_L5I4X1_IMM4(W) (((W) >> IW_L5I4X1_IMM4_LSB) & IW_L5I4X1_IMM4_UNSHIFTED_MASK) |
| #define SET_IW_L5I4X1_IMM4(V) (((V) & IW_L5I4X1_IMM4_UNSHIFTED_MASK) << IW_L5I4X1_IMM4_LSB) |
| #define IW_L5I4X1_REGRANGE_LSB 10 |
| #define IW_L5I4X1_REGRANGE_SIZE 3 |
| #define IW_L5I4X1_REGRANGE_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_L5I4X1_REGRANGE_SIZE)) |
| #define IW_L5I4X1_REGRANGE_SHIFTED_MASK (IW_L5I4X1_REGRANGE_UNSHIFTED_MASK << IW_L5I4X1_REGRANGE_LSB) |
| #define GET_IW_L5I4X1_REGRANGE(W) (((W) >> IW_L5I4X1_REGRANGE_LSB) & IW_L5I4X1_REGRANGE_UNSHIFTED_MASK) |
| #define SET_IW_L5I4X1_REGRANGE(V) (((V) & IW_L5I4X1_REGRANGE_UNSHIFTED_MASK) << IW_L5I4X1_REGRANGE_LSB) |
| #define IW_L5I4X1_FP_LSB 13 |
| #define IW_L5I4X1_FP_SIZE 1 |
| #define IW_L5I4X1_FP_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_L5I4X1_FP_SIZE)) |
| #define IW_L5I4X1_FP_SHIFTED_MASK (IW_L5I4X1_FP_UNSHIFTED_MASK << IW_L5I4X1_FP_LSB) |
| #define GET_IW_L5I4X1_FP(W) (((W) >> IW_L5I4X1_FP_LSB) & IW_L5I4X1_FP_UNSHIFTED_MASK) |
| #define SET_IW_L5I4X1_FP(V) (((V) & IW_L5I4X1_FP_UNSHIFTED_MASK) << IW_L5I4X1_FP_LSB) |
| #define IW_L5I4X1_CS_LSB 14 |
| #define IW_L5I4X1_CS_SIZE 1 |
| #define IW_L5I4X1_CS_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_L5I4X1_CS_SIZE)) |
| #define IW_L5I4X1_CS_SHIFTED_MASK (IW_L5I4X1_CS_UNSHIFTED_MASK << IW_L5I4X1_CS_LSB) |
| #define GET_IW_L5I4X1_CS(W) (((W) >> IW_L5I4X1_CS_LSB) & IW_L5I4X1_CS_UNSHIFTED_MASK) |
| #define SET_IW_L5I4X1_CS(V) (((V) & IW_L5I4X1_CS_UNSHIFTED_MASK) << IW_L5I4X1_CS_LSB) |
| #define IW_L5I4X1_X_LSB 15 |
| #define IW_L5I4X1_X_SIZE 1 |
| #define IW_L5I4X1_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_L5I4X1_X_SIZE)) |
| #define IW_L5I4X1_X_SHIFTED_MASK (IW_L5I4X1_X_UNSHIFTED_MASK << IW_L5I4X1_X_LSB) |
| #define GET_IW_L5I4X1_X(W) (((W) >> IW_L5I4X1_X_LSB) & IW_L5I4X1_X_UNSHIFTED_MASK) |
| #define SET_IW_L5I4X1_X(V) (((V) & IW_L5I4X1_X_UNSHIFTED_MASK) << IW_L5I4X1_X_LSB) |
| #define IW_T2X1L3_A3_LSB 6 |
| #define IW_T2X1L3_A3_SIZE 3 |
| #define IW_T2X1L3_A3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1L3_A3_SIZE)) |
| #define IW_T2X1L3_A3_SHIFTED_MASK (IW_T2X1L3_A3_UNSHIFTED_MASK << IW_T2X1L3_A3_LSB) |
| #define GET_IW_T2X1L3_A3(W) (((W) >> IW_T2X1L3_A3_LSB) & IW_T2X1L3_A3_UNSHIFTED_MASK) |
| #define SET_IW_T2X1L3_A3(V) (((V) & IW_T2X1L3_A3_UNSHIFTED_MASK) << IW_T2X1L3_A3_LSB) |
| #define IW_T2X1L3_B3_LSB 9 |
| #define IW_T2X1L3_B3_SIZE 3 |
| #define IW_T2X1L3_B3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1L3_B3_SIZE)) |
| #define IW_T2X1L3_B3_SHIFTED_MASK (IW_T2X1L3_B3_UNSHIFTED_MASK << IW_T2X1L3_B3_LSB) |
| #define GET_IW_T2X1L3_B3(W) (((W) >> IW_T2X1L3_B3_LSB) & IW_T2X1L3_B3_UNSHIFTED_MASK) |
| #define SET_IW_T2X1L3_B3(V) (((V) & IW_T2X1L3_B3_UNSHIFTED_MASK) << IW_T2X1L3_B3_LSB) |
| #define IW_T2X1L3_SHAMT_LSB 12 |
| #define IW_T2X1L3_SHAMT_SIZE 3 |
| #define IW_T2X1L3_SHAMT_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1L3_SHAMT_SIZE)) |
| #define IW_T2X1L3_SHAMT_SHIFTED_MASK (IW_T2X1L3_SHAMT_UNSHIFTED_MASK << IW_T2X1L3_SHAMT_LSB) |
| #define GET_IW_T2X1L3_SHAMT(W) (((W) >> IW_T2X1L3_SHAMT_LSB) & IW_T2X1L3_SHAMT_UNSHIFTED_MASK) |
| #define SET_IW_T2X1L3_SHAMT(V) (((V) & IW_T2X1L3_SHAMT_UNSHIFTED_MASK) << IW_T2X1L3_SHAMT_LSB) |
| #define IW_T2X1L3_X_LSB 15 |
| #define IW_T2X1L3_X_SIZE 1 |
| #define IW_T2X1L3_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1L3_X_SIZE)) |
| #define IW_T2X1L3_X_SHIFTED_MASK (IW_T2X1L3_X_UNSHIFTED_MASK << IW_T2X1L3_X_LSB) |
| #define GET_IW_T2X1L3_X(W) (((W) >> IW_T2X1L3_X_LSB) & IW_T2X1L3_X_UNSHIFTED_MASK) |
| #define SET_IW_T2X1L3_X(V) (((V) & IW_T2X1L3_X_UNSHIFTED_MASK) << IW_T2X1L3_X_LSB) |
| #define IW_T2X1I3_A3_LSB 6 |
| #define IW_T2X1I3_A3_SIZE 3 |
| #define IW_T2X1I3_A3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1I3_A3_SIZE)) |
| #define IW_T2X1I3_A3_SHIFTED_MASK (IW_T2X1I3_A3_UNSHIFTED_MASK << IW_T2X1I3_A3_LSB) |
| #define GET_IW_T2X1I3_A3(W) (((W) >> IW_T2X1I3_A3_LSB) & IW_T2X1I3_A3_UNSHIFTED_MASK) |
| #define SET_IW_T2X1I3_A3(V) (((V) & IW_T2X1I3_A3_UNSHIFTED_MASK) << IW_T2X1I3_A3_LSB) |
| #define IW_T2X1I3_B3_LSB 9 |
| #define IW_T2X1I3_B3_SIZE 3 |
| #define IW_T2X1I3_B3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1I3_B3_SIZE)) |
| #define IW_T2X1I3_B3_SHIFTED_MASK (IW_T2X1I3_B3_UNSHIFTED_MASK << IW_T2X1I3_B3_LSB) |
| #define GET_IW_T2X1I3_B3(W) (((W) >> IW_T2X1I3_B3_LSB) & IW_T2X1I3_B3_UNSHIFTED_MASK) |
| #define SET_IW_T2X1I3_B3(V) (((V) & IW_T2X1I3_B3_UNSHIFTED_MASK) << IW_T2X1I3_B3_LSB) |
| #define IW_T2X1I3_IMM3_LSB 12 |
| #define IW_T2X1I3_IMM3_SIZE 3 |
| #define IW_T2X1I3_IMM3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1I3_IMM3_SIZE)) |
| #define IW_T2X1I3_IMM3_SHIFTED_MASK (IW_T2X1I3_IMM3_UNSHIFTED_MASK << IW_T2X1I3_IMM3_LSB) |
| #define GET_IW_T2X1I3_IMM3(W) (((W) >> IW_T2X1I3_IMM3_LSB) & IW_T2X1I3_IMM3_UNSHIFTED_MASK) |
| #define SET_IW_T2X1I3_IMM3(V) (((V) & IW_T2X1I3_IMM3_UNSHIFTED_MASK) << IW_T2X1I3_IMM3_LSB) |
| #define IW_T2X1I3_X_LSB 15 |
| #define IW_T2X1I3_X_SIZE 1 |
| #define IW_T2X1I3_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1I3_X_SIZE)) |
| #define IW_T2X1I3_X_SHIFTED_MASK (IW_T2X1I3_X_UNSHIFTED_MASK << IW_T2X1I3_X_LSB) |
| #define GET_IW_T2X1I3_X(W) (((W) >> IW_T2X1I3_X_LSB) & IW_T2X1I3_X_UNSHIFTED_MASK) |
| #define SET_IW_T2X1I3_X(V) (((V) & IW_T2X1I3_X_UNSHIFTED_MASK) << IW_T2X1I3_X_LSB) |
| #define IW_T3X1_A3_LSB 6 |
| #define IW_T3X1_A3_SIZE 3 |
| #define IW_T3X1_A3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T3X1_A3_SIZE)) |
| #define IW_T3X1_A3_SHIFTED_MASK (IW_T3X1_A3_UNSHIFTED_MASK << IW_T3X1_A3_LSB) |
| #define GET_IW_T3X1_A3(W) (((W) >> IW_T3X1_A3_LSB) & IW_T3X1_A3_UNSHIFTED_MASK) |
| #define SET_IW_T3X1_A3(V) (((V) & IW_T3X1_A3_UNSHIFTED_MASK) << IW_T3X1_A3_LSB) |
| #define IW_T3X1_B3_LSB 9 |
| #define IW_T3X1_B3_SIZE 3 |
| #define IW_T3X1_B3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T3X1_B3_SIZE)) |
| #define IW_T3X1_B3_SHIFTED_MASK (IW_T3X1_B3_UNSHIFTED_MASK << IW_T3X1_B3_LSB) |
| #define GET_IW_T3X1_B3(W) (((W) >> IW_T3X1_B3_LSB) & IW_T3X1_B3_UNSHIFTED_MASK) |
| #define SET_IW_T3X1_B3(V) (((V) & IW_T3X1_B3_UNSHIFTED_MASK) << IW_T3X1_B3_LSB) |
| #define IW_T3X1_C3_LSB 12 |
| #define IW_T3X1_C3_SIZE 3 |
| #define IW_T3X1_C3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T3X1_C3_SIZE)) |
| #define IW_T3X1_C3_SHIFTED_MASK (IW_T3X1_C3_UNSHIFTED_MASK << IW_T3X1_C3_LSB) |
| #define GET_IW_T3X1_C3(W) (((W) >> IW_T3X1_C3_LSB) & IW_T3X1_C3_UNSHIFTED_MASK) |
| #define SET_IW_T3X1_C3(V) (((V) & IW_T3X1_C3_UNSHIFTED_MASK) << IW_T3X1_C3_LSB) |
| #define IW_T3X1_X_LSB 15 |
| #define IW_T3X1_X_SIZE 1 |
| #define IW_T3X1_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T3X1_X_SIZE)) |
| #define IW_T3X1_X_SHIFTED_MASK (IW_T3X1_X_UNSHIFTED_MASK << IW_T3X1_X_LSB) |
| #define GET_IW_T3X1_X(W) (((W) >> IW_T3X1_X_LSB) & IW_T3X1_X_UNSHIFTED_MASK) |
| #define SET_IW_T3X1_X(V) (((V) & IW_T3X1_X_UNSHIFTED_MASK) << IW_T3X1_X_LSB) |
| /* The X field for all three R.N-class instruction formats is represented |
| here as 4 bits, including the bits defined as constant 0 or 1 that |
| determine which of the formats T2X3, F1X1, or X2L5 it is. */ |
| #define IW_R_N_X_LSB 12 |
| #define IW_R_N_X_SIZE 4 |
| #define IW_R_N_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R_N_X_SIZE)) |
| #define IW_R_N_X_SHIFTED_MASK (IW_R_N_X_UNSHIFTED_MASK << IW_R_N_X_LSB) |
| #define GET_IW_R_N_X(W) (((W) >> IW_R_N_X_LSB) & IW_R_N_X_UNSHIFTED_MASK) |
| #define SET_IW_R_N_X(V) (((V) & IW_R_N_X_UNSHIFTED_MASK) << IW_R_N_X_LSB) |
| #define IW_T2X3_A3_LSB 6 |
| #define IW_T2X3_A3_SIZE 3 |
| #define IW_T2X3_A3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X3_A3_SIZE)) |
| #define IW_T2X3_A3_SHIFTED_MASK (IW_T2X3_A3_UNSHIFTED_MASK << IW_T2X3_A3_LSB) |
| #define GET_IW_T2X3_A3(W) (((W) >> IW_T2X3_A3_LSB) & IW_T2X3_A3_UNSHIFTED_MASK) |
| #define SET_IW_T2X3_A3(V) (((V) & IW_T2X3_A3_UNSHIFTED_MASK) << IW_T2X3_A3_LSB) |
| #define IW_T2X3_B3_LSB 9 |
| #define IW_T2X3_B3_SIZE 3 |
| #define IW_T2X3_B3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X3_B3_SIZE)) |
| #define IW_T2X3_B3_SHIFTED_MASK (IW_T2X3_B3_UNSHIFTED_MASK << IW_T2X3_B3_LSB) |
| #define GET_IW_T2X3_B3(W) (((W) >> IW_T2X3_B3_LSB) & IW_T2X3_B3_UNSHIFTED_MASK) |
| #define SET_IW_T2X3_B3(V) (((V) & IW_T2X3_B3_UNSHIFTED_MASK) << IW_T2X3_B3_LSB) |
| #define IW_F1X1_A_LSB 6 |
| #define IW_F1X1_A_SIZE 5 |
| #define IW_F1X1_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X1_A_SIZE)) |
| #define IW_F1X1_A_SHIFTED_MASK (IW_F1X1_A_UNSHIFTED_MASK << IW_F1X1_A_LSB) |
| #define GET_IW_F1X1_A(W) (((W) >> IW_F1X1_A_LSB) & IW_F1X1_A_UNSHIFTED_MASK) |
| #define SET_IW_F1X1_A(V) (((V) & IW_F1X1_A_UNSHIFTED_MASK) << IW_F1X1_A_LSB) |
| #define IW_F1X1_RSV_LSB 11 |
| #define IW_F1X1_RSV_SIZE 1 |
| #define IW_F1X1_RSV_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X1_RSV_SIZE)) |
| #define IW_F1X1_RSV_SHIFTED_MASK (IW_F1X1_RSV_UNSHIFTED_MASK << IW_F1X1_RSV_LSB) |
| #define GET_IW_F1X1_RSV(W) (((W) >> IW_F1X1_RSV_LSB) & IW_F1X1_RSV_UNSHIFTED_MASK) |
| #define SET_IW_F1X1_RSV(V) (((V) & IW_F1X1_RSV_UNSHIFTED_MASK) << IW_F1X1_RSV_LSB) |
| #define IW_X2L5_IMM5_LSB 6 |
| #define IW_X2L5_IMM5_SIZE 5 |
| #define IW_X2L5_IMM5_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_X2L5_IMM5_SIZE)) |
| #define IW_X2L5_IMM5_SHIFTED_MASK (IW_X2L5_IMM5_UNSHIFTED_MASK << IW_X2L5_IMM5_LSB) |
| #define GET_IW_X2L5_IMM5(W) (((W) >> IW_X2L5_IMM5_LSB) & IW_X2L5_IMM5_UNSHIFTED_MASK) |
| #define SET_IW_X2L5_IMM5(V) (((V) & IW_X2L5_IMM5_UNSHIFTED_MASK) << IW_X2L5_IMM5_LSB) |
| #define IW_X2L5_RSV_LSB 11 |
| #define IW_X2L5_RSV_SIZE 1 |
| #define IW_X2L5_RSV_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_X2L5_RSV_SIZE)) |
| #define IW_X2L5_RSV_SHIFTED_MASK (IW_X2L5_RSV_UNSHIFTED_MASK << IW_X2L5_RSV_LSB) |
| #define GET_IW_X2L5_RSV(W) (((W) >> IW_X2L5_RSV_LSB) & IW_X2L5_RSV_UNSHIFTED_MASK) |
| #define SET_IW_X2L5_RSV(V) (((V) & IW_X2L5_RSV_UNSHIFTED_MASK) << IW_X2L5_RSV_LSB) |
| #define IW_F1I5_IMM5_LSB 6 |
| #define IW_F1I5_IMM5_SIZE 5 |
| #define IW_F1I5_IMM5_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1I5_IMM5_SIZE)) |
| #define IW_F1I5_IMM5_SHIFTED_MASK (IW_F1I5_IMM5_UNSHIFTED_MASK << IW_F1I5_IMM5_LSB) |
| #define GET_IW_F1I5_IMM5(W) (((W) >> IW_F1I5_IMM5_LSB) & IW_F1I5_IMM5_UNSHIFTED_MASK) |
| #define SET_IW_F1I5_IMM5(V) (((V) & IW_F1I5_IMM5_UNSHIFTED_MASK) << IW_F1I5_IMM5_LSB) |
| #define IW_F1I5_B_LSB 11 |
| #define IW_F1I5_B_SIZE 5 |
| #define IW_F1I5_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1I5_B_SIZE)) |
| #define IW_F1I5_B_SHIFTED_MASK (IW_F1I5_B_UNSHIFTED_MASK << IW_F1I5_B_LSB) |
| #define GET_IW_F1I5_B(W) (((W) >> IW_F1I5_B_LSB) & IW_F1I5_B_UNSHIFTED_MASK) |
| #define SET_IW_F1I5_B(V) (((V) & IW_F1I5_B_UNSHIFTED_MASK) << IW_F1I5_B_LSB) |
| #define IW_F2_A_LSB 6 |
| #define IW_F2_A_SIZE 5 |
| #define IW_F2_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2_A_SIZE)) |
| #define IW_F2_A_SHIFTED_MASK (IW_F2_A_UNSHIFTED_MASK << IW_F2_A_LSB) |
| #define GET_IW_F2_A(W) (((W) >> IW_F2_A_LSB) & IW_F2_A_UNSHIFTED_MASK) |
| #define SET_IW_F2_A(V) (((V) & IW_F2_A_UNSHIFTED_MASK) << IW_F2_A_LSB) |
| #define IW_F2_B_LSB 11 |
| #define IW_F2_B_SIZE 5 |
| #define IW_F2_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2_B_SIZE)) |
| #define IW_F2_B_SHIFTED_MASK (IW_F2_B_UNSHIFTED_MASK << IW_F2_B_LSB) |
| #define GET_IW_F2_B(W) (((W) >> IW_F2_B_LSB) & IW_F2_B_UNSHIFTED_MASK) |
| #define SET_IW_F2_B(V) (((V) & IW_F2_B_UNSHIFTED_MASK) << IW_F2_B_LSB) |
| /* R2 opcodes. */ |
| #define R2_OP_CALL 0 |
| #define R2_OP_AS_N 1 |
| #define R2_OP_BR 2 |
| #define R2_OP_BR_N 3 |
| #define R2_OP_ADDI 4 |
| #define R2_OP_LDBU_N 5 |
| #define R2_OP_LDBU 6 |
| #define R2_OP_LDB 7 |
| #define R2_OP_JMPI 8 |
| #define R2_OP_R_N 9 |
| #define R2_OP_ANDI_N 11 |
| #define R2_OP_ANDI 12 |
| #define R2_OP_LDHU_N 13 |
| #define R2_OP_LDHU 14 |
| #define R2_OP_LDH 15 |
| #define R2_OP_ASI_N 17 |
| #define R2_OP_BGE 18 |
| #define R2_OP_LDWSP_N 19 |
| #define R2_OP_ORI 20 |
| #define R2_OP_LDW_N 21 |
| #define R2_OP_CMPGEI 22 |
| #define R2_OP_LDW 23 |
| #define R2_OP_SHI_N 25 |
| #define R2_OP_BLT 26 |
| #define R2_OP_MOVI_N 27 |
| #define R2_OP_XORI 28 |
| #define R2_OP_STZ_N 29 |
| #define R2_OP_CMPLTI 30 |
| #define R2_OP_ANDCI 31 |
| #define R2_OP_OPX 32 |
| #define R2_OP_PP_N 33 |
| #define R2_OP_BNE 34 |
| #define R2_OP_BNEZ_N 35 |
| #define R2_OP_MULI 36 |
| #define R2_OP_STB_N 37 |
| #define R2_OP_CMPNEI 38 |
| #define R2_OP_STB 39 |
| #define R2_OP_I12 40 |
| #define R2_OP_SPI_N 41 |
| #define R2_OP_BEQ 42 |
| #define R2_OP_BEQZ_N 43 |
| #define R2_OP_ANDHI 44 |
| #define R2_OP_STH_N 45 |
| #define R2_OP_CMPEQI 46 |
| #define R2_OP_STH 47 |
| #define R2_OP_CUSTOM 48 |
| #define R2_OP_BGEU 50 |
| #define R2_OP_STWSP_N 51 |
| #define R2_OP_ORHI 52 |
| #define R2_OP_STW_N 53 |
| #define R2_OP_CMPGEUI 54 |
| #define R2_OP_STW 55 |
| #define R2_OP_BLTU 58 |
| #define R2_OP_MOV_N 59 |
| #define R2_OP_XORHI 60 |
| #define R2_OP_SPADDI_N 61 |
| #define R2_OP_CMPLTUI 62 |
| #define R2_OP_ANDCHI 63 |
| #define R2_OPX_WRPIE 0 |
| #define R2_OPX_ERET 1 |
| #define R2_OPX_ROLI 2 |
| #define R2_OPX_ROL 3 |
| #define R2_OPX_FLUSHP 4 |
| #define R2_OPX_RET 5 |
| #define R2_OPX_NOR 6 |
| #define R2_OPX_MULXUU 7 |
| #define R2_OPX_ENI 8 |
| #define R2_OPX_BRET 9 |
| #define R2_OPX_ROR 11 |
| #define R2_OPX_FLUSHI 12 |
| #define R2_OPX_JMP 13 |
| #define R2_OPX_AND 14 |
| #define R2_OPX_CMPGE 16 |
| #define R2_OPX_SLLI 18 |
| #define R2_OPX_SLL 19 |
| #define R2_OPX_WRPRS 20 |
| #define R2_OPX_OR 22 |
| #define R2_OPX_MULXSU 23 |
| #define R2_OPX_CMPLT 24 |
| #define R2_OPX_SRLI 26 |
| #define R2_OPX_SRL 27 |
| #define R2_OPX_NEXTPC 28 |
| #define R2_OPX_CALLR 29 |
| #define R2_OPX_XOR 30 |
| #define R2_OPX_MULXSS 31 |
| #define R2_OPX_CMPNE 32 |
| #define R2_OPX_INSERT 35 |
| #define R2_OPX_DIVU 36 |
| #define R2_OPX_DIV 37 |
| #define R2_OPX_RDCTL 38 |
| #define R2_OPX_MUL 39 |
| #define R2_OPX_CMPEQ 40 |
| #define R2_OPX_INITI 41 |
| #define R2_OPX_MERGE 43 |
| #define R2_OPX_HBREAK 44 |
| #define R2_OPX_TRAP 45 |
| #define R2_OPX_WRCTL 46 |
| #define R2_OPX_CMPGEU 48 |
| #define R2_OPX_ADD 49 |
| #define R2_OPX_EXTRACT 51 |
| #define R2_OPX_BREAK 52 |
| #define R2_OPX_LDEX 53 |
| #define R2_OPX_SYNC 54 |
| #define R2_OPX_LDSEX 55 |
| #define R2_OPX_CMPLTU 56 |
| #define R2_OPX_SUB 57 |
| #define R2_OPX_SRAI 58 |
| #define R2_OPX_SRA 59 |
| #define R2_OPX_STEX 61 |
| #define R2_OPX_STSEX 63 |
| #define R2_I12_LDBIO 0 |
| #define R2_I12_STBIO 1 |
| #define R2_I12_LDBUIO 2 |
| #define R2_I12_DCACHE 3 |
| #define R2_I12_LDHIO 4 |
| #define R2_I12_STHIO 5 |
| #define R2_I12_LDHUIO 6 |
| #define R2_I12_RDPRS 7 |
| #define R2_I12_LDWIO 8 |
| #define R2_I12_STWIO 9 |
| #define R2_I12_LDWM 12 |
| #define R2_I12_STWM 13 |
| #define R2_DCACHE_INITD 0 |
| #define R2_DCACHE_INITDA 1 |
| #define R2_DCACHE_FLUSHD 2 |
| #define R2_DCACHE_FLUSHDA 3 |
| #define R2_AS_N_ADD_N 0 |
| #define R2_AS_N_SUB_N 1 |
| #define R2_R_N_AND_N 0 |
| #define R2_R_N_OR_N 2 |
| #define R2_R_N_XOR_N 3 |
| #define R2_R_N_SLL_N 4 |
| #define R2_R_N_SRL_N 5 |
| #define R2_R_N_NOT_N 6 |
| #define R2_R_N_NEG_N 7 |
| #define R2_R_N_CALLR_N 8 |
| #define R2_R_N_JMPR_N 10 |
| #define R2_R_N_BREAK_N 12 |
| #define R2_R_N_TRAP_N 13 |
| #define R2_R_N_RET_N 14 |
| #define R2_SPI_N_SPINCI_N 0 |
| #define R2_SPI_N_SPDECI_N 1 |
| #define R2_ASI_N_ADDI_N 0 |
| #define R2_ASI_N_SUBI_N 1 |
| #define R2_SHI_N_SLLI_N 0 |
| #define R2_SHI_N_SRLI_N 1 |
| #define R2_PP_N_POP_N 0 |
| #define R2_PP_N_PUSH_N 1 |
| #define R2_STZ_N_STWZ_N 0 |
| #define R2_STZ_N_STBZ_N 1 |
| /* Convenience macros for R2 encodings. */ |
| #define MATCH_R2_OP(NAME) \ |
| (SET_IW_R2_OP (R2_OP_##NAME)) |
| #define MASK_R2_OP \ |
| IW_R2_OP_SHIFTED_MASK |
| #define MATCH_R2_OPX0(NAME) \ |
| (SET_IW_R2_OP (R2_OP_OPX) | SET_IW_OPX_X (R2_OPX_##NAME)) |
| #define MASK_R2_OPX0 \ |
| (IW_R2_OP_SHIFTED_MASK | IW_OPX_X_SHIFTED_MASK \ |
| | IW_F3X6L5_IMM5_SHIFTED_MASK) |
| #define MATCH_R2_OPX(NAME, A, B, C) \ |
| (MATCH_R2_OPX0 (NAME) | SET_IW_F3X6L5_A (A) | SET_IW_F3X6L5_B (B) \ |
| | SET_IW_F3X6L5_C (C)) |
| #define MASK_R2_OPX(A, B, C, N) \ |
| (IW_R2_OP_SHIFTED_MASK | IW_OPX_X_SHIFTED_MASK \ |
| | (A ? IW_F3X6L5_A_SHIFTED_MASK : 0) \ |
| | (B ? IW_F3X6L5_B_SHIFTED_MASK : 0) \ |
| | (C ? IW_F3X6L5_C_SHIFTED_MASK : 0) \ |
| | (N ? IW_F3X6L5_IMM5_SHIFTED_MASK : 0)) |
| #define MATCH_R2_I12(NAME) \ |
| (SET_IW_R2_OP (R2_OP_I12) | SET_IW_I12_X (R2_I12_##NAME)) |
| #define MASK_R2_I12 \ |
| (IW_R2_OP_SHIFTED_MASK | IW_I12_X_SHIFTED_MASK ) |
| #define MATCH_R2_DCACHE(NAME) \ |
| (MATCH_R2_I12(DCACHE) | SET_IW_F1X4I12_X (R2_DCACHE_##NAME)) |
| #define MASK_R2_DCACHE \ |
| (MASK_R2_I12 | IW_F1X4I12_X_SHIFTED_MASK) |
| #define MATCH_R2_R_N(NAME) \ |
| (SET_IW_R2_OP (R2_OP_R_N) | SET_IW_R_N_X (R2_R_N_##NAME)) |
| #define MASK_R2_R_N \ |
| (IW_R2_OP_SHIFTED_MASK | IW_R_N_X_SHIFTED_MASK ) |
| /* Match/mask macros for R2 instructions. */ |
| #define MATCH_R2_ADD MATCH_R2_OPX0 (ADD) |
| #define MASK_R2_ADD MASK_R2_OPX0 |
| #define MATCH_R2_ADDI MATCH_R2_OP (ADDI) |
| #define MASK_R2_ADDI MASK_R2_OP |
| #define MATCH_R2_ADD_N (MATCH_R2_OP (AS_N) | SET_IW_T3X1_X (R2_AS_N_ADD_N)) |
| #define MASK_R2_ADD_N (MASK_R2_OP | IW_T3X1_X_SHIFTED_MASK) |
| #define MATCH_R2_ADDI_N (MATCH_R2_OP (ASI_N) | SET_IW_T2X1I3_X (R2_ASI_N_ADDI_N)) |
| #define MASK_R2_ADDI_N (MASK_R2_OP | IW_T2X1I3_X_SHIFTED_MASK) |
| #define MATCH_R2_AND MATCH_R2_OPX0 (AND) |
| #define MASK_R2_AND MASK_R2_OPX0 |
| #define MATCH_R2_ANDCHI MATCH_R2_OP (ANDCHI) |
| #define MASK_R2_ANDCHI MASK_R2_OP |
| #define MATCH_R2_ANDCI MATCH_R2_OP (ANDCI) |
| #define MASK_R2_ANDCI MASK_R2_OP |
| #define MATCH_R2_ANDHI MATCH_R2_OP (ANDHI) |
| #define MASK_R2_ANDHI MASK_R2_OP |
| #define MATCH_R2_ANDI MATCH_R2_OP (ANDI) |
| #define MASK_R2_ANDI MASK_R2_OP |
| #define MATCH_R2_ANDI_N MATCH_R2_OP (ANDI_N) |
| #define MASK_R2_ANDI_N MASK_R2_OP |
| #define MATCH_R2_AND_N MATCH_R2_R_N (AND_N) |
| #define MASK_R2_AND_N MASK_R2_R_N |
| #define MATCH_R2_BEQ MATCH_R2_OP (BEQ) |
| #define MASK_R2_BEQ MASK_R2_OP |
| #define MATCH_R2_BEQZ_N MATCH_R2_OP (BEQZ_N) |
| #define MASK_R2_BEQZ_N MASK_R2_OP |
| #define MATCH_R2_BGE MATCH_R2_OP (BGE) |
| #define MASK_R2_BGE MASK_R2_OP |
| #define MATCH_R2_BGEU MATCH_R2_OP (BGEU) |
| #define MASK_R2_BGEU MASK_R2_OP |
| #define MATCH_R2_BGT MATCH_R2_OP (BLT) |
| #define MASK_R2_BGT MASK_R2_OP |
| #define MATCH_R2_BGTU MATCH_R2_OP (BLTU) |
| #define MASK_R2_BGTU MASK_R2_OP |
| #define MATCH_R2_BLE MATCH_R2_OP (BGE) |
| #define MASK_R2_BLE MASK_R2_OP |
| #define MATCH_R2_BLEU MATCH_R2_OP (BGEU) |
| #define MASK_R2_BLEU MASK_R2_OP |
| #define MATCH_R2_BLT MATCH_R2_OP (BLT) |
| #define MASK_R2_BLT MASK_R2_OP |
| #define MATCH_R2_BLTU MATCH_R2_OP (BLTU) |
| #define MASK_R2_BLTU MASK_R2_OP |
| #define MATCH_R2_BNE MATCH_R2_OP (BNE) |
| #define MASK_R2_BNE MASK_R2_OP |
| #define MATCH_R2_BNEZ_N MATCH_R2_OP (BNEZ_N) |
| #define MASK_R2_BNEZ_N MASK_R2_OP |
| #define MATCH_R2_BR MATCH_R2_OP (BR) |
| #define MASK_R2_BR MASK_R2_OP | IW_F2I16_A_SHIFTED_MASK | IW_F2I16_B_SHIFTED_MASK |
| #define MATCH_R2_BREAK MATCH_R2_OPX (BREAK, 0, 0, 0x1e) |
| #define MASK_R2_BREAK MASK_R2_OPX (1, 1, 1, 0) |
| #define MATCH_R2_BREAK_N MATCH_R2_R_N (BREAK_N) |
| #define MASK_R2_BREAK_N MASK_R2_R_N |
| #define MATCH_R2_BRET MATCH_R2_OPX (BRET, 0x1e, 0, 0) |
| #define MASK_R2_BRET MASK_R2_OPX (1, 1, 1, 1) |
| #define MATCH_R2_BR_N MATCH_R2_OP (BR_N) |
| #define MASK_R2_BR_N MASK_R2_OP |
| #define MATCH_R2_CALL MATCH_R2_OP (CALL) |
| #define MASK_R2_CALL MASK_R2_OP |
| #define MATCH_R2_CALLR MATCH_R2_OPX (CALLR, 0, 0, 0x1f) |
| #define MASK_R2_CALLR MASK_R2_OPX (0, 1, 1, 1) |
| #define MATCH_R2_CALLR_N MATCH_R2_R_N (CALLR_N) |
| #define MASK_R2_CALLR_N MASK_R2_R_N |
| #define MATCH_R2_CMPEQ MATCH_R2_OPX0 (CMPEQ) |
| #define MASK_R2_CMPEQ MASK_R2_OPX0 |
| #define MATCH_R2_CMPEQI MATCH_R2_OP (CMPEQI) |
| #define MASK_R2_CMPEQI MASK_R2_OP |
| #define MATCH_R2_CMPGE MATCH_R2_OPX0 (CMPGE) |
| #define MASK_R2_CMPGE MASK_R2_OPX0 |
| #define MATCH_R2_CMPGEI MATCH_R2_OP (CMPGEI) |
| #define MASK_R2_CMPGEI MASK_R2_OP |
| #define MATCH_R2_CMPGEU MATCH_R2_OPX0 (CMPGEU) |
| #define MASK_R2_CMPGEU MASK_R2_OPX0 |
| #define MATCH_R2_CMPGEUI MATCH_R2_OP (CMPGEUI) |
| #define MASK_R2_CMPGEUI MASK_R2_OP |
| #define MATCH_R2_CMPGT MATCH_R2_OPX0 (CMPLT) |
| #define MASK_R2_CMPGT MASK_R2_OPX0 |
| #define MATCH_R2_CMPGTI MATCH_R2_OP (CMPGEI) |
| #define MASK_R2_CMPGTI MASK_R2_OP |
| #define MATCH_R2_CMPGTU MATCH_R2_OPX0 (CMPLTU) |
| #define MASK_R2_CMPGTU MASK_R2_OPX0 |
| #define MATCH_R2_CMPGTUI MATCH_R2_OP (CMPGEUI) |
| #define MASK_R2_CMPGTUI MASK_R2_OP |
| #define MATCH_R2_CMPLE MATCH_R2_OPX0 (CMPGE) |
| #define MASK_R2_CMPLE MASK_R2_OPX0 |
| #define MATCH_R2_CMPLEI MATCH_R2_OP (CMPLTI) |
| #define MASK_R2_CMPLEI MASK_R2_OP |
| #define MATCH_R2_CMPLEU MATCH_R2_OPX0 (CMPGEU) |
| #define MASK_R2_CMPLEU MASK_R2_OPX0 |
| #define MATCH_R2_CMPLEUI MATCH_R2_OP (CMPLTUI) |
| #define MASK_R2_CMPLEUI MASK_R2_OP |
| #define MATCH_R2_CMPLT MATCH_R2_OPX0 (CMPLT) |
| #define MASK_R2_CMPLT MASK_R2_OPX0 |
| #define MATCH_R2_CMPLTI MATCH_R2_OP (CMPLTI) |
| #define MASK_R2_CMPLTI MASK_R2_OP |
| #define MATCH_R2_CMPLTU MATCH_R2_OPX0 (CMPLTU) |
| #define MASK_R2_CMPLTU MASK_R2_OPX0 |
| #define MATCH_R2_CMPLTUI MATCH_R2_OP (CMPLTUI) |
| #define MASK_R2_CMPLTUI MASK_R2_OP |
| #define MATCH_R2_CMPNE MATCH_R2_OPX0 (CMPNE) |
| #define MASK_R2_CMPNE MASK_R2_OPX0 |
| #define MATCH_R2_CMPNEI MATCH_R2_OP (CMPNEI) |
| #define MASK_R2_CMPNEI MASK_R2_OP |
| #define MATCH_R2_CUSTOM MATCH_R2_OP (CUSTOM) |
| #define MASK_R2_CUSTOM MASK_R2_OP |
| #define MATCH_R2_DIV MATCH_R2_OPX0 (DIV) |
| #define MASK_R2_DIV MASK_R2_OPX0 |
| #define MATCH_R2_DIVU MATCH_R2_OPX0 (DIVU) |
| #define MASK_R2_DIVU MASK_R2_OPX0 |
| #define MATCH_R2_ENI MATCH_R2_OPX (ENI, 0, 0, 0) |
| #define MASK_R2_ENI MASK_R2_OPX (1, 1, 1, 0) |
| #define MATCH_R2_ERET MATCH_R2_OPX (ERET, 0x1d, 0x1e, 0) |
| #define MASK_R2_ERET MASK_R2_OPX (1, 1, 1, 1) |
| #define MATCH_R2_EXTRACT MATCH_R2_OPX (EXTRACT, 0, 0, 0) |
| #define MASK_R2_EXTRACT MASK_R2_OPX (0, 0, 0, 0) |
| #define MATCH_R2_FLUSHD MATCH_R2_DCACHE (FLUSHD) |
| #define MASK_R2_FLUSHD MASK_R2_DCACHE |
| #define MATCH_R2_FLUSHDA MATCH_R2_DCACHE (FLUSHDA) |
| #define MASK_R2_FLUSHDA MASK_R2_DCACHE |
| #define MATCH_R2_FLUSHI MATCH_R2_OPX (FLUSHI, 0, 0, 0) |
| #define MASK_R2_FLUSHI MASK_R2_OPX (0, 1, 1, 1) |
| #define MATCH_R2_FLUSHP MATCH_R2_OPX (FLUSHP, 0, 0, 0) |
| #define MASK_R2_FLUSHP MASK_R2_OPX (1, 1, 1, 1) |
| #define MATCH_R2_INITD MATCH_R2_DCACHE (INITD) |
| #define MASK_R2_INITD MASK_R2_DCACHE |
| #define MATCH_R2_INITDA MATCH_R2_DCACHE (INITDA) |
| #define MASK_R2_INITDA MASK_R2_DCACHE |
| #define MATCH_R2_INITI MATCH_R2_OPX (INITI, 0, 0, 0) |
| #define MASK_R2_INITI MASK_R2_OPX (0, 1, 1, 1) |
| #define MATCH_R2_INSERT MATCH_R2_OPX (INSERT, 0, 0, 0) |
| #define MASK_R2_INSERT MASK_R2_OPX (0, 0, 0, 0) |
| #define MATCH_R2_JMP MATCH_R2_OPX (JMP, 0, 0, 0) |
| #define MASK_R2_JMP MASK_R2_OPX (0, 1, 1, 1) |
| #define MATCH_R2_JMPI MATCH_R2_OP (JMPI) |
| #define MASK_R2_JMPI MASK_R2_OP |
| #define MATCH_R2_JMPR_N MATCH_R2_R_N (JMPR_N) |
| #define MASK_R2_JMPR_N MASK_R2_R_N |
| #define MATCH_R2_LDB MATCH_R2_OP (LDB) |
| #define MASK_R2_LDB MASK_R2_OP |
| #define MATCH_R2_LDBIO MATCH_R2_I12 (LDBIO) |
| #define MASK_R2_LDBIO MASK_R2_I12 |
| #define MATCH_R2_LDBU MATCH_R2_OP (LDBU) |
| #define MASK_R2_LDBU MASK_R2_OP |
| #define MATCH_R2_LDBUIO MATCH_R2_I12 (LDBUIO) |
| #define MASK_R2_LDBUIO MASK_R2_I12 |
| #define MATCH_R2_LDBU_N MATCH_R2_OP (LDBU_N) |
| #define MASK_R2_LDBU_N MASK_R2_OP |
| #define MATCH_R2_LDEX MATCH_R2_OPX (LDEX, 0, 0, 0) |
| #define MASK_R2_LDEX MASK_R2_OPX (0, 1, 0, 1) |
| #define MATCH_R2_LDH MATCH_R2_OP (LDH) |
| #define MASK_R2_LDH MASK_R2_OP |
| #define MATCH_R2_LDHIO MATCH_R2_I12 (LDHIO) |
| #define MASK_R2_LDHIO MASK_R2_I12 |
| #define MATCH_R2_LDHU MATCH_R2_OP (LDHU) |
| #define MASK_R2_LDHU MASK_R2_OP |
| #define MATCH_R2_LDHUIO MATCH_R2_I12 (LDHUIO) |
| #define MASK_R2_LDHUIO MASK_R2_I12 |
| #define MATCH_R2_LDHU_N MATCH_R2_OP (LDHU_N) |
| #define MASK_R2_LDHU_N MASK_R2_OP |
| #define MATCH_R2_LDSEX MATCH_R2_OPX (LDSEX, 0, 0, 0) |
| #define MASK_R2_LDSEX MASK_R2_OPX (0, 1, 0, 1) |
| #define MATCH_R2_LDW MATCH_R2_OP (LDW) |
| #define MASK_R2_LDW MASK_R2_OP |
| #define MATCH_R2_LDWIO MATCH_R2_I12 (LDWIO) |
| #define MASK_R2_LDWIO MASK_R2_I12 |
| #define MATCH_R2_LDWM MATCH_R2_I12 (LDWM) |
| #define MASK_R2_LDWM MASK_R2_I12 |
| #define MATCH_R2_LDWSP_N MATCH_R2_OP (LDWSP_N) |
| #define MASK_R2_LDWSP_N MASK_R2_OP |
| #define MATCH_R2_LDW_N MATCH_R2_OP (LDW_N) |
| #define MASK_R2_LDW_N MASK_R2_OP |
| #define MATCH_R2_MERGE MATCH_R2_OPX (MERGE, 0, 0, 0) |
| #define MASK_R2_MERGE MASK_R2_OPX (0, 0, 0, 0) |
| #define MATCH_R2_MOV MATCH_R2_OPX (ADD, 0, 0, 0) |
| #define MASK_R2_MOV MASK_R2_OPX (0, 1, 0, 1) |
| #define MATCH_R2_MOVHI MATCH_R2_OP (ORHI) | SET_IW_F2I16_A (0) |
| #define MASK_R2_MOVHI MASK_R2_OP | IW_F2I16_A_SHIFTED_MASK |
| #define MATCH_R2_MOVI MATCH_R2_OP (ADDI) | SET_IW_F2I16_A (0) |
| #define MASK_R2_MOVI MASK_R2_OP | IW_F2I16_A_SHIFTED_MASK |
| #define MATCH_R2_MOVUI MATCH_R2_OP (ORI) | SET_IW_F2I16_A (0) |
| #define MASK_R2_MOVUI MASK_R2_OP | IW_F2I16_A_SHIFTED_MASK |
| #define MATCH_R2_MOV_N MATCH_R2_OP (MOV_N) |
| #define MASK_R2_MOV_N MASK_R2_OP |
| #define MATCH_R2_MOVI_N MATCH_R2_OP (MOVI_N) |
| #define MASK_R2_MOVI_N MASK_R2_OP |
| #define MATCH_R2_MUL MATCH_R2_OPX0 (MUL) |
| #define MASK_R2_MUL MASK_R2_OPX0 |
| #define MATCH_R2_MULI MATCH_R2_OP (MULI) |
| #define MASK_R2_MULI MASK_R2_OP |
| #define MATCH_R2_MULXSS MATCH_R2_OPX0 (MULXSS) |
| #define MASK_R2_MULXSS MASK_R2_OPX0 |
| #define MATCH_R2_MULXSU MATCH_R2_OPX0 (MULXSU) |
| #define MASK_R2_MULXSU MASK_R2_OPX0 |
| #define MATCH_R2_MULXUU MATCH_R2_OPX0 (MULXUU) |
| #define MASK_R2_MULXUU MASK_R2_OPX0 |
| #define MATCH_R2_NEG_N MATCH_R2_R_N (NEG_N) |
| #define MASK_R2_NEG_N MASK_R2_R_N |
| #define MATCH_R2_NEXTPC MATCH_R2_OPX (NEXTPC, 0, 0, 0) |
| #define MASK_R2_NEXTPC MASK_R2_OPX (1, 1, 0, 1) |
| #define MATCH_R2_NOP MATCH_R2_OPX (ADD, 0, 0, 0) |
| #define MASK_R2_NOP MASK_R2_OPX (1, 1, 1, 1) |
| #define MATCH_R2_NOP_N (MATCH_R2_OP (MOV_N) | SET_IW_F2_A (0) | SET_IW_F2_B (0)) |
| #define MASK_R2_NOP_N (MASK_R2_OP | IW_F2_A_SHIFTED_MASK | IW_F2_B_SHIFTED_MASK) |
| #define MATCH_R2_NOR MATCH_R2_OPX0 (NOR) |
| #define MASK_R2_NOR MASK_R2_OPX0 |
| #define MATCH_R2_NOT_N MATCH_R2_R_N (NOT_N) |
| #define MASK_R2_NOT_N MASK_R2_R_N |
| #define MATCH_R2_OR MATCH_R2_OPX0 (OR) |
| #define MASK_R2_OR MASK_R2_OPX0 |
| #define MATCH_R2_OR_N MATCH_R2_R_N (OR_N) |
| #define MASK_R2_OR_N MASK_R2_R_N |
| #define MATCH_R2_ORHI MATCH_R2_OP (ORHI) |
| #define MASK_R2_ORHI MASK_R2_OP |
| #define MATCH_R2_ORI MATCH_R2_OP (ORI) |
| #define MASK_R2_ORI MASK_R2_OP |
| #define MATCH_R2_POP_N (MATCH_R2_OP (PP_N) | SET_IW_L5I4X1_X (R2_PP_N_POP_N)) |
| #define MASK_R2_POP_N (MASK_R2_OP | IW_L5I4X1_X_SHIFTED_MASK) |
| #define MATCH_R2_PUSH_N (MATCH_R2_OP (PP_N) | SET_IW_L5I4X1_X (R2_PP_N_PUSH_N)) |
| #define MASK_R2_PUSH_N (MASK_R2_OP | IW_L5I4X1_X_SHIFTED_MASK) |
| #define MATCH_R2_RDCTL MATCH_R2_OPX (RDCTL, 0, 0, 0) |
| #define MASK_R2_RDCTL MASK_R2_OPX (1, 1, 0, 0) |
| #define MATCH_R2_RDPRS MATCH_R2_I12 (RDPRS) |
| #define MASK_R2_RDPRS MASK_R2_I12 |
| #define MATCH_R2_RET MATCH_R2_OPX (RET, 0x1f, 0, 0) |
| #define MASK_R2_RET MASK_R2_OPX (1, 1, 1, 1) |
| #define MATCH_R2_RET_N (MATCH_R2_R_N (RET_N) | SET_IW_X2L5_IMM5 (0)) |
| #define MASK_R2_RET_N (MASK_R2_R_N | IW_X2L5_IMM5_SHIFTED_MASK) |
| #define MATCH_R2_ROL MATCH_R2_OPX0 (ROL) |
| #define MASK_R2_ROL MASK_R2_OPX0 |
| #define MATCH_R2_ROLI MATCH_R2_OPX (ROLI, 0, 0, 0) |
| #define MASK_R2_ROLI MASK_R2_OPX (0, 1, 0, 0) |
| #define MATCH_R2_ROR MATCH_R2_OPX0 (ROR) |
| #define MASK_R2_ROR MASK_R2_OPX0 |
| #define MATCH_R2_SLL MATCH_R2_OPX0 (SLL) |
| #define MASK_R2_SLL MASK_R2_OPX0 |
| #define MATCH_R2_SLLI MATCH_R2_OPX (SLLI, 0, 0, 0) |
| #define MASK_R2_SLLI MASK_R2_OPX (0, 1, 0, 0) |
| #define MATCH_R2_SLL_N MATCH_R2_R_N (SLL_N) |
| #define MASK_R2_SLL_N MASK_R2_R_N |
| #define MATCH_R2_SLLI_N (MATCH_R2_OP (SHI_N) | SET_IW_T2X1L3_X (R2_SHI_N_SLLI_N)) |
| #define MASK_R2_SLLI_N (MASK_R2_OP | IW_T2X1L3_X_SHIFTED_MASK) |
| #define MATCH_R2_SPADDI_N MATCH_R2_OP (SPADDI_N) |
| #define MASK_R2_SPADDI_N MASK_R2_OP |
| #define MATCH_R2_SPDECI_N (MATCH_R2_OP (SPI_N) | SET_IW_X1I7_X (R2_SPI_N_SPDECI_N)) |
| #define MASK_R2_SPDECI_N (MASK_R2_OP | IW_X1I7_X_SHIFTED_MASK) |
| #define MATCH_R2_SPINCI_N (MATCH_R2_OP (SPI_N) | SET_IW_X1I7_X (R2_SPI_N_SPINCI_N)) |
| #define MASK_R2_SPINCI_N (MASK_R2_OP | IW_X1I7_X_SHIFTED_MASK) |
| #define MATCH_R2_SRA MATCH_R2_OPX0 (SRA) |
| #define MASK_R2_SRA MASK_R2_OPX0 |
| #define MATCH_R2_SRAI MATCH_R2_OPX (SRAI, 0, 0, 0) |
| #define MASK_R2_SRAI MASK_R2_OPX (0, 1, 0, 0) |
| #define MATCH_R2_SRL MATCH_R2_OPX0 (SRL) |
| #define MASK_R2_SRL MASK_R2_OPX0 |
| #define MATCH_R2_SRLI MATCH_R2_OPX (SRLI, 0, 0, 0) |
| #define MASK_R2_SRLI MASK_R2_OPX (0, 1, 0, 0) |
| #define MATCH_R2_SRL_N MATCH_R2_R_N (SRL_N) |
| #define MASK_R2_SRL_N MASK_R2_R_N |
| #define MATCH_R2_SRLI_N (MATCH_R2_OP (SHI_N) | SET_IW_T2X1L3_X (R2_SHI_N_SRLI_N)) |
| #define MASK_R2_SRLI_N (MASK_R2_OP | IW_T2X1L3_X_SHIFTED_MASK) |
| #define MATCH_R2_STB MATCH_R2_OP (STB) |
| #define MASK_R2_STB MASK_R2_OP |
| #define MATCH_R2_STBIO MATCH_R2_I12 (STBIO) |
| #define MASK_R2_STBIO MASK_R2_I12 |
| #define MATCH_R2_STB_N MATCH_R2_OP (STB_N) |
| #define MASK_R2_STB_N MASK_R2_OP |
| #define MATCH_R2_STBZ_N (MATCH_R2_OP (STZ_N) | SET_IW_T1X1I6_X (R2_STZ_N_STBZ_N)) |
| #define MASK_R2_STBZ_N (MASK_R2_OP | IW_T1X1I6_X_SHIFTED_MASK) |
| #define MATCH_R2_STEX MATCH_R2_OPX0 (STEX) |
| #define MASK_R2_STEX MASK_R2_OPX0 |
| #define MATCH_R2_STH MATCH_R2_OP (STH) |
| #define MASK_R2_STH MASK_R2_OP |
| #define MATCH_R2_STHIO MATCH_R2_I12 (STHIO) |
| #define MASK_R2_STHIO MASK_R2_I12 |
| #define MATCH_R2_STH_N MATCH_R2_OP (STH_N) |
| #define MASK_R2_STH_N MASK_R2_OP |
| #define MATCH_R2_STSEX MATCH_R2_OPX0 (STSEX) |
| #define MASK_R2_STSEX MASK_R2_OPX0 |
| #define MATCH_R2_STW MATCH_R2_OP (STW) |
| #define MASK_R2_STW MASK_R2_OP |
| #define MATCH_R2_STWIO MATCH_R2_I12 (STWIO) |
| #define MASK_R2_STWIO MASK_R2_I12 |
| #define MATCH_R2_STWM MATCH_R2_I12 (STWM) |
| #define MASK_R2_STWM MASK_R2_I12 |
| #define MATCH_R2_STWSP_N MATCH_R2_OP (STWSP_N) |
| #define MASK_R2_STWSP_N MASK_R2_OP |
| #define MATCH_R2_STW_N MATCH_R2_OP (STW_N) |
| #define MASK_R2_STW_N MASK_R2_OP |
| #define MATCH_R2_STWZ_N MATCH_R2_OP (STZ_N) |
| #define MASK_R2_STWZ_N MASK_R2_OP |
| #define MATCH_R2_SUB MATCH_R2_OPX0 (SUB) |
| #define MASK_R2_SUB MASK_R2_OPX0 |
| #define MATCH_R2_SUBI MATCH_R2_OP (ADDI) |
| #define MASK_R2_SUBI MASK_R2_OP |
| #define MATCH_R2_SUB_N (MATCH_R2_OP (AS_N) | SET_IW_T3X1_X (R2_AS_N_SUB_N)) |
| #define MASK_R2_SUB_N (MASK_R2_OP | IW_T3X1_X_SHIFTED_MASK) |
| #define MATCH_R2_SUBI_N (MATCH_R2_OP (ASI_N) | SET_IW_T2X1I3_X (R2_ASI_N_SUBI_N)) |
| #define MASK_R2_SUBI_N (MASK_R2_OP | IW_T2X1I3_X_SHIFTED_MASK) |
| #define MATCH_R2_SYNC MATCH_R2_OPX (SYNC, 0, 0, 0) |
| #define MASK_R2_SYNC MASK_R2_OPX (1, 1, 1, 1) |
| #define MATCH_R2_TRAP MATCH_R2_OPX (TRAP, 0, 0, 0x1d) |
| #define MASK_R2_TRAP MASK_R2_OPX (1, 1, 1, 0) |
| #define MATCH_R2_TRAP_N MATCH_R2_R_N (TRAP_N) |
| #define MASK_R2_TRAP_N MASK_R2_R_N |
| #define MATCH_R2_WRCTL MATCH_R2_OPX (WRCTL, 0, 0, 0) |
| #define MASK_R2_WRCTL MASK_R2_OPX (0, 1, 1, 0) |
| #define MATCH_R2_WRPIE MATCH_R2_OPX (WRPIE, 0, 0, 0) |
| #define MASK_R2_WRPIE MASK_R2_OPX (0, 1, 0, 1) |
| #define MATCH_R2_WRPRS MATCH_R2_OPX (WRPRS, 0, 0, 0) |
| #define MASK_R2_WRPRS MASK_R2_OPX (0, 1, 0, 1) |
| #define MATCH_R2_XOR MATCH_R2_OPX0 (XOR) |
| #define MASK_R2_XOR MASK_R2_OPX0 |
| #define MATCH_R2_XORHI MATCH_R2_OP (XORHI) |
| #define MASK_R2_XORHI MASK_R2_OP |
| #define MATCH_R2_XORI MATCH_R2_OP (XORI) |
| #define MASK_R2_XORI MASK_R2_OP |
| #define MATCH_R2_XOR_N MATCH_R2_R_N (XOR_N) |
| #define MASK_R2_XOR_N MASK_R2_R_N |
| #endif /* _NIOS2R2_H */ |
| /contrib/toolchain/binutils/include/opcode/np1.h |
|---|
| 1,5 → 1,5 |
| /* Print GOULD NPL instructions for GDB, the GNU debugger. |
| Copyright 1986, 1987, 1989, 1991, 2010 Free Software Foundation, Inc. |
| Copyright (C) 1986-2015 Free Software Foundation, Inc. |
| This file is part of GDB. |
| /contrib/toolchain/binutils/include/opcode/ns32k.h |
|---|
| 1,5 → 1,5 |
| /* ns32k-opcode.h -- Opcode table for National Semi 32k processor |
| Copyright 1987, 1991, 1994, 2002, 2010 Free Software Foundation, Inc. |
| Copyright (C) 1987-2015 Free Software Foundation, Inc. |
| This file is part of GAS, the GNU Assembler. |
| /contrib/toolchain/binutils/include/opcode/pdp11.h |
|---|
| 1,5 → 1,5 |
| /* PDP-11 opcde list. |
| Copyright 2001, 2002, 2010 Free Software Foundation, Inc. |
| Copyright (C) 2001-2015 Free Software Foundation, Inc. |
| This file is part of GDB and GAS. |
| /contrib/toolchain/binutils/include/opcode/pj.h |
|---|
| 1,5 → 1,5 |
| /* Definitions for decoding the picoJava opcode table. |
| Copyright 1999, 2002, 2003, 2010 Free Software Foundation, Inc. |
| Copyright (C) 1999-2015 Free Software Foundation, Inc. |
| Contributed by Steve Chamberlain of Transmeta (sac@pobox.com). |
| This program is free software; you can redistribute it and/or modify |
| /contrib/toolchain/binutils/include/opcode/pn.h |
|---|
| 1,5 → 1,5 |
| /* Print GOULD PN (PowerNode) instructions for GDB, the GNU debugger. |
| Copyright 1986, 1987, 1989, 1991, 2010 Free Software Foundation, Inc. |
| Copyright (C) 1986-2015 Free Software Foundation, Inc. |
| This file is part of GDB. |
| /contrib/toolchain/binutils/include/opcode/ppc.h |
|---|
| 1,6 → 1,5 |
| /* ppc.h -- Header file for PowerPC opcode table |
| Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, |
| 2007, 2008, 2009, 2010, 2012 Free Software Foundation, Inc. |
| Copyright (C) 1994-2015 Free Software Foundation, Inc. |
| Written by Ian Lance Taylor, Cygnus Support |
| This file is part of GDB, GAS, and the GNU binutils. |
| 196,6 → 195,21 |
| that isn't a superset of POWER8, we can define this to its own mask. */ |
| #define PPC_OPCODE_HTM PPC_OPCODE_POWER8 |
| /* Opcode is supported by ppc750cl. */ |
| #define PPC_OPCODE_750 0x4000000000ull |
| /* Opcode is supported by ppc7450. */ |
| #define PPC_OPCODE_7450 0x8000000000ull |
| /* Opcode is supported by ppc821/850/860. */ |
| #define PPC_OPCODE_860 0x10000000000ull |
| /* Opcode is only supported by Power9 architecture. */ |
| #define PPC_OPCODE_POWER9 0x20000000000ull |
| /* Opcode is supported by Vector-Scalar (VSX) Unit from ISA 2.08. */ |
| #define PPC_OPCODE_VSX3 0x40000000000ull |
| /* A macro to extract the major opcode from an instruction. */ |
| #define PPC_OP(i) (((i) >> 26) & 0x3f) |
| 278,7 → 292,7 |
| /* Use with the shift field of a struct powerpc_operand to indicate |
| that BITM and SHIFT cannot be used to determine where the operand |
| goes in the insn. */ |
| #define PPC_OPSHIFT_INV (-1 << 31) |
| #define PPC_OPSHIFT_INV (-1U << 31) |
| /* Values defined for the flags field of a struct powerpc_operand. */ |
| 382,6 → 396,11 |
| /* This is a CR FIELD that does not use symbolic names. */ |
| #define PPC_OPERAND_CR_REG (0x200000) |
| /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand |
| is omitted, then the value it should use for the operand is stored |
| in the SHIFT field of the immediatly following operand field. */ |
| #define PPC_OPERAND_OPTIONAL_VALUE (0x400000) |
| /* The POWER and PowerPC assemblers use a few macros. We keep them |
| with the operands table for simplicity. The macro table is an |
| array of struct powerpc_macro. */ |
| 410,4 → 429,12 |
| extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *); |
| static inline long |
| ppc_optional_operand_value (const struct powerpc_operand *operand) |
| { |
| if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0) |
| return (operand+1)->shift; |
| return 0; |
| } |
| #endif /* PPC_H */ |
| /contrib/toolchain/binutils/include/opcode/pyr.h |
|---|
| 1,6 → 1,6 |
| /* pyramid.opcode.h -- gdb initial attempt. |
| Copyright 2001, 2010 Free Software Foundation, Inc. |
| Copyright (C) 2001-2015 Free Software Foundation, Inc. |
| This program is free software; you can redistribute it and/or modify |
| it under the terms of the GNU General Public License as published by |
| /contrib/toolchain/binutils/include/opcode/rl78.h |
|---|
| 1,6 → 1,5 |
| /* Opcode decoder for the Renesas RL78 |
| Copyright 2011 |
| Free Software Foundation, Inc. |
| Copyright (C) 2011-2015 Free Software Foundation, Inc. |
| Written by DJ Delorie <dj@redhat.com> |
| This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler. |
| 27,6 → 26,17 |
| #ifndef RL78_OPCODES_H_INCLUDED |
| #define RL78_OPCODES_H_INCLUDED |
| #ifdef __cplusplus |
| extern "C" { |
| #endif |
| typedef enum { |
| RL78_ISA_DEFAULT, |
| RL78_ISA_G10, |
| RL78_ISA_G13, |
| RL78_ISA_G14, |
| } RL78_Dis_Isa; |
| /* For the purposes of these structures, the RL78 registers are as |
| follows, despite most of these being memory-mapped and |
| bank-switched: */ |
| 163,6 → 173,10 |
| RL78_Opcode_Operand op[2]; |
| } RL78_Opcode_Decoded; |
| int rl78_decode_opcode (unsigned long, RL78_Opcode_Decoded *, int (*)(void *), void *); |
| int rl78_decode_opcode (unsigned long, RL78_Opcode_Decoded *, int (*)(void *), void *, RL78_Dis_Isa); |
| #ifdef __cplusplus |
| } |
| #endif |
| #endif |
| /contrib/toolchain/binutils/include/opcode/rx.h |
|---|
| 1,6 → 1,5 |
| /* Opcode decoder for the Renesas RX |
| Copyright 2008, 2009, 2010 |
| Free Software Foundation, Inc. |
| Copyright (C) 2008-2015 Free Software Foundation, Inc. |
| Written by DJ Delorie <dj@redhat.com> |
| This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler. |
| 24,6 → 23,10 |
| analyzer, and the disassembler. Given an opcode data source, |
| it decodes the next opcode into the following structures. */ |
| #ifdef __cplusplus |
| extern "C" { |
| #endif |
| typedef enum |
| { |
| RX_AnySize = 0, |
| 35,6 → 38,8 |
| RX_SWord, |
| RX_3Byte, |
| RX_Long, |
| RX_Bad_Size, |
| RX_MAX_SIZE |
| } RX_Size; |
| typedef enum |
| 43,6 → 48,7 |
| RX_Operand_Immediate, /* #addend */ |
| RX_Operand_Register, /* Rn */ |
| RX_Operand_Indirect, /* [Rn + addend] */ |
| RX_Operand_Zero_Indirect,/* [Rn] */ |
| RX_Operand_Postinc, /* [Rn+] */ |
| RX_Operand_Predec, /* [-Rn] */ |
| RX_Operand_Condition, /* eq, gtu, etc */ |
| 98,6 → 104,10 |
| RXO_nop, |
| RXO_nop2, |
| RXO_nop3, |
| RXO_nop4, |
| RXO_nop5, |
| RXO_nop6, |
| RXO_nop7, |
| RXO_scmpu, |
| RXO_smovu, |
| 213,3 → 223,7 |
| registers. 32..47 are condition codes. */ |
| int rx_decode_opcode (unsigned long, RX_Opcode_Decoded *, int (*)(void *), void *); |
| #ifdef __cplusplus |
| } |
| #endif |
| /contrib/toolchain/binutils/include/opcode/s390.h |
|---|
| 1,5 → 1,5 |
| /* s390.h -- Header file for S390 opcode table |
| Copyright 2000, 2001, 2003, 2010 Free Software Foundation, Inc. |
| Copyright (C) 2000-2015 Free Software Foundation, Inc. |
| Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). |
| This file is part of BFD, the Binary File Descriptor library. |
| 41,9 → 41,16 |
| S390_OPCODE_Z10, |
| S390_OPCODE_Z196, |
| S390_OPCODE_ZEC12, |
| S390_OPCODE_Z13, |
| S390_OPCODE_MAXCPU |
| }; |
| /* Instruction specific flags. */ |
| #define S390_INSTR_FLAG_OPTPARM 0x1 |
| #define S390_INSTR_FLAG_HTM 0x2 |
| #define S390_INSTR_FLAG_VX 0x4 |
| #define S390_INSTR_FLAG_FACILITY_MASK 0x6 |
| /* The opcode table is an array of struct s390_opcode. */ |
| struct s390_opcode |
| 74,6 → 81,9 |
| /* First cpu this opcode is available for. */ |
| enum s390_opcode_cpu_val min_cpu; |
| /* Instruction specific flags. */ |
| unsigned int flags; |
| }; |
| /* The table itself is sorted by major opcode number, and is otherwise |
| 86,7 → 96,7 |
| extern const struct s390_opcode s390_opformats[]; |
| extern const int s390_num_opformats; |
| /* Values defined for the flags field of a struct powerpc_opcode. */ |
| /* Values defined for the flags field of a struct s390_opcode. */ |
| /* The operands table is an array of struct s390_operand. */ |
| 103,7 → 113,7 |
| }; |
| /* Elements in the table are retrieved by indexing with values from |
| the operands field of the powerpc_opcodes table. */ |
| the operands field of the s390_opcodes table. */ |
| extern const struct s390_operand s390_operands[]; |
| 151,4 → 161,14 |
| /* The operand needs to be a valid GP or FP register pair. */ |
| #define S390_OPERAND_REG_PAIR 0x800 |
| /* This operand names a vector register. The disassembler uses this |
| to print register names with a leading 'v'. */ |
| #define S390_OPERAND_VR 0x1000 |
| #define S390_OPERAND_CP16 0x2000 |
| #define S390_OPERAND_OR1 0x4000 |
| #define S390_OPERAND_OR2 0x8000 |
| #define S390_OPERAND_OR8 0x10000 |
| #endif /* S390_H */ |
| /contrib/toolchain/binutils/include/opcode/score-datadep.h |
|---|
| 1,5 → 1,5 |
| /* score-datadep.h -- Score Instructions data dependency table |
| Copyright 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. |
| Copyright (C) 2006-2015 Free Software Foundation, Inc. |
| Contributed by: |
| Brain.lin (brain.lin@sunplusct.com) |
| Mei Ligang (ligang@sunnorth.com.cn) |
| /contrib/toolchain/binutils/include/opcode/score-inst.h |
|---|
| 1,5 → 1,5 |
| /* score-inst.h -- Score Instructions Table |
| Copyright 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. |
| Copyright (C) 2006-2015 Free Software Foundation, Inc. |
| Contributed by: |
| Brain.lin (brain.lin@sunplusct.com) |
| Mei Ligang (ligang@sunnorth.com.cn) |
| /contrib/toolchain/binutils/include/opcode/sparc.h |
|---|
| 1,6 → 1,5 |
| /* Definitions for opcode table for the sparc. |
| Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002, |
| 2003, 2005, 2010, 2011 Free Software Foundation, Inc. |
| Copyright (C) 1989-2015 Free Software Foundation, Inc. |
| This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and |
| the GNU Binutils. |
| 101,6 → 100,7 |
| /* This was called "delayed" in versions before the flags. */ |
| unsigned int flags; |
| unsigned int hwcaps; |
| unsigned int hwcaps2; |
| short architecture; /* Bitmask of sparc_opcode_arch_val's. */ |
| } sparc_opcode; |
| 116,7 → 116,8 |
| #define F_PREF_ALIAS (F_ALIAS|F_PREFERRED) |
| /* These must match the HWCAP_* values precisely. */ |
| /* These must match the ELF_SPARC_HWCAP_* and ELF_SPARC_HWCAP2_* |
| values precisely. See include/elf/sparc.h. */ |
| #define HWCAP_MUL32 0x00000001 /* umul/umulcc/smul/smulcc insns */ |
| #define HWCAP_DIV32 0x00000002 /* udiv/udivcc/sdiv/sdivcc insns */ |
| #define HWCAP_FSMULD 0x00000004 /* 'fsmuld' insn */ |
| 149,6 → 150,20 |
| #define HWCAP_CBCOND 0x10000000 /* Compare and Branch insns */ |
| #define HWCAP_CRC32C 0x20000000 /* CRC32C insn */ |
| #define HWCAP2_FJATHPLUS 0x00000001 /* Fujitsu Athena+ */ |
| #define HWCAP2_VIS3B 0x00000002 /* Subset of VIS3 present on sparc64 X+. */ |
| #define HWCAP2_ADP 0x00000004 /* Application Data Protection */ |
| #define HWCAP2_SPARC5 0x00000008 /* The 29 new fp and sub instructions */ |
| #define HWCAP2_MWAIT 0x00000010 /* mwait instruction and load/monitor ASIs */ |
| #define HWCAP2_XMPMUL 0x00000020 /* XOR multiple precision multiply */ |
| #define HWCAP2_XMONT 0x00000040 /* XOR Montgomery mult/sqr instructions */ |
| #define HWCAP2_NSEC \ |
| 0x00000080 /* pause insn with support for nsec timings */ |
| #define HWCAP2_FJATHHPC 0x00001000 /* Fujitsu HPC instrs */ |
| #define HWCAP2_FJDES 0x00002000 /* Fujitsu DES instrs */ |
| #define HWCAP2_FJAES 0x00010000 /* Fujitsu AES instrs */ |
| /* All sparc opcodes are 32 bits, except for the `set' instruction (really a |
| macro), which is 64 bits. It is handled as a special case. |
| 174,6 → 189,7 |
| g frsd floating point register. |
| H frsd floating point register (double/even). |
| J frsd floating point register (quad/multiple of 4). |
| } frsd floating point register (double/even) that is == frs2 |
| b crs1 coprocessor register |
| c crs2 coprocessor register |
| D crsd coprocessor register |
| 215,6 → 231,7 |
| s %fprs. (v9) |
| P %pc. (v9) |
| W %tick. (v9) |
| { %mcdper. (v9b) |
| o %asi. (v9) |
| 6 %fcc0. (v9) |
| 7 %fcc1. (v9) |
| /contrib/toolchain/binutils/include/opcode/spu-insns.h |
|---|
| 1,6 → 1,6 |
| /* SPU ELF support for BFD. |
| Copyright 2006, 2007, 2010 Free Software Foundation, Inc. |
| Copyright (C) 2006-2015 Free Software Foundation, Inc. |
| This file is part of BFD, the Binary File Descriptor library. |
| /contrib/toolchain/binutils/include/opcode/spu.h |
|---|
| 1,6 → 1,6 |
| /* SPU ELF support for BFD. |
| Copyright 2006, 2010 Free Software Foundation, Inc. |
| Copyright (C) 2006-2015 Free Software Foundation, Inc. |
| This file is part of GDB, GAS, and the GNU binutils. |
| /contrib/toolchain/binutils/include/opcode/tahoe.h |
|---|
| 2,7 → 2,7 |
| * Ported by the State University of New York at Buffalo by the Distributed |
| * Computer Systems Lab, Department of Computer Science, 1991. |
| */ |
| /* Copyright 2012 Free Software Foundation, Inc. |
| /* Copyright (C) 2012-2015 Free Software Foundation, Inc. |
| This file is part of GDB and BINUTILS. |
| /contrib/toolchain/binutils/include/opcode/tic30.h |
|---|
| 1,5 → 1,5 |
| /* tic30.h -- Header file for TI TMS320C30 opcode table |
| Copyright 1998, 2005, 2009, 2010 Free Software Foundation, Inc. |
| Copyright (C) 1998-2015 Free Software Foundation, Inc. |
| Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au) |
| This file is part of GDB, GAS, and the GNU binutils. |
| /contrib/toolchain/binutils/include/opcode/tic4x.h |
|---|
| 1,6 → 1,6 |
| /* Table of opcodes for the Texas Instruments TMS320C[34]X family. |
| Copyright (C) 2002, 2003, 2010 Free Software Foundation. |
| Copyright (C) 2002-2015 Free Software Foundation, Inc. |
| Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz) |
| /contrib/toolchain/binutils/include/opcode/tic54x.h |
|---|
| 1,5 → 1,5 |
| /* tic54x.h -- Header file for TI TMS320C54X opcode table |
| Copyright 1999, 2000, 2001, 2005, 2009, 2010 Free Software Foundation, Inc. |
| Copyright (C) 1999-2015 Free Software Foundation, Inc. |
| Written by Timothy Wall (twall@cygnus.com) |
| This file is part of GDB, GAS, and the GNU binutils. |
| /contrib/toolchain/binutils/include/opcode/tic6x-control-registers.h |
|---|
| 1,6 → 1,5 |
| /* TI C6X control register information. |
| Copyright 2010 |
| Free Software Foundation, Inc. |
| Copyright (C) 2010-2015 Free Software Foundation, Inc. |
| This program is free software; you can redistribute it and/or modify |
| it under the terms of the GNU General Public License as published by |
| /contrib/toolchain/binutils/include/opcode/tic6x-insn-formats.h |
|---|
| 1,5 → 1,5 |
| /* TI C6X instruction format information. |
| Copyright 2010-2013 Free Software Foundation, Inc. |
| Copyright (C) 2010-2015 Free Software Foundation, Inc. |
| This program is free software; you can redistribute it and/or modify |
| it under the terms of the GNU General Public License as published by |
| /contrib/toolchain/binutils/include/opcode/tic6x-opcode-table.h |
|---|
| 1,5 → 1,5 |
| /* TI C6X opcode table. |
| Copyright 2010-2013 Free Software Foundation, Inc. |
| Copyright (C) 2010-2015 Free Software Foundation, Inc. |
| This program is free software; you can redistribute it and/or modify |
| it under the terms of the GNU General Public License as published by |
| /contrib/toolchain/binutils/include/opcode/tic6x.h |
|---|
| 1,5 → 1,5 |
| /* TI C6X opcode information. |
| Copyright 2010-2013 Free Software Foundation, Inc. |
| Copyright (C) 2010-2015 Free Software Foundation, Inc. |
| This program is free software; you can redistribute it and/or modify |
| it under the terms of the GNU General Public License as published by |
| /contrib/toolchain/binutils/include/opcode/tic80.h |
|---|
| 1,5 → 1,5 |
| /* tic80.h -- Header file for TI TMS320C80 (MV) opcode table |
| Copyright 1996, 1997, 2003, 2010 Free Software Foundation, Inc. |
| Copyright (C) 1996-2015 Free Software Foundation, Inc. |
| Written by Fred Fish (fnf@cygnus.com), Cygnus Support |
| This file is part of GDB, GAS, and the GNU binutils. |
| /contrib/toolchain/binutils/include/opcode/tilegx.h |
|---|
| 1,6 → 1,6 |
| /* TILE-Gx opcode information. |
| * |
| * Copyright 2011 Free Software Foundation, Inc. |
| * Copyright (C) 2011-2015 Free Software Foundation, Inc. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as published by |
| 21,6 → 21,10 |
| #ifndef opcode_tile_h |
| #define opcode_tile_h |
| #ifdef __cplusplus |
| extern "C" { |
| #endif |
| typedef unsigned long long tilegx_bundle_bits; |
| 1301,4 → 1305,8 |
| #define TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES \ |
| TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES |
| #ifdef __cplusplus |
| } |
| #endif |
| #endif /* opcode_tilegx_h */ |
| /contrib/toolchain/binutils/include/opcode/tilepro.h |
|---|
| 1,6 → 1,6 |
| /* TILEPro opcode information. |
| * |
| * Copyright 2011 Free Software Foundation, Inc. |
| * Copyright (C) 2011-2015 Free Software Foundation, Inc. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as published by |
| /contrib/toolchain/binutils/include/opcode/v850.h |
|---|
| 1,5 → 1,5 |
| /* v850.h -- Header file for NEC V850 opcode table |
| Copyright 1996-2013 Free Software Foundation, Inc. |
| Copyright (C) 1996-2015 Free Software Foundation, Inc. |
| Written by J.T. Conklin, Cygnus Support |
| This file is part of GDB, GAS, and the GNU binutils. |
| /contrib/toolchain/binutils/include/opcode/vax.h |
|---|
| 1,5 → 1,5 |
| /* Vax opcde list. |
| Copyright 1989, 1991, 1992, 1995, 2010 Free Software Foundation, Inc. |
| Copyright (C) 1989-2015 Free Software Foundation, Inc. |
| This file is part of GDB and GAS. |
| /contrib/toolchain/binutils/include/opcode/visium.h |
|---|
| 0,0 → 1,337 |
| /* Opcode table header for Visium. |
| Copyright (C) 2003-2015 Free Software Foundation, Inc. |
| This file is part of GDB, GAS, and GNU binutils. |
| GDB, GAS and the GNU binutils are free software; you can redistribute |
| them and/or modify them under the terms of the GNU General Public |
| License as published by the Free Software Foundation; either version 3, |
| or (at your option) any later version. |
| GDB, GAS, and the GNU binutils are distributed in the hope that they |
| will be useful, but WITHOUT ANY WARRANTY; without even the implied |
| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See |
| the GNU General Public License for more details. |
| You should have received a copy of the GNU General Public License |
| along with this file; see the file COPYING3. If not, write to the Free |
| Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
| MA 02110-1301, USA. */ |
| enum visium_opcode_arch_val |
| { |
| VISIUM_OPCODE_ARCH_DEF = 0, |
| VISIUM_OPCODE_ARCH_GR5, |
| VISIUM_OPCODE_ARCH_GR6, |
| VISIUM_OPCODE_ARCH_BAD |
| }; |
| /* The highest architecture in the table. */ |
| #define VISIUM_OPCODE_ARCH_MAX (VISIUM_OPCODE_ARCH_BAD - 1) |
| /* Given an enum visium_opcode_arch_val, return the bitmask to use in |
| insn encoding/decoding. */ |
| #define VISIUM_OPCODE_ARCH_MASK(arch) (1 << (arch)) |
| /* Some defines to make life easy. */ |
| #define MASK_DEF VISIUM_OPCODE_ARCH_MASK (VISIUM_OPCODE_ARCH_DEF) |
| #define MASK_GR5 VISIUM_OPCODE_ARCH_MASK (VISIUM_OPCODE_ARCH_GR5) |
| #define MASK_GR6 VISIUM_OPCODE_ARCH_MASK (VISIUM_OPCODE_ARCH_GR6) |
| /* Bit masks of architectures supporting the insn. */ |
| #define def (MASK_DEF | MASK_GR5 | MASK_GR6) |
| #define gr5 (MASK_GR5 | MASK_GR6) |
| #define gr6 (MASK_GR6) |
| /* The condition code field is not used (zero) for most instructions. |
| BRR and BRA make normal use of it. Floating point instructions use |
| it as a sub-opcode. */ |
| #define CC_MASK (0xf << 27) |
| /* It seems a shame not to use these bits in a class 0 instruction, |
| since they could be used to extend the range of the branch. */ |
| #define CLASS0_UNUSED_MASK (0x1f << 16) |
| /* For class 1 instructions the following bit is unused. */ |
| #define CLASS1_UNUSED_MASK (1 << 9) |
| /* For class 1 instructions this field gives the index for a write |
| instruction, the specific operation for an EAM instruction, or |
| the floating point destination register for a floating point |
| instruction. */ |
| #define CLASS1_INDEX_MASK (0x1f << 10) |
| /* For class 3 instructions the following field gives the destination |
| general register. */ |
| #define CLASS3_DEST_MASK (0x1f << 10) |
| /* For class 1 and class 3 instructions the following bit selects an |
| EAM write/read rather than a memory write/read. */ |
| #define EAM_SELECT_MASK (1 << 15) |
| /* Floating point instructions are distinguished from general EAM |
| instructions by the following bit. */ |
| #define FP_SELECT_MASK (1 << 3) |
| /* For both class 1 and class 3 the following fields give, where |
| appropriate the srcA and srcB registers whether floating point |
| or general. */ |
| #define SRCA_MASK (0x1f << 16) |
| #define SRCB_MASK (0x1f << 4) |
| /* The class 3 interrupt bit. It turns a BRA into a SYS1, and an |
| RFLAG into a SYS2. This bit should not be set in the user's |
| class 3 instructions. This bit is also used in class 3 |
| to distinguish between floating point and other EAM operations. |
| (see FP_SELECT_MASK). */ |
| #define CLASS3_INT (1 << 3) |
| /* Class 3 shift instructions use this bit to indicate that the |
| srcB field is a 5 bit immediate shift count rather than a |
| register number. */ |
| #define CLASS3_SOURCEB_IMMED (1 << 9) |
| #define BMD 0x02630004 |
| #define BMI 0x82230004 |
| #define DSI 0x82800004 |
| #define ENI 0x02a00004 |
| #define RFI 0x82fe01d4 |
| struct reg_entry |
| { |
| char *name; |
| unsigned char code; |
| }; |
| static const struct reg_entry gen_reg_table[] = |
| { |
| {"fp", 0x16}, |
| {"r0", 0x0}, |
| {"r1", 0x1}, |
| {"r10", 0xA}, |
| {"r11", 0xB}, |
| {"r12", 0xC}, |
| {"r13", 0xD}, |
| {"r14", 0xE}, |
| {"r15", 0xF}, |
| {"r16", 0x10}, |
| {"r17", 0x11}, |
| {"r18", 0x12}, |
| {"r19", 0x13}, |
| {"r2", 0x2}, |
| {"r20", 0x14}, |
| {"r21", 0x15}, |
| {"r22", 0x16}, |
| {"r23", 0x17}, |
| {"r24", 0x18}, |
| {"r25", 0x19}, |
| {"r26", 0x1a}, |
| {"r27", 0x1b}, |
| {"r28", 0x1c}, |
| {"r29", 0x1d}, |
| {"r3", 0x3}, |
| {"r30", 0x1e}, |
| {"r31", 0x1f}, |
| {"r4", 0x4}, |
| {"r5", 0x5}, |
| {"r6", 0x6}, |
| {"r7", 0x7}, |
| {"r8", 0x8}, |
| {"r9", 0x9}, |
| {"sp", 0x17}, |
| }; |
| static const struct reg_entry fp_reg_table[] = |
| { |
| {"f0", 0x0}, |
| {"f1", 0x1}, |
| {"f10", 0xa}, |
| {"f11", 0xb}, |
| {"f12", 0xc}, |
| {"f13", 0xd}, |
| {"f14", 0xe}, |
| {"f15", 0xf}, |
| {"f2", 0x2}, |
| {"f3", 0x3}, |
| {"f4", 0x4}, |
| {"f5", 0x5}, |
| {"f6", 0x6}, |
| {"f7", 0x7}, |
| {"f8", 0x8}, |
| {"f9", 0x9}, |
| }; |
| static const struct cc_entry |
| { |
| char *name; |
| int code; |
| } cc_table [] = |
| { |
| {"cc", 6}, |
| {"cs", 2}, |
| {"eq", 1}, |
| {"fa", 0}, |
| {"ge", 9}, |
| {"gt", 10}, |
| {"hi", 11}, |
| {"le", 12}, |
| {"ls", 13}, |
| {"lt", 14}, |
| {"nc", 8}, |
| {"ne", 5}, |
| {"ns", 4}, |
| {"oc", 7}, |
| {"os", 3}, |
| {"tr", 15}, |
| }; |
| enum addressing_mode |
| { |
| mode_d, /* register := */ |
| mode_a, /* op= register */ |
| mode_da, /* register := register */ |
| mode_ab, /* register * register */ |
| mode_dab, /* register := register * register */ |
| mode_iab, /* 5-bit immediate * register * register */ |
| mode_0ab, /* zero * register * register */ |
| mode_da0, /* register := register * zero */ |
| mode_cad, /* condition * register * register */ |
| mode_das, /* register := register * 5-bit immed/register shift count */ |
| mode_di, /* register := 5-bit immediate */ |
| mode_ir, /* 5-bit immediate * register */ |
| mode_ai, /* register 16-bit unsigned immediate */ |
| mode_i, /* 16-bit unsigned immediate */ |
| mode_bax, /* register * register * 5-bit immediate */ |
| mode_dax, /* register := register * 5-bit immediate */ |
| mode_s, /* special mode */ |
| mode_sr, /* special mode with register */ |
| mode_ci, /* condition * 16-bit signed word displacement */ |
| mode_fdab, /* float := float * float */ |
| mode_ifdab, /* fpinst: 4-bit immediate * float * float * float */ |
| mode_idfab, /* fpuread: 4-bit immediate * register * float * float */ |
| mode_fda, /* float := float */ |
| mode_fdra, /* float := register */ |
| mode_rdfab, /* register := float * float */ |
| mode_rdfa, /* register := float */ |
| mode_rrr, /* 3 register sources and destinations (block move) */ |
| }; |
| #define class0 (0<<25) |
| #define class1 (1<<25) |
| #define class2 (2<<25) |
| #define class3 (3<<25) |
| static const struct opcode_entry |
| { |
| char *mnem; |
| enum addressing_mode mode; |
| unsigned code; |
| char flags; |
| } |
| opcode_table[] = |
| { |
| { "adc.b", mode_dab, class3|(1<<21)|(1), def }, |
| { "adc.l", mode_dab, class3|(1<<21)|(4), def }, |
| { "adc.w", mode_dab, class3|(1<<21)|(2), def }, |
| { "add.b", mode_dab, class3|(0<<21)|(1), def }, |
| { "add.l", mode_dab, class3|(0<<21)|(4), def }, |
| { "add.w", mode_dab, class3|(0<<21)|(2), def }, |
| { "addi", mode_ai, class2, def }, |
| { "and.b", mode_dab, class3|(10<<21)|(1), def}, |
| { "and.l", mode_dab, class3|(10<<21)|(4), def }, |
| { "and.w", mode_dab, class3|(10<<21)|(2), def }, |
| { "asl.b", mode_das, class3|(7<<21)|(1), def }, |
| { "asl.l", mode_das, class3|(7<<21)|(4), def }, |
| { "asl.w", mode_das, class3|(7<<21)|(2), def }, |
| { "asld", mode_a, class1|(15<<21)|(1<<15)|(11<<10)|(4), def }, |
| { "asr.b", mode_das, class3|(5<<21)|(1), def }, |
| { "asr.l", mode_das, class3|(5<<21)|(4), def }, |
| { "asr.w", mode_das, class3|(5<<21)|(2), def }, |
| { "asrd", mode_a, class1|(15<<21)|(1<<15)|(9<<10)|(4), def }, |
| { "bmd", mode_rrr, class1|(3<<21)|(3<<16)|(4), gr6 }, |
| { "bmi", mode_rrr, class1|(1<<21)|(3<<16)|(4), gr6 }, |
| { "bra", mode_cad, class3|(12<<21)|(4), def }, |
| { "brr", mode_ci, class0, def }, |
| { "cmp.b", mode_0ab, class3|(2<<21)|(1), def }, |
| { "cmp.l", mode_0ab, class3|(2<<21)|(4), def }, |
| { "cmp.w", mode_0ab, class3|(2<<21)|(2), def }, |
| { "cmpc.b", mode_0ab, class3|(3<<21)|(1), def }, |
| { "cmpc.l", mode_0ab, class3|(3<<21)|(4), def }, |
| { "cmpc.w", mode_0ab, class3|(3<<21)|(2), def }, |
| { "divds", mode_a, class1|(15<<21)|(1<<15)|(6<<10)|(4), def }, |
| { "divdu", mode_a, class1|(15<<21)|(1<<15)|(7<<10)|(4), def }, |
| { "divs", mode_a, class1|(15<<21)|(1<<15)|(2<<10)|(4), def }, |
| { "divu", mode_a, class1|(15<<21)|(1<<15)|(3<<10)|(4), def }, |
| { "dsi", mode_s, class1|(4<<21)|(4), def }, |
| { "eamread", mode_di, class3|(15<<21)|(1<<15)|(1<<9)|(4), def }, |
| { "eamwrite", mode_iab, class1|(15<<21)|(1<<15)|(4), def }, |
| { "eni", mode_s, class1|(5<<21)|(4), def }, |
| { "extb.b", mode_da, class3|(14<<21)|(1), def }, |
| { "extb.l", mode_da, class3|(14<<21)|(4), def }, |
| { "extb.w", mode_da, class3|(14<<21)|(2), def }, |
| { "extw.l", mode_da, class3|(4<<21)|(4), def }, |
| { "extw.w", mode_da, class3|(4<<21)|(2), def }, |
| { "fabs", mode_fda, class1|(7<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 }, |
| { "fadd", mode_fdab, class1|(1<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 }, |
| { "fcmp", mode_rdfab,class3|(10<<27)|(15<<21)|(1<<15)|(1<<9)|(1<<3)|(4), gr5 }, |
| { "fcmpe", mode_rdfab,class3|(11<<27)|(15<<21)|(1<<15)|(1<<9)|(1<<3)|(4), gr5 }, |
| { "fdiv", mode_fdab, class1|(4<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 }, |
| { "fload", mode_fdra, class1|(15<<21)|(1<<15)|(1<<3)|(4), gr5 }, |
| { "fmove", mode_fda, class1|(12<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5}, |
| { "fmult", mode_fdab, class1|(3<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 }, |
| { "fneg", mode_fda, class1|(6<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 }, |
| { "fpinst", mode_ifdab,class1|(15<<21)|(1<<15)|(1<<3)|(4), gr5 }, |
| { "fpuread", mode_idfab,class3|(15<<21)|(1<<15)|(1<<9)|(1<<3)|(4), gr5 }, |
| { "fsqrt", mode_fda, class1|(5<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 }, |
| { "fstore", mode_rdfa, class3|(15<<21)|(1<<15)|(1<<9)|(1<<3)|(4), gr5 }, |
| { "fsub", mode_fdab, class1|(2<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 }, |
| { "ftoi", mode_fda, class1|(8<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 }, |
| { "itof", mode_fda, class1|(9<<27)|(15<<21)|(1<<15)|(1<<3)|(4), gr5 }, |
| { "lsr.b", mode_das, class3|(6<<21)|(1), def }, |
| { "lsr.l", mode_das, class3|(6<<21)|(4), def }, |
| { "lsr.w", mode_das, class3|(6<<21)|(2), def }, |
| { "lsrd", mode_a, class1|(15<<21)|(1<<15)|(10<<10)|(4), def }, |
| { "move.b", mode_da0, class3|(9<<21)|(1), def }, |
| { "move.l", mode_da0, class3|(9<<21)|(4), def }, |
| { "move.w", mode_da0, class3|(9<<21)|(2), def }, |
| { "movil", mode_ai, class2|(4<<21), def }, |
| { "moviq", mode_ai, class2|(6<<21), def }, |
| { "moviu", mode_ai, class2|(5<<21), def }, |
| { "mults", mode_ab, class1|(15<<21)|(1<<15)|(0<<10)|(4), def }, |
| { "multu", mode_ab, class1|(15<<21)|(1<<15)|(1<<10)|(4), def }, |
| { "nop", mode_s, class0, def }, |
| { "not.b", mode_da, class3|(11<<21)|(1), def }, |
| { "not.l", mode_da, class3|(11<<21)|(4), def }, |
| { "not.w", mode_da, class3|(11<<21)|(2), def }, |
| { "or.b", mode_dab, class3|(9<<21)|(1), def }, |
| { "or.l", mode_dab, class3|(9<<21)|(4), def }, |
| { "or.w", mode_dab, class3|(9<<21)|(2), def }, |
| { "read.b", mode_dax, class3|(15<<21)|(1<<9)|(1), def }, |
| { "read.l", mode_dax, class3|(15<<21)|(1<<9)|(4), def }, |
| { "read.w", mode_dax, class3|(15<<21)|(1<<9)|(2), def }, |
| { "readmda", mode_d, class3|(15<<21)|(1<<15)|(1<<9)|(4), def }, |
| { "readmdb", mode_d, class3|(15<<21)|(1<<15)|(1<<9)|(1<<4)|(4), def }, |
| { "readmdc", mode_d, class3|(15<<21)|(1<<15)|(1<<9)|(2<<4)|(4), def }, |
| { "rfi", mode_s, class1|(7<<21)|(30<<16)|(29<<4)|(4), def }, |
| { "rflag", mode_d, class3|(13<<21)|(4), def }, |
| { "stop", mode_ir, class1|(0<<21)|(4), def }, |
| { "sub.b", mode_dab, class3|(2<<21)|(1), def }, |
| { "sub.l", mode_dab, class3|(2<<21)|(4), def }, |
| { "sub.w", mode_dab, class3|(2<<21)|(2), def }, |
| { "subc.b", mode_dab, class3|(3<<21)|(1), def }, |
| { "subc.l", mode_dab, class3|(3<<21)|(4), def }, |
| { "subc.w", mode_dab, class3|(3<<21)|(2), def }, |
| { "subi", mode_ai, class2|(2<<21), def }, |
| { "trace", mode_ir, class1|(13<<21), def }, |
| { "write.b", mode_bax, class1|(15<<21)|(1), def }, |
| { "write.l", mode_bax, class1|(15<<21)|(4), def }, |
| { "write.w", mode_bax, class1|(15<<21)|(2), def }, |
| { "writemd", mode_ab, class1|(15<<21)|(1<<15)|(4<<10)|(4), def }, |
| { "writemdc", mode_a, class1|(15<<21)|(1<<15)|(5<<10)|(4), def }, |
| { "wrtl", mode_i, class2|(8<<21), gr6 }, |
| { "wrtu", mode_i, class2|(9<<21), gr6 }, |
| { "xor.b", mode_dab, class3|(8<<21)|(1), def }, |
| { "xor.l", mode_dab, class3|(8<<21)|(4), def }, |
| { "xor.w", mode_dab, class3|(8<<21)|(2), def }, |
| }; |
| /contrib/toolchain/binutils/include/opcode/xgate.h |
|---|
| 1,5 → 1,5 |
| /* xgate.h -- Freescale XGATE opcode list |
| Copyright 2010, 2011, 2012 Free Software Foundation, Inc. |
| Copyright (C) 2010-2015 Free Software Foundation, Inc. |
| Written by Sean Keys (skeys@ipdatasys.com) |
| This file is part of the GNU opcodes library. |
| 46,37 → 46,23 |
| #define XGATE_CYCLE_A 0x40 |
| #define XGATE_CYCLE_f 0x80 |
| /* Opcode format abbreviations. */ |
| #define XG_INH 0x0001 /* Inherent. */ |
| #define XG_I 0x0002 /* 3-bit immediate address. */ |
| #define XG_R_I 0x0004 /* Register followed by 4/8-bit immediate value. */ |
| #define XG_R_R 0x0008 /* Register followed by a register. */ |
| #define XG_R_R_R 0x0010 /* Register followed by two registers. */ |
| #define XG_R 0x0020 /* Single register. */ |
| #define XG_PC 0x0040 /* PC relative 10 or 11 bit. */ |
| #define XG_R_C 0x0080 /* General register followed by ccr register. */ |
| #define XG_C_R 0x0100 /* CCR register followed by a general register. */ |
| #define XG_R_P 0x0200 /* General register followed by pc register. */ |
| #define XG_R_R_I 0x0400 /* Two general registers followed by an immediate value. */ |
| #define XG_PCREL 0x0800 /* Immediate value that is relative to the current pc. */ |
| /* XGATE operand formats as stored in the XGATE_opcode table. |
| They are only used by GAS to recognize operands. */ |
| #define XGATE_OP_INH "" |
| #define XGATE_OP_TRI "r,r,r" |
| #define XGATE_OP_DYA "r,r" |
| #define XGATE_OP_IMM16 "r,if" |
| #define XGATE_OP_IMM8 "r,i8" |
| #define XGATE_OP_IMM4 "r,i4" |
| #define XGATE_OP_IMM3 "i3" |
| #define XGATE_OP_MON "r" |
| #define XGATE_OP_MON_R_C "r,c" |
| #define XGATE_OP_MON_C_R "c,r" |
| #define XGATE_OP_MON_R_P "r,p" |
| #define XGATE_OP_IDR "r,r,+" |
| #define XGATE_OP_IDO5 "r,r,i5" |
| #define XGATE_OP_REL9 "b9" |
| #define XGATE_OP_REL10 "ba" |
| #define XGATE_OP_INH "" /* Inherent. */ |
| #define XGATE_OP_TRI "r,r,r" /* Register followed by two registers. */ |
| #define XGATE_OP_DYA "r,r" /* Register followed by a register. */ |
| #define XGATE_OP_IMM16 "r,if" /* Register followed by 16-bit value. */ |
| #define XGATE_OP_IMM8 "r,i8" /* Register followed by 8-bit value. */ |
| #define XGATE_OP_IMM4 "r,i4" /* Register followed by 4-bit value. */ |
| #define XGATE_OP_IMM3 "i3" /* Register followed by 3-bit value. */ |
| #define XGATE_OP_MON "r" /* Single register. */ |
| #define XGATE_OP_MON_R_C "r,c" /* General register followed by ccr register. */ |
| #define XGATE_OP_MON_C_R "c,r" /* CCR register followed by a general register. */ |
| #define XGATE_OP_MON_R_P "r,p" /* General register followed by pc register. */ |
| #define XGATE_OP_IDR "r,r,+" /* Three registers with the third having a -/+ directive. */ |
| #define XGATE_OP_IDO5 "r,r,i5" /* Two general registers followed by an immediate value. */ |
| #define XGATE_OP_REL9 "b9" /* 9-bit value that is relative to the current pc. */ |
| #define XGATE_OP_REL10 "ba" /* 10-bit value that is relative to the current pc. */ |
| #define XGATE_OP_DYA_MON "=r" |
| /* Macro definitions. */ |
| #define XGATE_OP_IMM16mADD "r,if; addl addh" |
| 90,11 → 76,6 |
| #define XGATE_V2 0x2 |
| #define XGATE_V3 0x4 |
| /* Max opcodes per opcode handle. */ |
| #define MAX_OPCODES 0x05 |
| #define MAX_DETECT_CHARS 0x10 |
| /* The opcode table definitions. */ |
| struct xgate_opcode |
| { |
| 101,7 → 82,6 |
| char * name; /* Op-code name. */ |
| char * constraints; /* Constraint chars. */ |
| char * format; /* Bit definitions. */ |
| unsigned int sh_format; /* Shorthand format mask. */ |
| unsigned int size; /* Opcode size in bytes. */ |
| unsigned int bin_opcode; /* Binary opcode with operands masked off. */ |
| unsigned char cycles_min; /* Minimum cpu cycles needed. */ |