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  → /contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/svga/include/ @ 5563

  → /contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/svga/include/ @ 5564

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Regard whitespace Rev 5563 → Rev 5564

/contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/svga/include/README
0,0 → 1,3
This directory contains the headers from the VMware SVGA Device Developer Kit:
https://vmware-svga.svn.sourceforge.net/svnroot/vmware-svga/trunk/lib/vmware/

/contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/svga/include/includeCheck.h
0,0 → 1,0
/* dummy file */

/contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/svga/include/svga3d_caps.h
0,0 → 1,114
/**********************************************************
* Copyright 2007-2014 VMware, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
**********************************************************/
/*
* svga3d_caps.h --
*
* Definitions for SVGA3D hardware capabilities. Capabilities
* are used to query for optional rendering features during
* driver initialization. The capability data is stored as very
* basic key/value dictionary within the "FIFO register" memory
* area at the beginning of BAR2.
*
* Note that these definitions are only for 3D capabilities.
* The SVGA device also has "device capabilities" and "FIFO
* capabilities", which are non-3D-specific and are stored as
* bitfields rather than key/value pairs.
*/
#ifndef _SVGA3D_CAPS_H_
#define _SVGA3D_CAPS_H_
#define INCLUDE_ALLOW_MODULE
#define INCLUDE_ALLOW_USERLEVEL
#include "includeCheck.h"
#include <string.h>
#include "svga_reg.h"
#define SVGA_FIFO_3D_CAPS_SIZE (SVGA_FIFO_3D_CAPS_LAST - \
SVGA_FIFO_3D_CAPS + 1)
/*
* SVGA3dCapsRecordType
*
* Record types that can be found in the caps block.
* Related record types are grouped together numerically so that
* SVGA3dCaps_FindRecord() can be applied on a range of record
* types.
*/
typedef enum {
SVGA3DCAPS_RECORD_UNKNOWN = 0,
SVGA3DCAPS_RECORD_DEVCAPS_MIN = 0x100,
SVGA3DCAPS_RECORD_DEVCAPS = 0x100,
SVGA3DCAPS_RECORD_DEVCAPS_MAX = 0x1ff,
} SVGA3dCapsRecordType;
/*
* SVGA3dCapsRecordHeader
*
* Header field leading each caps block record. Contains the offset (in
* register words, NOT bytes) to the next caps block record (or the end
* of caps block records which will be a zero word) and the record type
* as defined above.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCapsRecordHeader {
uint32 length;
SVGA3dCapsRecordType type;
}
#include "vmware_pack_end.h"
SVGA3dCapsRecordHeader;
/*
* SVGA3dCapsRecord
*
* Caps block record; "data" is a placeholder for the actual data structure
* contained within the record; for example a record containing a FOOBAR
* structure would be of size "sizeof(SVGA3dCapsRecordHeader) +
* sizeof(FOOBAR)".
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCapsRecord {
SVGA3dCapsRecordHeader header;
uint32 data[1];
}
#include "vmware_pack_end.h"
SVGA3dCapsRecord;
typedef uint32 SVGA3dCapPair[2];
#endif // _SVGA3D_CAPS_H_

/contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/svga/include/svga3d_cmd.h
0,0 → 1,1654
/**********************************************************
* Copyright 1998-2014 VMware, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
**********************************************************/
/*
* svga3d_cmd.h --
*
* SVGA 3d hardware cmd definitions
*/
#ifndef _SVGA3D_CMD_H_
#define _SVGA3D_CMD_H_
#define INCLUDE_ALLOW_MODULE
#define INCLUDE_ALLOW_USERLEVEL
#define INCLUDE_ALLOW_VMCORE
#include "includeCheck.h"
#include "svga3d_types.h"
/*
* Identifiers for commands in the command FIFO.
*
* IDs between 1000 and 1039 (inclusive) were used by obsolete versions of
* the SVGA3D protocol and remain reserved; they should not be used in the
* future.
*
* IDs between 1040 and 1999 (inclusive) are available for use by the
* current SVGA3D protocol.
*
* FIFO clients other than SVGA3D should stay below 1000, or at 2000
* and up.
*/
#define SVGA_3D_CMD_LEGACY_BASE 1000
#define SVGA_3D_CMD_BASE 1040
#define SVGA_3D_CMD_SURFACE_DEFINE 1040
#define SVGA_3D_CMD_SURFACE_DESTROY 1041
#define SVGA_3D_CMD_SURFACE_COPY 1042
#define SVGA_3D_CMD_SURFACE_STRETCHBLT 1043
#define SVGA_3D_CMD_SURFACE_DMA 1044
#define SVGA_3D_CMD_CONTEXT_DEFINE 1045
#define SVGA_3D_CMD_CONTEXT_DESTROY 1046
#define SVGA_3D_CMD_SETTRANSFORM 1047
#define SVGA_3D_CMD_SETZRANGE 1048
#define SVGA_3D_CMD_SETRENDERSTATE 1049
#define SVGA_3D_CMD_SETRENDERTARGET 1050
#define SVGA_3D_CMD_SETTEXTURESTATE 1051
#define SVGA_3D_CMD_SETMATERIAL 1052
#define SVGA_3D_CMD_SETLIGHTDATA 1053
#define SVGA_3D_CMD_SETLIGHTENABLED 1054
#define SVGA_3D_CMD_SETVIEWPORT 1055
#define SVGA_3D_CMD_SETCLIPPLANE 1056
#define SVGA_3D_CMD_CLEAR 1057
#define SVGA_3D_CMD_PRESENT 1058
#define SVGA_3D_CMD_SHADER_DEFINE 1059
#define SVGA_3D_CMD_SHADER_DESTROY 1060
#define SVGA_3D_CMD_SET_SHADER 1061
#define SVGA_3D_CMD_SET_SHADER_CONST 1062
#define SVGA_3D_CMD_DRAW_PRIMITIVES 1063
#define SVGA_3D_CMD_SETSCISSORRECT 1064
#define SVGA_3D_CMD_BEGIN_QUERY 1065
#define SVGA_3D_CMD_END_QUERY 1066
#define SVGA_3D_CMD_WAIT_FOR_QUERY 1067
#define SVGA_3D_CMD_PRESENT_READBACK 1068
#define SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN 1069
#define SVGA_3D_CMD_SURFACE_DEFINE_V2 1070
#define SVGA_3D_CMD_GENERATE_MIPMAPS 1071
#define SVGA_3D_CMD_VIDEO_CREATE_DECODER 1072
#define SVGA_3D_CMD_VIDEO_DESTROY_DECODER 1073
#define SVGA_3D_CMD_VIDEO_CREATE_PROCESSOR 1074
#define SVGA_3D_CMD_VIDEO_DESTROY_PROCESSOR 1075
#define SVGA_3D_CMD_VIDEO_DECODE_START_FRAME 1076
#define SVGA_3D_CMD_VIDEO_DECODE_RENDER 1077
#define SVGA_3D_CMD_VIDEO_DECODE_END_FRAME 1078
#define SVGA_3D_CMD_VIDEO_PROCESS_FRAME 1079
#define SVGA_3D_CMD_ACTIVATE_SURFACE 1080
#define SVGA_3D_CMD_DEACTIVATE_SURFACE 1081
#define SVGA_3D_CMD_SCREEN_DMA 1082
#define SVGA_3D_CMD_SET_UNITY_SURFACE_COOKIE 1083
#define SVGA_3D_CMD_OPEN_CONTEXT_SURFACE 1084
#define SVGA_3D_CMD_LOGICOPS_BITBLT 1085
#define SVGA_3D_CMD_LOGICOPS_TRANSBLT 1086
#define SVGA_3D_CMD_LOGICOPS_STRETCHBLT 1087
#define SVGA_3D_CMD_LOGICOPS_COLORFILL 1088
#define SVGA_3D_CMD_LOGICOPS_ALPHABLEND 1089
#define SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND 1090
#define SVGA_3D_CMD_SET_OTABLE_BASE 1091
#define SVGA_3D_CMD_READBACK_OTABLE 1092
#define SVGA_3D_CMD_DEFINE_GB_MOB 1093
#define SVGA_3D_CMD_DESTROY_GB_MOB 1094
#define SVGA_3D_CMD_REDEFINE_GB_MOB 1095
#define SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING 1096
#define SVGA_3D_CMD_DEFINE_GB_SURFACE 1097
#define SVGA_3D_CMD_DESTROY_GB_SURFACE 1098
#define SVGA_3D_CMD_BIND_GB_SURFACE 1099
#define SVGA_3D_CMD_COND_BIND_GB_SURFACE 1100
#define SVGA_3D_CMD_UPDATE_GB_IMAGE 1101
#define SVGA_3D_CMD_UPDATE_GB_SURFACE 1102
#define SVGA_3D_CMD_READBACK_GB_IMAGE 1103
#define SVGA_3D_CMD_READBACK_GB_SURFACE 1104
#define SVGA_3D_CMD_INVALIDATE_GB_IMAGE 1105
#define SVGA_3D_CMD_INVALIDATE_GB_SURFACE 1106
#define SVGA_3D_CMD_DEFINE_GB_CONTEXT 1107
#define SVGA_3D_CMD_DESTROY_GB_CONTEXT 1108
#define SVGA_3D_CMD_BIND_GB_CONTEXT 1109
#define SVGA_3D_CMD_READBACK_GB_CONTEXT 1110
#define SVGA_3D_CMD_INVALIDATE_GB_CONTEXT 1111
#define SVGA_3D_CMD_DEFINE_GB_SHADER 1112
#define SVGA_3D_CMD_DESTROY_GB_SHADER 1113
#define SVGA_3D_CMD_BIND_GB_SHADER 1114
#define SVGA_3D_CMD_BIND_SHADERCONSTS 1115
#define SVGA_3D_CMD_BEGIN_GB_QUERY 1116
#define SVGA_3D_CMD_END_GB_QUERY 1117
#define SVGA_3D_CMD_WAIT_FOR_GB_QUERY 1118
#define SVGA_3D_CMD_NOP 1119
#define SVGA_3D_CMD_ENABLE_GART 1120
#define SVGA_3D_CMD_DISABLE_GART 1121
#define SVGA_3D_CMD_MAP_MOB_INTO_GART 1122
#define SVGA_3D_CMD_UNMAP_GART_RANGE 1123
#define SVGA_3D_CMD_DEFINE_GB_SCREENTARGET 1124
#define SVGA_3D_CMD_DESTROY_GB_SCREENTARGET 1125
#define SVGA_3D_CMD_BIND_GB_SCREENTARGET 1126
#define SVGA_3D_CMD_UPDATE_GB_SCREENTARGET 1127
#define SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL 1128
#define SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL 1129
#define SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE 1130
#define SVGA_3D_CMD_GB_SCREEN_DMA 1131
#define SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH 1132
#define SVGA_3D_CMD_GB_MOB_FENCE 1133
#define SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 1134
#define SVGA_3D_CMD_DEFINE_GB_MOB64 1135
#define SVGA_3D_CMD_REDEFINE_GB_MOB64 1136
#define SVGA_3D_CMD_NOP_ERROR 1137
#define SVGA_3D_CMD_RESERVED1 1138
#define SVGA_3D_CMD_RESERVED2 1139
#define SVGA_3D_CMD_RESERVED3 1140
#define SVGA_3D_CMD_RESERVED4 1141
#define SVGA_3D_CMD_RESERVED5 1142
#define SVGA_3D_CMD_MAX 1203
#define SVGA_3D_CMD_FUTURE_MAX 3000
/*
* FIFO command format definitions:
*/
/*
* The data size header following cmdNum for every 3d command
*/
typedef
#include "vmware_pack_begin.h"
struct {
uint32 id;
uint32 size;
}
#include "vmware_pack_end.h"
SVGA3dCmdHeader;
typedef enum {
SVGA3D_SURFACE_CUBEMAP = (1 << 0),
/*
* HINT flags are not enforced by the device but are useful for
* performance.
*/
SVGA3D_SURFACE_HINT_STATIC = (1 << 1),
SVGA3D_SURFACE_HINT_DYNAMIC = (1 << 2),
SVGA3D_SURFACE_HINT_INDEXBUFFER = (1 << 3),
SVGA3D_SURFACE_HINT_VERTEXBUFFER = (1 << 4),
SVGA3D_SURFACE_HINT_TEXTURE = (1 << 5),
SVGA3D_SURFACE_HINT_RENDERTARGET = (1 << 6),
SVGA3D_SURFACE_HINT_DEPTHSTENCIL = (1 << 7),
SVGA3D_SURFACE_HINT_WRITEONLY = (1 << 8),
SVGA3D_SURFACE_MASKABLE_ANTIALIAS = (1 << 9),
SVGA3D_SURFACE_AUTOGENMIPMAPS = (1 << 10),
SVGA3D_SURFACE_DECODE_RENDERTARGET = (1 << 11),
/*
* Is this surface using a base-level pitch for it's mob backing?
*
* This flag is not intended to be set by guest-drivers, but is instead
* set by the device when the surface is bound to a mob with a specified
* pitch.
*/
SVGA3D_SURFACE_MOB_PITCH = (1 << 12),
SVGA3D_SURFACE_INACTIVE = (1 << 13),
SVGA3D_SURFACE_HINT_RT_LOCKABLE = (1 << 14),
SVGA3D_SURFACE_VOLUME = (1 << 15),
/*
* Required to be set on a surface to bind it to a screen target.
*/
SVGA3D_SURFACE_SCREENTARGET = (1 << 16),
SVGA3D_SURFACE_RESERVED1 = (1 << 17),
SVGA3D_SURFACE_1D = (1 << 18),
SVGA3D_SURFACE_ARRAY = (1 << 19),
} SVGA3dSurfaceFlags;
#define SVGA3D_SURFACE_HB_DISALLOWED_MASK (SVGA3D_SURFACE_SCREENTARGET | \
SVGA3D_SURFACE_MOB_PITCH | \
SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
SVGA3D_SURFACE_BIND_STREAM_OUTPUT)
typedef
#include "vmware_pack_begin.h"
struct {
uint32 numMipLevels;
}
#include "vmware_pack_end.h"
SVGA3dSurfaceFace;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 sid;
SVGA3dSurfaceFlags surfaceFlags;
SVGA3dSurfaceFormat format;
/*
* If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
* structures must have the same value of numMipLevels field.
* Otherwise, all but the first SVGA3dSurfaceFace structures must have the
* numMipLevels set to 0.
*/
SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];
/*
* Followed by an SVGA3dSize structure for each mip level in each face.
*
* A note on surface sizes: Sizes are always specified in pixels,
* even if the true surface size is not a multiple of the minimum
* block size of the surface's format. For example, a 3x3x1 DXT1
* compressed texture would actually be stored as a 4x4x1 image in
* memory.
*/
}
#include "vmware_pack_end.h"
SVGA3dCmdDefineSurface; /* SVGA_3D_CMD_SURFACE_DEFINE */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 sid;
SVGA3dSurfaceFlags surfaceFlags;
SVGA3dSurfaceFormat format;
/*
* If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
* structures must have the same value of numMipLevels field.
* Otherwise, all but the first SVGA3dSurfaceFace structures must have the
* numMipLevels set to 0.
*/
SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];
uint32 multisampleCount;
SVGA3dTextureFilter autogenFilter;
/*
* Followed by an SVGA3dSize structure for each mip level in each face.
*
* A note on surface sizes: Sizes are always specified in pixels,
* even if the true surface size is not a multiple of the minimum
* block size of the surface's format. For example, a 3x3x1 DXT1
* compressed texture would actually be stored as a 4x4x1 image in
* memory.
*/
}
#include "vmware_pack_end.h"
SVGA3dCmdDefineSurface_v2; /* SVGA_3D_CMD_SURFACE_DEFINE_V2 */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 sid;
}
#include "vmware_pack_end.h"
SVGA3dCmdDestroySurface; /* SVGA_3D_CMD_SURFACE_DESTROY */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
}
#include "vmware_pack_end.h"
SVGA3dCmdDefineContext; /* SVGA_3D_CMD_CONTEXT_DEFINE */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
}
#include "vmware_pack_end.h"
SVGA3dCmdDestroyContext; /* SVGA_3D_CMD_CONTEXT_DESTROY */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
SVGA3dClearFlag clearFlag;
uint32 color;
float depth;
uint32 stencil;
/* Followed by variable number of SVGA3dRect structures */
}
#include "vmware_pack_end.h"
SVGA3dCmdClear; /* SVGA_3D_CMD_CLEAR */
typedef
#include "vmware_pack_begin.h"
struct {
SVGA3dLightType type;
SVGA3dBool inWorldSpace;
float diffuse[4];
float specular[4];
float ambient[4];
float position[4];
float direction[4];
float range;
float falloff;
float attenuation0;
float attenuation1;
float attenuation2;
float theta;
float phi;
}
#include "vmware_pack_end.h"
SVGA3dLightData;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 sid;
/* Followed by variable number of SVGA3dCopyRect structures */
}
#include "vmware_pack_end.h"
SVGA3dCmdPresent; /* SVGA_3D_CMD_PRESENT */
typedef
#include "vmware_pack_begin.h"
struct {
SVGA3dRenderStateName state;
union {
uint32 uintValue;
float floatValue;
};
}
#include "vmware_pack_end.h"
SVGA3dRenderState;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
/* Followed by variable number of SVGA3dRenderState structures */
}
#include "vmware_pack_end.h"
SVGA3dCmdSetRenderState; /* SVGA_3D_CMD_SETRENDERSTATE */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
SVGA3dRenderTargetType type;
SVGA3dSurfaceImageId target;
}
#include "vmware_pack_end.h"
SVGA3dCmdSetRenderTarget; /* SVGA_3D_CMD_SETRENDERTARGET */
typedef
#include "vmware_pack_begin.h"
struct {
SVGA3dSurfaceImageId src;
SVGA3dSurfaceImageId dest;
/* Followed by variable number of SVGA3dCopyBox structures */
}
#include "vmware_pack_end.h"
SVGA3dCmdSurfaceCopy; /* SVGA_3D_CMD_SURFACE_COPY */
typedef
#include "vmware_pack_begin.h"
struct {
SVGA3dSurfaceImageId src;
SVGA3dSurfaceImageId dest;
SVGA3dBox boxSrc;
SVGA3dBox boxDest;
SVGA3dStretchBltMode mode;
}
#include "vmware_pack_end.h"
SVGA3dCmdSurfaceStretchBlt; /* SVGA_3D_CMD_SURFACE_STRETCHBLT */
typedef
#include "vmware_pack_begin.h"
struct {
/*
* If the discard flag is present in a surface DMA operation, the host may
* discard the contents of the current mipmap level and face of the target
* surface before applying the surface DMA contents.
*/
uint32 discard : 1;
/*
* If the unsynchronized flag is present, the host may perform this upload
* without syncing to pending reads on this surface.
*/
uint32 unsynchronized : 1;
/*
* Guests *MUST* set the reserved bits to 0 before submitting the command
* suffix as future flags may occupy these bits.
*/
uint32 reserved : 30;
}
#include "vmware_pack_end.h"
SVGA3dSurfaceDMAFlags;
typedef
#include "vmware_pack_begin.h"
struct {
SVGAGuestImage guest;
SVGA3dSurfaceImageId host;
SVGA3dTransferType transfer;
/*
* Followed by variable number of SVGA3dCopyBox structures. For consistency
* in all clipping logic and coordinate translation, we define the
* "source" in each copyBox as the guest image and the
* "destination" as the host image, regardless of transfer
* direction.
*
* For efficiency, the SVGA3D device is free to copy more data than
* specified. For example, it may round copy boxes outwards such
* that they lie on particular alignment boundaries.
*/
}
#include "vmware_pack_end.h"
SVGA3dCmdSurfaceDMA; /* SVGA_3D_CMD_SURFACE_DMA */
/*
* SVGA3dCmdSurfaceDMASuffix --
*
* This is a command suffix that will appear after a SurfaceDMA command in
* the FIFO. It contains some extra information that hosts may use to
* optimize performance or protect the guest. This suffix exists to preserve
* backwards compatibility while also allowing for new functionality to be
* implemented.
*/
typedef
#include "vmware_pack_begin.h"
struct {
uint32 suffixSize;
/*
* The maximum offset is used to determine the maximum offset from the
* guestPtr base address that will be accessed or written to during this
* surfaceDMA. If the suffix is supported, the host will respect this
* boundary while performing surface DMAs.
*
* Defaults to MAX_UINT32
*/
uint32 maximumOffset;
/*
* A set of flags that describes optimizations that the host may perform
* while performing this surface DMA operation. The guest should never rely
* on behaviour that is different when these flags are set for correctness.
*
* Defaults to 0
*/
SVGA3dSurfaceDMAFlags flags;
}
#include "vmware_pack_end.h"
SVGA3dCmdSurfaceDMASuffix;
/*
* SVGA_3D_CMD_DRAW_PRIMITIVES --
*
* This command is the SVGA3D device's generic drawing entry point.
* It can draw multiple ranges of primitives, optionally using an
* index buffer, using an arbitrary collection of vertex buffers.
*
* Each SVGA3dVertexDecl defines a distinct vertex array to bind
* during this draw call. The declarations specify which surface
* the vertex data lives in, what that vertex data is used for,
* and how to interpret it.
*
* Each SVGA3dPrimitiveRange defines a collection of primitives
* to render using the same vertex arrays. An index buffer is
* optional.
*/
typedef
#include "vmware_pack_begin.h"
struct {
/*
* A range hint is an optional specification for the range of indices
* in an SVGA3dArray that will be used. If 'last' is zero, it is assumed
* that the entire array will be used.
*
* These are only hints. The SVGA3D device may use them for
* performance optimization if possible, but it's also allowed to
* ignore these values.
*/
uint32 first;
uint32 last;
}
#include "vmware_pack_end.h"
SVGA3dArrayRangeHint;
typedef
#include "vmware_pack_begin.h"
struct {
/*
* Define the origin and shape of a vertex or index array. Both
* 'offset' and 'stride' are in bytes. The provided surface will be
* reinterpreted as a flat array of bytes in the same format used
* by surface DMA operations. To avoid unnecessary conversions, the
* surface should be created with the SVGA3D_BUFFER format.
*
* Index 0 in the array starts 'offset' bytes into the surface.
* Index 1 begins at byte 'offset + stride', etc. Array indices may
* not be negative.
*/
uint32 surfaceId;
uint32 offset;
uint32 stride;
}
#include "vmware_pack_end.h"
SVGA3dArray;
typedef
#include "vmware_pack_begin.h"
struct {
/*
* Describe a vertex array's data type, and define how it is to be
* used by the fixed function pipeline or the vertex shader. It
* isn't useful to have two VertexDecls with the same
* VertexArrayIdentity in one draw call.
*/
SVGA3dDeclType type;
SVGA3dDeclMethod method;
SVGA3dDeclUsage usage;
uint32 usageIndex;
}
#include "vmware_pack_end.h"
SVGA3dVertexArrayIdentity;
typedef
#include "vmware_pack_begin.h"
struct SVGA3dVertexDecl {
SVGA3dVertexArrayIdentity identity;
SVGA3dArray array;
SVGA3dArrayRangeHint rangeHint;
}
#include "vmware_pack_end.h"
SVGA3dVertexDecl;
typedef
#include "vmware_pack_begin.h"
struct SVGA3dPrimitiveRange {
/*
* Define a group of primitives to render, from sequential indices.
*
* The value of 'primitiveType' and 'primitiveCount' imply the
* total number of vertices that will be rendered.
*/
SVGA3dPrimitiveType primType;
uint32 primitiveCount;
/*
* Optional index buffer. If indexArray.surfaceId is
* SVGA3D_INVALID_ID, we render without an index buffer. Rendering
* without an index buffer is identical to rendering with an index
* buffer containing the sequence [0, 1, 2, 3, ...].
*
* If an index buffer is in use, indexWidth specifies the width in
* bytes of each index value. It must be less than or equal to
* indexArray.stride.
*
* (Currently, the SVGA3D device requires index buffers to be tightly
* packed. In other words, indexWidth == indexArray.stride)
*/
SVGA3dArray indexArray;
uint32 indexWidth;
/*
* Optional index bias. This number is added to all indices from
* indexArray before they are used as vertex array indices. This
* can be used in multiple ways:
*
* - When not using an indexArray, this bias can be used to
* specify where in the vertex arrays to begin rendering.
*
* - A positive number here is equivalent to increasing the
* offset in each vertex array.
*
* - A negative number can be used to render using a small
* vertex array and an index buffer that contains large
* values. This may be used by some applications that
* crop a vertex buffer without modifying their index
* buffer.
*
* Note that rendering with a negative bias value may be slower and
* use more memory than rendering with a positive or zero bias.
*/
int32 indexBias;
}
#include "vmware_pack_end.h"
SVGA3dPrimitiveRange;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
uint32 numVertexDecls;
uint32 numRanges;
/*
* There are two variable size arrays after the
* SVGA3dCmdDrawPrimitives structure. In order,
* they are:
*
* 1. SVGA3dVertexDecl, quantity 'numVertexDecls', but no more than
* SVGA3D_MAX_VERTEX_ARRAYS;
* 2. SVGA3dPrimitiveRange, quantity 'numRanges', but no more than
* SVGA3D_MAX_DRAW_PRIMITIVE_RANGES;
* 3. Optionally, SVGA3dVertexDivisor, quantity 'numVertexDecls' (contains
* the frequency divisor for the corresponding vertex decl).
*/
}
#include "vmware_pack_end.h"
SVGA3dCmdDrawPrimitives; /* SVGA_3D_CMD_DRAWPRIMITIVES */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 stage;
SVGA3dTextureStateName name;
union {
uint32 value;
float floatValue;
};
}
#include "vmware_pack_end.h"
SVGA3dTextureState;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
/* Followed by variable number of SVGA3dTextureState structures */
}
#include "vmware_pack_end.h"
SVGA3dCmdSetTextureState; /* SVGA_3D_CMD_SETTEXTURESTATE */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
SVGA3dTransformType type;
float matrix[16];
}
#include "vmware_pack_end.h"
SVGA3dCmdSetTransform; /* SVGA_3D_CMD_SETTRANSFORM */
typedef
#include "vmware_pack_begin.h"
struct {
float min;
float max;
}
#include "vmware_pack_end.h"
SVGA3dZRange;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
SVGA3dZRange zRange;
}
#include "vmware_pack_end.h"
SVGA3dCmdSetZRange; /* SVGA_3D_CMD_SETZRANGE */
typedef
#include "vmware_pack_begin.h"
struct {
float diffuse[4];
float ambient[4];
float specular[4];
float emissive[4];
float shininess;
}
#include "vmware_pack_end.h"
SVGA3dMaterial;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
SVGA3dFace face;
SVGA3dMaterial material;
}
#include "vmware_pack_end.h"
SVGA3dCmdSetMaterial; /* SVGA_3D_CMD_SETMATERIAL */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
uint32 index;
SVGA3dLightData data;
}
#include "vmware_pack_end.h"
SVGA3dCmdSetLightData; /* SVGA_3D_CMD_SETLIGHTDATA */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
uint32 index;
uint32 enabled;
}
#include "vmware_pack_end.h"
SVGA3dCmdSetLightEnabled; /* SVGA_3D_CMD_SETLIGHTENABLED */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
SVGA3dRect rect;
}
#include "vmware_pack_end.h"
SVGA3dCmdSetViewport; /* SVGA_3D_CMD_SETVIEWPORT */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
SVGA3dRect rect;
}
#include "vmware_pack_end.h"
SVGA3dCmdSetScissorRect; /* SVGA_3D_CMD_SETSCISSORRECT */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
uint32 index;
float plane[4];
}
#include "vmware_pack_end.h"
SVGA3dCmdSetClipPlane; /* SVGA_3D_CMD_SETCLIPPLANE */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
uint32 shid;
SVGA3dShaderType type;
/* Followed by variable number of DWORDs for shader bycode */
}
#include "vmware_pack_end.h"
SVGA3dCmdDefineShader; /* SVGA_3D_CMD_SHADER_DEFINE */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
uint32 shid;
SVGA3dShaderType type;
}
#include "vmware_pack_end.h"
SVGA3dCmdDestroyShader; /* SVGA_3D_CMD_SHADER_DESTROY */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
uint32 reg; /* register number */
SVGA3dShaderType type;
SVGA3dShaderConstType ctype;
uint32 values[4];
/*
* Followed by a variable number of additional values.
*/
}
#include "vmware_pack_end.h"
SVGA3dCmdSetShaderConst; /* SVGA_3D_CMD_SET_SHADER_CONST */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
SVGA3dShaderType type;
uint32 shid;
}
#include "vmware_pack_end.h"
SVGA3dCmdSetShader; /* SVGA_3D_CMD_SET_SHADER */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
SVGA3dQueryType type;
}
#include "vmware_pack_end.h"
SVGA3dCmdBeginQuery; /* SVGA_3D_CMD_BEGIN_QUERY */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
SVGA3dQueryType type;
SVGAGuestPtr guestResult; /* Points to an SVGA3dQueryResult structure */
}
#include "vmware_pack_end.h"
SVGA3dCmdEndQuery; /* SVGA_3D_CMD_END_QUERY */
/*
* SVGA3D_CMD_WAIT_FOR_QUERY --
*
* Will read the SVGA3dQueryResult structure pointed to by guestResult,
* and if the state member is set to anything else than
* SVGA3D_QUERYSTATE_PENDING, this command will always be a no-op.
*
* Otherwise, in addition to the query explicitly waited for,
* All queries with the same type and issued with the same cid, for which
* an SVGA_3D_CMD_END_QUERY command has previously been sent, will
* be finished after execution of this command.
*
* A query will be identified by the gmrId and offset of the guestResult
* member. If the device can't find an SVGA_3D_CMD_END_QUERY that has
* been sent previously with an indentical gmrId and offset, it will
* effectively end all queries with an identical type issued with the
* same cid, and the SVGA3dQueryResult structure pointed to by
* guestResult will not be written to. This property can be used to
* implement a query barrier for a given cid and query type.
*/
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid; /* Same parameters passed to END_QUERY */
SVGA3dQueryType type;
SVGAGuestPtr guestResult;
}
#include "vmware_pack_end.h"
SVGA3dCmdWaitForQuery; /* SVGA_3D_CMD_WAIT_FOR_QUERY */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 totalSize; /* Set by guest before query is ended. */
SVGA3dQueryState state; /* Set by host or guest. See SVGA3dQueryState. */
union { /* Set by host on exit from PENDING state */
uint32 result32;
uint32 queryCookie; /* May be used to identify which QueryGetData this
result corresponds to. */
};
}
#include "vmware_pack_end.h"
SVGA3dQueryResult;
/*
* SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN --
*
* This is a blit from an SVGA3D surface to a Screen Object.
* This blit must be directed at a specific screen.
*
* The blit copies from a rectangular region of an SVGA3D surface
* image to a rectangular region of a screen.
*
* This command takes an optional variable-length list of clipping
* rectangles after the body of the command. If no rectangles are
* specified, there is no clipping region. The entire destRect is
* drawn to. If one or more rectangles are included, they describe
* a clipping region. The clip rectangle coordinates are measured
* relative to the top-left corner of destRect.
*
* The srcImage must be from mip=0 face=0.
*
* This supports scaling if the src and dest are of different sizes.
*
* Availability:
* SVGA_FIFO_CAP_SCREEN_OBJECT
*/
typedef
#include "vmware_pack_begin.h"
struct {
SVGA3dSurfaceImageId srcImage;
SVGASignedRect srcRect;
uint32 destScreenId; /* Screen Object ID */
SVGASignedRect destRect;
/* Clipping: zero or more SVGASignedRects follow */
}
#include "vmware_pack_end.h"
SVGA3dCmdBlitSurfaceToScreen; /* SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 sid;
SVGA3dTextureFilter filter;
}
#include "vmware_pack_end.h"
SVGA3dCmdGenerateMipmaps; /* SVGA_3D_CMD_GENERATE_MIPMAPS */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 sid;
}
#include "vmware_pack_end.h"
SVGA3dCmdActivateSurface; /* SVGA_3D_CMD_ACTIVATE_SURFACE */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 sid;
}
#include "vmware_pack_end.h"
SVGA3dCmdDeactivateSurface; /* SVGA_3D_CMD_DEACTIVATE_SURFACE */
/*
* Screen DMA command
*
* Available with SVGA_FIFO_CAP_SCREEN_OBJECT_2. The SVGA_CAP_3D device
* cap bit is not required.
*
* - refBuffer and destBuffer are 32bit BGRX; refBuffer and destBuffer could
* be different, but it is required that guest makes sure refBuffer has
* exactly the same contents that were written to when last time screen DMA
* command is received by host.
*
* - changemap is generated by lib/blit, and it has the changes from last
* received screen DMA or more.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdScreenDMA {
uint32 screenId;
SVGAGuestImage refBuffer;
SVGAGuestImage destBuffer;
SVGAGuestImage changeMap;
}
#include "vmware_pack_end.h"
SVGA3dCmdScreenDMA; /* SVGA_3D_CMD_SCREEN_DMA */
/*
* Set Unity Surface Cookie
*
* Associates the supplied cookie with the surface id for use with
* Unity. This cookie is a hint from guest to host, there is no way
* for the guest to readback the cookie and the host is free to drop
* the cookie association at will. The default value for the cookie
* on all surfaces is 0.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdSetUnitySurfaceCookie {
uint32 sid;
uint64 cookie;
}
#include "vmware_pack_end.h"
SVGA3dCmdSetUnitySurfaceCookie; /* SVGA_3D_CMD_SET_UNITY_SURFACE_COOKIE */
/*
* Open a context-specific surface in a non-context-specific manner.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdOpenContextSurface {
uint32 sid;
}
#include "vmware_pack_end.h"
SVGA3dCmdOpenContextSurface; /* SVGA_3D_CMD_OPEN_CONTEXT_SURFACE */
/*
* Logic ops
*/
#define SVGA3D_LOTRANSBLT_HONORALPHA (0x01)
#define SVGA3D_LOSTRETCHBLT_MIRRORX (0x01)
#define SVGA3D_LOSTRETCHBLT_MIRRORY (0x02)
#define SVGA3D_LOALPHABLEND_SRCHASALPHA (0x01)
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdLogicOpsBitBlt {
/*
* All LogicOps surfaces are one-level
* surfaces so mipmap & face should always
* be zero.
*/
SVGA3dSurfaceImageId src;
SVGA3dSurfaceImageId dst;
SVGA3dLogicOp logicOp;
/* Followed by variable number of SVGA3dCopyBox structures */
}
#include "vmware_pack_end.h"
SVGA3dCmdLogicOpsBitBlt; /* SVGA_3D_CMD_LOGICOPS_BITBLT */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdLogicOpsTransBlt {
/*
* All LogicOps surfaces are one-level
* surfaces so mipmap & face should always
* be zero.
*/
SVGA3dSurfaceImageId src;
SVGA3dSurfaceImageId dst;
uint32 color;
uint32 flags;
SVGA3dBox srcBox;
SVGA3dBox dstBox;
}
#include "vmware_pack_end.h"
SVGA3dCmdLogicOpsTransBlt; /* SVGA_3D_CMD_LOGICOPS_TRANSBLT */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdLogicOpsStretchBlt {
/*
* All LogicOps surfaces are one-level
* surfaces so mipmap & face should always
* be zero.
*/
SVGA3dSurfaceImageId src;
SVGA3dSurfaceImageId dst;
uint16 mode;
uint16 flags;
SVGA3dBox srcBox;
SVGA3dBox dstBox;
}
#include "vmware_pack_end.h"
SVGA3dCmdLogicOpsStretchBlt; /* SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdLogicOpsColorFill {
/*
* All LogicOps surfaces are one-level
* surfaces so mipmap & face should always
* be zero.
*/
SVGA3dSurfaceImageId dst;
uint32 color;
SVGA3dLogicOp logicOp;
/* Followed by variable number of SVGA3dRect structures. */
}
#include "vmware_pack_end.h"
SVGA3dCmdLogicOpsColorFill; /* SVGA_3D_CMD_LOGICOPS_COLORFILL */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdLogicOpsAlphaBlend {
/*
* All LogicOps surfaces are one-level
* surfaces so mipmap & face should always
* be zero.
*/
SVGA3dSurfaceImageId src;
SVGA3dSurfaceImageId dst;
uint32 alphaVal;
uint32 flags;
SVGA3dBox srcBox;
SVGA3dBox dstBox;
}
#include "vmware_pack_end.h"
SVGA3dCmdLogicOpsAlphaBlend; /* SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
#define SVGA3D_CLEARTYPE_INVALID_GAMMA_INDEX 0xFFFFFFFF
#define SVGA3D_CLEARTYPE_GAMMA_WIDTH 512
#define SVGA3D_CLEARTYPE_GAMMA_HEIGHT 16
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdLogicOpsClearTypeBlend {
/*
* All LogicOps surfaces are one-level
* surfaces so mipmap & face should always
* be zero.
*/
SVGA3dSurfaceImageId tmp;
SVGA3dSurfaceImageId dst;
SVGA3dSurfaceImageId gammaSurf;
SVGA3dSurfaceImageId alphaSurf;
uint32 gamma;
uint32 color;
uint32 color2;
int alphaOffsetX;
int alphaOffsetY;
/* Followed by variable number of SVGA3dBox structures */
}
#include "vmware_pack_end.h"
SVGA3dCmdLogicOpsClearTypeBlend; /* SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
/*
* Guest-backed objects definitions.
*/
#define SVGA_STFLAG_PRIMARY (1 << 0)
typedef uint32 SVGAScreenTargetFlags;
typedef
#include "vmware_pack_begin.h"
struct {
float value[4];
}
#include "vmware_pack_end.h"
SVGA3dShaderConstFloat;
typedef
#include "vmware_pack_begin.h"
struct {
int32 value[4];
}
#include "vmware_pack_end.h"
SVGA3dShaderConstInt;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 value;
}
#include "vmware_pack_end.h"
SVGA3dShaderConstBool;
/*
* Define a guest-backed surface.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDefineGBSurface {
uint32 sid;
SVGA3dSurfaceFlags surfaceFlags;
SVGA3dSurfaceFormat format;
uint32 numMipLevels;
uint32 multisampleCount;
SVGA3dTextureFilter autogenFilter;
SVGA3dSize size;
}
#include "vmware_pack_end.h"
SVGA3dCmdDefineGBSurface; /* SVGA_3D_CMD_DEFINE_GB_SURFACE */
/*
* Destroy a guest-backed surface.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDestroyGBSurface {
uint32 sid;
}
#include "vmware_pack_end.h"
SVGA3dCmdDestroyGBSurface; /* SVGA_3D_CMD_DESTROY_GB_SURFACE */
/*
* Bind a guest-backed surface to a mob.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdBindGBSurface {
uint32 sid;
SVGAMobId mobid;
}
#include "vmware_pack_end.h"
SVGA3dCmdBindGBSurface; /* SVGA_3D_CMD_BIND_GB_SURFACE */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdBindGBSurfaceWithPitch {
uint32 sid;
SVGAMobId mobid;
uint32 baseLevelPitch;
}
#include "vmware_pack_end.h"
SVGA3dCmdBindGBSurfaceWithPitch; /* SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH */
/*
* Conditionally bind a mob to a guest-backed surface if testMobid
* matches the currently bound mob. Optionally issue a
* readback/update on the surface while it is still bound to the old
* mobid if the mobid is changed by this command.
*/
#define SVGA3D_COND_BIND_GB_SURFACE_FLAG_READBACK (1 << 0)
#define SVGA3D_COND_BIND_GB_SURFACE_FLAG_UPDATE (1 << 1)
typedef
#include "vmware_pack_begin.h"
struct{
uint32 sid;
SVGAMobId testMobid;
SVGAMobId mobid;
uint32 flags;
}
#include "vmware_pack_end.h"
SVGA3dCmdCondBindGBSurface; /* SVGA_3D_CMD_COND_BIND_GB_SURFACE */
/*
* Update an image in a guest-backed surface.
* (Inform the device that the guest-contents have been updated.)
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdUpdateGBImage {
SVGA3dSurfaceImageId image;
SVGA3dBox box;
}
#include "vmware_pack_end.h"
SVGA3dCmdUpdateGBImage; /* SVGA_3D_CMD_UPDATE_GB_IMAGE */
/*
* Update an entire guest-backed surface.
* (Inform the device that the guest-contents have been updated.)
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdUpdateGBSurface {
uint32 sid;
}
#include "vmware_pack_end.h"
SVGA3dCmdUpdateGBSurface; /* SVGA_3D_CMD_UPDATE_GB_SURFACE */
/*
* Readback an image in a guest-backed surface.
* (Request the device to flush the dirty contents into the guest.)
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdReadbackGBImage {
SVGA3dSurfaceImageId image;
}
#include "vmware_pack_end.h"
SVGA3dCmdReadbackGBImage; /* SVGA_3D_CMD_READBACK_GB_IMAGE */
/*
* Readback an entire guest-backed surface.
* (Request the device to flush the dirty contents into the guest.)
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdReadbackGBSurface {
uint32 sid;
}
#include "vmware_pack_end.h"
SVGA3dCmdReadbackGBSurface; /* SVGA_3D_CMD_READBACK_GB_SURFACE */
/*
* Readback a sub rect of an image in a guest-backed surface. After
* issuing this command the driver is required to issue an update call
* of the same region before issuing any other commands that reference
* this surface or rendering is not guaranteed.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdReadbackGBImagePartial {
SVGA3dSurfaceImageId image;
SVGA3dBox box;
uint32 invertBox;
}
#include "vmware_pack_end.h"
SVGA3dCmdReadbackGBImagePartial; /* SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL */
/*
* Invalidate an image in a guest-backed surface.
* (Notify the device that the contents can be lost.)
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdInvalidateGBImage {
SVGA3dSurfaceImageId image;
}
#include "vmware_pack_end.h"
SVGA3dCmdInvalidateGBImage; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE */
/*
* Invalidate an entire guest-backed surface.
* (Notify the device that the contents if all images can be lost.)
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdInvalidateGBSurface {
uint32 sid;
}
#include "vmware_pack_end.h"
SVGA3dCmdInvalidateGBSurface; /* SVGA_3D_CMD_INVALIDATE_GB_SURFACE */
/*
* Invalidate a sub rect of an image in a guest-backed surface. After
* issuing this command the driver is required to issue an update call
* of the same region before issuing any other commands that reference
* this surface or rendering is not guaranteed.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdInvalidateGBImagePartial {
SVGA3dSurfaceImageId image;
SVGA3dBox box;
uint32 invertBox;
}
#include "vmware_pack_end.h"
SVGA3dCmdInvalidateGBImagePartial; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL */
/*
* Define a guest-backed context.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDefineGBContext {
uint32 cid;
}
#include "vmware_pack_end.h"
SVGA3dCmdDefineGBContext; /* SVGA_3D_CMD_DEFINE_GB_CONTEXT */
/*
* Destroy a guest-backed context.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDestroyGBContext {
uint32 cid;
}
#include "vmware_pack_end.h"
SVGA3dCmdDestroyGBContext; /* SVGA_3D_CMD_DESTROY_GB_CONTEXT */
/*
* Bind a guest-backed context.
*
* validContents should be set to 0 for new contexts,
* and 1 if this is an old context which is getting paged
* back on to the device.
*
* For new contexts, it is recommended that the driver
* issue commands to initialize all interesting state
* prior to rendering.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdBindGBContext {
uint32 cid;
SVGAMobId mobid;
uint32 validContents;
}
#include "vmware_pack_end.h"
SVGA3dCmdBindGBContext; /* SVGA_3D_CMD_BIND_GB_CONTEXT */
/*
* Readback a guest-backed context.
* (Request that the device flush the contents back into guest memory.)
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdReadbackGBContext {
uint32 cid;
}
#include "vmware_pack_end.h"
SVGA3dCmdReadbackGBContext; /* SVGA_3D_CMD_READBACK_GB_CONTEXT */
/*
* Invalidate a guest-backed context.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdInvalidateGBContext {
uint32 cid;
}
#include "vmware_pack_end.h"
SVGA3dCmdInvalidateGBContext; /* SVGA_3D_CMD_INVALIDATE_GB_CONTEXT */
/*
* Define a guest-backed shader.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDefineGBShader {
uint32 shid;
SVGA3dShaderType type;
uint32 sizeInBytes;
}
#include "vmware_pack_end.h"
SVGA3dCmdDefineGBShader; /* SVGA_3D_CMD_DEFINE_GB_SHADER */
/*
* Bind a guest-backed shader.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdBindGBShader {
uint32 shid;
SVGAMobId mobid;
uint32 offsetInBytes;
}
#include "vmware_pack_end.h"
SVGA3dCmdBindGBShader; /* SVGA_3D_CMD_BIND_GB_SHADER */
/*
* Destroy a guest-backed shader.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdDestroyGBShader {
uint32 shid;
}
#include "vmware_pack_end.h"
SVGA3dCmdDestroyGBShader; /* SVGA_3D_CMD_DESTROY_GB_SHADER */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdBindGBShaderConsts {
uint32 cid;
SVGA3dShaderType shaderType;
SVGA3dShaderConstType shaderConstType;
uint32 sid;
}
#include "vmware_pack_end.h"
SVGA3dCmdBindGBShaderConsts; /* SVGA_3D_CMD_BIND_SHADERCONSTS */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
uint32 regStart;
SVGA3dShaderType shaderType;
SVGA3dShaderConstType constType;
/*
* Followed by a variable number of shader constants.
*
* Note that FLOAT and INT constants are 4-dwords in length, while
* BOOL constants are 1-dword in length.
*/
}
#include "vmware_pack_end.h"
SVGA3dCmdSetGBShaderConstInline; /* SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
SVGA3dQueryType type;
}
#include "vmware_pack_end.h"
SVGA3dCmdBeginGBQuery; /* SVGA_3D_CMD_BEGIN_GB_QUERY */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
SVGA3dQueryType type;
SVGAMobId mobid;
uint32 offset;
}
#include "vmware_pack_end.h"
SVGA3dCmdEndGBQuery; /* SVGA_3D_CMD_END_GB_QUERY */
/*
* SVGA_3D_CMD_WAIT_FOR_GB_QUERY --
*
* The semantics of this command are identical to the
* SVGA_3D_CMD_WAIT_FOR_QUERY except that the results are written
* to a Mob instead of a GMR.
*/
typedef
#include "vmware_pack_begin.h"
struct {
uint32 cid;
SVGA3dQueryType type;
SVGAMobId mobid;
uint32 offset;
}
#include "vmware_pack_end.h"
SVGA3dCmdWaitForGBQuery; /* SVGA_3D_CMD_WAIT_FOR_GB_QUERY */
typedef
#include "vmware_pack_begin.h"
struct {
SVGAMobId mobid;
uint32 fbOffset;
uint32 initialized;
}
#include "vmware_pack_end.h"
SVGA3dCmdEnableGart; /* SVGA_3D_CMD_ENABLE_GART */
typedef
#include "vmware_pack_begin.h"
struct {
SVGAMobId mobid;
uint32 gartOffset;
}
#include "vmware_pack_end.h"
SVGA3dCmdMapMobIntoGart; /* SVGA_3D_CMD_MAP_MOB_INTO_GART */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 gartOffset;
uint32 numPages;
}
#include "vmware_pack_end.h"
SVGA3dCmdUnmapGartRange; /* SVGA_3D_CMD_UNMAP_GART_RANGE */
/*
* Screen Targets
*/
typedef
#include "vmware_pack_begin.h"
struct {
uint32 stid;
uint32 width;
uint32 height;
int32 xRoot;
int32 yRoot;
SVGAScreenTargetFlags flags;
/*
* The physical DPI that the guest expects this screen displayed at.
*
* Guests which are not DPI-aware should set this to zero.
*/
uint32 dpi;
}
#include "vmware_pack_end.h"
SVGA3dCmdDefineGBScreenTarget; /* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 stid;
}
#include "vmware_pack_end.h"
SVGA3dCmdDestroyGBScreenTarget; /* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 stid;
SVGA3dSurfaceImageId image;
}
#include "vmware_pack_end.h"
SVGA3dCmdBindGBScreenTarget; /* SVGA_3D_CMD_BIND_GB_SCREENTARGET */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 stid;
SVGA3dRect rect;
}
#include "vmware_pack_end.h"
SVGA3dCmdUpdateGBScreenTarget; /* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCmdGBScreenDMA {
uint32 screenId;
uint32 dead;
SVGAMobId destMobID;
uint32 destPitch;
SVGAMobId changeMapMobID;
}
#include "vmware_pack_end.h"
SVGA3dCmdGBScreenDMA; /* SVGA_3D_CMD_GB_SCREEN_DMA */
typedef
#include "vmware_pack_begin.h"
struct {
uint32 value;
uint32 mobId;
uint32 mobOffset;
}
#include "vmware_pack_end.h"
SVGA3dCmdGBMobFence; /* SVGA_3D_CMD_GB_MOB_FENCE*/
#endif // _SVGA3D_CMD_H_

/contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/svga/include/svga3d_devcaps.h
0,0 → 1,236
/**********************************************************
* Copyright 1998-2014 VMware, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
**********************************************************/
/*
* svga3d_devcaps.h --
*
* SVGA 3d caps definitions
*/
#ifndef _SVGA3D_DEVCAPS_H_
#define _SVGA3D_DEVCAPS_H_
#define INCLUDE_ALLOW_MODULE
#define INCLUDE_ALLOW_USERLEVEL
#define INCLUDE_ALLOW_VMCORE
#include "includeCheck.h"
/*
* 3D Hardware Version
*
* The hardware version is stored in the SVGA_FIFO_3D_HWVERSION fifo
* register. Is set by the host and read by the guest. This lets
* us make new guest drivers which are backwards-compatible with old
* SVGA hardware revisions. It does not let us support old guest
* drivers. Good enough for now.
*
*/
#define SVGA3D_MAKE_HWVERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
#define SVGA3D_MAJOR_HWVERSION(version) ((version) >> 16)
#define SVGA3D_MINOR_HWVERSION(version) ((version) & 0xFF)
typedef enum {
SVGA3D_HWVERSION_WS5_RC1 = SVGA3D_MAKE_HWVERSION(0, 1),
SVGA3D_HWVERSION_WS5_RC2 = SVGA3D_MAKE_HWVERSION(0, 2),
SVGA3D_HWVERSION_WS51_RC1 = SVGA3D_MAKE_HWVERSION(0, 3),
SVGA3D_HWVERSION_WS6_B1 = SVGA3D_MAKE_HWVERSION(1, 1),
SVGA3D_HWVERSION_FUSION_11 = SVGA3D_MAKE_HWVERSION(1, 4),
SVGA3D_HWVERSION_WS65_B1 = SVGA3D_MAKE_HWVERSION(2, 0),
SVGA3D_HWVERSION_WS8_B1 = SVGA3D_MAKE_HWVERSION(2, 1),
SVGA3D_HWVERSION_CURRENT = SVGA3D_HWVERSION_WS8_B1,
} SVGA3dHardwareVersion;
/*
* DevCap indexes.
*/
typedef enum {
SVGA3D_DEVCAP_INVALID = ((uint32)-1),
SVGA3D_DEVCAP_3D = 0,
SVGA3D_DEVCAP_MAX_LIGHTS = 1,
/*
* SVGA3D_DEVCAP_MAX_TEXTURES reflects the maximum number of
* fixed-function texture units available. Each of these units
* work in both FFP and Shader modes, and they support texture
* transforms and texture coordinates. The host may have additional
* texture image units that are only usable with shaders.
*/
SVGA3D_DEVCAP_MAX_TEXTURES = 2,
SVGA3D_DEVCAP_MAX_CLIP_PLANES = 3,
SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = 4,
SVGA3D_DEVCAP_VERTEX_SHADER = 5,
SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = 6,
SVGA3D_DEVCAP_FRAGMENT_SHADER = 7,
SVGA3D_DEVCAP_MAX_RENDER_TARGETS = 8,
SVGA3D_DEVCAP_S23E8_TEXTURES = 9,
SVGA3D_DEVCAP_S10E5_TEXTURES = 10,
SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = 11,
SVGA3D_DEVCAP_D16_BUFFER_FORMAT = 12,
SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = 13,
SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = 14,
SVGA3D_DEVCAP_QUERY_TYPES = 15,
SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = 16,
SVGA3D_DEVCAP_MAX_POINT_SIZE = 17,
SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = 18,
SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = 19,
SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = 20,
SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = 21,
SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = 22,
SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = 23,
SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = 24,
SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = 25,
SVGA3D_DEVCAP_MAX_VERTEX_INDEX = 26,
SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = 27,
SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = 28,
SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = 29,
SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = 30,
SVGA3D_DEVCAP_TEXTURE_OPS = 31,
SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = 32,
SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = 33,
SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = 34,
SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = 35,
SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = 36,
SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = 37,
SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = 38,
SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = 39,
SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = 40,
SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = 41,
SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = 42,
SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = 43,
SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = 44,
SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = 45,
SVGA3D_DEVCAP_SURFACEFMT_DXT1 = 46,
SVGA3D_DEVCAP_SURFACEFMT_DXT2 = 47,
SVGA3D_DEVCAP_SURFACEFMT_DXT3 = 48,
SVGA3D_DEVCAP_SURFACEFMT_DXT4 = 49,
SVGA3D_DEVCAP_SURFACEFMT_DXT5 = 50,
SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = 51,
SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = 52,
SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = 53,
SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = 54,
SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = 55,
SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = 56,
SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = 57,
SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = 58,
SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = 59,
SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = 60,
SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = 61,
/*
* There is a hole in our devcap definitions for
* historical reasons.
*
* Define a constant just for completeness.
*/
SVGA3D_DEVCAP_MISSING62 = 62,
SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = 63,
/*
* Note that MAX_SIMULTANEOUS_RENDER_TARGETS is a maximum count of color
* render targets. This does not include the depth or stencil targets.
*/
SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = 64,
SVGA3D_DEVCAP_SURFACEFMT_V16U16 = 65,
SVGA3D_DEVCAP_SURFACEFMT_G16R16 = 66,
SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = 67,
SVGA3D_DEVCAP_SURFACEFMT_UYVY = 68,
SVGA3D_DEVCAP_SURFACEFMT_YUY2 = 69,
SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = 70,
SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = 71,
SVGA3D_DEVCAP_ALPHATOCOVERAGE = 72,
SVGA3D_DEVCAP_SUPERSAMPLE = 73,
SVGA3D_DEVCAP_AUTOGENMIPMAPS = 74,
SVGA3D_DEVCAP_SURFACEFMT_NV12 = 75,
SVGA3D_DEVCAP_SURFACEFMT_AYUV = 76,
/*
* This is the maximum number of SVGA context IDs that the guest
* can define using SVGA_3D_CMD_CONTEXT_DEFINE.
*/
SVGA3D_DEVCAP_MAX_CONTEXT_IDS = 77,
/*
* This is the maximum number of SVGA surface IDs that the guest
* can define using SVGA_3D_CMD_SURFACE_DEFINE*.
*/
SVGA3D_DEVCAP_MAX_SURFACE_IDS = 78,
SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = 79,
SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = 80,
SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = 81,
SVGA3D_DEVCAP_SURFACEFMT_ATI1 = 82,
SVGA3D_DEVCAP_SURFACEFMT_ATI2 = 83,
/*
* Deprecated.
*/
SVGA3D_DEVCAP_DEAD1 = 84,
/*
* This contains several SVGA_3D_CAPS_VIDEO_DECODE elements
* ored together, one for every type of video decoding supported.
*/
SVGA3D_DEVCAP_VIDEO_DECODE = 85,
/*
* This contains several SVGA_3D_CAPS_VIDEO_PROCESS elements
* ored together, one for every type of video processing supported.
*/
SVGA3D_DEVCAP_VIDEO_PROCESS = 86,
SVGA3D_DEVCAP_LINE_AA = 87, /* boolean */
SVGA3D_DEVCAP_LINE_STIPPLE = 88, /* boolean */
SVGA3D_DEVCAP_MAX_LINE_WIDTH = 89, /* float */
SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH = 90, /* float */
SVGA3D_DEVCAP_SURFACEFMT_YV12 = 91,
/*
* Does the host support the SVGA logic ops commands?
*/
SVGA3D_DEVCAP_LOGICOPS = 92,
/*
* Are TS_CONSTANT, TS_COLOR_KEY, and TS_COLOR_KEY_ENABLE supported?
*/
SVGA3D_DEVCAP_TS_COLOR_KEY = 93, /* boolean */
SVGA3D_DEVCAP_MAX /* This must be the last index. */
} SVGA3dDevCapIndex;
typedef union {
Bool b;
uint32 u;
int32 i;
float f;
} SVGA3dDevCapResult;
#endif // _SVGA3D_DEVCAPS_H_

/contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/svga/include/svga3d_limits.h
0,0 → 1,101
/**********************************************************
* Copyright 2007-2014 VMware, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
**********************************************************/
/*
* svga3d_limits.h --
*
* SVGA 3d hardware limits
*/
#ifndef _SVGA3D_LIMITS_H_
#define _SVGA3D_LIMITS_H_
#define INCLUDE_ALLOW_MODULE
#define INCLUDE_ALLOW_USERLEVEL
#define INCLUDE_ALLOW_VMCORE
#include "includeCheck.h"
#define SVGA3D_NUM_CLIPPLANES 6
#define SVGA3D_MAX_RENDER_TARGETS 8
#define SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS (SVGA3D_MAX_RENDER_TARGETS)
#define SVGA3D_MAX_CONTEXT_IDS 256
#define SVGA3D_MAX_SURFACE_IDS (32 * 1024)
/*
* Maximum ID a shader can be assigned on a given context.
*/
#define SVGA3D_MAX_SHADERIDS 5000
/*
* Maximum number of shaders of a given type that can be defined
* (including all contexts).
*/
#define SVGA3D_MAX_SIMULTANEOUS_SHADERS 20000
#define SVGA3D_NUM_TEXTURE_UNITS 32
#define SVGA3D_NUM_LIGHTS 8
#define SVGA3D_MAX_VIDEODECODERS 8
#define SVGA3D_MAX_VIDEOPROCESSORS 8
#define SVGA3D_MAX_VIDEODECODER_FRAMES 400
/*
* Maximum size in dwords of shader text the SVGA device will allow.
* Currently 8 MB.
*/
#define SVGA3D_MAX_SHADER_MEMORY (8 * 1024 * 1024 / sizeof(uint32))
#define SVGA3D_MAX_CLIP_PLANES 6
/*
* This is the limit to the number of fixed-function texture
* transforms and texture coordinates we can support. It does *not*
* correspond to the number of texture image units (samplers) we
* support!
*/
#define SVGA3D_MAX_TEXTURE_COORDS 8
/*
* Number of faces in a cubemap.
*/
#define SVGA3D_MAX_SURFACE_FACES 6
/*
* Maximum number of array indexes in a GB surface (with DX enabled).
*/
#define SVGA3D_MAX_SURFACE_ARRAYSIZE 512
/*
* The maximum number of vertex arrays we're guaranteed to support in
* SVGA_3D_CMD_DRAWPRIMITIVES.
*/
#define SVGA3D_MAX_VERTEX_ARRAYS 32
/*
* The maximum number of primitive ranges we're guaranteed to support
* in SVGA_3D_CMD_DRAWPRIMITIVES.
*/
#define SVGA3D_MAX_DRAW_PRIMITIVE_RANGES 32
#endif // _SVGA3D_LIMITS_H_

/contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/svga/include/svga3d_reg.h
0,0 → 1,49
/**********************************************************
* Copyright 1998-2014 VMware, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
**********************************************************/
/*
* svga3d_reg.h --
*
* SVGA 3d hardware definitions
*/
#ifndef _SVGA3D_REG_H_
#define _SVGA3D_REG_H_
#define INCLUDE_ALLOW_MODULE
#define INCLUDE_ALLOW_USERLEVEL
#define INCLUDE_ALLOW_VMCORE
#include "includeCheck.h"
#include "svga_reg.h"
#include "svga3d_types.h"
#include "svga3d_limits.h"
#include "svga3d_cmd.h"
#include "svga3d_devcaps.h"
#endif /* _SVGA3D_REG_H_ */

/contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/svga/include/svga3d_shaderdefs.h
0,0 → 1,518
/**********************************************************
* Copyright 2007-2014 VMware, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
**********************************************************/
/*
* svga3d_shaderdefs.h --
*
* SVGA3D byte code format and limit definitions.
*
* The format of the byte code directly corresponds to that defined
* by Microsoft DirectX SDK 9.0c (file d3d9types.h). The format can
* also be extended so that different shader formats can be supported
* for example GLSL, ARB vp/fp, NV/ATI shader formats, etc.
*
*/
#ifndef __SVGA3D_SHADER_DEFS__
#define __SVGA3D_SHADER_DEFS__
/* SVGA3D shader hardware limits. */
#define SVGA3D_INPUTREG_MAX 16
#define SVGA3D_OUTPUTREG_MAX 12
#define SVGA3D_VERTEX_SAMPLERREG_MAX 4
#define SVGA3D_PIXEL_SAMPLERREG_MAX 16
#define SVGA3D_SAMPLERREG_MAX (SVGA3D_PIXEL_SAMPLERREG_MAX+\
SVGA3D_VERTEX_SAMPLERREG_MAX)
#define SVGA3D_TEMPREG_MAX 32
#define SVGA3D_CONSTREG_MAX 256
#define SVGA3D_CONSTINTREG_MAX 16
#define SVGA3D_CONSTBOOLREG_MAX 16
#define SVGA3D_ADDRREG_MAX 1
#define SVGA3D_PREDREG_MAX 1
/* SVGA3D byte code specific limits */
#define SVGA3D_MAX_SRC_REGS 4
#define SVGA3D_MAX_NESTING_LEVEL 32
/* SVGA3D version information. */
#define SVGA3D_VS_TYPE 0xFFFE
#define SVGA3D_PS_TYPE 0xFFFF
typedef struct {
union {
struct {
uint32 minor : 8;
uint32 major : 8;
uint32 type : 16;
};
uint32 value;
};
} SVGA3dShaderVersion;
#define SVGA3D_VS_10 ((SVGA3D_VS_TYPE << 16) | 1 << 8)
#define SVGA3D_VS_11 (SVGA3D_VS_10 | 1)
#define SVGA3D_VS_20 ((SVGA3D_VS_TYPE << 16) | 2 << 8)
#define SVGA3D_VS_21 (SVGA3D_VS_20 | 1)
#define SVGA3D_VS_30 ((SVGA3D_VS_TYPE << 16) | 3 << 8)
#define SVGA3D_PS_10 ((SVGA3D_PS_TYPE << 16) | 1 << 8)
#define SVGA3D_PS_11 (SVGA3D_PS_10 | 1)
#define SVGA3D_PS_12 (SVGA3D_PS_10 | 2)
#define SVGA3D_PS_13 (SVGA3D_PS_10 | 3)
#define SVGA3D_PS_14 (SVGA3D_PS_10 | 4)
#define SVGA3D_PS_20 ((SVGA3D_PS_TYPE << 16) | 2 << 8)
#define SVGA3D_PS_21 (SVGA3D_PS_20 | 1)
#define SVGA3D_PS_30 ((SVGA3D_PS_TYPE << 16) | 3 << 8)
/* The *_ENABLED are for backwards compatibility with old drivers */
typedef enum {
SVGA3DPSVERSION_NONE = 0,
SVGA3DPSVERSION_ENABLED = 1,
SVGA3DPSVERSION_11 = 3,
SVGA3DPSVERSION_12 = 5,
SVGA3DPSVERSION_13 = 7,
SVGA3DPSVERSION_14 = 9,
SVGA3DPSVERSION_20 = 11,
SVGA3DPSVERSION_30 = 13,
SVGA3DPSVERSION_40 = 15,
SVGA3DPSVERSION_MAX
} SVGA3dPixelShaderVersion;
typedef enum {
SVGA3DVSVERSION_NONE = 0,
SVGA3DVSVERSION_ENABLED = 1,
SVGA3DVSVERSION_11 = 3,
SVGA3DVSVERSION_20 = 5,
SVGA3DVSVERSION_30 = 7,
SVGA3DVSVERSION_40 = 9,
SVGA3DVSVERSION_MAX
} SVGA3dVertexShaderVersion;
/* SVGA3D instruction op codes. */
typedef enum {
SVGA3DOP_NOP = 0,
SVGA3DOP_MOV,
SVGA3DOP_ADD,
SVGA3DOP_SUB,
SVGA3DOP_MAD,
SVGA3DOP_MUL,
SVGA3DOP_RCP,
SVGA3DOP_RSQ,
SVGA3DOP_DP3,
SVGA3DOP_DP4,
SVGA3DOP_MIN,
SVGA3DOP_MAX,
SVGA3DOP_SLT,
SVGA3DOP_SGE,
SVGA3DOP_EXP,
SVGA3DOP_LOG,
SVGA3DOP_LIT,
SVGA3DOP_DST,
SVGA3DOP_LRP,
SVGA3DOP_FRC,
SVGA3DOP_M4x4,
SVGA3DOP_M4x3,
SVGA3DOP_M3x4,
SVGA3DOP_M3x3,
SVGA3DOP_M3x2,
SVGA3DOP_CALL,
SVGA3DOP_CALLNZ,
SVGA3DOP_LOOP,
SVGA3DOP_RET,
SVGA3DOP_ENDLOOP,
SVGA3DOP_LABEL,
SVGA3DOP_DCL,
SVGA3DOP_POW,
SVGA3DOP_CRS,
SVGA3DOP_SGN,
SVGA3DOP_ABS,
SVGA3DOP_NRM,
SVGA3DOP_SINCOS,
SVGA3DOP_REP,
SVGA3DOP_ENDREP,
SVGA3DOP_IF,
SVGA3DOP_IFC,
SVGA3DOP_ELSE,
SVGA3DOP_ENDIF,
SVGA3DOP_BREAK,
SVGA3DOP_BREAKC,
SVGA3DOP_MOVA,
SVGA3DOP_DEFB,
SVGA3DOP_DEFI,
SVGA3DOP_TEXCOORD = 64,
SVGA3DOP_TEXKILL,
SVGA3DOP_TEX,
SVGA3DOP_TEXBEM,
SVGA3DOP_TEXBEML,
SVGA3DOP_TEXREG2AR,
SVGA3DOP_TEXREG2GB = 70,
SVGA3DOP_TEXM3x2PAD,
SVGA3DOP_TEXM3x2TEX,
SVGA3DOP_TEXM3x3PAD,
SVGA3DOP_TEXM3x3TEX,
SVGA3DOP_RESERVED0,
SVGA3DOP_TEXM3x3SPEC,
SVGA3DOP_TEXM3x3VSPEC,
SVGA3DOP_EXPP,
SVGA3DOP_LOGP,
SVGA3DOP_CND = 80,
SVGA3DOP_DEF,
SVGA3DOP_TEXREG2RGB,
SVGA3DOP_TEXDP3TEX,
SVGA3DOP_TEXM3x2DEPTH,
SVGA3DOP_TEXDP3,
SVGA3DOP_TEXM3x3,
SVGA3DOP_TEXDEPTH,
SVGA3DOP_CMP,
SVGA3DOP_BEM,
SVGA3DOP_DP2ADD = 90,
SVGA3DOP_DSX,
SVGA3DOP_DSY,
SVGA3DOP_TEXLDD,
SVGA3DOP_SETP,
SVGA3DOP_TEXLDL,
SVGA3DOP_BREAKP = 96,
SVGA3DOP_LAST_INST,
SVGA3DOP_PHASE = 0xFFFD,
SVGA3DOP_COMMENT = 0xFFFE,
SVGA3DOP_END = 0xFFFF,
} SVGA3dShaderOpCodeType;
/* SVGA3D operation control/comparison function types */
typedef enum {
SVGA3DOPCONT_NONE,
SVGA3DOPCONT_PROJECT, /* Projective texturing */
SVGA3DOPCONT_BIAS, /* Texturing with a LOD bias */
} SVGA3dShaderOpCodeControlFnType;
typedef enum {
SVGA3DOPCOMP_RESERVED0 = 0,
SVGA3DOPCOMP_GT,
SVGA3DOPCOMP_EQ,
SVGA3DOPCOMP_GE,
SVGA3DOPCOMP_LT,
SVGA3DOPCOMPC_NE,
SVGA3DOPCOMP_LE,
SVGA3DOPCOMP_RESERVED1
} SVGA3dShaderOpCodeCompFnType;
/* SVGA3D register types */
typedef enum {
SVGA3DREG_TEMP = 0, /* Temporary register file */
SVGA3DREG_INPUT, /* Input register file */
SVGA3DREG_CONST, /* Constant register file */
SVGA3DREG_ADDR, /* Address register for VS */
SVGA3DREG_TEXTURE = 3, /* Texture register file for PS */
SVGA3DREG_RASTOUT, /* Rasterizer register file */
SVGA3DREG_ATTROUT, /* Attribute output register file */
SVGA3DREG_TEXCRDOUT, /* Texture coordinate output register file */
SVGA3DREG_OUTPUT = 6, /* Output register file for VS 3.0+ */
SVGA3DREG_CONSTINT, /* Constant integer vector register file */
SVGA3DREG_COLOROUT, /* Color output register file */
SVGA3DREG_DEPTHOUT, /* Depth output register file */
SVGA3DREG_SAMPLER, /* Sampler state register file */
SVGA3DREG_CONST2, /* Constant register file 2048 - 4095 */
SVGA3DREG_CONST3, /* Constant register file 4096 - 6143 */
SVGA3DREG_CONST4, /* Constant register file 6144 - 8191 */
SVGA3DREG_CONSTBOOL, /* Constant boolean register file */
SVGA3DREG_LOOP, /* Loop counter register file */
SVGA3DREG_TEMPFLOAT16, /* 16-bit float temp register file */
SVGA3DREG_MISCTYPE, /* Miscellaneous (single) registers */
SVGA3DREG_LABEL, /* Label */
SVGA3DREG_PREDICATE, /* Predicate register */
} SVGA3dShaderRegType;
/* SVGA3D rasterizer output register types */
typedef enum {
SVGA3DRASTOUT_POSITION = 0,
SVGA3DRASTOUT_FOG,
SVGA3DRASTOUT_PSIZE
} SVGA3dShaderRastOutRegType;
/* SVGA3D miscellaneous register types */
typedef enum {
SVGA3DMISCREG_POSITION = 0, /* Input position x,y,z,rhw (PS) */
SVGA3DMISCREG_FACE /* Floating point primitive area (PS) */
} SVGA3DShaderMiscRegType;
/* SVGA3D sampler types */
typedef enum {
SVGA3DSAMP_UNKNOWN = 0, /* Uninitialized value */
SVGA3DSAMP_2D = 2, /* dcl_2d s# (for declaring a 2D texture) */
SVGA3DSAMP_CUBE, /* dcl_cube s# (for declaring a cube texture) */
SVGA3DSAMP_VOLUME, /* dcl_volume s# (for declaring a volume texture) */
SVGA3DSAMP_2D_SHADOW, /* dcl_2d s# (for declaring a 2D shadow texture) */
SVGA3DSAMP_MAX,
} SVGA3dShaderSamplerType;
/* SVGA3D write mask */
#define SVGA3DWRITEMASK_0 1 /* Component 0 (X;Red) */
#define SVGA3DWRITEMASK_1 2 /* Component 1 (Y;Green) */
#define SVGA3DWRITEMASK_2 4 /* Component 2 (Z;Blue) */
#define SVGA3DWRITEMASK_3 8 /* Component 3 (W;Alpha) */
#define SVGA3DWRITEMASK_ALL 15 /* All components */
/* SVGA3D destination modifiers */
#define SVGA3DDSTMOD_NONE 0 /* nop */
#define SVGA3DDSTMOD_SATURATE 1 /* clamp to [0, 1] */
#define SVGA3DDSTMOD_PARTIALPRECISION 2 /* Partial precision hint */
/*
* Relevant to multisampling only:
* When the pixel center is not covered, sample
* attribute or compute gradients/LOD
* using multisample "centroid" location.
* "Centroid" is some location within the covered
* region of the pixel.
*/
#define SVGA3DDSTMOD_MSAMPCENTROID 4
/* SVGA3D destination shift scale */
typedef enum {
SVGA3DDSTSHFSCALE_X1 = 0, /* 1.0 */
SVGA3DDSTSHFSCALE_X2 = 1, /* 2.0 */
SVGA3DDSTSHFSCALE_X4 = 2, /* 4.0 */
SVGA3DDSTSHFSCALE_X8 = 3, /* 8.0 */
SVGA3DDSTSHFSCALE_D8 = 13, /* 0.125 */
SVGA3DDSTSHFSCALE_D4 = 14, /* 0.25 */
SVGA3DDSTSHFSCALE_D2 = 15 /* 0.5 */
} SVGA3dShaderDstShfScaleType;
/* SVGA3D source swizzle */
#define SVGA3DSWIZZLE_REPLICATEX 0x00
#define SVGA3DSWIZZLE_REPLICATEY 0x55
#define SVGA3DSWIZZLE_REPLICATEZ 0xAA
#define SVGA3DSWIZZLE_REPLICATEW 0xFF
#define SVGA3DSWIZZLE_NONE 0xE4
#define SVGA3DSWIZZLE_YZXW 0xC9
#define SVGA3DSWIZZLE_ZXYW 0xD2
#define SVGA3DSWIZZLE_WXYZ 0x1B
/* SVGA3D source modifiers */
typedef enum {
SVGA3DSRCMOD_NONE = 0, /* nop */
SVGA3DSRCMOD_NEG, /* negate */
SVGA3DSRCMOD_BIAS, /* bias */
SVGA3DSRCMOD_BIASNEG, /* bias and negate */
SVGA3DSRCMOD_SIGN, /* sign */
SVGA3DSRCMOD_SIGNNEG, /* sign and negate */
SVGA3DSRCMOD_COMP, /* complement */
SVGA3DSRCMOD_X2, /* x2 */
SVGA3DSRCMOD_X2NEG, /* x2 and negate */
SVGA3DSRCMOD_DZ, /* divide through by z component */
SVGA3DSRCMOD_DW, /* divide through by w component */
SVGA3DSRCMOD_ABS, /* abs() */
SVGA3DSRCMOD_ABSNEG, /* -abs() */
SVGA3DSRCMOD_NOT, /* ! (for predicate register) */
} SVGA3dShaderSrcModType;
/* SVGA3D instruction token */
typedef struct {
union {
struct {
uint32 comment_op : 16;
uint32 comment_size : 16;
};
struct {
uint32 op : 16;
uint32 control : 3;
uint32 reserved2 : 5;
uint32 size : 4;
uint32 predicated : 1;
uint32 reserved1 : 1;
uint32 coissue : 1;
uint32 reserved0 : 1;
};
uint32 value;
};
} SVGA3dShaderInstToken;
/* SVGA3D destination parameter token */
typedef struct {
union {
struct {
uint32 num : 11;
uint32 type_upper : 2;
uint32 relAddr : 1;
uint32 reserved1 : 2;
uint32 mask : 4;
uint32 dstMod : 4;
uint32 shfScale : 4;
uint32 type_lower : 3;
uint32 reserved0 : 1;
};
uint32 value;
};
} SVGA3dShaderDestToken;
/* SVGA3D source parameter token */
typedef struct {
union {
struct {
uint32 num : 11;
uint32 type_upper : 2;
uint32 relAddr : 1;
uint32 reserved1 : 2;
uint32 swizzle : 8;
uint32 srcMod : 4;
uint32 type_lower : 3;
uint32 reserved0 : 1;
};
uint32 value;
};
} SVGA3dShaderSrcToken;
/* SVGA3DOP_DCL parameter tokens */
typedef struct {
union {
struct {
union {
struct {
uint32 usage : 5;
uint32 reserved1 : 11;
uint32 index : 4;
uint32 reserved0 : 12;
}; /* input / output declaration */
struct {
uint32 reserved3 : 27;
uint32 type : 4;
uint32 reserved2 : 1;
}; /* sampler declaration */
};
SVGA3dShaderDestToken dst;
};
uint32 values[2];
};
} SVGA3DOpDclArgs;
/* SVGA3DOP_DEF parameter tokens */
typedef struct {
union {
struct {
SVGA3dShaderDestToken dst;
union {
float constValues[4];
int constIValues[4];
Bool constBValue;
};
};
uint32 values[5];
};
} SVGA3DOpDefArgs;
/* SVGA3D shader token */
typedef union {
uint32 value;
SVGA3dShaderInstToken inst;
SVGA3dShaderDestToken dest;
SVGA3dShaderSrcToken src;
} SVGA3dShaderToken;
/* SVGA3D shader program */
typedef struct {
SVGA3dShaderVersion version;
/* SVGA3dShaderToken stream */
} SVGA3dShaderProgram;
/* SVGA3D version specific register assignments */
static const uint32 SVGA3D_INPUT_REG_POSITION_VS11 = 0;
static const uint32 SVGA3D_INPUT_REG_PSIZE_VS11 = 1;
static const uint32 SVGA3D_INPUT_REG_FOG_VS11 = 3;
static const uint32 SVGA3D_INPUT_REG_FOG_MASK_VS11 = SVGA3DWRITEMASK_3;
static const uint32 SVGA3D_INPUT_REG_COLOR_BASE_VS11 = 2;
static const uint32 SVGA3D_INPUT_REG_TEXCOORD_BASE_VS11 = 4;
static const uint32 SVGA3D_INPUT_REG_COLOR_BASE_PS11 = 0;
static const uint32 SVGA3D_INPUT_REG_TEXCOORD_BASE_PS11 = 2;
static const uint32 SVGA3D_OUTPUT_REG_DEPTH_PS11 = 0;
static const uint32 SVGA3D_OUTPUT_REG_COLOR_PS11 = 1;
static const uint32 SVGA3D_INPUT_REG_COLOR_BASE_PS20 = 0;
static const uint32 SVGA3D_INPUT_REG_COLOR_NUM_PS20 = 2;
static const uint32 SVGA3D_INPUT_REG_TEXCOORD_BASE_PS20 = 2;
static const uint32 SVGA3D_INPUT_REG_TEXCOORD_NUM_PS20 = 8;
static const uint32 SVGA3D_OUTPUT_REG_COLOR_BASE_PS20 = 1;
static const uint32 SVGA3D_OUTPUT_REG_COLOR_NUM_PS20 = 4;
static const uint32 SVGA3D_OUTPUT_REG_DEPTH_BASE_PS20 = 0;
static const uint32 SVGA3D_OUTPUT_REG_DEPTH_NUM_PS20 = 1;
/*
*----------------------------------------------------------------------
*
* SVGA3dShaderGetRegType --
*
* As the register type is split into two non sequential fields,
* this function provides an useful way of accessing the actual
* register type without having to manually concatenate the
* type_upper and type_lower fields.
*
* Results:
* Returns the register type.
*
*----------------------------------------------------------------------
*/
static INLINE SVGA3dShaderRegType
SVGA3dShaderGetRegType(uint32 token)
{
SVGA3dShaderSrcToken src;
src.value = token;
return (SVGA3dShaderRegType)(src.type_upper << 3 | src.type_lower);
}
#endif /* __SVGA3D_SHADER_DEFS__ */

/contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/svga/include/svga3d_surfacedefs.h
0,0 → 1,906
/**********************************************************
* Copyright 1998-2014 VMware, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
**********************************************************/
/*
* svga3d_surfacedefs.h --
*
* Surface/format/image helper code.
*/
#include "svga3d_reg.h"
#define max_t(type, x, y) ((x) > (y) ? (x) : (y))
/*
* enum svga3d_block_desc describes the active data channels in a block.
*
* There can be at-most four active channels in a block:
* 1. Red, bump W, luminance and depth are stored in the first channel.
* 2. Green, bump V and stencil are stored in the second channel.
* 3. Blue and bump U are stored in the third channel.
* 4. Alpha and bump Q are stored in the fourth channel.
*
* Block channels can be used to store compressed and buffer data:
* 1. For compressed formats, only the data channel is used and its size
* is equal to that of a singular block in the compression scheme.
* 2. For buffer formats, only the data channel is used and its size is
* exactly one byte in length.
* 3. In each case the bit depth represent the size of a singular block.
*
* Note: Compressed and IEEE formats do not use the bitMask structure.
*/
enum svga3d_block_desc {
SVGA3DBLOCKDESC_NONE = 0, /* No channels are active */
SVGA3DBLOCKDESC_BLUE = 1 << 0, /* Block with red channel
data */
SVGA3DBLOCKDESC_U = 1 << 0, /* Block with bump U channel
data */
SVGA3DBLOCKDESC_UV_VIDEO = 1 << 7, /* Block with alternating video
U and V */
SVGA3DBLOCKDESC_GREEN = 1 << 1, /* Block with green channel
data */
SVGA3DBLOCKDESC_V = 1 << 1, /* Block with bump V channel
data */
SVGA3DBLOCKDESC_STENCIL = 1 << 1, /* Block with a stencil
channel */
SVGA3DBLOCKDESC_RED = 1 << 2, /* Block with blue channel
data */
SVGA3DBLOCKDESC_W = 1 << 2, /* Block with bump W channel
data */
SVGA3DBLOCKDESC_LUMINANCE = 1 << 2, /* Block with luminance channel
data */
SVGA3DBLOCKDESC_Y = 1 << 2, /* Block with video luminance
data */
SVGA3DBLOCKDESC_DEPTH = 1 << 2, /* Block with depth channel */
SVGA3DBLOCKDESC_ALPHA = 1 << 3, /* Block with an alpha
channel */
SVGA3DBLOCKDESC_Q = 1 << 3, /* Block with bump Q channel
data */
SVGA3DBLOCKDESC_BUFFER = 1 << 4, /* Block stores 1 byte of
data */
SVGA3DBLOCKDESC_COMPRESSED = 1 << 5, /* Block stores n bytes of
data depending on the
compression method used */
SVGA3DBLOCKDESC_IEEE_FP = 1 << 6, /* Block stores data in an IEEE
floating point
representation in
all channels */
SVGA3DBLOCKDESC_PLANAR_YUV = 1 << 8, /* Three separate blocks store
data. */
SVGA3DBLOCKDESC_U_VIDEO = 1 << 9, /* Block with U video data */
SVGA3DBLOCKDESC_V_VIDEO = 1 << 10, /* Block with V video data */
SVGA3DBLOCKDESC_EXP = 1 << 11, /* Shared exponent */
SVGA3DBLOCKDESC_SRGB = 1 << 12, /* Data is in sRGB format */
SVGA3DBLOCKDESC_2PLANAR_YUV = 1 << 13, /* 2 planes of Y, UV,
e.g., NV12. */
SVGA3DBLOCKDESC_3PLANAR_YUV = 1 << 14, /* 3 planes of separate
Y, U, V, e.g., YV12. */
SVGA3DBLOCKDESC_RG = SVGA3DBLOCKDESC_RED |
SVGA3DBLOCKDESC_GREEN,
SVGA3DBLOCKDESC_RGB = SVGA3DBLOCKDESC_RG |
SVGA3DBLOCKDESC_BLUE,
SVGA3DBLOCKDESC_RGB_SRGB = SVGA3DBLOCKDESC_RGB |
SVGA3DBLOCKDESC_SRGB,
SVGA3DBLOCKDESC_RGBA = SVGA3DBLOCKDESC_RGB |
SVGA3DBLOCKDESC_ALPHA,
SVGA3DBLOCKDESC_RGBA_SRGB = SVGA3DBLOCKDESC_RGBA |
SVGA3DBLOCKDESC_SRGB,
SVGA3DBLOCKDESC_UV = SVGA3DBLOCKDESC_U |
SVGA3DBLOCKDESC_V,
SVGA3DBLOCKDESC_UVL = SVGA3DBLOCKDESC_UV |
SVGA3DBLOCKDESC_LUMINANCE,
SVGA3DBLOCKDESC_UVW = SVGA3DBLOCKDESC_UV |
SVGA3DBLOCKDESC_W,
SVGA3DBLOCKDESC_UVWA = SVGA3DBLOCKDESC_UVW |
SVGA3DBLOCKDESC_ALPHA,
SVGA3DBLOCKDESC_UVWQ = SVGA3DBLOCKDESC_U |
SVGA3DBLOCKDESC_V |
SVGA3DBLOCKDESC_W |
SVGA3DBLOCKDESC_Q,
SVGA3DBLOCKDESC_LA = SVGA3DBLOCKDESC_LUMINANCE |
SVGA3DBLOCKDESC_ALPHA,
SVGA3DBLOCKDESC_R_FP = SVGA3DBLOCKDESC_RED |
SVGA3DBLOCKDESC_IEEE_FP,
SVGA3DBLOCKDESC_RG_FP = SVGA3DBLOCKDESC_R_FP |
SVGA3DBLOCKDESC_GREEN,
SVGA3DBLOCKDESC_RGB_FP = SVGA3DBLOCKDESC_RG_FP |
SVGA3DBLOCKDESC_BLUE,
SVGA3DBLOCKDESC_RGBA_FP = SVGA3DBLOCKDESC_RGB_FP |
SVGA3DBLOCKDESC_ALPHA,
SVGA3DBLOCKDESC_DS = SVGA3DBLOCKDESC_DEPTH |
SVGA3DBLOCKDESC_STENCIL,
SVGA3DBLOCKDESC_YUV = SVGA3DBLOCKDESC_UV_VIDEO |
SVGA3DBLOCKDESC_Y,
SVGA3DBLOCKDESC_AYUV = SVGA3DBLOCKDESC_ALPHA |
SVGA3DBLOCKDESC_Y |
SVGA3DBLOCKDESC_U_VIDEO |
SVGA3DBLOCKDESC_V_VIDEO,
SVGA3DBLOCKDESC_RGBE = SVGA3DBLOCKDESC_RGB |
SVGA3DBLOCKDESC_EXP,
SVGA3DBLOCKDESC_COMPRESSED_SRGB = SVGA3DBLOCKDESC_COMPRESSED |
SVGA3DBLOCKDESC_SRGB,
SVGA3DBLOCKDESC_NV12 = SVGA3DBLOCKDESC_PLANAR_YUV |
SVGA3DBLOCKDESC_2PLANAR_YUV,
SVGA3DBLOCKDESC_YV12 = SVGA3DBLOCKDESC_PLANAR_YUV |
SVGA3DBLOCKDESC_3PLANAR_YUV,
};
/*
* SVGA3dSurfaceDesc describes the actual pixel data.
*
* This structure provides the following information:
* 1. Block description.
* 2. Dimensions of a block in the surface.
* 3. Size of block in bytes.
* 4. Bit depth of the pixel data.
* 5. Channel bit depths and masks (if applicable).
*/
#define SVGA3D_CHANNEL_DEF(type) \
struct { \
union { \
type blue; \
type u; \
type uv_video; \
type u_video; \
}; \
union { \
type green; \
type v; \
type stencil; \
type v_video; \
}; \
union { \
type red; \
type w; \
type luminance; \
type y; \
type depth; \
type data; \
}; \
union { \
type alpha; \
type q; \
type exp; \
}; \
}
struct svga3d_surface_desc {
enum svga3d_block_desc block_desc;
SVGA3dSize block_size;
uint32 bytes_per_block;
uint32 pitch_bytes_per_block;
struct {
uint32 total;
SVGA3D_CHANNEL_DEF(uint8);
} bit_depth;
struct {
SVGA3D_CHANNEL_DEF(uint8);
} bit_offset;
};
static const struct svga3d_surface_desc svga3d_surface_descs[] = {
{SVGA3DBLOCKDESC_NONE,
{1, 1, 1}, 0, 0, {0, {{0}, {0}, {0}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_FORMAT_INVALID */
{SVGA3DBLOCKDESC_RGB,
{1, 1, 1}, 4, 4, {24, {{8}, {8}, {8}, {0} } },
{{{0}, {8}, {16}, {24} } } }, /* SVGA3D_X8R8G8B8 */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
{{{0}, {8}, {16}, {24} } } }, /* SVGA3D_A8R8G8B8 */
{SVGA3DBLOCKDESC_RGB,
{1, 1, 1}, 2, 2, {16, {{5}, {6}, {5}, {0} } },
{{{0}, {5}, {11}, {0} } } }, /* SVGA3D_R5G6B5 */
{SVGA3DBLOCKDESC_RGB,
{1, 1, 1}, 2, 2, {15, {{5}, {5}, {5}, {0} } },
{{{0}, {5}, {10}, {0} } } }, /* SVGA3D_X1R5G5B5 */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 2, 2, {16, {{5}, {5}, {5}, {1} } },
{{{0}, {5}, {10}, {15} } } }, /* SVGA3D_A1R5G5B5 */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 2, 2, {16, {{4}, {4}, {4}, {4} } },
{{{0}, {4}, {8}, {12} } } }, /* SVGA3D_A4R4G4B4 */
{SVGA3DBLOCKDESC_DEPTH,
{1, 1, 1}, 4, 4, {32, {{0}, {0}, {32}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_Z_D32 */
{SVGA3DBLOCKDESC_DEPTH,
{1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_Z_D16 */
{SVGA3DBLOCKDESC_DS,
{1, 1, 1}, 4, 4, {32, {{0}, {8}, {24}, {0} } },
{{{0}, {24}, {0}, {0} } } }, /* SVGA3D_Z_D24S8 */
{SVGA3DBLOCKDESC_DS,
{1, 1, 1}, 2, 2, {16, {{0}, {1}, {15}, {0} } },
{{{0}, {15}, {0}, {0} } } }, /* SVGA3D_Z_D15S1 */
{SVGA3DBLOCKDESC_LUMINANCE,
{1, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_LUMINANCE8 */
{SVGA3DBLOCKDESC_LA,
{1, 1, 1}, 1, 1, {8, {{0}, {0}, {4}, {4} } },
{{{0}, {0}, {0}, {4} } } }, /* SVGA3D_LUMINANCE4_ALPHA4 */
{SVGA3DBLOCKDESC_LUMINANCE,
{1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_LUMINANCE16 */
{SVGA3DBLOCKDESC_LA,
{1, 1, 1}, 2, 2, {16, {{0}, {0}, {8}, {8} } },
{{{0}, {0}, {0}, {8} } } }, /* SVGA3D_LUMINANCE8_ALPHA8 */
{SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 8, 8, {64, {{0}, {0}, {64}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_DXT1 */
{SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_DXT2 */
{SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_DXT3 */
{SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_DXT4 */
{SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_DXT5 */
{SVGA3DBLOCKDESC_UV,
{1, 1, 1}, 2, 2, {16, {{0}, {0}, {8}, {8} } },
{{{0}, {0}, {0}, {8} } } }, /* SVGA3D_BUMPU8V8 */
{SVGA3DBLOCKDESC_UVL,
{1, 1, 1}, 2, 2, {16, {{5}, {5}, {6}, {0} } },
{{{11}, {6}, {0}, {0} } } }, /* SVGA3D_BUMPL6V5U5 */
{SVGA3DBLOCKDESC_UVL,
{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {0} } },
{{{16}, {8}, {0}, {0} } } }, /* SVGA3D_BUMPX8L8V8U8 */
{SVGA3DBLOCKDESC_UVL,
{1, 1, 1}, 3, 3, {24, {{8}, {8}, {8}, {0} } },
{{{16}, {8}, {0}, {0} } } }, /* SVGA3D_BUMPL8V8U8 */
{SVGA3DBLOCKDESC_RGBA_FP,
{1, 1, 1}, 8, 8, {64, {{16}, {16}, {16}, {16} } },
{{{32}, {16}, {0}, {48} } } }, /* SVGA3D_ARGB_S10E5 */
{SVGA3DBLOCKDESC_RGBA_FP,
{1, 1, 1}, 16, 16, {128, {{32}, {32}, {32}, {32} } },
{{{64}, {32}, {0}, {96} } } }, /* SVGA3D_ARGB_S23E8 */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4, {32, {{10}, {10}, {10}, {2} } },
{{{0}, {10}, {20}, {30} } } }, /* SVGA3D_A2R10G10B10 */
{SVGA3DBLOCKDESC_UV,
{1, 1, 1}, 2, 2, {16, {{8}, {8}, {0}, {0} } },
{{{8}, {0}, {0}, {0} } } }, /* SVGA3D_V8U8 */
{SVGA3DBLOCKDESC_UVWQ,
{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
{{{24}, {16}, {8}, {0} } } }, /* SVGA3D_Q8W8V8U8 */
{SVGA3DBLOCKDESC_UV,
{1, 1, 1}, 2, 2, {16, {{8}, {8}, {0}, {0} } },
{{{8}, {0}, {0}, {0} } } }, /* SVGA3D_CxV8U8 */
{SVGA3DBLOCKDESC_UVL,
{1, 1, 1}, 4, 4, {24, {{8}, {8}, {8}, {0} } },
{{{16}, {8}, {0}, {0} } } }, /* SVGA3D_X8L8V8U8 */
{SVGA3DBLOCKDESC_UVWA,
{1, 1, 1}, 4, 4, {32, {{10}, {10}, {10}, {2} } },
{{{0}, {10}, {20}, {30} } } }, /* SVGA3D_A2W10V10U10 */
{SVGA3DBLOCKDESC_ALPHA,
{1, 1, 1}, 1, 1, {8, {{0}, {0}, {0}, {8} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_ALPHA8 */
{SVGA3DBLOCKDESC_R_FP,
{1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R_S10E5 */
{SVGA3DBLOCKDESC_R_FP,
{1, 1, 1}, 4, 4, {32, {{0}, {0}, {32}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R_S23E8 */
{SVGA3DBLOCKDESC_RG_FP,
{1, 1, 1}, 4, 4, {32, {{0}, {16}, {16}, {0} } },
{{{0}, {16}, {0}, {0} } } }, /* SVGA3D_RG_S10E5 */
{SVGA3DBLOCKDESC_RG_FP,
{1, 1, 1}, 8, 8, {64, {{0}, {32}, {32}, {0} } },
{{{0}, {32}, {0}, {0} } } }, /* SVGA3D_RG_S23E8 */
{SVGA3DBLOCKDESC_BUFFER,
{1, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BUFFER */
{SVGA3DBLOCKDESC_DEPTH,
{1, 1, 1}, 4, 4, {32, {{0}, {0}, {24}, {0} } },
{{{0}, {24}, {0}, {0} } } }, /* SVGA3D_Z_D24X8 */
{SVGA3DBLOCKDESC_UV,
{1, 1, 1}, 4, 4, {32, {{16}, {16}, {0}, {0} } },
{{{16}, {0}, {0}, {0} } } }, /* SVGA3D_V16U16 */
{SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 4, 4, {32, {{0}, {16}, {16}, {0} } },
{{{0}, {0}, {16}, {0} } } }, /* SVGA3D_G16R16 */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 8, 8, {64, {{16}, {16}, {16}, {16} } },
{{{32}, {16}, {0}, {48} } } }, /* SVGA3D_A16B16G16R16 */
{SVGA3DBLOCKDESC_YUV,
{1, 1, 1}, 2, 2, {16, {{8}, {0}, {8}, {0} } },
{{{0}, {0}, {8}, {0} } } }, /* SVGA3D_UYVY */
{SVGA3DBLOCKDESC_YUV,
{1, 1, 1}, 2, 2, {16, {{8}, {0}, {8}, {0} } },
{{{8}, {0}, {0}, {0} } } }, /* SVGA3D_YUY2 */
{SVGA3DBLOCKDESC_NV12,
{2, 2, 1}, 6, 2, {48, {{0}, {0}, {48}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_NV12 */
{SVGA3DBLOCKDESC_AYUV,
{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
{{{0}, {8}, {16}, {24} } } }, /* SVGA3D_AYUV */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 16, 16, {128, {{32}, {32}, {32}, {32} } },
{{{64}, {32}, {0}, {96} } } }, /* SVGA3D_R32G32B32A32_TYPELESS */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 16, 16, {128, {{32}, {32}, {32}, {32} } },
{{{64}, {32}, {0}, {96} } } }, /* SVGA3D_R32G32B32A32_UINT */
{SVGA3DBLOCKDESC_UVWQ,
{1, 1, 1}, 16, 16, {128, {{32}, {32}, {32}, {32} } },
{{{64}, {32}, {0}, {96} } } }, /* SVGA3D_R32G32B32A32_SINT */
{SVGA3DBLOCKDESC_RGB,
{1, 1, 1}, 12, 12, {96, {{32}, {32}, {32}, {0} } },
{{{64}, {32}, {0}, {0} } } }, /* SVGA3D_R32G32B32_TYPELESS */
{SVGA3DBLOCKDESC_RGB_FP,
{1, 1, 1}, 12, 12, {96, {{32}, {32}, {32}, {0} } },
{{{64}, {32}, {0}, {0} } } }, /* SVGA3D_R32G32B32_FLOAT */
{SVGA3DBLOCKDESC_RGB,
{1, 1, 1}, 12, 12, {96, {{32}, {32}, {32}, {0} } },
{{{64}, {32}, {0}, {0} } } }, /* SVGA3D_R32G32B32_UINT */
{SVGA3DBLOCKDESC_UVW,
{1, 1, 1}, 12, 12, {96, {{32}, {32}, {32}, {0} } },
{{{64}, {32}, {0}, {0} } } }, /* SVGA3D_R32G32B32_SINT */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 8, 8, {64, {{16}, {16}, {16}, {16} } },
{{{32}, {16}, {0}, {48} } } }, /* SVGA3D_R16G16B16A16_TYPELESS */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 8, 8, {64, {{16}, {16}, {16}, {16} } },
{{{32}, {16}, {0}, {48} } } }, /* SVGA3D_R16G16B16A16_UINT */
{SVGA3DBLOCKDESC_UVWQ,
{1, 1, 1}, 8, 8, {64, {{16}, {16}, {16}, {16} } },
{{{32}, {16}, {0}, {48} } } }, /* SVGA3D_R16G16B16A16_SNORM */
{SVGA3DBLOCKDESC_UVWQ,
{1, 1, 1}, 8, 8, {64, {{16}, {16}, {16}, {16} } },
{{{32}, {16}, {0}, {48} } } }, /* SVGA3D_R16G16B16A16_SINT */
{SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 8, 8, {64, {{0}, {32}, {32}, {0} } },
{{{0}, {32}, {0}, {0} } } }, /* SVGA3D_R32G32_TYPELESS */
{SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 8, 8, {64, {{0}, {32}, {32}, {0} } },
{{{0}, {32}, {0}, {0} } } }, /* SVGA3D_R32G32_UINT */
{SVGA3DBLOCKDESC_UV,
{1, 1, 1}, 8, 8, {64, {{0}, {32}, {32}, {0} } },
{{{0}, {32}, {0}, {0} } } }, /* SVGA3D_R32G32_SINT */
{SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 8, 8, {64, {{0}, {8}, {32}, {0} } },
{{{0}, {32}, {0}, {0} } } }, /* SVGA3D_R32G8X24_TYPELESS */
{SVGA3DBLOCKDESC_DS,
{1, 1, 1}, 8, 8, {64, {{0}, {8}, {32}, {0} } },
{{{0}, {32}, {0}, {0} } } }, /* SVGA3D_D32_FLOAT_S8X24_UINT */
{SVGA3DBLOCKDESC_R_FP,
{1, 1, 1}, 8, 8, {64, {{0}, {0}, {32}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R32_FLOAT_X8_X24_TYPELESS */
{SVGA3DBLOCKDESC_GREEN,
{1, 1, 1}, 8, 8, {64, {{0}, {8}, {0}, {0} } },
{{{0}, {32}, {0}, {0} } } }, /* SVGA3D_X32_TYPELESS_G8X24_UINT */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4, {32, {{10}, {10}, {10}, {2} } },
{{{0}, {10}, {20}, {30} } } }, /* SVGA3D_R10G10B10A2_TYPELESS */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4, {32, {{10}, {10}, {10}, {2} } },
{{{0}, {10}, {20}, {30} } } }, /* SVGA3D_R10G10B10A2_UINT */
{SVGA3DBLOCKDESC_RGB_FP,
{1, 1, 1}, 4, 4, {32, {{10}, {11}, {11}, {0} } },
{{{0}, {10}, {21}, {0} } } }, /* SVGA3D_R11G11B10_FLOAT */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
{{{16}, {8}, {0}, {24} } } }, /* SVGA3D_R8G8B8A8_TYPELESS */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
{{{16}, {8}, {0}, {24} } } }, /* SVGA3D_R8G8B8A8_UNORM */
{SVGA3DBLOCKDESC_RGBA_SRGB,
{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
{{{16}, {8}, {0}, {24} } } }, /* SVGA3D_R8G8B8A8_UNORM_SRGB */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
{{{16}, {8}, {0}, {24} } } }, /* SVGA3D_R8G8B8A8_UINT */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
{{{16}, {8}, {0}, {24} } } }, /* SVGA3D_R8G8B8A8_SINT */
{SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 4, 4, {32, {{0}, {16}, {16}, {0} } },
{{{0}, {16}, {0}, {0} } } }, /* SVGA3D_R16G16_TYPELESS */
{SVGA3DBLOCKDESC_RG_FP,
{1, 1, 1}, 4, 4, {32, {{0}, {16}, {16}, {0} } },
{{{0}, {16}, {0}, {0} } } }, /* SVGA3D_R16G16_UINT */
{SVGA3DBLOCKDESC_UV,
{1, 1, 1}, 4, 4, {32, {{0}, {16}, {16}, {0} } },
{{{0}, {16}, {0}, {0} } } }, /* SVGA3D_R16G16_SINT */
{SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 4, 4, {32, {{0}, {0}, {32}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R32_TYPELESS */
{SVGA3DBLOCKDESC_DEPTH,
{1, 1, 1}, 4, 4, {32, {{0}, {0}, {32}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_D32_FLOAT */
{SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 4, 4, {32, {{0}, {0}, {32}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R32_UINT */
{SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 4, 4, {32, {{0}, {0}, {32}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R32_SINT */
{SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 4, 4, {32, {{0}, {8}, {24}, {0} } },
{{{0}, {24}, {0}, {0} } } }, /* SVGA3D_R24G8_TYPELESS */
{SVGA3DBLOCKDESC_DS,
{1, 1, 1}, 4, 4, {32, {{0}, {8}, {24}, {0} } },
{{{0}, {24}, {0}, {0} } } }, /* SVGA3D_D24_UNORM_S8_UINT */
{SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 4, 4, {32, {{0}, {0}, {24}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R24_UNORM_X8_TYPELESS */
{SVGA3DBLOCKDESC_GREEN,
{1, 1, 1}, 4, 4, {32, {{0}, {8}, {0}, {0} } },
{{{0}, {24}, {0}, {0} } } }, /* SVGA3D_X24_TYPELESS_G8_UINT */
{SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 2, 2, {16, {{0}, {8}, {8}, {0} } },
{{{0}, {8}, {0}, {0} } } }, /* SVGA3D_R8G8_TYPELESS */
{SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 2, 2, {16, {{0}, {8}, {8}, {0} } },
{{{0}, {8}, {0}, {0} } } }, /* SVGA3D_R8G8_UNORM */
{SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 2, 2, {16, {{0}, {8}, {8}, {0} } },
{{{0}, {8}, {0}, {0} } } }, /* SVGA3D_R8G8_UINT */
{SVGA3DBLOCKDESC_UV,
{1, 1, 1}, 2, 2, {16, {{0}, {8}, {8}, {0} } },
{{{0}, {8}, {0}, {0} } } }, /* SVGA3D_R8G8_SINT */
{SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R16_TYPELESS */
{SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R16_UNORM */
{SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R16_UINT */
{SVGA3DBLOCKDESC_U,
{1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R16_SNORM */
{SVGA3DBLOCKDESC_U,
{1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R16_SINT */
{SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R8_TYPELESS */
{SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R8_UNORM */
{SVGA3DBLOCKDESC_RED,
{1, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R8_UINT */
{SVGA3DBLOCKDESC_U,
{1, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R8_SNORM */
{SVGA3DBLOCKDESC_U,
{1, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R8_SINT */
{SVGA3DBLOCKDESC_RED,
{8, 1, 1}, 1, 1, {8, {{0}, {0}, {8}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_R1_UNORM */
{SVGA3DBLOCKDESC_RGBE,
{1, 1, 1}, 4, 4, {32, {{9}, {9}, {9}, {5} } },
{{{18}, {9}, {0}, {27} } } }, /* SVGA3D_R9G9B9E5_SHAREDEXP */
{SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 2, 2, {16, {{0}, {8}, {8}, {0} } },
{{{0}, {8}, {0}, {0} } } }, /* SVGA3D_R8G8_B8G8_UNORM */
{SVGA3DBLOCKDESC_RG,
{1, 1, 1}, 2, 2, {16, {{0}, {8}, {8}, {0} } },
{{{0}, {8}, {0}, {0} } } }, /* SVGA3D_G8R8_G8B8_UNORM */
{SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 8, 8, {64, {{0}, {0}, {64}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC1_TYPELESS */
{SVGA3DBLOCKDESC_COMPRESSED_SRGB,
{4, 4, 1}, 8, 8, {64, {{0}, {0}, {64}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC1_UNORM_SRGB */
{SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC2_TYPELESS */
{SVGA3DBLOCKDESC_COMPRESSED_SRGB,
{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC2_UNORM_SRGB */
{SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC3_TYPELESS */
{SVGA3DBLOCKDESC_COMPRESSED_SRGB,
{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC3_UNORM_SRGB */
{SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 8, 8, {64, {{0}, {0}, {64}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC4_TYPELESS */
{SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 8, 8, {64, {{0}, {0}, {64}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC4_UNORM */
{SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 8, 8, {64, {{0}, {0}, {64}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC4_SNORM */
{SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC5_TYPELESS */
{SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC5_UNORM */
{SVGA3DBLOCKDESC_COMPRESSED,
{4, 4, 1}, 16, 16, {128, {{0}, {0}, {128}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_BC5_SNORM */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4, {32, {{10}, {10}, {10}, {2} } },
{{{0}, {10}, {20}, {30} } } }, /* SVGA3D_R10G10B10_XR_BIAS_A2_UNORM */
{SVGA3DBLOCKDESC_RGBA,
{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
{{{0}, {8}, {16}, {24} } } }, /* SVGA3D_B8G8R8A8_TYPELESS */
{SVGA3DBLOCKDESC_RGBA_SRGB,
{1, 1, 1}, 4, 4, {32, {{8}, {8}, {8}, {8} } },
{{{0}, {8}, {16}, {24} } } }, /* SVGA3D_B8G8R8A8_UNORM_SRGB */
{SVGA3DBLOCKDESC_RGB,
{1, 1, 1}, 4, 4, {24, {{8}, {8}, {8}, {0} } },
{{{0}, {8}, {16}, {24} } } }, /* SVGA3D_B8G8R8X8_TYPELESS */
{SVGA3DBLOCKDESC_RGB_SRGB,
{1, 1, 1}, 4, 4, {24, {{8}, {8}, {8}, {0} } },
{{{0}, {8}, {16}, {24} } } }, /* SVGA3D_B8G8R8X8_UNORM_SRGB */
{SVGA3DBLOCKDESC_DEPTH,
{1, 1, 1}, 2, 2, {16, {{0}, {0}, {16}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_Z_DF16 */
{SVGA3DBLOCKDESC_DS,
{1, 1, 1}, 4, 4, {32, {{0}, {8}, {24}, {0} } },
{{{0}, {24}, {0}, {0} } } }, /* SVGA3D_Z_DF24 */
{SVGA3DBLOCKDESC_DS,
{1, 1, 1}, 4, 4, {32, {{0}, {8}, {24}, {0} } },
{{{0}, {24}, {0}, {0} } } }, /* SVGA3D_Z_D24S8_INT */
{SVGA3DBLOCKDESC_YV12,
{2, 2, 1}, 6, 2, {48, {{0}, {0}, {48}, {0} } },
{{{0}, {0}, {0}, {0} } } }, /* SVGA3D_YV12 */
};
extern const struct svga3d_surface_desc g_SVGA3dSurfaceDescs[];
extern int g_SVGA3dSurfaceDescs_size;
static inline uint32 clamped_umul32(uint32 a, uint32 b)
{
uint64_t tmp = (uint64_t) a*b;
return (tmp > (uint64_t) ((uint32) -1)) ? (uint32) -1 : tmp;
}
static inline const struct svga3d_surface_desc *
svga3dsurface_get_desc(SVGA3dSurfaceFormat format)
{
if (format < ARRAY_SIZE(svga3d_surface_descs))
return &svga3d_surface_descs[format];
return &svga3d_surface_descs[SVGA3D_FORMAT_INVALID];
}
/*
*----------------------------------------------------------------------
*
* svga3dsurface_get_mip_size --
*
* Given a base level size and the mip level, compute the size of
* the mip level.
*
* Results:
* See above.
*
* Side effects:
* None.
*
*----------------------------------------------------------------------
*/
static inline SVGA3dSize
svga3dsurface_get_mip_size(SVGA3dSize base_level, uint32 mip_level)
{
SVGA3dSize size;
size.width = max_t(uint32, base_level.width >> mip_level, 1);
size.height = max_t(uint32, base_level.height >> mip_level, 1);
size.depth = max_t(uint32, base_level.depth >> mip_level, 1);
return size;
}
static inline void
svga3dsurface_get_size_in_blocks(const struct svga3d_surface_desc *desc,
const SVGA3dSize *pixel_size,
SVGA3dSize *block_size)
{
block_size->width = DIV_ROUND_UP(pixel_size->width,
desc->block_size.width);
block_size->height = DIV_ROUND_UP(pixel_size->height,
desc->block_size.height);
block_size->depth = DIV_ROUND_UP(pixel_size->depth,
desc->block_size.depth);
}
static inline bool
svga3dsurface_is_planar_surface(const struct svga3d_surface_desc *desc)
{
return (desc->block_desc & SVGA3DBLOCKDESC_PLANAR_YUV) != 0;
}
static inline uint32
svga3dsurface_calculate_pitch(const struct svga3d_surface_desc *desc,
const SVGA3dSize *size)
{
uint32 pitch;
SVGA3dSize blocks;
svga3dsurface_get_size_in_blocks(desc, size, &blocks);
pitch = blocks.width * desc->pitch_bytes_per_block;
return pitch;
}
/*
*-----------------------------------------------------------------------------
*
* svga3dsurface_get_image_buffer_size --
*
* Return the number of bytes of buffer space required to store
* one image of a surface, optionally using the specified pitch.
*
* If pitch is zero, it is assumed that rows are tightly packed.
*
* This function is overflow-safe. If the result would have
* overflowed, instead we return MAX_UINT32.
*
* Results:
* Byte count.
*
* Side effects:
* None.
*
*-----------------------------------------------------------------------------
*/
static inline uint32
svga3dsurface_get_image_buffer_size(const struct svga3d_surface_desc *desc,
const SVGA3dSize *size,
uint32 pitch)
{
SVGA3dSize image_blocks;
uint32 slice_size, total_size;
svga3dsurface_get_size_in_blocks(desc, size, &image_blocks);
if (svga3dsurface_is_planar_surface(desc)) {
total_size = clamped_umul32(image_blocks.width,
image_blocks.height);
total_size = clamped_umul32(total_size, image_blocks.depth);
total_size = clamped_umul32(total_size, desc->bytes_per_block);
return total_size;
}
if (pitch == 0)
pitch = svga3dsurface_calculate_pitch(desc, size);
slice_size = clamped_umul32(image_blocks.height, pitch);
total_size = clamped_umul32(slice_size, image_blocks.depth);
return total_size;
}
static inline uint32
svga3dsurface_get_image_offset(SVGA3dSurfaceFormat format,
SVGA3dSize baseLevelSize,
uint32 numMipLevels,
uint32 face,
uint32 mip)
{
uint32 offset;
uint32 mipChainBytes;
uint32 mipChainBytesToLevel;
uint32 i;
const struct svga3d_surface_desc *desc;
SVGA3dSize mipSize;
uint32 bytes;
desc = svga3dsurface_get_desc(format);
mipChainBytes = 0;
mipChainBytesToLevel = 0;
for (i = 0; i < numMipLevels; i++) {
mipSize = svga3dsurface_get_mip_size(baseLevelSize, i);
bytes = svga3dsurface_get_image_buffer_size(desc, &mipSize, 0);
mipChainBytes += bytes;
if (i < mip) {
mipChainBytesToLevel += bytes;
}
}
offset = mipChainBytes * face + mipChainBytesToLevel;
return offset;
}
static inline uint32
svga3dsurface_get_serialized_size(SVGA3dSurfaceFormat format,
SVGA3dSize base_level_size,
uint32 num_mip_levels,
bool cubemap)
{
const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format);
uint64_t total_size = 0;
uint32 mip;
for (mip = 0; mip < num_mip_levels; mip++) {
SVGA3dSize size =
svga3dsurface_get_mip_size(base_level_size, mip);
total_size += svga3dsurface_get_image_buffer_size(desc,
&size, 0);
}
if (cubemap)
total_size *= SVGA3D_MAX_SURFACE_FACES;
return (total_size > (uint64_t) MAX_UINT32) ? MAX_UINT32 :
(uint32) total_size;
}
/**
* Compute the offset (in bytes) to a pixel in an image (or volume).
* 'width' is the image width in pixels
* 'height' is the image height in pixels
*/
static inline uint32
svga3dsurface_get_pixel_offset(SVGA3dSurfaceFormat format,
uint32 width, uint32 height,
uint32 x, uint32 y, uint32 z)
{
const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format);
const uint32 bw = desc->block_size.width, bh = desc->block_size.height;
const uint32 bd = desc->block_size.depth;
const uint32 rowstride = DIV_ROUND_UP(width, bw) * desc->bytes_per_block;
const uint32 imgstride = DIV_ROUND_UP(height, bh) * rowstride;
const uint32 offset = (z / bd * imgstride +
y / bh * rowstride +
x / bw * desc->bytes_per_block);
return offset;
}

/contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/svga/include/svga3d_types.h
0,0 → 1,1306
/**********************************************************
* Copyright 1998-2014 VMware, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
**********************************************************/
/*
* svga3d_types.h --
*
* SVGA 3d hardware definitions for basic types
*/
#ifndef _SVGA3D_TYPES_H_
#define _SVGA3D_TYPES_H_
#define INCLUDE_ALLOW_MODULE
#define INCLUDE_ALLOW_USERLEVEL
#define INCLUDE_ALLOW_VMCORE
#include "includeCheck.h"
/*
* Generic Types
*/
#define SVGA3D_INVALID_ID ((uint32)-1)
#define SVGA3D_INVALID_CID SVGA3D_INVALID_ID
#define SVGA3D_INVALID_SID SVGA3D_INVALID_ID
#define SVGA3D_INVALID_SHID SVGA3D_INVALID_ID
typedef uint32 SVGA3dBool; /* 32-bit Bool definition */
typedef uint32 SVGA3dColor; /* a, r, g, b */
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCopyRect {
uint32 x;
uint32 y;
uint32 w;
uint32 h;
uint32 srcx;
uint32 srcy;
}
#include "vmware_pack_end.h"
SVGA3dCopyRect;
typedef
#include "vmware_pack_begin.h"
struct SVGA3dCopyBox {
uint32 x;
uint32 y;
uint32 z;
uint32 w;
uint32 h;
uint32 d;
uint32 srcx;
uint32 srcy;
uint32 srcz;
}
#include "vmware_pack_end.h"
SVGA3dCopyBox;
typedef
#include "vmware_pack_begin.h"
struct SVGA3dRect {
uint32 x;
uint32 y;
uint32 w;
uint32 h;
}
#include "vmware_pack_end.h"
SVGA3dRect;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 x;
uint32 y;
uint32 z;
uint32 w;
uint32 h;
uint32 d;
}
#include "vmware_pack_end.h"
SVGA3dBox;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 x;
uint32 y;
uint32 z;
}
#include "vmware_pack_end.h"
SVGA3dPoint;
/*
* Surface formats.
*
* If you modify this list, be sure to keep GLUtil.c in sync. It
* includes the internal format definition of each surface in
* GLUtil_ConvertSurfaceFormat, and it contains a table of
* human-readable names in GLUtil_GetFormatName.
*/
typedef enum SVGA3dSurfaceFormat {
SVGA3D_FORMAT_INVALID = 0,
SVGA3D_X8R8G8B8 = 1,
SVGA3D_FORMAT_MIN = 1,
SVGA3D_A8R8G8B8 = 2,
SVGA3D_R5G6B5 = 3,
SVGA3D_X1R5G5B5 = 4,
SVGA3D_A1R5G5B5 = 5,
SVGA3D_A4R4G4B4 = 6,
SVGA3D_Z_D32 = 7,
SVGA3D_Z_D16 = 8,
SVGA3D_Z_D24S8 = 9,
SVGA3D_Z_D15S1 = 10,
SVGA3D_LUMINANCE8 = 11,
SVGA3D_LUMINANCE4_ALPHA4 = 12,
SVGA3D_LUMINANCE16 = 13,
SVGA3D_LUMINANCE8_ALPHA8 = 14,
SVGA3D_DXT1 = 15,
SVGA3D_DXT2 = 16,
SVGA3D_DXT3 = 17,
SVGA3D_DXT4 = 18,
SVGA3D_DXT5 = 19,
SVGA3D_BUMPU8V8 = 20,
SVGA3D_BUMPL6V5U5 = 21,
SVGA3D_BUMPX8L8V8U8 = 22,
SVGA3D_BUMPL8V8U8 = 23,
SVGA3D_ARGB_S10E5 = 24, /* 16-bit floating-point ARGB */
SVGA3D_ARGB_S23E8 = 25, /* 32-bit floating-point ARGB */
SVGA3D_A2R10G10B10 = 26,
/* signed formats */
SVGA3D_V8U8 = 27,
SVGA3D_Q8W8V8U8 = 28,
SVGA3D_CxV8U8 = 29,
/* mixed formats */
SVGA3D_X8L8V8U8 = 30,
SVGA3D_A2W10V10U10 = 31,
SVGA3D_ALPHA8 = 32,
/* Single- and dual-component floating point formats */
SVGA3D_R_S10E5 = 33,
SVGA3D_R_S23E8 = 34,
SVGA3D_RG_S10E5 = 35,
SVGA3D_RG_S23E8 = 36,
SVGA3D_BUFFER = 37,
SVGA3D_Z_D24X8 = 38,
SVGA3D_V16U16 = 39,
SVGA3D_G16R16 = 40,
SVGA3D_A16B16G16R16 = 41,
/* Packed Video formats */
SVGA3D_UYVY = 42,
SVGA3D_YUY2 = 43,
/* Planar video formats */
SVGA3D_NV12 = 44,
/* Video format with alpha */
SVGA3D_AYUV = 45,
SVGA3D_R32G32B32A32_TYPELESS = 46,
SVGA3D_R32G32B32A32_UINT = 47,
SVGA3D_R32G32B32A32_SINT = 48,
SVGA3D_R32G32B32_TYPELESS = 49,
SVGA3D_R32G32B32_FLOAT = 50,
SVGA3D_R32G32B32_UINT = 51,
SVGA3D_R32G32B32_SINT = 52,
SVGA3D_R16G16B16A16_TYPELESS = 53,
SVGA3D_R16G16B16A16_UINT = 54,
SVGA3D_R16G16B16A16_SNORM = 55,
SVGA3D_R16G16B16A16_SINT = 56,
SVGA3D_R32G32_TYPELESS = 57,
SVGA3D_R32G32_UINT = 58,
SVGA3D_R32G32_SINT = 59,
SVGA3D_R32G8X24_TYPELESS = 60,
SVGA3D_D32_FLOAT_S8X24_UINT = 61,
SVGA3D_R32_FLOAT_X8X24_TYPELESS = 62,
SVGA3D_X32_TYPELESS_G8X24_UINT = 63,
SVGA3D_R10G10B10A2_TYPELESS = 64,
SVGA3D_R10G10B10A2_UINT = 65,
SVGA3D_R11G11B10_FLOAT = 66,
SVGA3D_R8G8B8A8_TYPELESS = 67,
SVGA3D_R8G8B8A8_UNORM = 68,
SVGA3D_R8G8B8A8_UNORM_SRGB = 69,
SVGA3D_R8G8B8A8_UINT = 70,
SVGA3D_R8G8B8A8_SINT = 71,
SVGA3D_R16G16_TYPELESS = 72,
SVGA3D_R16G16_UINT = 73,
SVGA3D_R16G16_SINT = 74,
SVGA3D_R32_TYPELESS = 75,
SVGA3D_D32_FLOAT = 76,
SVGA3D_R32_UINT = 77,
SVGA3D_R32_SINT = 78,
SVGA3D_R24G8_TYPELESS = 79,
SVGA3D_D24_UNORM_S8_UINT = 80,
SVGA3D_R24_UNORM_X8_TYPELESS = 81,
SVGA3D_X24_TYPELESS_G8_UINT = 82,
SVGA3D_R8G8_TYPELESS = 83,
SVGA3D_R8G8_UNORM = 84,
SVGA3D_R8G8_UINT = 85,
SVGA3D_R8G8_SINT = 86,
SVGA3D_R16_TYPELESS = 87,
SVGA3D_R16_UNORM = 88,
SVGA3D_R16_UINT = 89,
SVGA3D_R16_SNORM = 90,
SVGA3D_R16_SINT = 91,
SVGA3D_R8_TYPELESS = 92,
SVGA3D_R8_UNORM = 93,
SVGA3D_R8_UINT = 94,
SVGA3D_R8_SNORM = 95,
SVGA3D_R8_SINT = 96,
SVGA3D_P8 = 97,
SVGA3D_R9G9B9E5_SHAREDEXP = 98,
SVGA3D_R8G8_B8G8_UNORM = 99,
SVGA3D_G8R8_G8B8_UNORM = 100,
SVGA3D_BC1_TYPELESS = 101,
SVGA3D_BC1_UNORM_SRGB = 102,
SVGA3D_BC2_TYPELESS = 103,
SVGA3D_BC2_UNORM_SRGB = 104,
SVGA3D_BC3_TYPELESS = 105,
SVGA3D_BC3_UNORM_SRGB = 106,
SVGA3D_BC4_TYPELESS = 107,
SVGA3D_ATI1 = 108, /* DX9-specific BC4_UNORM */
SVGA3D_BC4_SNORM = 109,
SVGA3D_BC5_TYPELESS = 110,
SVGA3D_ATI2 = 111, /* DX9-specific BC5_UNORM */
SVGA3D_BC5_SNORM = 112,
SVGA3D_R10G10B10_XR_BIAS_A2_UNORM = 113,
SVGA3D_B8G8R8A8_TYPELESS = 114,
SVGA3D_B8G8R8A8_UNORM_SRGB = 115,
SVGA3D_B8G8R8X8_TYPELESS = 116,
SVGA3D_B8G8R8X8_UNORM_SRGB = 117,
/* Advanced D3D9 depth formats. */
SVGA3D_Z_DF16 = 118,
SVGA3D_Z_DF24 = 119,
SVGA3D_Z_D24S8_INT = 120,
/* Planar video formats. */
SVGA3D_YV12 = 121,
SVGA3D_R32G32B32A32_FLOAT = 122,
SVGA3D_R16G16B16A16_FLOAT = 123,
SVGA3D_R16G16B16A16_UNORM = 124,
SVGA3D_R32G32_FLOAT = 125,
SVGA3D_R10G10B10A2_UNORM = 126,
SVGA3D_R8G8B8A8_SNORM = 127,
SVGA3D_R16G16_FLOAT = 128,
SVGA3D_R16G16_UNORM = 129,
SVGA3D_R16G16_SNORM = 130,
SVGA3D_R32_FLOAT = 131,
SVGA3D_R8G8_SNORM = 132,
SVGA3D_R16_FLOAT = 133,
SVGA3D_D16_UNORM = 134,
SVGA3D_A8_UNORM = 135,
SVGA3D_BC1_UNORM = 136,
SVGA3D_BC2_UNORM = 137,
SVGA3D_BC3_UNORM = 138,
SVGA3D_B5G6R5_UNORM = 139,
SVGA3D_B5G5R5A1_UNORM = 140,
SVGA3D_B8G8R8A8_UNORM = 141,
SVGA3D_B8G8R8X8_UNORM = 142,
SVGA3D_BC4_UNORM = 143,
SVGA3D_BC5_UNORM = 144,
SVGA3D_FORMAT_MAX
} SVGA3dSurfaceFormat;
/*
* These are really the D3DFORMAT_OP defines from the wdk. We need
* them so that we can query the host for what the supported surface
* operations are (when we're using the D3D backend, in particular),
* and so we can send those operations to the guest.
*/
typedef enum {
SVGA3DFORMAT_OP_TEXTURE = 0x00000001,
SVGA3DFORMAT_OP_VOLUMETEXTURE = 0x00000002,
SVGA3DFORMAT_OP_CUBETEXTURE = 0x00000004,
SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET = 0x00000008,
SVGA3DFORMAT_OP_SAME_FORMAT_RENDERTARGET = 0x00000010,
SVGA3DFORMAT_OP_ZSTENCIL = 0x00000040,
SVGA3DFORMAT_OP_ZSTENCIL_WITH_ARBITRARY_COLOR_DEPTH = 0x00000080,
/*
* This format can be used as a render target if the current display mode
* is the same depth if the alpha channel is ignored. e.g. if the device
* can render to A8R8G8B8 when the display mode is X8R8G8B8, then the
* format op list entry for A8R8G8B8 should have this cap.
*/
SVGA3DFORMAT_OP_SAME_FORMAT_UP_TO_ALPHA_RENDERTARGET = 0x00000100,
/*
* This format contains DirectDraw support (including Flip). This flag
* should not to be set on alpha formats.
*/
SVGA3DFORMAT_OP_DISPLAYMODE = 0x00000400,
/*
* The rasterizer can support some level of Direct3D support in this format
* and implies that the driver can create a Context in this mode (for some
* render target format). When this flag is set, the SVGA3DFORMAT_OP_DISPLAYMODE
* flag must also be set.
*/
SVGA3DFORMAT_OP_3DACCELERATION = 0x00000800,
/*
* This is set for a private format when the driver has put the bpp in
* the structure.
*/
SVGA3DFORMAT_OP_PIXELSIZE = 0x00001000,
/*
* Indicates that this format can be converted to any RGB format for which
* SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB is specified
*/
SVGA3DFORMAT_OP_CONVERT_TO_ARGB = 0x00002000,
/*
* Indicates that this format can be used to create offscreen plain surfaces.
*/
SVGA3DFORMAT_OP_OFFSCREENPLAIN = 0x00004000,
/*
* Indicated that this format can be read as an SRGB texture (meaning that the
* sampler will linearize the looked up data)
*/
SVGA3DFORMAT_OP_SRGBREAD = 0x00008000,
/*
* Indicates that this format can be used in the bumpmap instructions
*/
SVGA3DFORMAT_OP_BUMPMAP = 0x00010000,
/*
* Indicates that this format can be sampled by the displacement map sampler
*/
SVGA3DFORMAT_OP_DMAP = 0x00020000,
/*
* Indicates that this format cannot be used with texture filtering
*/
SVGA3DFORMAT_OP_NOFILTER = 0x00040000,
/*
* Indicates that format conversions are supported to this RGB format if
* SVGA3DFORMAT_OP_CONVERT_TO_ARGB is specified in the source format.
*/
SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB = 0x00080000,
/*
* Indicated that this format can be written as an SRGB target
* (meaning that the pixel pipe will DE-linearize data on output to format)
*/
SVGA3DFORMAT_OP_SRGBWRITE = 0x00100000,
/*
* Indicates that this format cannot be used with alpha blending
*/
SVGA3DFORMAT_OP_NOALPHABLEND = 0x00200000,
/*
* Indicates that the device can auto-generated sublevels for resources
* of this format
*/
SVGA3DFORMAT_OP_AUTOGENMIPMAP = 0x00400000,
/*
* Indicates that this format can be used by vertex texture sampler
*/
SVGA3DFORMAT_OP_VERTEXTEXTURE = 0x00800000,
/*
* Indicates that this format supports neither texture coordinate
* wrap modes, nor mipmapping.
*/
SVGA3DFORMAT_OP_NOTEXCOORDWRAPNORMIP = 0x01000000
} SVGA3dFormatOp;
#define SVGA3D_FORMAT_POSITIVE \
(SVGA3DFORMAT_OP_TEXTURE | \
SVGA3DFORMAT_OP_VOLUMETEXTURE | \
SVGA3DFORMAT_OP_CUBETEXTURE | \
SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET | \
SVGA3DFORMAT_OP_SAME_FORMAT_RENDERTARGET | \
SVGA3DFORMAT_OP_ZSTENCIL | \
SVGA3DFORMAT_OP_ZSTENCIL_WITH_ARBITRARY_COLOR_DEPTH | \
SVGA3DFORMAT_OP_SAME_FORMAT_UP_TO_ALPHA_RENDERTARGET | \
SVGA3DFORMAT_OP_DISPLAYMODE | \
SVGA3DFORMAT_OP_3DACCELERATION | \
SVGA3DFORMAT_OP_PIXELSIZE | \
SVGA3DFORMAT_OP_CONVERT_TO_ARGB | \
SVGA3DFORMAT_OP_OFFSCREENPLAIN | \
SVGA3DFORMAT_OP_SRGBREAD | \
SVGA3DFORMAT_OP_BUMPMAP | \
SVGA3DFORMAT_OP_DMAP | \
SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB | \
SVGA3DFORMAT_OP_SRGBWRITE | \
SVGA3DFORMAT_OP_AUTOGENMIPMAP | \
SVGA3DFORMAT_OP_VERTEXTEXTURE)
#define SVGA3D_FORMAT_NEGATIVE \
(SVGA3DFORMAT_OP_NOFILTER | \
SVGA3DFORMAT_OP_NOALPHABLEND | \
SVGA3DFORMAT_OP_NOTEXCOORDWRAPNORMIP)
/*
* This structure is a conversion of SVGA3DFORMAT_OP_*
* Entries must be located at the same position.
*/
typedef union {
uint32 value;
struct {
uint32 texture : 1;
uint32 volumeTexture : 1;
uint32 cubeTexture : 1;
uint32 offscreenRenderTarget : 1;
uint32 sameFormatRenderTarget : 1;
uint32 unknown1 : 1;
uint32 zStencil : 1;
uint32 zStencilArbitraryDepth : 1;
uint32 sameFormatUpToAlpha : 1;
uint32 unknown2 : 1;
uint32 displayMode : 1;
uint32 acceleration3d : 1;
uint32 pixelSize : 1;
uint32 convertToARGB : 1;
uint32 offscreenPlain : 1;
uint32 sRGBRead : 1;
uint32 bumpMap : 1;
uint32 dmap : 1;
uint32 noFilter : 1;
uint32 memberOfGroupARGB : 1;
uint32 sRGBWrite : 1;
uint32 noAlphaBlend : 1;
uint32 autoGenMipMap : 1;
uint32 vertexTexture : 1;
uint32 noTexCoordWrapNorMip : 1;
};
} SVGA3dSurfaceFormatCaps;
/*
* SVGA_3D_CMD_SETRENDERSTATE Types. All value types
* must fit in a uint32.
*/
typedef enum {
SVGA3D_RS_INVALID = 0,
SVGA3D_RS_MIN = 1,
SVGA3D_RS_ZENABLE = 1, /* SVGA3dBool */
SVGA3D_RS_ZWRITEENABLE = 2, /* SVGA3dBool */
SVGA3D_RS_ALPHATESTENABLE = 3, /* SVGA3dBool */
SVGA3D_RS_DITHERENABLE = 4, /* SVGA3dBool */
SVGA3D_RS_BLENDENABLE = 5, /* SVGA3dBool */
SVGA3D_RS_FOGENABLE = 6, /* SVGA3dBool */
SVGA3D_RS_SPECULARENABLE = 7, /* SVGA3dBool */
SVGA3D_RS_STENCILENABLE = 8, /* SVGA3dBool */
SVGA3D_RS_LIGHTINGENABLE = 9, /* SVGA3dBool */
SVGA3D_RS_NORMALIZENORMALS = 10, /* SVGA3dBool */
SVGA3D_RS_POINTSPRITEENABLE = 11, /* SVGA3dBool */
SVGA3D_RS_POINTSCALEENABLE = 12, /* SVGA3dBool */
SVGA3D_RS_STENCILREF = 13, /* uint32 */
SVGA3D_RS_STENCILMASK = 14, /* uint32 */
SVGA3D_RS_STENCILWRITEMASK = 15, /* uint32 */
SVGA3D_RS_FOGSTART = 16, /* float */
SVGA3D_RS_FOGEND = 17, /* float */
SVGA3D_RS_FOGDENSITY = 18, /* float */
SVGA3D_RS_POINTSIZE = 19, /* float */
SVGA3D_RS_POINTSIZEMIN = 20, /* float */
SVGA3D_RS_POINTSIZEMAX = 21, /* float */
SVGA3D_RS_POINTSCALE_A = 22, /* float */
SVGA3D_RS_POINTSCALE_B = 23, /* float */
SVGA3D_RS_POINTSCALE_C = 24, /* float */
SVGA3D_RS_FOGCOLOR = 25, /* SVGA3dColor */
SVGA3D_RS_AMBIENT = 26, /* SVGA3dColor */
SVGA3D_RS_CLIPPLANEENABLE = 27, /* SVGA3dClipPlanes */
SVGA3D_RS_FOGMODE = 28, /* SVGA3dFogMode */
SVGA3D_RS_FILLMODE = 29, /* SVGA3dFillMode */
SVGA3D_RS_SHADEMODE = 30, /* SVGA3dShadeMode */
SVGA3D_RS_LINEPATTERN = 31, /* SVGA3dLinePattern */
SVGA3D_RS_SRCBLEND = 32, /* SVGA3dBlendOp */
SVGA3D_RS_DSTBLEND = 33, /* SVGA3dBlendOp */
SVGA3D_RS_BLENDEQUATION = 34, /* SVGA3dBlendEquation */
SVGA3D_RS_CULLMODE = 35, /* SVGA3dFace */
SVGA3D_RS_ZFUNC = 36, /* SVGA3dCmpFunc */
SVGA3D_RS_ALPHAFUNC = 37, /* SVGA3dCmpFunc */
SVGA3D_RS_STENCILFUNC = 38, /* SVGA3dCmpFunc */
SVGA3D_RS_STENCILFAIL = 39, /* SVGA3dStencilOp */
SVGA3D_RS_STENCILZFAIL = 40, /* SVGA3dStencilOp */
SVGA3D_RS_STENCILPASS = 41, /* SVGA3dStencilOp */
SVGA3D_RS_ALPHAREF = 42, /* float (0.0 .. 1.0) */
SVGA3D_RS_FRONTWINDING = 43, /* SVGA3dFrontWinding */
SVGA3D_RS_COORDINATETYPE = 44, /* SVGA3dCoordinateType */
SVGA3D_RS_ZBIAS = 45, /* float */
SVGA3D_RS_RANGEFOGENABLE = 46, /* SVGA3dBool */
SVGA3D_RS_COLORWRITEENABLE = 47, /* SVGA3dColorMask */
SVGA3D_RS_VERTEXMATERIALENABLE = 48, /* SVGA3dBool */
SVGA3D_RS_DIFFUSEMATERIALSOURCE = 49, /* SVGA3dVertexMaterial */
SVGA3D_RS_SPECULARMATERIALSOURCE = 50, /* SVGA3dVertexMaterial */
SVGA3D_RS_AMBIENTMATERIALSOURCE = 51, /* SVGA3dVertexMaterial */
SVGA3D_RS_EMISSIVEMATERIALSOURCE = 52, /* SVGA3dVertexMaterial */
SVGA3D_RS_TEXTUREFACTOR = 53, /* SVGA3dColor */
SVGA3D_RS_LOCALVIEWER = 54, /* SVGA3dBool */
SVGA3D_RS_SCISSORTESTENABLE = 55, /* SVGA3dBool */
SVGA3D_RS_BLENDCOLOR = 56, /* SVGA3dColor */
SVGA3D_RS_STENCILENABLE2SIDED = 57, /* SVGA3dBool */
SVGA3D_RS_CCWSTENCILFUNC = 58, /* SVGA3dCmpFunc */
SVGA3D_RS_CCWSTENCILFAIL = 59, /* SVGA3dStencilOp */
SVGA3D_RS_CCWSTENCILZFAIL = 60, /* SVGA3dStencilOp */
SVGA3D_RS_CCWSTENCILPASS = 61, /* SVGA3dStencilOp */
SVGA3D_RS_VERTEXBLEND = 62, /* SVGA3dVertexBlendFlags */
SVGA3D_RS_SLOPESCALEDEPTHBIAS = 63, /* float */
SVGA3D_RS_DEPTHBIAS = 64, /* float */
/*
* Output Gamma Level
*
* Output gamma effects the gamma curve of colors that are output from the
* rendering pipeline. A value of 1.0 specifies a linear color space. If the
* value is <= 0.0, gamma correction is ignored and linear color space is
* used.
*/
SVGA3D_RS_OUTPUTGAMMA = 65, /* float */
SVGA3D_RS_ZVISIBLE = 66, /* SVGA3dBool */
SVGA3D_RS_LASTPIXEL = 67, /* SVGA3dBool */
SVGA3D_RS_CLIPPING = 68, /* SVGA3dBool */
SVGA3D_RS_WRAP0 = 69, /* SVGA3dWrapFlags */
SVGA3D_RS_WRAP1 = 70, /* SVGA3dWrapFlags */
SVGA3D_RS_WRAP2 = 71, /* SVGA3dWrapFlags */
SVGA3D_RS_WRAP3 = 72, /* SVGA3dWrapFlags */
SVGA3D_RS_WRAP4 = 73, /* SVGA3dWrapFlags */
SVGA3D_RS_WRAP5 = 74, /* SVGA3dWrapFlags */
SVGA3D_RS_WRAP6 = 75, /* SVGA3dWrapFlags */
SVGA3D_RS_WRAP7 = 76, /* SVGA3dWrapFlags */
SVGA3D_RS_WRAP8 = 77, /* SVGA3dWrapFlags */
SVGA3D_RS_WRAP9 = 78, /* SVGA3dWrapFlags */
SVGA3D_RS_WRAP10 = 79, /* SVGA3dWrapFlags */
SVGA3D_RS_WRAP11 = 80, /* SVGA3dWrapFlags */
SVGA3D_RS_WRAP12 = 81, /* SVGA3dWrapFlags */
SVGA3D_RS_WRAP13 = 82, /* SVGA3dWrapFlags */
SVGA3D_RS_WRAP14 = 83, /* SVGA3dWrapFlags */
SVGA3D_RS_WRAP15 = 84, /* SVGA3dWrapFlags */
SVGA3D_RS_MULTISAMPLEANTIALIAS = 85, /* SVGA3dBool */
SVGA3D_RS_MULTISAMPLEMASK = 86, /* uint32 */
SVGA3D_RS_INDEXEDVERTEXBLENDENABLE = 87, /* SVGA3dBool */
SVGA3D_RS_TWEENFACTOR = 88, /* float */
SVGA3D_RS_ANTIALIASEDLINEENABLE = 89, /* SVGA3dBool */
SVGA3D_RS_COLORWRITEENABLE1 = 90, /* SVGA3dColorMask */
SVGA3D_RS_COLORWRITEENABLE2 = 91, /* SVGA3dColorMask */
SVGA3D_RS_COLORWRITEENABLE3 = 92, /* SVGA3dColorMask */
SVGA3D_RS_SEPARATEALPHABLENDENABLE = 93, /* SVGA3dBool */
SVGA3D_RS_SRCBLENDALPHA = 94, /* SVGA3dBlendOp */
SVGA3D_RS_DSTBLENDALPHA = 95, /* SVGA3dBlendOp */
SVGA3D_RS_BLENDEQUATIONALPHA = 96, /* SVGA3dBlendEquation */
SVGA3D_RS_TRANSPARENCYANTIALIAS = 97, /* SVGA3dTransparencyAntialiasType */
SVGA3D_RS_LINEWIDTH = 98, /* float */
SVGA3D_RS_MAX
} SVGA3dRenderStateName;
typedef enum {
SVGA3D_TRANSPARENCYANTIALIAS_NORMAL = 0,
SVGA3D_TRANSPARENCYANTIALIAS_ALPHATOCOVERAGE = 1,
SVGA3D_TRANSPARENCYANTIALIAS_SUPERSAMPLE = 2,
SVGA3D_TRANSPARENCYANTIALIAS_MAX
} SVGA3dTransparencyAntialiasType;
typedef enum {
SVGA3D_VERTEXMATERIAL_NONE = 0, /* Use the value in the current material */
SVGA3D_VERTEXMATERIAL_DIFFUSE = 1, /* Use the value in the diffuse component */
SVGA3D_VERTEXMATERIAL_SPECULAR = 2, /* Use the value in the specular component */
SVGA3D_VERTEXMATERIAL_MAX = 3,
} SVGA3dVertexMaterial;
typedef enum {
SVGA3D_FILLMODE_INVALID = 0,
SVGA3D_FILLMODE_MIN = 1,
SVGA3D_FILLMODE_POINT = 1,
SVGA3D_FILLMODE_LINE = 2,
SVGA3D_FILLMODE_FILL = 3,
SVGA3D_FILLMODE_MAX
} SVGA3dFillModeType;
typedef
#include "vmware_pack_begin.h"
union {
struct {
uint16 mode; /* SVGA3dFillModeType */
uint16 face; /* SVGA3dFace */
};
uint32 uintValue;
}
#include "vmware_pack_end.h"
SVGA3dFillMode;
typedef enum {
SVGA3D_SHADEMODE_INVALID = 0,
SVGA3D_SHADEMODE_FLAT = 1,
SVGA3D_SHADEMODE_SMOOTH = 2,
SVGA3D_SHADEMODE_PHONG = 3, /* Not supported */
SVGA3D_SHADEMODE_MAX
} SVGA3dShadeMode;
typedef
#include "vmware_pack_begin.h"
union {
struct {
uint16 repeat;
uint16 pattern;
};
uint32 uintValue;
}
#include "vmware_pack_end.h"
SVGA3dLinePattern;
typedef enum {
SVGA3D_BLENDOP_INVALID = 0,
SVGA3D_BLENDOP_MIN = 1,
SVGA3D_BLENDOP_ZERO = 1,
SVGA3D_BLENDOP_ONE = 2,
SVGA3D_BLENDOP_SRCCOLOR = 3,
SVGA3D_BLENDOP_INVSRCCOLOR = 4,
SVGA3D_BLENDOP_SRCALPHA = 5,
SVGA3D_BLENDOP_INVSRCALPHA = 6,
SVGA3D_BLENDOP_DESTALPHA = 7,
SVGA3D_BLENDOP_INVDESTALPHA = 8,
SVGA3D_BLENDOP_DESTCOLOR = 9,
SVGA3D_BLENDOP_INVDESTCOLOR = 10,
SVGA3D_BLENDOP_SRCALPHASAT = 11,
SVGA3D_BLENDOP_BLENDFACTOR = 12,
SVGA3D_BLENDOP_INVBLENDFACTOR = 13,
SVGA3D_BLENDOP_SRC1COLOR = 14,
SVGA3D_BLENDOP_INVSRC1COLOR = 15,
SVGA3D_BLENDOP_SRC1ALPHA = 16,
SVGA3D_BLENDOP_INVSRC1ALPHA = 17,
SVGA3D_BLENDOP_MAX
} SVGA3dBlendOp;
typedef enum {
SVGA3D_BLENDEQ_INVALID = 0,
SVGA3D_BLENDEQ_MIN = 1,
SVGA3D_BLENDEQ_ADD = 1,
SVGA3D_BLENDEQ_SUBTRACT = 2,
SVGA3D_BLENDEQ_REVSUBTRACT = 3,
SVGA3D_BLENDEQ_MINIMUM = 4,
SVGA3D_BLENDEQ_MAXIMUM = 5,
SVGA3D_BLENDEQ_MAX
} SVGA3dBlendEquation;
typedef enum {
SVGA3D_FRONTWINDING_INVALID = 0,
SVGA3D_FRONTWINDING_CW = 1,
SVGA3D_FRONTWINDING_CCW = 2,
SVGA3D_FRONTWINDING_MAX
} SVGA3dFrontWinding;
typedef enum {
SVGA3D_FACE_INVALID = 0,
SVGA3D_FACE_NONE = 1,
SVGA3D_FACE_MIN = 1,
SVGA3D_FACE_FRONT = 2,
SVGA3D_FACE_BACK = 3,
SVGA3D_FACE_FRONT_BACK = 4,
SVGA3D_FACE_MAX
} SVGA3dFace;
/*
* The order and the values should not be changed
*/
typedef enum {
SVGA3D_CMP_INVALID = 0,
SVGA3D_CMP_NEVER = 1,
SVGA3D_CMP_LESS = 2,
SVGA3D_CMP_EQUAL = 3,
SVGA3D_CMP_LESSEQUAL = 4,
SVGA3D_CMP_GREATER = 5,
SVGA3D_CMP_NOTEQUAL = 6,
SVGA3D_CMP_GREATEREQUAL = 7,
SVGA3D_CMP_ALWAYS = 8,
SVGA3D_CMP_MAX
} SVGA3dCmpFunc;
/*
* SVGA3D_FOGFUNC_* specifies the fog equation, or PER_VERTEX which allows
* the fog factor to be specified in the alpha component of the specular
* (a.k.a. secondary) vertex color.
*/
typedef enum {
SVGA3D_FOGFUNC_INVALID = 0,
SVGA3D_FOGFUNC_EXP = 1,
SVGA3D_FOGFUNC_EXP2 = 2,
SVGA3D_FOGFUNC_LINEAR = 3,
SVGA3D_FOGFUNC_PER_VERTEX = 4
} SVGA3dFogFunction;
/*
* SVGA3D_FOGTYPE_* specifies if fog factors are computed on a per-vertex
* or per-pixel basis.
*/
typedef enum {
SVGA3D_FOGTYPE_INVALID = 0,
SVGA3D_FOGTYPE_VERTEX = 1,
SVGA3D_FOGTYPE_PIXEL = 2,
SVGA3D_FOGTYPE_MAX = 3
} SVGA3dFogType;
/*
* SVGA3D_FOGBASE_* selects depth or range-based fog. Depth-based fog is
* computed using the eye Z value of each pixel (or vertex), whereas range-
* based fog is computed using the actual distance (range) to the eye.
*/
typedef enum {
SVGA3D_FOGBASE_INVALID = 0,
SVGA3D_FOGBASE_DEPTHBASED = 1,
SVGA3D_FOGBASE_RANGEBASED = 2,
SVGA3D_FOGBASE_MAX = 3
} SVGA3dFogBase;
typedef enum {
SVGA3D_STENCILOP_INVALID = 0,
SVGA3D_STENCILOP_MIN = 1,
SVGA3D_STENCILOP_KEEP = 1,
SVGA3D_STENCILOP_ZERO = 2,
SVGA3D_STENCILOP_REPLACE = 3,
SVGA3D_STENCILOP_INCRSAT = 4,
SVGA3D_STENCILOP_DECRSAT = 5,
SVGA3D_STENCILOP_INVERT = 6,
SVGA3D_STENCILOP_INCR = 7,
SVGA3D_STENCILOP_DECR = 8,
SVGA3D_STENCILOP_MAX
} SVGA3dStencilOp;
typedef enum {
SVGA3D_CLIPPLANE_0 = (1 << 0),
SVGA3D_CLIPPLANE_1 = (1 << 1),
SVGA3D_CLIPPLANE_2 = (1 << 2),
SVGA3D_CLIPPLANE_3 = (1 << 3),
SVGA3D_CLIPPLANE_4 = (1 << 4),
SVGA3D_CLIPPLANE_5 = (1 << 5),
} SVGA3dClipPlanes;
typedef enum {
SVGA3D_CLEAR_COLOR = 0x1,
SVGA3D_CLEAR_DEPTH = 0x2,
SVGA3D_CLEAR_STENCIL = 0x4,
/*
* Hint only, must be used together with SVGA3D_CLEAR_COLOR. If
* SVGA3D_CLEAR_DEPTH or SVGA3D_CLEAR_STENCIL bit is set, this
* bit will be ignored.
*/
SVGA3D_CLEAR_COLORFILL = 0x8
} SVGA3dClearFlag;
typedef enum {
SVGA3D_RT_DEPTH = 0,
SVGA3D_RT_MIN = 0,
SVGA3D_RT_STENCIL = 1,
SVGA3D_RT_COLOR0 = 2,
SVGA3D_RT_COLOR1 = 3,
SVGA3D_RT_COLOR2 = 4,
SVGA3D_RT_COLOR3 = 5,
SVGA3D_RT_COLOR4 = 6,
SVGA3D_RT_COLOR5 = 7,
SVGA3D_RT_COLOR6 = 8,
SVGA3D_RT_COLOR7 = 9,
SVGA3D_RT_MAX,
SVGA3D_RT_INVALID = ((uint32)-1),
} SVGA3dRenderTargetType;
#define SVGA3D_MAX_RT_COLOR (SVGA3D_RT_COLOR7 - SVGA3D_RT_COLOR0 + 1)
typedef
#include "vmware_pack_begin.h"
union {
struct {
uint32 red : 1;
uint32 green : 1;
uint32 blue : 1;
uint32 alpha : 1;
};
uint32 uintValue;
}
#include "vmware_pack_end.h"
SVGA3dColorMask;
typedef enum {
SVGA3D_VBLEND_DISABLE = 0,
SVGA3D_VBLEND_1WEIGHT = 1,
SVGA3D_VBLEND_2WEIGHT = 2,
SVGA3D_VBLEND_3WEIGHT = 3,
SVGA3D_VBLEND_MAX = 4,
} SVGA3dVertexBlendFlags;
typedef enum {
SVGA3D_WRAPCOORD_0 = 1 << 0,
SVGA3D_WRAPCOORD_1 = 1 << 1,
SVGA3D_WRAPCOORD_2 = 1 << 2,
SVGA3D_WRAPCOORD_3 = 1 << 3,
SVGA3D_WRAPCOORD_ALL = 0xF,
} SVGA3dWrapFlags;
/*
* SVGA_3D_CMD_TEXTURESTATE Types. All value types
* must fit in a uint32.
*/
typedef enum {
SVGA3D_TS_INVALID = 0,
SVGA3D_TS_MIN = 1,
SVGA3D_TS_BIND_TEXTURE = 1, /* SVGA3dSurfaceId */
SVGA3D_TS_COLOROP = 2, /* SVGA3dTextureCombiner */
SVGA3D_TS_COLORARG1 = 3, /* SVGA3dTextureArgData */
SVGA3D_TS_COLORARG2 = 4, /* SVGA3dTextureArgData */
SVGA3D_TS_ALPHAOP = 5, /* SVGA3dTextureCombiner */
SVGA3D_TS_ALPHAARG1 = 6, /* SVGA3dTextureArgData */
SVGA3D_TS_ALPHAARG2 = 7, /* SVGA3dTextureArgData */
SVGA3D_TS_ADDRESSU = 8, /* SVGA3dTextureAddress */
SVGA3D_TS_ADDRESSV = 9, /* SVGA3dTextureAddress */
SVGA3D_TS_MIPFILTER = 10, /* SVGA3dTextureFilter */
SVGA3D_TS_MAGFILTER = 11, /* SVGA3dTextureFilter */
SVGA3D_TS_MINFILTER = 12, /* SVGA3dTextureFilter */
SVGA3D_TS_BORDERCOLOR = 13, /* SVGA3dColor */
SVGA3D_TS_TEXCOORDINDEX = 14, /* uint32 */
SVGA3D_TS_TEXTURETRANSFORMFLAGS = 15, /* SVGA3dTexTransformFlags */
SVGA3D_TS_TEXCOORDGEN = 16, /* SVGA3dTextureCoordGen */
SVGA3D_TS_BUMPENVMAT00 = 17, /* float */
SVGA3D_TS_BUMPENVMAT01 = 18, /* float */
SVGA3D_TS_BUMPENVMAT10 = 19, /* float */
SVGA3D_TS_BUMPENVMAT11 = 20, /* float */
SVGA3D_TS_TEXTURE_MIPMAP_LEVEL = 21, /* uint32 */
SVGA3D_TS_TEXTURE_LOD_BIAS = 22, /* float */
SVGA3D_TS_TEXTURE_ANISOTROPIC_LEVEL = 23, /* uint32 */
SVGA3D_TS_ADDRESSW = 24, /* SVGA3dTextureAddress */
/*
* Sampler Gamma Level
*
* Sampler gamma effects the color of samples taken from the sampler. A
* value of 1.0 will produce linear samples. If the value is <= 0.0 the
* gamma value is ignored and a linear space is used.
*/
SVGA3D_TS_GAMMA = 25, /* float */
SVGA3D_TS_BUMPENVLSCALE = 26, /* float */
SVGA3D_TS_BUMPENVLOFFSET = 27, /* float */
SVGA3D_TS_COLORARG0 = 28, /* SVGA3dTextureArgData */
SVGA3D_TS_ALPHAARG0 = 29, /* SVGA3dTextureArgData */
SVGA3D_TS_PREGB_MAX = 30, /* Max value before GBObjects */
SVGA3D_TS_CONSTANT = 30, /* SVGA3dColor */
SVGA3D_TS_COLOR_KEY_ENABLE = 31, /* SVGA3dBool */
SVGA3D_TS_COLOR_KEY = 32, /* SVGA3dColor */
SVGA3D_TS_MAX
} SVGA3dTextureStateName;
typedef enum {
SVGA3D_TC_INVALID = 0,
SVGA3D_TC_DISABLE = 1,
SVGA3D_TC_SELECTARG1 = 2,
SVGA3D_TC_SELECTARG2 = 3,
SVGA3D_TC_MODULATE = 4,
SVGA3D_TC_ADD = 5,
SVGA3D_TC_ADDSIGNED = 6,
SVGA3D_TC_SUBTRACT = 7,
SVGA3D_TC_BLENDTEXTUREALPHA = 8,
SVGA3D_TC_BLENDDIFFUSEALPHA = 9,
SVGA3D_TC_BLENDCURRENTALPHA = 10,
SVGA3D_TC_BLENDFACTORALPHA = 11,
SVGA3D_TC_MODULATE2X = 12,
SVGA3D_TC_MODULATE4X = 13,
SVGA3D_TC_DSDT = 14,
SVGA3D_TC_DOTPRODUCT3 = 15,
SVGA3D_TC_BLENDTEXTUREALPHAPM = 16,
SVGA3D_TC_ADDSIGNED2X = 17,
SVGA3D_TC_ADDSMOOTH = 18,
SVGA3D_TC_PREMODULATE = 19,
SVGA3D_TC_MODULATEALPHA_ADDCOLOR = 20,
SVGA3D_TC_MODULATECOLOR_ADDALPHA = 21,
SVGA3D_TC_MODULATEINVALPHA_ADDCOLOR = 22,
SVGA3D_TC_MODULATEINVCOLOR_ADDALPHA = 23,
SVGA3D_TC_BUMPENVMAPLUMINANCE = 24,
SVGA3D_TC_MULTIPLYADD = 25,
SVGA3D_TC_LERP = 26,
SVGA3D_TC_MAX
} SVGA3dTextureCombiner;
#define SVGA3D_TC_CAP_BIT(svga3d_tc_op) (svga3d_tc_op ? (1 << (svga3d_tc_op - 1)) : 0)
typedef enum {
SVGA3D_TEX_ADDRESS_INVALID = 0,
SVGA3D_TEX_ADDRESS_MIN = 1,
SVGA3D_TEX_ADDRESS_WRAP = 1,
SVGA3D_TEX_ADDRESS_MIRROR = 2,
SVGA3D_TEX_ADDRESS_CLAMP = 3,
SVGA3D_TEX_ADDRESS_BORDER = 4,
SVGA3D_TEX_ADDRESS_MIRRORONCE = 5,
SVGA3D_TEX_ADDRESS_EDGE = 6,
SVGA3D_TEX_ADDRESS_MAX
} SVGA3dTextureAddress;
/*
* SVGA3D_TEX_FILTER_NONE as the minification filter means mipmapping is
* disabled, and the rasterizer should use the magnification filter instead.
*/
typedef enum {
SVGA3D_TEX_FILTER_NONE = 0,
SVGA3D_TEX_FILTER_MIN = 0,
SVGA3D_TEX_FILTER_NEAREST = 1,
SVGA3D_TEX_FILTER_LINEAR = 2,
SVGA3D_TEX_FILTER_ANISOTROPIC = 3,
SVGA3D_TEX_FILTER_FLATCUBIC = 4, // Deprecated, not implemented
SVGA3D_TEX_FILTER_GAUSSIANCUBIC = 5, // Deprecated, not implemented
SVGA3D_TEX_FILTER_PYRAMIDALQUAD = 6, // Not currently implemented
SVGA3D_TEX_FILTER_GAUSSIANQUAD = 7, // Not currently implemented
SVGA3D_TEX_FILTER_MAX
} SVGA3dTextureFilter;
typedef enum {
SVGA3D_TEX_TRANSFORM_OFF = 0,
SVGA3D_TEX_TRANSFORM_S = (1 << 0),
SVGA3D_TEX_TRANSFORM_T = (1 << 1),
SVGA3D_TEX_TRANSFORM_R = (1 << 2),
SVGA3D_TEX_TRANSFORM_Q = (1 << 3),
SVGA3D_TEX_PROJECTED = (1 << 15),
} SVGA3dTexTransformFlags;
typedef enum {
SVGA3D_TEXCOORD_GEN_OFF = 0,
SVGA3D_TEXCOORD_GEN_EYE_POSITION = 1,
SVGA3D_TEXCOORD_GEN_EYE_NORMAL = 2,
SVGA3D_TEXCOORD_GEN_REFLECTIONVECTOR = 3,
SVGA3D_TEXCOORD_GEN_SPHERE = 4,
SVGA3D_TEXCOORD_GEN_MAX
} SVGA3dTextureCoordGen;
/*
* Texture argument constants for texture combiner
*/
typedef enum {
SVGA3D_TA_INVALID = 0,
SVGA3D_TA_TFACTOR = 1,
SVGA3D_TA_PREVIOUS = 2,
SVGA3D_TA_DIFFUSE = 3,
SVGA3D_TA_TEXTURE = 4,
SVGA3D_TA_SPECULAR = 5,
SVGA3D_TA_CONSTANT = 6,
SVGA3D_TA_MAX
} SVGA3dTextureArgData;
#define SVGA3D_TM_MASK_LEN 4
/* Modifiers for texture argument constants defined above. */
typedef enum {
SVGA3D_TM_NONE = 0,
SVGA3D_TM_ALPHA = (1 << SVGA3D_TM_MASK_LEN),
SVGA3D_TM_ONE_MINUS = (2 << SVGA3D_TM_MASK_LEN),
} SVGA3dTextureArgModifier;
/*
* Vertex declarations
*
* Notes:
*
* SVGA3D_DECLUSAGE_POSITIONT is for pre-transformed vertices. If you
* draw with any POSITIONT vertex arrays, the programmable vertex
* pipeline will be implicitly disabled. Drawing will take place as if
* no vertex shader was bound.
*/
typedef enum {
SVGA3D_DECLUSAGE_POSITION = 0,
SVGA3D_DECLUSAGE_BLENDWEIGHT, // 1
SVGA3D_DECLUSAGE_BLENDINDICES, // 2
SVGA3D_DECLUSAGE_NORMAL, // 3
SVGA3D_DECLUSAGE_PSIZE, // 4
SVGA3D_DECLUSAGE_TEXCOORD, // 5
SVGA3D_DECLUSAGE_TANGENT, // 6
SVGA3D_DECLUSAGE_BINORMAL, // 7
SVGA3D_DECLUSAGE_TESSFACTOR, // 8
SVGA3D_DECLUSAGE_POSITIONT, // 9
SVGA3D_DECLUSAGE_COLOR, // 10
SVGA3D_DECLUSAGE_FOG, // 11
SVGA3D_DECLUSAGE_DEPTH, // 12
SVGA3D_DECLUSAGE_SAMPLE, // 13
SVGA3D_DECLUSAGE_MAX
} SVGA3dDeclUsage;
typedef enum {
SVGA3D_DECLMETHOD_DEFAULT = 0,
SVGA3D_DECLMETHOD_PARTIALU,
SVGA3D_DECLMETHOD_PARTIALV,
SVGA3D_DECLMETHOD_CROSSUV, // Normal
SVGA3D_DECLMETHOD_UV,
SVGA3D_DECLMETHOD_LOOKUP, // Lookup a displacement map
SVGA3D_DECLMETHOD_LOOKUPPRESAMPLED, // Lookup a pre-sampled displacement map
} SVGA3dDeclMethod;
typedef enum {
SVGA3D_DECLTYPE_FLOAT1 = 0,
SVGA3D_DECLTYPE_FLOAT2 = 1,
SVGA3D_DECLTYPE_FLOAT3 = 2,
SVGA3D_DECLTYPE_FLOAT4 = 3,
SVGA3D_DECLTYPE_D3DCOLOR = 4,
SVGA3D_DECLTYPE_UBYTE4 = 5,
SVGA3D_DECLTYPE_SHORT2 = 6,
SVGA3D_DECLTYPE_SHORT4 = 7,
SVGA3D_DECLTYPE_UBYTE4N = 8,
SVGA3D_DECLTYPE_SHORT2N = 9,
SVGA3D_DECLTYPE_SHORT4N = 10,
SVGA3D_DECLTYPE_USHORT2N = 11,
SVGA3D_DECLTYPE_USHORT4N = 12,
SVGA3D_DECLTYPE_UDEC3 = 13,
SVGA3D_DECLTYPE_DEC3N = 14,
SVGA3D_DECLTYPE_FLOAT16_2 = 15,
SVGA3D_DECLTYPE_FLOAT16_4 = 16,
SVGA3D_DECLTYPE_MAX,
} SVGA3dDeclType;
/*
* This structure is used for the divisor for geometry instancing;
* it's a direct translation of the Direct3D equivalent.
*/
typedef union {
struct {
/*
* For index data, this number represents the number of instances to draw.
* For instance data, this number represents the number of
* instances/vertex in this stream
*/
uint32 count : 30;
/*
* This is 1 if this is supposed to be the data that is repeated for
* every instance.
*/
uint32 indexedData : 1;
/*
* This is 1 if this is supposed to be the per-instance data.
*/
uint32 instanceData : 1;
};
uint32 value;
} SVGA3dVertexDivisor;
typedef enum {
/*
* SVGA3D_PRIMITIVE_INVALID is a valid primitive type.
*
* List MIN second so debuggers will think INVALID is
* the correct name.
*/
SVGA3D_PRIMITIVE_INVALID = 0,
SVGA3D_PRIMITIVE_MIN = 0,
SVGA3D_PRIMITIVE_TRIANGLELIST = 1,
SVGA3D_PRIMITIVE_POINTLIST = 2,
SVGA3D_PRIMITIVE_LINELIST = 3,
SVGA3D_PRIMITIVE_LINESTRIP = 4,
SVGA3D_PRIMITIVE_TRIANGLESTRIP = 5,
SVGA3D_PRIMITIVE_TRIANGLEFAN = 6,
SVGA3D_PRIMITIVE_LINELIST_ADJ = 7,
SVGA3D_PRIMITIVE_PREDX_MAX = 7,
SVGA3D_PRIMITIVE_LINESTRIP_ADJ = 8,
SVGA3D_PRIMITIVE_TRIANGLELIST_ADJ = 9,
SVGA3D_PRIMITIVE_TRIANGLESTRIP_ADJ = 10,
SVGA3D_PRIMITIVE_MAX
} SVGA3dPrimitiveType;
typedef enum {
SVGA3D_COORDINATE_INVALID = 0,
SVGA3D_COORDINATE_LEFTHANDED = 1,
SVGA3D_COORDINATE_RIGHTHANDED = 2,
SVGA3D_COORDINATE_MAX
} SVGA3dCoordinateType;
typedef enum {
SVGA3D_TRANSFORM_INVALID = 0,
SVGA3D_TRANSFORM_WORLD = 1,
SVGA3D_TRANSFORM_MIN = 1,
SVGA3D_TRANSFORM_VIEW = 2,
SVGA3D_TRANSFORM_PROJECTION = 3,
SVGA3D_TRANSFORM_TEXTURE0 = 4,
SVGA3D_TRANSFORM_TEXTURE1 = 5,
SVGA3D_TRANSFORM_TEXTURE2 = 6,
SVGA3D_TRANSFORM_TEXTURE3 = 7,
SVGA3D_TRANSFORM_TEXTURE4 = 8,
SVGA3D_TRANSFORM_TEXTURE5 = 9,
SVGA3D_TRANSFORM_TEXTURE6 = 10,
SVGA3D_TRANSFORM_TEXTURE7 = 11,
SVGA3D_TRANSFORM_WORLD1 = 12,
SVGA3D_TRANSFORM_WORLD2 = 13,
SVGA3D_TRANSFORM_WORLD3 = 14,
SVGA3D_TRANSFORM_MAX
} SVGA3dTransformType;
typedef enum {
SVGA3D_LIGHTTYPE_INVALID = 0,
SVGA3D_LIGHTTYPE_MIN = 1,
SVGA3D_LIGHTTYPE_POINT = 1,
SVGA3D_LIGHTTYPE_SPOT1 = 2, /* 1-cone, in degrees */
SVGA3D_LIGHTTYPE_SPOT2 = 3, /* 2-cone, in radians */
SVGA3D_LIGHTTYPE_DIRECTIONAL = 4,
SVGA3D_LIGHTTYPE_MAX
} SVGA3dLightType;
typedef enum {
SVGA3D_CUBEFACE_POSX = 0,
SVGA3D_CUBEFACE_NEGX = 1,
SVGA3D_CUBEFACE_POSY = 2,
SVGA3D_CUBEFACE_NEGY = 3,
SVGA3D_CUBEFACE_POSZ = 4,
SVGA3D_CUBEFACE_NEGZ = 5,
} SVGA3dCubeFace;
typedef enum {
SVGA3D_SHADERTYPE_INVALID = 0,
SVGA3D_SHADERTYPE_MIN = 1,
SVGA3D_SHADERTYPE_VS = 1,
SVGA3D_SHADERTYPE_PS = 2,
SVGA3D_SHADERTYPE_MAX = 3,
SVGA3D_SHADERTYPE_PREDX_MAX = 3,
SVGA3D_SHADERTYPE_GS = 3,
SVGA3D_SHADERTYPE_DX_MAX = 4,
} SVGA3dShaderType;
#define SVGA3D_NUM_SHADERTYPE_PREDX \
(SVGA3D_SHADERTYPE_PREDX_MAX - SVGA3D_SHADERTYPE_MIN)
#define SVGA3D_NUM_SHADERTYPE_DX \
(SVGA3D_SHADERTYPE_DX_MAX - SVGA3D_SHADERTYPE_MIN)
typedef enum {
SVGA3D_CONST_TYPE_MIN = 0,
SVGA3D_CONST_TYPE_FLOAT = 0,
SVGA3D_CONST_TYPE_INT = 1,
SVGA3D_CONST_TYPE_BOOL = 2,
SVGA3D_CONST_TYPE_MAX = 3,
} SVGA3dShaderConstType;
/*
* Register limits for shader consts.
*/
#define SVGA3D_CONSTREG_MAX 256
#define SVGA3D_CONSTINTREG_MAX 16
#define SVGA3D_CONSTBOOLREG_MAX 16
typedef enum {
SVGA3D_STRETCH_BLT_POINT = 0,
SVGA3D_STRETCH_BLT_LINEAR = 1,
SVGA3D_STRETCH_BLT_MAX
} SVGA3dStretchBltMode;
typedef enum {
SVGA3D_QUERYTYPE_INVALID = ((uint32)-1),
SVGA3D_QUERYTYPE_MIN = 0,
SVGA3D_QUERYTYPE_OCCLUSION = 0,
SVGA3D_QUERYTYPE_EVENT = 1,
SVGA3D_QUERYTYPE_TIMESTAMP = 2,
SVGA3D_QUERYTYPE_TIMESTAMPDISJOINT = 3,
SVGA3D_QUERYTYPE_PIPELINESTATS = 4,
SVGA3D_QUERYTYPE_OCCLUSIONPREDICATE = 5,
SVGA3D_QUERYTYPE_STREAMOUTPUTSTATS = 6,
SVGA3D_QUERYTYPE_STREAMOVERFLOWPREDICATE = 7,
SVGA3D_QUERYTYPE_OCCLUSION64 = 8,
SVGA3D_QUERYTYPE_MAX
} SVGA3dQueryType;
#define SVGA3D_NUM_QUERYTYPE (SVGA3D_QUERYTYPE_MAX - SVGA3D_QUERYTYPE_MIN)
/*
* This is the maximum number of queries per context that can be active
* simultaneously between a beginQuery and endQuery.
*/
#define SVGA3D_MAX_QUERY_PER_CONTEXT 64
typedef enum {
SVGA3D_QUERYSTATE_PENDING = 0, /* Waiting on the host (set by guest) */
SVGA3D_QUERYSTATE_SUCCEEDED = 1, /* Completed successfully (set by host) */
SVGA3D_QUERYSTATE_FAILED = 2, /* Completed unsuccessfully (set by host) */
SVGA3D_QUERYSTATE_NEW = 3, /* Never submitted (For guest use only) */
} SVGA3dQueryState;
typedef enum {
SVGA3D_WRITE_HOST_VRAM = 1,
SVGA3D_READ_HOST_VRAM = 2,
} SVGA3dTransferType;
typedef enum {
SVGA3D_LOGICOP_INVALID = 0,
SVGA3D_LOGICOP_MIN = 1,
SVGA3D_LOGICOP_COPY = 1,
SVGA3D_LOGICOP_NOT = 2,
SVGA3D_LOGICOP_AND = 3,
SVGA3D_LOGICOP_OR = 4,
SVGA3D_LOGICOP_XOR = 5,
SVGA3D_LOGICOP_NXOR = 6,
SVGA3D_LOGICOP_ROP3MIN = 30, /* 7-29 are reserved for future logic ops. */
SVGA3D_LOGICOP_ROP3MAX = (SVGA3D_LOGICOP_ROP3MIN + 255),
SVGA3D_LOGICOP_MAX = (SVGA3D_LOGICOP_ROP3MAX + 1),
} SVGA3dLogicOp;
typedef
#include "vmware_pack_begin.h"
struct {
union {
struct {
uint16 function; // SVGA3dFogFunction
uint8 type; // SVGA3dFogType
uint8 base; // SVGA3dFogBase
};
uint32 uintValue;
};
}
#include "vmware_pack_end.h"
SVGA3dFogMode;
/*
* Uniquely identify one image (a 1D/2D/3D array) from a surface. This
* is a surface ID as well as face/mipmap indices.
*/
typedef
#include "vmware_pack_begin.h"
struct SVGA3dSurfaceImageId {
uint32 sid;
uint32 face;
uint32 mipmap;
}
#include "vmware_pack_end.h"
SVGA3dSurfaceImageId;
typedef
#include "vmware_pack_begin.h"
struct {
uint32 width;
uint32 height;
uint32 depth;
}
#include "vmware_pack_end.h"
SVGA3dSize;
/*
* Guest-backed objects definitions.
*/
typedef uint32 SVGAMobId;
typedef enum SVGAMobFormat {
SVGA3D_MOBFMT_INVALID = SVGA3D_INVALID_ID,
SVGA3D_MOBFMT_PTDEPTH_0 = 0,
SVGA3D_MOBFMT_MIN = 0,
SVGA3D_MOBFMT_PTDEPTH_1 = 1,
SVGA3D_MOBFMT_PTDEPTH_2 = 2,
SVGA3D_MOBFMT_RANGE = 3,
SVGA3D_MOBFMT_PTDEPTH64_0 = 4,
SVGA3D_MOBFMT_PTDEPTH64_1 = 5,
SVGA3D_MOBFMT_PTDEPTH64_2 = 6,
SVGA3D_MOBFMT_MAX,
} SVGAMobFormat;
#endif // _SVGA3D_TYPES_H_

/contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/svga/include/svga_escape.h
0,0 → 1,89
/**********************************************************
* Copyright 2007-2014 VMware, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
**********************************************************/
/*
* svga_escape.h --
*
* Definitions for our own (vendor-specific) SVGA Escape commands.
*/
#ifndef _SVGA_ESCAPE_H_
#define _SVGA_ESCAPE_H_
/*
* Namespace IDs for the escape command
*/
#define SVGA_ESCAPE_NSID_VMWARE 0x00000000
#define SVGA_ESCAPE_NSID_DEVEL 0xFFFFFFFF
/*
* Within SVGA_ESCAPE_NSID_VMWARE, we multiplex commands according to
* the first DWORD of escape data (after the nsID and size). As a
* guideline we're using the high word and low word as a major and
* minor command number, respectively.
*
* Major command number allocation:
*
* 0000: Reserved
* 0001: SVGA_ESCAPE_VMWARE_LOG (svga_binary_logger.h)
* 0002: SVGA_ESCAPE_VMWARE_VIDEO (svga_overlay.h)
* 0003: SVGA_ESCAPE_VMWARE_HINT (svga_escape.h)
*/
#define SVGA_ESCAPE_VMWARE_MAJOR_MASK 0xFFFF0000
/*
* SVGA Hint commands.
*
* These escapes let the SVGA driver provide optional information to
* he host about the state of the guest or guest applications. The
* host can use these hints to make user interface or performance
* decisions.
*
* Notes:
*
* - SVGA_ESCAPE_VMWARE_HINT_FULLSCREEN is deprecated for guests
* that use the SVGA Screen Object extension. Instead of sending
* this escape, use the SVGA_SCREEN_FULLSCREEN_HINT flag on your
* Screen Object.
*/
#define SVGA_ESCAPE_VMWARE_HINT 0x00030000
#define SVGA_ESCAPE_VMWARE_HINT_FULLSCREEN 0x00030001 // Deprecated
typedef
struct {
uint32 command;
uint32 fullscreen;
struct {
int32 x, y;
} monitorPosition;
} SVGAEscapeHintFullscreen;
#endif /* _SVGA_ESCAPE_H_ */

/contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/svga/include/svga_overlay.h
0,0 → 1,199
/**********************************************************
* Copyright 2007-2014 VMware, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
**********************************************************/
/*
* svga_overlay.h --
*
* Definitions for video-overlay support.
*/
#ifndef _SVGA_OVERLAY_H_
#define _SVGA_OVERLAY_H_
#include "svga_reg.h"
/*
* Video formats we support
*/
#define VMWARE_FOURCC_YV12 0x32315659 // 'Y' 'V' '1' '2'
#define VMWARE_FOURCC_YUY2 0x32595559 // 'Y' 'U' 'Y' '2'
#define VMWARE_FOURCC_UYVY 0x59565955 // 'U' 'Y' 'V' 'Y'
typedef enum {
SVGA_OVERLAY_FORMAT_INVALID = 0,
SVGA_OVERLAY_FORMAT_YV12 = VMWARE_FOURCC_YV12,
SVGA_OVERLAY_FORMAT_YUY2 = VMWARE_FOURCC_YUY2,
SVGA_OVERLAY_FORMAT_UYVY = VMWARE_FOURCC_UYVY,
} SVGAOverlayFormat;
#define SVGA_VIDEO_COLORKEY_MASK 0x00ffffff
#define SVGA_ESCAPE_VMWARE_VIDEO 0x00020000
#define SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS 0x00020001
/* FIFO escape layout:
* Type, Stream Id, (Register Id, Value) pairs */
#define SVGA_ESCAPE_VMWARE_VIDEO_FLUSH 0x00020002
/* FIFO escape layout:
* Type, Stream Id */
typedef
struct SVGAEscapeVideoSetRegs {
struct {
uint32 cmdType;
uint32 streamId;
} header;
// May include zero or more items.
struct {
uint32 registerId;
uint32 value;
} items[1];
} SVGAEscapeVideoSetRegs;
typedef
struct SVGAEscapeVideoFlush {
uint32 cmdType;
uint32 streamId;
} SVGAEscapeVideoFlush;
/*
* Struct definitions for the video overlay commands built on
* SVGAFifoCmdEscape.
*/
typedef
struct {
uint32 command;
uint32 overlay;
} SVGAFifoEscapeCmdVideoBase;
typedef
struct {
SVGAFifoEscapeCmdVideoBase videoCmd;
} SVGAFifoEscapeCmdVideoFlush;
typedef
struct {
SVGAFifoEscapeCmdVideoBase videoCmd;
struct {
uint32 regId;
uint32 value;
} items[1];
} SVGAFifoEscapeCmdVideoSetRegs;
typedef
struct {
SVGAFifoEscapeCmdVideoBase videoCmd;
struct {
uint32 regId;
uint32 value;
} items[SVGA_VIDEO_NUM_REGS];
} SVGAFifoEscapeCmdVideoSetAllRegs;
/*
*----------------------------------------------------------------------
*
* VMwareVideoGetAttributes --
*
* Computes the size, pitches and offsets for YUV frames.
*
* Results:
* TRUE on success; otherwise FALSE on failure.
*
* Side effects:
* Pitches and offsets for the given YUV frame are put in 'pitches'
* and 'offsets' respectively. They are both optional though.
*
*----------------------------------------------------------------------
*/
static INLINE Bool
VMwareVideoGetAttributes(const SVGAOverlayFormat format, // IN
uint32 *width, // IN / OUT
uint32 *height, // IN / OUT
uint32 *size, // OUT
uint32 *pitches, // OUT (optional)
uint32 *offsets) // OUT (optional)
{
int tmp;
*width = (*width + 1) & ~1;
if (offsets) {
offsets[0] = 0;
}
switch (format) {
case VMWARE_FOURCC_YV12:
*height = (*height + 1) & ~1;
*size = (*width) * (*height);
if (pitches) {
pitches[0] = *width;
}
if (offsets) {
offsets[1] = *size;
}
tmp = *width >> 1;
if (pitches) {
pitches[1] = pitches[2] = tmp;
}
tmp *= (*height >> 1);
*size += tmp;
if (offsets) {
offsets[2] = *size;
}
*size += tmp;
break;
case VMWARE_FOURCC_YUY2:
case VMWARE_FOURCC_UYVY:
*size = *width * 2;
if (pitches) {
pitches[0] = *size;
}
*size *= *height;
break;
default:
return FALSE;
}
return TRUE;
}
#endif // _SVGA_OVERLAY_H_

/contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/svga/include/svga_reg.h
0,0 → 1,1863
/**********************************************************
* Copyright 1998-2014 VMware, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
**********************************************************/
/*
* svga_reg.h --
*
* Virtual hardware definitions for the VMware SVGA II device.
*/
#ifndef _SVGA_REG_H_
#define _SVGA_REG_H_
#include "svga_types.h"
/*
* SVGA_REG_ENABLE bit definitions.
*/
typedef enum {
SVGA_REG_ENABLE_DISABLE = 0,
SVGA_REG_ENABLE_ENABLE = (1 << 0),
SVGA_REG_ENABLE_HIDE = (1 << 1),
} SvgaRegEnable;
/*
* Arbitrary and meaningless limits. Please ignore these when writing
* new drivers.
*/
#define SVGA_MAX_WIDTH 2560
#define SVGA_MAX_HEIGHT 1600
#define SVGA_MAX_BITS_PER_PIXEL 32
#define SVGA_MAX_DEPTH 24
#define SVGA_MAX_DISPLAYS 10
/*
* Legal values for the SVGA_REG_CURSOR_ON register in old-fashioned
* cursor bypass mode. This is still supported, but no new guest
* drivers should use it.
*/
#define SVGA_CURSOR_ON_HIDE 0x0 /* Must be 0 to maintain backward compatibility */
#define SVGA_CURSOR_ON_SHOW 0x1 /* Must be 1 to maintain backward compatibility */
#define SVGA_CURSOR_ON_REMOVE_FROM_FB 0x2 /* Remove the cursor from the framebuffer because we need to see what's under it */
#define SVGA_CURSOR_ON_RESTORE_TO_FB 0x3 /* Put the cursor back in the framebuffer so the user can see it */
/*
* The maximum framebuffer size that can traced for e.g. guests in VESA mode.
* The changeMap in the monitor is proportional to this number. Therefore, we'd
* like to keep it as small as possible to reduce monitor overhead (using
* SVGA_VRAM_MAX_SIZE for this increases the size of the shared area by over
* 4k!).
*
* NB: For compatibility reasons, this value must be greater than 0xff0000.
* See bug 335072.
*/
#define SVGA_FB_MAX_TRACEABLE_SIZE 0x1000000
#define SVGA_MAX_PSEUDOCOLOR_DEPTH 8
#define SVGA_MAX_PSEUDOCOLORS (1 << SVGA_MAX_PSEUDOCOLOR_DEPTH)
#define SVGA_NUM_PALETTE_REGS (3 * SVGA_MAX_PSEUDOCOLORS)
#define SVGA_MAGIC 0x900000UL
#define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
/* Version 2 let the address of the frame buffer be unsigned on Win32 */
#define SVGA_VERSION_2 2
#define SVGA_ID_2 SVGA_MAKE_ID(SVGA_VERSION_2)
/* Version 1 has new registers starting with SVGA_REG_CAPABILITIES so
PALETTE_BASE has moved */
#define SVGA_VERSION_1 1
#define SVGA_ID_1 SVGA_MAKE_ID(SVGA_VERSION_1)
/* Version 0 is the initial version */
#define SVGA_VERSION_0 0
#define SVGA_ID_0 SVGA_MAKE_ID(SVGA_VERSION_0)
/* "Invalid" value for all SVGA IDs. (Version ID, screen object ID, surface ID...) */
#define SVGA_ID_INVALID 0xFFFFFFFF
/* Port offsets, relative to BAR0 */
#define SVGA_INDEX_PORT 0x0
#define SVGA_VALUE_PORT 0x1
#define SVGA_BIOS_PORT 0x2
#define SVGA_IRQSTATUS_PORT 0x8
/*
* Interrupt source flags for IRQSTATUS_PORT and IRQMASK.
*
* Interrupts are only supported when the
* SVGA_CAP_IRQMASK capability is present.
*/
#define SVGA_IRQFLAG_ANY_FENCE 0x1 /* Any fence was passed */
#define SVGA_IRQFLAG_FIFO_PROGRESS 0x2 /* Made forward progress in the FIFO */
#define SVGA_IRQFLAG_FENCE_GOAL 0x4 /* SVGA_FIFO_FENCE_GOAL reached */
#define SVGA_IRQFLAG_COMMAND_BUFFER 0x8 /* Command buffer completed */
#define SVGA_IRQFLAG_ERROR 0x10 /* Error while processing commands */
/*
* Registers
*/
enum {
SVGA_REG_ID = 0,
SVGA_REG_ENABLE = 1,
SVGA_REG_WIDTH = 2,
SVGA_REG_HEIGHT = 3,
SVGA_REG_MAX_WIDTH = 4,
SVGA_REG_MAX_HEIGHT = 5,
SVGA_REG_DEPTH = 6,
SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */
SVGA_REG_PSEUDOCOLOR = 8,
SVGA_REG_RED_MASK = 9,
SVGA_REG_GREEN_MASK = 10,
SVGA_REG_BLUE_MASK = 11,
SVGA_REG_BYTES_PER_LINE = 12,
SVGA_REG_FB_START = 13, /* (Deprecated) */
SVGA_REG_FB_OFFSET = 14,
SVGA_REG_VRAM_SIZE = 15,
SVGA_REG_FB_SIZE = 16,
/* ID 0 implementation only had the above registers, then the palette */
SVGA_REG_ID_0_TOP = 17,
SVGA_REG_CAPABILITIES = 17,
SVGA_REG_MEM_START = 18, /* (Deprecated) */
SVGA_REG_MEM_SIZE = 19,
SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
SVGA_REG_SYNC = 21, /* See "FIFO Synchronization Registers" */
SVGA_REG_BUSY = 22, /* See "FIFO Synchronization Registers" */
SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */
SVGA_REG_CURSOR_ID = 24, /* (Deprecated) */
SVGA_REG_CURSOR_X = 25, /* (Deprecated) */
SVGA_REG_CURSOR_Y = 26, /* (Deprecated) */
SVGA_REG_CURSOR_ON = 27, /* (Deprecated) */
SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* (Deprecated) */
SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */
SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */
SVGA_REG_NUM_DISPLAYS = 31, /* (Deprecated) */
SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */
SVGA_REG_IRQMASK = 33, /* Interrupt mask */
/* Legacy multi-monitor support */
SVGA_REG_NUM_GUEST_DISPLAYS = 34,/* Number of guest displays in X/Y direction */
SVGA_REG_DISPLAY_ID = 35, /* Display ID for the following display attributes */
SVGA_REG_DISPLAY_IS_PRIMARY = 36,/* Whether this is a primary display */
SVGA_REG_DISPLAY_POSITION_X = 37,/* The display position x */
SVGA_REG_DISPLAY_POSITION_Y = 38,/* The display position y */
SVGA_REG_DISPLAY_WIDTH = 39, /* The display's width */
SVGA_REG_DISPLAY_HEIGHT = 40, /* The display's height */
/* See "Guest memory regions" below. */
SVGA_REG_GMR_ID = 41,
SVGA_REG_GMR_DESCRIPTOR = 42,
SVGA_REG_GMR_MAX_IDS = 43,
SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH = 44,
SVGA_REG_TRACES = 45, /* Enable trace-based updates even when FIFO is on */
SVGA_REG_GMRS_MAX_PAGES = 46, /* Maximum number of 4KB pages for all GMRs */
SVGA_REG_MEMORY_SIZE = 47, /* Total dedicated device memory excluding FIFO */
SVGA_REG_COMMAND_LOW = 48, /* Lower 32 bits and submits commands */
SVGA_REG_COMMAND_HIGH = 49, /* Upper 32 bits of command buffer PA */
SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM = 50, /* Max primary memory */
SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51, /* Suggested limit on mob mem */
SVGA_REG_DEV_CAP = 52, /* Write dev cap index, read value */
SVGA_REG_CMD_PREPEND_LOW = 53,
SVGA_REG_iCMD_PREPEND_HIGH = 54,
SVGA_REG_SCREENTARGET_MAX_WIDTH = 55,
SVGA_REG_SCREENTARGET_MAX_HEIGHT = 56,
SVGA_REG_MOB_MAX_SIZE = 57,
SVGA_REG_TOP = 58, /* Must be 1 more than the last register */
SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
/* Next 768 (== 256*3) registers exist for colormap */
SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + SVGA_NUM_PALETTE_REGS
/* Base of scratch registers */
/* Next reg[SVGA_REG_SCRATCH_SIZE] registers exist for scratch usage:
First 4 are reserved for VESA BIOS Extension; any remaining are for
the use of the current SVGA driver. */
};
/*
* Guest memory regions (GMRs):
*
* This is a new memory mapping feature available in SVGA devices
* which have the SVGA_CAP_GMR bit set. Previously, there were two
* fixed memory regions available with which to share data between the
* device and the driver: the FIFO ('MEM') and the framebuffer. GMRs
* are our name for an extensible way of providing arbitrary DMA
* buffers for use between the driver and the SVGA device. They are a
* new alternative to framebuffer memory, usable for both 2D and 3D
* graphics operations.
*
* Since GMR mapping must be done synchronously with guest CPU
* execution, we use a new pair of SVGA registers:
*
* SVGA_REG_GMR_ID --
*
* Read/write.
* This register holds the 32-bit ID (a small positive integer)
* of a GMR to create, delete, or redefine. Writing this register
* has no side-effects.
*
* SVGA_REG_GMR_DESCRIPTOR --
*
* Write-only.
* Writing this register will create, delete, or redefine the GMR
* specified by the above ID register. If this register is zero,
* the GMR is deleted. Any pointers into this GMR (including those
* currently being processed by FIFO commands) will be
* synchronously invalidated.
*
* If this register is nonzero, it must be the physical page
* number (PPN) of a data structure which describes the physical
* layout of the memory region this GMR should describe. The
* descriptor structure will be read synchronously by the SVGA
* device when this register is written. The descriptor need not
* remain allocated for the lifetime of the GMR.
*
* The guest driver should write SVGA_REG_GMR_ID first, then
* SVGA_REG_GMR_DESCRIPTOR.
*
* SVGA_REG_GMR_MAX_IDS --
*
* Read-only.
* The SVGA device may choose to support a maximum number of
* user-defined GMR IDs. This register holds the number of supported
* IDs. (The maximum supported ID plus 1)
*
* SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH --
*
* Read-only.
* The SVGA device may choose to put a limit on the total number
* of SVGAGuestMemDescriptor structures it will read when defining
* a single GMR.
*
* The descriptor structure is an array of SVGAGuestMemDescriptor
* structures. Each structure may do one of three things:
*
* - Terminate the GMR descriptor list.
* (ppn==0, numPages==0)
*
* - Add a PPN or range of PPNs to the GMR's virtual address space.
* (ppn != 0, numPages != 0)
*
* - Provide the PPN of the next SVGAGuestMemDescriptor, in order to
* support multi-page GMR descriptor tables without forcing the
* driver to allocate physically contiguous memory.
* (ppn != 0, numPages == 0)
*
* Note that each physical page of SVGAGuestMemDescriptor structures
* can describe at least 2MB of guest memory. If the driver needs to
* use more than one page of descriptor structures, it must use one of
* its SVGAGuestMemDescriptors to point to an additional page. The
* device will never automatically cross a page boundary.
*
* Once the driver has described a GMR, it is immediately available
* for use via any FIFO command that uses an SVGAGuestPtr structure.
* These pointers include a GMR identifier plus an offset into that
* GMR.
*
* The driver must check the SVGA_CAP_GMR bit before using the GMR
* registers.
*/
/*
* Special GMR IDs, allowing SVGAGuestPtrs to point to framebuffer
* memory as well. In the future, these IDs could even be used to
* allow legacy memory regions to be redefined by the guest as GMRs.
*
* Using the guest framebuffer (GFB) at BAR1 for general purpose DMA
* is being phased out. Please try to use user-defined GMRs whenever
* possible.
*/
#define SVGA_GMR_NULL ((uint32) -1)
#define SVGA_GMR_FRAMEBUFFER ((uint32) -2) // Guest Framebuffer (GFB)
typedef
struct SVGAGuestMemDescriptor {
uint32 ppn;
uint32 numPages;
} SVGAGuestMemDescriptor;
typedef
struct SVGAGuestPtr {
uint32 gmrId;
uint32 offset;
} SVGAGuestPtr;
/*
* Register based command buffers --
*
* Provide an SVGA device interface that allows the guest to submit
* command buffers to the SVGA device through an SVGA device register.
* The metadata for each command buffer is contained in the
* SVGACBHeader structure along with the return status codes.
*
* The SVGA device supports command buffers if
* SVGA_CAP_COMMAND_BUFFERS is set in the device caps register. The
* fifo must be enabled for command buffers to be submitted.
*
* Command buffers are submitted when the guest writing the 64 byte
* aligned physical address into the SVGA_REG_COMMAND_LOW and
* SVGA_REG_COMMAND_HIGH. SVGA_REG_COMMAND_HIGH contains the upper 32
* bits of the physical address. SVGA_REG_COMMAND_LOW contains the
* lower 32 bits of the physical address, since the command buffer
* headers are required to be 64 byte aligned the lower 6 bits are
* used for the SVGACBContext value. Writing to SVGA_REG_COMMAND_LOW
* submits the command buffer to the device and queues it for
* execution. The SVGA device supports at least
* SVGA_CB_MAX_QUEUED_PER_CONTEXT command buffers that can be queued
* per context and if that limit is reached the device will write the
* status SVGA_CB_STATUS_QUEUE_FULL to the status value of the command
* buffer header synchronously and not raise any IRQs.
*
* It is invalid to submit a command buffer without a valid physical
* address and results are undefined.
*
* The device guarantees that command buffers of size SVGA_CB_MAX_SIZE
* will be supported. If a larger command buffer is submitted results
* are unspecified and the device will either complete the command
* buffer or return an error.
*
* The device guarantees that any individual command in a command
* buffer can be up to SVGA_CB_MAX_COMMAND_SIZE in size which is
* enough to fit a 64x64 color-cursor definition. If the command is
* too large the device is allowed to process the command or return an
* error.
*
* The device context is a special SVGACBContext that allows for
* synchronous register like accesses with the flexibility of
* commands. There is a different command set defined by
* SVGADeviceContextCmdId. The commands in each command buffer is not
* allowed to straddle physical pages.
*/
#define SVGA_CB_MAX_SIZE (512 * 1024) // 512 KB
#define SVGA_CB_MAX_QUEUED_PER_CONTEXT 32
#define SVGA_CB_MAX_COMMAND_SIZE (32 * 1024) // 32 KB
#define SVGA_CB_CONTEXT_MASK 0x3f
typedef enum {
SVGA_CB_CONTEXT_DEVICE = 0x3f,
SVGA_CB_CONTEXT_0 = 0x0,
SVGA_CB_CONTEXT_MAX = 0x1,
} SVGACBContext;
typedef enum {
/*
* The guest is supposed to write SVGA_CB_STATUS_NONE to the status
* field before submitting the command buffer header, the host will
* change the value when it is done with the command buffer.
*/
SVGA_CB_STATUS_NONE = 0,
/*
* Written by the host when a command buffer completes successfully.
* The device raises an IRQ with SVGA_IRQFLAG_COMMAND_BUFFER unless
* the SVGA_CB_FLAG_NO_IRQ flag is set.
*/
SVGA_CB_STATUS_COMPLETED = 1,
/*
* Written by the host synchronously with the command buffer
* submission to indicate the command buffer was not submitted. No
* IRQ is raised.
*/
SVGA_CB_STATUS_QUEUE_FULL = 2,
/*
* Written by the host when an error was detected parsing a command
* in the command buffer, errorOffset is written to contain the
* offset to the first byte of the failing command. The device
* raises the IRQ with both SVGA_IRQFLAG_ERROR and
* SVGA_IRQFLAG_COMMAND_BUFFER. Some of the commands may have been
* processed.
*/
SVGA_CB_STATUS_COMMAND_ERROR = 3,
/*
* Written by the host if there is an error parsing the command
* buffer header. The device raises the IRQ with both
* SVGA_IRQFLAG_ERROR and SVGA_IRQFLAG_COMMAND_BUFFER. The device
* did not processes any of the command buffer.
*/
SVGA_CB_STATUS_CB_HEADER_ERROR = 4,
/*
* Written by the host if the guest requested the host to preempt
* the command buffer. The device will not raise any IRQs and the
* command buffer was not processed.
*/
SVGA_CB_STATUS_PREEMPTED = 5,
} SVGACBStatus;
typedef enum {
SVGA_CB_FLAG_NONE = 0,
SVGA_CB_FLAG_NO_IRQ = 1 << 0,
} SVGACBFlags;
typedef
struct {
volatile SVGACBStatus status;
volatile uint32 errorOffset;
uint64 id;
SVGACBFlags flags;
uint32 length;
union {
PA pa;
} ptr;
uint32 mustBeZero[8];
} SVGACBHeader;
typedef enum {
SVGA_DC_CMD_NOP = 0,
SVGA_DC_CMD_START_STOP_CONTEXT = 1,
SVGA_DC_CMD_PREEMPT = 2,
SVGA_DC_CMD_MAX = 3,
SVGA_DC_CMD_FORCE_UINT = MAX_UINT32,
} SVGADeviceContextCmdId;
typedef struct {
uint32 enable;
SVGACBContext context;
} SVGADCCmdStartStop;
/*
* SVGADCCmdPreempt --
*
* This command allows the guest to request that all command buffers
* on the specified context be preempted that can be. After execution
* of this command all command buffers that were preempted will
* already have SVGA_CB_STATUS_PREEMPTED written into the status
* field. The device might still be processing a command buffer,
* assuming execution of it started before the preemption request was
* received. Specifying the ignoreIDZero flag to TRUE will cause the
* device to not preempt command buffers with the id field in the
* command buffer header set to zero.
*/
typedef struct {
SVGACBContext context;
uint32 ignoreIDZero;
} SVGADCCmdPreempt;
/*
* SVGAGMRImageFormat --
*
* This is a packed representation of the source 2D image format
* for a GMR-to-screen blit. Currently it is defined as an encoding
* of the screen's color depth and bits-per-pixel, however, 16 bits
* are reserved for future use to identify other encodings (such as
* RGBA or higher-precision images).
*
* Currently supported formats:
*
* bpp depth Format Name
* --- ----- -----------
* 32 24 32-bit BGRX
* 24 24 24-bit BGR
* 16 16 RGB 5-6-5
* 16 15 RGB 5-5-5
*
*/
typedef struct SVGAGMRImageFormat {
union {
struct {
uint32 bitsPerPixel : 8;
uint32 colorDepth : 8;
uint32 reserved : 16; // Must be zero
};
uint32 value;
};
} SVGAGMRImageFormat;
typedef
struct SVGAGuestImage {
SVGAGuestPtr ptr;
/*
* A note on interpretation of pitch: This value of pitch is the
* number of bytes between vertically adjacent image
* blocks. Normally this is the number of bytes between the first
* pixel of two adjacent scanlines. With compressed textures,
* however, this may represent the number of bytes between
* compression blocks rather than between rows of pixels.
*
* XXX: Compressed textures currently must be tightly packed in guest memory.
*
* If the image is 1-dimensional, pitch is ignored.
*
* If 'pitch' is zero, the SVGA3D device calculates a pitch value
* assuming each row of blocks is tightly packed.
*/
uint32 pitch;
} SVGAGuestImage;
/*
* SVGAColorBGRX --
*
* A 24-bit color format (BGRX), which does not depend on the
* format of the legacy guest framebuffer (GFB) or the current
* GMRFB state.
*/
typedef struct SVGAColorBGRX {
union {
struct {
uint32 b : 8;
uint32 g : 8;
uint32 r : 8;
uint32 x : 8; // Unused
};
uint32 value;
};
} SVGAColorBGRX;
/*
* SVGASignedRect --
* SVGASignedPoint --
*
* Signed rectangle and point primitives. These are used by the new
* 2D primitives for drawing to Screen Objects, which can occupy a
* signed virtual coordinate space.
*
* SVGASignedRect specifies a half-open interval: the (left, top)
* pixel is part of the rectangle, but the (right, bottom) pixel is
* not.
*/
typedef
struct {
int32 left;
int32 top;
int32 right;
int32 bottom;
} SVGASignedRect;
typedef
struct {
int32 x;
int32 y;
} SVGASignedPoint;
/*
* SVGA Device Capabilities
*
* Note the holes in the bitfield. Missing bits have been deprecated,
* and must not be reused. Those capabilities will never be reported
* by new versions of the SVGA device.
*
* XXX: Add longer descriptions for each capability, including a list
* of the new features that each capability provides.
*
* SVGA_CAP_IRQMASK --
* Provides device interrupts. Adds device register SVGA_REG_IRQMASK
* to set interrupt mask and direct I/O port SVGA_IRQSTATUS_PORT to
* set/clear pending interrupts.
*
* SVGA_CAP_GMR --
* Provides synchronous mapping of guest memory regions (GMR).
* Adds device registers SVGA_REG_GMR_ID, SVGA_REG_GMR_DESCRIPTOR,
* SVGA_REG_GMR_MAX_IDS, and SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH.
*
* SVGA_CAP_TRACES --
* Allows framebuffer trace-based updates even when FIFO is enabled.
* Adds device register SVGA_REG_TRACES.
*
* SVGA_CAP_GMR2 --
* Provides asynchronous commands to define and remap guest memory
* regions. Adds device registers SVGA_REG_GMRS_MAX_PAGES and
* SVGA_REG_MEMORY_SIZE.
*
* SVGA_CAP_SCREEN_OBJECT_2 --
* Allow screen object support, and require backing stores from the
* guest for each screen object.
*
* SVGA_CAP_COMMAND_BUFFERS --
* Enable register based command buffer submission.
*
* SVGA_CAP_GBOBJECTS --
* Enable guest-backed objects and surfaces.
*
*/
#define SVGA_CAP_NONE 0x00000000
#define SVGA_CAP_RECT_COPY 0x00000002
#define SVGA_CAP_CURSOR 0x00000020
#define SVGA_CAP_CURSOR_BYPASS 0x00000040 // Legacy (Use Cursor Bypass 3 instead)
#define SVGA_CAP_CURSOR_BYPASS_2 0x00000080 // Legacy (Use Cursor Bypass 3 instead)
#define SVGA_CAP_8BIT_EMULATION 0x00000100
#define SVGA_CAP_ALPHA_CURSOR 0x00000200
#define SVGA_CAP_3D 0x00004000
#define SVGA_CAP_EXTENDED_FIFO 0x00008000
#define SVGA_CAP_MULTIMON 0x00010000 // Legacy multi-monitor support
#define SVGA_CAP_PITCHLOCK 0x00020000
#define SVGA_CAP_IRQMASK 0x00040000
#define SVGA_CAP_DISPLAY_TOPOLOGY 0x00080000 // Legacy multi-monitor support
#define SVGA_CAP_GMR 0x00100000
#define SVGA_CAP_TRACES 0x00200000
#define SVGA_CAP_GMR2 0x00400000
#define SVGA_CAP_SCREEN_OBJECT_2 0x00800000
#define SVGA_CAP_COMMAND_BUFFERS 0x01000000
#define SVGA_CAP_DEAD1 0x02000000
#define SVGA_CAP_CMD_BUFFERS_2 0x04000000
#define SVGA_CAP_GBOBJECTS 0x08000000
/*
* The Guest can optionally read some SVGA device capabilities through
* the backdoor with command BDOOR_CMD_GET_SVGA_CAPABILITIES before
* the SVGA device is initialized. The type of capability the guest
* is requesting from the SVGABackdoorCapType enum should be placed in
* the upper 16 bits of the backdoor command id (ECX). On success the
* the value of EBX will be set to BDOOR_MAGIC and EAX will be set to
* the requested capability. If the command is not supported then EBX
* will be left unchanged and EAX will be set to -1. Because it is
* possible that -1 is the value of the requested cap the correct way
* to check if the command was successful is to check if EBX was changed
* to BDOOR_MAGIC making sure to initialize the register to something
* else first.
*/
typedef enum {
SVGABackdoorCapDeviceCaps = 0,
SVGABackdoorCapFifoCaps = 1,
SVGABackdoorCap3dHWVersion = 2,
SVGABackdoorCapMax = 3,
} SVGABackdoorCapType;
/*
* FIFO register indices.
*
* The FIFO is a chunk of device memory mapped into guest physmem. It
* is always treated as 32-bit words.
*
* The guest driver gets to decide how to partition it between
* - FIFO registers (there are always at least 4, specifying where the
* following data area is and how much data it contains; there may be
* more registers following these, depending on the FIFO protocol
* version in use)
* - FIFO data, written by the guest and slurped out by the VMX.
* These indices are 32-bit word offsets into the FIFO.
*/
enum {
/*
* Block 1 (basic registers): The originally defined FIFO registers.
* These exist and are valid for all versions of the FIFO protocol.
*/
SVGA_FIFO_MIN = 0,
SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
SVGA_FIFO_NEXT_CMD,
SVGA_FIFO_STOP,
/*
* Block 2 (extended registers): Mandatory registers for the extended
* FIFO. These exist if the SVGA caps register includes
* SVGA_CAP_EXTENDED_FIFO; some of them are valid only if their
* associated capability bit is enabled.
*
* Note that when originally defined, SVGA_CAP_EXTENDED_FIFO implied
* support only for (FIFO registers) CAPABILITIES, FLAGS, and FENCE.
* This means that the guest has to test individually (in most cases
* using FIFO caps) for the presence of registers after this; the VMX
* can define "extended FIFO" to mean whatever it wants, and currently
* won't enable it unless there's room for that set and much more.
*/
SVGA_FIFO_CAPABILITIES = 4,
SVGA_FIFO_FLAGS,
// Valid with SVGA_FIFO_CAP_FENCE:
SVGA_FIFO_FENCE,
/*
* Block 3a (optional extended registers): Additional registers for the
* extended FIFO, whose presence isn't actually implied by
* SVGA_CAP_EXTENDED_FIFO; these exist if SVGA_FIFO_MIN is high enough to
* leave room for them.
*
* These in block 3a, the VMX currently considers mandatory for the
* extended FIFO.
*/
// Valid if exists (i.e. if extended FIFO enabled):
SVGA_FIFO_3D_HWVERSION, /* See SVGA3dHardwareVersion in svga3d_reg.h */
// Valid with SVGA_FIFO_CAP_PITCHLOCK:
SVGA_FIFO_PITCHLOCK,
// Valid with SVGA_FIFO_CAP_CURSOR_BYPASS_3:
SVGA_FIFO_CURSOR_ON, /* Cursor bypass 3 show/hide register */
SVGA_FIFO_CURSOR_X, /* Cursor bypass 3 x register */
SVGA_FIFO_CURSOR_Y, /* Cursor bypass 3 y register */
SVGA_FIFO_CURSOR_COUNT, /* Incremented when any of the other 3 change */
SVGA_FIFO_CURSOR_LAST_UPDATED,/* Last time the host updated the cursor */
// Valid with SVGA_FIFO_CAP_RESERVE:
SVGA_FIFO_RESERVED, /* Bytes past NEXT_CMD with real contents */
/*
* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2:
*
* By default this is SVGA_ID_INVALID, to indicate that the cursor
* coordinates are specified relative to the virtual root. If this
* is set to a specific screen ID, cursor position is reinterpreted
* as a signed offset relative to that screen's origin.
*/
SVGA_FIFO_CURSOR_SCREEN_ID,
/*
* Valid with SVGA_FIFO_CAP_DEAD
*
* An arbitrary value written by the host, drivers should not use it.
*/
SVGA_FIFO_DEAD,
/*
* Valid with SVGA_FIFO_CAP_3D_HWVERSION_REVISED:
*
* Contains 3D HWVERSION (see SVGA3dHardwareVersion in svga3d_reg.h)
* on platforms that can enforce graphics resource limits.
*/
SVGA_FIFO_3D_HWVERSION_REVISED,
/*
* XXX: The gap here, up until SVGA_FIFO_3D_CAPS, can be used for new
* registers, but this must be done carefully and with judicious use of
* capability bits, since comparisons based on SVGA_FIFO_MIN aren't
* enough to tell you whether the register exists: we've shipped drivers
* and products that used SVGA_FIFO_3D_CAPS but didn't know about some of
* the earlier ones. The actual order of introduction was:
* - PITCHLOCK
* - 3D_CAPS
* - CURSOR_* (cursor bypass 3)
* - RESERVED
* So, code that wants to know whether it can use any of the
* aforementioned registers, or anything else added after PITCHLOCK and
* before 3D_CAPS, needs to reason about something other than
* SVGA_FIFO_MIN.
*/
/*
* 3D caps block space; valid with 3D hardware version >=
* SVGA3D_HWVERSION_WS6_B1.
*/
SVGA_FIFO_3D_CAPS = 32,
SVGA_FIFO_3D_CAPS_LAST = 32 + 255,
/*
* End of VMX's current definition of "extended-FIFO registers".
* Registers before here are always enabled/disabled as a block; either
* the extended FIFO is enabled and includes all preceding registers, or
* it's disabled entirely.
*
* Block 3b (truly optional extended registers): Additional registers for
* the extended FIFO, which the VMX already knows how to enable and
* disable with correct granularity.
*
* Registers after here exist if and only if the guest SVGA driver
* sets SVGA_FIFO_MIN high enough to leave room for them.
*/
// Valid if register exists:
SVGA_FIFO_GUEST_3D_HWVERSION, /* Guest driver's 3D version */
SVGA_FIFO_FENCE_GOAL, /* Matching target for SVGA_IRQFLAG_FENCE_GOAL */
SVGA_FIFO_BUSY, /* See "FIFO Synchronization Registers" */
/*
* Always keep this last. This defines the maximum number of
* registers we know about. At power-on, this value is placed in
* the SVGA_REG_MEM_REGS register, and we expect the guest driver
* to allocate this much space in FIFO memory for registers.
*/
SVGA_FIFO_NUM_REGS
};
/*
* Definition of registers included in extended FIFO support.
*
* The guest SVGA driver gets to allocate the FIFO between registers
* and data. It must always allocate at least 4 registers, but old
* drivers stopped there.
*
* The VMX will enable extended FIFO support if and only if the guest
* left enough room for all registers defined as part of the mandatory
* set for the extended FIFO.
*
* Note that the guest drivers typically allocate the FIFO only at
* initialization time, not at mode switches, so it's likely that the
* number of FIFO registers won't change without a reboot.
*
* All registers less than this value are guaranteed to be present if
* svgaUser->fifo.extended is set. Any later registers must be tested
* individually for compatibility at each use (in the VMX).
*
* This value is used only by the VMX, so it can change without
* affecting driver compatibility; keep it that way?
*/
#define SVGA_FIFO_EXTENDED_MANDATORY_REGS (SVGA_FIFO_3D_CAPS_LAST + 1)
/*
* FIFO Synchronization Registers
*
* This explains the relationship between the various FIFO
* sync-related registers in IOSpace and in FIFO space.
*
* SVGA_REG_SYNC --
*
* The SYNC register can be used in two different ways by the guest:
*
* 1. If the guest wishes to fully sync (drain) the FIFO,
* it will write once to SYNC then poll on the BUSY
* register. The FIFO is sync'ed once BUSY is zero.
*
* 2. If the guest wants to asynchronously wake up the host,
* it will write once to SYNC without polling on BUSY.
* Ideally it will do this after some new commands have
* been placed in the FIFO, and after reading a zero
* from SVGA_FIFO_BUSY.
*
* (1) is the original behaviour that SYNC was designed to
* support. Originally, a write to SYNC would implicitly
* trigger a read from BUSY. This causes us to synchronously
* process the FIFO.
*
* This behaviour has since been changed so that writing SYNC
* will *not* implicitly cause a read from BUSY. Instead, it
* makes a channel call which asynchronously wakes up the MKS
* thread.
*
* New guests can use this new behaviour to implement (2)
* efficiently. This lets guests get the host's attention
* without waiting for the MKS to poll, which gives us much
* better CPU utilization on SMP hosts and on UP hosts while
* we're blocked on the host GPU.
*
* Old guests shouldn't notice the behaviour change. SYNC was
* never guaranteed to process the entire FIFO, since it was
* bounded to a particular number of CPU cycles. Old guests will
* still loop on the BUSY register until the FIFO is empty.
*
* Writing to SYNC currently has the following side-effects:
*
* - Sets SVGA_REG_BUSY to TRUE (in the monitor)
* - Asynchronously wakes up the MKS thread for FIFO processing
* - The value written to SYNC is recorded as a "reason", for
* stats purposes.
*
* If SVGA_FIFO_BUSY is available, drivers are advised to only
* write to SYNC if SVGA_FIFO_BUSY is FALSE. Drivers should set
* SVGA_FIFO_BUSY to TRUE after writing to SYNC. The MKS will
* eventually set SVGA_FIFO_BUSY on its own, but this approach
* lets the driver avoid sending multiple asynchronous wakeup
* messages to the MKS thread.
*
* SVGA_REG_BUSY --
*
* This register is set to TRUE when SVGA_REG_SYNC is written,
* and it reads as FALSE when the FIFO has been completely
* drained.
*
* Every read from this register causes us to synchronously
* process FIFO commands. There is no guarantee as to how many
* commands each read will process.
*
* CPU time spent processing FIFO commands will be billed to
* the guest.
*
* New drivers should avoid using this register unless they
* need to guarantee that the FIFO is completely drained. It
* is overkill for performing a sync-to-fence. Older drivers
* will use this register for any type of synchronization.
*
* SVGA_FIFO_BUSY --
*
* This register is a fast way for the guest driver to check
* whether the FIFO is already being processed. It reads and
* writes at normal RAM speeds, with no monitor intervention.
*
* If this register reads as TRUE, the host is guaranteeing that
* any new commands written into the FIFO will be noticed before
* the MKS goes back to sleep.
*
* If this register reads as FALSE, no such guarantee can be
* made.
*
* The guest should use this register to quickly determine
* whether or not it needs to wake up the host. If the guest
* just wrote a command or group of commands that it would like
* the host to begin processing, it should:
*
* 1. Read SVGA_FIFO_BUSY. If it reads as TRUE, no further
* action is necessary.
*
* 2. Write TRUE to SVGA_FIFO_BUSY. This informs future guest
* code that we've already sent a SYNC to the host and we
* don't need to send a duplicate.
*
* 3. Write a reason to SVGA_REG_SYNC. This will send an
* asynchronous wakeup to the MKS thread.
*/
/*
* FIFO Capabilities
*
* Fence -- Fence register and command are supported
* Accel Front -- Front buffer only commands are supported
* Pitch Lock -- Pitch lock register is supported
* Video -- SVGA Video overlay units are supported
* Escape -- Escape command is supported
*
* XXX: Add longer descriptions for each capability, including a list
* of the new features that each capability provides.
*
* SVGA_FIFO_CAP_SCREEN_OBJECT --
*
* Provides dynamic multi-screen rendering, for improved Unity and
* multi-monitor modes. With Screen Object, the guest can
* dynamically create and destroy 'screens', which can represent
* Unity windows or virtual monitors. Screen Object also provides
* strong guarantees that DMA operations happen only when
* guest-initiated. Screen Object deprecates the BAR1 guest
* framebuffer (GFB) and all commands that work only with the GFB.
*
* New registers:
* FIFO_CURSOR_SCREEN_ID, VIDEO_DATA_GMRID, VIDEO_DST_SCREEN_ID
*
* New 2D commands:
* DEFINE_SCREEN, DESTROY_SCREEN, DEFINE_GMRFB, BLIT_GMRFB_TO_SCREEN,
* BLIT_SCREEN_TO_GMRFB, ANNOTATION_FILL, ANNOTATION_COPY
*
* New 3D commands:
* BLIT_SURFACE_TO_SCREEN
*
* New guarantees:
*
* - The host will not read or write guest memory, including the GFB,
* except when explicitly initiated by a DMA command.
*
* - All DMA, including legacy DMA like UPDATE and PRESENT_READBACK,
* is guaranteed to complete before any subsequent FENCEs.
*
* - All legacy commands which affect a Screen (UPDATE, PRESENT,
* PRESENT_READBACK) as well as new Screen blit commands will
* all behave consistently as blits, and memory will be read
* or written in FIFO order.
*
* For example, if you PRESENT from one SVGA3D surface to multiple
* places on the screen, the data copied will always be from the
* SVGA3D surface at the time the PRESENT was issued in the FIFO.
* This was not necessarily true on devices without Screen Object.
*
* This means that on devices that support Screen Object, the
* PRESENT_READBACK command should not be necessary unless you
* actually want to read back the results of 3D rendering into
* system memory. (And for that, the BLIT_SCREEN_TO_GMRFB
* command provides a strict superset of functionality.)
*
* - When a screen is resized, either using Screen Object commands or
* legacy multimon registers, its contents are preserved.
*
* SVGA_FIFO_CAP_GMR2 --
*
* Provides new commands to define and remap guest memory regions (GMR).
*
* New 2D commands:
* DEFINE_GMR2, REMAP_GMR2.
*
* SVGA_FIFO_CAP_3D_HWVERSION_REVISED --
*
* Indicates new register SVGA_FIFO_3D_HWVERSION_REVISED exists.
* This register may replace SVGA_FIFO_3D_HWVERSION on platforms
* that enforce graphics resource limits. This allows the platform
* to clear SVGA_FIFO_3D_HWVERSION and disable 3D in legacy guest
* drivers that do not limit their resources.
*
* Note this is an alias to SVGA_FIFO_CAP_GMR2 because these indicators
* are codependent (and thus we use a single capability bit).
*
* SVGA_FIFO_CAP_SCREEN_OBJECT_2 --
*
* Modifies the DEFINE_SCREEN command to include a guest provided
* backing store in GMR memory and the bytesPerLine for the backing
* store. This capability requires the use of a backing store when
* creating screen objects. However if SVGA_FIFO_CAP_SCREEN_OBJECT
* is present then backing stores are optional.
*
* SVGA_FIFO_CAP_DEAD --
*
* Drivers should not use this cap bit. This cap bit can not be
* reused since some hosts already expose it.
*/
#define SVGA_FIFO_CAP_NONE 0
#define SVGA_FIFO_CAP_FENCE (1<<0)
#define SVGA_FIFO_CAP_ACCELFRONT (1<<1)
#define SVGA_FIFO_CAP_PITCHLOCK (1<<2)
#define SVGA_FIFO_CAP_VIDEO (1<<3)
#define SVGA_FIFO_CAP_CURSOR_BYPASS_3 (1<<4)
#define SVGA_FIFO_CAP_ESCAPE (1<<5)
#define SVGA_FIFO_CAP_RESERVE (1<<6)
#define SVGA_FIFO_CAP_SCREEN_OBJECT (1<<7)
#define SVGA_FIFO_CAP_GMR2 (1<<8)
#define SVGA_FIFO_CAP_3D_HWVERSION_REVISED SVGA_FIFO_CAP_GMR2
#define SVGA_FIFO_CAP_SCREEN_OBJECT_2 (1<<9)
#define SVGA_FIFO_CAP_DEAD (1<<10)
/*
* FIFO Flags
*
* Accel Front -- Driver should use front buffer only commands
*/
#define SVGA_FIFO_FLAG_NONE 0
#define SVGA_FIFO_FLAG_ACCELFRONT (1<<0)
#define SVGA_FIFO_FLAG_RESERVED (1<<31) // Internal use only
/*
* FIFO reservation sentinel value
*/
#define SVGA_FIFO_RESERVED_UNKNOWN 0xffffffff
/*
* Video overlay support
*/
#define SVGA_NUM_OVERLAY_UNITS 32
/*
* Video capabilities that the guest is currently using
*/
#define SVGA_VIDEO_FLAG_COLORKEY 0x0001
/*
* Offsets for the video overlay registers
*/
enum {
SVGA_VIDEO_ENABLED = 0,
SVGA_VIDEO_FLAGS,
SVGA_VIDEO_DATA_OFFSET,
SVGA_VIDEO_FORMAT,
SVGA_VIDEO_COLORKEY,
SVGA_VIDEO_SIZE, // Deprecated
SVGA_VIDEO_WIDTH,
SVGA_VIDEO_HEIGHT,
SVGA_VIDEO_SRC_X,
SVGA_VIDEO_SRC_Y,
SVGA_VIDEO_SRC_WIDTH,
SVGA_VIDEO_SRC_HEIGHT,
SVGA_VIDEO_DST_X, // Signed int32
SVGA_VIDEO_DST_Y, // Signed int32
SVGA_VIDEO_DST_WIDTH,
SVGA_VIDEO_DST_HEIGHT,
SVGA_VIDEO_PITCH_1,
SVGA_VIDEO_PITCH_2,
SVGA_VIDEO_PITCH_3,
SVGA_VIDEO_DATA_GMRID, // Optional, defaults to SVGA_GMR_FRAMEBUFFER
SVGA_VIDEO_DST_SCREEN_ID, // Optional, defaults to virtual coords (SVGA_ID_INVALID)
SVGA_VIDEO_NUM_REGS
};
/*
* SVGA Overlay Units
*
* width and height relate to the entire source video frame.
* srcX, srcY, srcWidth and srcHeight represent subset of the source
* video frame to be displayed.
*/
typedef struct SVGAOverlayUnit {
uint32 enabled;
uint32 flags;
uint32 dataOffset;
uint32 format;
uint32 colorKey;
uint32 size;
uint32 width;
uint32 height;
uint32 srcX;
uint32 srcY;
uint32 srcWidth;
uint32 srcHeight;
int32 dstX;
int32 dstY;
uint32 dstWidth;
uint32 dstHeight;
uint32 pitches[3];
uint32 dataGMRId;
uint32 dstScreenId;
} SVGAOverlayUnit;
/*
* Guest display topology
*
* XXX: This structure is not part of the SVGA device's interface, and
* doesn't really belong here.
*/
#define SVGA_INVALID_DISPLAY_ID ((uint32)-1)
typedef struct SVGADisplayTopology {
uint16 displayId;
uint16 isPrimary;
uint32 width;
uint32 height;
uint32 positionX;
uint32 positionY;
} SVGADisplayTopology;
/*
* SVGAScreenObject --
*
* This is a new way to represent a guest's multi-monitor screen or
* Unity window. Screen objects are only supported if the
* SVGA_FIFO_CAP_SCREEN_OBJECT capability bit is set.
*
* If Screen Objects are supported, they can be used to fully
* replace the functionality provided by the framebuffer registers
* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY.
*
* The screen object is a struct with guaranteed binary
* compatibility. New flags can be added, and the struct may grow,
* but existing fields must retain their meaning.
*
* Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2 are required fields of
* a SVGAGuestPtr that is used to back the screen contents. This
* memory must come from the GFB. The guest is not allowed to
* access the memory and doing so will have undefined results. The
* backing store is required to be page aligned and the size is
* padded to the next page boundry. The number of pages is:
* (bytesPerLine * size.width * 4 + PAGE_SIZE - 1) / PAGE_SIZE
*
* The pitch in the backingStore is required to be at least large
* enough to hold a 32bbp scanline. It is recommended that the
* driver pad bytesPerLine for a potential performance win.
*
* The cloneCount field is treated as a hint from the guest that
* the user wants this display to be cloned, countCount times. A
* value of zero means no cloning should happen.
*/
#define SVGA_SCREEN_MUST_BE_SET (1 << 0) // Must be set or results undefined
#define SVGA_SCREEN_HAS_ROOT SVGA_SCREEN_MUST_BE_SET // Deprecated
#define SVGA_SCREEN_IS_PRIMARY (1 << 1) // Guest considers this screen to be 'primary'
#define SVGA_SCREEN_FULLSCREEN_HINT (1 << 2) // Guest is running a fullscreen app here
/*
* Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2. When the screen is
* deactivated the base layer is defined to lose all contents and
* become black. When a screen is deactivated the backing store is
* optional. When set backingPtr and bytesPerLine will be ignored.
*/
#define SVGA_SCREEN_DEACTIVATE (1 << 3)
/*
* Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2. When this flag is set
* the screen contents will be outputted as all black to the user
* though the base layer contents is preserved. The screen base layer
* can still be read and written to like normal though the no visible
* effect will be seen by the user. When the flag is changed the
* screen will be blanked or redrawn to the current contents as needed
* without any extra commands from the driver. This flag only has an
* effect when the screen is not deactivated.
*/
#define SVGA_SCREEN_BLANKING (1 << 4)
typedef
struct {
uint32 structSize; // sizeof(SVGAScreenObject)
uint32 id;
uint32 flags;
struct {
uint32 width;
uint32 height;
} size;
struct {
int32 x;
int32 y;
} root;
/*
* Added and required by SVGA_FIFO_CAP_SCREEN_OBJECT_2, optional
* with SVGA_FIFO_CAP_SCREEN_OBJECT.
*/
SVGAGuestImage backingStore;
uint32 cloneCount;
} SVGAScreenObject;
/*
* Commands in the command FIFO:
*
* Command IDs defined below are used for the traditional 2D FIFO
* communication (not all commands are available for all versions of the
* SVGA FIFO protocol).
*
* Note the holes in the command ID numbers: These commands have been
* deprecated, and the old IDs must not be reused.
*
* Command IDs from 1000 to 1999 are reserved for use by the SVGA3D
* protocol.
*
* Each command's parameters are described by the comments and
* structs below.
*/
typedef enum {
SVGA_CMD_INVALID_CMD = 0,
SVGA_CMD_UPDATE = 1,
SVGA_CMD_RECT_COPY = 3,
SVGA_CMD_RECT_ROP_COPY = 14,
SVGA_CMD_DEFINE_CURSOR = 19,
SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
SVGA_CMD_UPDATE_VERBOSE = 25,
SVGA_CMD_FRONT_ROP_FILL = 29,
SVGA_CMD_FENCE = 30,
SVGA_CMD_ESCAPE = 33,
SVGA_CMD_DEFINE_SCREEN = 34,
SVGA_CMD_DESTROY_SCREEN = 35,
SVGA_CMD_DEFINE_GMRFB = 36,
SVGA_CMD_BLIT_GMRFB_TO_SCREEN = 37,
SVGA_CMD_BLIT_SCREEN_TO_GMRFB = 38,
SVGA_CMD_ANNOTATION_FILL = 39,
SVGA_CMD_ANNOTATION_COPY = 40,
SVGA_CMD_DEFINE_GMR2 = 41,
SVGA_CMD_REMAP_GMR2 = 42,
SVGA_CMD_DEAD = 43,
SVGA_CMD_DEAD_2 = 44,
SVGA_CMD_MAX
} SVGAFifoCmdId;
#define SVGA_CMD_MAX_DATASIZE (256 * 1024)
#define SVGA_CMD_MAX_ARGS 64
#define SVGA_CB_MAX_COMMAND_SIZE (32 * 1024) // 32 KB
/*
* SVGA_CMD_UPDATE --
*
* This is a DMA transfer which copies from the Guest Framebuffer
* (GFB) at BAR1 + SVGA_REG_FB_OFFSET to any screens which
* intersect with the provided virtual rectangle.
*
* This command does not support using arbitrary guest memory as a
* data source- it only works with the pre-defined GFB memory.
* This command also does not support signed virtual coordinates.
* If you have defined screens (using SVGA_CMD_DEFINE_SCREEN) with
* negative root x/y coordinates, the negative portion of those
* screens will not be reachable by this command.
*
* This command is not necessary when using framebuffer
* traces. Traces are automatically enabled if the SVGA FIFO is
* disabled, and you may explicitly enable/disable traces using
* SVGA_REG_TRACES. With traces enabled, any write to the GFB will
* automatically act as if a subsequent SVGA_CMD_UPDATE was issued.
*
* Traces and SVGA_CMD_UPDATE are the only supported ways to render
* pseudocolor screen updates. The newer Screen Object commands
* only support true color formats.
*
* Availability:
* Always available.
*/
typedef
struct {
uint32 x;
uint32 y;
uint32 width;
uint32 height;
} SVGAFifoCmdUpdate;
/*
* SVGA_CMD_RECT_COPY --
*
* Perform a rectangular DMA transfer from one area of the GFB to
* another, and copy the result to any screens which intersect it.
*
* Availability:
* SVGA_CAP_RECT_COPY
*/
typedef
struct {
uint32 srcX;
uint32 srcY;
uint32 destX;
uint32 destY;
uint32 width;
uint32 height;
} SVGAFifoCmdRectCopy;
/*
* SVGA_CMD_RECT_ROP_COPY --
*
* Perform a rectangular DMA transfer from one area of the GFB to
* another, and copy the result to any screens which intersect it.
* The value of ROP may only be SVGA_ROP_COPY, and this command is
* only supported for backwards compatibility reasons.
*
* Availability:
* SVGA_CAP_RECT_COPY
*/
typedef
struct {
uint32 srcX;
uint32 srcY;
uint32 destX;
uint32 destY;
uint32 width;
uint32 height;
uint32 rop;
} SVGAFifoCmdRectRopCopy;
/*
* SVGA_CMD_DEFINE_CURSOR --
*
* Provide a new cursor image, as an AND/XOR mask.
*
* The recommended way to position the cursor overlay is by using
* the SVGA_FIFO_CURSOR_* registers, supported by the
* SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability.
*
* Availability:
* SVGA_CAP_CURSOR
*/
typedef
struct {
uint32 id; // Reserved, must be zero.
uint32 hotspotX;
uint32 hotspotY;
uint32 width;
uint32 height;
uint32 andMaskDepth; // Value must be 1 or equal to BITS_PER_PIXEL
uint32 xorMaskDepth; // Value must be 1 or equal to BITS_PER_PIXEL
/*
* Followed by scanline data for AND mask, then XOR mask.
* Each scanline is padded to a 32-bit boundary.
*/
} SVGAFifoCmdDefineCursor;
/*
* SVGA_CMD_DEFINE_ALPHA_CURSOR --
*
* Provide a new cursor image, in 32-bit BGRA format.
*
* The recommended way to position the cursor overlay is by using
* the SVGA_FIFO_CURSOR_* registers, supported by the
* SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability.
*
* Availability:
* SVGA_CAP_ALPHA_CURSOR
*/
typedef
struct {
uint32 id; // Reserved, must be zero.
uint32 hotspotX;
uint32 hotspotY;
uint32 width;
uint32 height;
/* Followed by scanline data */
} SVGAFifoCmdDefineAlphaCursor;
/*
* SVGA_CMD_UPDATE_VERBOSE --
*
* Just like SVGA_CMD_UPDATE, but also provide a per-rectangle
* 'reason' value, an opaque cookie which is used by internal
* debugging tools. Third party drivers should not use this
* command.
*
* Availability:
* SVGA_CAP_EXTENDED_FIFO
*/
typedef
struct {
uint32 x;
uint32 y;
uint32 width;
uint32 height;
uint32 reason;
} SVGAFifoCmdUpdateVerbose;
/*
* SVGA_CMD_FRONT_ROP_FILL --
*
* This is a hint which tells the SVGA device that the driver has
* just filled a rectangular region of the GFB with a solid
* color. Instead of reading these pixels from the GFB, the device
* can assume that they all equal 'color'. This is primarily used
* for remote desktop protocols.
*
* Availability:
* SVGA_FIFO_CAP_ACCELFRONT
*/
#define SVGA_ROP_COPY 0x03
typedef
struct {
uint32 color; // In the same format as the GFB
uint32 x;
uint32 y;
uint32 width;
uint32 height;
uint32 rop; // Must be SVGA_ROP_COPY
} SVGAFifoCmdFrontRopFill;
/*
* SVGA_CMD_FENCE --
*
* Insert a synchronization fence. When the SVGA device reaches
* this command, it will copy the 'fence' value into the
* SVGA_FIFO_FENCE register. It will also compare the fence against
* SVGA_FIFO_FENCE_GOAL. If the fence matches the goal and the
* SVGA_IRQFLAG_FENCE_GOAL interrupt is enabled, the device will
* raise this interrupt.
*
* Availability:
* SVGA_FIFO_FENCE for this command,
* SVGA_CAP_IRQMASK for SVGA_FIFO_FENCE_GOAL.
*/
typedef
struct {
uint32 fence;
} SVGAFifoCmdFence;
/*
* SVGA_CMD_ESCAPE --
*
* Send an extended or vendor-specific variable length command.
* This is used for video overlay, third party plugins, and
* internal debugging tools. See svga_escape.h
*
* Availability:
* SVGA_FIFO_CAP_ESCAPE
*/
typedef
struct {
uint32 nsid;
uint32 size;
/* followed by 'size' bytes of data */
} SVGAFifoCmdEscape;
/*
* SVGA_CMD_DEFINE_SCREEN --
*
* Define or redefine an SVGAScreenObject. See the description of
* SVGAScreenObject above. The video driver is responsible for
* generating new screen IDs. They should be small positive
* integers. The virtual device will have an implementation
* specific upper limit on the number of screen IDs
* supported. Drivers are responsible for recycling IDs. The first
* valid ID is zero.
*
* - Interaction with other registers:
*
* For backwards compatibility, when the GFB mode registers (WIDTH,
* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
* deletes all screens other than screen #0, and redefines screen
* #0 according to the specified mode. Drivers that use
* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0.
*
* If you use screen objects, do not use the legacy multi-mon
* registers (SVGA_REG_NUM_GUEST_DISPLAYS, SVGA_REG_DISPLAY_*).
*
* Availability:
* SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
*/
typedef
struct {
SVGAScreenObject screen; // Variable-length according to version
} SVGAFifoCmdDefineScreen;
/*
* SVGA_CMD_DESTROY_SCREEN --
*
* Destroy an SVGAScreenObject. Its ID is immediately available for
* re-use.
*
* Availability:
* SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
*/
typedef
struct {
uint32 screenId;
} SVGAFifoCmdDestroyScreen;
/*
* SVGA_CMD_DEFINE_GMRFB --
*
* This command sets a piece of SVGA device state called the
* Guest Memory Region Framebuffer, or GMRFB. The GMRFB is a
* piece of light-weight state which identifies the location and
* format of an image in guest memory or in BAR1. The GMRFB has
* an arbitrary size, and it doesn't need to match the geometry
* of the GFB or any screen object.
*
* The GMRFB can be redefined as often as you like. You could
* always use the same GMRFB, you could redefine it before
* rendering from a different guest screen, or you could even
* redefine it before every blit.
*
* There are multiple ways to use this command. The simplest way is
* to use it to move the framebuffer either to elsewhere in the GFB
* (BAR1) memory region, or to a user-defined GMR. This lets a
* driver use a framebuffer allocated entirely out of normal system
* memory, which we encourage.
*
* Another way to use this command is to set up a ring buffer of
* updates in GFB memory. If a driver wants to ensure that no
* frames are skipped by the SVGA device, it is important that the
* driver not modify the source data for a blit until the device is
* done processing the command. One efficient way to accomplish
* this is to use a ring of small DMA buffers. Each buffer is used
* for one blit, then we move on to the next buffer in the
* ring. The FENCE mechanism is used to protect each buffer from
* re-use until the device is finished with that buffer's
* corresponding blit.
*
* This command does not affect the meaning of SVGA_CMD_UPDATE.
* UPDATEs always occur from the legacy GFB memory area. This
* command has no support for pseudocolor GMRFBs. Currently only
* true-color 15, 16, and 24-bit depths are supported. Future
* devices may expose capabilities for additional framebuffer
* formats.
*
* The default GMRFB value is undefined. Drivers must always send
* this command at least once before performing any blit from the
* GMRFB.
*
* Availability:
* SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
*/
typedef
struct {
SVGAGuestPtr ptr;
uint32 bytesPerLine;
SVGAGMRImageFormat format;
} SVGAFifoCmdDefineGMRFB;
/*
* SVGA_CMD_BLIT_GMRFB_TO_SCREEN --
*
* This is a guest-to-host blit. It performs a DMA operation to
* copy a rectangular region of pixels from the current GMRFB to
* one or more Screen Objects.
*
* The destination coordinate may be specified relative to a
* screen's origin (if a screen ID is specified) or relative to the
* virtual coordinate system's origin (if the screen ID is
* SVGA_ID_INVALID). The actual destination may span zero or more
* screens, in the case of a virtual destination rect or a rect
* which extends off the edge of the specified screen.
*
* This command writes to the screen's "base layer": the underlying
* framebuffer which exists below any cursor or video overlays. No
* action is necessary to explicitly hide or update any overlays
* which exist on top of the updated region.
*
* The SVGA device is guaranteed to finish reading from the GMRFB
* by the time any subsequent FENCE commands are reached.
*
* This command consumes an annotation. See the
* SVGA_CMD_ANNOTATION_* commands for details.
*
* Availability:
* SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
*/
typedef
struct {
SVGASignedPoint srcOrigin;
SVGASignedRect destRect;
uint32 destScreenId;
} SVGAFifoCmdBlitGMRFBToScreen;
/*
* SVGA_CMD_BLIT_SCREEN_TO_GMRFB --
*
* This is a host-to-guest blit. It performs a DMA operation to
* copy a rectangular region of pixels from a single Screen Object
* back to the current GMRFB.
*
* Usage note: This command should be used rarely. It will
* typically be inefficient, but it is necessary for some types of
* synchronization between 3D (GPU) and 2D (CPU) rendering into
* overlapping areas of a screen.
*
* The source coordinate is specified relative to a screen's
* origin. The provided screen ID must be valid. If any parameters
* are invalid, the resulting pixel values are undefined.
*
* This command reads the screen's "base layer". Overlays like
* video and cursor are not included, but any data which was sent
* using a blit-to-screen primitive will be available, no matter
* whether the data's original source was the GMRFB or the 3D
* acceleration hardware.
*
* Note that our guest-to-host blits and host-to-guest blits aren't
* symmetric in their current implementation. While the parameters
* are identical, host-to-guest blits are a lot less featureful.
* They do not support clipping: If the source parameters don't
* fully fit within a screen, the blit fails. They must originate
* from exactly one screen. Virtual coordinates are not directly
* supported.
*
* Host-to-guest blits do support the same set of GMRFB formats
* offered by guest-to-host blits.
*
* The SVGA device is guaranteed to finish writing to the GMRFB by
* the time any subsequent FENCE commands are reached.
*
* Availability:
* SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
*/
typedef
struct {
SVGASignedPoint destOrigin;
SVGASignedRect srcRect;
uint32 srcScreenId;
} SVGAFifoCmdBlitScreenToGMRFB;
/*
* SVGA_CMD_ANNOTATION_FILL --
*
* This is a blit annotation. This command stores a small piece of
* device state which is consumed by the next blit-to-screen
* command. The state is only cleared by commands which are
* specifically documented as consuming an annotation. Other
* commands (such as ESCAPEs for debugging) may intervene between
* the annotation and its associated blit.
*
* This annotation is a promise about the contents of the next
* blit: The video driver is guaranteeing that all pixels in that
* blit will have the same value, specified here as a color in
* SVGAColorBGRX format.
*
* The SVGA device can still render the blit correctly even if it
* ignores this annotation, but the annotation may allow it to
* perform the blit more efficiently, for example by ignoring the
* source data and performing a fill in hardware.
*
* This annotation is most important for performance when the
* user's display is being remoted over a network connection.
*
* Availability:
* SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
*/
typedef
struct {
SVGAColorBGRX color;
} SVGAFifoCmdAnnotationFill;
/*
* SVGA_CMD_ANNOTATION_COPY --
*
* This is a blit annotation. See SVGA_CMD_ANNOTATION_FILL for more
* information about annotations.
*
* This annotation is a promise about the contents of the next
* blit: The video driver is guaranteeing that all pixels in that
* blit will have the same value as those which already exist at an
* identically-sized region on the same or a different screen.
*
* Note that the source pixels for the COPY in this annotation are
* sampled before applying the anqnotation's associated blit. They
* are allowed to overlap with the blit's destination pixels.
*
* The copy source rectangle is specified the same way as the blit
* destination: it can be a rectangle which spans zero or more
* screens, specified relative to either a screen or to the virtual
* coordinate system's origin. If the source rectangle includes
* pixels which are not from exactly one screen, the results are
* undefined.
*
* Availability:
* SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
*/
typedef
struct {
SVGASignedPoint srcOrigin;
uint32 srcScreenId;
} SVGAFifoCmdAnnotationCopy;
/*
* SVGA_CMD_DEFINE_GMR2 --
*
* Define guest memory region v2. See the description of GMRs above.
*
* Availability:
* SVGA_CAP_GMR2
*/
typedef
struct {
uint32 gmrId;
uint32 numPages;
} SVGAFifoCmdDefineGMR2;
/*
* SVGA_CMD_REMAP_GMR2 --
*
* Remap guest memory region v2. See the description of GMRs above.
*
* This command allows guest to modify a portion of an existing GMR by
* invalidating it or reassigning it to different guest physical pages.
* The pages are identified by physical page number (PPN). The pages
* are assumed to be pinned and valid for DMA operations.
*
* Description of command flags:
*
* SVGA_REMAP_GMR2_VIA_GMR: If enabled, references a PPN list in a GMR.
* The PPN list must not overlap with the remap region (this can be
* handled trivially by referencing a separate GMR). If flag is
* disabled, PPN list is appended to SVGARemapGMR command.
*
* SVGA_REMAP_GMR2_PPN64: If set, PPN list is in PPN64 format, otherwise
* it is in PPN32 format.
*
* SVGA_REMAP_GMR2_SINGLE_PPN: If set, PPN list contains a single entry.
* A single PPN can be used to invalidate a portion of a GMR or
* map it to to a single guest scratch page.
*
* Availability:
* SVGA_CAP_GMR2
*/
typedef enum {
SVGA_REMAP_GMR2_PPN32 = 0,
SVGA_REMAP_GMR2_VIA_GMR = (1 << 0),
SVGA_REMAP_GMR2_PPN64 = (1 << 1),
SVGA_REMAP_GMR2_SINGLE_PPN = (1 << 2),
} SVGARemapGMR2Flags;
typedef
struct {
uint32 gmrId;
SVGARemapGMR2Flags flags;
uint32 offsetPages; // offset in pages to begin remap
uint32 numPages; // number of pages to remap
/*
* Followed by additional data depending on SVGARemapGMR2Flags.
*
* If flag SVGA_REMAP_GMR2_VIA_GMR is set, single SVGAGuestPtr follows.
* Otherwise an array of page descriptors in PPN32 or PPN64 format
* (according to flag SVGA_REMAP_GMR2_PPN64) follows. If flag
* SVGA_REMAP_GMR2_SINGLE_PPN is set, array contains a single entry.
*/
} SVGAFifoCmdRemapGMR2;
/*
* Size of SVGA device memory such as frame buffer and FIFO.
*/
#define SVGA_VRAM_MIN_SIZE (4 * 640 * 480) // bytes
#define SVGA_VRAM_MIN_SIZE_3D (16 * 1024 * 1024)
#define SVGA_VRAM_MAX_SIZE (128 * 1024 * 1024)
#define SVGA_MEMORY_SIZE_MAX (1024 * 1024 * 1024)
#define SVGA_FIFO_SIZE_MAX (2 * 1024 * 1024)
#define SVGA_GRAPHICS_MEMORY_KB_MIN (32 * 1024)
#define SVGA_GRAPHICS_MEMORY_KB_MAX (2 * 1024 * 1024)
#define SVGA_GRAPHICS_MEMORY_KB_DEFAULT (256 * 1024)
#define SVGA_VRAM_SIZE_W2K (64 * 1024 * 1024) // 64 MB
/*
* To simplify autoDetect display configuration, support a minimum of
* two 1920x1200 monitors, 32bpp, side-by-side, optionally rotated:
* numDisplays = 2
* maxWidth = numDisplay * 1920 = 3840
* maxHeight = rotated width of single monitor = 1920
* vramSize = maxWidth * maxHeight * 4 = 29491200
*/
#define SVGA_VRAM_SIZE_AUTODETECT (32 * 1024 * 1024)
#if defined(VMX86_SERVER)
#define SVGA_VRAM_SIZE (4 * 1024 * 1024)
#define SVGA_VRAM_SIZE_3D (64 * 1024 * 1024)
#define SVGA_FIFO_SIZE (256 * 1024)
#define SVGA_FIFO_SIZE_3D (516 * 1024) // Bump to 516KB to workaround WDDM driver issue (see bug# 744318)
#define SVGA_MEMORY_SIZE_DEFAULT (160 * 1024 * 1024)
#define SVGA_AUTODETECT_DEFAULT FALSE
#else
#define SVGA_VRAM_SIZE (16 * 1024 * 1024)
#define SVGA_VRAM_SIZE_3D SVGA_VRAM_MAX_SIZE
#define SVGA_FIFO_SIZE (2 * 1024 * 1024)
#define SVGA_FIFO_SIZE_3D SVGA_FIFO_SIZE
#define SVGA_MEMORY_SIZE_DEFAULT (768 * 1024 * 1024)
#define SVGA_AUTODETECT_DEFAULT TRUE
#endif
#endif

/contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/svga/include/svga_types.h
0,0 → 1,57
/**********************************************************
* Copyright 1998-2014 VMware, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
**********************************************************/
#ifndef _SVGA_TYPES_H_
#define _SVGA_TYPES_H_
#include "pipe/p_compiler.h"
#ifndef __HAIKU__
typedef int64_t int64;
typedef uint64_t uint64;
typedef int32_t int32;
typedef uint32_t uint32;
typedef int16_t int16;
typedef uint16_t uint16;
typedef int8_t int8;
typedef uint8_t uint8;
#else
#include <OS.h>
#endif /* HAIKU */
typedef uint8_t Bool;
typedef uint64 PA;
typedef uint32 PPN;
typedef uint64 PPN64;
#undef MAX_UINT32
#define MAX_UINT32 0xffffffffU
#endif /* _SVGA_TYPES_H_ */

/contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/svga/include/vmware_pack_begin.h
0,0 → 1,0
/* dummy file */

/contrib/sdk/sources/Mesa/mesa-10.6.0/src/gallium/drivers/svga/include/vmware_pack_end.h
0,0 → 1,0
/* dummy file */