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Ignore whitespace Rev 144 → Rev 145

/programs/develop/metcc/trunk/libc/compile.js
0,0 → 1,118
var fso=new ActiveXObject("Scripting.FileSystemObject");
var wsh=WScript.CreateObject("WScript.Shell");
var curpath=".";
var gccpath="c:\\program files\\MinGW\\MinGW\\bin\\";
//var gccpath="cmd.exe /c ";
var gccexe="\""+gccpath+"cc1.exe"+"\" ";
var asexe="\""+gccpath+"as.exe"+"\" ";
var objcopyexe="\""+gccpath+"objcopy.exe"+"\" ";
//var gccexe=gccpath+"cc1.exe" ;
//var asexe=gccpath+"as.exe";
var scriptline="CREATE melibc.a\r\n";
 
curpath=".\\string\\";
compileasm("memmove");
compileasm("memset");
curpath=".\\mesys\\";
compileasm("backgr");
compileasm("button");
compileasm("clock");
compileasm("date");
compileasm("debug_board");
compileasm("delay");
compileasm("dga");
compileasm("draw_bar");
compileasm("draw_image");
compileasm("draw_window");
compileasm("event");
compileasm("exit");
compileasm("file_58");
compileasm("ipc");
compileasm("irq");
compileasm("keyboard");
compileasm("line");
compileasm("midi");
compileasm("pci");
compileasm("pixel");
compileasm("process");
compileasm("screen");
compileasm("sound");
compileasm("thread");
compileasm("window_redraw");
compileasm("write_text");
curpath=".\\mem\\";
compileasm("memalloc");
curpath=".\\mesys\\";
compilec("debug_board_");
curpath=".\\string\\";
compilec("memchr");
compilec("memcmp");
compilec("strcat");
compilec("strchr");
compilec("strcmp");
compilec("strcoll");
compilec("strcpy");
compilec("strcspn");
compilec("strdup");
compilec("strerror");
compilec("strlen");
compilec("strnbrk");
compilec("strncat");
compilec("strncmp");
compilec("strncpy");
compilec("strrchr");
compilec("strspn");
compilec("strstr");
compilec("strtok");
compilec("strxfrm");
curpath=".\\file\\";
compilec("fclose");
compilec("fopen");
compilec("feof");
compilec("fflush");
compilec("fgetc");
compilec("fgetpos");
compilec("fsetpos");
compilec("fputc");
compilec("fread");
compilec("fwrite");
compilec("fseek");
compilec("ftell");
compilec("rewind");
compilec("fprintf");
compilec("fscanf");
compilec("ungetc");
curpath=".\\start\\";
compileasm("start");
//linking
scriptline+="SAVE\r\n";
linko();
function compileasm(filename)
{
wsh.Run("fasm.exe "+quote(curpath+filename+".asm")+
" "+quote(curpath+filename+".o"),0,true);
addo(filename);
}
function compilec(filename)
{
wsh.Run(gccexe+"-nostdinc -I .\\include -DGNUC " + quote(curpath + filename + ".c")+
" -o " + quote(curpath + filename + ".s"),0,true);
wsh.Run(asexe+quote(curpath+filename+".s")+" -o "+quote(curpath+filename+".o"),0,true);
wsh.Run(objcopyexe+" -O elf32-i386 --remove-leading-char "+quote(curpath+filename+".o"),0,true);
addo(filename);
}
function addo(filename)
{
scriptline+="ADDMOD "+curpath+filename+".o\r\n";
}
function linko()
{
//fso.DeleteFile(".\\melibc.a");
var file=fso.OpenTextFile("./script.txt",2,true);
file.Write(scriptline);
wsh.Run("cmd.exe /c ar.exe -M < ./script.txt",4,true);
}
function quote(name)
{
return "\""+name+"\"";
}
/programs/develop/metcc/trunk/libc/file/fclose.c
0,0 → 1,10
#include "stdio.h"
#include "string.h"
int fclose(FILE* file)
{
int res;
res=_msys_write_file(file->filename,file->filesize,file->buffer);
free(file->buffer);
free(file);
return res;
}
/programs/develop/metcc/trunk/libc/file/feof.c
0,0 → 1,5
#include "stdio.h"
int feof(FILE* file)
{
return file->filepos>=file->filesize;
}
/programs/develop/metcc/trunk/libc/file/fflush.c
0,0 → 1,7
#include "stdio.h"
int fflush(FILE* file)
{
if ((file->mode & 3)==FILE_OPEN_READ)
return 0;
return _msys_file_write(file->filename,file->filesize,file->buffer) ? EOF : 0;
}
/programs/develop/metcc/trunk/libc/file/fgetc.c
0,0 → 1,12
#include "stdio.h"
int fgetc(FILE* file)
{
if ((file->mode & 3!=FILE_OPEN_READ) && (file->mode & FILE_OPEN_PLUS==0))
return EOF;
if (file->filepos>=file->filesize)
return EOF;
else
{
return (int)file->buffer[file->filepos++];
}
}
/programs/develop/metcc/trunk/libc/file/fgetpos.c
0,0 → 1,6
#include "stdio.h"
int fgetpos(FILE* file,fpos_t* pos)
{
*pos=file->filepos;
return 0;
}
/programs/develop/metcc/trunk/libc/file/fopen.c
0,0 → 1,89
#include "stdio.h"
#include "string.h"
FILE* fopen(const char* filename, const char *mode)
{
FILE* res;
int imode;
imode=0;
if (*mode=='r')
{
imode=FILE_OPEN_READ;
mode++;
}else if (*mode=='w')
{
imode=FILE_OPEN_WRITE;
mode++;
}else if (*mode=='a')
{
imode=FILE_OPEN_APPEND;
mode++;
}else
return 0;
if (*mode=='t')
{
imode|=FILE_OPEN_TEXT;
mode++;
}else if (*mode=='b')
mode++;
if (*mode=='+')
{
imode|=FILE_OPEN_PLUS;
mode++;
}
if (*mode!=0)
return 0;
res=malloc(sizeof(FILE));
res->buffer=0;
res->buffersize=0;
res->filesize=0;
res->filepos=0;
res->filename=0;
res->mode=imode;
//check if file exists
res=_msys_read_file(filename,0,0,0,&res->filesize);
if (res==5)
{
if ((imode & 3) == FILE_OPEN_READ)
{
free(res);
return 0;
}
res=_msys_write_file(filename,0,0);
if (res!=0)
{
free(res);
return 0;
}
res->filesize=0;
}
if (imode & 3==FILE_OPEN_WRITE)
{
res->buffersize=512;
res->buffer=malloc(res->buffersize);
if (res->buffer=0)
{
free(res);
return 0;
}
res->filesize=0;
}else
{
res->buffersize=(res->filesize & (~511))+512;
res->buffer=malloc(res->buffersize);
if (res->buffer==0)
{
free(res);
return 0;
}
res=_msys_read_file(filename,0,res->filesize,res->buffer,0);
if (res!=0)
{
free(res->buffer);
free(res);
}
if (imode & 3==FILE_OPEN_APPEND)
res->filepos=res->filesize;
}
res->filename=strdup(filename);
return res;
}
/programs/develop/metcc/trunk/libc/file/fprintf.c
0,0 → 1,216
#include "stdio.h"
const char xdigs_lower[16]="0123456789abcdef";
const char xdigs_upper[16]="0123456789ABCDEF";
int fprintf(FILE* file, const char* format, ...)
{
void* arg;
int ispoint;
int beforepoint;
int afterpoint;
int longflag;
int contflag;
int i;
long long number;
char buffer[50];
char* str;
arg=&format;
arg+=sizeof(const char*);
while (*format!='\0')
{
if (*format!='%')
{
fputc(*format,file);
format++;
continue;
}
ispoint=0;
beforepoint=0;
afterpoint=0;
longflag=0;
contflag=1;
format++;
while (*format && contflag)
{
switch (*format)
{
case '.':
ispoint=1;
format++;
break;
case '0':
case '1':
case '2':
case '3':
case '4':
case '5':
case '6':
case '7':
case '8':
case '9':
if (ispoint)
afterpoint=afterpoint*10+(*format)-'0';
else
beforepoint=beforepoint*10+(*format)-'0';
format++;
break;
case 'l':
if (longflag==0)
longflag=1;
else
longflag=2;
format++;
break;
case 'L':
longflag=2;
format++;
break;
case 'f':
case 'd':
case 'x':
case 'X':
case 'c':
case 's':
case '%':
contflag=0;
break;
default:
contflag=0;
}
}
if (contflag)
break;
switch (*format)
{
case '%':
fpuc('%',file);
break;
case 'd':
if (longflag==2)
{
number=*((long long *)arg);
arg+=sizeof(long long);
}else
{
number=*((int*)arg);
arg+=sizeof(int);
}
if (number<0)
{
beforepoint--;
fputc('-',file);
number=-number;
}
i=0;
while (number>0)
{
buffer[i]='0'+number%10;
number=number/10;
i++;
}
while (i<beforepoint)
{
fputc(' ',file);
beforepoint--;
}
while (i>0)
{
i--;
fputc(buffer[i],file);
}
break;
case 'c':
fputc(*(char*)arg,file);
arg+=sizeof(char);
break;
case 's':
str=*(char**)arg;
arg+=sizeof(char*);
if (beforepoint==0)
beforepoint--;
while (*str && beforepoint)
{
fputc(*str,file);
beforepoint--;
str++;
}
break;
case 'x':
if (longflag==2)
{
number=*((long long *)arg);
arg+=sizeof(long long);
}else
{
number=*((int*)arg);
arg+=sizeof(int);
}
if (number<0)
{
beforepoint--;
fputc('-',file);
number=-number;
}
i=0;
while (number>0)
{
buffer[i]=xdigs_lower[number & 15];
number=number>>4;
i++;
}
while (i<beforepoint)
{
fputc(' ',file);
beforepoint--;
}
while (i>0)
{
i--;
fputc(buffer[i],file);
}
break;
case 'X':
if (longflag==2)
{
number=*((long long *)arg);
arg+=sizeof(long long);
}else
{
number=*((int*)arg);
arg+=sizeof(int);
}
if (number<0)
{
beforepoint--;
fputc('-',file);
number=-number;
}
i=0;
while (number>0)
{
buffer[i]=xdigs_upper[number & 15];
number=number>>4;
i++;
}
while (i<beforepoint)
{
fputc(' ',file);
beforepoint--;
}
while (i>0)
{
i--;
fputc(buffer[i],file);
}
break;
case 'f':
if (longflag==2)
arg+=10;
else if (longflag==1)
arg+=8;
else
arg+=4;
break;
}
format++;
}
}
/programs/develop/metcc/trunk/libc/file/fputc.c
0,0 → 1,24
#include "stdio.h"
int fputc(int c,FILE* file)
{
void* p;
if ((file->mode & 3)==FILE_OPEN_READ)
return EOF;
if ((file->mode & 3)==FILE_OPEN_APPEND)
file->filepos=file->filesize;
if (file->filepos==file->filesize)
{
file->filesize++;
if (file->filesize>file->buffersize)
{
p=realloc(file->buffer,file->filesize+file->filesize<<1);
if (p==0)
return EOF;
file->buffersize=file->filesize+file->filesize<<1;
file->buffer=p;
}
}
file->buffer[file->filepos]=(char)c;
file->filepos++;
return 0;
}
/programs/develop/metcc/trunk/libc/file/fread.c
0,0 → 1,12
#include "stdio.h"
int fread(void* buffer,int size,int count,FILE* file)
{
if ((file->mode & 3!=FILE_OPEN_READ) && (file->mode & FILE_OPEN_PLUS==0))
return 0;
count=count*size;
if (count+file->filepos>file->filesize)
count=file->filesize-file->filepos;
memcpy(buffer,file->buffer+file->filepos,count);
file->filepos+=count;
return count/size;
}
/programs/develop/metcc/trunk/libc/file/fscanf.c
0,0 → 1,188
#include "stdio.h"
void skipspaces(FILE* file)
{
int c;
while(1)
{
c=getc(file);
if (c!=' ' && c!='\r' && c!='\n')
{
ungetc(c,file);
return;
}
}
}
int fscanf(FILE* file,const char* format, ...)
{
int res;
void* arg;
int i;
int c;
int contflag;
int longflag;
int sign;
long long number;
long double rnumber;
char* str;
res=0;
arg=&format;
arg+=sizeof(const char*);
while (*format!='\0')
{
if (*format!='%')
{
c=fgetc(file);
if (c!=*format)
{
fungetc(c,file);
return -1;
}
format++;
continue;
}
contflag=1;
longflag=0;
while (*format && contflag)
{
switch(*format)
{
case '.':
case '0':
case '1':
case '2':
case '3':
case '4':
case '5':
case '6':
case '7':
case '8':
case '9':
format++;
continue;
break;
case 'l':
if (longflag==0)
longflag=1;
else
longflag=2;
format++;
break;
case 'L':
longflag=2;
format++;
break;
case 'f':
case 'd':
case 'c':
case 's':
case '%':
contflag=0;
break;
default:
contflag=0;
}
}
if (contflag)
break;
switch(*format)
{
case '%':
c=fgetc(file);
if (c!='%')
{
ungetc(c,file);
return -1;
}
res--;
break;
case 'd':
number=0;
sign=1;
skipspaces(file);
c=fgetc(file);
if (c=='-')
{
sign=-1;
}else if (c!='+')
ungetc(c,file);
contflag=0;
while(1)
{
c=fgetc(file);
if (c>='0' && c<='9')
{
contflag++;
number=number*10+(c-'0');
}else
break;
}
ungetc(c,file);
if (!contflag)
return res;
if (longflag<=1)
{
*((int*)arg)=number;
arg+=sizeof(int);
}else
{
*((long long*)arg)=number;
arg+=sizeof(long long);
}
break;
case 'c':
c=fgetc(file);
if (c==EOF)
return res;
*((char*)arg)=c;
arg+=sizeof(char);
break;
case 's':
skipspaces(file);
contflag=0;
str=*((char**)arg);
arg+=sizeof(char*);
while(1)
{
c=fgetc(file);
if (c==EOF || c==' ' || c=='\n' || c=='\r')
{
ungetc(c,file);
break;
}
*str=c;
str++;
contflag++;
}
if (!contflag)
return res;
break;
case 'f':
skipspaces(file);
// TODO: read real numbers
rnumber=0;
switch (longflag)
{
case 0:
*((float*)arg)=rnumber;
arg+=sizeof(float);
break;
case 1:
*((double*)arg)=rnumber;
arg+=sizeof(double);
break;
case 2:
*((long double*)arg)=rnumber;
arg+=sizeof(long double);
break;
default:
return res;
}
break;
default:
break;
}
format++;
res++;
}
return res;
}
/programs/develop/metcc/trunk/libc/file/fseek.c
0,0 → 1,11
#include "stdio.h"
int fseek(FILE* file,long offset,int origin)
{
if (origin==SEEK_CUR)
offset+=file->filepos;
else if (origin==SEEK_END)
offset+=file->filesize;
else if (origin!=SEEK_SET)
return EOF;
return fsetpos(file,offset);
}
/programs/develop/metcc/trunk/libc/file/fsetpos.c
0,0 → 1,11
#include "stdio.h"
int fsetpos(FILE* file,const fpos_t * pos)
{
if (*pos>=0)
{
file->filepos=*pos;
return 0;
}
else
return EOF;
}
/programs/develop/metcc/trunk/libc/file/ftell.c
0,0 → 1,5
#include "stdio.h"
long ftell(FILE* file)
{
return file->filepos;
}
/programs/develop/metcc/trunk/libc/file/fwrite.c
0,0 → 1,23
#include "stdio.h"
int fwrite(const void* buffer,int size,int count,FILE* file)
{
void* p;
if ((file->mode & 3==FILE_OPEN_READ) && (file->mode & FILE_OPEN_PLUS==0))
return 0;
if (file->mode & 3==FILE_OPEN_APPEND)
file->filepos=file->filesize;
count=count*size;
if (file->buffersize<file->filepos+count)
{
p=realloc(file->buffer,(file->filepos+count)+(file->filepos+count)<<1);
if (p==0)
return 0;
file->buffer=p;
file->buffersize=(file->filepos+count)+(file->filepos+count)<<1;
}
if (file->filesize<file->filepos+count)
file->filesize=file->filepos+count;
memcpy(file->buffer+file->filepos,buffer,count);
file->filepos+=count;
return count;
}
/programs/develop/metcc/trunk/libc/file/rewind.c
0,0 → 1,5
#include "stdio.h"
void rewind(FILE* file)
{
file->filepos=0;
}
/programs/develop/metcc/trunk/libc/file/ungetc.c
0,0 → 1,11
#include "stdio.h"
int ungetc(int c,FILE* file)
{
if (c==EOF)
return EOF;
if (file->filepos<=0 || file->filepos>file->filesize)
return EOF;
file->filepos--;
file->buffer[file->filepos]=(char)c;
return c;
}
/programs/develop/metcc/trunk/libc/file
Property changes:
Added: svn:ignore
+*.o
+*.s
/programs/develop/metcc/trunk/libc/include/mesys.h
0,0 → 1,88
#ifndef mesys_h
#define mesys_h
#ifdef GNUC
#define stdcall __stdcall
#else
#define stdcall __attribute__ ((__stdcall))
#endif
extern void stdcall _msys_draw_window(int xcoord,int ycoord, int xsize,
int ysize,int workcolor,int type,
int captioncolor,int windowtype,int bordercolor);
extern int stdcall _msys_read_file(char* filename,int fileoffset,int size,void* data,
int* filesize);
extern int stdcall _msys_write_file(char* filename,int size,void* data);
extern void stdcall _msys_run_program(char* filename,char* parameters);
extern void stdcall _msys_debug_out(int c);
extern void debug_out_str(char* str);
extern void stdcall _msys_set_background_size(int xsize,int ysize);
extern void stdcall _msys_write_background_mem(int pos,int color);
extern void stdcall _msys_draw_background(void);
extern void stdcall _msys_set_background_draw_type(int type);
extern void stdcall _msys_background_blockmove(void* src,int bgr_pos, int count);
extern void stdcall _msys_draw_bar(int x, int y, int xsize, int ysize, int color);
extern void stdcall _msys_make_button(int x, int y, int xsize, int ysize, int id, int color);
extern int stdcall _msys_get_button_id(void);
extern int stdcall _msys_get_system_clock(void);
extern int stdcall _msys_get_date(void);
extern void stdcall _msys_delay(int m);
extern void stdcall _msys_dga_get_resolution(int* xres, int* yres, int* bpp, int* bpscan);
extern int stdcall _msys_wait_for_event_infinite(void);
extern int stdcall _msys_check_for_event(void);
extern int stdcall _msys_wait_for_event(int time);
extern void stdcall _msys_set_wanted_events(int ev);
extern void stdcall _msys_exit(void);
extern void stdcall _msys_putimage(int x, int y, int xsize, int ysize, void* image);
extern void stdcall _msys_send_message(int pid, void* msg, int size);
extern void stdcall _msys_define_receive_area(void* area, int size);
extern int stdcall _msys_get_irq_owner(int irq);
extern int stdcall _msys_get_data_read_by_irq(int irq, int* size, void* data);
extern int stdcall _msys_send_data_to_device(int port, unsigned char val);
extern int stdcall _msys_receive_data_from_device(int port,unsigned char* data);
extern void stdcall _msys_program_irq(void* intrtable, int irq);
extern void stdcall _msys_reserve_irq(int irq);
extern void stdcall _msys_free_irq(int irq);
extern int stdcall _msys_reserve_port_area(int start,int end);
extern int stdcall _msys_free_port_area(int start,int end);
extern int stdcall _msys_get_key(void);
extern void stdcall _msys_set_keyboard_mode(int mode);
extern void stdcall _msys_line(int x1,int y1,int x2,int y2,int color);
extern void stdcall _msys_midi_reset(void);
extern void stdcall _msys_midi_send(int data);
extern int stdcall _msys_get_pci_version(void);
extern int stdcall _msys_get_last_pci_bus(void);
extern int stdcall _msys_get_pci_access_mechanism(void);
extern int stdcall _msys_pci_read_config_byte(int bus,int dev,int fn,int reg);
extern int stdcall _msys_pci_read_config_word(int bus,int dev,int fn,int reg);
extern int stdcall _msys_pci_read_config_dword(int bus,int dev,int fn,int reg);
extern int stdcall _msys_pci_write_config_byte(int bus,int dev,int fn,int reg,int value);
extern int stdcall _msys_pci_write_config_word(int bus,int dev,int fn,int reg,int value);
extern int stdcall _msys_pci_write_config_value(int bus,int dev,int fn,int reg,int value);
extern int stdcall _msys_putpixel(int x,int y,int color);
typedef struct {
int cpu_usage;
int window_pos_info;
char name[12];
int memstart;
int memused;
int pid;
int winx_start;
int winy_start;
int winx_size;
int winy_size;
int slot_info;
} process_table_entry;
extern int stdcall _msys_get_process_table(process_table_entry* proctab,int pid);
extern int stdcall _msys_get_screen_size(int* x,int* y);
extern void stdcall _msys_sound_load_block(void* blockptr);
extern void stdcall _msys_sound_play_block(void);
extern void stdcall _msys_sound_set_channels(int channels);
extern void stdcall _msys_sound_set_data_size(int size);
extern void stdcall _msys_sound_set_frequency(int frequency);
extern void stdcall _msys_sound_speaker_play(void* data);
extern void stdcall _msys_write_text(int x,int y,int color,char* text,int len);
extern void* stdcall _msys_start_thread(void (* func_ptr)(void),int stack_size,int* pid);
extern void stdcall _msys_window_redraw(int status);
extern void* stdcall malloc(int);
extern void stdcall free(void*);
extern void* stdcall realloc(void*,int);
#endif
/programs/develop/metcc/trunk/libc/include/stdio.h
0,0 → 1,38
#ifndef stdio_h
#define stdio_h
#include "mesys.h"
typedef struct {
char* buffer;
int buffersize;
int filesize;
int filepos;
char* filename;
int mode;
} FILE;
#define FILE_OPEN_READ 0
#define FILE_OPEN_WRITE 1
#define FILE_OPEN_APPEND 2
#define FILE_OPEN_TEXT 4
#define FILE_OPEN_PLUS 8
#define EOF -1
extern FILE* fopen(const char* filename, const char *mode);
extern int fclose(FILE* file);
extern int feof(FILE* file);
extern int fflush(FILE* file);
extern int fgetc(FILE* file);
typedef int fpos_t;
extern int fgetpos(FILE* file,fpos_t* pos);
extern int fsetpos(FILE* file,const fpos_t* pos);
extern int fputc(int c,FILE* file);
extern int fread(void* buffer,int size,int count,FILE* file);
extern int fwrite(const void* buffer,int size,int count,FILE* file);
extern long ftell(FILE* file);
#define SEEK_CUR 0
#define SEEK_END 1
#define SEEK_SET 2
extern int fseek(FILE* file,long offset,int origin);
extern void rewind(FILE* file);
extern int fprintf(FILE* file, const char* format, ...);
extern int fscanf(FILE* file,const char* format, ...);
extern int ungetc(int c,FILE* file);
#endif
/programs/develop/metcc/trunk/libc/include/string.h
0,0 → 1,25
#ifndef string_h
#define string_h
extern void* memchr(const void*,int,int);
extern int memcmp(const void*,const void*,int);
extern void* memcpy(void*,const void*,int);
extern void* memmove(void*,const void*,int);
extern void* memset(void*,int,int);
extern char* strcat(char*,const char*);
extern char* strchr(const char*,int);
extern int strcmp(const char*,const char*);
extern int strcoll(const char*,const char*);
extern char* strcpy(char*,const char*);
extern int strcspn(const char*,const char*);
extern int strlen(const char*);
extern char* strncat(char*,const char*,int);
extern int strncmp(const char*,const char*,int);
extern char* strncpy(char*,const char*,int);
extern char* strpbrk(const char*,const char*);
extern char* strrchr(const char*,int);
extern int strspn(const char*,const char*);
extern char* strstr(const char*,const char*);
extern char* strtok(char*,const char*);
extern int strxfrm(char*,const char*,int);
extern char* strdup(const char*);
#endif
/programs/develop/metcc/trunk/libc/mem/memalloc.asm
0,0 → 1,536
format ELF
section '.text' executable
public malloc
public free
public realloc
public mf_init
;multithread: ;uncomment this for thread-safe version
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Memory allocator for MenuetOS ;;
;; Halyavin Andrey halyavin@land.ru, 2006 ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; allocated mem block structure ;;
;; +0: bit 0 - used flag ;;
;; bits 31..1 - block size ;;
;; +4: address of prev block ;;
;; +8 .. +(blocksize) - allocated memory ;;
;; +(blocksize) - next block ;;
;; ;;
;; free mem block structure ;;
;; +0: bit 0 - used flag ;;
;; bits 31..1 - block size ;;
;; +4: address of prev block ;;
;; +8: prev free block ;;
;; +12: next free block ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
memblock.size=0
memblock.prevblock=4
memblock.prevfreeblock=8
memblock.nextfreeblock=12
 
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; mf_init ;;
;; Initialize memory map for dynamic use ;;
;; input: eax: starting address or 0 ;;
;; output: none ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
mf_init:
push ebx
push ecx
test eax,eax
jnz .noautodet
sub esp,1024
mov ebx,esp
mov ecx,-1
mov eax,9
int 0x40
mov eax,[esp+26]
add esp,1024
.noautodet:
add eax,15
and eax,not 15
mov [heapsmallblocks],eax
add eax,2048
mov [heapstart],eax
mov [heapfreelist],eax
mov [heaplastblock],eax
 
mov ecx,eax
if defined heapstartsize
add ecx,heapstartsize
else
add ecx,4096
end if
add ecx,4095
and ecx,not 4095
push eax
mov eax,64
mov ebx,1
int 0x40
pop eax
mov [eax+memblock.prevblock],dword 0
mov [heapend],ecx
mov [eax+memblock.size],ecx
sub [eax+memblock.size],eax
xor ebx,ebx
mov dword [eax+memblock.prevfreeblock],heapfreelist-memblock.nextfreeblock
mov [eax+memblock.nextfreeblock],ebx
mov [heapmutex],ebx
push edi
mov edi,[heapsmallblocks]
mov ecx,512
xor eax,eax
rep stosd
pop edi
pop ecx
pop ebx
ret
 
if defined multithread
heaplock:
push eax
push ebx
push ecx
mov eax,68
mov ebx,1
.loop:
xchg ecx,[heapmutex]
test ecx,ecx
jz .endloop
int 0x40 ;change task
jmp .loop
.endloop:
pop ecx
pop ebx
pop eax
ret
 
heapunlock:
mov [heapmutex],dword 0
ret
end if
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; heap_split_block ;;
;; Split free block to allocated block and free one. ;;
;; input: ;;
;; eax - size of allocated block ;;
;; ebx - block ;;
;; output: ;;
;; eax - real size of allocated block ;;
;; ebx - pointer to new block ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
heap_split_block:
push ecx
mov ecx,[ebx+memblock.size]
sub ecx,16
cmp ecx,eax
jge .norm
inc dword [ebx+memblock.size]
mov eax,ecx
xor ebx,ebx
pop ecx
ret
.norm:
add ecx,16
mov [ebx+memblock.size],eax
inc dword [ebx+memblock.size]
mov [ebx+eax+memblock.prevblock],ebx
add ebx,eax
sub ecx,eax
mov [ebx+memblock.size],ecx
mov ecx,eax
mov eax,ebx
call heap_fix_right
mov eax,ecx
pop ecx
ret
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; heap_add_free_block ;;
;; Add free block to one of free block lists. ;;
;; input: ;;
;; eax - address of free block ;;
;; output: ;;
;; none ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
heap_add_free_block:
cmp dword [eax+memblock.size],4096
push ebx
jge .bigblock
mov ebx,[eax+memblock.size]
shr ebx,1
add ebx,[heapsmallblocks]
push dword [ebx]
pop dword [eax+memblock.nextfreeblock]
mov [ebx],eax
mov dword [eax+memblock.prevfreeblock],ebx
sub dword [eax+memblock.prevfreeblock],memblock.nextfreeblock
mov ebx,[eax+memblock.nextfreeblock]
test ebx,ebx
jz .no_next_block
mov [ebx+memblock.prevfreeblock],eax
.no_next_block:
pop ebx
ret
.bigblock:
mov ebx,[heapfreelist]
mov [eax+memblock.nextfreeblock],ebx
mov [heapfreelist],eax
mov dword [eax+memblock.prevfreeblock],heapfreelist-memblock.nextfreeblock
; mov ebx,[eax+memblock.nextfreeblock]
test ebx,ebx
jz .no_next_big_block
mov [ebx+memblock.prevfreeblock],eax
.no_next_big_block:
pop ebx
ret
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; heap_remove_block ;;
;; Remove free block from the list of free blocks. ;;
;; input: ;;
;; eax - free block ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
heap_remove_block:
push ebx
push ecx
mov ecx,[eax+memblock.prevfreeblock]
mov ebx,[eax+memblock.nextfreeblock]
mov [ecx+memblock.nextfreeblock],ebx
test ebx,ebx
jz .no_next_block
mov [ebx+memblock.prevfreeblock],ecx
.no_next_block:
pop ecx
pop ebx
ret
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; mf_alloc
;; allocates a block of memory in heap
;; intput: eax: size of block
;; output: eax: address of allocated memory block or 0 if there's no mem.
;; allocator will not create new nodes that contain less that 8b of space,
;; and minimal allocation is actually 16 bytes - 8 for node and 8 for user.
;; allocator will never create non-aligned memory blocks.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
mf_alloc:
test eax,eax
jg .not_null ; test that we are not allocating null size block
xor eax,eax
ret
.not_null:
if defined multithread
call heaplock
end if
push edi
; push edx
push ecx
push ebx
add eax,7
and eax,not 7 ; make sure that block size is aligned
 
lea edi,[eax+8] ; desired block size
cmp edi,4096
jge .general_cycle
 
mov ebx,[heapsmallblocks]
xor ecx,ecx
shr edi,1
 
.smallloop:
cmp [ebx+edi],ecx
jnz .smallblockfound
add edi,4
cmp edi,2048
jl .smallloop
lea edi,[eax+8]
jmp .general_cycle
 
.smallblockfound:
lea ecx,[eax+8]
mov eax,[ebx+edi]
call heap_remove_block
mov ebx,eax
xchg eax,ecx
call heap_split_block
test ebx,ebx
jz .perfect_small_block
mov eax,ebx
call heap_add_free_block
.perfect_small_block:
lea eax,[ecx+8]
jmp .ret
 
.general_cycle:
;edi - size needed
mov eax,[heapfreelist]
 
.loop:
test eax,eax
jz .new_mem
cmp [eax+memblock.size],edi
jge .blockfound
mov eax,[eax+memblock.nextfreeblock]
jmp .loop
 
.blockfound:
call heap_remove_block
mov ebx,eax
mov ecx,eax
mov eax,edi
call heap_split_block
test ebx,ebx
jz .perfect_block
mov eax,ebx
call heap_add_free_block
.perfect_block:
lea eax,[ecx+8]
.ret:
if defined multithread
call heapunlock
end if
pop ebx
pop ecx
; pop edx
pop edi
ret
 
.new_mem:
mov eax,edi
add eax,4095
and eax,not 4095
mov ecx,[heapend]
add [heapend],eax
push eax
mov eax,64
push ebx
push ecx
mov ecx,[heapend]
mov ebx,1
int 0x40
pop ecx
pop ebx
pop eax
mov [ecx+memblock.size],eax
mov eax,[heaplastblock]
mov [ecx+memblock.prevblock],eax
mov [heaplastblock],ecx
mov eax,ecx
call heap_add_free_block
jmp .general_cycle
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; heap_fix_right ;;
;; input: ;;
;; eax - pointer to free block ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
heap_fix_right:
push ebx
mov ebx,eax
add ebx,[eax+memblock.size]
cmp ebx,[heapend]
jz .endblock
mov [ebx+memblock.prevblock],eax
pop ebx
ret
.endblock:
mov [heaplastblock],eax
pop ebx
ret
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; heap_merge_left ;;
;; input: ;;
;; eax - pointer to free block ;;
;; output: ;;
;; eax - pointer to merged block ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
heap_merge_left:
push ebx
mov ebx,[eax+memblock.prevblock]
test ebx,ebx
jz .ret
test byte [ebx+memblock.size],1
jnz .ret
xchg eax,ebx
call heap_remove_block
mov ebx,[ebx+memblock.size]
add [eax+memblock.size],ebx
call heap_fix_right
.ret:
pop ebx
ret
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; heap_merge_right ;;
;; input: ;;
;; eax - pointer to free block ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
heap_merge_right:
push ebx
mov ebx,eax
add ebx,[eax+memblock.size]
cmp ebx,[heapend]
jz .ret
test byte [ebx+memblock.size],1
jnz .ret
xchg eax,ebx
call heap_remove_block
xchg eax,ebx
mov ebx,[ebx+memblock.size]
add [eax+memblock.size],ebx
call heap_fix_right
.ret:
pop ebx
ret
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; mf_free ;;
;; input: ;;
;; eax - pointer ;;
;; output: ;;
;; eax=1 - ok ;;
;; eax=0 - failed ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
mf_free:
test eax,eax
jnz .no_null
inc eax
ret
.no_null:
if defined multithread
call heaplock
end if
sub eax,8
dec dword [eax+memblock.size]
call heap_merge_left
call heap_merge_right
call heap_add_free_block
.ret:
if defined multithread
call heapunlock
end if
ret
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; heap_try_reloc
;; input:
;; eax - address
;; ebx - new size
;; output:
;; ebx=1 - ok
;; ebx=0 - failed
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
heap_try_reloc:
push eax
sub eax,8
add ebx,15
dec dword [eax+memblock.size]
and ebx,not 7
cmp [eax+memblock.size],ebx
jge .truncate
push ebx
mov ebx,eax
add ebx,[eax+memblock.size]
cmp ebx,[heapend]
jz .fail ;todo: we can allocate new mem here
test [ebx+memblock.size],byte 1
jnz .fail
xchg eax,ebx
call heap_remove_block
mov eax,[eax+memblock.size]
add [ebx+memblock.size],eax
mov eax,ebx
call heap_fix_right
pop ebx
.truncate:
xchg eax,ebx
call heap_split_block
test ebx,ebx
jz .no_last_block
mov eax,ebx
call heap_add_free_block
call heap_merge_right
.no_last_block:
xor ebx,ebx
pop eax
inc ebx
ret
.fail:
pop ebx
xor ebx,ebx
pop eax
inc dword [eax-8+memblock.size]
ret
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; mf_realloc
;; input:
;; eax - pointer
;; ebx - new size
;; output:
;; eax - new pointer
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
mf_realloc:
push ebx
if defined multithread
call heaplock
end if
call heap_try_reloc
test ebx,ebx
jnz .ret
;allocate new memory
push eax
mov eax,[esp+4]
call mf_alloc
test eax,eax
jz .fail
push esi
push edi
push ecx
mov edi,eax
mov esi,[esp+12]
mov ecx,[esi-8+memblock.size]
shr ecx,2
rep movsd
pop ecx
pop edi
pop esi
xchg eax,[esp]
call mf_free
.fail:
pop eax
.ret:
if defined multithread
call heapunlock
end if
pop ebx
ret
;C entries
malloc:
mov eax,[esp+4]
call mf_alloc
ret
free:
mov eax,[esp+4]
call mf_free
ret
realloc:
mov edx,ebx
mov eax,[esp+4]
mov ebx,[esp+8]
call mf_realloc
mov ebx,edx
ret
section '.bss' writeable
heapsmallblocks rd 1
heapstart rd 1
heapend rd 1
heapfreelist rd 1
heapmutex rd 1
heaplastblock rd 1
/programs/develop/metcc/trunk/libc/mem
Property changes:
Added: svn:ignore
+*.o
+*.s
/programs/develop/metcc/trunk/libc/mesys/backgr.asm
0,0 → 1,58
format ELF
section '.text' executable
public _msys_set_background_size
_msys_set_background_size:
;arg1 - xsize
;arg2 - ysize
push ebx
mov ecx,[esp+8]
mov edx,[esp+12]
mov eax,15
mov ebx,1
int 0x40
pop ebx
ret 8
public _msys_write_background_mem
_msys_write_background_mem:
;arg1 - pos
;arg2 - color
push ebx
mov eax,15
mov ebx,2
mov ecx,[esp+8]
mov edx,[esp+12]
int 0x40
pop ebx
ret 8
public _msys_draw_background
_msys_draw_background:
mov edx,ebx
mov eax,15
mov ebx,3
int 0x40
mov ebx,edx
ret
public _msys_set_background_draw_type
_msys_set_background_draw_type:
;arg1 - type
mov edx,ebx
mov eax,15
mov ebx,4
mov ecx,[esp+4]
int 0x40
mov ebx,edx
ret 4
public _msys_background_blockmove
_msys_background_blockmove:
;arg1 - source
;arg2 - position in dest
;arg3 - size
push ebx esi
mov eax,15
mov ebx,5
mov ecx,[esp+12]
mov edx,[esp+16]
mov esi,[esp+20]
int 0x40
pop esi ebx
ret 12
/programs/develop/metcc/trunk/libc/mesys/button.asm
0,0 → 1,36
format ELF
section '.text' executable
public _msys_make_button
_msys_make_button:
;arg1 - x
;arg2 - y
;arg3 - xsize
;arg4 - ysize
;arg5 - id
;arg6 - color
push ebx esi
mov ebx,[esp+12]
shl ebx,16
mov bx,[esp+20]
mov ecx,[esp+16]
shl ecx,16
mov cx,[esp+24]
mov edx,[esp+28]
mov esi,[esp+32]
mov eax,8
int 0x40
pop esi ebx
ret 24
public _msys_get_button_id
_msys_get_button_id:
mov eax,17
int 0x40
test al,al
jnz .no_button
shr eax,8
ret
.no_button:
xor eax,eax
dec eax
ret
/programs/develop/metcc/trunk/libc/mesys/clock.asm
0,0 → 1,7
format ELF
section '.text' executable
public _msys_get_system_clock
_msys_get_system_clock:
mov eax,3
int 0x40
ret
/programs/develop/metcc/trunk/libc/mesys/date.asm
0,0 → 1,7
format ELF
section '.text' executable
public _msys_get_date
_msys_get_date:
mov eax,29
int 0x40
ret
/programs/develop/metcc/trunk/libc/mesys/debug_board.asm
0,0 → 1,13
format ELF
section '.text' executable
 
public _msys_debug_out
_msys_debug_out:
;arg1 - char to out
push ebx
mov ecx,[esp+8]
mov ebx,1
mov eax,63
int 0x40
pop ebx
ret 4
/programs/develop/metcc/trunk/libc/mesys/debug_board_.c
0,0 → 1,9
#include "mesys.h"
void debug_out_str(char* str)
{
while (*str!='\0')
{
_msys_debug_out(*str);
str++;
}
}
/programs/develop/metcc/trunk/libc/mesys/delay.asm
0,0 → 1,11
format ELF
section '.text' executable
public _msys_delay
_msys_delay:
;arg1 - time
mov edx,ebx
mov eax,5
mov ebx,[esp+4]
int 0x40
mov ebx,edx
ret 4
/programs/develop/metcc/trunk/libc/mesys/dga.asm
0,0 → 1,34
format ELF
section '.text' executable
public _msys_dga_get_resolution
_msys_dga_get_resolution:
;arg1 - *xres
;arg2 - *yres
;arg3 - *bpp
;arg4 - *bpscan
mov edx,ebx
mov eax,61
mov ebx,1
int 0x40
mov ebx,[esp+8]
mov [ebx],ax
mov word [ebx+2],0
shr eax,16
mov ebx,[esp+4]
mov [ebx],eax
mov eax,61
mov ebx,2
int 0x40
mov ebx,[esp+12]
mov [ebx],eax
mov eax,61
mov ebx,3
int 0x40
mov ebx,[esp+16]
mov [ebx],eax
mov ebx,edx
ret 16
/programs/develop/metcc/trunk/libc/mesys/draw_bar.asm
0,0 → 1,21
format ELF
section '.text' executable
public _msys_draw_bar
_msys_draw_bar:
;arg1 - x
;arg2 - y
;arg3 - xsize
;arg4 - ysize
;arg5 - color
push ebx
mov eax,13
mov ebx,[esp+8]
shl ebx,16
mov bx,[esp+16]
mov ecx,[esp+12]
shl ecx,16
mov cx,[esp+20]
mov edx,[esp+24]
int 0x40
pop ebx
ret 20
/programs/develop/metcc/trunk/libc/mesys/draw_image.asm
0,0 → 1,21
format ELF
section '.text' executable
public _msys_putimage
_msys_putimage:
;arg1 - x
;arg2 - y
;arg3 - xsize
;arg4 - ysize
;arg5 - image
push ebx
mov ebx,[esp+24]
mov ecx,[esp+16]
shl ecx,16
mov ecx,[esp+20]
mov ebx,[esp+8]
shl ebx,16
mov ebx,[esp+12]
mov eax,7
int 0x40
pop ebx
ret 20
/programs/develop/metcc/trunk/libc/mesys/draw_window.asm
0,0 → 1,35
format ELF
section '.text' executable
 
public _msys_draw_window
_msys_draw_window:
;arg1 - xcoord
;arg2 - ycoord
;arg3 - xsize
;arg4 - ysize
;arg5 - workcolor
;arg6 - type
;arg7 - captioncolor
;arg8 - windowtype
;arg9 - bordercolor
push ebp
mov ebp,esp
push ebx esi edi
mov ebx,[ebp+8]
shl ebx,16
mov bx,[ebp+16]
mov ecx,[ebp+12]
shl ecx,16
mov cx,[ebp+20]
mov edx,[ebp+28]
shl edx,24
add edx,[ebp+24]
mov esi,[ebp+36]
shl esi,24
add esi,[ebp+32]
mov edi,[ebp+40]
xor eax,eax
int 0x40
pop edi esi ebx
pop ebp
ret 36
/programs/develop/metcc/trunk/libc/mesys/event.asm
0,0 → 1,33
format ELF
section '.text' executable
public _msys_wait_for_event_infinite
_msys_wait_for_event_infinite:
mov eax,10
int 0x40
ret
public _msys_check_for_event
_msys_check_for_event:
mov eax,11
int 0x40
ret
public _msys_wait_for_event
_msys_wait_for_event:
;arg1 - time
mov edx,ebx
mov eax,23
mov ebx,[esp+4]
int 0x40
mov ebx,edx
ret 4
public _msys_set_wanted_events
_msys_set_wanted_events:
;arg1 - flags
mov edx,ebx
mov eax,40
mov ebx,[esp+4]
int 0x40
mov ebx,edx
ret 4
/programs/develop/metcc/trunk/libc/mesys/exit.asm
0,0 → 1,8
format ELF
section '.text' executable
public _msys_exit
_msys_exit:
xor eax,eax
dec eax
int 0x40
; ret
/programs/develop/metcc/trunk/libc/mesys/file_58.asm
0,0 → 1,110
format ELF
section '.text' executable
public _msys_read_file
_msys_read_file:
;arg1 - file name
;arg2 - file offset
;arg3 - size to read
;arg4 - data
;arg5 - file size
push ebp
mov ebp,esp
xor eax,eax
mov [file_struct.operation],eax
mov eax,[ebp+12]
mov [file_struct.offset],eax
mov eax,[ebp+16]
mov [file_struct.offset],eax
mov eax,[ebp+20]
mov [file_struct.offset],eax
mov [file_struct.temp_buffer],temp_buffer
mov edx,[ebp+8]
call copy_file_name
push ebx
mov ebx,file_struct
mov eax,58
int 0x40
mov ecx,[ebp+24]
test ecx,ecx
jz .no_file_size
mov [ecx],ebx
.no_file_size:
pop ebx
pop ebp
ret 20
 
copy_file_name:
push esi edi
cld
mov edi,edx
xor eax,eax
xor ecx,ecx
dec ecx
repnz scasb
not ecx
mov edi,file_struct.path
mov esi,edx
rep movsb
pop edi esi
ret
 
public _msys_write_file
_msys_write_file:
;arg1 - file name
;arg2 - size
;arg3 - data
push ebp
mov ebp,esp
xor eax,eax
mov [file_struct.offset],eax
inc eax
mov [file_struct.operation],eax
mov eax,[ebp+12]
mov [file_struct.size],eax
mov eax,[ebp+16]
mov [file_struct.data],eax
mov [file_struct.temp_buffer],temp_buffer
mov edx,[ebp+8]
call copy_file_name
push ebx
mov eax,58
mov ebx,file_struct
int 0x40
pop ebx
pop ebp
ret 12
 
public _msys_run_program
_msys_run_program:
;arg1 - program name
;arg2 - parameters
push ebp
mov ebp,esp
mov [file_struct.operation],16
xor eax,eax
mov [file_struct.offset],eax
mov [file_struct.data],eax
mov eax,[ebp+12]
mov [file_struct.param],eax
mov [file_struct.temp_buffer],temp_buffer;
mov edx,[ebp+8]
call copy_file_name
push ebx
mov eax,58
mov ebx,file_struct
int 0x40
pop ebx
pop ebp
ret 8
section '.bss' writeable
file_struct:
.operation rd 1
.offset rd 1
.param:
.size rd 1
.data rd 1
.temp_buffer rd 1
.path rb 1024
temp_buffer rb 4096
 
 
/programs/develop/metcc/trunk/libc/mesys/ipc.asm
0,0 → 1,29
format ELF
section '.text' executable
public _msys_send_message
_msys_send_message:
;arg1 - pid
;arg2 - msg
;arg3 - size
push ebx esi
mov eax,60
mov ebx,2
mov ecx,[esp+12]
mov edx,[esp+16]
mov esi,[esp+20]
int 0x40
pop esi ebx
ret 12
public _msys_define_receive_area
_msys_define_receive_area:
;arg1 - area
;arg2 - size
push ebx
mov eax,60
mov ebx,1
mov ecx,[esp+8]
mov edx,[esp+12]
int 0x40
pop ebx
ret 8
/programs/develop/metcc/trunk/libc/mesys/irq.asm
0,0 → 1,127
format ELF
section '.text' executable
public _msys_get_irq_owner
_msys_get_irq_owner:
;arg1 - irq
mov edx,ebx
mov eax,41
mov ebx,[esp+4]
int 0x40
mov ebx,edx
ret 4
public _msys_get_data_read_by_irq
_msys_get_data_read_by_irq:
;arg1 - irq
;arg2 - *size
;arg3 - data
mov edx,ebx
mov eax,42
mov ebx,[esp+4]
int 0x40
cmp ecx,2
jz .not_an_owner
push ecx
mov ecx,[esp+16]
test ecx,ecx
jz .ignore_data
mov [ecx],bl
.ignore_data:
mov ecx,[esp+12]
mov [ecx],eax
pop eax
mov ebx,edx
ret 12
.not_an_owner:
mov eax,2
mov ebx,edx
ret
public _msys_send_data_to_device
_msys_send_data_to_device:
;arg1 - port
;arg2 - data
mov edx,ebx
mov eax,63
mov ebx,[esp+8]
mov ecx,[esp+4]
int 0x40
mov ebx,edx
ret 8
public _msys_receive_data_from_device
_msys_receive_data_from_device:
;arg1 - port
;arg2 - data
mov edx,ebx
mov eax,43
mov ecx,[esp+4]
add ecx,0x80000000
int 0x40
mov ecx,[esp+8]
mov [ecx],bl
mov ebx,edx
ret 8
public _msys_program_irq
_msys_program_irq:
;arg1 - intrtable
;arg2 - irq
mov edx,ebx
mov eax,44
mov ebx,[esp+4]
mov ecx,[esp+8]
int 0x40
mov ebx,edx
ret 8
public _msys_reserve_irq
_msys_reserve_irq:
;arg1 - irq
mov edx,ebx
mov eax,45
xor ebx,ebx
mov ecx,[esp+4]
int 0x40
mov ebx,edx
ret 4
public _msys_free_irq
_msys_free_irq:
;arg1 - irq
mov edx,ebx
mov eax,45
xor ebx,ebx
inc ebx
mov ecx,[esp+4]
int 0x40
mov ebx,edx
ret 4
public _msys_reserve_port_area
_msys_reserve_port_area:
;arg1 - start
;arg2 - end
push ebx
mov eax,46
xor ebx,ebx
mov ecx,[esp+8]
mov edx,[esp+12]
int 0x40
pop ebx
ret 8
public _msys_free_port_area
_msys_free_port_area:
;arg1 - start
;arg2 - end
push ebx
mov eax,46
xor ebx,ebx
inc ebx
mov ecx,[esp+8]
mov edx,[esp+12]
int 0x40
pop ebx
ret 8
/programs/develop/metcc/trunk/libc/mesys/keyboard.asm
0,0 → 1,18
format ELF
section '.text' executable
public _msys_get_key
_msys_get_key:
mov eax,2
int 0x40
ret
public _msys_set_keyboard_mode
_msys_set_keyboard_mode:
;arg1 - mode
mov edx,ebx
mov eax,66
xor ebx,ebx
inc ebx
mov ecx,[esp+4]
mov ebx,edx
ret 4
/programs/develop/metcc/trunk/libc/mesys/line.asm
0,0 → 1,21
format ELF
section '.text' executable
public _msys_line
_msys_line:
;arg1 - x1
;arg2 - y1
;arg3 - x2
;arg4 - y2
;arg5 - color
push ebx
mov ebx,[esp+8]
shl ebx,16
mov bx,[esp+16]
mov ecx,[esp+12]
shl ecx,16
mov cx,[esp+20]
mov edx,[esp+24]
mov eax,38
int 0x40
pop ebx
ret 20
/programs/develop/metcc/trunk/libc/mesys/midi.asm
0,0 → 1,22
format ELF
section '.text' executable
public _msys_midi_reset
_msys_midi_reset:
mov edx,ebx
mov eax,20
xor ebx,ebx
inc ebx
int 0x40
mov ebx,edx
ret
public _msys_midi_send
_msys_midi_send:
;arg1 - data
mov edx,ebx
mov eax,20
mov ebx,2
xor ecx,ecx
mov cl,[esp+4]
mov ebx,edx
ret 4
/programs/develop/metcc/trunk/libc/mesys/pci.asm
0,0 → 1,146
format ELF
section '.text' executable
public _msys_get_pci_version
_msys_get_pci_version:
mov edx,ebx
mov eax,62
xor ebx,ebx
int 0x40
movzx eax,ax
mov ebx,edx
ret
public _msys_get_last_pci_bus
_msys_get_last_pci_bus:
mov edx,ebx
mov eax,62
xor ebx,ebx
inc ebx
int 0x40
movzx eax,al
mov ebx,edx
ret
public _msys_get_pci_access_mechanism
_msys_get_pci_access_mechanism:
mov edx,ebx
mov eax,62
mov ebx,2
int 0x40
movzx eax,al
mov ebx,edx
ret
public _msys_pci_read_config_byte
_msys_pci_read_config_byte:
;arg1 - bus
;arg2 - dev
;arg3 - fn
;arg4 - reg
mov edx,ebx
mov eax,62
mov bl,4
mov bh,[esp+4]
mov ch,[esp+8]
shl ch,3
add ch,[esp+12]
mov cl,[esp+16]
int 0x40
mov ebx,edx
ret 16
public _msys_pci_read_config_word
_msys_pci_read_config_word:
;arg1 - bus
;arg2 - dev
;arg3 - fn
;arg4 - reg
mov edx,ebx
mov eax,62
mov bl,5
mov bh,[esp+4]
mov ch,[esp+8]
shl ch,3
add ch,[esp+12]
mov cl,[esp+16]
int 0x40
mov ebx,edx
ret 16
public _msys_pci_read_config_dword
_msys_pci_read_config_dword:
;arg1 - bus
;arg2 - dev
;arg3 - fn
;arg4 - reg
mov edx,ebx
mov eax,62
mov bl,6
mov bh,[esp+4]
mov ch,[esp+8]
shl ch,3
add ch,[esp+12]
mov cl,[esp+16]
int 0x40
mov ebx,edx
ret 16
public _msys_pci_write_config_byte
_msys_pci_write_config_byte:
;arg1 - bus
;arg2 - dev
;arg3 - fn
;arg4 - reg
;arg5 - value
push ebx
mov eax,62
mov bl,8
mov bh,[esp+8]
mov ch,[esp+12]
shl ch,3
mov ch,[esp+16]
mov cl,[esp+20]
movzx edx,byte [esp+24]
int 0x40
pop ebx
ret 20
public _msys_pci_write_config_word
_msys_pci_write_config_word:
;arg1 - bus
;arg2 - dev
;arg3 - fn
;arg4 - reg
;arg5 - value
push ebx
mov eax,62
mov bl,9
mov bh,[esp+8]
mov ch,[esp+12]
shl ch,3
mov ch,[esp+16]
mov cl,[esp+20]
movzx edx,word [esp+24]
int 0x40
pop ebx
ret 20
public _msys_pci_write_config_dword
_msys_pci_write_config_dword:
;arg1 - bus
;arg2 - dev
;arg3 - fn
;arg4 - reg
;arg5 - value
push ebx
mov eax,62
mov bl,10
mov bh,[esp+8]
mov ch,[esp+12]
shl ch,3
mov ch,[esp+16]
mov cl,[esp+20]
mov edx,[esp+24]
int 0x40
pop ebx
ret 20
/programs/develop/metcc/trunk/libc/mesys/pixel.asm
0,0 → 1,16
format ELF
section '.text' executable
public _msys_putpixel
_msys_putpixel:
;arg1 - x
;arg2 - y
;arg3 - color
push ebx
xor eax,eax
mov ebx,[esp+8]
inc eax
mov ecx,[esp+12]
mov edx,[esp+16]
int 0x40
pop ebx
ret 12
/programs/develop/metcc/trunk/libc/mesys/process.asm
0,0 → 1,13
format ELF
section '.text' executable
public _msys_get_process_table
_msys_get_process_table:
;arg1 - pointer to information
;arg2 - pid
mov edx,ebx
mov eax,9
mov ebx,[esp+4]
mov ecx,[esp+8]
int 0x40
mov ebx,edx
ret 8
/programs/develop/metcc/trunk/libc/mesys/screen.asm
0,0 → 1,15
format ELF
section '.text' executable
public _msys_get_screen_size
_msys_get_screen_size:
;arg1 - x
;arg2 - y
mov eax,14
int 0x40
mov ecx,[esp+8]
mov [ecx],ax
mov word [ecx+2],0
shr eax,16
mov ecx,[esp+4]
mov [ecx],eax
ret 8
/programs/develop/metcc/trunk/libc/mesys/sound.asm
0,0 → 1,70
format ELF
section '.text' executable
public _msys_sound_load_block
_msys_sound_load_block:
;arg1 - blockptr
mov edx,ebx
mov eax,55
xor ebx,ebx
mov ecx,[esp+4]
int 0x40
mov ebx,edx
ret 4
public _msys_sound_play_block
_msys_sound_play_block:
mov edx,ebx
mov eax,55
xor ebx,ebx
inc ebx
int 0x40
mov ebx,edx
ret
public _msys_sound_set_channels
_msys_sound_set_channels:
;arg1 - channels
push ebx
mov eax,55
mov ebx,2
xor ecx,ecx
mov edx,[esp+8]
int 0x40
pop ebx
ret 4
public _msys_sound_set_data_size
_msys_sound_set_data_size:
;arg1 - data size
push ebx
mov eax,55
mov ebx,2
xor ecx,ecx
inc ecx
mov edx,[esp+8]
int 0x40
pop ebx
ret 4
public _msys_sound_set_frequency
_msys_sound_set_frequency:
;arg1 - frequency
push ebx
mov eax,55
mov ebx,2
mov ecx,2
mov edx,[esp+8]
int 0x40
pop ebx
ret 4
public _msys_sound_speaker_play
_msys_sound_speaker_play:
;arg1 - data
mov edx,ebx
mov eax,55
mov ebx,55
mov ecx,[esp+4]
int 0x40
mov ebx,edx
ret 4
/programs/develop/metcc/trunk/libc/mesys/thread.asm
0,0 → 1,33
format ELF
section '.text' executable
extrn malloc
public _msys_start_thread
_msys_start_thread:
;arg1 - proc
;arg2 - stacksize
;arg3 - pid
push dword [esp+8]
call malloc
test eax,eax
jz .no_mem
push ebx
mov edx,eax
add edx,[esp+12]
mov [edx-4],dword 0
mov ecx,[esp+8]
mov ebx,1
mov eax,51
int 0x40
mov ebx,[esp+16]
test ebx,ebx
jz .no_val
mov [ebx],eax
.no_val:
mov eax,edx
sub eax,[esp+12]
pop ebx
ret 12
.no_mem:
mov ecx,[esp+12]
mov [ecx],eax
ret 12
/programs/develop/metcc/trunk/libc/mesys/window_redraw.asm
0,0 → 1,11
format ELF
section '.text' executable
public _msys_window_redraw
_msys_window_redraw:
;arg1 - status
mov edx,ebx
mov eax,12
mov ebx,[esp+4]
int 0x40
mov ebx,edx
ret 4
/programs/develop/metcc/trunk/libc/mesys/write_text.asm
0,0 → 1,20
format ELF
section '.text' executable
public _msys_write_text
_msys_write_text:
;arg1 - x
;arg2 - y
;arg3 - color
;arg4 - text
;arg5 - len
push ebx esi
mov eax,4
mov ebx,[esp+12]
shl ebx,16
mov bx,[esp+16]
mov ecx,[esp+20]
mov edx,[esp+24]
mov esi,[esp+28]
int 0x40
pop esi ebx
ret 20
/programs/develop/metcc/trunk/libc/mesys
Property changes:
Added: svn:ignore
+*.o
+*.s
/programs/develop/metcc/trunk/libc/start/start.asm
0,0 → 1,130
format ELF
section '.text' executable
public start
extrn mf_init
extrn main
;include 'debug2.inc'
__DEBUG__=0
virtual at 0
db 'MENUET01' ; 1. Magic number (8 bytes)
dd 0x01 ; 2. Version of executable file
dd 0x0 ; 3. Start address
dd 0x0 ; 4. Size of image
dd 0x100000 ; 5. Size of needed memory
dd 0x100000 ; 6. Pointer to stack
hparams dd 0x0 ; 7. Pointer to program arguments
hpath dd 0x0 ; 8. Pointer to program path
end virtual
start:
;DEBUGF 'Start programm\n'
xor eax,eax
call mf_init
;DEBUGF ' path "%s"\n params "%s"\n', .path, .params
; check for overflow
mov al, [path+buf_len-1]
or al, [params+buf_len-1]
jnz .crash
; check if path written by OS
mov eax, [hparams]
test eax, eax
jz .without_path
mov eax, path
.without_path:
mov esi, eax
call push_param
; retrieving parameters
mov esi, params
xor edx, edx ; dl - èä¸ò ïàðàìåòð(1) èëè ðàçäåëèòåëè(0)
; dh - ñèìâîë ñ êîòîðîãî íà÷àëñÿ ïàðàìåòð (1 êàâû÷êè, 0 îñòàëüíîå)
mov ecx, 1 ; cl = 1
; ch = 0 ïðîñòî íîëü
.parse:
lodsb
test al, al
jz .run
test dl, dl
jnz .findendparam
;{åñëè áûë ðàçäåëèòåëü
cmp al, ' '
jz .parse ;çàãðóæåí ïðîáåë, ãðóçèì ñëåäóþùèé ñèìâîë
mov dl, cl ;íà÷èíàåòñÿ ïàðàìåòð
cmp al, '"'
jz @f ;çàãðóæåíû êàâû÷êè
mov dh, ch ;ïàðàìåòð áåç êàâû÷åê
dec esi
call push_param
inc esi
jmp .parse
 
@@:
mov dh, cl ;ïàðàìåòð â êàâû÷åêàõ
call push_param ;åñëè íå ïðîáåë çíà÷èò íà÷èíàåòñÿ êàêîé òî ïàðàìåòð
jmp .parse ;åñëè áûë ðàçäåëèòåëü}
 
.findendparam:
test dh, dh
jz @f ; áåç êàâû÷åê
cmp al, '"'
jz .clear
jmp .parse
@@:
cmp al, ' '
jnz .parse
 
.clear:
lea ebx, [esi - 1]
mov [ebx], ch
mov dl, ch
jmp .parse
 
.run:
;DEBUGF 'call main(%x, %x) with params:\n', [argc], argv
if __DEBUG__ = 1
mov ecx, [argc]
@@:
lea esi, [ecx * 4 + argv-4]
DEBUGF '0x%x) "%s"\n', cx, [esi]
loop @b
end if
push [argc]
push argv
call main
.exit:
;DEBUGF 'Exit from prog\n';
xor eax,eax
dec eax
int 0x40
dd -1
.crash:
;DEBUGF 'E:buffer overflowed\n'
jmp .exit
;============================
push_param:
;============================
;parameters
; esi - pointer
;description
; procedure increase argc
; and add pointer to array argv
; procedure changes ebx
mov ebx, [argc]
cmp ebx, max_parameters
jae .dont_add
mov [argv+4*ebx], esi
inc [argc]
.dont_add:
ret
;==============================
public params as '__argv'
public path as '__path'
 
section '.bss'
buf_len = 0x400
max_parameters=0x20
argc rd 1
argv rd max_parameters
path rb buf_len
params rb buf_len
 
;section '.data'
;include_debug_strings ; ALWAYS present in data section
/programs/develop/metcc/trunk/libc/start
Property changes:
Added: svn:ignore
+*.o
+*.s
/programs/develop/metcc/trunk/libc/string/_mesys.asm
0,0 → 1,156
format ELF
section '.text' executable
 
public _msys_draw_window
_msys_draw_window:
;arg1 - xcoord
;arg2 - ycoord
;arg3 - xsize
;arg4 - ysize
;arg5 - workcolor
;arg6 - type
;arg7 - captioncolor
;arg8 - windowtype
;arg9 - bordercolor
push ebp
mov ebp,esp
push ebx esi edi
mov ebx,[ebp+8]
shl ebx,16
mov bx,[ebp+16]
mov ecx,[ebp+12]
shl ecx,16
mov cx,[ebp+20]
mov edx,[ebp+28]
shl edx,24
add edx,[ebp+24]
mov esi,[ebp+36]
shl esi,24
add esi,[ebp+32]
mov edi,[ebp+40]
xor eax,eax
int 0x40
pop edi esi ebx
pop ebp
ret
 
public _msys_read_file
_msys_read_file:
;arg1 - file name
;arg2 - file offset
;arg3 - size to read
;arg4 - data
;arg5 - temp buffer
;arg6 - file size
push ebp
mov ebp,esp
xor eax,eax
mov [file_struct.operation],eax
mov eax,[ebp+12]
mov [file_struct.offset],eax
mov eax,[ebp+16]
mov [file_struct.offset],eax
mov eax,[ebp+20]
mov [file_struct.offset],eax
mov [file_struct.temp_buffer],temp_buffer
mov edx,[ebp+8]
call copy_file_name
push ebx
mov ebx,file_struct
mov eax,58
int 0x40
mov ecx,[ebp+28]
test ecx,ecx
jz .no_file_size
mov [ecx],ebx
.no_file_size:
pop ebx
pop ebp
ret
 
copy_file_name:
push esi edi
cld
mov edi,edx
xor eax,eax
xor ecx,ecx
dec ecx
repnz scasb
not ecx
mov edi,file_struct.path
mov esi,edx
rep movsb
pop edi esi
ret
 
public _msys_write_file
_msys_write_file:
;arg1 - file name
;arg2 - size
;arg3 - data
push ebp
mov ebp,esp
xor eax,eax
mov [file_struct.offset],eax
inc eax
mov [file_struct.operation],eax
mov eax,[ebp+12]
mov [file_struct.size],eax
mov eax,[ebp+16]
mov [file_struct.data],eax
mov [file_struct.temp_buffer],temp_buffer
mov edx,[ebp+8]
call copy_file_name
push ebx
mov eax,58
mov ebx,file_struct
int 0x40
pop ebx
pop ebp
ret
 
public _msys_run_program
_msys_run_program:
;arg1 - program name
;arg2 - parameters
push ebp
mov ebp,esp
mov [file_struct.operation],16
xor eax,eax
mov [file_struct.offset],eax
mov [file_struct.data],eax
mov eax,[ebp+12]
mov [file_struct.param],eax
mov [file_struct.temp_buffer],temp_buffer;
mov edx,[ebp+8]
call copy_file_name
push ebx
mov eax,58
mov ebx,file_struct
int 0x40
pop ebx
pop ebp
ret
 
public _msys_debug_out
_msys_debug_out:
;arg1 - char to out
push ebx
mov ecx,[esp+8]
mov ebx,1
mov eax,63
int 0x40
pop ebx
ret
section '.data' writeable
section '.bss' writeable
file_struct:
.operation rd 1
.offset rd 1
.param:
.size rd 1
.data rd 1
.temp_buffer rd 1
.path rb 1024
temp_buffer rb 4096
/programs/develop/metcc/trunk/libc/string/memchr.c
0,0 → 1,10
void* memchr(const void* buf,int c,int count)
{
int i;
for (i=0;i<count;i++)
if (*(char*)buf==c)
return (void*)buf;
else
buf++;
return (void*)0;
}
/programs/develop/metcc/trunk/libc/string/memcmp.c
0,0 → 1,13
typedef unsigned char uc;
int memcmp(const void* buf1,const void* buf2,int count)
{
int i;
for (i=0;i<count;i++)
{
if (*(uc*)buf1<*(uc*)buf2)
return -1;
if (*(uc*)buf1>*(uc*)buf2)
return 1;
}
return 0;
}
/programs/develop/metcc/trunk/libc/string/memmove.asm
0,0 → 1,16
format ELF
section '.text' executable
public memcpy
public memmove
memcpy:
memmove:
push esi edi
mov edi,[esp+12]
mov esi,[esp+16]
mov ecx,[esp+20]
jecxz .no_copy
cld
rep movsb
.no_copy:
pop edi esi
ret
/programs/develop/metcc/trunk/libc/string/memset.asm
0,0 → 1,15
format ELF
section '.text' executable
public memset
memset:
push edi
mov edi,[esp+8]
mov eax,[esp+12]
mov ecx,[esp+16]
jecxz .no_set
cld
rep stosb
.no_set:
pop edi
ret
/programs/develop/metcc/trunk/libc/string/strcat.c
0,0 → 1,13
char* strcat(char* strDest, const char* strSource)
{
char* res;
res=strDest;
while (*strDest!='\0') strDest++;
while (*strSource!='\0')
{
*strDest=*strSource;
strDest++;
strSource++;
}
return res;
}
/programs/develop/metcc/trunk/libc/string/strchr.c
0,0 → 1,10
char* strchr(const char* string, int c)
{
while (*string!='\0')
{
if (*string==c)
return (char*)string;
string++;
}
return (char*)0;
}
/programs/develop/metcc/trunk/libc/string/strcmp.c
0,0 → 1,14
int strcmp(const char* string1, const char* string2)
{
while (1)
{
if (*string1<*string2)
return -1;
if (*string1>*string2)
return 1;
if (*string1=='\0')
return 0;
string1++;
string2++;
}
}
/programs/develop/metcc/trunk/libc/string/strcoll.c
0,0 → 1,4
int strcoll(const char* string1,const char* string2)
{
return strcmp(string1,string2);
}
/programs/develop/metcc/trunk/libc/string/strcpy.c
0,0 → 1,14
char* strcpy(char* strDest,char* strSource)
{
char* res;
res=strDest;
while(1)
{
*strDest=*strSource;
if (*strSource=='\0')
break;
strDest++;
strSource++;
}
return res;
}
/programs/develop/metcc/trunk/libc/string/strcspn.c
0,0 → 1,17
int strcspn(const char* string, const char* strCharSet)
{
const char* temp;
int i;
i=0;
while(1)
{
temp=strCharSet;
while (*temp!='\0')
{
if (*string==*temp)
return i;
temp++;
}
i++;string++;
}
}
/programs/develop/metcc/trunk/libc/string/strdup.c
0,0 → 1,9
char* strdup(char* str)
{
char* res;
int len;
len=strlen(str)+1;
res=malloc(len);
memcpy(res,str,len);
return res;
}
/programs/develop/metcc/trunk/libc/string/strerror.c
0,0 → 1,4
char* strerror(int err)
{
return (char*)0;
}
/programs/develop/metcc/trunk/libc/string/strlen.c
0,0 → 1,11
int strlen(const char* string)
{
int i;
i=0;
while (*string!='\0')
{
i++;
string++;
}
return i;
}
/programs/develop/metcc/trunk/libc/string/strnbrk.c
0,0 → 1,16
char* strpbrk(const char* string, const char* strCharSet)
{
char* temp;
while (*string!='\0')
{
temp=strCharSet;
while (*temp!='\0')
{
if (*string==*temp)
return string;
temp++;
}
string++;
}
return (char*)0;
}
/programs/develop/metcc/trunk/libc/string/strncat.c
0,0 → 1,14
char* strncat(char* strDest,const char* strSource,int count)
{
char* res;
res=strDest;
while (*strDest!='\0') strDest++;
while (count>0 && *strSource!='\0')
{
*strDest=*strSource;
count--;
strDest++;
strSource++;
}
return res;
}
/programs/develop/metcc/trunk/libc/string/strncmp.c
0,0 → 1,14
int strncmp(const char* string1, const char* string2, int count)
{
while(count>0)
{
if (*string1<*string2)
return -1;
if (*string1>*string2)
return 1;
if (*string1=='\0')
return 0;
count--;
}
return 0;
}
/programs/develop/metcc/trunk/libc/string/strncpy.c
0,0 → 1,14
char* strncpy(char* strDest,const char* strSource,int count)
{
char* res;
res=strDest;
while (count>0)
{
*strDest=*strSource;
if (*strSource!='\0')
strSource++;
strDest++;
count--;
}
return res;
}
/programs/develop/metcc/trunk/libc/string/strrchr.c
0,0 → 1,14
char* strrchr(const char* s,int c)
{
char* res;
res=(char*)0;
while (1)
{
if (*s==(char)c)
res=(char*)s;
if (*s=='\0')
break;
s++;
}
return res;
}
/programs/develop/metcc/trunk/libc/string/strspn.c
0,0 → 1,20
int strspn(const char* string,const char* strCharSet)
{
int i;
const char* temp;
i=0;
while (*string!='\0')
{
temp=strCharSet;
while (temp!='\0')
{
if (*temp==*string)
break;
}
if (temp=='\0')
break;
*string++;
i++;
}
return i;
}
/programs/develop/metcc/trunk/libc/string/strstr.c
0,0 → 1,13
extern int strncmp(char* s1,char* s2,int len);
char* strstr(const char* s, const char* find)
{
int len;
len=strlen(find);
while (1)
{
if (strncmp(s,find,len)==0) return s;
if (*s=='\0')
return (char*) 0;
s++;
}
}
/programs/develop/metcc/trunk/libc/string/strtok.c
0,0 → 1,14
#include "string.h"
char* strtok(char* s,const char* delim)
{
char* res;
if (*s=='\0')
return (char*)0;
s+=strspn(s,delim);
if (*s=='\0')
return (char*)0;
res=s;
s+=strcspn(s,delim);
*s=='\0';
return res;
}
/programs/develop/metcc/trunk/libc/string/strxfrm.c
0,0 → 1,4
int strxfrm(char* strDest, const char* strSource, int count)
{
return 0;
}
/programs/develop/metcc/trunk/libc/string
Property changes:
Added: svn:ignore
+*.o
+*.s
/programs/develop/metcc/trunk/libc
Property changes:
Added: svn:ignore
+*.a
+script.txt
/programs/develop/metcc/trunk/readme.txt
0,0 → 1,4
The main file of metcc is "tcc.c". It certainly can be compiled by MinGW Studio.
In order to compile MenuetOS program you must have start.o, metcc.exe in the same
directory. The command line should be of type "metcc.exe program.c melibc.a -oprogram".
In order to compile "melibc.a" you should configure paths is compile.js and run it.
/programs/develop/metcc/trunk/source/COPYING
0,0 → 1,504
GNU LESSER GENERAL PUBLIC LICENSE
Version 2.1, February 1999
 
Copyright (C) 1991, 1999 Free Software Foundation, Inc.
59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
 
[This is the first released version of the Lesser GPL. It also counts
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the version number 2.1.]
 
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This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
 
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
Also add information on how to contact you by electronic and paper mail.
 
You should also get your employer (if you work as a programmer) or your
school, if any, to sign a "copyright disclaimer" for the library, if
necessary. Here is a sample; alter the names:
 
Yoyodyne, Inc., hereby disclaims all copyright interest in the
library `Frob' (a library for tweaking knobs) written by James Random Hacker.
 
<signature of Ty Coon>, 1 April 1990
Ty Coon, President of Vice
 
That's all there is to it!
 
 
/programs/develop/metcc/trunk/source/VERSION
0,0 → 1,0
0.9.23
/programs/develop/metcc/trunk/source/arm-gen.c
0,0 → 1,1386
/*
* ARMv4 code generator for TCC
*
* Copyright (c) 2003 Daniel Glöckner
*
* Based on i386-gen.c by Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
 
/* number of available registers */
#define NB_REGS 9
 
/* a register can belong to several classes. The classes must be
sorted from more general to more precise (see gv2() code which does
assumptions on it). */
#define RC_INT 0x0001 /* generic integer register */
#define RC_FLOAT 0x0002 /* generic float register */
#define RC_R0 0x0004
#define RC_R1 0x0008
#define RC_R2 0x0010
#define RC_R3 0x0020
#define RC_R12 0x0040
#define RC_F0 0x0080
#define RC_F1 0x0100
#define RC_F2 0x0200
#define RC_F3 0x0400
#define RC_IRET RC_R0 /* function return: integer register */
#define RC_LRET RC_R1 /* function return: second integer register */
#define RC_FRET RC_F0 /* function return: float register */
 
/* pretty names for the registers */
enum {
TREG_R0 = 0,
TREG_R1,
TREG_R2,
TREG_R3,
TREG_R12,
TREG_F0,
TREG_F1,
TREG_F2,
TREG_F3,
};
 
int reg_classes[NB_REGS] = {
/* r0 */ RC_INT | RC_R0,
/* r1 */ RC_INT | RC_R1,
/* r2 */ RC_INT | RC_R2,
/* r3 */ RC_INT | RC_R3,
/* r12 */ RC_INT | RC_R12,
/* f0 */ RC_FLOAT | RC_F0,
/* f1 */ RC_FLOAT | RC_F1,
/* f2 */ RC_FLOAT | RC_F2,
/* f3 */ RC_FLOAT | RC_F3,
};
 
static int two2mask(int a,int b) {
return (reg_classes[a]|reg_classes[b])&~(RC_INT|RC_FLOAT);
}
 
static int regmask(int r) {
return reg_classes[r]&~(RC_INT|RC_FLOAT);
}
 
/* return registers for function */
#define REG_IRET TREG_R0 /* single word int return register */
#define REG_LRET TREG_R1 /* second word return register (for long long) */
#define REG_FRET TREG_F0 /* float return register */
 
/* defined if function parameters must be evaluated in reverse order */
#define INVERT_FUNC_PARAMS
 
/* defined if structures are passed as pointers. Otherwise structures
are directly pushed on stack. */
//#define FUNC_STRUCT_PARAM_AS_PTR
 
/* pointer size, in bytes */
#define PTR_SIZE 4
 
/* long double size and alignment, in bytes */
#define LDOUBLE_SIZE 8
#define LDOUBLE_ALIGN 4
/* maximum alignment (for aligned attribute support) */
#define MAX_ALIGN 8
 
#define CHAR_IS_UNSIGNED
 
/******************************************************/
/* ELF defines */
 
#define EM_TCC_TARGET EM_ARM
 
/* relocation type for 32 bit data relocation */
#define R_DATA_32 R_ARM_ABS32
#define R_JMP_SLOT R_ARM_JUMP_SLOT
#define R_COPY R_ARM_COPY
 
#define ELF_START_ADDR 0x00008000
#define ELF_PAGE_SIZE 0x1000
 
/******************************************************/
static unsigned long func_sub_sp_offset,last_itod_magic;
 
void o(unsigned long i)
{
/* this is a good place to start adding big-endian support*/
int ind1;
 
ind1 = ind + 4;
if (!cur_text_section)
error("compiler error! This happens f.ex. if the compiler\n"
"can't evaluate constant expressions outside of a function.");
if (ind1 > cur_text_section->data_allocated)
section_realloc(cur_text_section, ind1);
cur_text_section->data[ind++] = i&255;
i>>=8;
cur_text_section->data[ind++] = i&255;
i>>=8;
cur_text_section->data[ind++] = i&255;
i>>=8;
cur_text_section->data[ind++] = i;
}
 
static unsigned long stuff_const(unsigned long op,unsigned long c)
{
int try_neg=0;
unsigned long nc = 0,negop = 0;
 
switch(op&0x1F00000)
{
case 0x800000: //add
case 0x400000: //sub
try_neg=1;
negop=op^0xC00000;
nc=-c;
break;
case 0x1A00000: //mov
case 0x1E00000: //mvn
try_neg=1;
negop=op^0x400000;
nc=~c;
break;
case 0x200000: //xor
if(c==~0)
return (op&0xF010F000)|((op>>16)&0xF)|0x1E00000;
break;
case 0x0: //and
if(c==~0)
return (op&0xF010F000)|((op>>16)&0xF)|0x1A00000;
case 0x1C00000: //bic
try_neg=1;
negop=op^0x1C00000;
nc=~c;
break;
case 0x1800000: //orr
if(c==~0)
return (op&0xFFF0FFFF)|0x1E00000;
break;
}
do {
unsigned long m;
int i;
if(c<256) /* catch undefined <<32 */
return op|c;
for(i=2;i<32;i+=2) {
m=(0xff>>i)|(0xff<<(32-i));
if(!(c&~m))
return op|(i<<7)|(c<<i)|(c>>(32-i));
}
op=negop;
c=nc;
} while(try_neg--);
return 0;
}
 
 
//only add,sub
void stuff_const_harder(unsigned long op,unsigned long v) {
unsigned long x;
x=stuff_const(op,v);
if(x)
o(x);
else {
unsigned long a[16],nv,no,o2,n2;
int i,j,k;
a[0]=0xff;
o2=(op&0xfff0ffff)|((op&0xf000)<<4);;
for(i=1;i<16;i++)
a[i]=(a[i-1]>>2)|(a[i-1]<<30);
for(i=0;i<12;i++)
for(j=i+4;i<13+i;i++)
if((v&(a[i]|a[j]))==v) {
o(stuff_const(op,v&a[i]));
o(stuff_const(o2,v&a[j]));
return;
}
no=op^0xC00000;
n2=o2^0xC00000;
nv=-v;
for(i=0;i<12;i++)
for(j=i+4;i<13+i;i++)
if((nv&(a[i]|a[j]))==nv) {
o(stuff_const(no,nv&a[i]));
o(stuff_const(n2,nv&a[j]));
return;
}
for(i=0;i<8;i++)
for(j=i+4;i<12;i++)
for(k=j+4;k<13+i;i++)
if((v&(a[i]|a[j]|a[k]))==v) {
o(stuff_const(op,v&a[i]));
o(stuff_const(o2,v&a[j]));
o(stuff_const(o2,v&a[k]));
return;
}
no=op^0xC00000;
nv=-v;
for(i=0;i<8;i++)
for(j=i+4;i<12;i++)
for(k=j+4;k<13+i;i++)
if((nv&(a[i]|a[j]|a[k]))==nv) {
o(stuff_const(no,nv&a[i]));
o(stuff_const(n2,nv&a[j]));
o(stuff_const(n2,nv&a[k]));
return;
}
o(stuff_const(op,v&a[0]));
o(stuff_const(o2,v&a[4]));
o(stuff_const(o2,v&a[8]));
o(stuff_const(o2,v&a[12]));
}
}
 
unsigned long encbranch(int pos,int addr,int fail)
{
addr-=pos+8;
addr/=4;
if(addr>=0x1000000 || addr<-0x1000000) {
if(fail)
error("FIXME: function bigger than 32MB");
return 0;
}
return 0x0A000000|(addr&0xffffff);
}
 
int decbranch(int pos)
{
int x;
x=*(int *)(cur_text_section->data + pos);
x&=0x00ffffff;
if(x&0x800000)
x-=0x1000000;
return x*4+pos+8;
}
 
/* output a symbol and patch all calls to it */
void gsym_addr(int t, int a)
{
unsigned long *x;
int lt;
while(t) {
x=(unsigned long *)(cur_text_section->data + t);
t=decbranch(lt=t);
if(a==lt+4)
*x=0xE1A00000; // nop
else {
*x &= 0xff000000;
*x |= encbranch(lt,a,1);
}
}
}
 
void gsym(int t)
{
gsym_addr(t, ind);
}
 
static unsigned long fpr(int r)
{
if(r<TREG_F0 || r>TREG_F3)
error("compiler error! register %i is no fp register\n",r);
return r-5;
}
 
static unsigned long intr(int r)
{
if(r==4)
return 12;
if((r<0 || r>4) && r!=14)
error("compiler error! register %i is no int register\n",r);
return r;
}
 
static void calcaddr(unsigned long *base,int *off,int *sgn,int maxoff,unsigned shift)
{
if(*off>maxoff || *off&((1<<shift)-1)) {
unsigned long x,y;
x=0xE280E000;
if(*sgn)
x=0xE240E000;
x|=(*base)<<16;
*base=14; // lr
y=stuff_const(x,*off&~maxoff);
if(y) {
o(y);
*off&=maxoff;
return;
}
y=stuff_const(x,(*off+maxoff)&~maxoff);
if(y) {
o(y);
*sgn=!*sgn;
*off=((*off+maxoff)&~maxoff)-*off;
return;
}
stuff_const_harder(x,*off&~maxoff);
*off&=maxoff;
}
}
 
static unsigned long mapcc(int cc)
{
switch(cc)
{
case TOK_ULT:
return 0x30000000;
case TOK_UGE:
return 0x20000000;
case TOK_EQ:
return 0x00000000;
case TOK_NE:
return 0x10000000;
case TOK_ULE:
return 0x90000000;
case TOK_UGT:
return 0x80000000;
case TOK_LT:
return 0xB0000000;
case TOK_GE:
return 0xA0000000;
case TOK_LE:
return 0xD0000000;
case TOK_GT:
return 0xC0000000;
}
error("unexpected condition code");
return 0xE0000000;
}
 
static int negcc(int cc)
{
switch(cc)
{
case TOK_ULT:
return TOK_UGE;
case TOK_UGE:
return TOK_ULT;
case TOK_EQ:
return TOK_NE;
case TOK_NE:
return TOK_EQ;
case TOK_ULE:
return TOK_UGT;
case TOK_UGT:
return TOK_ULE;
case TOK_LT:
return TOK_GE;
case TOK_GE:
return TOK_LT;
case TOK_LE:
return TOK_GT;
case TOK_GT:
return TOK_LE;
}
error("unexpected condition code");
return TOK_NE;
}
 
/* load 'r' from value 'sv' */
void load(int r, SValue *sv)
{
int v, ft, fc, fr, sign;
unsigned long op;
SValue v1;
 
fr = sv->r;
ft = sv->type.t;
fc = sv->c.ul;
 
if(fc>=0)
sign=0;
else {
sign=1;
fc=-fc;
}
v = fr & VT_VALMASK;
if (fr & VT_LVAL) {
unsigned long base=0xB; // fp
if(v == VT_LLOCAL) {
v1.type.t = VT_PTR;
v1.r = VT_LOCAL | VT_LVAL;
v1.c.ul = sv->c.ul;
load(base=14 /* lr */, &v1);
fc=sign=0;
v=VT_LOCAL;
} else if(v == VT_CONST) {
v1.type.t = VT_PTR;
v1.r = fr&~VT_LVAL;
v1.c.ul = sv->c.ul;
v1.sym=sv->sym;
load(base=14, &v1);
fc=sign=0;
v=VT_LOCAL;
} else if(v < VT_CONST) {
base=intr(v);
fc=sign=0;
v=VT_LOCAL;
}
if(v == VT_LOCAL) {
if(is_float(ft)) {
calcaddr(&base,&fc,&sign,1020,2);
op=0xED100100;
if(!sign)
op|=0x800000;
#if LDOUBLE_SIZE == 8
if ((ft & VT_BTYPE) != VT_FLOAT)
op|=0x8000;
#else
if ((ft & VT_BTYPE) == VT_DOUBLE)
op|=0x8000;
else if ((ft & VT_BTYPE) == VT_LDOUBLE)
op|=0x400000;
#endif
o(op|(fpr(r)<<12)|(fc>>2)|(base<<16));
} else if((ft & VT_TYPE) == VT_BYTE || (ft & VT_BTYPE) == VT_SHORT) {
calcaddr(&base,&fc,&sign,255,0);
op=0xE1500090;
if ((ft & VT_BTYPE) == VT_SHORT)
op|=0x20;
if ((ft & VT_UNSIGNED) == 0)
op|=0x40;
if(!sign)
op|=0x800000;
o(op|(intr(r)<<12)|(base<<16)|((fc&0xf0)<<4)|(fc&0xf));
} else {
calcaddr(&base,&fc,&sign,4095,0);
op=0xE5100000;
if(!sign)
op|=0x800000;
if ((ft & VT_BTYPE) == VT_BYTE)
op|=0x400000;
o(op|(intr(r)<<12)|fc|(base<<16));
}
return;
}
} else {
if (v == VT_CONST) {
op=stuff_const(0xE3A00000|(intr(r)<<12),sv->c.ul);
if (fr & VT_SYM || !op) {
o(0xE59F0000|(intr(r)<<12));
o(0xEA000000);
if(fr & VT_SYM)
greloc(cur_text_section, sv->sym, ind, R_ARM_ABS32);
o(sv->c.ul);
} else
o(op);
return;
} else if (v == VT_LOCAL) {
op=stuff_const(0xE28B0000|(intr(r)<<12),sv->c.ul);
if (fr & VT_SYM || !op) {
o(0xE59F0000|(intr(r)<<12));
o(0xEA000000);
if(fr & VT_SYM) // needed ?
greloc(cur_text_section, sv->sym, ind, R_ARM_ABS32);
o(sv->c.ul);
o(0xE08B0000|(intr(r)<<12)|intr(r));
} else
o(op);
return;
} else if(v == VT_CMP) {
o(mapcc(sv->c.ul)|0x3A00001|(intr(r)<<12));
o(mapcc(negcc(sv->c.ul))|0x3A00000|(intr(r)<<12));
return;
} else if (v == VT_JMP || v == VT_JMPI) {
int t;
t = v & 1;
o(0xE3A00000|(intr(r)<<12)|t);
o(0xEA000000);
gsym(sv->c.ul);
o(0xE3A00000|(intr(r)<<12)|(t^1));
return;
} else if (v < VT_CONST) {
if(is_float(ft))
o(0xEE008180|(fpr(r)<<12)|fpr(v));
else
o(0xE1A00000|(intr(r)<<12)|intr(v));
return;
}
}
error("load unimplemented!");
}
 
/* store register 'r' in lvalue 'v' */
void store(int r, SValue *sv)
{
SValue v1;
int v, ft, fc, fr, sign;
unsigned long op;
 
fr = sv->r;
ft = sv->type.t;
fc = sv->c.ul;
 
if(fc>=0)
sign=0;
else {
sign=1;
fc=-fc;
}
v = fr & VT_VALMASK;
if (fr & VT_LVAL || fr == VT_LOCAL) {
unsigned long base=0xb;
if(v < VT_CONST) {
base=intr(v);
v=VT_LOCAL;
fc=sign=0;
} else if(v == VT_CONST) {
v1.type.t = ft;
v1.r = fr&~VT_LVAL;
v1.c.ul = sv->c.ul;
v1.sym=sv->sym;
load(base=14, &v1);
fc=sign=0;
v=VT_LOCAL;
}
if(v == VT_LOCAL) {
if(is_float(ft)) {
calcaddr(&base,&fc,&sign,1020,2);
op=0xED000100;
if(!sign)
op|=0x800000;
#if LDOUBLE_SIZE == 8
if ((ft & VT_BTYPE) != VT_FLOAT)
op|=0x8000;
#else
if ((ft & VT_BTYPE) == VT_DOUBLE)
op|=0x8000;
if ((ft & VT_BTYPE) == VT_LDOUBLE)
op|=0x400000;
#endif
o(op|(fpr(r)<<12)|(fc>>2)|(base<<16));
return;
} else if((ft & VT_BTYPE) == VT_SHORT) {
calcaddr(&base,&fc,&sign,255,0);
op=0xE14000B0;
if(!sign)
op|=0x800000;
o(op|(intr(r)<<12)|(base<<16)|((fc&0xf0)<<4)|(fc&0xf));
} else {
calcaddr(&base,&fc,&sign,4095,0);
op=0xE5000000;
if(!sign)
op|=0x800000;
if ((ft & VT_BTYPE) == VT_BYTE)
op|=0x400000;
o(op|(intr(r)<<12)|fc|(base<<16));
}
return;
}
}
error("store unimplemented");
}
 
static void gadd_sp(int val)
{
stuff_const_harder(0xE28DD000,val);
}
 
/* 'is_jmp' is '1' if it is a jump */
static void gcall_or_jmp(int is_jmp)
{
int r;
if ((vtop->r & (VT_VALMASK | VT_LVAL)) == VT_CONST) {
unsigned long x;
/* constant case */
x=encbranch(ind,ind+vtop->c.ul,0);
if(x) {
if (vtop->r & VT_SYM) {
/* relocation case */
greloc(cur_text_section, vtop->sym, ind, R_ARM_PC24);
} else
put_elf_reloc(symtab_section, cur_text_section, ind, R_ARM_PC24, 0);
o(x|(is_jmp?0xE0000000:0xE1000000));
} else {
if(!is_jmp)
o(0xE28FE004); // add lr,pc,#4
o(0xE51FF004); // ldr pc,[pc,#-4]
if (vtop->r & VT_SYM)
greloc(cur_text_section, vtop->sym, ind, R_ARM_ABS32);
o(vtop->c.ul);
}
} else {
/* otherwise, indirect call */
r = gv(RC_INT);
if(!is_jmp)
o(0xE1A0E00F); // mov lr,pc
o(0xE1A0F000|intr(r)); // mov pc,r
}
}
 
/* Generate function call. The function address is pushed first, then
all the parameters in call order. This functions pops all the
parameters and the function address. */
void gfunc_call(int nb_args)
{
int size, align, r, args_size, i;
Sym *func_sym;
signed char plan[4][2]={{-1,-1},{-1,-1},{-1,-1},{-1,-1}};
int todo=0xf, keep, plan2[4]={0,0,0,0};
 
r = vtop->r & VT_VALMASK;
if (r == VT_CMP || (r & ~1) == VT_JMP)
gv(RC_INT);
args_size = 0;
for(i = nb_args ; i-- && args_size < 16 ;) {
if ((vtop[-i].type.t & VT_BTYPE) == VT_STRUCT) {
size = type_size(&vtop[-i].type, &align);
size = (size + 3) & ~3;
args_size += size;
} else if ((vtop[-i].type.t & VT_BTYPE) == VT_FLOAT)
args_size += 4;
else if ((vtop[-i].type.t & VT_BTYPE) == VT_DOUBLE)
args_size += 8;
else if ((vtop[-i].type.t & VT_BTYPE) == VT_LDOUBLE)
args_size += LDOUBLE_SIZE;
else {
plan[nb_args-1-i][0]=args_size/4;
args_size += 4;
if ((vtop[-i].type.t & VT_BTYPE) == VT_LLONG && args_size < 16) {
plan[nb_args-1-i][1]=args_size/4;
args_size += 4;
}
}
}
args_size = keep = 0;
for(i = 0;i < nb_args; i++) {
vnrott(keep+1);
if ((vtop->type.t & VT_BTYPE) == VT_STRUCT) {
size = type_size(&vtop->type, &align);
/* align to stack align size */
size = (size + 3) & ~3;
/* allocate the necessary size on stack */
gadd_sp(-size);
/* generate structure store */
r = get_reg(RC_INT);
o(0xE1A0000D|(intr(r)<<12));
vset(&vtop->type, r | VT_LVAL, 0);
vswap();
vstore();
vtop--;
args_size += size;
} else if (is_float(vtop->type.t)) {
r=fpr(gv(RC_FLOAT))<<12;
if ((vtop->type.t & VT_BTYPE) == VT_FLOAT)
size = 4;
else if ((vtop->type.t & VT_BTYPE) == VT_DOUBLE)
size = 8;
else
size = LDOUBLE_SIZE;
if (size == 12)
r|=0x400000;
else if(size == 8)
r|=0x8000;
 
o(0xED2D0100|r|(size>>2));
vtop--;
args_size += size;
} else {
int s;
/* simple type (currently always same size) */
/* XXX: implicit cast ? */
size=4;
if ((vtop->type.t & VT_BTYPE) == VT_LLONG) {
lexpand_nr();
s=RC_INT;
if(nb_args-i<5 && plan[nb_args-i-1][1]!=-1) {
s=regmask(plan[nb_args-i-1][1]);
todo&=~(1<<plan[nb_args-i-1][1]);
}
if(s==RC_INT) {
r = gv(s);
o(0xE52D0004|(intr(r)<<12)); /* str r,[sp,#-4]! */
vtop--;
} else {
plan2[keep]=s;
keep++;
vswap();
}
size = 8;
}
s=RC_INT;
if(nb_args-i<5 && plan[nb_args-i-1][0]!=-1) {
s=regmask(plan[nb_args-i-1][0]);
todo&=~(1<<plan[nb_args-i-1][0]);
}
if(s==RC_INT) {
r = gv(s);
o(0xE52D0004|(intr(r)<<12)); /* str r,[sp,#-4]! */
vtop--;
} else {
plan2[keep]=s;
keep++;
}
args_size += size;
}
}
for(i=keep;i--;) {
gv(plan2[i]);
vrott(keep);
}
save_regs(keep); /* save used temporary registers */
keep++;
if(args_size) {
int n;
n=args_size/4;
if(n>4)
n=4;
todo&=((1<<n)-1);
if(todo) {
int i;
o(0xE8BD0000|todo);
for(i=0;i<4;i++)
if(todo&(1<<i)) {
vpushi(0);
vtop->r=i;
keep++;
}
}
args_size-=n*4;
}
vnrott(keep);
func_sym = vtop->type.ref;
gcall_or_jmp(0);
if (args_size)
gadd_sp(args_size);
vtop-=keep;
}
 
/* generate function prolog of type 't' */
void gfunc_prolog(CType *func_type)
{
Sym *sym,*sym2;
int n,addr,size,align;
 
sym = func_type->ref;
func_vt = sym->type;
n=0;
addr=12;
if((func_vt.t & VT_BTYPE) == VT_STRUCT) {
func_vc = addr;
addr += 4;
n++;
}
for(sym2=sym->next;sym2 && n<4;sym2=sym2->next) {
size = type_size(&sym2->type, &align);
size = (size + 3) & ~3;
n+=size/4;
}
o(0xE1A0C00D); /* mov ip,sp */
if(func_type->ref->c == FUNC_ELLIPSIS)
n=4;
if(n) {
if(n>4)
n=4;
o(0xE92D0000|((1<<n)-1)); /* save r0-r4 on stack if needed */
}
o(0xE92D5800); /* save fp, ip, lr*/
o(0xE1A0B00D); /* mov fp,sp */
func_sub_sp_offset = ind;
o(0xE1A00000); /* nop, leave space for stack adjustment */
while ((sym = sym->next)) {
CType *type;
type = &sym->type;
sym_push(sym->v & ~SYM_FIELD, type, VT_LOCAL | VT_LVAL, addr);
size = type_size(type, &align);
size = (size + 3) & ~3;
addr += size;
}
last_itod_magic=0;
loc = 0;
}
 
/* generate function epilog */
void gfunc_epilog(void)
{
unsigned long x;
o(0xE89BA800); /* restore fp, sp, pc */
if(loc) {
x=stuff_const(0xE24DD000, (-loc + 3) & -4); /* sub sp,sp,# */
if(x)
*(unsigned long *)(cur_text_section->data + func_sub_sp_offset) = x;
else {
unsigned long addr;
addr=ind;
o(0xE59FC004); /* ldr ip,[pc+4] */
o(0xE04DD00C); /* sub sp,sp,ip */
o(0xE1A0F00E); /* mov pc,lr */
o((-loc + 3) & -4);
*(unsigned long *)(cur_text_section->data + func_sub_sp_offset) = 0xE1000000|encbranch(func_sub_sp_offset,addr,1);
}
}
}
 
/* generate a jump to a label */
int gjmp(int t)
{
int r;
r=ind;
o(0xE0000000|encbranch(r,t,1));
return r;
}
 
/* generate a jump to a fixed address */
void gjmp_addr(int a)
{
gjmp(a);
}
 
/* generate a test. set 'inv' to invert test. Stack entry is popped */
int gtst(int inv, int t)
{
int v, r;
unsigned long op;
v = vtop->r & VT_VALMASK;
r=ind;
if (v == VT_CMP) {
op=mapcc(inv?negcc(vtop->c.i):vtop->c.i);
op|=encbranch(r,t,1);
o(op);
t=r;
} else if (v == VT_JMP || v == VT_JMPI) {
if ((v & 1) == inv) {
if(!vtop->c.i)
vtop->c.i=t;
else {
unsigned long *x;
int p,lp;
if(t) {
p = vtop->c.i;
do {
p = decbranch(lp=p);
} while(p);
x = (unsigned long *)(cur_text_section->data + lp);
*x &= 0xff000000;
*x |= encbranch(lp,t,1);
}
t = vtop->c.i;
}
} else {
t = gjmp(t);
gsym(vtop->c.i);
}
} else {
if (is_float(vtop->type.t)) {
r=gv(RC_FLOAT);
o(0xEE90F118|fpr(r)<<16);
vtop->r = VT_CMP;
vtop->c.i = TOK_NE;
return gtst(inv, t);
} else if ((vtop->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST) {
/* constant jmp optimization */
if ((vtop->c.i != 0) != inv)
t = gjmp(t);
} else {
v = gv(RC_INT);
o(0xE3300000|(intr(v)<<16));
vtop->r = VT_CMP;
vtop->c.i = TOK_NE;
return gtst(inv, t);
}
}
vtop--;
return t;
}
 
/* generate an integer binary operation */
void gen_opi(int op)
{
int c, func = 0;
unsigned long opc = 0,r,fr;
 
c=0;
switch(op) {
case '+':
opc = 0x8;
c=1;
break;
case TOK_ADDC1: /* add with carry generation */
opc = 0x9;
c=1;
break;
case '-':
opc = 0x4;
c=1;
break;
case TOK_SUBC1: /* sub with carry generation */
opc = 0x5;
c=1;
break;
case TOK_ADDC2: /* add with carry use */
opc = 0xA;
c=1;
break;
case TOK_SUBC2: /* sub with carry use */
opc = 0xC;
c=1;
break;
case '&':
opc = 0x0;
c=1;
break;
case '^':
opc = 0x2;
c=1;
break;
case '|':
opc = 0x18;
c=1;
break;
case '*':
gv2(RC_INT, RC_INT);
r = vtop[-1].r;
fr = vtop[0].r;
vtop--;
o(0xE0000090|(intr(r)<<16)|(intr(r)<<8)|intr(fr));
return;
case TOK_SHL:
opc = 0;
c=2;
break;
case TOK_SHR:
opc = 1;
c=2;
break;
case TOK_SAR:
opc = 2;
c=2;
break;
case '/':
case TOK_PDIV:
func=TOK___divsi3;
c=3;
break;
case TOK_UDIV:
func=TOK___udivsi3;
c=3;
break;
case '%':
func=TOK___modsi3;
c=3;
break;
case TOK_UMOD:
func=TOK___umodsi3;
c=3;
break;
case TOK_UMULL:
gv2(RC_INT, RC_INT);
r=intr(vtop[-1].r2=get_reg(RC_INT));
c=vtop[-1].r;
vtop[-1].r=get_reg_ex(RC_INT,regmask(c));
vtop--;
o(0xE0800090|(r<<16)|(intr(vtop->r)<<12)|(intr(c)<<8)|intr(vtop[1].r));
return;
default:
opc = 0x15;
c=1;
break;
}
switch(c) {
case 1:
if((vtop[-1].r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST) {
if(opc == 4 || opc == 5 || opc == 0xc) {
vswap();
opc|=2; // sub -> rsb
}
}
if ((vtop->r & VT_VALMASK) == VT_CMP ||
(vtop->r & (VT_VALMASK & ~1)) == VT_JMP)
gv(RC_INT);
vswap();
c=intr(gv(RC_INT));
vswap();
opc=0xE0000000|(opc<<20)|(c<<16);
if((vtop->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST) {
unsigned long x;
x=stuff_const(opc|0x2000000,vtop->c.i);
if(x) {
r=intr(vtop[-1].r=get_reg_ex(RC_INT,regmask(vtop[-1].r)));
o(x|(r<<12));
goto done;
}
}
fr=intr(gv(RC_INT));
r=intr(vtop[-1].r=get_reg_ex(RC_INT,two2mask(vtop->r,vtop[-1].r)));
o(opc|(r<<12)|fr);
done:
vtop--;
if (op >= TOK_ULT && op <= TOK_GT) {
vtop->r = VT_CMP;
vtop->c.i = op;
}
break;
case 2:
opc=0xE1A00000|(opc<<5);
if ((vtop->r & VT_VALMASK) == VT_CMP ||
(vtop->r & (VT_VALMASK & ~1)) == VT_JMP)
gv(RC_INT);
vswap();
r=intr(gv(RC_INT));
vswap();
opc|=r;
if ((vtop->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST) {
fr=intr(vtop[-1].r=get_reg_ex(RC_INT,regmask(vtop[-1].r)));
c = vtop->c.i & 0x1f;
o(opc|(c<<7)|(fr<<12));
} else {
fr=intr(gv(RC_INT));
c=intr(vtop[-1].r=get_reg_ex(RC_INT,two2mask(vtop->r,vtop[-1].r)));
o(opc|(c<<12)|(fr<<8)|0x10);
}
vtop--;
break;
case 3:
vpush_global_sym(&func_old_type, func);
vrott(3);
gfunc_call(2);
vpushi(0);
vtop->r = REG_IRET;
break;
default:
error("gen_opi %i unimplemented!",op);
}
}
 
static int is_fconst()
{
long double f;
int r;
if((vtop->r & (VT_VALMASK | VT_LVAL | VT_SYM)) != VT_CONST)
return 0;
if (vtop->type.t == VT_FLOAT)
f = vtop->c.f;
else if (vtop->type.t == VT_DOUBLE)
f = vtop->c.d;
else
f = vtop->c.ld;
if(!ieee_finite(f))
return 0;
r=0x8;
if(f<0.0) {
r=0x18;
f=-f;
}
if(f==0.0)
return r;
if(f==1.0)
return r|1;
if(f==2.0)
return r|2;
if(f==3.0)
return r|3;
if(f==4.0)
return r|4;
if(f==5.0)
return r|5;
if(f==0.5)
return r|6;
if(f==10.0)
return r|7;
return 0;
}
 
/* generate a floating point operation 'v = t1 op t2' instruction. The
two operands are guaranted to have the same floating point type */
void gen_opf(int op)
{
unsigned long x;
int r,r2,c1,c2;
//fputs("gen_opf\n",stderr);
vswap();
c1 = is_fconst();
vswap();
c2 = is_fconst();
x=0xEE000100;
#if LDOUBLE_SIZE == 8
if ((vtop->type.t & VT_BTYPE) != VT_FLOAT)
x|=0x80;
#else
if ((vtop->type.t & VT_BTYPE) == VT_DOUBLE)
x|=0x80;
else if ((vtop->type.t & VT_BTYPE) == VT_LDOUBLE)
x|=0x80000;
#endif
switch(op)
{
case '+':
if(!c2) {
vswap();
c2=c1;
}
vswap();
r=fpr(gv(RC_FLOAT));
vswap();
if(c2) {
if(c2>0xf)
x|=0x200000; // suf
r2=c2&0xf;
} else {
r2=fpr(gv(RC_FLOAT));
}
break;
case '-':
if(c2) {
if(c2<=0xf)
x|=0x200000; // suf
r2=c2&0xf;
vswap();
r=fpr(gv(RC_FLOAT));
vswap();
} else if(c1 && c1<=0xf) {
x|=0x300000; // rsf
r2=c1;
r=fpr(gv(RC_FLOAT));
vswap();
} else {
x|=0x200000; // suf
vswap();
r=fpr(gv(RC_FLOAT));
vswap();
r2=fpr(gv(RC_FLOAT));
}
break;
case '*':
if(!c2 || c2>0xf) {
vswap();
c2=c1;
}
vswap();
r=fpr(gv(RC_FLOAT));
vswap();
if(c2 && c2<=0xf)
r2=c2;
else
r2=fpr(gv(RC_FLOAT));
x|=0x100000; // muf
break;
case '/':
if(c2 && c2<=0xf) {
x|=0x400000; // dvf
r2=c2;
vswap();
r=fpr(gv(RC_FLOAT));
vswap();
} else if(c1 && c1<=0xf) {
x|=0x500000; // rdf
r2=c1;
r=fpr(gv(RC_FLOAT));
vswap();
} else {
x|=0x400000; // dvf
vswap();
r=fpr(gv(RC_FLOAT));
vswap();
r2=fpr(gv(RC_FLOAT));
}
break;
default:
if(op >= TOK_ULT && op <= TOK_GT) {
x|=0xd0f110; // cmfe
switch(op) {
case TOK_ULT:
case TOK_UGE:
case TOK_ULE:
case TOK_UGT:
fputs("unsigned comparision on floats?\n",stderr);
break;
case TOK_LT:
op=TOK_ULT;
break;
case TOK_GE:
op=TOK_UGE;
break;
case TOK_LE:
op=TOK_ULE;
break;
case TOK_GT:
op=TOK_UGT;
break;
case TOK_EQ:
case TOK_NE:
x&=~0x400000; // cmfe -> cmf
break;
}
if(c1 && !c2) {
c2=c1;
vswap();
switch(op) {
case TOK_ULT:
op=TOK_UGT;
break;
case TOK_UGE:
op=TOK_ULE;
break;
case TOK_ULE:
op=TOK_UGE;
break;
case TOK_UGT:
op=TOK_ULT;
break;
}
}
// bug (intention?) in Linux FPU emulator
// doesn't set carry if equal
if(op==TOK_ULT)
op=TOK_LT;
else if(op==TOK_UGE)
op=TOK_GE;
vswap();
r=fpr(gv(RC_FLOAT));
vswap();
if(c2) {
if(c2>0xf)
x|=0x200000;
r2=c2&0xf;
} else {
r2=fpr(gv(RC_FLOAT));
}
vtop[-1].r = VT_CMP;
vtop[-1].c.i = op;
} else {
error("unknown fp op %x!\n",op);
return;
}
}
if(vtop[-1].r == VT_CMP)
c1=15;
else {
c1=vtop->r;
if(r2&0x8)
c1=vtop[-1].r;
vtop[-1].r=get_reg_ex(RC_FLOAT,two2mask(vtop[-1].r,c1));
c1=fpr(vtop[-1].r);
}
vtop--;
o(x|(r<<16)|(c1<<12)|r2);
}
 
/* convert integers to fp 't' type. Must handle 'int', 'unsigned int'
and 'long long' cases. */
void gen_cvt_itof(int t)
{
int r,r2,bt;
bt=vtop->type.t & VT_BTYPE;
if(bt == VT_INT || bt == VT_SHORT || bt == VT_BYTE) {
r=intr(gv(RC_INT));
r2=fpr(vtop->r=get_reg(RC_FLOAT));
o(0xEE000190|(r2<<16)|(r<<12));
if((vtop->type.t & (VT_UNSIGNED|VT_BTYPE)) == (VT_UNSIGNED|VT_INT)) {
unsigned int off=0;
o(0xE3500000|(r<<12));
r=fpr(get_reg(RC_FLOAT));
if(last_itod_magic) {
off=ind+8-last_itod_magic;
off/=4;
if(off>255)
off=0;
}
o(0xBD1F8100|(r<<12)|off);
if(!off) {
o(0xEA000001);
last_itod_magic=ind;
o(0x41F00000);
o(0);
}
o(0xBE000180|(r2<<16)|(r2<<12)|r);
}
return;
} else if(bt == VT_LLONG) {
int func;
if(vtop->type.t & VT_UNSIGNED)
func=TOK___ulltold;
else
func=TOK___slltold;
vpush_global_sym(&func_old_type, func);
vswap();
gfunc_call(1);
vpushi(0);
vtop->r=TREG_F0;
return;
}
error("unimplemented gen_cvt_itof %x!",vtop->type.t);
}
 
/* convert fp to int 't' type */
void gen_cvt_ftoi(int t)
{
int r,r2,u,func=0;
u=t&VT_UNSIGNED;
t&=VT_BTYPE;
r2=vtop->type.t & VT_BTYPE;
if(t==VT_INT) {
if(u) {
if(r2 == VT_FLOAT)
func=TOK___fixunssfsi;
else if(r2 == VT_DOUBLE)
func=TOK___fixunsdfsi;
else if(r2 == VT_LDOUBLE)
#if LDOUBLE_SIZE == 8
func=TOK___fixunsdfsi;
#else
func=TOK___fixunsxfsi;
#endif
} else {
r=fpr(gv(RC_FLOAT));
r2=intr(vtop->r=get_reg(RC_INT));
o(0xEE100170|(r2<<12)|r);
return;
}
} else if(t == VT_LLONG) { // unsigned handled in gen_cvt_ftoi1
if(r2 == VT_FLOAT)
func=TOK___fixsfdi;
else if(r2 == VT_DOUBLE)
func=TOK___fixdfdi;
else if(r2 == VT_LDOUBLE)
#if LDOUBLE_SIZE == 8
func=TOK___fixdfdi;
#else
func=TOK___fixxfdi;
#endif
}
if(func) {
vpush_global_sym(&func_old_type, func);
vswap();
gfunc_call(1);
vpushi(0);
if(t == VT_LLONG)
vtop->r2 = REG_LRET;
vtop->r = REG_IRET;
return;
}
error("unimplemented gen_cvt_ftoi!");
}
 
/* convert from one floating point type to another */
void gen_cvt_ftof(int t)
{
/* all we have to do on i386 and ARM is to put the float in a register */
gv(RC_FLOAT);
}
 
/* computed goto support */
void ggoto(void)
{
gcall_or_jmp(1);
vtop--;
}
 
/* end of ARM code generator */
/*************************************************************/
 
/programs/develop/metcc/trunk/source/bcheck.c
0,0 → 1,867
/*
* Tiny C Memory and bounds checker
*
* Copyright (c) 2002 Fabrice Bellard
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <stdlib.h>
#include <stdio.h>
#include <stdarg.h>
#include <string.h>
#ifndef __FreeBSD__
#include <malloc.h>
#endif
 
//#define BOUND_DEBUG
 
/* define so that bound array is static (faster, but use memory if
bound checking not used) */
//#define BOUND_STATIC
 
/* use malloc hooks. Currently the code cannot be reliable if no hooks */
#define CONFIG_TCC_MALLOC_HOOKS
 
#define HAVE_MEMALIGN
 
#if defined(__FreeBSD__) || defined(__dietlibc__)
#warning Bound checking not fully supported on FreeBSD
#undef CONFIG_TCC_MALLOC_HOOKS
#undef HAVE_MEMALIGN
#endif
 
#define BOUND_T1_BITS 13
#define BOUND_T2_BITS 11
#define BOUND_T3_BITS (32 - BOUND_T1_BITS - BOUND_T2_BITS)
 
#define BOUND_T1_SIZE (1 << BOUND_T1_BITS)
#define BOUND_T2_SIZE (1 << BOUND_T2_BITS)
#define BOUND_T3_SIZE (1 << BOUND_T3_BITS)
#define BOUND_E_BITS 4
 
#define BOUND_T23_BITS (BOUND_T2_BITS + BOUND_T3_BITS)
#define BOUND_T23_SIZE (1 << BOUND_T23_BITS)
 
 
/* this pointer is generated when bound check is incorrect */
#define INVALID_POINTER ((void *)(-2))
/* size of an empty region */
#define EMPTY_SIZE 0xffffffff
/* size of an invalid region */
#define INVALID_SIZE 0
 
typedef struct BoundEntry {
unsigned long start;
unsigned long size;
struct BoundEntry *next;
unsigned long is_invalid; /* true if pointers outside region are invalid */
} BoundEntry;
 
/* external interface */
void __bound_init(void);
void __bound_new_region(void *p, unsigned long size);
int __bound_delete_region(void *p);
 
#define FASTCALL __attribute__((regparm(3)))
 
void *__bound_malloc(size_t size, const void *caller);
void *__bound_memalign(size_t size, size_t align, const void *caller);
void __bound_free(void *ptr, const void *caller);
void *__bound_realloc(void *ptr, size_t size, const void *caller);
static void *libc_malloc(size_t size);
static void libc_free(void *ptr);
static void install_malloc_hooks(void);
static void restore_malloc_hooks(void);
 
#ifdef CONFIG_TCC_MALLOC_HOOKS
static void *saved_malloc_hook;
static void *saved_free_hook;
static void *saved_realloc_hook;
static void *saved_memalign_hook;
#endif
 
/* linker definitions */
extern char _end;
 
/* TCC definitions */
extern char __bounds_start; /* start of static bounds table */
/* error message, just for TCC */
const char *__bound_error_msg;
 
/* runtime error output */
extern void rt_error(unsigned long pc, const char *fmt, ...);
 
#ifdef BOUND_STATIC
static BoundEntry *__bound_t1[BOUND_T1_SIZE]; /* page table */
#else
static BoundEntry **__bound_t1; /* page table */
#endif
static BoundEntry *__bound_empty_t2; /* empty page, for unused pages */
static BoundEntry *__bound_invalid_t2; /* invalid page, for invalid pointers */
 
static BoundEntry *__bound_find_region(BoundEntry *e1, void *p)
{
unsigned long addr, tmp;
BoundEntry *e;
 
e = e1;
while (e != NULL) {
addr = (unsigned long)p;
addr -= e->start;
if (addr <= e->size) {
/* put region at the head */
tmp = e1->start;
e1->start = e->start;
e->start = tmp;
tmp = e1->size;
e1->size = e->size;
e->size = tmp;
return e1;
}
e = e->next;
}
/* no entry found: return empty entry or invalid entry */
if (e1->is_invalid)
return __bound_invalid_t2;
else
return __bound_empty_t2;
}
 
/* print a bound error message */
static void bound_error(const char *fmt, ...)
{
__bound_error_msg = fmt;
*(int *)0 = 0; /* force a runtime error */
}
 
static void bound_alloc_error(void)
{
bound_error("not enough memory for bound checking code");
}
 
/* currently, tcc cannot compile that because we use GNUC extensions */
#if !defined(__TINYC__)
 
/* return '(p + offset)' for pointer arithmetic (a pointer can reach
the end of a region in this case */
void * FASTCALL __bound_ptr_add(void *p, int offset)
{
unsigned long addr = (unsigned long)p;
BoundEntry *e;
#if defined(BOUND_DEBUG)
printf("add: 0x%x %d\n", (int)p, offset);
#endif
 
e = __bound_t1[addr >> (BOUND_T2_BITS + BOUND_T3_BITS)];
e = (BoundEntry *)((char *)e +
((addr >> (BOUND_T3_BITS - BOUND_E_BITS)) &
((BOUND_T2_SIZE - 1) << BOUND_E_BITS)));
addr -= e->start;
if (addr > e->size) {
e = __bound_find_region(e, p);
addr = (unsigned long)p - e->start;
}
addr += offset;
if (addr > e->size)
return INVALID_POINTER; /* return an invalid pointer */
return p + offset;
}
 
/* return '(p + offset)' for pointer indirection (the resulting must
be strictly inside the region */
#define BOUND_PTR_INDIR(dsize) \
void * FASTCALL __bound_ptr_indir ## dsize (void *p, int offset) \
{ \
unsigned long addr = (unsigned long)p; \
BoundEntry *e; \
\
e = __bound_t1[addr >> (BOUND_T2_BITS + BOUND_T3_BITS)]; \
e = (BoundEntry *)((char *)e + \
((addr >> (BOUND_T3_BITS - BOUND_E_BITS)) & \
((BOUND_T2_SIZE - 1) << BOUND_E_BITS))); \
addr -= e->start; \
if (addr > e->size) { \
e = __bound_find_region(e, p); \
addr = (unsigned long)p - e->start; \
} \
addr += offset + dsize; \
if (addr > e->size) \
return INVALID_POINTER; /* return an invalid pointer */ \
return p + offset; \
}
 
#ifdef __i386__
/* return the frame pointer of the caller */
#define GET_CALLER_FP(fp)\
{\
unsigned long *fp1;\
__asm__ __volatile__ ("movl %%ebp,%0" :"=g" (fp1));\
fp = fp1[0];\
}
#else
#error put code to extract the calling frame pointer
#endif
 
/* called when entering a function to add all the local regions */
void FASTCALL __bound_local_new(void *p1)
{
unsigned long addr, size, fp, *p = p1;
GET_CALLER_FP(fp);
for(;;) {
addr = p[0];
if (addr == 0)
break;
addr += fp;
size = p[1];
p += 2;
__bound_new_region((void *)addr, size);
}
}
 
/* called when leaving a function to delete all the local regions */
void FASTCALL __bound_local_delete(void *p1)
{
unsigned long addr, fp, *p = p1;
GET_CALLER_FP(fp);
for(;;) {
addr = p[0];
if (addr == 0)
break;
addr += fp;
p += 2;
__bound_delete_region((void *)addr);
}
}
 
#else
 
void __bound_local_new(void *p)
{
}
void __bound_local_delete(void *p)
{
}
 
void *__bound_ptr_add(void *p, int offset)
{
return p + offset;
}
 
#define BOUND_PTR_INDIR(dsize) \
void *__bound_ptr_indir ## dsize (void *p, int offset) \
{ \
return p + offset; \
}
#endif
 
BOUND_PTR_INDIR(1)
BOUND_PTR_INDIR(2)
BOUND_PTR_INDIR(4)
BOUND_PTR_INDIR(8)
BOUND_PTR_INDIR(12)
BOUND_PTR_INDIR(16)
 
static BoundEntry *__bound_new_page(void)
{
BoundEntry *page;
int i;
 
page = libc_malloc(sizeof(BoundEntry) * BOUND_T2_SIZE);
if (!page)
bound_alloc_error();
for(i=0;i<BOUND_T2_SIZE;i++) {
/* put empty entries */
page[i].start = 0;
page[i].size = EMPTY_SIZE;
page[i].next = NULL;
page[i].is_invalid = 0;
}
return page;
}
 
/* currently we use malloc(). Should use bound_new_page() */
static BoundEntry *bound_new_entry(void)
{
BoundEntry *e;
e = libc_malloc(sizeof(BoundEntry));
return e;
}
 
static void bound_free_entry(BoundEntry *e)
{
libc_free(e);
}
 
static inline BoundEntry *get_page(int index)
{
BoundEntry *page;
page = __bound_t1[index];
if (page == __bound_empty_t2 || page == __bound_invalid_t2) {
/* create a new page if necessary */
page = __bound_new_page();
__bound_t1[index] = page;
}
return page;
}
 
/* mark a region as being invalid (can only be used during init) */
static void mark_invalid(unsigned long addr, unsigned long size)
{
unsigned long start, end;
BoundEntry *page;
int t1_start, t1_end, i, j, t2_start, t2_end;
 
start = addr;
end = addr + size;
 
t2_start = (start + BOUND_T3_SIZE - 1) >> BOUND_T3_BITS;
if (end != 0)
t2_end = end >> BOUND_T3_BITS;
else
t2_end = 1 << (BOUND_T1_BITS + BOUND_T2_BITS);
 
#if 0
printf("mark_invalid: start = %x %x\n", t2_start, t2_end);
#endif
/* first we handle full pages */
t1_start = (t2_start + BOUND_T2_SIZE - 1) >> BOUND_T2_BITS;
t1_end = t2_end >> BOUND_T2_BITS;
 
i = t2_start & (BOUND_T2_SIZE - 1);
j = t2_end & (BOUND_T2_SIZE - 1);
if (t1_start == t1_end) {
page = get_page(t2_start >> BOUND_T2_BITS);
for(; i < j; i++) {
page[i].size = INVALID_SIZE;
page[i].is_invalid = 1;
}
} else {
if (i > 0) {
page = get_page(t2_start >> BOUND_T2_BITS);
for(; i < BOUND_T2_SIZE; i++) {
page[i].size = INVALID_SIZE;
page[i].is_invalid = 1;
}
}
for(i = t1_start; i < t1_end; i++) {
__bound_t1[i] = __bound_invalid_t2;
}
if (j != 0) {
page = get_page(t1_end);
for(i = 0; i < j; i++) {
page[i].size = INVALID_SIZE;
page[i].is_invalid = 1;
}
}
}
}
 
void __bound_init(void)
{
int i;
BoundEntry *page;
unsigned long start, size;
int *p;
 
/* save malloc hooks and install bound check hooks */
install_malloc_hooks();
 
#ifndef BOUND_STATIC
__bound_t1 = libc_malloc(BOUND_T1_SIZE * sizeof(BoundEntry *));
if (!__bound_t1)
bound_alloc_error();
#endif
__bound_empty_t2 = __bound_new_page();
for(i=0;i<BOUND_T1_SIZE;i++) {
__bound_t1[i] = __bound_empty_t2;
}
 
page = __bound_new_page();
for(i=0;i<BOUND_T2_SIZE;i++) {
/* put invalid entries */
page[i].start = 0;
page[i].size = INVALID_SIZE;
page[i].next = NULL;
page[i].is_invalid = 1;
}
__bound_invalid_t2 = page;
 
/* invalid pointer zone */
start = (unsigned long)INVALID_POINTER & ~(BOUND_T23_SIZE - 1);
size = BOUND_T23_SIZE;
mark_invalid(start, size);
 
#if !defined(__TINYC__) && defined(CONFIG_TCC_MALLOC_HOOKS)
/* malloc zone is also marked invalid. can only use that with
hooks because all libs should use the same malloc. The solution
would be to build a new malloc for tcc. */
start = (unsigned long)&_end;
size = 128 * 0x100000;
mark_invalid(start, size);
#endif
 
/* add all static bound check values */
p = (int *)&__bounds_start;
while (p[0] != 0) {
__bound_new_region((void *)p[0], p[1]);
p += 2;
}
}
 
static inline void add_region(BoundEntry *e,
unsigned long start, unsigned long size)
{
BoundEntry *e1;
if (e->start == 0) {
/* no region : add it */
e->start = start;
e->size = size;
} else {
/* already regions in the list: add it at the head */
e1 = bound_new_entry();
e1->start = e->start;
e1->size = e->size;
e1->next = e->next;
e->start = start;
e->size = size;
e->next = e1;
}
}
 
/* create a new region. It should not already exist in the region list */
void __bound_new_region(void *p, unsigned long size)
{
unsigned long start, end;
BoundEntry *page, *e, *e2;
int t1_start, t1_end, i, t2_start, t2_end;
 
start = (unsigned long)p;
end = start + size;
t1_start = start >> (BOUND_T2_BITS + BOUND_T3_BITS);
t1_end = end >> (BOUND_T2_BITS + BOUND_T3_BITS);
 
/* start */
page = get_page(t1_start);
t2_start = (start >> (BOUND_T3_BITS - BOUND_E_BITS)) &
((BOUND_T2_SIZE - 1) << BOUND_E_BITS);
t2_end = (end >> (BOUND_T3_BITS - BOUND_E_BITS)) &
((BOUND_T2_SIZE - 1) << BOUND_E_BITS);
#ifdef BOUND_DEBUG
printf("new %lx %lx %x %x %x %x\n",
start, end, t1_start, t1_end, t2_start, t2_end);
#endif
 
e = (BoundEntry *)((char *)page + t2_start);
add_region(e, start, size);
 
if (t1_end == t1_start) {
/* same ending page */
e2 = (BoundEntry *)((char *)page + t2_end);
if (e2 > e) {
e++;
for(;e<e2;e++) {
e->start = start;
e->size = size;
}
add_region(e, start, size);
}
} else {
/* mark until end of page */
e2 = page + BOUND_T2_SIZE;
e++;
for(;e<e2;e++) {
e->start = start;
e->size = size;
}
/* mark intermediate pages, if any */
for(i=t1_start+1;i<t1_end;i++) {
page = get_page(i);
e2 = page + BOUND_T2_SIZE;
for(e=page;e<e2;e++) {
e->start = start;
e->size = size;
}
}
/* last page */
page = get_page(t1_end);
e2 = (BoundEntry *)((char *)page + t2_end);
for(e=page;e<e2;e++) {
e->start = start;
e->size = size;
}
add_region(e, start, size);
}
}
 
/* delete a region */
static inline void delete_region(BoundEntry *e,
void *p, unsigned long empty_size)
{
unsigned long addr;
BoundEntry *e1;
 
addr = (unsigned long)p;
addr -= e->start;
if (addr <= e->size) {
/* region found is first one */
e1 = e->next;
if (e1 == NULL) {
/* no more region: mark it empty */
e->start = 0;
e->size = empty_size;
} else {
/* copy next region in head */
e->start = e1->start;
e->size = e1->size;
e->next = e1->next;
bound_free_entry(e1);
}
} else {
/* find the matching region */
for(;;) {
e1 = e;
e = e->next;
/* region not found: do nothing */
if (e == NULL)
break;
addr = (unsigned long)p - e->start;
if (addr <= e->size) {
/* found: remove entry */
e1->next = e->next;
bound_free_entry(e);
break;
}
}
}
}
 
/* WARNING: 'p' must be the starting point of the region. */
/* return non zero if error */
int __bound_delete_region(void *p)
{
unsigned long start, end, addr, size, empty_size;
BoundEntry *page, *e, *e2;
int t1_start, t1_end, t2_start, t2_end, i;
 
start = (unsigned long)p;
t1_start = start >> (BOUND_T2_BITS + BOUND_T3_BITS);
t2_start = (start >> (BOUND_T3_BITS - BOUND_E_BITS)) &
((BOUND_T2_SIZE - 1) << BOUND_E_BITS);
/* find region size */
page = __bound_t1[t1_start];
e = (BoundEntry *)((char *)page + t2_start);
addr = start - e->start;
if (addr > e->size)
e = __bound_find_region(e, p);
/* test if invalid region */
if (e->size == EMPTY_SIZE || (unsigned long)p != e->start)
return -1;
/* compute the size we put in invalid regions */
if (e->is_invalid)
empty_size = INVALID_SIZE;
else
empty_size = EMPTY_SIZE;
size = e->size;
end = start + size;
 
/* now we can free each entry */
t1_end = end >> (BOUND_T2_BITS + BOUND_T3_BITS);
t2_end = (end >> (BOUND_T3_BITS - BOUND_E_BITS)) &
((BOUND_T2_SIZE - 1) << BOUND_E_BITS);
 
delete_region(e, p, empty_size);
if (t1_end == t1_start) {
/* same ending page */
e2 = (BoundEntry *)((char *)page + t2_end);
if (e2 > e) {
e++;
for(;e<e2;e++) {
e->start = 0;
e->size = empty_size;
}
delete_region(e, p, empty_size);
}
} else {
/* mark until end of page */
e2 = page + BOUND_T2_SIZE;
e++;
for(;e<e2;e++) {
e->start = 0;
e->size = empty_size;
}
/* mark intermediate pages, if any */
/* XXX: should free them */
for(i=t1_start+1;i<t1_end;i++) {
page = get_page(i);
e2 = page + BOUND_T2_SIZE;
for(e=page;e<e2;e++) {
e->start = 0;
e->size = empty_size;
}
}
/* last page */
page = get_page(t2_end);
e2 = (BoundEntry *)((char *)page + t2_end);
for(e=page;e<e2;e++) {
e->start = 0;
e->size = empty_size;
}
delete_region(e, p, empty_size);
}
return 0;
}
 
/* return the size of the region starting at p, or EMPTY_SIZE if non
existant region. */
static unsigned long get_region_size(void *p)
{
unsigned long addr = (unsigned long)p;
BoundEntry *e;
 
e = __bound_t1[addr >> (BOUND_T2_BITS + BOUND_T3_BITS)];
e = (BoundEntry *)((char *)e +
((addr >> (BOUND_T3_BITS - BOUND_E_BITS)) &
((BOUND_T2_SIZE - 1) << BOUND_E_BITS)));
addr -= e->start;
if (addr > e->size)
e = __bound_find_region(e, p);
if (e->start != (unsigned long)p)
return EMPTY_SIZE;
return e->size;
}
 
/* patched memory functions */
 
static void install_malloc_hooks(void)
{
#ifdef CONFIG_TCC_MALLOC_HOOKS
saved_malloc_hook = __malloc_hook;
saved_free_hook = __free_hook;
saved_realloc_hook = __realloc_hook;
saved_memalign_hook = __memalign_hook;
__malloc_hook = __bound_malloc;
__free_hook = __bound_free;
__realloc_hook = __bound_realloc;
__memalign_hook = __bound_memalign;
#endif
}
 
static void restore_malloc_hooks(void)
{
#ifdef CONFIG_TCC_MALLOC_HOOKS
__malloc_hook = saved_malloc_hook;
__free_hook = saved_free_hook;
__realloc_hook = saved_realloc_hook;
__memalign_hook = saved_memalign_hook;
#endif
}
 
static void *libc_malloc(size_t size)
{
void *ptr;
restore_malloc_hooks();
ptr = malloc(size);
install_malloc_hooks();
return ptr;
}
 
static void libc_free(void *ptr)
{
restore_malloc_hooks();
free(ptr);
install_malloc_hooks();
}
 
/* XXX: we should use a malloc which ensure that it is unlikely that
two malloc'ed data have the same address if 'free' are made in
between. */
void *__bound_malloc(size_t size, const void *caller)
{
void *ptr;
/* we allocate one more byte to ensure the regions will be
separated by at least one byte. With the glibc malloc, it may
be in fact not necessary */
ptr = libc_malloc(size + 1);
if (!ptr)
return NULL;
__bound_new_region(ptr, size);
return ptr;
}
 
void *__bound_memalign(size_t size, size_t align, const void *caller)
{
void *ptr;
 
restore_malloc_hooks();
 
#ifndef HAVE_MEMALIGN
if (align > 4) {
/* XXX: handle it ? */
ptr = NULL;
} else {
/* we suppose that malloc aligns to at least four bytes */
ptr = malloc(size + 1);
}
#else
/* we allocate one more byte to ensure the regions will be
separated by at least one byte. With the glibc malloc, it may
be in fact not necessary */
ptr = memalign(size + 1, align);
#endif
install_malloc_hooks();
if (!ptr)
return NULL;
__bound_new_region(ptr, size);
return ptr;
}
 
void __bound_free(void *ptr, const void *caller)
{
if (ptr == NULL)
return;
if (__bound_delete_region(ptr) != 0)
bound_error("freeing invalid region");
 
libc_free(ptr);
}
 
void *__bound_realloc(void *ptr, size_t size, const void *caller)
{
void *ptr1;
int old_size;
 
if (size == 0) {
__bound_free(ptr, caller);
return NULL;
} else {
ptr1 = __bound_malloc(size, caller);
if (ptr == NULL || ptr1 == NULL)
return ptr1;
old_size = get_region_size(ptr);
if (old_size == EMPTY_SIZE)
bound_error("realloc'ing invalid pointer");
memcpy(ptr1, ptr, old_size);
__bound_free(ptr, caller);
return ptr1;
}
}
 
#ifndef CONFIG_TCC_MALLOC_HOOKS
void *__bound_calloc(size_t nmemb, size_t size)
{
void *ptr;
size = size * nmemb;
ptr = __bound_malloc(size, NULL);
if (!ptr)
return NULL;
memset(ptr, 0, size);
return ptr;
}
#endif
 
#if 0
static void bound_dump(void)
{
BoundEntry *page, *e;
int i, j;
 
printf("region dump:\n");
for(i=0;i<BOUND_T1_SIZE;i++) {
page = __bound_t1[i];
for(j=0;j<BOUND_T2_SIZE;j++) {
e = page + j;
/* do not print invalid or empty entries */
if (e->size != EMPTY_SIZE && e->start != 0) {
printf("%08x:",
(i << (BOUND_T2_BITS + BOUND_T3_BITS)) +
(j << BOUND_T3_BITS));
do {
printf(" %08lx:%08lx", e->start, e->start + e->size);
e = e->next;
} while (e != NULL);
printf("\n");
}
}
}
}
#endif
 
/* some useful checked functions */
 
/* check that (p ... p + size - 1) lies inside 'p' region, if any */
static void __bound_check(const void *p, size_t size)
{
if (size == 0)
return;
p = __bound_ptr_add((void *)p, size);
if (p == INVALID_POINTER)
bound_error("invalid pointer");
}
 
void *__bound_memcpy(void *dst, const void *src, size_t size)
{
__bound_check(dst, size);
__bound_check(src, size);
/* check also region overlap */
if (src >= dst && src < dst + size)
bound_error("overlapping regions in memcpy()");
return memcpy(dst, src, size);
}
 
void *__bound_memmove(void *dst, const void *src, size_t size)
{
__bound_check(dst, size);
__bound_check(src, size);
return memmove(dst, src, size);
}
 
void *__bound_memset(void *dst, int c, size_t size)
{
__bound_check(dst, size);
return memset(dst, c, size);
}
 
/* XXX: could be optimized */
int __bound_strlen(const char *s)
{
const char *p;
int len;
 
len = 0;
for(;;) {
p = __bound_ptr_indir1((char *)s, len);
if (p == INVALID_POINTER)
bound_error("bad pointer in strlen()");
if (*p == '\0')
break;
len++;
}
return len;
}
 
char *__bound_strcpy(char *dst, const char *src)
{
int len;
len = __bound_strlen(src);
return __bound_memcpy(dst, src, len + 1);
}
 
/programs/develop/metcc/trunk/source/boundtest.c
0,0 → 1,214
#include <stdlib.h>
#include <stdio.h>
 
#define NB_ITS 1000000
//#define NB_ITS 1
#define TAB_SIZE 100
 
int tab[TAB_SIZE];
int ret_sum;
char tab3[256];
 
int test1(void)
{
int i, sum = 0;
for(i=0;i<TAB_SIZE;i++) {
sum += tab[i];
}
return sum;
}
 
/* error */
int test2(void)
{
int i, sum = 0;
for(i=0;i<TAB_SIZE + 1;i++) {
sum += tab[i];
}
return sum;
}
 
/* actually, profiling test */
int test3(void)
{
int sum;
int i, it;
 
sum = 0;
for(it=0;it<NB_ITS;it++) {
for(i=0;i<TAB_SIZE;i++) {
sum += tab[i];
}
}
return sum;
}
 
/* ok */
int test4(void)
{
int i, sum = 0;
int *tab4;
 
tab4 = malloc(20 * sizeof(int));
for(i=0;i<20;i++) {
sum += tab4[i];
}
free(tab4);
 
return sum;
}
 
/* error */
int test5(void)
{
int i, sum = 0;
int *tab4;
 
tab4 = malloc(20 * sizeof(int));
for(i=0;i<21;i++) {
sum += tab4[i];
}
free(tab4);
 
return sum;
}
 
/* error */
/* XXX: currently: bug */
int test6(void)
{
int i, sum = 0;
int *tab4;
tab4 = malloc(20 * sizeof(int));
free(tab4);
for(i=0;i<21;i++) {
sum += tab4[i];
}
 
return sum;
}
 
/* error */
int test7(void)
{
int i, sum = 0;
int *p;
 
for(i=0;i<TAB_SIZE + 1;i++) {
p = &tab[i];
if (i == TAB_SIZE)
printf("i=%d %x\n", i, p);
sum += *p;
}
return sum;
}
 
/* ok */
int test8(void)
{
int i, sum = 0;
int tab[10];
 
for(i=0;i<10;i++) {
sum += tab[i];
}
return sum;
}
 
/* error */
int test9(void)
{
int i, sum = 0;
char tab[10];
 
for(i=0;i<11;i++) {
sum += tab[i];
}
return sum;
}
 
/* ok */
int test10(void)
{
char tab[10];
char tab1[10];
 
memset(tab, 0, 10);
memcpy(tab, tab1, 10);
memmove(tab, tab1, 10);
return 0;
}
 
/* error */
int test11(void)
{
char tab[10];
 
memset(tab, 0, 11);
return 0;
}
 
/* error */
int test12(void)
{
void *ptr;
ptr = malloc(10);
free(ptr);
free(ptr);
return 0;
}
 
/* error */
int test13(void)
{
char pad1 = 0;
char tab[10];
char pad2 = 0;
memset(tab, 'a', sizeof(tab));
return strlen(tab);
}
 
int (*table_test[])(void) = {
test1,
test1,
test2,
test3,
test4,
test5,
test6,
test7,
test8,
test9,
test10,
test11,
test12,
test13,
};
 
int main(int argc, char **argv)
{
int index;
int (*ftest)(void);
 
if (argc < 2) {
printf("usage: boundtest n\n"
"test TCC bound checking system\n"
);
exit(1);
}
 
index = 0;
if (argc >= 2)
index = atoi(argv[1]);
/* well, we also use bounds on this ! */
ftest = table_test[index];
ftest();
 
return 0;
}
 
/*
* without bound 0.77 s
* with bounds 4.73
*/
/programs/develop/metcc/trunk/source/c67-gen.c
0,0 → 1,2548
/*
* TMS320C67xx code generator for TCC
*
* Copyright (c) 2001, 2002 Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
 
//#define ASSEMBLY_LISTING_C67
 
/* number of available registers */
#define NB_REGS 24
 
/* a register can belong to several classes. The classes must be
sorted from more general to more precise (see gv2() code which does
assumptions on it). */
#define RC_INT 0x0001 /* generic integer register */
#define RC_FLOAT 0x0002 /* generic float register */
#define RC_EAX 0x0004
#define RC_ST0 0x0008
#define RC_ECX 0x0010
#define RC_EDX 0x0020
#define RC_INT_BSIDE 0x00000040 /* generic integer register on b side */
#define RC_C67_A4 0x00000100
#define RC_C67_A5 0x00000200
#define RC_C67_B4 0x00000400
#define RC_C67_B5 0x00000800
#define RC_C67_A6 0x00001000
#define RC_C67_A7 0x00002000
#define RC_C67_B6 0x00004000
#define RC_C67_B7 0x00008000
#define RC_C67_A8 0x00010000
#define RC_C67_A9 0x00020000
#define RC_C67_B8 0x00040000
#define RC_C67_B9 0x00080000
#define RC_C67_A10 0x00100000
#define RC_C67_A11 0x00200000
#define RC_C67_B10 0x00400000
#define RC_C67_B11 0x00800000
#define RC_C67_A12 0x01000000
#define RC_C67_A13 0x02000000
#define RC_C67_B12 0x04000000
#define RC_C67_B13 0x08000000
#define RC_IRET RC_C67_A4 /* function return: integer register */
#define RC_LRET RC_C67_A5 /* function return: second integer register */
#define RC_FRET RC_C67_A4 /* function return: float register */
 
/* pretty names for the registers */
enum {
TREG_EAX = 0, // really A2
TREG_ECX, // really A3
TREG_EDX, // really B0
TREG_ST0, // really B1
TREG_C67_A4,
TREG_C67_A5,
TREG_C67_B4,
TREG_C67_B5,
TREG_C67_A6,
TREG_C67_A7,
TREG_C67_B6,
TREG_C67_B7,
TREG_C67_A8,
TREG_C67_A9,
TREG_C67_B8,
TREG_C67_B9,
TREG_C67_A10,
TREG_C67_A11,
TREG_C67_B10,
TREG_C67_B11,
TREG_C67_A12,
TREG_C67_A13,
TREG_C67_B12,
TREG_C67_B13,
};
 
int reg_classes[NB_REGS] = {
/* eax */ RC_INT | RC_FLOAT | RC_EAX,
// only allow even regs for floats (allow for doubles)
/* ecx */ RC_INT | RC_ECX,
/* edx */ RC_INT | RC_INT_BSIDE | RC_FLOAT | RC_EDX,
// only allow even regs for floats (allow for doubles)
/* st0 */ RC_INT | RC_INT_BSIDE | RC_ST0,
/* A4 */ RC_C67_A4,
/* A5 */ RC_C67_A5,
/* B4 */ RC_C67_B4,
/* B5 */ RC_C67_B5,
/* A6 */ RC_C67_A6,
/* A7 */ RC_C67_A7,
/* B6 */ RC_C67_B6,
/* B7 */ RC_C67_B7,
/* A8 */ RC_C67_A8,
/* A9 */ RC_C67_A9,
/* B8 */ RC_C67_B8,
/* B9 */ RC_C67_B9,
/* A10 */ RC_C67_A10,
/* A11 */ RC_C67_A11,
/* B10 */ RC_C67_B10,
/* B11 */ RC_C67_B11,
/* A12 */ RC_C67_A10,
/* A13 */ RC_C67_A11,
/* B12 */ RC_C67_B10,
/* B13 */ RC_C67_B11
};
 
/* return registers for function */
#define REG_IRET TREG_C67_A4 /* single word int return register */
#define REG_LRET TREG_C67_A5 /* second word return register (for long long) */
#define REG_FRET TREG_C67_A4 /* float return register */
 
 
#define ALWAYS_ASSERT(x) \
do {\
if (!(x))\
error("internal compiler error file at %s:%d", __FILE__, __LINE__);\
} while (0)
 
// although tcc thinks it is passing parameters on the stack,
// the C67 really passes up to the first 10 params in special
// regs or regs pairs (for 64 bit params). So keep track of
// the stack offsets so we can translate to the appropriate
// reg (pair)
 
 
#define NoCallArgsPassedOnStack 10
int NoOfCurFuncArgs;
int TranslateStackToReg[NoCallArgsPassedOnStack];
int ParamLocOnStack[NoCallArgsPassedOnStack];
int TotalBytesPushedOnStack;
 
/* defined if function parameters must be evaluated in reverse order */
 
//#define INVERT_FUNC_PARAMS
 
/* defined if structures are passed as pointers. Otherwise structures
are directly pushed on stack. */
//#define FUNC_STRUCT_PARAM_AS_PTR
 
/* pointer size, in bytes */
#define PTR_SIZE 4
 
/* long double size and alignment, in bytes */
#define LDOUBLE_SIZE 12
#define LDOUBLE_ALIGN 4
/* maximum alignment (for aligned attribute support) */
#define MAX_ALIGN 8
 
/******************************************************/
/* ELF defines */
 
#define EM_TCC_TARGET EM_C60
 
/* relocation type for 32 bit data relocation */
#define R_DATA_32 R_C60_32
#define R_JMP_SLOT R_C60_JMP_SLOT
#define R_COPY R_C60_COPY
 
#define ELF_START_ADDR 0x00000400
#define ELF_PAGE_SIZE 0x1000
 
/******************************************************/
 
static unsigned long func_sub_sp_offset;
static int func_ret_sub;
 
 
static BOOL C67_invert_test;
static int C67_compare_reg;
 
#ifdef ASSEMBLY_LISTING_C67
FILE *f = NULL;
#endif
 
 
void C67_g(int c)
{
int ind1;
 
#ifdef ASSEMBLY_LISTING_C67
fprintf(f, " %08X", c);
#endif
ind1 = ind + 4;
if (ind1 > (int) cur_text_section->data_allocated)
section_realloc(cur_text_section, ind1);
cur_text_section->data[ind] = c & 0xff;
cur_text_section->data[ind + 1] = (c >> 8) & 0xff;
cur_text_section->data[ind + 2] = (c >> 16) & 0xff;
cur_text_section->data[ind + 3] = (c >> 24) & 0xff;
ind = ind1;
}
 
 
/* output a symbol and patch all calls to it */
void gsym_addr(int t, int a)
{
int n, *ptr;
while (t) {
ptr = (int *) (cur_text_section->data + t);
{
Sym *sym;
 
// extract 32 bit address from MVKH/MVKL
n = ((*ptr >> 7) & 0xffff);
n |= ((*(ptr + 1) >> 7) & 0xffff) << 16;
 
// define a label that will be relocated
 
sym = get_sym_ref(&char_pointer_type, cur_text_section, a, 0);
greloc(cur_text_section, sym, t, R_C60LO16);
greloc(cur_text_section, sym, t + 4, R_C60HI16);
 
// clear out where the pointer was
 
*ptr &= ~(0xffff << 7);
*(ptr + 1) &= ~(0xffff << 7);
}
t = n;
}
}
 
void gsym(int t)
{
gsym_addr(t, ind);
}
 
// these are regs that tcc doesn't really know about,
// but asign them unique values so the mapping routines
// can distinquish them
 
#define C67_A0 105
#define C67_SP 106
#define C67_B3 107
#define C67_FP 108
#define C67_B2 109
#define C67_CREG_ZERO -1 // Special code for no condition reg test
 
 
int ConvertRegToRegClass(int r)
{
// only works for A4-B13
 
return RC_C67_A4 << (r - TREG_C67_A4);
}
 
 
// map TCC reg to C67 reg number
 
int C67_map_regn(int r)
{
if (r == 0) // normal tcc regs
return 0x2; // A2
else if (r == 1) // normal tcc regs
return 3; // A3
else if (r == 2) // normal tcc regs
return 0; // B0
else if (r == 3) // normal tcc regs
return 1; // B1
else if (r >= TREG_C67_A4 && r <= TREG_C67_B13) // these form a pattern of alt pairs
return (((r & 0xfffffffc) >> 1) | (r & 1)) + 2;
else if (r == C67_A0)
return 0; // set to A0 (offset reg)
else if (r == C67_B2)
return 2; // set to B2 (offset reg)
else if (r == C67_B3)
return 3; // set to B3 (return address reg)
else if (r == C67_SP)
return 15; // set to SP (B15) (offset reg)
else if (r == C67_FP)
return 15; // set to FP (A15) (offset reg)
else if (r == C67_CREG_ZERO)
return 0; // Special code for no condition reg test
else
ALWAYS_ASSERT(FALSE);
 
return 0;
}
 
// mapping from tcc reg number to
// C67 register to condition code field
//
// valid condition code regs are:
//
// tcc reg 2 ->B0 -> 1
// tcc reg 3 ->B1 -> 2
// tcc reg 0 -> A2 -> 5
// tcc reg 1 -> A3 -> X
// tcc reg B2 -> 3
 
int C67_map_regc(int r)
{
if (r == 0) // normal tcc regs
return 0x5;
else if (r == 2) // normal tcc regs
return 0x1;
else if (r == 3) // normal tcc regs
return 0x2;
else if (r == C67_B2) // normal tcc regs
return 0x3;
else if (r == C67_CREG_ZERO)
return 0; // Special code for no condition reg test
else
ALWAYS_ASSERT(FALSE);
 
return 0;
}
 
 
// map TCC reg to C67 reg side A or B
 
int C67_map_regs(int r)
{
if (r == 0) // normal tcc regs
return 0x0;
else if (r == 1) // normal tcc regs
return 0x0;
else if (r == 2) // normal tcc regs
return 0x1;
else if (r == 3) // normal tcc regs
return 0x1;
else if (r >= TREG_C67_A4 && r <= TREG_C67_B13) // these form a pattern of alt pairs
return (r & 2) >> 1;
else if (r == C67_A0)
return 0; // set to A side
else if (r == C67_B2)
return 1; // set to B side
else if (r == C67_B3)
return 1; // set to B side
else if (r == C67_SP)
return 0x1; // set to SP (B15) B side
else if (r == C67_FP)
return 0x0; // set to FP (A15) A side
else
ALWAYS_ASSERT(FALSE);
 
return 0;
}
 
int C67_map_S12(char *s)
{
if (strstr(s, ".S1") != NULL)
return 0;
else if (strcmp(s, ".S2"))
return 1;
else
ALWAYS_ASSERT(FALSE);
 
return 0;
}
 
int C67_map_D12(char *s)
{
if (strstr(s, ".D1") != NULL)
return 0;
else if (strcmp(s, ".D2"))
return 1;
else
ALWAYS_ASSERT(FALSE);
 
return 0;
}
 
 
 
void C67_asm(char *s, int a, int b, int c)
{
BOOL xpath;
 
#ifdef ASSEMBLY_LISTING_C67
if (!f) {
f = fopen("TCC67_out.txt", "wt");
}
fprintf(f, "%04X ", ind);
#endif
 
if (strstr(s, "MVKL") == s) {
C67_g((C67_map_regn(b) << 23) |
((a & 0xffff) << 7) | (0x0a << 2) | (C67_map_regs(b) << 1));
} else if (strstr(s, "MVKH") == s) {
C67_g((C67_map_regn(b) << 23) |
(((a >> 16) & 0xffff) << 7) |
(0x1a << 2) | (C67_map_regs(b) << 1));
} else if (strstr(s, "STW.D SP POST DEC") == s) {
C67_g((C67_map_regn(a) << 23) | //src
(15 << 18) | //SP B15
(2 << 13) | //ucst5 (must keep 8 byte boundary !!)
(0xa << 9) | //mode a = post dec ucst
(0 << 8) | //r (LDDW bit 0)
(1 << 7) | //y D1/D2 use B side
(7 << 4) | //ldst 3=STB, 5=STH 5, 7=STW, 6=LDW 4=LDH 2=LDB 0=LDHU 1=LDBU
(1 << 2) | //opcode
(C67_map_regs(a) << 1) | //side of src
(0 << 0)); //parallel
} else if (strstr(s, "STB.D *+SP[A0]") == s) {
C67_g((C67_map_regn(a) << 23) | //src
(15 << 18) | //base reg A15
(0 << 13) | //offset reg A0
(5 << 9) | //mode 5 = pos offset, base reg + off reg
(0 << 8) | //r (LDDW bit 0)
(0 << 7) | //y D1/D2 A side
(3 << 4) | //ldst 3=STB, 5=STH 5, 7=STW, 6=LDW 4=LDH 2=LDB 0=LDHU 1=LDBU
(1 << 2) | //opcode
(C67_map_regs(a) << 1) | //side of src
(0 << 0)); //parallel
} else if (strstr(s, "STH.D *+SP[A0]") == s) {
C67_g((C67_map_regn(a) << 23) | //src
(15 << 18) | //base reg A15
(0 << 13) | //offset reg A0
(5 << 9) | //mode 5 = pos offset, base reg + off reg
(0 << 8) | //r (LDDW bit 0)
(0 << 7) | //y D1/D2 A side
(5 << 4) | //ldst 3=STB, 5=STH 5, 7=STW, 6=LDW 4=LDH 2=LDB 0=LDHU 1=LDBU
(1 << 2) | //opcode
(C67_map_regs(a) << 1) | //side of src
(0 << 0)); //parallel
} else if (strstr(s, "STB.D *+SP[A0]") == s) {
C67_g((C67_map_regn(a) << 23) | //src
(15 << 18) | //base reg A15
(0 << 13) | //offset reg A0
(5 << 9) | //mode 5 = pos offset, base reg + off reg
(0 << 8) | //r (LDDW bit 0)
(0 << 7) | //y D1/D2 A side
(3 << 4) | //ldst 3=STB, 5=STH 5, 7=STW, 6=LDW 4=LDH 2=LDB 0=LDHU 1=LDBU
(1 << 2) | //opcode
(C67_map_regs(a) << 1) | //side of src
(0 << 0)); //parallel
} else if (strstr(s, "STH.D *+SP[A0]") == s) {
C67_g((C67_map_regn(a) << 23) | //src
(15 << 18) | //base reg A15
(0 << 13) | //offset reg A0
(5 << 9) | //mode 5 = pos offset, base reg + off reg
(0 << 8) | //r (LDDW bit 0)
(0 << 7) | //y D1/D2 A side
(5 << 4) | //ldst 3=STB, 5=STH 5, 7=STW, 6=LDW 4=LDH 2=LDB 0=LDHU 1=LDBU
(1 << 2) | //opcode
(C67_map_regs(a) << 1) | //side of src
(0 << 0)); //parallel
} else if (strstr(s, "STW.D *+SP[A0]") == s) {
C67_g((C67_map_regn(a) << 23) | //src
(15 << 18) | //base reg A15
(0 << 13) | //offset reg A0
(5 << 9) | //mode 5 = pos offset, base reg + off reg
(0 << 8) | //r (LDDW bit 0)
(0 << 7) | //y D1/D2 A side
(7 << 4) | //ldst 3=STB, 5=STH 5, 7=STW, 6=LDW 4=LDH 2=LDB 0=LDHU 1=LDBU
(1 << 2) | //opcode
(C67_map_regs(a) << 1) | //side of src
(0 << 0)); //parallel
} else if (strstr(s, "STW.D *") == s) {
C67_g((C67_map_regn(a) << 23) | //src
(C67_map_regn(b) << 18) | //base reg A0
(0 << 13) | //cst5
(1 << 9) | //mode 1 = pos cst offset
(0 << 8) | //r (LDDW bit 0)
(C67_map_regs(b) << 7) | //y D1/D2 base reg side
(7 << 4) | //ldst 3=STB, 5=STH 5, 7=STW, 6=LDW 4=LDH 2=LDB 0=LDHU 1=LDBU
(1 << 2) | //opcode
(C67_map_regs(a) << 1) | //side of src
(0 << 0)); //parallel
} else if (strstr(s, "STH.D *") == s) {
C67_g((C67_map_regn(a) << 23) | //src
(C67_map_regn(b) << 18) | //base reg A0
(0 << 13) | //cst5
(1 << 9) | //mode 1 = pos cst offset
(0 << 8) | //r (LDDW bit 0)
(C67_map_regs(b) << 7) | //y D1/D2 base reg side
(5 << 4) | //ldst 3=STB, 5=STH 5, 7=STW, 6=LDW 4=LDH 2=LDB 0=LDHU 1=LDBU
(1 << 2) | //opcode
(C67_map_regs(a) << 1) | //side of src
(0 << 0)); //parallel
} else if (strstr(s, "STB.D *") == s) {
C67_g((C67_map_regn(a) << 23) | //src
(C67_map_regn(b) << 18) | //base reg A0
(0 << 13) | //cst5
(1 << 9) | //mode 1 = pos cst offset
(0 << 8) | //r (LDDW bit 0)
(C67_map_regs(b) << 7) | //y D1/D2 base reg side
(3 << 4) | //ldst 3=STB, 5=STH 5, 7=STW, 6=LDW 4=LDH 2=LDB 0=LDHU 1=LDBU
(1 << 2) | //opcode
(C67_map_regs(a) << 1) | //side of src
(0 << 0)); //parallel
} else if (strstr(s, "STW.D +*") == s) {
ALWAYS_ASSERT(c < 32);
C67_g((C67_map_regn(a) << 23) | //src
(C67_map_regn(b) << 18) | //base reg A0
(c << 13) | //cst5
(1 << 9) | //mode 1 = pos cst offset
(0 << 8) | //r (LDDW bit 0)
(C67_map_regs(b) << 7) | //y D1/D2 base reg side
(7 << 4) | //ldst 3=STB, 5=STH 5, 7=STW, 6=LDW 4=LDH 2=LDB 0=LDHU 1=LDBU
(1 << 2) | //opcode
(C67_map_regs(a) << 1) | //side of src
(0 << 0)); //parallel
} else if (strstr(s, "LDW.D SP PRE INC") == s) {
C67_g((C67_map_regn(a) << 23) | //dst
(15 << 18) | //base reg B15
(2 << 13) | //ucst5 (must keep 8 byte boundary)
(9 << 9) | //mode 9 = pre inc ucst5
(0 << 8) | //r (LDDW bit 0)
(1 << 7) | //y D1/D2 B side
(6 << 4) | //ldst 3=STB, 5=STH 5, 7=STW, 6=LDW 4=LDH 2=LDB 0=LDHU 1=LDBU
(1 << 2) | //opcode
(C67_map_regs(a) << 1) | //side of dst
(0 << 0)); //parallel
} else if (strstr(s, "LDDW.D SP PRE INC") == s) {
C67_g((C67_map_regn(a) << 23) | //dst
(15 << 18) | //base reg B15
(1 << 13) | //ucst5 (must keep 8 byte boundary)
(9 << 9) | //mode 9 = pre inc ucst5
(1 << 8) | //r (LDDW bit 1)
(1 << 7) | //y D1/D2 B side
(6 << 4) | //ldst 3=STB, 5=STH 5, 7=STW, 6=LDW 4=LDH 2=LDB 0=LDHU 1=LDBU
(1 << 2) | //opcode
(C67_map_regs(a) << 1) | //side of dst
(0 << 0)); //parallel
} else if (strstr(s, "LDW.D *+SP[A0]") == s) {
C67_g((C67_map_regn(a) << 23) | //dst
(15 << 18) | //base reg A15
(0 << 13) | //offset reg A0
(5 << 9) | //mode 5 = pos offset, base reg + off reg
(0 << 8) | //r (LDDW bit 0)
(0 << 7) | //y D1/D2 A side
(6 << 4) | //ldst 3=STB, 5=STH 5, 7=STW, 6=LDW 4=LDH 2=LDB 0=LDHU 1=LDBU
(1 << 2) | //opcode
(C67_map_regs(a) << 1) | //side of dst
(0 << 0)); //parallel
} else if (strstr(s, "LDDW.D *+SP[A0]") == s) {
C67_g((C67_map_regn(a) << 23) | //dst
(15 << 18) | //base reg A15
(0 << 13) | //offset reg A0
(5 << 9) | //mode 5 = pos offset, base reg + off reg
(1 << 8) | //r (LDDW bit 1)
(0 << 7) | //y D1/D2 A side
(6 << 4) | //ldst 3=STB, 5=STH 5, 7=STW, 6=LDW 4=LDH 2=LDB 0=LDHU 1=LDBU
(1 << 2) | //opcode
(C67_map_regs(a) << 1) | //side of dst
(0 << 0)); //parallel
} else if (strstr(s, "LDH.D *+SP[A0]") == s) {
C67_g((C67_map_regn(a) << 23) | //dst
(15 << 18) | //base reg A15
(0 << 13) | //offset reg A0
(5 << 9) | //mode 5 = pos offset, base reg + off reg
(0 << 8) | //r (LDDW bit 0)
(0 << 7) | //y D1/D2 A side
(4 << 4) | //ldst 3=STB, 5=STH 5, 7=STW, 6=LDW 4=LDH 2=LDB 0=LDHU 1=LDBU
(1 << 2) | //opcode
(C67_map_regs(a) << 1) | //side of dst
(0 << 0)); //parallel
} else if (strstr(s, "LDB.D *+SP[A0]") == s) {
C67_g((C67_map_regn(a) << 23) | //dst
(15 << 18) | //base reg A15
(0 << 13) | //offset reg A0
(5 << 9) | //mode 5 = pos offset, base reg + off reg
(0 << 8) | //r (LDDW bit 0)
(0 << 7) | //y D1/D2 A side
(2 << 4) | //ldst 3=STB, 5=STH 5, 7=STW, 6=LDW 4=LDH 2=LDB 0=LDHU 1=LDBU
(1 << 2) | //opcode
(C67_map_regs(a) << 1) | //side of dst
(0 << 0)); //parallel
} else if (strstr(s, "LDHU.D *+SP[A0]") == s) {
C67_g((C67_map_regn(a) << 23) | //dst
(15 << 18) | //base reg A15
(0 << 13) | //offset reg A0
(5 << 9) | //mode 5 = pos offset, base reg + off reg
(0 << 8) | //r (LDDW bit 0)
(0 << 7) | //y D1/D2 A side
(0 << 4) | //ldst 3=STB, 5=STH 5, 7=STW, 6=LDW 4=LDH 2=LDB 0=LDHU 1=LDBU
(1 << 2) | //opcode
(C67_map_regs(a) << 1) | //side of dst
(0 << 0)); //parallel
} else if (strstr(s, "LDBU.D *+SP[A0]") == s) {
C67_g((C67_map_regn(a) << 23) | //dst
(15 << 18) | //base reg A15
(0 << 13) | //offset reg A0
(5 << 9) | //mode 5 = pos offset, base reg + off reg
(0 << 8) | //r (LDDW bit 0)
(0 << 7) | //y D1/D2 A side
(1 << 4) | //ldst 3=STB, 5=STH 5, 7=STW, 6=LDW 4=LDH 2=LDB 0=LDHU 1=LDBU
(1 << 2) | //opcode
(C67_map_regs(a) << 1) | //side of dst
(0 << 0)); //parallel
} else if (strstr(s, "LDW.D *") == s) {
C67_g((C67_map_regn(b) << 23) | //dst
(C67_map_regn(a) << 18) | //base reg A15
(0 << 13) | //cst5
(1 << 9) | //mode 1 = pos cst offset
(0 << 8) | //r (LDDW bit 0)
(C67_map_regs(a) << 7) | //y D1/D2 src side
(6 << 4) | //ldst 3=STB, 5=STH 5, 7=STW, 6=LDW 4=LDH 2=LDB 0=LDHU 1=LDBU
(1 << 2) | //opcode
(C67_map_regs(b) << 1) | //side of dst
(0 << 0)); //parallel
} else if (strstr(s, "LDDW.D *") == s) {
C67_g((C67_map_regn(b) << 23) | //dst
(C67_map_regn(a) << 18) | //base reg A15
(0 << 13) | //cst5
(1 << 9) | //mode 1 = pos cst offset
(1 << 8) | //r (LDDW bit 1)
(C67_map_regs(a) << 7) | //y D1/D2 src side
(6 << 4) | //ldst 3=STB, 5=STH 5, 7=STW, 6=LDW 4=LDH 2=LDB 0=LDHU 1=LDBU
(1 << 2) | //opcode
(C67_map_regs(b) << 1) | //side of dst
(0 << 0)); //parallel
} else if (strstr(s, "LDH.D *") == s) {
C67_g((C67_map_regn(b) << 23) | //dst
(C67_map_regn(a) << 18) | //base reg A15
(0 << 13) | //cst5
(1 << 9) | //mode 1 = pos cst offset
(0 << 8) | //r (LDDW bit 0)
(C67_map_regs(a) << 7) | //y D1/D2 src side
(4 << 4) | //ldst 3=STB, 5=STH 5, 7=STW, 6=LDW 4=LDH 2=LDB 0=LDHU 1=LDBU
(1 << 2) | //opcode
(C67_map_regs(b) << 1) | //side of dst
(0 << 0)); //parallel
} else if (strstr(s, "LDB.D *") == s) {
C67_g((C67_map_regn(b) << 23) | //dst
(C67_map_regn(a) << 18) | //base reg A15
(0 << 13) | //cst5
(1 << 9) | //mode 1 = pos cst offset
(0 << 8) | //r (LDDW bit 0)
(C67_map_regs(a) << 7) | //y D1/D2 src side
(2 << 4) | //ldst 3=STB, 5=STH 5, 7=STW, 6=LDW 4=LDH 2=LDB 0=LDHU 1=LDBU
(1 << 2) | //opcode
(C67_map_regs(b) << 1) | //side of dst
(0 << 0)); //parallel
} else if (strstr(s, "LDHU.D *") == s) {
C67_g((C67_map_regn(b) << 23) | //dst
(C67_map_regn(a) << 18) | //base reg A15
(0 << 13) | //cst5
(1 << 9) | //mode 1 = pos cst offset
(0 << 8) | //r (LDDW bit 0)
(C67_map_regs(a) << 7) | //y D1/D2 src side
(0 << 4) | //ldst 3=STB, 5=STH 5, 7=STW, 6=LDW 4=LDH 2=LDB 0=LDHU 1=LDBU
(1 << 2) | //opcode
(C67_map_regs(b) << 1) | //side of dst
(0 << 0)); //parallel
} else if (strstr(s, "LDBU.D *") == s) {
C67_g((C67_map_regn(b) << 23) | //dst
(C67_map_regn(a) << 18) | //base reg A15
(0 << 13) | //cst5
(1 << 9) | //mode 1 = pos cst offset
(0 << 8) | //r (LDDW bit 0)
(C67_map_regs(a) << 7) | //y D1/D2 src side
(1 << 4) | //ldst 3=STB, 5=STH 5, 7=STW, 6=LDW 4=LDH 2=LDB 0=LDHU 1=LDBU
(1 << 2) | //opcode
(C67_map_regs(b) << 1) | //side of dst
(0 << 0)); //parallel
} else if (strstr(s, "LDW.D +*") == s) {
C67_g((C67_map_regn(b) << 23) | //dst
(C67_map_regn(a) << 18) | //base reg A15
(1 << 13) | //cst5
(1 << 9) | //mode 1 = pos cst offset
(0 << 8) | //r (LDDW bit 0)
(C67_map_regs(a) << 7) | //y D1/D2 src side
(6 << 4) | //ldst 3=STB, 5=STH 5, 7=STW, 6=LDW 4=LDH 2=LDB 0=LDHU 1=LDBU
(1 << 2) | //opcode
(C67_map_regs(b) << 1) | //side of dst
(0 << 0)); //parallel
} else if (strstr(s, "CMPLTSP") == s) {
xpath = C67_map_regs(a) ^ C67_map_regs(b);
ALWAYS_ASSERT(C67_map_regs(c) == C67_map_regs(a));
 
C67_g((C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2
(C67_map_regn(a) << 13) | //src1
(xpath << 12) | //x use cross path for src2
(0x3a << 6) | //opcode
(0x8 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side for reg c
(0 << 0)); //parallel
} else if (strstr(s, "CMPGTSP") == s) {
xpath = C67_map_regs(a) ^ C67_map_regs(b);
ALWAYS_ASSERT(C67_map_regs(c) == C67_map_regs(a));
 
C67_g((C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2
(C67_map_regn(a) << 13) | //src1
(xpath << 12) | //x use cross path for src2
(0x39 << 6) | //opcode
(0x8 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side for reg c
(0 << 0)); //parallel
} else if (strstr(s, "CMPEQSP") == s) {
xpath = C67_map_regs(a) ^ C67_map_regs(b);
ALWAYS_ASSERT(C67_map_regs(c) == C67_map_regs(a));
 
C67_g((C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2
(C67_map_regn(a) << 13) | //src1
(xpath << 12) | //x use cross path for src2
(0x38 << 6) | //opcode
(0x8 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side for reg c
(0 << 0)); //parallel
}
 
else if (strstr(s, "CMPLTDP") == s) {
xpath = C67_map_regs(a) ^ C67_map_regs(b);
ALWAYS_ASSERT(C67_map_regs(c) == C67_map_regs(a));
 
C67_g((C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2
(C67_map_regn(a) << 13) | //src1
(xpath << 12) | //x use cross path for src2
(0x2a << 6) | //opcode
(0x8 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side for reg c
(0 << 0)); //parallel
} else if (strstr(s, "CMPGTDP") == s) {
xpath = C67_map_regs(a) ^ C67_map_regs(b);
ALWAYS_ASSERT(C67_map_regs(c) == C67_map_regs(a));
 
C67_g((C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2
(C67_map_regn(a) << 13) | //src1
(xpath << 12) | //x use cross path for src2
(0x29 << 6) | //opcode
(0x8 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side for reg c
(0 << 0)); //parallel
} else if (strstr(s, "CMPEQDP") == s) {
xpath = C67_map_regs(a) ^ C67_map_regs(b);
ALWAYS_ASSERT(C67_map_regs(c) == C67_map_regs(a));
 
C67_g((C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2
(C67_map_regn(a) << 13) | //src1
(xpath << 12) | //x use cross path for src2
(0x28 << 6) | //opcode
(0x8 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side for reg c
(0 << 0)); //parallel
} else if (strstr(s, "CMPLT") == s) {
xpath = C67_map_regs(a) ^ C67_map_regs(b);
ALWAYS_ASSERT(C67_map_regs(c) == C67_map_regs(a));
 
C67_g((C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2
(C67_map_regn(a) << 13) | //src1
(xpath << 12) | //x use cross path for src2
(0x57 << 5) | //opcode
(0x6 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side for reg c
(0 << 0)); //parallel
} else if (strstr(s, "CMPGT") == s) {
xpath = C67_map_regs(a) ^ C67_map_regs(b);
ALWAYS_ASSERT(C67_map_regs(c) == C67_map_regs(a));
 
C67_g((C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2
(C67_map_regn(a) << 13) | //src1
(xpath << 12) | //x use cross path for src2
(0x47 << 5) | //opcode
(0x6 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side for reg c
(0 << 0)); //parallel
} else if (strstr(s, "CMPEQ") == s) {
xpath = C67_map_regs(a) ^ C67_map_regs(b);
ALWAYS_ASSERT(C67_map_regs(c) == C67_map_regs(a));
 
C67_g((C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2
(C67_map_regn(a) << 13) | //src1
(xpath << 12) | //x use cross path for src2
(0x53 << 5) | //opcode
(0x6 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side for reg c
(0 << 0)); //parallel
} else if (strstr(s, "CMPLTU") == s) {
xpath = C67_map_regs(a) ^ C67_map_regs(b);
ALWAYS_ASSERT(C67_map_regs(c) == C67_map_regs(a));
 
C67_g((C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2
(C67_map_regn(a) << 13) | //src1
(xpath << 12) | //x use cross path for src2
(0x5f << 5) | //opcode
(0x6 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side for reg c
(0 << 0)); //parallel
} else if (strstr(s, "CMPGTU") == s) {
xpath = C67_map_regs(a) ^ C67_map_regs(b);
ALWAYS_ASSERT(C67_map_regs(c) == C67_map_regs(a));
 
C67_g((C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2
(C67_map_regn(a) << 13) | //src1
(xpath << 12) | //x use cross path for src2
(0x4f << 5) | //opcode
(0x6 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side for reg c
(0 << 0)); //parallel
} else if (strstr(s, "B DISP") == s) {
C67_g((0 << 29) | //creg
(0 << 28) | //z
(a << 7) | //cnst
(0x4 << 2) | //opcode fixed
(0 << 1) | //S0/S1
(0 << 0)); //parallel
} else if (strstr(s, "B.") == s) {
xpath = C67_map_regs(c) ^ 1;
 
C67_g((C67_map_regc(b) << 29) | //creg
(a << 28) | //inv
(0 << 23) | //dst
(C67_map_regn(c) << 18) | //src2
(0 << 13) | //
(xpath << 12) | //x cross path if !B side
(0xd << 6) | //opcode
(0x8 << 2) | //opcode fixed
(1 << 1) | //must be S2
(0 << 0)); //parallel
} else if (strstr(s, "MV.L") == s) {
xpath = C67_map_regs(b) ^ C67_map_regs(c);
 
C67_g((0 << 29) | //creg
(0 << 28) | //inv
(C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2
(0 << 13) | //src1 (cst5)
(xpath << 12) | //x cross path if opposite sides
(0x2 << 5) | //opcode
(0x6 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side of dest
(0 << 0)); //parallel
} else if (strstr(s, "SPTRUNC.L") == s) {
xpath = C67_map_regs(b) ^ C67_map_regs(c);
 
C67_g((0 << 29) | //creg
(0 << 28) | //inv
(C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2
(0 << 13) | //src1 NA
(xpath << 12) | //x cross path if opposite sides
(0xb << 5) | //opcode
(0x6 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side of dest
(0 << 0)); //parallel
} else if (strstr(s, "DPTRUNC.L") == s) {
xpath = C67_map_regs(b) ^ C67_map_regs(c);
 
C67_g((0 << 29) | //creg
(0 << 28) | //inv
(C67_map_regn(c) << 23) | //dst
((C67_map_regn(b) + 1) << 18) | //src2 WEIRD CPU must specify odd reg for some reason
(0 << 13) | //src1 NA
(xpath << 12) | //x cross path if opposite sides
(0x1 << 5) | //opcode
(0x6 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side of dest
(0 << 0)); //parallel
} else if (strstr(s, "INTSP.L") == s) {
xpath = C67_map_regs(b) ^ C67_map_regs(c);
 
C67_g((0 << 29) | //creg
(0 << 28) | //inv
(C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2
(0 << 13) | //src1 NA
(xpath << 12) | //x cross path if opposite sides
(0x4a << 5) | //opcode
(0x6 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side of dest
(0 << 0)); //parallel
} else if (strstr(s, "INTSPU.L") == s) {
xpath = C67_map_regs(b) ^ C67_map_regs(c);
 
C67_g((0 << 29) | //creg
(0 << 28) | //inv
(C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2
(0 << 13) | //src1 NA
(xpath << 12) | //x cross path if opposite sides
(0x49 << 5) | //opcode
(0x6 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side of dest
(0 << 0)); //parallel
} else if (strstr(s, "INTDP.L") == s) {
xpath = C67_map_regs(b) ^ C67_map_regs(c);
 
C67_g((0 << 29) | //creg
(0 << 28) | //inv
(C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2
(0 << 13) | //src1 NA
(xpath << 12) | //x cross path if opposite sides
(0x39 << 5) | //opcode
(0x6 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side of dest
(0 << 0)); //parallel
} else if (strstr(s, "INTDPU.L") == s) {
xpath = C67_map_regs(b) ^ C67_map_regs(c);
 
C67_g((0 << 29) | //creg
(0 << 28) | //inv
(C67_map_regn(c) << 23) | //dst
((C67_map_regn(b) + 1) << 18) | //src2 WEIRD CPU must specify odd reg for some reason
(0 << 13) | //src1 NA
(xpath << 12) | //x cross path if opposite sides
(0x3b << 5) | //opcode
(0x6 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side of dest
(0 << 0)); //parallel
} else if (strstr(s, "SPDP.L") == s) {
xpath = C67_map_regs(b) ^ C67_map_regs(c);
 
C67_g((0 << 29) | //creg
(0 << 28) | //inv
(C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2
(0 << 13) | //src1 NA
(xpath << 12) | //x cross path if opposite sides
(0x2 << 6) | //opcode
(0x8 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side of dest
(0 << 0)); //parallel
} else if (strstr(s, "DPSP.L") == s) {
ALWAYS_ASSERT(C67_map_regs(b) == C67_map_regs(c));
 
C67_g((0 << 29) | //creg
(0 << 28) | //inv
(C67_map_regn(c) << 23) | //dst
((C67_map_regn(b) + 1) << 18) | //src2 WEIRD CPU must specify odd reg for some reason
(0 << 13) | //src1 NA
(0 << 12) | //x cross path if opposite sides
(0x9 << 5) | //opcode
(0x6 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side of dest
(0 << 0)); //parallel
} else if (strstr(s, "ADD.L") == s) {
xpath = C67_map_regs(b) ^ C67_map_regs(c);
 
ALWAYS_ASSERT(C67_map_regs(a) == C67_map_regs(c));
 
C67_g((0 << 29) | //creg
(0 << 28) | //inv
(C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2 (possible x path)
(C67_map_regn(a) << 13) | //src1
(xpath << 12) | //x cross path if opposite sides
(0x3 << 5) | //opcode
(0x6 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side of dest
(0 << 0)); //parallel
} else if (strstr(s, "SUB.L") == s) {
xpath = C67_map_regs(b) ^ C67_map_regs(c);
 
ALWAYS_ASSERT(C67_map_regs(a) == C67_map_regs(c));
 
C67_g((0 << 29) | //creg
(0 << 28) | //inv
(C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2 (possible x path)
(C67_map_regn(a) << 13) | //src1
(xpath << 12) | //x cross path if opposite sides
(0x7 << 5) | //opcode
(0x6 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side of dest
(0 << 0)); //parallel
} else if (strstr(s, "OR.L") == s) {
xpath = C67_map_regs(b) ^ C67_map_regs(c);
 
ALWAYS_ASSERT(C67_map_regs(a) == C67_map_regs(c));
 
C67_g((0 << 29) | //creg
(0 << 28) | //inv
(C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2 (possible x path)
(C67_map_regn(a) << 13) | //src1
(xpath << 12) | //x cross path if opposite sides
(0x7f << 5) | //opcode
(0x6 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side of dest
(0 << 0)); //parallel
} else if (strstr(s, "AND.L") == s) {
xpath = C67_map_regs(b) ^ C67_map_regs(c);
 
ALWAYS_ASSERT(C67_map_regs(a) == C67_map_regs(c));
 
C67_g((0 << 29) | //creg
(0 << 28) | //inv
(C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2 (possible x path)
(C67_map_regn(a) << 13) | //src1
(xpath << 12) | //x cross path if opposite sides
(0x7b << 5) | //opcode
(0x6 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side of dest
(0 << 0)); //parallel
} else if (strstr(s, "XOR.L") == s) {
xpath = C67_map_regs(b) ^ C67_map_regs(c);
 
ALWAYS_ASSERT(C67_map_regs(a) == C67_map_regs(c));
 
C67_g((0 << 29) | //creg
(0 << 28) | //inv
(C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2 (possible x path)
(C67_map_regn(a) << 13) | //src1
(xpath << 12) | //x cross path if opposite sides
(0x6f << 5) | //opcode
(0x6 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side of dest
(0 << 0)); //parallel
} else if (strstr(s, "ADDSP.L") == s) {
xpath = C67_map_regs(b) ^ C67_map_regs(c);
 
ALWAYS_ASSERT(C67_map_regs(a) == C67_map_regs(c));
 
C67_g((0 << 29) | //creg
(0 << 28) | //inv
(C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2 (possible x path)
(C67_map_regn(a) << 13) | //src1
(xpath << 12) | //x cross path if opposite sides
(0x10 << 5) | //opcode
(0x6 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side of dest
(0 << 0)); //parallel
} else if (strstr(s, "ADDDP.L") == s) {
xpath = C67_map_regs(b) ^ C67_map_regs(c);
 
ALWAYS_ASSERT(C67_map_regs(a) == C67_map_regs(c));
 
C67_g((0 << 29) | //creg
(0 << 28) | //inv
(C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2 (possible x path)
(C67_map_regn(a) << 13) | //src1
(xpath << 12) | //x cross path if opposite sides
(0x18 << 5) | //opcode
(0x6 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side of dest
(0 << 0)); //parallel
} else if (strstr(s, "SUBSP.L") == s) {
xpath = C67_map_regs(b) ^ C67_map_regs(c);
 
ALWAYS_ASSERT(C67_map_regs(a) == C67_map_regs(c));
 
C67_g((0 << 29) | //creg
(0 << 28) | //inv
(C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2 (possible x path)
(C67_map_regn(a) << 13) | //src1
(xpath << 12) | //x cross path if opposite sides
(0x11 << 5) | //opcode
(0x6 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side of dest
(0 << 0)); //parallel
} else if (strstr(s, "SUBDP.L") == s) {
xpath = C67_map_regs(b) ^ C67_map_regs(c);
 
ALWAYS_ASSERT(C67_map_regs(a) == C67_map_regs(c));
 
C67_g((0 << 29) | //creg
(0 << 28) | //inv
(C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2 (possible x path)
(C67_map_regn(a) << 13) | //src1
(xpath << 12) | //x cross path if opposite sides
(0x19 << 5) | //opcode
(0x6 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side of dest
(0 << 0)); //parallel
} else if (strstr(s, "MPYSP.M") == s) {
xpath = C67_map_regs(b) ^ C67_map_regs(c);
 
ALWAYS_ASSERT(C67_map_regs(a) == C67_map_regs(c));
 
C67_g((0 << 29) | //creg
(0 << 28) | //inv
(C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2 (possible x path)
(C67_map_regn(a) << 13) | //src1
(xpath << 12) | //x cross path if opposite sides
(0x1c << 7) | //opcode
(0x0 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side of dest
(0 << 0)); //parallel
} else if (strstr(s, "MPYDP.M") == s) {
xpath = C67_map_regs(b) ^ C67_map_regs(c);
 
ALWAYS_ASSERT(C67_map_regs(a) == C67_map_regs(c));
 
C67_g((0 << 29) | //creg
(0 << 28) | //inv
(C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2 (possible x path)
(C67_map_regn(a) << 13) | //src1
(xpath << 12) | //x cross path if opposite sides
(0x0e << 7) | //opcode
(0x0 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side of dest
(0 << 0)); //parallel
} else if (strstr(s, "MPYI.M") == s) {
xpath = C67_map_regs(b) ^ C67_map_regs(c);
 
ALWAYS_ASSERT(C67_map_regs(a) == C67_map_regs(c));
 
C67_g((0 << 29) | //creg
(0 << 28) | //inv
(C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2
(C67_map_regn(a) << 13) | //src1 (cst5)
(xpath << 12) | //x cross path if opposite sides
(0x4 << 7) | //opcode
(0x0 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side of dest
(0 << 0)); //parallel
} else if (strstr(s, "SHR.S") == s) {
xpath = C67_map_regs(b) ^ C67_map_regs(c);
 
ALWAYS_ASSERT(C67_map_regs(c) == C67_map_regs(a));
 
C67_g((0 << 29) | //creg
(0 << 28) | //inv
(C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2
(C67_map_regn(a) << 13) | //src1
(xpath << 12) | //x cross path if opposite sides
(0x37 << 6) | //opcode
(0x8 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side of dest
(0 << 0)); //parallel
} else if (strstr(s, "SHRU.S") == s) {
xpath = C67_map_regs(b) ^ C67_map_regs(c);
 
ALWAYS_ASSERT(C67_map_regs(c) == C67_map_regs(a));
 
C67_g((0 << 29) | //creg
(0 << 28) | //inv
(C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2
(C67_map_regn(a) << 13) | //src1
(xpath << 12) | //x cross path if opposite sides
(0x27 << 6) | //opcode
(0x8 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side of dest
(0 << 0)); //parallel
} else if (strstr(s, "SHL.S") == s) {
xpath = C67_map_regs(b) ^ C67_map_regs(c);
 
ALWAYS_ASSERT(C67_map_regs(c) == C67_map_regs(a));
 
C67_g((0 << 29) | //creg
(0 << 28) | //inv
(C67_map_regn(c) << 23) | //dst
(C67_map_regn(b) << 18) | //src2
(C67_map_regn(a) << 13) | //src1
(xpath << 12) | //x cross path if opposite sides
(0x33 << 6) | //opcode
(0x8 << 2) | //opcode fixed
(C67_map_regs(c) << 1) | //side of dest
(0 << 0)); //parallel
} else if (strstr(s, "||ADDK") == s) {
xpath = 0; // no xpath required just use the side of the src/dst
 
C67_g((0 << 29) | //creg
(0 << 28) | //inv
(C67_map_regn(b) << 23) | //dst
(a << 07) | //scst16
(0x14 << 2) | //opcode fixed
(C67_map_regs(b) << 1) | //side of dst
(1 << 0)); //parallel
} else if (strstr(s, "ADDK") == s) {
xpath = 0; // no xpath required just use the side of the src/dst
 
C67_g((0 << 29) | //creg
(0 << 28) | //inv
(C67_map_regn(b) << 23) | //dst
(a << 07) | //scst16
(0x14 << 2) | //opcode fixed
(C67_map_regs(b) << 1) | //side of dst
(0 << 0)); //parallel
} else if (strstr(s, "NOP") == s) {
C67_g(((a - 1) << 13) | //no of cycles
(0 << 0)); //parallel
} else
ALWAYS_ASSERT(FALSE);
 
#ifdef ASSEMBLY_LISTING_C67
fprintf(f, " %s %d %d %d\n", s, a, b, c);
#endif
 
}
 
//r=reg to load, fr=from reg, symbol for relocation, constant
 
void C67_MVKL(int r, int fc)
{
C67_asm("MVKL.", fc, r, 0);
}
 
void C67_MVKH(int r, int fc)
{
C67_asm("MVKH.", fc, r, 0);
}
 
void C67_STB_SP_A0(int r)
{
C67_asm("STB.D *+SP[A0]", r, 0, 0); // STB r,*+SP[A0]
}
 
void C67_STH_SP_A0(int r)
{
C67_asm("STH.D *+SP[A0]", r, 0, 0); // STH r,*+SP[A0]
}
 
void C67_STW_SP_A0(int r)
{
C67_asm("STW.D *+SP[A0]", r, 0, 0); // STW r,*+SP[A0]
}
 
void C67_STB_PTR(int r, int r2)
{
C67_asm("STB.D *", r, r2, 0); // STB r, *r2
}
 
void C67_STH_PTR(int r, int r2)
{
C67_asm("STH.D *", r, r2, 0); // STH r, *r2
}
 
void C67_STW_PTR(int r, int r2)
{
C67_asm("STW.D *", r, r2, 0); // STW r, *r2
}
 
void C67_STW_PTR_PRE_INC(int r, int r2, int n)
{
C67_asm("STW.D +*", r, r2, n); // STW r, *+r2
}
 
void C67_PUSH(int r)
{
C67_asm("STW.D SP POST DEC", r, 0, 0); // STW r,*SP--
}
 
void C67_LDW_SP_A0(int r)
{
C67_asm("LDW.D *+SP[A0]", r, 0, 0); // LDW *+SP[A0],r
}
 
void C67_LDDW_SP_A0(int r)
{
C67_asm("LDDW.D *+SP[A0]", r, 0, 0); // LDDW *+SP[A0],r
}
 
void C67_LDH_SP_A0(int r)
{
C67_asm("LDH.D *+SP[A0]", r, 0, 0); // LDH *+SP[A0],r
}
 
void C67_LDB_SP_A0(int r)
{
C67_asm("LDB.D *+SP[A0]", r, 0, 0); // LDB *+SP[A0],r
}
 
void C67_LDHU_SP_A0(int r)
{
C67_asm("LDHU.D *+SP[A0]", r, 0, 0); // LDHU *+SP[A0],r
}
 
void C67_LDBU_SP_A0(int r)
{
C67_asm("LDBU.D *+SP[A0]", r, 0, 0); // LDBU *+SP[A0],r
}
 
void C67_LDW_PTR(int r, int r2)
{
C67_asm("LDW.D *", r, r2, 0); // LDW *r,r2
}
 
void C67_LDDW_PTR(int r, int r2)
{
C67_asm("LDDW.D *", r, r2, 0); // LDDW *r,r2
}
 
void C67_LDH_PTR(int r, int r2)
{
C67_asm("LDH.D *", r, r2, 0); // LDH *r,r2
}
 
void C67_LDB_PTR(int r, int r2)
{
C67_asm("LDB.D *", r, r2, 0); // LDB *r,r2
}
 
void C67_LDHU_PTR(int r, int r2)
{
C67_asm("LDHU.D *", r, r2, 0); // LDHU *r,r2
}
 
void C67_LDBU_PTR(int r, int r2)
{
C67_asm("LDBU.D *", r, r2, 0); // LDBU *r,r2
}
 
void C67_LDW_PTR_PRE_INC(int r, int r2)
{
C67_asm("LDW.D +*", r, r2, 0); // LDW *+r,r2
}
 
void C67_POP(int r)
{
C67_asm("LDW.D SP PRE INC", r, 0, 0); // LDW *++SP,r
}
 
void C67_POP_DW(int r)
{
C67_asm("LDDW.D SP PRE INC", r, 0, 0); // LDDW *++SP,r
}
 
void C67_CMPLT(int s1, int s2, int dst)
{
C67_asm("CMPLT.L1", s1, s2, dst);
}
 
void C67_CMPGT(int s1, int s2, int dst)
{
C67_asm("CMPGT.L1", s1, s2, dst);
}
 
void C67_CMPEQ(int s1, int s2, int dst)
{
C67_asm("CMPEQ.L1", s1, s2, dst);
}
 
void C67_CMPLTU(int s1, int s2, int dst)
{
C67_asm("CMPLTU.L1", s1, s2, dst);
}
 
void C67_CMPGTU(int s1, int s2, int dst)
{
C67_asm("CMPGTU.L1", s1, s2, dst);
}
 
 
void C67_CMPLTSP(int s1, int s2, int dst)
{
C67_asm("CMPLTSP.S1", s1, s2, dst);
}
 
void C67_CMPGTSP(int s1, int s2, int dst)
{
C67_asm("CMPGTSP.S1", s1, s2, dst);
}
 
void C67_CMPEQSP(int s1, int s2, int dst)
{
C67_asm("CMPEQSP.S1", s1, s2, dst);
}
 
void C67_CMPLTDP(int s1, int s2, int dst)
{
C67_asm("CMPLTDP.S1", s1, s2, dst);
}
 
void C67_CMPGTDP(int s1, int s2, int dst)
{
C67_asm("CMPGTDP.S1", s1, s2, dst);
}
 
void C67_CMPEQDP(int s1, int s2, int dst)
{
C67_asm("CMPEQDP.S1", s1, s2, dst);
}
 
 
void C67_IREG_B_REG(int inv, int r1, int r2) // [!R] B r2
{
C67_asm("B.S2", inv, r1, r2);
}
 
 
// call with how many 32 bit words to skip
// (0 would branch to the branch instruction)
 
void C67_B_DISP(int disp) // B +2 Branch with constant displacement
{
// Branch point is relative to the 8 word fetch packet
//
// we will assume the text section always starts on an 8 word (32 byte boundary)
//
// so add in how many words into the fetch packet the branch is
 
 
C67_asm("B DISP", disp + ((ind & 31) >> 2), 0, 0);
}
 
void C67_NOP(int n)
{
C67_asm("NOP", n, 0, 0);
}
 
void C67_ADDK(int n, int r)
{
ALWAYS_ASSERT(abs(n) < 32767);
 
C67_asm("ADDK", n, r, 0);
}
 
void C67_ADDK_PARALLEL(int n, int r)
{
ALWAYS_ASSERT(abs(n) < 32767);
 
C67_asm("||ADDK", n, r, 0);
}
 
void C67_Adjust_ADDK(int *inst, int n)
{
ALWAYS_ASSERT(abs(n) < 32767);
 
*inst = (*inst & (~(0xffff << 7))) | ((n & 0xffff) << 7);
}
 
void C67_MV(int r, int v)
{
C67_asm("MV.L", 0, r, v);
}
 
 
void C67_DPTRUNC(int r, int v)
{
C67_asm("DPTRUNC.L", 0, r, v);
}
 
void C67_SPTRUNC(int r, int v)
{
C67_asm("SPTRUNC.L", 0, r, v);
}
 
void C67_INTSP(int r, int v)
{
C67_asm("INTSP.L", 0, r, v);
}
 
void C67_INTDP(int r, int v)
{
C67_asm("INTDP.L", 0, r, v);
}
 
void C67_INTSPU(int r, int v)
{
C67_asm("INTSPU.L", 0, r, v);
}
 
void C67_INTDPU(int r, int v)
{
C67_asm("INTDPU.L", 0, r, v);
}
 
void C67_SPDP(int r, int v)
{
C67_asm("SPDP.L", 0, r, v);
}
 
void C67_DPSP(int r, int v) // note regs must be on the same side
{
C67_asm("DPSP.L", 0, r, v);
}
 
void C67_ADD(int r, int v)
{
C67_asm("ADD.L", v, r, v);
}
 
void C67_SUB(int r, int v)
{
C67_asm("SUB.L", v, r, v);
}
 
void C67_AND(int r, int v)
{
C67_asm("AND.L", v, r, v);
}
 
void C67_OR(int r, int v)
{
C67_asm("OR.L", v, r, v);
}
 
void C67_XOR(int r, int v)
{
C67_asm("XOR.L", v, r, v);
}
 
void C67_ADDSP(int r, int v)
{
C67_asm("ADDSP.L", v, r, v);
}
 
void C67_SUBSP(int r, int v)
{
C67_asm("SUBSP.L", v, r, v);
}
 
void C67_MPYSP(int r, int v)
{
C67_asm("MPYSP.M", v, r, v);
}
 
void C67_ADDDP(int r, int v)
{
C67_asm("ADDDP.L", v, r, v);
}
 
void C67_SUBDP(int r, int v)
{
C67_asm("SUBDP.L", v, r, v);
}
 
void C67_MPYDP(int r, int v)
{
C67_asm("MPYDP.M", v, r, v);
}
 
void C67_MPYI(int r, int v)
{
C67_asm("MPYI.M", v, r, v);
}
 
void C67_SHL(int r, int v)
{
C67_asm("SHL.S", r, v, v);
}
 
void C67_SHRU(int r, int v)
{
C67_asm("SHRU.S", r, v, v);
}
 
void C67_SHR(int r, int v)
{
C67_asm("SHR.S", r, v, v);
}
 
 
 
/* load 'r' from value 'sv' */
void load(int r, SValue * sv)
{
int v, t, ft, fc, fr, size = 0, element;
BOOL Unsigned = false;
SValue v1;
 
fr = sv->r;
ft = sv->type.t;
fc = sv->c.ul;
 
v = fr & VT_VALMASK;
if (fr & VT_LVAL) {
if (v == VT_LLOCAL) {
v1.type.t = VT_INT;
v1.r = VT_LOCAL | VT_LVAL;
v1.c.ul = fc;
load(r, &v1);
fr = r;
} else if ((ft & VT_BTYPE) == VT_LDOUBLE) {
error("long double not supported");
} else if ((ft & VT_TYPE) == VT_BYTE) {
size = 1;
} else if ((ft & VT_TYPE) == (VT_BYTE | VT_UNSIGNED)) {
size = 1;
Unsigned = TRUE;
} else if ((ft & VT_TYPE) == VT_SHORT) {
size = 2;
} else if ((ft & VT_TYPE) == (VT_SHORT | VT_UNSIGNED)) {
size = 2;
Unsigned = TRUE;
} else if ((ft & VT_BTYPE) == VT_DOUBLE) {
size = 8;
} else {
size = 4;
}
 
// check if fc is a positive reference on the stack,
// if it is tcc is referencing what it thinks is a parameter
// on the stack, so check if it is really in a register.
 
 
if (v == VT_LOCAL && fc > 0) {
int stack_pos = 8;
 
for (t = 0; t < NoCallArgsPassedOnStack; t++) {
if (fc == stack_pos)
break;
 
stack_pos += TranslateStackToReg[t];
}
 
// param has been pushed on stack, get it like a local var
 
fc = ParamLocOnStack[t] - 8;
}
 
if ((fr & VT_VALMASK) < VT_CONST) // check for pure indirect
{
if (size == 1) {
if (Unsigned)
C67_LDBU_PTR(v, r); // LDBU *v,r
else
C67_LDB_PTR(v, r); // LDB *v,r
} else if (size == 2) {
if (Unsigned)
C67_LDHU_PTR(v, r); // LDHU *v,r
else
C67_LDH_PTR(v, r); // LDH *v,r
} else if (size == 4) {
C67_LDW_PTR(v, r); // LDW *v,r
} else if (size == 8) {
C67_LDDW_PTR(v, r); // LDDW *v,r
}
 
C67_NOP(4); // NOP 4
return;
} else if (fr & VT_SYM) {
greloc(cur_text_section, sv->sym, ind, R_C60LO16); // rem the inst need to be patched
greloc(cur_text_section, sv->sym, ind + 4, R_C60HI16);
 
 
C67_MVKL(C67_A0, fc); //r=reg to load, constant
C67_MVKH(C67_A0, fc); //r=reg to load, constant
 
 
if (size == 1) {
if (Unsigned)
C67_LDBU_PTR(C67_A0, r); // LDBU *A0,r
else
C67_LDB_PTR(C67_A0, r); // LDB *A0,r
} else if (size == 2) {
if (Unsigned)
C67_LDHU_PTR(C67_A0, r); // LDHU *A0,r
else
C67_LDH_PTR(C67_A0, r); // LDH *A0,r
} else if (size == 4) {
C67_LDW_PTR(C67_A0, r); // LDW *A0,r
} else if (size == 8) {
C67_LDDW_PTR(C67_A0, r); // LDDW *A0,r
}
 
C67_NOP(4); // NOP 4
return;
} else {
element = size;
 
// divide offset in bytes to create element index
C67_MVKL(C67_A0, (fc / element) + 8 / element); //r=reg to load, constant
C67_MVKH(C67_A0, (fc / element) + 8 / element); //r=reg to load, constant
 
if (size == 1) {
if (Unsigned)
C67_LDBU_SP_A0(r); // LDBU r, SP[A0]
else
C67_LDB_SP_A0(r); // LDB r, SP[A0]
} else if (size == 2) {
if (Unsigned)
C67_LDHU_SP_A0(r); // LDHU r, SP[A0]
else
C67_LDH_SP_A0(r); // LDH r, SP[A0]
} else if (size == 4) {
C67_LDW_SP_A0(r); // LDW r, SP[A0]
} else if (size == 8) {
C67_LDDW_SP_A0(r); // LDDW r, SP[A0]
}
 
 
C67_NOP(4); // NOP 4
return;
}
} else {
if (v == VT_CONST) {
if (fr & VT_SYM) {
greloc(cur_text_section, sv->sym, ind, R_C60LO16); // rem the inst need to be patched
greloc(cur_text_section, sv->sym, ind + 4, R_C60HI16);
}
C67_MVKL(r, fc); //r=reg to load, constant
C67_MVKH(r, fc); //r=reg to load, constant
} else if (v == VT_LOCAL) {
C67_MVKL(r, fc + 8); //r=reg to load, constant C67 stack points to next free
C67_MVKH(r, fc + 8); //r=reg to load, constant
C67_ADD(C67_FP, r); // MV v,r v -> r
} else if (v == VT_CMP) {
C67_MV(C67_compare_reg, r); // MV v,r v -> r
} else if (v == VT_JMP || v == VT_JMPI) {
t = v & 1;
C67_B_DISP(4); // Branch with constant displacement, skip over this branch, load, nop, load
C67_MVKL(r, t); // r=reg to load, 0 or 1 (do this while branching)
C67_NOP(4); // NOP 4
gsym(fc); // modifies other branches to branch here
C67_MVKL(r, t ^ 1); // r=reg to load, 0 or 1
} else if (v != r) {
C67_MV(v, r); // MV v,r v -> r
 
if ((ft & VT_BTYPE) == VT_DOUBLE)
C67_MV(v + 1, r + 1); // MV v,r v -> r
}
}
}
 
 
/* store register 'r' in lvalue 'v' */
void store(int r, SValue * v)
{
int fr, bt, ft, fc, size, t, element;
 
ft = v->type.t;
fc = v->c.ul;
fr = v->r & VT_VALMASK;
bt = ft & VT_BTYPE;
/* XXX: incorrect if float reg to reg */
 
if (bt == VT_LDOUBLE) {
error("long double not supported");
} else {
if (bt == VT_SHORT)
size = 2;
else if (bt == VT_BYTE)
size = 1;
else if (bt == VT_DOUBLE)
size = 8;
else
size = 4;
 
if ((v->r & VT_VALMASK) == VT_CONST) {
/* constant memory reference */
 
if (v->r & VT_SYM) {
greloc(cur_text_section, v->sym, ind, R_C60LO16); // rem the inst need to be patched
greloc(cur_text_section, v->sym, ind + 4, R_C60HI16);
}
C67_MVKL(C67_A0, fc); //r=reg to load, constant
C67_MVKH(C67_A0, fc); //r=reg to load, constant
 
if (size == 1)
C67_STB_PTR(r, C67_A0); // STB r, *A0
else if (size == 2)
C67_STH_PTR(r, C67_A0); // STH r, *A0
else if (size == 4 || size == 8)
C67_STW_PTR(r, C67_A0); // STW r, *A0
 
if (size == 8)
C67_STW_PTR_PRE_INC(r + 1, C67_A0, 1); // STW r, *+A0[1]
} else if ((v->r & VT_VALMASK) == VT_LOCAL) {
// check case of storing to passed argument that
// tcc thinks is on the stack but for C67 is
// passed as a reg. However it may have been
// saved to the stack, if that reg was required
// for a call to a child function
 
if (fc > 0) // argument ??
{
// walk through sizes and figure which param
 
int stack_pos = 8;
 
for (t = 0; t < NoCallArgsPassedOnStack; t++) {
if (fc == stack_pos)
break;
 
stack_pos += TranslateStackToReg[t];
}
 
// param has been pushed on stack, get it like a local var
fc = ParamLocOnStack[t] - 8;
}
 
if (size == 8)
element = 4;
else
element = size;
 
// divide offset in bytes to create word index
C67_MVKL(C67_A0, (fc / element) + 8 / element); //r=reg to load, constant
C67_MVKH(C67_A0, (fc / element) + 8 / element); //r=reg to load, constant
 
 
 
if (size == 1)
C67_STB_SP_A0(r); // STB r, SP[A0]
else if (size == 2)
C67_STH_SP_A0(r); // STH r, SP[A0]
else if (size == 4 || size == 8)
C67_STW_SP_A0(r); // STW r, SP[A0]
 
if (size == 8) {
C67_ADDK(1, C67_A0); // ADDK 1,A0
C67_STW_SP_A0(r + 1); // STW r, SP[A0]
}
} else {
if (size == 1)
C67_STB_PTR(r, fr); // STB r, *fr
else if (size == 2)
C67_STH_PTR(r, fr); // STH r, *fr
else if (size == 4 || size == 8)
C67_STW_PTR(r, fr); // STW r, *fr
 
if (size == 8) {
C67_STW_PTR_PRE_INC(r + 1, fr, 1); // STW r, *+fr[1]
}
}
}
}
 
/* 'is_jmp' is '1' if it is a jump */
static void gcall_or_jmp(int is_jmp)
{
int r;
Sym *sym;
 
if ((vtop->r & (VT_VALMASK | VT_LVAL)) == VT_CONST) {
/* constant case */
if (vtop->r & VT_SYM) {
/* relocation case */
 
// get add into A0, then start the jump B3
 
greloc(cur_text_section, vtop->sym, ind, R_C60LO16); // rem the inst need to be patched
greloc(cur_text_section, vtop->sym, ind + 4, R_C60HI16);
 
C67_MVKL(C67_A0, 0); //r=reg to load, constant
C67_MVKH(C67_A0, 0); //r=reg to load, constant
C67_IREG_B_REG(0, C67_CREG_ZERO, C67_A0); // B.S2x A0
 
if (is_jmp) {
C67_NOP(5); // simple jump, just put NOP
} else {
// Call, must load return address into B3 during delay slots
 
sym = get_sym_ref(&char_pointer_type, cur_text_section, ind + 12, 0); // symbol for return address
greloc(cur_text_section, sym, ind, R_C60LO16); // rem the inst need to be patched
greloc(cur_text_section, sym, ind + 4, R_C60HI16);
C67_MVKL(C67_B3, 0); //r=reg to load, constant
C67_MVKH(C67_B3, 0); //r=reg to load, constant
C67_NOP(3); // put remaining NOPs
}
} else {
/* put an empty PC32 relocation */
ALWAYS_ASSERT(FALSE);
}
} else {
/* otherwise, indirect call */
r = gv(RC_INT);
C67_IREG_B_REG(0, C67_CREG_ZERO, r); // B.S2x r
 
if (is_jmp) {
C67_NOP(5); // simple jump, just put NOP
} else {
// Call, must load return address into B3 during delay slots
 
sym = get_sym_ref(&char_pointer_type, cur_text_section, ind + 12, 0); // symbol for return address
greloc(cur_text_section, sym, ind, R_C60LO16); // rem the inst need to be patched
greloc(cur_text_section, sym, ind + 4, R_C60HI16);
C67_MVKL(C67_B3, 0); //r=reg to load, constant
C67_MVKH(C67_B3, 0); //r=reg to load, constant
C67_NOP(3); // put remaining NOPs
}
}
}
 
/* generate function call with address in (vtop->t, vtop->c) and free function
context. Stack entry is popped */
void gfunc_call(int nb_args)
{
int i, r, size = 0;
int args_sizes[NoCallArgsPassedOnStack];
 
if (nb_args > NoCallArgsPassedOnStack) {
error("more than 10 function params not currently supported");
// handle more than 10, put some on the stack
}
 
for (i = 0; i < nb_args; i++) {
if ((vtop->type.t & VT_BTYPE) == VT_STRUCT) {
ALWAYS_ASSERT(FALSE);
} else if ((vtop->type.t & VT_BTYPE) == VT_STRUCT) {
ALWAYS_ASSERT(FALSE);
} else {
/* simple type (currently always same size) */
/* XXX: implicit cast ? */
 
 
if ((vtop->type.t & VT_BTYPE) == VT_LLONG) {
error("long long not supported");
} else if ((vtop->type.t & VT_BTYPE) == VT_LDOUBLE) {
error("long double not supported");
} else if ((vtop->type.t & VT_BTYPE) == VT_DOUBLE) {
size = 8;
} else {
size = 4;
}
 
// put the parameter into the corresponding reg (pair)
 
r = gv(RC_C67_A4 << (2 * i));
 
// must put on stack because with 1 pass compiler , no way to tell
// if an up coming nested call might overwrite these regs
 
C67_PUSH(r);
 
if (size == 8) {
C67_STW_PTR_PRE_INC(r + 1, C67_SP, 3); // STW r, *+SP[3] (go back and put the other)
}
args_sizes[i] = size;
}
vtop--;
}
// POP all the params on the stack into registers for the
// immediate call (in reverse order)
 
for (i = nb_args - 1; i >= 0; i--) {
 
if (args_sizes[i] == 8)
C67_POP_DW(TREG_C67_A4 + i * 2);
else
C67_POP(TREG_C67_A4 + i * 2);
}
gcall_or_jmp(0);
vtop--;
}
 
 
// to be compatible with Code Composer for the C67
// the first 10 parameters must be passed in registers
// (pairs for 64 bits) starting wit; A4:A5, then B4:B5 and
// ending with B12:B13.
//
// When a call is made, if the caller has its parameters
// in regs A4-B13 these must be saved before/as the call
// parameters are loaded and restored upon return (or if/when needed).
 
/* generate function prolog of type 't' */
void gfunc_prolog(CType * func_type)
{
int addr, align, size, func_call, i;
Sym *sym;
CType *type;
 
sym = func_type->ref;
func_call = sym->r;
addr = 8;
/* if the function returns a structure, then add an
implicit pointer parameter */
func_vt = sym->type;
if ((func_vt.t & VT_BTYPE) == VT_STRUCT) {
func_vc = addr;
addr += 4;
}
 
NoOfCurFuncArgs = 0;
 
/* define parameters */
while ((sym = sym->next) != NULL) {
type = &sym->type;
sym_push(sym->v & ~SYM_FIELD, type, VT_LOCAL | VT_LVAL, addr);
size = type_size(type, &align);
size = (size + 3) & ~3;
 
// keep track of size of arguments so
// we can translate where tcc thinks they
// are on the stack into the appropriate reg
 
TranslateStackToReg[NoOfCurFuncArgs] = size;
NoOfCurFuncArgs++;
 
#ifdef FUNC_STRUCT_PARAM_AS_PTR
/* structs are passed as pointer */
if ((type->t & VT_BTYPE) == VT_STRUCT) {
size = 4;
}
#endif
addr += size;
}
func_ret_sub = 0;
/* pascal type call ? */
if (func_call == FUNC_STDCALL)
func_ret_sub = addr - 8;
 
C67_MV(C67_FP, C67_A0); // move FP -> A0
C67_MV(C67_SP, C67_FP); // move SP -> FP
 
// place all the args passed in regs onto the stack
 
loc = 0;
for (i = 0; i < NoOfCurFuncArgs; i++) {
 
ParamLocOnStack[i] = loc; // remember where the param is
loc += -8;
 
C67_PUSH(TREG_C67_A4 + i * 2);
 
if (TranslateStackToReg[i] == 8) {
C67_STW_PTR_PRE_INC(TREG_C67_A4 + i * 2 + 1, C67_SP, 3); // STW r, *+SP[1] (go back and put the other)
}
}
 
TotalBytesPushedOnStack = -loc;
 
func_sub_sp_offset = ind; // remember where we put the stack instruction
C67_ADDK(0, C67_SP); // ADDK.L2 loc,SP (just put zero temporarily)
 
C67_PUSH(C67_A0);
C67_PUSH(C67_B3);
}
 
/* generate function epilog */
void gfunc_epilog(void)
{
{
int local = (-loc + 7) & -8; // stack must stay aligned to 8 bytes for LDDW instr
C67_POP(C67_B3);
C67_NOP(4); // NOP wait for load
C67_IREG_B_REG(0, C67_CREG_ZERO, C67_B3); // B.S2 B3
C67_POP(C67_FP);
C67_ADDK(local, C67_SP); // ADDK.L2 loc,SP
C67_Adjust_ADDK((int *) (cur_text_section->data +
func_sub_sp_offset),
-local + TotalBytesPushedOnStack);
C67_NOP(3); // NOP
}
}
 
/* generate a jump to a label */
int gjmp(int t)
{
int ind1 = ind;
 
C67_MVKL(C67_A0, t); //r=reg to load, constant
C67_MVKH(C67_A0, t); //r=reg to load, constant
C67_IREG_B_REG(0, C67_CREG_ZERO, C67_A0); // [!R] B.S2x A0
C67_NOP(5);
return ind1;
}
 
/* generate a jump to a fixed address */
void gjmp_addr(int a)
{
Sym *sym;
// I guess this routine is used for relative short
// local jumps, for now just handle it as the general
// case
 
// define a label that will be relocated
 
sym = get_sym_ref(&char_pointer_type, cur_text_section, a, 0);
greloc(cur_text_section, sym, ind, R_C60LO16);
greloc(cur_text_section, sym, ind + 4, R_C60HI16);
 
gjmp(0); // place a zero there later the symbol will be added to it
}
 
/* generate a test. set 'inv' to invert test. Stack entry is popped */
int gtst(int inv, int t)
{
int ind1, n;
int v, *p;
 
v = vtop->r & VT_VALMASK;
if (v == VT_CMP) {
/* fast case : can jump directly since flags are set */
// C67 uses B2 sort of as flags register
ind1 = ind;
C67_MVKL(C67_A0, t); //r=reg to load, constant
C67_MVKH(C67_A0, t); //r=reg to load, constant
 
if (C67_compare_reg != TREG_EAX && // check if not already in a conditional test reg
C67_compare_reg != TREG_EDX &&
C67_compare_reg != TREG_ST0 && C67_compare_reg != C67_B2) {
C67_MV(C67_compare_reg, C67_B2);
C67_compare_reg = C67_B2;
}
 
C67_IREG_B_REG(C67_invert_test ^ inv, C67_compare_reg, C67_A0); // [!R] B.S2x A0
C67_NOP(5);
t = ind1; //return where we need to patch
 
} else if (v == VT_JMP || v == VT_JMPI) {
/* && or || optimization */
if ((v & 1) == inv) {
/* insert vtop->c jump list in t */
p = &vtop->c.i;
 
// I guess the idea is to traverse to the
// null at the end of the list and store t
// there
 
n = *p;
while (n != 0) {
p = (int *) (cur_text_section->data + n);
 
// extract 32 bit address from MVKH/MVKL
n = ((*p >> 7) & 0xffff);
n |= ((*(p + 1) >> 7) & 0xffff) << 16;
}
*p |= (t & 0xffff) << 7;
*(p + 1) |= ((t >> 16) & 0xffff) << 7;
t = vtop->c.i;
 
} else {
t = gjmp(t);
gsym(vtop->c.i);
}
} else {
if (is_float(vtop->type.t)) {
vpushi(0);
gen_op(TOK_NE);
}
if ((vtop->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST) {
/* constant jmp optimization */
if ((vtop->c.i != 0) != inv)
t = gjmp(t);
} else {
// I think we need to get the value on the stack
// into a register, test it, and generate a branch
// return the address of the branch, so it can be
// later patched
 
v = gv(RC_INT); // get value into a reg
ind1 = ind;
C67_MVKL(C67_A0, t); //r=reg to load, constant
C67_MVKH(C67_A0, t); //r=reg to load, constant
 
if (v != TREG_EAX && // check if not already in a conditional test reg
v != TREG_EDX && v != TREG_ST0 && v != C67_B2) {
C67_MV(v, C67_B2);
v = C67_B2;
}
 
C67_IREG_B_REG(inv, v, C67_A0); // [!R] B.S2x A0
C67_NOP(5);
t = ind1; //return where we need to patch
ind1 = ind;
}
}
vtop--;
return t;
}
 
/* generate an integer binary operation */
void gen_opi(int op)
{
int r, fr, opc, t;
 
switch (op) {
case '+':
case TOK_ADDC1: /* add with carry generation */
opc = 0;
gen_op8:
 
 
// C67 can't do const compares, must load into a reg
// so just go to gv2 directly - tktk
 
 
 
if (op >= TOK_ULT && op <= TOK_GT)
gv2(RC_INT_BSIDE, RC_INT); // make sure r (src1) is on the B Side of CPU
else
gv2(RC_INT, RC_INT);
 
r = vtop[-1].r;
fr = vtop[0].r;
 
C67_compare_reg = C67_B2;
 
 
if (op == TOK_LT) {
C67_CMPLT(r, fr, C67_B2);
C67_invert_test = false;
} else if (op == TOK_GE) {
C67_CMPLT(r, fr, C67_B2);
C67_invert_test = true;
} else if (op == TOK_GT) {
C67_CMPGT(r, fr, C67_B2);
C67_invert_test = false;
} else if (op == TOK_LE) {
C67_CMPGT(r, fr, C67_B2);
C67_invert_test = true;
} else if (op == TOK_EQ) {
C67_CMPEQ(r, fr, C67_B2);
C67_invert_test = false;
} else if (op == TOK_NE) {
C67_CMPEQ(r, fr, C67_B2);
C67_invert_test = true;
} else if (op == TOK_ULT) {
C67_CMPLTU(r, fr, C67_B2);
C67_invert_test = false;
} else if (op == TOK_UGE) {
C67_CMPLTU(r, fr, C67_B2);
C67_invert_test = true;
} else if (op == TOK_UGT) {
C67_CMPGTU(r, fr, C67_B2);
C67_invert_test = false;
} else if (op == TOK_ULE) {
C67_CMPGTU(r, fr, C67_B2);
C67_invert_test = true;
} else if (op == '+')
C67_ADD(fr, r); // ADD r,fr,r
else if (op == '-')
C67_SUB(fr, r); // SUB r,fr,r
else if (op == '&')
C67_AND(fr, r); // AND r,fr,r
else if (op == '|')
C67_OR(fr, r); // OR r,fr,r
else if (op == '^')
C67_XOR(fr, r); // XOR r,fr,r
else
ALWAYS_ASSERT(FALSE);
 
vtop--;
if (op >= TOK_ULT && op <= TOK_GT) {
vtop->r = VT_CMP;
vtop->c.i = op;
}
break;
case '-':
case TOK_SUBC1: /* sub with carry generation */
opc = 5;
goto gen_op8;
case TOK_ADDC2: /* add with carry use */
opc = 2;
goto gen_op8;
case TOK_SUBC2: /* sub with carry use */
opc = 3;
goto gen_op8;
case '&':
opc = 4;
goto gen_op8;
case '^':
opc = 6;
goto gen_op8;
case '|':
opc = 1;
goto gen_op8;
case '*':
case TOK_UMULL:
gv2(RC_INT, RC_INT);
r = vtop[-1].r;
fr = vtop[0].r;
vtop--;
C67_MPYI(fr, r); // 32 bit bultiply fr,r,fr
C67_NOP(8); // NOP 8 for worst case
break;
case TOK_SHL:
gv2(RC_INT_BSIDE, RC_INT_BSIDE); // shift amount must be on same side as dst
r = vtop[-1].r;
fr = vtop[0].r;
vtop--;
C67_SHL(fr, r); // arithmetic/logical shift
break;
 
case TOK_SHR:
gv2(RC_INT_BSIDE, RC_INT_BSIDE); // shift amount must be on same side as dst
r = vtop[-1].r;
fr = vtop[0].r;
vtop--;
C67_SHRU(fr, r); // logical shift
break;
 
case TOK_SAR:
gv2(RC_INT_BSIDE, RC_INT_BSIDE); // shift amount must be on same side as dst
r = vtop[-1].r;
fr = vtop[0].r;
vtop--;
C67_SHR(fr, r); // arithmetic shift
break;
 
case '/':
t = TOK__divi;
call_func:
vswap();
/* call generic idiv function */
vpush_global_sym(&func_old_type, t);
vrott(3);
gfunc_call(2);
vpushi(0);
vtop->r = REG_IRET;
vtop->r2 = VT_CONST;
break;
case TOK_UDIV:
case TOK_PDIV:
t = TOK__divu;
goto call_func;
case '%':
t = TOK__remi;
goto call_func;
case TOK_UMOD:
t = TOK__remu;
goto call_func;
 
default:
opc = 7;
goto gen_op8;
}
}
 
/* generate a floating point operation 'v = t1 op t2' instruction. The
two operands are guaranted to have the same floating point type */
/* XXX: need to use ST1 too */
void gen_opf(int op)
{
int ft, fc, fr, r;
 
if (op >= TOK_ULT && op <= TOK_GT)
gv2(RC_EDX, RC_EAX); // make sure src2 is on b side
else
gv2(RC_FLOAT, RC_FLOAT); // make sure src2 is on b side
 
ft = vtop->type.t;
fc = vtop->c.ul;
r = vtop->r;
fr = vtop[-1].r;
 
 
if ((ft & VT_BTYPE) == VT_LDOUBLE)
error("long doubles not supported");
 
if (op >= TOK_ULT && op <= TOK_GT) {
 
r = vtop[-1].r;
fr = vtop[0].r;
 
C67_compare_reg = C67_B2;
 
if (op == TOK_LT) {
if ((ft & VT_BTYPE) == VT_DOUBLE)
C67_CMPLTDP(r, fr, C67_B2);
else
C67_CMPLTSP(r, fr, C67_B2);
 
C67_invert_test = false;
} else if (op == TOK_GE) {
if ((ft & VT_BTYPE) == VT_DOUBLE)
C67_CMPLTDP(r, fr, C67_B2);
else
C67_CMPLTSP(r, fr, C67_B2);
 
C67_invert_test = true;
} else if (op == TOK_GT) {
if ((ft & VT_BTYPE) == VT_DOUBLE)
C67_CMPGTDP(r, fr, C67_B2);
else
C67_CMPGTSP(r, fr, C67_B2);
 
C67_invert_test = false;
} else if (op == TOK_LE) {
if ((ft & VT_BTYPE) == VT_DOUBLE)
C67_CMPGTDP(r, fr, C67_B2);
else
C67_CMPGTSP(r, fr, C67_B2);
 
C67_invert_test = true;
} else if (op == TOK_EQ) {
if ((ft & VT_BTYPE) == VT_DOUBLE)
C67_CMPEQDP(r, fr, C67_B2);
else
C67_CMPEQSP(r, fr, C67_B2);
 
C67_invert_test = false;
} else if (op == TOK_NE) {
if ((ft & VT_BTYPE) == VT_DOUBLE)
C67_CMPEQDP(r, fr, C67_B2);
else
C67_CMPEQSP(r, fr, C67_B2);
 
C67_invert_test = true;
} else {
ALWAYS_ASSERT(FALSE);
}
vtop->r = VT_CMP; // tell TCC that result is in "flags" actually B2
} else {
if (op == '+') {
if ((ft & VT_BTYPE) == VT_DOUBLE) {
C67_ADDDP(r, fr); // ADD fr,r,fr
C67_NOP(6);
} else {
C67_ADDSP(r, fr); // ADD fr,r,fr
C67_NOP(3);
}
vtop--;
} else if (op == '-') {
if ((ft & VT_BTYPE) == VT_DOUBLE) {
C67_SUBDP(r, fr); // SUB fr,r,fr
C67_NOP(6);
} else {
C67_SUBSP(r, fr); // SUB fr,r,fr
C67_NOP(3);
}
vtop--;
} else if (op == '*') {
if ((ft & VT_BTYPE) == VT_DOUBLE) {
C67_MPYDP(r, fr); // MPY fr,r,fr
C67_NOP(9);
} else {
C67_MPYSP(r, fr); // MPY fr,r,fr
C67_NOP(3);
}
vtop--;
} else if (op == '/') {
if ((ft & VT_BTYPE) == VT_DOUBLE) {
// must call intrinsic DP floating point divide
vswap();
/* call generic idiv function */
vpush_global_sym(&func_old_type, TOK__divd);
vrott(3);
gfunc_call(2);
vpushi(0);
vtop->r = REG_FRET;
vtop->r2 = REG_LRET;
 
} else {
// must call intrinsic SP floating point divide
vswap();
/* call generic idiv function */
vpush_global_sym(&func_old_type, TOK__divf);
vrott(3);
gfunc_call(2);
vpushi(0);
vtop->r = REG_FRET;
vtop->r2 = VT_CONST;
}
} else
ALWAYS_ASSERT(FALSE);
 
 
}
}
 
 
/* convert integers to fp 't' type. Must handle 'int', 'unsigned int'
and 'long long' cases. */
void gen_cvt_itof(int t)
{
int r;
 
gv(RC_INT);
r = vtop->r;
 
if ((t & VT_BTYPE) == VT_DOUBLE) {
if (t & VT_UNSIGNED)
C67_INTDPU(r, r);
else
C67_INTDP(r, r);
 
C67_NOP(4);
vtop->type.t = VT_DOUBLE;
} else {
if (t & VT_UNSIGNED)
C67_INTSPU(r, r);
else
C67_INTSP(r, r);
C67_NOP(3);
vtop->type.t = VT_FLOAT;
}
 
}
 
/* convert fp to int 't' type */
/* XXX: handle long long case */
void gen_cvt_ftoi(int t)
{
int r;
 
gv(RC_FLOAT);
r = vtop->r;
 
if (t != VT_INT)
error("long long not supported");
else {
if ((vtop->type.t & VT_BTYPE) == VT_DOUBLE) {
C67_DPTRUNC(r, r);
C67_NOP(3);
} else {
C67_SPTRUNC(r, r);
C67_NOP(3);
}
 
vtop->type.t = VT_INT;
 
}
}
 
/* convert from one floating point type to another */
void gen_cvt_ftof(int t)
{
int r, r2;
 
if ((vtop->type.t & VT_BTYPE) == VT_DOUBLE &&
(t & VT_BTYPE) == VT_FLOAT) {
// convert double to float
 
gv(RC_FLOAT); // get it in a register pair
 
r = vtop->r;
 
C67_DPSP(r, r); // convert it to SP same register
C67_NOP(3);
 
vtop->type.t = VT_FLOAT;
vtop->r2 = VT_CONST; // set this as unused
} else if ((vtop->type.t & VT_BTYPE) == VT_FLOAT &&
(t & VT_BTYPE) == VT_DOUBLE) {
// convert float to double
 
gv(RC_FLOAT); // get it in a register
 
r = vtop->r;
 
if (r == TREG_EAX) { // make sure the paired reg is avail
r2 = get_reg(RC_ECX);
} else if (r == TREG_EDX) {
r2 = get_reg(RC_ST0);
} else {
ALWAYS_ASSERT(FALSE);
r2 = 0; /* avoid warning */
}
 
C67_SPDP(r, r); // convert it to DP same register
C67_NOP(1);
 
vtop->type.t = VT_DOUBLE;
vtop->r2 = r2; // set this as unused
} else {
ALWAYS_ASSERT(FALSE);
}
}
 
/* computed goto support */
void ggoto(void)
{
gcall_or_jmp(1);
vtop--;
}
 
/* end of X86 code generator */
/*************************************************************/
/programs/develop/metcc/trunk/source/coff.h
0,0 → 1,446
/**************************************************************************/
/* COFF.H */
/* COFF data structures and related definitions used by the linker */
/**************************************************************************/
 
/*------------------------------------------------------------------------*/
/* COFF FILE HEADER */
/*------------------------------------------------------------------------*/
struct filehdr {
unsigned short f_magic; /* magic number */
unsigned short f_nscns; /* number of sections */
long f_timdat; /* time & date stamp */
long f_symptr; /* file pointer to symtab */
long f_nsyms; /* number of symtab entries */
unsigned short f_opthdr; /* sizeof(optional hdr) */
unsigned short f_flags; /* flags */
unsigned short f_TargetID; /* for C6x = 0x0099 */
};
 
/*------------------------------------------------------------------------*/
/* File header flags */
/*------------------------------------------------------------------------*/
#define F_RELFLG 0x01 /* relocation info stripped from file */
#define F_EXEC 0x02 /* file is executable (no unresolved refs) */
#define F_LNNO 0x04 /* line nunbers stripped from file */
#define F_LSYMS 0x08 /* local symbols stripped from file */
#define F_GSP10 0x10 /* 34010 version */
#define F_GSP20 0x20 /* 34020 version */
#define F_SWABD 0x40 /* bytes swabbed (in names) */
#define F_AR16WR 0x80 /* byte ordering of an AR16WR (PDP-11) */
#define F_LITTLE 0x100 /* byte ordering of an AR32WR (vax) */
#define F_BIG 0x200 /* byte ordering of an AR32W (3B, maxi) */
#define F_PATCH 0x400 /* contains "patch" list in optional header */
#define F_NODF 0x400
 
#define F_VERSION (F_GSP10 | F_GSP20)
#define F_BYTE_ORDER (F_LITTLE | F_BIG)
#define FILHDR struct filehdr
 
//#define FILHSZ sizeof(FILHDR)
#define FILHSZ 22 // above rounds to align on 4 bytes which causes problems
 
#define COFF_C67_MAGIC 0x00c2
 
/*------------------------------------------------------------------------*/
/* Macros to recognize magic numbers */
/*------------------------------------------------------------------------*/
#define ISMAGIC(x) (((unsigned short)(x))==(unsigned short)magic)
#define ISARCHIVE(x) ((((unsigned short)(x))==(unsigned short)ARTYPE))
#define BADMAGIC(x) (((unsigned short)(x) & 0x8080) && !ISMAGIC(x))
 
/*------------------------------------------------------------------------*/
/* OPTIONAL FILE HEADER */
/*------------------------------------------------------------------------*/
typedef struct aouthdr {
short magic; /* see magic.h */
short vstamp; /* version stamp */
long tsize; /* text size in bytes, padded to FW bdry*/
long dsize; /* initialized data " " */
long bsize; /* uninitialized data " " */
long entrypt; /* entry pt. */
long text_start; /* base of text used for this file */
long data_start; /* base of data used for this file */
} AOUTHDR;
 
#define AOUTSZ sizeof(AOUTHDR)
 
/*----------------------------------------------------------------------*/
/* When a UNIX aout header is to be built in the optional header, */
/* the following magic numbers can appear in that header: */
/* */
/* AOUT1MAGIC : default : readonly sharable text segment */
/* AOUT2MAGIC: : writable text segment */
/* PAGEMAGIC : : configured for paging */
/*----------------------------------------------------------------------*/
#define AOUT1MAGIC 0410
#define AOUT2MAGIC 0407
#define PAGEMAGIC 0413
 
/*------------------------------------------------------------------------*/
/* COMMON ARCHIVE FILE STRUCTURES */
/* */
/* ARCHIVE File Organization: */
/* _______________________________________________ */
/* |__________ARCHIVE_MAGIC_STRING_______________| */
/* |__________ARCHIVE_FILE_MEMBER_1______________| */
/* | | */
/* | Archive File Header "ar_hdr" | */
/* |.............................................| */
/* | Member Contents | */
/* | 1. External symbol directory | */
/* | 2. Text file | */
/* |_____________________________________________| */
/* |________ARCHIVE_FILE_MEMBER_2________________| */
/* | "ar_hdr" | */
/* |.............................................| */
/* | Member Contents (.o or text file) | */
/* |_____________________________________________| */
/* | . . . | */
/* | . . . | */
/* | . . . | */
/* |_____________________________________________| */
/* |________ARCHIVE_FILE_MEMBER_n________________| */
/* | "ar_hdr" | */
/* |.............................................| */
/* | Member Contents | */
/* |_____________________________________________| */
/* */
/*------------------------------------------------------------------------*/
 
#define COFF_ARMAG "!<arch>\n"
#define SARMAG 8
#define ARFMAG "`\n"
 
struct ar_hdr /* archive file member header - printable ascii */
{
char ar_name[16]; /* file member name - `/' terminated */
char ar_date[12]; /* file member date - decimal */
char ar_uid[6]; /* file member user id - decimal */
char ar_gid[6]; /* file member group id - decimal */
char ar_mode[8]; /* file member mode - octal */
char ar_size[10]; /* file member size - decimal */
char ar_fmag[2]; /* ARFMAG - string to end header */
};
 
/*------------------------------------------------------------------------*/
/* SECTION HEADER */
/*------------------------------------------------------------------------*/
struct scnhdr {
char s_name[8]; /* section name */
long s_paddr; /* physical address */
long s_vaddr; /* virtual address */
long s_size; /* section size */
long s_scnptr; /* file ptr to raw data for section */
long s_relptr; /* file ptr to relocation */
long s_lnnoptr; /* file ptr to line numbers */
unsigned int s_nreloc; /* number of relocation entries */
unsigned int s_nlnno; /* number of line number entries */
unsigned int s_flags; /* flags */
unsigned short s_reserved; /* reserved byte */
unsigned short s_page; /* memory page id */
};
 
#define SCNHDR struct scnhdr
#define SCNHSZ sizeof(SCNHDR)
 
/*------------------------------------------------------------------------*/
/* Define constants for names of "special" sections */
/*------------------------------------------------------------------------*/
//#define _TEXT ".text"
#define _DATA ".data"
#define _BSS ".bss"
#define _CINIT ".cinit"
#define _TV ".tv"
 
/*------------------------------------------------------------------------*/
/* The low 4 bits of s_flags is used as a section "type" */
/*------------------------------------------------------------------------*/
#define STYP_REG 0x00 /* "regular" : allocated, relocated, loaded */
#define STYP_DSECT 0x01 /* "dummy" : not allocated, relocated, not loaded */
#define STYP_NOLOAD 0x02 /* "noload" : allocated, relocated, not loaded */
#define STYP_GROUP 0x04 /* "grouped" : formed of input sections */
#define STYP_PAD 0x08 /* "padding" : not allocated, not relocated, loaded */
#define STYP_COPY 0x10 /* "copy" : used for C init tables -
not allocated, relocated,
loaded; reloc & lineno
entries processed normally */
#define STYP_TEXT 0x20 /* section contains text only */
#define STYP_DATA 0x40 /* section contains data only */
#define STYP_BSS 0x80 /* section contains bss only */
 
#define STYP_ALIGN 0x100 /* align flag passed by old version assemblers */
#define ALIGN_MASK 0x0F00 /* part of s_flags that is used for align vals */
#define ALIGNSIZE(x) (1 << ((x & ALIGN_MASK) >> 8))
 
/*------------------------------------------------------------------------*/
/* RELOCATION ENTRIES */
/*------------------------------------------------------------------------*/
struct reloc
{
long r_vaddr; /* (virtual) address of reference */
short r_symndx; /* index into symbol table */
unsigned short r_disp; /* additional bits for address calculation */
unsigned short r_type; /* relocation type */
};
 
#define RELOC struct reloc
#define RELSZ 10 /* sizeof(RELOC) */
 
/*--------------------------------------------------------------------------*/
/* define all relocation types */
/*--------------------------------------------------------------------------*/
 
#define R_ABS 0 /* absolute address - no relocation */
#define R_DIR16 01 /* UNUSED */
#define R_REL16 02 /* UNUSED */
#define R_DIR24 04 /* UNUSED */
#define R_REL24 05 /* 24 bits, direct */
#define R_DIR32 06 /* UNUSED */
#define R_RELBYTE 017 /* 8 bits, direct */
#define R_RELWORD 020 /* 16 bits, direct */
#define R_RELLONG 021 /* 32 bits, direct */
#define R_PCRBYTE 022 /* 8 bits, PC-relative */
#define R_PCRWORD 023 /* 16 bits, PC-relative */
#define R_PCRLONG 024 /* 32 bits, PC-relative */
#define R_OCRLONG 030 /* GSP: 32 bits, one's complement direct */
#define R_GSPPCR16 031 /* GSP: 16 bits, PC relative (in words) */
#define R_GSPOPR32 032 /* GSP: 32 bits, direct big-endian */
#define R_PARTLS16 040 /* Brahma: 16 bit offset of 24 bit address*/
#define R_PARTMS8 041 /* Brahma: 8 bit page of 24 bit address */
#define R_PARTLS7 050 /* DSP: 7 bit offset of 16 bit address */
#define R_PARTMS9 051 /* DSP: 9 bit page of 16 bit address */
#define R_REL13 052 /* DSP: 13 bits, direct */
 
/*------------------------------------------------------------------------*/
/* LINE NUMBER ENTRIES */
/*------------------------------------------------------------------------*/
struct lineno
{
union
{
long l_symndx ; /* sym. table index of function name
iff l_lnno == 0 */
long l_paddr ; /* (physical) address of line number */
} l_addr ;
unsigned short l_lnno ; /* line number */
};
 
#define LINENO struct lineno
#define LINESZ 6 /* sizeof(LINENO) */
 
/*------------------------------------------------------------------------*/
/* STORAGE CLASSES */
/*------------------------------------------------------------------------*/
#define C_EFCN -1 /* physical end of function */
#define C_NULL 0
#define C_AUTO 1 /* automatic variable */
#define C_EXT 2 /* external symbol */
#define C_STAT 3 /* static */
#define C_REG 4 /* register variable */
#define C_EXTDEF 5 /* external definition */
#define C_LABEL 6 /* label */
#define C_ULABEL 7 /* undefined label */
#define C_MOS 8 /* member of structure */
#define C_ARG 9 /* function argument */
#define C_STRTAG 10 /* structure tag */
#define C_MOU 11 /* member of union */
#define C_UNTAG 12 /* union tag */
#define C_TPDEF 13 /* type definition */
#define C_USTATIC 14 /* undefined static */
#define C_ENTAG 15 /* enumeration tag */
#define C_MOE 16 /* member of enumeration */
#define C_REGPARM 17 /* register parameter */
#define C_FIELD 18 /* bit field */
 
#define C_BLOCK 100 /* ".bb" or ".eb" */
#define C_FCN 101 /* ".bf" or ".ef" */
#define C_EOS 102 /* end of structure */
#define C_FILE 103 /* file name */
#define C_LINE 104 /* dummy sclass for line number entry */
#define C_ALIAS 105 /* duplicate tag */
#define C_HIDDEN 106 /* special storage class for external */
/* symbols in dmert public libraries */
/*------------------------------------------------------------------------*/
/* SYMBOL TABLE ENTRIES */
/*------------------------------------------------------------------------*/
 
#define SYMNMLEN 8 /* Number of characters in a symbol name */
#define FILNMLEN 14 /* Number of characters in a file name */
#define DIMNUM 4 /* Number of array dimensions in auxiliary entry */
 
 
struct syment
{
union
{
char _n_name[SYMNMLEN]; /* old COFF version */
struct
{
long _n_zeroes; /* new == 0 */
long _n_offset; /* offset into string table */
} _n_n;
char *_n_nptr[2]; /* allows for overlaying */
} _n;
long n_value; /* value of symbol */
short n_scnum; /* section number */
unsigned short n_type; /* type and derived type */
char n_sclass; /* storage class */
char n_numaux; /* number of aux. entries */
};
 
#define n_name _n._n_name
#define n_nptr _n._n_nptr[1]
#define n_zeroes _n._n_n._n_zeroes
#define n_offset _n._n_n._n_offset
 
/*------------------------------------------------------------------------*/
/* Relocatable symbols have a section number of the */
/* section in which they are defined. Otherwise, section */
/* numbers have the following meanings: */
/*------------------------------------------------------------------------*/
#define N_UNDEF 0 /* undefined symbol */
#define N_ABS -1 /* value of symbol is absolute */
#define N_DEBUG -2 /* special debugging symbol */
#define N_TV (unsigned short)-3 /* needs transfer vector (preload) */
#define P_TV (unsigned short)-4 /* needs transfer vector (postload) */
 
/*------------------------------------------------------------------------*/
/* The fundamental type of a symbol packed into the low */
/* 4 bits of the word. */
/*------------------------------------------------------------------------*/
#define _EF ".ef"
 
#define T_NULL 0 /* no type info */
#define T_ARG 1 /* function argument (only used by compiler) */
#define T_CHAR 2 /* character */
#define T_SHORT 3 /* short integer */
#define T_INT 4 /* integer */
#define T_LONG 5 /* long integer */
#define T_FLOAT 6 /* floating point */
#define T_DOUBLE 7 /* double word */
#define T_STRUCT 8 /* structure */
#define T_UNION 9 /* union */
#define T_ENUM 10 /* enumeration */
#define T_MOE 11 /* member of enumeration */
#define T_UCHAR 12 /* unsigned character */
#define T_USHORT 13 /* unsigned short */
#define T_UINT 14 /* unsigned integer */
#define T_ULONG 15 /* unsigned long */
 
/*------------------------------------------------------------------------*/
/* derived types are: */
/*------------------------------------------------------------------------*/
#define DT_NON 0 /* no derived type */
#define DT_PTR 1 /* pointer */
#define DT_FCN 2 /* function */
#define DT_ARY 3 /* array */
 
#define MKTYPE(basic, d1,d2,d3,d4,d5,d6) \
((basic) | ((d1) << 4) | ((d2) << 6) | ((d3) << 8) |\
((d4) << 10) | ((d5) << 12) | ((d6) << 14))
 
/*------------------------------------------------------------------------*/
/* type packing constants and macros */
/*------------------------------------------------------------------------*/
#define N_BTMASK_COFF 017
#define N_TMASK_COFF 060
#define N_TMASK1_COFF 0300
#define N_TMASK2_COFF 0360
#define N_BTSHFT_COFF 4
#define N_TSHIFT_COFF 2
 
#define BTYPE_COFF(x) ((x) & N_BTMASK_COFF)
#define ISINT(x) (((x) >= T_CHAR && (x) <= T_LONG) || \
((x) >= T_UCHAR && (x) <= T_ULONG) || (x) == T_ENUM)
#define ISFLT_COFF(x) ((x) == T_DOUBLE || (x) == T_FLOAT)
#define ISPTR_COFF(x) (((x) & N_TMASK_COFF) == (DT_PTR << N_BTSHFT_COFF))
#define ISFCN_COFF(x) (((x) & N_TMASK_COFF) == (DT_FCN << N_BTSHFT_COFF))
#define ISARY_COFF(x) (((x) & N_TMASK_COFF) == (DT_ARY << N_BTSHFT_COFF))
#define ISTAG_COFF(x) ((x)==C_STRTAG || (x)==C_UNTAG || (x)==C_ENTAG)
 
#define INCREF_COFF(x) ((((x)&~N_BTMASK_COFF)<<N_TSHIFT_COFF)|(DT_PTR<<N_BTSHFT_COFF)|(x&N_BTMASK_COFF))
#define DECREF_COFF(x) ((((x)>>N_TSHIFT_COFF)&~N_BTMASK_COFF)|((x)&N_BTMASK_COFF))
 
/*------------------------------------------------------------------------*/
/* AUXILIARY SYMBOL ENTRY */
/*------------------------------------------------------------------------*/
union auxent
{
struct
{
long x_tagndx; /* str, un, or enum tag indx */
union
{
struct
{
unsigned short x_lnno; /* declaration line number */
unsigned short x_size; /* str, union, array size */
} x_lnsz;
long x_fsize; /* size of function */
} x_misc;
union
{
struct /* if ISFCN, tag, or .bb */
{
long x_lnnoptr; /* ptr to fcn line # */
long x_endndx; /* entry ndx past block end */
} x_fcn;
struct /* if ISARY, up to 4 dimen. */
{
unsigned short x_dimen[DIMNUM];
} x_ary;
} x_fcnary;
unsigned short x_regcount; /* number of registers used by func */
} x_sym;
struct
{
char x_fname[FILNMLEN];
} x_file;
struct
{
long x_scnlen; /* section length */
unsigned short x_nreloc; /* number of relocation entries */
unsigned short x_nlinno; /* number of line numbers */
} x_scn;
};
 
#define SYMENT struct syment
#define SYMESZ 18 /* sizeof(SYMENT) */
 
#define AUXENT union auxent
#define AUXESZ 18 /* sizeof(AUXENT) */
 
/*------------------------------------------------------------------------*/
/* NAMES OF "SPECIAL" SYMBOLS */
/*------------------------------------------------------------------------*/
#define _STEXT ".text"
#define _ETEXT "etext"
#define _SDATA ".data"
#define _EDATA "edata"
#define _SBSS ".bss"
#define _END "end"
#define _CINITPTR "cinit"
 
/*--------------------------------------------------------------------------*/
/* ENTRY POINT SYMBOLS */
/*--------------------------------------------------------------------------*/
#define _START "_start"
#define _MAIN "_main"
/* _CSTART "_c_int00" (defined in params.h) */
 
 
#define _TVORIG "_tvorig"
#define _TORIGIN "_torigin"
#define _DORIGIN "_dorigin"
 
#define _SORIGIN "_sorigin"
/programs/develop/metcc/trunk/source/config.h
0,0 → 1,7
/* Automatically generated by configure - do not modify */
#define CONFIG_TCCDIR "/usr/local/lib/tcc"
#define GCC_MAJOR 3
#define HOST_I386 1
#define TCC_VERSION "0.9.23"
//#define TCC_TARGET_PE
#define TCC_TARGET_MEOS
/programs/develop/metcc/trunk/source/elf.h
0,0 → 1,1627
/* This file defines standard ELF types, structures, and macros.
Copyright (C) 1995, 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by Ian Lance Taylor <ian@cygnus.com>.
 
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Library General Public License as
published by the Free Software Foundation; either version 2 of the
License, or (at your option) any later version.
 
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Library General Public License for more details.
 
You should have received a copy of the GNU Library General Public
License along with the GNU C Library; see the file COPYING.LIB. If not,
write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
 
#ifndef _ELF_H
#define _ELF_H 1
 
#ifndef WIN32
#include <inttypes.h>
#else
#ifndef __int8_t_defined
#define __int8_t_defined
typedef signed char int8_t;
typedef short int int16_t;
typedef int int32_t;
typedef long long int int64_t;
#endif
 
typedef unsigned char uint8_t;
typedef unsigned short int uint16_t;
typedef unsigned int uint32_t;
typedef unsigned long long int uint64_t;
#endif
 
/* Standard ELF types. */
 
/* Type for a 16-bit quantity. */
typedef uint16_t Elf32_Half;
typedef uint16_t Elf64_Half;
 
/* Types for signed and unsigned 32-bit quantities. */
typedef uint32_t Elf32_Word;
typedef int32_t Elf32_Sword;
typedef uint32_t Elf64_Word;
typedef int32_t Elf64_Sword;
 
/* Types for signed and unsigned 64-bit quantities. */
typedef uint64_t Elf32_Xword;
typedef int64_t Elf32_Sxword;
typedef uint64_t Elf64_Xword;
typedef int64_t Elf64_Sxword;
 
/* Type of addresses. */
typedef uint32_t Elf32_Addr;
typedef uint64_t Elf64_Addr;
 
/* Type of file offsets. */
typedef uint32_t Elf32_Off;
typedef uint64_t Elf64_Off;
 
/* Type for section indices, which are 16-bit quantities. */
typedef uint16_t Elf32_Section;
typedef uint16_t Elf64_Section;
 
/* Type of symbol indices. */
typedef uint32_t Elf32_Symndx;
typedef uint64_t Elf64_Symndx;
 
 
/* The ELF file header. This appears at the start of every ELF file. */
 
#define EI_NIDENT (16)
 
typedef struct
{
unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */
Elf32_Half e_type; /* Object file type */
Elf32_Half e_machine; /* Architecture */
Elf32_Word e_version; /* Object file version */
Elf32_Addr e_entry; /* Entry point virtual address */
Elf32_Off e_phoff; /* Program header table file offset */
Elf32_Off e_shoff; /* Section header table file offset */
Elf32_Word e_flags; /* Processor-specific flags */
Elf32_Half e_ehsize; /* ELF header size in bytes */
Elf32_Half e_phentsize; /* Program header table entry size */
Elf32_Half e_phnum; /* Program header table entry count */
Elf32_Half e_shentsize; /* Section header table entry size */
Elf32_Half e_shnum; /* Section header table entry count */
Elf32_Half e_shstrndx; /* Section header string table index */
} Elf32_Ehdr;
 
typedef struct
{
unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */
Elf64_Half e_type; /* Object file type */
Elf64_Half e_machine; /* Architecture */
Elf64_Word e_version; /* Object file version */
Elf64_Addr e_entry; /* Entry point virtual address */
Elf64_Off e_phoff; /* Program header table file offset */
Elf64_Off e_shoff; /* Section header table file offset */
Elf64_Word e_flags; /* Processor-specific flags */
Elf64_Half e_ehsize; /* ELF header size in bytes */
Elf64_Half e_phentsize; /* Program header table entry size */
Elf64_Half e_phnum; /* Program header table entry count */
Elf64_Half e_shentsize; /* Section header table entry size */
Elf64_Half e_shnum; /* Section header table entry count */
Elf64_Half e_shstrndx; /* Section header string table index */
} Elf64_Ehdr;
 
/* Fields in the e_ident array. The EI_* macros are indices into the
array. The macros under each EI_* macro are the values the byte
may have. */
 
#define EI_MAG0 0 /* File identification byte 0 index */
#define ELFMAG0 0x7f /* Magic number byte 0 */
 
#define EI_MAG1 1 /* File identification byte 1 index */
#define ELFMAG1 'E' /* Magic number byte 1 */
 
#define EI_MAG2 2 /* File identification byte 2 index */
#define ELFMAG2 'L' /* Magic number byte 2 */
 
#define EI_MAG3 3 /* File identification byte 3 index */
#define ELFMAG3 'F' /* Magic number byte 3 */
 
/* Conglomeration of the identification bytes, for easy testing as a word. */
#define ELFMAG "\177ELF"
#define SELFMAG 4
 
#define EI_CLASS 4 /* File class byte index */
#define ELFCLASSNONE 0 /* Invalid class */
#define ELFCLASS32 1 /* 32-bit objects */
#define ELFCLASS64 2 /* 64-bit objects */
#define ELFCLASSNUM 3
 
#define EI_DATA 5 /* Data encoding byte index */
#define ELFDATANONE 0 /* Invalid data encoding */
#define ELFDATA2LSB 1 /* 2's complement, little endian */
#define ELFDATA2MSB 2 /* 2's complement, big endian */
#define ELFDATANUM 3
 
#define EI_VERSION 6 /* File version byte index */
/* Value must be EV_CURRENT */
 
#define EI_OSABI 7 /* OS ABI identification */
#define ELFOSABI_SYSV 0 /* UNIX System V ABI */
#define ELFOSABI_HPUX 1 /* HP-UX */
#define ELFOSABI_FREEBSD 9 /* Free BSD */
#define ELFOSABI_ARM 97 /* ARM */
#define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */
 
#define EI_ABIVERSION 8 /* ABI version */
 
#define EI_PAD 9 /* Byte index of padding bytes */
 
/* Legal values for e_type (object file type). */
 
#define ET_NONE 0 /* No file type */
#define ET_REL 1 /* Relocatable file */
#define ET_EXEC 2 /* Executable file */
#define ET_DYN 3 /* Shared object file */
#define ET_CORE 4 /* Core file */
#define ET_NUM 5 /* Number of defined types */
#define ET_LOPROC 0xff00 /* Processor-specific */
#define ET_HIPROC 0xffff /* Processor-specific */
 
/* Legal values for e_machine (architecture). */
 
#define EM_NONE 0 /* No machine */
#define EM_M32 1 /* AT&T WE 32100 */
#define EM_SPARC 2 /* SUN SPARC */
#define EM_386 3 /* Intel 80386 */
#define EM_68K 4 /* Motorola m68k family */
#define EM_88K 5 /* Motorola m88k family */
#define EM_486 6 /* Intel 80486 */
#define EM_860 7 /* Intel 80860 */
#define EM_MIPS 8 /* MIPS R3000 big-endian */
#define EM_S370 9 /* Amdahl */
#define EM_MIPS_RS4_BE 10 /* MIPS R4000 big-endian */
#define EM_RS6000 11 /* RS6000 */
 
#define EM_PARISC 15 /* HPPA */
#define EM_nCUBE 16 /* nCUBE */
#define EM_VPP500 17 /* Fujitsu VPP500 */
#define EM_SPARC32PLUS 18 /* Sun's "v8plus" */
#define EM_960 19 /* Intel 80960 */
#define EM_PPC 20 /* PowerPC */
 
#define EM_V800 36 /* NEC V800 series */
#define EM_FR20 37 /* Fujitsu FR20 */
#define EM_RH32 38 /* TRW RH32 */
#define EM_MMA 39 /* Fujitsu MMA */
#define EM_ARM 40 /* ARM */
#define EM_FAKE_ALPHA 41 /* Digital Alpha */
#define EM_SH 42 /* Hitachi SH */
#define EM_SPARCV9 43 /* SPARC v9 64-bit */
#define EM_TRICORE 44 /* Siemens Tricore */
#define EM_ARC 45 /* Argonaut RISC Core */
#define EM_H8_300 46 /* Hitachi H8/300 */
#define EM_H8_300H 47 /* Hitachi H8/300H */
#define EM_H8S 48 /* Hitachi H8S */
#define EM_H8_500 49 /* Hitachi H8/500 */
#define EM_IA_64 50 /* Intel Merced */
#define EM_MIPS_X 51 /* Stanford MIPS-X */
#define EM_COLDFIRE 52 /* Motorola Coldfire */
#define EM_68HC12 53 /* Motorola M68HC12 */
#define EM_NUM 54
 
/* If it is necessary to assign new unofficial EM_* values, please
pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the
chances of collision with official or non-GNU unofficial values. */
 
#define EM_ALPHA 0x9026
#define EM_C60 0x9c60
 
/* Legal values for e_version (version). */
 
#define EV_NONE 0 /* Invalid ELF version */
#define EV_CURRENT 1 /* Current version */
#define EV_NUM 2
 
/* Section header. */
 
typedef struct
{
Elf32_Word sh_name; /* Section name (string tbl index) */
Elf32_Word sh_type; /* Section type */
Elf32_Word sh_flags; /* Section flags */
Elf32_Addr sh_addr; /* Section virtual addr at execution */
Elf32_Off sh_offset; /* Section file offset */
Elf32_Word sh_size; /* Section size in bytes */
Elf32_Word sh_link; /* Link to another section */
Elf32_Word sh_info; /* Additional section information */
Elf32_Word sh_addralign; /* Section alignment */
Elf32_Word sh_entsize; /* Entry size if section holds table */
} Elf32_Shdr;
 
typedef struct
{
Elf64_Word sh_name; /* Section name (string tbl index) */
Elf64_Word sh_type; /* Section type */
Elf64_Xword sh_flags; /* Section flags */
Elf64_Addr sh_addr; /* Section virtual addr at execution */
Elf64_Off sh_offset; /* Section file offset */
Elf64_Xword sh_size; /* Section size in bytes */
Elf64_Word sh_link; /* Link to another section */
Elf64_Word sh_info; /* Additional section information */
Elf64_Xword sh_addralign; /* Section alignment */
Elf64_Xword sh_entsize; /* Entry size if section holds table */
} Elf64_Shdr;
 
/* Special section indices. */
 
#define SHN_UNDEF 0 /* Undefined section */
#define SHN_LORESERVE 0xff00 /* Start of reserved indices */
#define SHN_LOPROC 0xff00 /* Start of processor-specific */
#define SHN_HIPROC 0xff1f /* End of processor-specific */
#define SHN_ABS 0xfff1 /* Associated symbol is absolute */
#define SHN_COMMON 0xfff2 /* Associated symbol is common */
#define SHN_HIRESERVE 0xffff /* End of reserved indices */
 
/* Legal values for sh_type (section type). */
 
#define SHT_NULL 0 /* Section header table entry unused */
#define SHT_PROGBITS 1 /* Program data */
#define SHT_SYMTAB 2 /* Symbol table */
#define SHT_STRTAB 3 /* String table */
#define SHT_RELA 4 /* Relocation entries with addends */
#define SHT_HASH 5 /* Symbol hash table */
#define SHT_DYNAMIC 6 /* Dynamic linking information */
#define SHT_NOTE 7 /* Notes */
#define SHT_NOBITS 8 /* Program space with no data (bss) */
#define SHT_REL 9 /* Relocation entries, no addends */
#define SHT_SHLIB 10 /* Reserved */
#define SHT_DYNSYM 11 /* Dynamic linker symbol table */
#define SHT_NUM 12 /* Number of defined types. */
#define SHT_LOOS 0x60000000 /* Start OS-specific */
#define SHT_LOSUNW 0x6ffffffb /* Sun-specific low bound. */
#define SHT_SUNW_COMDAT 0x6ffffffb
#define SHT_SUNW_syminfo 0x6ffffffc
#define SHT_GNU_verdef 0x6ffffffd /* Version definition section. */
#define SHT_GNU_verneed 0x6ffffffe /* Version needs section. */
#define SHT_GNU_versym 0x6fffffff /* Version symbol table. */
#define SHT_HISUNW 0x6fffffff /* Sun-specific high bound. */
#define SHT_HIOS 0x6fffffff /* End OS-specific type */
#define SHT_LOPROC 0x70000000 /* Start of processor-specific */
#define SHT_HIPROC 0x7fffffff /* End of processor-specific */
#define SHT_LOUSER 0x80000000 /* Start of application-specific */
#define SHT_HIUSER 0x8fffffff /* End of application-specific */
 
/* Legal values for sh_flags (section flags). */
 
#define SHF_WRITE (1 << 0) /* Writable */
#define SHF_ALLOC (1 << 1) /* Occupies memory during execution */
#define SHF_EXECINSTR (1 << 2) /* Executable */
#define SHF_MASKPROC 0xf0000000 /* Processor-specific */
 
/* Symbol table entry. */
 
typedef struct
{
Elf32_Word st_name; /* Symbol name (string tbl index) */
Elf32_Addr st_value; /* Symbol value */
Elf32_Word st_size; /* Symbol size */
unsigned char st_info; /* Symbol type and binding */
unsigned char st_other; /* No defined meaning, 0 */
Elf32_Section st_shndx; /* Section index */
} Elf32_Sym;
 
typedef struct
{
Elf64_Word st_name; /* Symbol name (string tbl index) */
unsigned char st_info; /* Symbol type and binding */
unsigned char st_other; /* No defined meaning, 0 */
Elf64_Section st_shndx; /* Section index */
Elf64_Addr st_value; /* Symbol value */
Elf64_Xword st_size; /* Symbol size */
} Elf64_Sym;
 
/* The syminfo section if available contains additional information about
every dynamic symbol. */
 
typedef struct
{
Elf32_Half si_boundto; /* Direct bindings, symbol bound to */
Elf32_Half si_flags; /* Per symbol flags */
} Elf32_Syminfo;
 
typedef struct
{
Elf64_Half si_boundto; /* Direct bindings, symbol bound to */
Elf64_Half si_flags; /* Per symbol flags */
} Elf64_Syminfo;
 
/* Possible values for si_boundto. */
#define SYMINFO_BT_SELF 0xffff /* Symbol bound to self */
#define SYMINFO_BT_PARENT 0xfffe /* Symbol bound to parent */
#define SYMINFO_BT_LOWRESERVE 0xff00 /* Beginning of reserved entries */
 
/* Possible bitmasks for si_flags. */
#define SYMINFO_FLG_DIRECT 0x0001 /* Direct bound symbol */
#define SYMINFO_FLG_PASSTHRU 0x0002 /* Pass-thru symbol for translator */
#define SYMINFO_FLG_COPY 0x0004 /* Symbol is a copy-reloc */
#define SYMINFO_FLG_LAZYLOAD 0x0008 /* Symbol bound to object to be lazy
loaded */
/* Syminfo version values. */
#define SYMINFO_NONE 0
#define SYMINFO_CURRENT 1
#define SYMINFO_NUM 2
 
 
/* Special section index. */
 
#define SHN_UNDEF 0 /* No section, undefined symbol. */
 
/* How to extract and insert information held in the st_info field. */
 
#define ELF32_ST_BIND(val) (((unsigned char) (val)) >> 4)
#define ELF32_ST_TYPE(val) ((val) & 0xf)
#define ELF32_ST_INFO(bind, type) (((bind) << 4) + ((type) & 0xf))
 
/* Both Elf32_Sym and Elf64_Sym use the same one-byte st_info field. */
#define ELF64_ST_BIND(val) ELF32_ST_BIND (val)
#define ELF64_ST_TYPE(val) ELF32_ST_TYPE (val)
#define ELF64_ST_INFO(bind, type) ELF32_ST_INFO ((bind), (type))
 
/* Legal values for ST_BIND subfield of st_info (symbol binding). */
 
#define STB_LOCAL 0 /* Local symbol */
#define STB_GLOBAL 1 /* Global symbol */
#define STB_WEAK 2 /* Weak symbol */
#define STB_NUM 3 /* Number of defined types. */
#define STB_LOOS 10 /* Start of OS-specific */
#define STB_HIOS 12 /* End of OS-specific */
#define STB_LOPROC 13 /* Start of processor-specific */
#define STB_HIPROC 15 /* End of processor-specific */
 
/* Legal values for ST_TYPE subfield of st_info (symbol type). */
 
#define STT_NOTYPE 0 /* Symbol type is unspecified */
#define STT_OBJECT 1 /* Symbol is a data object */
#define STT_FUNC 2 /* Symbol is a code object */
#define STT_SECTION 3 /* Symbol associated with a section */
#define STT_FILE 4 /* Symbol's name is file name */
#define STT_NUM 5 /* Number of defined types. */
#define STT_LOOS 11 /* Start of OS-specific */
#define STT_HIOS 12 /* End of OS-specific */
#define STT_LOPROC 13 /* Start of processor-specific */
#define STT_HIPROC 15 /* End of processor-specific */
 
 
/* Symbol table indices are found in the hash buckets and chain table
of a symbol hash table section. This special index value indicates
the end of a chain, meaning no further symbols are found in that bucket. */
 
#define STN_UNDEF 0 /* End of a chain. */
 
 
/* How to extract and insert information held in the st_other field. */
 
#define ELF32_ST_VISIBILITY(o) ((o) & 0x03)
 
/* For ELF64 the definitions are the same. */
#define ELF64_ST_VISIBILITY(o) ELF32_ST_VISIBILITY (o)
 
/* Symbol visibility specification encoded in the st_other field. */
#define STV_DEFAULT 0 /* Default symbol visibility rules */
#define STV_INTERNAL 1 /* Processor specific hidden class */
#define STV_HIDDEN 2 /* Sym unavailable in other modules */
#define STV_PROTECTED 3 /* Not preemptible, not exported */
 
 
/* Relocation table entry without addend (in section of type SHT_REL). */
 
typedef struct
{
Elf32_Addr r_offset; /* Address */
Elf32_Word r_info; /* Relocation type and symbol index */
} Elf32_Rel;
 
/* I have seen two different definitions of the Elf64_Rel and
Elf64_Rela structures, so we'll leave them out until Novell (or
whoever) gets their act together. */
/* The following, at least, is used on Sparc v9, MIPS, and Alpha. */
 
typedef struct
{
Elf64_Addr r_offset; /* Address */
Elf64_Xword r_info; /* Relocation type and symbol index */
} Elf64_Rel;
 
/* Relocation table entry with addend (in section of type SHT_RELA). */
 
typedef struct
{
Elf32_Addr r_offset; /* Address */
Elf32_Word r_info; /* Relocation type and symbol index */
Elf32_Sword r_addend; /* Addend */
} Elf32_Rela;
 
typedef struct
{
Elf64_Addr r_offset; /* Address */
Elf64_Xword r_info; /* Relocation type and symbol index */
Elf64_Sxword r_addend; /* Addend */
} Elf64_Rela;
 
/* How to extract and insert information held in the r_info field. */
 
#define ELF32_R_SYM(val) ((val) >> 8)
#define ELF32_R_TYPE(val) ((val) & 0xff)
#define ELF32_R_INFO(sym, type) (((sym) << 8) + ((type) & 0xff))
 
#define ELF64_R_SYM(i) ((i) >> 32)
#define ELF64_R_TYPE(i) ((i) & 0xffffffff)
#define ELF64_R_INFO(sym,type) (((sym) << 32) + (type))
 
/* Program segment header. */
 
typedef struct
{
Elf32_Word p_type; /* Segment type */
Elf32_Off p_offset; /* Segment file offset */
Elf32_Addr p_vaddr; /* Segment virtual address */
Elf32_Addr p_paddr; /* Segment physical address */
Elf32_Word p_filesz; /* Segment size in file */
Elf32_Word p_memsz; /* Segment size in memory */
Elf32_Word p_flags; /* Segment flags */
Elf32_Word p_align; /* Segment alignment */
} Elf32_Phdr;
 
typedef struct
{
Elf64_Word p_type; /* Segment type */
Elf64_Word p_flags; /* Segment flags */
Elf64_Off p_offset; /* Segment file offset */
Elf64_Addr p_vaddr; /* Segment virtual address */
Elf64_Addr p_paddr; /* Segment physical address */
Elf64_Xword p_filesz; /* Segment size in file */
Elf64_Xword p_memsz; /* Segment size in memory */
Elf64_Xword p_align; /* Segment alignment */
} Elf64_Phdr;
 
/* Legal values for p_type (segment type). */
 
#define PT_NULL 0 /* Program header table entry unused */
#define PT_LOAD 1 /* Loadable program segment */
#define PT_DYNAMIC 2 /* Dynamic linking information */
#define PT_INTERP 3 /* Program interpreter */
#define PT_NOTE 4 /* Auxiliary information */
#define PT_SHLIB 5 /* Reserved */
#define PT_PHDR 6 /* Entry for header table itself */
#define PT_NUM 7 /* Number of defined types. */
#define PT_LOOS 0x60000000 /* Start of OS-specific */
#define PT_HIOS 0x6fffffff /* End of OS-specific */
#define PT_LOPROC 0x70000000 /* Start of processor-specific */
#define PT_HIPROC 0x7fffffff /* End of processor-specific */
 
/* Legal values for p_flags (segment flags). */
 
#define PF_X (1 << 0) /* Segment is executable */
#define PF_W (1 << 1) /* Segment is writable */
#define PF_R (1 << 2) /* Segment is readable */
#define PF_MASKPROC 0xf0000000 /* Processor-specific */
 
/* Legal values for note segment descriptor types for core files. */
 
#define NT_PRSTATUS 1 /* Contains copy of prstatus struct */
#define NT_FPREGSET 2 /* Contains copy of fpregset struct */
#define NT_PRPSINFO 3 /* Contains copy of prpsinfo struct */
#define NT_PRXREG 4 /* Contains copy of prxregset struct */
#define NT_PLATFORM 5 /* String from sysinfo(SI_PLATFORM) */
#define NT_AUXV 6 /* Contains copy of auxv array */
#define NT_GWINDOWS 7 /* Contains copy of gwindows struct */
#define NT_PSTATUS 10 /* Contains copy of pstatus struct */
#define NT_PSINFO 13 /* Contains copy of psinfo struct */
#define NT_PRCRED 14 /* Contains copy of prcred struct */
#define NT_UTSNAME 15 /* Contains copy of utsname struct */
#define NT_LWPSTATUS 16 /* Contains copy of lwpstatus struct */
#define NT_LWPSINFO 17 /* Contains copy of lwpinfo struct */
 
/* Legal values for the note segment descriptor types for object files. */
 
#define NT_VERSION 1 /* Contains a version string. */
 
 
/* Dynamic section entry. */
 
typedef struct
{
Elf32_Sword d_tag; /* Dynamic entry type */
union
{
Elf32_Word d_val; /* Integer value */
Elf32_Addr d_ptr; /* Address value */
} d_un;
} Elf32_Dyn;
 
typedef struct
{
Elf64_Sxword d_tag; /* Dynamic entry type */
union
{
Elf64_Xword d_val; /* Integer value */
Elf64_Addr d_ptr; /* Address value */
} d_un;
} Elf64_Dyn;
 
/* Legal values for d_tag (dynamic entry type). */
 
#define DT_NULL 0 /* Marks end of dynamic section */
#define DT_NEEDED 1 /* Name of needed library */
#define DT_PLTRELSZ 2 /* Size in bytes of PLT relocs */
#define DT_PLTGOT 3 /* Processor defined value */
#define DT_HASH 4 /* Address of symbol hash table */
#define DT_STRTAB 5 /* Address of string table */
#define DT_SYMTAB 6 /* Address of symbol table */
#define DT_RELA 7 /* Address of Rela relocs */
#define DT_RELASZ 8 /* Total size of Rela relocs */
#define DT_RELAENT 9 /* Size of one Rela reloc */
#define DT_STRSZ 10 /* Size of string table */
#define DT_SYMENT 11 /* Size of one symbol table entry */
#define DT_INIT 12 /* Address of init function */
#define DT_FINI 13 /* Address of termination function */
#define DT_SONAME 14 /* Name of shared object */
#define DT_RPATH 15 /* Library search path */
#define DT_SYMBOLIC 16 /* Start symbol search here */
#define DT_REL 17 /* Address of Rel relocs */
#define DT_RELSZ 18 /* Total size of Rel relocs */
#define DT_RELENT 19 /* Size of one Rel reloc */
#define DT_PLTREL 20 /* Type of reloc in PLT */
#define DT_DEBUG 21 /* For debugging; unspecified */
#define DT_TEXTREL 22 /* Reloc might modify .text */
#define DT_JMPREL 23 /* Address of PLT relocs */
#define DT_BIND_NOW 24 /* Process relocations of object */
#define DT_INIT_ARRAY 25 /* Array with addresses of init fct */
#define DT_FINI_ARRAY 26 /* Array with addresses of fini fct */
#define DT_INIT_ARRAYSZ 27 /* Size in bytes of DT_INIT_ARRAY */
#define DT_FINI_ARRAYSZ 28 /* Size in bytes of DT_FINI_ARRAY */
#define DT_NUM 29 /* Number used */
#define DT_LOOS 0x60000000 /* Start of OS-specific */
#define DT_HIOS 0x6fffffff /* End of OS-specific */
#define DT_LOPROC 0x70000000 /* Start of processor-specific */
#define DT_HIPROC 0x7fffffff /* End of processor-specific */
#define DT_PROCNUM DT_MIPS_NUM /* Most used by any processor */
 
/* DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the
Dyn.d_un.d_val field of the Elf*_Dyn structure. This follows Sun's
approach. */
#define DT_VALRNGLO 0x6ffffd00
#define DT_POSFLAG_1 0x6ffffdfd /* Flags for DT_* entries, effecting
the following DT_* entry. */
#define DT_SYMINSZ 0x6ffffdfe /* Size of syminfo table (in bytes) */
#define DT_SYMINENT 0x6ffffdff /* Entry size of syminfo */
#define DT_VALRNGHI 0x6ffffdff
 
/* DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the
Dyn.d_un.d_ptr field of the Elf*_Dyn structure.
 
If any adjustment is made to the ELF object after it has been
built these entries will need to be adjusted. */
#define DT_ADDRRNGLO 0x6ffffe00
#define DT_SYMINFO 0x6ffffeff /* syminfo table */
#define DT_ADDRRNGHI 0x6ffffeff
 
/* The versioning entry types. The next are defined as part of the
GNU extension. */
#define DT_VERSYM 0x6ffffff0
 
/* These were chosen by Sun. */
#define DT_FLAGS_1 0x6ffffffb /* State flags, see DF_1_* below. */
#define DT_VERDEF 0x6ffffffc /* Address of version definition
table */
#define DT_VERDEFNUM 0x6ffffffd /* Number of version definitions */
#define DT_VERNEED 0x6ffffffe /* Address of table with needed
versions */
#define DT_VERNEEDNUM 0x6fffffff /* Number of needed versions */
#define DT_VERSIONTAGIDX(tag) (DT_VERNEEDNUM - (tag)) /* Reverse order! */
#define DT_VERSIONTAGNUM 16
 
/* Sun added these machine-independent extensions in the "processor-specific"
range. Be compatible. */
#define DT_AUXILIARY 0x7ffffffd /* Shared object to load before self */
#define DT_FILTER 0x7fffffff /* Shared object to get values from */
#define DT_EXTRATAGIDX(tag) ((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1)
#define DT_EXTRANUM 3
 
/* State flags selectable in the `d_un.d_val' element of the DT_FLAGS_1
entry in the dynamic section. */
#define DF_1_NOW 0x00000001 /* Set RTLD_NOW for this object. */
#define DF_1_GLOBAL 0x00000002 /* Set RTLD_GLOBAL for this object. */
#define DF_1_GROUP 0x00000004 /* Set RTLD_GROUP for this object. */
#define DF_1_NODELETE 0x00000008 /* Set RTLD_NODELETE for this object.*/
#define DF_1_LOADFLTR 0x00000010 /* Trigger filtee loading at runtime.*/
#define DF_1_INITFIRST 0x00000020 /* Set RTLD_INITFIRST for this object*/
#define DF_1_NOOPEN 0x00000040 /* Set RTLD_NOOPEN for this object. */
 
/* Version definition sections. */
 
typedef struct
{
Elf32_Half vd_version; /* Version revision */
Elf32_Half vd_flags; /* Version information */
Elf32_Half vd_ndx; /* Version Index */
Elf32_Half vd_cnt; /* Number of associated aux entries */
Elf32_Word vd_hash; /* Version name hash value */
Elf32_Word vd_aux; /* Offset in bytes to verdaux array */
Elf32_Word vd_next; /* Offset in bytes to next verdef
entry */
} Elf32_Verdef;
 
typedef struct
{
Elf64_Half vd_version; /* Version revision */
Elf64_Half vd_flags; /* Version information */
Elf64_Half vd_ndx; /* Version Index */
Elf64_Half vd_cnt; /* Number of associated aux entries */
Elf64_Word vd_hash; /* Version name hash value */
Elf64_Word vd_aux; /* Offset in bytes to verdaux array */
Elf64_Word vd_next; /* Offset in bytes to next verdef
entry */
} Elf64_Verdef;
 
 
/* Legal values for vd_version (version revision). */
#define VER_DEF_NONE 0 /* No version */
#define VER_DEF_CURRENT 1 /* Current version */
#define VER_DEF_NUM 2 /* Given version number */
 
/* Legal values for vd_flags (version information flags). */
#define VER_FLG_BASE 0x1 /* Version definition of file itself */
#define VER_FLG_WEAK 0x2 /* Weak version identifier */
 
/* Auxialiary version information. */
 
typedef struct
{
Elf32_Word vda_name; /* Version or dependency names */
Elf32_Word vda_next; /* Offset in bytes to next verdaux
entry */
} Elf32_Verdaux;
 
typedef struct
{
Elf64_Word vda_name; /* Version or dependency names */
Elf64_Word vda_next; /* Offset in bytes to next verdaux
entry */
} Elf64_Verdaux;
 
 
/* Version dependency section. */
 
typedef struct
{
Elf32_Half vn_version; /* Version of structure */
Elf32_Half vn_cnt; /* Number of associated aux entries */
Elf32_Word vn_file; /* Offset of filename for this
dependency */
Elf32_Word vn_aux; /* Offset in bytes to vernaux array */
Elf32_Word vn_next; /* Offset in bytes to next verneed
entry */
} Elf32_Verneed;
 
typedef struct
{
Elf64_Half vn_version; /* Version of structure */
Elf64_Half vn_cnt; /* Number of associated aux entries */
Elf64_Word vn_file; /* Offset of filename for this
dependency */
Elf64_Word vn_aux; /* Offset in bytes to vernaux array */
Elf64_Word vn_next; /* Offset in bytes to next verneed
entry */
} Elf64_Verneed;
 
 
/* Legal values for vn_version (version revision). */
#define VER_NEED_NONE 0 /* No version */
#define VER_NEED_CURRENT 1 /* Current version */
#define VER_NEED_NUM 2 /* Given version number */
 
/* Auxiliary needed version information. */
 
typedef struct
{
Elf32_Word vna_hash; /* Hash value of dependency name */
Elf32_Half vna_flags; /* Dependency specific information */
Elf32_Half vna_other; /* Unused */
Elf32_Word vna_name; /* Dependency name string offset */
Elf32_Word vna_next; /* Offset in bytes to next vernaux
entry */
} Elf32_Vernaux;
 
typedef struct
{
Elf64_Word vna_hash; /* Hash value of dependency name */
Elf64_Half vna_flags; /* Dependency specific information */
Elf64_Half vna_other; /* Unused */
Elf64_Word vna_name; /* Dependency name string offset */
Elf64_Word vna_next; /* Offset in bytes to next vernaux
entry */
} Elf64_Vernaux;
 
 
/* Legal values for vna_flags. */
#define VER_FLG_WEAK 0x2 /* Weak version identifier */
 
 
/* Auxiliary vector. */
 
/* This vector is normally only used by the program interpreter. The
usual definition in an ABI supplement uses the name auxv_t. The
vector is not usually defined in a standard <elf.h> file, but it
can't hurt. We rename it to avoid conflicts. The sizes of these
types are an arrangement between the exec server and the program
interpreter, so we don't fully specify them here. */
 
typedef struct
{
int a_type; /* Entry type */
union
{
long int a_val; /* Integer value */
void *a_ptr; /* Pointer value */
void (*a_fcn) (void); /* Function pointer value */
} a_un;
} Elf32_auxv_t;
 
typedef struct
{
long int a_type; /* Entry type */
union
{
long int a_val; /* Integer value */
void *a_ptr; /* Pointer value */
void (*a_fcn) (void); /* Function pointer value */
} a_un;
} Elf64_auxv_t;
 
/* Legal values for a_type (entry type). */
 
#define AT_NULL 0 /* End of vector */
#define AT_IGNORE 1 /* Entry should be ignored */
#define AT_EXECFD 2 /* File descriptor of program */
#define AT_PHDR 3 /* Program headers for program */
#define AT_PHENT 4 /* Size of program header entry */
#define AT_PHNUM 5 /* Number of program headers */
#define AT_PAGESZ 6 /* System page size */
#define AT_BASE 7 /* Base address of interpreter */
#define AT_FLAGS 8 /* Flags */
#define AT_ENTRY 9 /* Entry point of program */
#define AT_NOTELF 10 /* Program is not ELF */
#define AT_UID 11 /* Real uid */
#define AT_EUID 12 /* Effective uid */
#define AT_GID 13 /* Real gid */
#define AT_EGID 14 /* Effective gid */
 
/* Some more special a_type values describing the hardware. */
#define AT_PLATFORM 15 /* String identifying platform. */
#define AT_HWCAP 16 /* Machine dependent hints about
processor capabilities. */
 
/* This entry gives some information about the FPU initialization
performed by the kernel. */
#define AT_FPUCW 17 /* Used FPU control word. */
 
 
/* Note section contents. Each entry in the note section begins with
a header of a fixed form. */
 
typedef struct
{
Elf32_Word n_namesz; /* Length of the note's name. */
Elf32_Word n_descsz; /* Length of the note's descriptor. */
Elf32_Word n_type; /* Type of the note. */
} Elf32_Nhdr;
 
typedef struct
{
Elf64_Word n_namesz; /* Length of the note's name. */
Elf64_Word n_descsz; /* Length of the note's descriptor. */
Elf64_Word n_type; /* Type of the note. */
} Elf64_Nhdr;
 
/* Known names of notes. */
 
/* Solaris entries in the note section have this name. */
#define ELF_NOTE_SOLARIS "SUNW Solaris"
 
/* Note entries for GNU systems have this name. */
#define ELF_NOTE_GNU "GNU"
 
 
/* Defined types of notes for Solaris. */
 
/* Value of descriptor (one word) is desired pagesize for the binary. */
#define ELF_NOTE_PAGESIZE_HINT 1
 
 
/* Defined note types for GNU systems. */
 
/* ABI information. The descriptor consists of words:
word 0: OS descriptor
word 1: major version of the ABI
word 2: minor version of the ABI
word 3: subminor version of the ABI
*/
#define ELF_NOTE_ABI 1
 
/* Known OSes. These value can appear in word 0 of an ELF_NOTE_ABI
note section entry. */
#define ELF_NOTE_OS_LINUX 0
#define ELF_NOTE_OS_GNU 1
#define ELF_NOTE_OS_SOLARIS2 2
 
 
/* Motorola 68k specific definitions. */
 
/* m68k relocs. */
 
#define R_68K_NONE 0 /* No reloc */
#define R_68K_32 1 /* Direct 32 bit */
#define R_68K_16 2 /* Direct 16 bit */
#define R_68K_8 3 /* Direct 8 bit */
#define R_68K_PC32 4 /* PC relative 32 bit */
#define R_68K_PC16 5 /* PC relative 16 bit */
#define R_68K_PC8 6 /* PC relative 8 bit */
#define R_68K_GOT32 7 /* 32 bit PC relative GOT entry */
#define R_68K_GOT16 8 /* 16 bit PC relative GOT entry */
#define R_68K_GOT8 9 /* 8 bit PC relative GOT entry */
#define R_68K_GOT32O 10 /* 32 bit GOT offset */
#define R_68K_GOT16O 11 /* 16 bit GOT offset */
#define R_68K_GOT8O 12 /* 8 bit GOT offset */
#define R_68K_PLT32 13 /* 32 bit PC relative PLT address */
#define R_68K_PLT16 14 /* 16 bit PC relative PLT address */
#define R_68K_PLT8 15 /* 8 bit PC relative PLT address */
#define R_68K_PLT32O 16 /* 32 bit PLT offset */
#define R_68K_PLT16O 17 /* 16 bit PLT offset */
#define R_68K_PLT8O 18 /* 8 bit PLT offset */
#define R_68K_COPY 19 /* Copy symbol at runtime */
#define R_68K_GLOB_DAT 20 /* Create GOT entry */
#define R_68K_JMP_SLOT 21 /* Create PLT entry */
#define R_68K_RELATIVE 22 /* Adjust by program base */
/* Keep this the last entry. */
#define R_68K_NUM 23
 
/* Intel 80386 specific definitions. */
 
/* i386 relocs. */
 
#define R_386_NONE 0 /* No reloc */
#define R_386_32 1 /* Direct 32 bit */
#define R_386_PC32 2 /* PC relative 32 bit */
#define R_386_GOT32 3 /* 32 bit GOT entry */
#define R_386_PLT32 4 /* 32 bit PLT address */
#define R_386_COPY 5 /* Copy symbol at runtime */
#define R_386_GLOB_DAT 6 /* Create GOT entry */
#define R_386_JMP_SLOT 7 /* Create PLT entry */
#define R_386_RELATIVE 8 /* Adjust by program base */
#define R_386_GOTOFF 9 /* 32 bit offset to GOT */
#define R_386_GOTPC 10 /* 32 bit PC relative offset to GOT */
/* Keep this the last entry. */
#define R_386_NUM 11
 
/* SUN SPARC specific definitions. */
 
/* Values for Elf64_Ehdr.e_flags. */
 
#define EF_SPARCV9_MM 3
#define EF_SPARCV9_TSO 0
#define EF_SPARCV9_PSO 1
#define EF_SPARCV9_RMO 2
#define EF_SPARC_EXT_MASK 0xFFFF00
#define EF_SPARC_SUN_US1 0x000200
#define EF_SPARC_HAL_R1 0x000400
 
/* SPARC relocs. */
 
#define R_SPARC_NONE 0 /* No reloc */
#define R_SPARC_8 1 /* Direct 8 bit */
#define R_SPARC_16 2 /* Direct 16 bit */
#define R_SPARC_32 3 /* Direct 32 bit */
#define R_SPARC_DISP8 4 /* PC relative 8 bit */
#define R_SPARC_DISP16 5 /* PC relative 16 bit */
#define R_SPARC_DISP32 6 /* PC relative 32 bit */
#define R_SPARC_WDISP30 7 /* PC relative 30 bit shifted */
#define R_SPARC_WDISP22 8 /* PC relative 22 bit shifted */
#define R_SPARC_HI22 9 /* High 22 bit */
#define R_SPARC_22 10 /* Direct 22 bit */
#define R_SPARC_13 11 /* Direct 13 bit */
#define R_SPARC_LO10 12 /* Truncated 10 bit */
#define R_SPARC_GOT10 13 /* Truncated 10 bit GOT entry */
#define R_SPARC_GOT13 14 /* 13 bit GOT entry */
#define R_SPARC_GOT22 15 /* 22 bit GOT entry shifted */
#define R_SPARC_PC10 16 /* PC relative 10 bit truncated */
#define R_SPARC_PC22 17 /* PC relative 22 bit shifted */
#define R_SPARC_WPLT30 18 /* 30 bit PC relative PLT address */
#define R_SPARC_COPY 19 /* Copy symbol at runtime */
#define R_SPARC_GLOB_DAT 20 /* Create GOT entry */
#define R_SPARC_JMP_SLOT 21 /* Create PLT entry */
#define R_SPARC_RELATIVE 22 /* Adjust by program base */
#define R_SPARC_UA32 23 /* Direct 32 bit unaligned */
 
/* Additional Sparc64 relocs. */
 
#define R_SPARC_PLT32 24 /* Direct 32 bit ref to PLT entry */
#define R_SPARC_HIPLT22 25 /* High 22 bit PLT entry */
#define R_SPARC_LOPLT10 26 /* Truncated 10 bit PLT entry */
#define R_SPARC_PCPLT32 27 /* PC rel 32 bit ref to PLT entry */
#define R_SPARC_PCPLT22 28 /* PC rel high 22 bit PLT entry */
#define R_SPARC_PCPLT10 29 /* PC rel trunc 10 bit PLT entry */
#define R_SPARC_10 30 /* Direct 10 bit */
#define R_SPARC_11 31 /* Direct 11 bit */
#define R_SPARC_64 32 /* Direct 64 bit */
#define R_SPARC_OLO10 33 /* ?? */
#define R_SPARC_HH22 34 /* Top 22 bits of direct 64 bit */
#define R_SPARC_HM10 35 /* High middle 10 bits of ... */
#define R_SPARC_LM22 36 /* Low middle 22 bits of ... */
#define R_SPARC_PC_HH22 37 /* Top 22 bits of pc rel 64 bit */
#define R_SPARC_PC_HM10 38 /* High middle 10 bit of ... */
#define R_SPARC_PC_LM22 39 /* Low miggle 22 bits of ... */
#define R_SPARC_WDISP16 40 /* PC relative 16 bit shifted */
#define R_SPARC_WDISP19 41 /* PC relative 19 bit shifted */
#define R_SPARC_7 43 /* Direct 7 bit */
#define R_SPARC_5 44 /* Direct 5 bit */
#define R_SPARC_6 45 /* Direct 6 bit */
#define R_SPARC_DISP64 46 /* PC relative 64 bit */
#define R_SPARC_PLT64 47 /* Direct 64 bit ref to PLT entry */
#define R_SPARC_HIX22 48 /* High 22 bit complemented */
#define R_SPARC_LOX10 49 /* Truncated 11 bit complemented */
#define R_SPARC_H44 50 /* Direct high 12 of 44 bit */
#define R_SPARC_M44 51 /* Direct mid 22 of 44 bit */
#define R_SPARC_L44 52 /* Direct low 10 of 44 bit */
#define R_SPARC_REGISTER 53 /* Global register usage */
#define R_SPARC_UA64 54 /* Direct 64 bit unaligned */
#define R_SPARC_UA16 55 /* Direct 16 bit unaligned */
/* Keep this the last entry. */
#define R_SPARC_NUM 56
 
/* For Sparc64, legal values for d_tag of Elf64_Dyn. */
 
#define DT_SPARC_REGISTER 0x70000001
#define DT_SPARC_NUM 2
 
/* Bits present in AT_HWCAP, primarily for Sparc32. */
 
#define HWCAP_SPARC_FLUSH 1 /* The cpu supports flush insn. */
#define HWCAP_SPARC_STBAR 2
#define HWCAP_SPARC_SWAP 4
#define HWCAP_SPARC_MULDIV 8
#define HWCAP_SPARC_V9 16 /* The cpu is v9, so v8plus is ok. */
 
/* MIPS R3000 specific definitions. */
 
/* Legal values for e_flags field of Elf32_Ehdr. */
 
#define EF_MIPS_NOREORDER 1 /* A .noreorder directive was used */
#define EF_MIPS_PIC 2 /* Contains PIC code */
#define EF_MIPS_CPIC 4 /* Uses PIC calling sequence */
#define EF_MIPS_XGOT 8
#define EF_MIPS_64BIT_WHIRL 16
#define EF_MIPS_ABI2 32
#define EF_MIPS_ABI_ON32 64
#define EF_MIPS_ARCH 0xf0000000 /* MIPS architecture level */
 
/* Legal values for MIPS architecture level. */
 
#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */
#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */
#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */
#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */
#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */
 
/* The following are non-official names and should not be used. */
 
#define E_MIPS_ARCH_1 0x00000000 /* -mips1 code. */
#define E_MIPS_ARCH_2 0x10000000 /* -mips2 code. */
#define E_MIPS_ARCH_3 0x20000000 /* -mips3 code. */
#define E_MIPS_ARCH_4 0x30000000 /* -mips4 code. */
#define E_MIPS_ARCH_5 0x40000000 /* -mips5 code. */
 
/* Special section indices. */
 
#define SHN_MIPS_ACOMMON 0xff00 /* Allocated common symbols */
#define SHN_MIPS_TEXT 0xff01 /* Allocated test symbols. */
#define SHN_MIPS_DATA 0xff02 /* Allocated data symbols. */
#define SHN_MIPS_SCOMMON 0xff03 /* Small common symbols */
#define SHN_MIPS_SUNDEFINED 0xff04 /* Small undefined symbols */
 
/* Legal values for sh_type field of Elf32_Shdr. */
 
#define SHT_MIPS_LIBLIST 0x70000000 /* Shared objects used in link */
#define SHT_MIPS_MSYM 0x70000001
#define SHT_MIPS_CONFLICT 0x70000002 /* Conflicting symbols */
#define SHT_MIPS_GPTAB 0x70000003 /* Global data area sizes */
#define SHT_MIPS_UCODE 0x70000004 /* Reserved for SGI/MIPS compilers */
#define SHT_MIPS_DEBUG 0x70000005 /* MIPS ECOFF debugging information*/
#define SHT_MIPS_REGINFO 0x70000006 /* Register usage information */
#define SHT_MIPS_PACKAGE 0x70000007
#define SHT_MIPS_PACKSYM 0x70000008
#define SHT_MIPS_RELD 0x70000009
#define SHT_MIPS_IFACE 0x7000000b
#define SHT_MIPS_CONTENT 0x7000000c
#define SHT_MIPS_OPTIONS 0x7000000d /* Miscellaneous options. */
#define SHT_MIPS_SHDR 0x70000010
#define SHT_MIPS_FDESC 0x70000011
#define SHT_MIPS_EXTSYM 0x70000012
#define SHT_MIPS_DENSE 0x70000013
#define SHT_MIPS_PDESC 0x70000014
#define SHT_MIPS_LOCSYM 0x70000015
#define SHT_MIPS_AUXSYM 0x70000016
#define SHT_MIPS_OPTSYM 0x70000017
#define SHT_MIPS_LOCSTR 0x70000018
#define SHT_MIPS_LINE 0x70000019
#define SHT_MIPS_RFDESC 0x7000001a
#define SHT_MIPS_DELTASYM 0x7000001b
#define SHT_MIPS_DELTAINST 0x7000001c
#define SHT_MIPS_DELTACLASS 0x7000001d
#define SHT_MIPS_DWARF 0x7000001e /* DWARF debugging information. */
#define SHT_MIPS_DELTADECL 0x7000001f
#define SHT_MIPS_SYMBOL_LIB 0x70000020
#define SHT_MIPS_EVENTS 0x70000021 /* Event section. */
#define SHT_MIPS_TRANSLATE 0x70000022
#define SHT_MIPS_PIXIE 0x70000023
#define SHT_MIPS_XLATE 0x70000024
#define SHT_MIPS_XLATE_DEBUG 0x70000025
#define SHT_MIPS_WHIRL 0x70000026
#define SHT_MIPS_EH_REGION 0x70000027
#define SHT_MIPS_XLATE_OLD 0x70000028
#define SHT_MIPS_PDR_EXCEPTION 0x70000029
 
/* Legal values for sh_flags field of Elf32_Shdr. */
 
#define SHF_MIPS_GPREL 0x10000000 /* Must be part of global data area */
#define SHF_MIPS_MERGE 0x20000000
#define SHF_MIPS_ADDR 0x40000000
#define SHF_MIPS_STRINGS 0x80000000
#define SHF_MIPS_NOSTRIP 0x08000000
#define SHF_MIPS_LOCAL 0x04000000
#define SHF_MIPS_NAMES 0x02000000
#define SHF_MIPS_NODUPE 0x01000000
 
 
/* Symbol tables. */
 
/* MIPS specific values for `st_other'. */
#define STO_MIPS_DEFAULT 0x0
#define STO_MIPS_INTERNAL 0x1
#define STO_MIPS_HIDDEN 0x2
#define STO_MIPS_PROTECTED 0x3
#define STO_MIPS_SC_ALIGN_UNUSED 0xff
 
/* MIPS specific values for `st_info'. */
#define STB_MIPS_SPLIT_COMMON 13
 
/* Entries found in sections of type SHT_MIPS_GPTAB. */
 
typedef union
{
struct
{
Elf32_Word gt_current_g_value; /* -G value used for compilation */
Elf32_Word gt_unused; /* Not used */
} gt_header; /* First entry in section */
struct
{
Elf32_Word gt_g_value; /* If this value were used for -G */
Elf32_Word gt_bytes; /* This many bytes would be used */
} gt_entry; /* Subsequent entries in section */
} Elf32_gptab;
 
/* Entry found in sections of type SHT_MIPS_REGINFO. */
 
typedef struct
{
Elf32_Word ri_gprmask; /* General registers used */
Elf32_Word ri_cprmask[4]; /* Coprocessor registers used */
Elf32_Sword ri_gp_value; /* $gp register value */
} Elf32_RegInfo;
 
/* Entries found in sections of type SHT_MIPS_OPTIONS. */
 
typedef struct
{
unsigned char kind; /* Determines interpretation of the
variable part of descriptor. */
unsigned char size; /* Size of descriptor, including header. */
Elf32_Section section; /* Section header index of section affected,
0 for global options. */
Elf32_Word info; /* Kind-specific information. */
} Elf_Options;
 
/* Values for `kind' field in Elf_Options. */
 
#define ODK_NULL 0 /* Undefined. */
#define ODK_REGINFO 1 /* Register usage information. */
#define ODK_EXCEPTIONS 2 /* Exception processing options. */
#define ODK_PAD 3 /* Section padding options. */
#define ODK_HWPATCH 4 /* Hardware workarounds performed */
#define ODK_FILL 5 /* record the fill value used by the linker. */
#define ODK_TAGS 6 /* reserve space for desktop tools to write. */
#define ODK_HWAND 7 /* HW workarounds. 'AND' bits when merging. */
#define ODK_HWOR 8 /* HW workarounds. 'OR' bits when merging. */
 
/* Values for `info' in Elf_Options for ODK_EXCEPTIONS entries. */
 
#define OEX_FPU_MIN 0x1f /* FPE's which MUST be enabled. */
#define OEX_FPU_MAX 0x1f00 /* FPE's which MAY be enabled. */
#define OEX_PAGE0 0x10000 /* page zero must be mapped. */
#define OEX_SMM 0x20000 /* Force sequential memory mode? */
#define OEX_FPDBUG 0x40000 /* Force floating point debug mode? */
#define OEX_PRECISEFP OEX_FPDBUG
#define OEX_DISMISS 0x80000 /* Dismiss invalid address faults? */
 
#define OEX_FPU_INVAL 0x10
#define OEX_FPU_DIV0 0x08
#define OEX_FPU_OFLO 0x04
#define OEX_FPU_UFLO 0x02
#define OEX_FPU_INEX 0x01
 
/* Masks for `info' in Elf_Options for an ODK_HWPATCH entry. */
 
#define OHW_R4KEOP 0x1 /* R4000 end-of-page patch. */
#define OHW_R8KPFETCH 0x2 /* may need R8000 prefetch patch. */
#define OHW_R5KEOP 0x4 /* R5000 end-of-page patch. */
#define OHW_R5KCVTL 0x8 /* R5000 cvt.[ds].l bug. clean=1. */
 
#define OPAD_PREFIX 0x1
#define OPAD_POSTFIX 0x2
#define OPAD_SYMBOL 0x4
 
/* Entry found in `.options' section. */
 
typedef struct
{
Elf32_Word hwp_flags1; /* Extra flags. */
Elf32_Word hwp_flags2; /* Extra flags. */
} Elf_Options_Hw;
 
/* Masks for `info' in ElfOptions for ODK_HWAND and ODK_HWOR entries. */
 
#define OHWA0_R4KEOP_CHECKED 0x00000001
#define OHWA1_R4KEOP_CLEAN 0x00000002
 
/* MIPS relocs. */
 
#define R_MIPS_NONE 0 /* No reloc */
#define R_MIPS_16 1 /* Direct 16 bit */
#define R_MIPS_32 2 /* Direct 32 bit */
#define R_MIPS_REL32 3 /* PC relative 32 bit */
#define R_MIPS_26 4 /* Direct 26 bit shifted */
#define R_MIPS_HI16 5 /* High 16 bit */
#define R_MIPS_LO16 6 /* Low 16 bit */
#define R_MIPS_GPREL16 7 /* GP relative 16 bit */
#define R_MIPS_LITERAL 8 /* 16 bit literal entry */
#define R_MIPS_GOT16 9 /* 16 bit GOT entry */
#define R_MIPS_PC16 10 /* PC relative 16 bit */
#define R_MIPS_CALL16 11 /* 16 bit GOT entry for function */
#define R_MIPS_GPREL32 12 /* GP relative 32 bit */
 
#define R_MIPS_SHIFT5 16
#define R_MIPS_SHIFT6 17
#define R_MIPS_64 18
#define R_MIPS_GOT_DISP 19
#define R_MIPS_GOT_PAGE 20
#define R_MIPS_GOT_OFST 21
#define R_MIPS_GOT_HI16 22
#define R_MIPS_GOT_LO16 23
#define R_MIPS_SUB 24
#define R_MIPS_INSERT_A 25
#define R_MIPS_INSERT_B 26
#define R_MIPS_DELETE 27
#define R_MIPS_HIGHER 28
#define R_MIPS_HIGHEST 29
#define R_MIPS_CALL_HI16 30
#define R_MIPS_CALL_LO16 31
#define R_MIPS_SCN_DISP 32
#define R_MIPS_REL16 33
#define R_MIPS_ADD_IMMEDIATE 34
#define R_MIPS_PJUMP 35
#define R_MIPS_RELGOT 36
#define R_MIPS_JALR 37
/* Keep this the last entry. */
#define R_MIPS_NUM 38
 
/* Legal values for p_type field of Elf32_Phdr. */
 
#define PT_MIPS_REGINFO 0x70000000 /* Register usage information */
#define PT_MIPS_RTPROC 0x70000001 /* Runtime procedure table. */
#define PT_MIPS_OPTIONS 0x70000002
 
/* Special program header types. */
 
#define PF_MIPS_LOCAL 0x10000000
 
/* Legal values for d_tag field of Elf32_Dyn. */
 
#define DT_MIPS_RLD_VERSION 0x70000001 /* Runtime linker interface version */
#define DT_MIPS_TIME_STAMP 0x70000002 /* Timestamp */
#define DT_MIPS_ICHECKSUM 0x70000003 /* Checksum */
#define DT_MIPS_IVERSION 0x70000004 /* Version string (string tbl index) */
#define DT_MIPS_FLAGS 0x70000005 /* Flags */
#define DT_MIPS_BASE_ADDRESS 0x70000006 /* Base address */
#define DT_MIPS_MSYM 0x70000007
#define DT_MIPS_CONFLICT 0x70000008 /* Address of CONFLICT section */
#define DT_MIPS_LIBLIST 0x70000009 /* Address of LIBLIST section */
#define DT_MIPS_LOCAL_GOTNO 0x7000000a /* Number of local GOT entries */
#define DT_MIPS_CONFLICTNO 0x7000000b /* Number of CONFLICT entries */
#define DT_MIPS_LIBLISTNO 0x70000010 /* Number of LIBLIST entries */
#define DT_MIPS_SYMTABNO 0x70000011 /* Number of DYNSYM entries */
#define DT_MIPS_UNREFEXTNO 0x70000012 /* First external DYNSYM */
#define DT_MIPS_GOTSYM 0x70000013 /* First GOT entry in DYNSYM */
#define DT_MIPS_HIPAGENO 0x70000014 /* Number of GOT page table entries */
#define DT_MIPS_RLD_MAP 0x70000016 /* Address of run time loader map. */
#define DT_MIPS_DELTA_CLASS 0x70000017 /* Delta C++ class definition. */
#define DT_MIPS_DELTA_CLASS_NO 0x70000018 /* Number of entries in
DT_MIPS_DELTA_CLASS. */
#define DT_MIPS_DELTA_INSTANCE 0x70000019 /* Delta C++ class instances. */
#define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a /* Number of entries in
DT_MIPS_DELTA_INSTANCE. */
#define DT_MIPS_DELTA_RELOC 0x7000001b /* Delta relocations. */
#define DT_MIPS_DELTA_RELOC_NO 0x7000001c /* Number of entries in
DT_MIPS_DELTA_RELOC. */
#define DT_MIPS_DELTA_SYM 0x7000001d /* Delta symbols that Delta
relocations refer to. */
#define DT_MIPS_DELTA_SYM_NO 0x7000001e /* Number of entries in
DT_MIPS_DELTA_SYM. */
#define DT_MIPS_DELTA_CLASSSYM 0x70000020 /* Delta symbols that hold the
class declaration. */
#define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 /* Number of entries in
DT_MIPS_DELTA_CLASSSYM. */
#define DT_MIPS_CXX_FLAGS 0x70000022 /* Flags indicating for C++ flavor. */
#define DT_MIPS_PIXIE_INIT 0x70000023
#define DT_MIPS_SYMBOL_LIB 0x70000024
#define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025
#define DT_MIPS_LOCAL_GOTIDX 0x70000026
#define DT_MIPS_HIDDEN_GOTIDX 0x70000027
#define DT_MIPS_PROTECTED_GOTIDX 0x70000028
#define DT_MIPS_OPTIONS 0x70000029 /* Address of .options. */
#define DT_MIPS_INTERFACE 0x7000002a /* Address of .interface. */
#define DT_MIPS_DYNSTR_ALIGN 0x7000002b
#define DT_MIPS_INTERFACE_SIZE 0x7000002c /* Size of the .interface section. */
#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d /* Address of rld_text_rsolve
function stored in GOT. */
#define DT_MIPS_PERF_SUFFIX 0x7000002e /* Default suffix of dso to be added
by rld on dlopen() calls. */
#define DT_MIPS_COMPACT_SIZE 0x7000002f /* (O32)Size of compact rel section. */
#define DT_MIPS_GP_VALUE 0x70000030 /* GP value for aux GOTs. */
#define DT_MIPS_AUX_DYNAMIC 0x70000031 /* Address of aux .dynamic. */
#define DT_MIPS_NUM 0x32
 
/* Legal values for DT_MIPS_FLAGS Elf32_Dyn entry. */
 
#define RHF_NONE 0 /* No flags */
#define RHF_QUICKSTART (1 << 0) /* Use quickstart */
#define RHF_NOTPOT (1 << 1) /* Hash size not power of 2 */
#define RHF_NO_LIBRARY_REPLACEMENT (1 << 2) /* Ignore LD_LIBRARY_PATH */
#define RHF_NO_MOVE (1 << 3)
#define RHF_SGI_ONLY (1 << 4)
#define RHF_GUARANTEE_INIT (1 << 5)
#define RHF_DELTA_C_PLUS_PLUS (1 << 6)
#define RHF_GUARANTEE_START_INIT (1 << 7)
#define RHF_PIXIE (1 << 8)
#define RHF_DEFAULT_DELAY_LOAD (1 << 9)
#define RHF_REQUICKSTART (1 << 10)
#define RHF_REQUICKSTARTED (1 << 11)
#define RHF_CORD (1 << 12)
#define RHF_NO_UNRES_UNDEF (1 << 13)
#define RHF_RLD_ORDER_SAFE (1 << 14)
 
/* Entries found in sections of type SHT_MIPS_LIBLIST. */
 
typedef struct
{
Elf32_Word l_name; /* Name (string table index) */
Elf32_Word l_time_stamp; /* Timestamp */
Elf32_Word l_checksum; /* Checksum */
Elf32_Word l_version; /* Interface version */
Elf32_Word l_flags; /* Flags */
} Elf32_Lib;
 
typedef struct
{
Elf64_Word l_name; /* Name (string table index) */
Elf64_Word l_time_stamp; /* Timestamp */
Elf64_Word l_checksum; /* Checksum */
Elf64_Word l_version; /* Interface version */
Elf64_Word l_flags; /* Flags */
} Elf64_Lib;
 
 
/* Legal values for l_flags. */
 
#define LL_NONE 0
#define LL_EXACT_MATCH (1 << 0) /* Require exact match */
#define LL_IGNORE_INT_VER (1 << 1) /* Ignore interface version */
#define LL_REQUIRE_MINOR (1 << 2)
#define LL_EXPORTS (1 << 3)
#define LL_DELAY_LOAD (1 << 4)
#define LL_DELTA (1 << 5)
 
/* Entries found in sections of type SHT_MIPS_CONFLICT. */
 
typedef Elf32_Addr Elf32_Conflict;
 
 
/* HPPA specific definitions. */
 
/* Legal values for e_flags field of Elf32_Ehdr. */
 
#define EF_PARISC_TRAPNL 1 /* Trap nil pointer dereference. */
#define EF_PARISC_EXT 2 /* Program uses arch. extensions. */
#define EF_PARISC_ARCH 0xffff0000 /* Architecture version. */
/* Defined values are:
0x020b PA-RISC 1.0 big-endian
0x0210 PA-RISC 1.1 big-endian
0x028b PA-RISC 1.0 little-endian
0x0290 PA-RISC 1.1 little-endian
*/
 
/* Legal values for sh_type field of Elf32_Shdr. */
 
#define SHT_PARISC_GOT 0x70000000 /* GOT for external data. */
#define SHT_PARISC_ARCH 0x70000001 /* Architecture extensions. */
#define SHT_PARISC_GLOBAL 0x70000002 /* Definition of $global$. */
#define SHT_PARISC_MILLI 0x70000003 /* Millicode routines. */
#define SHT_PARISC_UNWIND 0x70000004 /* Unwind information. */
#define SHT_PARISC_PLT 0x70000005 /* Procedure linkage table. */
#define SHT_PARISC_SDATA 0x70000006 /* Short initialized data. */
#define SHT_PARISC_SBSS 0x70000007 /* Short uninitialized data. */
#define SHT_PARISC_SYMEXTN 0x70000008 /* Argument/relocation info. */
#define SHT_PARISC_STUBS 0x70000009 /* Linker stubs. */
 
/* Legal values for sh_flags field of Elf32_Shdr. */
 
#define SHF_PARISC_GLOBAL 0x10000000 /* Section defines dp. */
#define SHF_PARISC_SHORT 0x20000000 /* Section with short addressing. */
 
/* Legal values for ST_TYPE subfield of st_info (symbol type). */
 
#define STT_PARISC_MILLICODE 13 /* Millicode function entry point. */
 
/* HPPA relocs. */
 
#define R_PARISC_NONE 0 /* No reloc. */
#define R_PARISC_DIR32 1 /* Direct 32-bit reference. */
#define R_PARISC_DIR21L 2 /* Left 21 bits of eff. address. */
#define R_PARISC_DIR17R 3 /* Right 17 bits of eff. address. */
#define R_PARISC_DIR14R 4 /* Right 14 bits of eff. address. */
#define R_PARISC_PCREL21L 5 /* PC-relative, left 21 bits. */
#define R_PARISC_PCREL14R 6 /* PC-relative, right 14 bits. */
#define R_PARISC_PCREL17C 7 /* Conditional PC-relative, ignore
if displacement > 17bits. */
#define R_PARISC_PCREL17F 8 /* Conditional PC-relative, must
fit in 17bits. */
#define R_PARISC_DPREL21L 9 /* DP-relative, left 21 bits. */
#define R_PARISC_DPREL14R 10 /* DP-relative, right 14 bits. */
#define R_PARISC_DPREL14F 11 /* DP-relative, must bit in 14 bits. */
#define R_PARISC_DLTREL21L 12 /* DLT-relative, left 21 bits. */
#define R_PARISC_DLTREL14R 13 /* DLT-relative, right 14 bits. */
#define R_PARISC_DLTREL14F 14 /* DLT-relative, must fit in 14 bits.*/
#define R_PARISC_DLTIND21L 15 /* DLT-relative indirect, left
21 bits. */
#define R_PARISC_DLTIND14R 16 /* DLT-relative indirect, right
14 bits. */
#define R_PARISC_DLTIND14F 17 /* DLT-relative indirect, must fit
int 14 bits. */
#define R_PARISC_PLABEL32 18 /* Direct 32-bit reference to proc. */
 
/* Alpha specific definitions. */
 
/* Legal values for e_flags field of Elf64_Ehdr. */
 
#define EF_ALPHA_32BIT 1 /* All addresses must be < 2GB. */
#define EF_ALPHA_CANRELAX 2 /* Relocations for relaxing exist. */
 
/* Legal values for sh_type field of Elf64_Shdr. */
 
/* These two are primerily concerned with ECOFF debugging info. */
#define SHT_ALPHA_DEBUG 0x70000001
#define SHT_ALPHA_REGINFO 0x70000002
 
/* Legal values for sh_flags field of Elf64_Shdr. */
 
#define SHF_ALPHA_GPREL 0x10000000
 
/* Legal values for st_other field of Elf64_Sym. */
#define STO_ALPHA_NOPV 0x80 /* No PV required. */
#define STO_ALPHA_STD_GPLOAD 0x88 /* PV only used for initial ldgp. */
 
/* Alpha relocs. */
 
#define R_ALPHA_NONE 0 /* No reloc */
#define R_ALPHA_REFLONG 1 /* Direct 32 bit */
#define R_ALPHA_REFQUAD 2 /* Direct 64 bit */
#define R_ALPHA_GPREL32 3 /* GP relative 32 bit */
#define R_ALPHA_LITERAL 4 /* GP relative 16 bit w/optimization */
#define R_ALPHA_LITUSE 5 /* Optimization hint for LITERAL */
#define R_ALPHA_GPDISP 6 /* Add displacement to GP */
#define R_ALPHA_BRADDR 7 /* PC+4 relative 23 bit shifted */
#define R_ALPHA_HINT 8 /* PC+4 relative 16 bit shifted */
#define R_ALPHA_SREL16 9 /* PC relative 16 bit */
#define R_ALPHA_SREL32 10 /* PC relative 32 bit */
#define R_ALPHA_SREL64 11 /* PC relative 64 bit */
#define R_ALPHA_OP_PUSH 12 /* OP stack push */
#define R_ALPHA_OP_STORE 13 /* OP stack pop and store */
#define R_ALPHA_OP_PSUB 14 /* OP stack subtract */
#define R_ALPHA_OP_PRSHIFT 15 /* OP stack right shift */
#define R_ALPHA_GPVALUE 16
#define R_ALPHA_GPRELHIGH 17
#define R_ALPHA_GPRELLOW 18
#define R_ALPHA_IMMED_GP_16 19
#define R_ALPHA_IMMED_GP_HI32 20
#define R_ALPHA_IMMED_SCN_HI32 21
#define R_ALPHA_IMMED_BR_HI32 22
#define R_ALPHA_IMMED_LO32 23
#define R_ALPHA_COPY 24 /* Copy symbol at runtime */
#define R_ALPHA_GLOB_DAT 25 /* Create GOT entry */
#define R_ALPHA_JMP_SLOT 26 /* Create PLT entry */
#define R_ALPHA_RELATIVE 27 /* Adjust by program base */
/* Keep this the last entry. */
#define R_ALPHA_NUM 28
 
 
/* PowerPC specific declarations */
 
/* PowerPC relocations defined by the ABIs */
#define R_PPC_NONE 0
#define R_PPC_ADDR32 1 /* 32bit absolute address */
#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */
#define R_PPC_ADDR16 3 /* 16bit absolute address */
#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */
#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */
#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */
#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */
#define R_PPC_ADDR14_BRTAKEN 8
#define R_PPC_ADDR14_BRNTAKEN 9
#define R_PPC_REL24 10 /* PC relative 26 bit */
#define R_PPC_REL14 11 /* PC relative 16 bit */
#define R_PPC_REL14_BRTAKEN 12
#define R_PPC_REL14_BRNTAKEN 13
#define R_PPC_GOT16 14
#define R_PPC_GOT16_LO 15
#define R_PPC_GOT16_HI 16
#define R_PPC_GOT16_HA 17
#define R_PPC_PLTREL24 18
#define R_PPC_COPY 19
#define R_PPC_GLOB_DAT 20
#define R_PPC_JMP_SLOT 21
#define R_PPC_RELATIVE 22
#define R_PPC_LOCAL24PC 23
#define R_PPC_UADDR32 24
#define R_PPC_UADDR16 25
#define R_PPC_REL32 26
#define R_PPC_PLT32 27
#define R_PPC_PLTREL32 28
#define R_PPC_PLT16_LO 29
#define R_PPC_PLT16_HI 30
#define R_PPC_PLT16_HA 31
#define R_PPC_SDAREL16 32
#define R_PPC_SECTOFF 33
#define R_PPC_SECTOFF_LO 34
#define R_PPC_SECTOFF_HI 35
#define R_PPC_SECTOFF_HA 36
/* Keep this the last entry. */
#define R_PPC_NUM 37
 
/* The remaining relocs are from the Embedded ELF ABI, and are not
in the SVR4 ELF ABI. */
#define R_PPC_EMB_NADDR32 101
#define R_PPC_EMB_NADDR16 102
#define R_PPC_EMB_NADDR16_LO 103
#define R_PPC_EMB_NADDR16_HI 104
#define R_PPC_EMB_NADDR16_HA 105
#define R_PPC_EMB_SDAI16 106
#define R_PPC_EMB_SDA2I16 107
#define R_PPC_EMB_SDA2REL 108
#define R_PPC_EMB_SDA21 109 /* 16 bit offset in SDA */
#define R_PPC_EMB_MRKREF 110
#define R_PPC_EMB_RELSEC16 111
#define R_PPC_EMB_RELST_LO 112
#define R_PPC_EMB_RELST_HI 113
#define R_PPC_EMB_RELST_HA 114
#define R_PPC_EMB_BIT_FLD 115
#define R_PPC_EMB_RELSDA 116 /* 16 bit relative offset in SDA */
 
/* Diab tool relocations. */
#define R_PPC_DIAB_SDA21_LO 180 /* like EMB_SDA21, but lower 16 bit */
#define R_PPC_DIAB_SDA21_HI 181 /* like EMB_SDA21, but high 16 bit */
#define R_PPC_DIAB_SDA21_HA 182 /* like EMB_SDA21, adjusted high 16 */
#define R_PPC_DIAB_RELSDA_LO 183 /* like EMB_RELSDA, but lower 16 bit */
#define R_PPC_DIAB_RELSDA_HI 184 /* like EMB_RELSDA, but high 16 bit */
#define R_PPC_DIAB_RELSDA_HA 185 /* like EMB_RELSDA, adjusted high 16 */
 
/* This is a phony reloc to handle any old fashioned TOC16 references
that may still be in object files. */
#define R_PPC_TOC16 255
 
 
/* ARM specific declarations */
 
/* Processor specific flags for the ELF header e_flags field. */
#define EF_ARM_RELEXEC 0x01
#define EF_ARM_HASENTRY 0x02
#define EF_ARM_INTERWORK 0x04
#define EF_ARM_APCS_26 0x08
#define EF_ARM_APCS_FLOAT 0x10
#define EF_ARM_PIC 0x20
#define EF_ALIGN8 0x40 /* 8-bit structure alignment is in use */
#define EF_NEW_ABI 0x80
#define EF_OLD_ABI 0x100
 
/* Additional symbol types for Thumb */
#define STT_ARM_TFUNC 0xd
 
/* ARM-specific values for sh_flags */
#define SHF_ARM_ENTRYSECT 0x10000000 /* Section contains an entry point */
#define SHF_ARM_COMDEF 0x80000000 /* Section may be multiply defined
in the input to a link step */
 
/* ARM-specific program header flags */
#define PF_ARM_SB 0x10000000 /* Segment contains the location
addressed by the static base */
 
/* ARM relocs. */
#define R_ARM_NONE 0 /* No reloc */
#define R_ARM_PC24 1 /* PC relative 26 bit branch */
#define R_ARM_ABS32 2 /* Direct 32 bit */
#define R_ARM_REL32 3 /* PC relative 32 bit */
#define R_ARM_PC13 4
#define R_ARM_ABS16 5 /* Direct 16 bit */
#define R_ARM_ABS12 6 /* Direct 12 bit */
#define R_ARM_THM_ABS5 7
#define R_ARM_ABS8 8 /* Direct 8 bit */
#define R_ARM_SBREL32 9
#define R_ARM_THM_PC22 10
#define R_ARM_THM_PC8 11
#define R_ARM_AMP_VCALL9 12
#define R_ARM_SWI24 13
#define R_ARM_THM_SWI8 14
#define R_ARM_XPC25 15
#define R_ARM_THM_XPC22 16
#define R_ARM_COPY 20 /* Copy symbol at runtime */
#define R_ARM_GLOB_DAT 21 /* Create GOT entry */
#define R_ARM_JUMP_SLOT 22 /* Create PLT entry */
#define R_ARM_RELATIVE 23 /* Adjust by program base */
#define R_ARM_GOTOFF 24 /* 32 bit offset to GOT */
#define R_ARM_GOTPC 25 /* 32 bit PC relative offset to GOT */
#define R_ARM_GOT32 26 /* 32 bit GOT entry */
#define R_ARM_PLT32 27 /* 32 bit PLT address */
#define R_ARM_GNU_VTENTRY 100
#define R_ARM_GNU_VTINHERIT 101
#define R_ARM_THM_PC11 102 /* thumb unconditional branch */
#define R_ARM_THM_PC9 103 /* thumb conditional branch */
#define R_ARM_RXPC25 249
#define R_ARM_RSBREL32 250
#define R_ARM_THM_RPC22 251
#define R_ARM_RREL32 252
#define R_ARM_RABS22 253
#define R_ARM_RPC24 254
#define R_ARM_RBASE 255
/* Keep this the last entry. */
#define R_ARM_NUM 256
 
/* TMS320C67xx specific declarations */
/* XXX: no ELF standard yet */
 
/* TMS320C67xx relocs. */
#define R_C60_32 1
#define R_C60_GOT32 3 /* 32 bit GOT entry */
#define R_C60_PLT32 4 /* 32 bit PLT address */
#define R_C60_COPY 5 /* Copy symbol at runtime */
#define R_C60_GLOB_DAT 6 /* Create GOT entry */
#define R_C60_JMP_SLOT 7 /* Create PLT entry */
#define R_C60_RELATIVE 8 /* Adjust by program base */
#define R_C60_GOTOFF 9 /* 32 bit offset to GOT */
#define R_C60_GOTPC 10 /* 32 bit PC relative offset to GOT */
 
#define R_C60HI16 0x55 // high 16 bit MVKH embedded
#define R_C60LO16 0x54 // low 16 bit MVKL embedded
 
#endif /* elf.h */
/programs/develop/metcc/trunk/source/float.h
0,0 → 1,57
#ifndef _FLOAT_H_
#define _FLOAT_H_
 
#define FLT_RADIX 2
 
/* IEEE float */
#define FLT_MANT_DIG 24
#define FLT_DIG 6
#define FLT_ROUNDS 1
#define FLT_EPSILON 1.19209290e-07F
#define FLT_MIN_EXP (-125)
#define FLT_MIN 1.17549435e-38F
#define FLT_MIN_10_EXP (-37)
#define FLT_MAX_EXP 128
#define FLT_MAX 3.40282347e+38F
#define FLT_MAX_10_EXP 38
 
/* IEEE double */
#define DBL_MANT_DIG 53
#define DBL_DIG 15
#define DBL_EPSILON 2.2204460492503131e-16
#define DBL_MIN_EXP (-1021)
#define DBL_MIN 2.2250738585072014e-308
#define DBL_MIN_10_EXP (-307)
#define DBL_MAX_EXP 1024
#define DBL_MAX 1.7976931348623157e+308
#define DBL_MAX_10_EXP 308
 
/* horrible intel long double */
#ifdef __i386__
 
#define LDBL_MANT_DIG 64
#define LDBL_DIG 18
#define LDBL_EPSILON 1.08420217248550443401e-19L
#define LDBL_MIN_EXP (-16381)
#define LDBL_MIN 3.36210314311209350626e-4932L
#define LDBL_MIN_10_EXP (-4931)
#define LDBL_MAX_EXP 16384
#define LDBL_MAX 1.18973149535723176502e+4932L
#define LDBL_MAX_10_EXP 4932
 
#else
 
/* same as IEEE double */
#define LDBL_MANT_DIG 53
#define LDBL_DIG 15
#define LDBL_EPSILON 2.2204460492503131e-16
#define LDBL_MIN_EXP (-1021)
#define LDBL_MIN 2.2250738585072014e-308
#define LDBL_MIN_10_EXP (-307)
#define LDBL_MAX_EXP 1024
#define LDBL_MAX 1.7976931348623157e+308
#define LDBL_MAX_10_EXP 308
 
#endif
 
#endif /* _FLOAT_H_ */
/programs/develop/metcc/trunk/source/i386-asm.c
0,0 → 1,1183
/*
* i386 specific functions for TCC assembler
*
* Copyright (c) 2001, 2002 Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
 
#define MAX_OPERANDS 3
 
typedef struct ASMInstr {
uint16_t sym;
uint16_t opcode;
uint16_t instr_type;
#define OPC_JMP 0x01 /* jmp operand */
#define OPC_B 0x02 /* only used zith OPC_WL */
#define OPC_WL 0x04 /* accepts w, l or no suffix */
#define OPC_BWL (OPC_B | OPC_WL) /* accepts b, w, l or no suffix */
#define OPC_REG 0x08 /* register is added to opcode */
#define OPC_MODRM 0x10 /* modrm encoding */
#define OPC_FWAIT 0x20 /* add fwait opcode */
#define OPC_TEST 0x40 /* test opcodes */
#define OPC_SHIFT 0x80 /* shift opcodes */
#define OPC_D16 0x0100 /* generate data16 prefix */
#define OPC_ARITH 0x0200 /* arithmetic opcodes */
#define OPC_SHORTJMP 0x0400 /* short jmp operand */
#define OPC_FARITH 0x0800 /* FPU arithmetic opcodes */
#define OPC_GROUP_SHIFT 13
 
/* in order to compress the operand type, we use specific operands and
we or only with EA */
#define OPT_REG8 0 /* warning: value is hardcoded from TOK_ASM_xxx */
#define OPT_REG16 1 /* warning: value is hardcoded from TOK_ASM_xxx */
#define OPT_REG32 2 /* warning: value is hardcoded from TOK_ASM_xxx */
#define OPT_MMX 3 /* warning: value is hardcoded from TOK_ASM_xxx */
#define OPT_SSE 4 /* warning: value is hardcoded from TOK_ASM_xxx */
#define OPT_CR 5 /* warning: value is hardcoded from TOK_ASM_xxx */
#define OPT_TR 6 /* warning: value is hardcoded from TOK_ASM_xxx */
#define OPT_DB 7 /* warning: value is hardcoded from TOK_ASM_xxx */
#define OPT_SEG 8
#define OPT_ST 9
#define OPT_IM8 10
#define OPT_IM8S 11
#define OPT_IM16 12
#define OPT_IM32 13
#define OPT_EAX 14 /* %al, %ax or %eax register */
#define OPT_ST0 15 /* %st(0) register */
#define OPT_CL 16 /* %cl register */
#define OPT_DX 17 /* %dx register */
#define OPT_ADDR 18 /* OP_EA with only offset */
#define OPT_INDIR 19 /* *(expr) */
 
/* composite types */
#define OPT_COMPOSITE_FIRST 20
#define OPT_IM 20 /* IM8 | IM16 | IM32 */
#define OPT_REG 21 /* REG8 | REG16 | REG32 */
#define OPT_REGW 22 /* REG16 | REG32 */
#define OPT_IMW 23 /* IM16 | IM32 */
 
/* can be ored with any OPT_xxx */
#define OPT_EA 0x80
 
uint8_t nb_ops;
uint8_t op_type[MAX_OPERANDS]; /* see OP_xxx */
} ASMInstr;
 
typedef struct Operand {
uint32_t type;
#define OP_REG8 (1 << OPT_REG8)
#define OP_REG16 (1 << OPT_REG16)
#define OP_REG32 (1 << OPT_REG32)
#define OP_MMX (1 << OPT_MMX)
#define OP_SSE (1 << OPT_SSE)
#define OP_CR (1 << OPT_CR)
#define OP_TR (1 << OPT_TR)
#define OP_DB (1 << OPT_DB)
#define OP_SEG (1 << OPT_SEG)
#define OP_ST (1 << OPT_ST)
#define OP_IM8 (1 << OPT_IM8)
#define OP_IM8S (1 << OPT_IM8S)
#define OP_IM16 (1 << OPT_IM16)
#define OP_IM32 (1 << OPT_IM32)
#define OP_EAX (1 << OPT_EAX)
#define OP_ST0 (1 << OPT_ST0)
#define OP_CL (1 << OPT_CL)
#define OP_DX (1 << OPT_DX)
#define OP_ADDR (1 << OPT_ADDR)
#define OP_INDIR (1 << OPT_INDIR)
 
#define OP_EA 0x40000000
#define OP_REG (OP_REG8 | OP_REG16 | OP_REG32)
#define OP_IM OP_IM32
int8_t reg; /* register, -1 if none */
int8_t reg2; /* second register, -1 if none */
uint8_t shift;
ExprValue e;
} Operand;
 
static const uint8_t reg_to_size[5] = {
[OP_REG8] = 0,
[OP_REG16] = 1,
[OP_REG32] = 2,
};
#define WORD_PREFIX_OPCODE 0x66
 
#define NB_TEST_OPCODES 30
 
static const uint8_t test_bits[NB_TEST_OPCODES] = {
0x00, /* o */
0x01, /* no */
0x02, /* b */
0x02, /* c */
0x02, /* nae */
0x03, /* nb */
0x03, /* nc */
0x03, /* ae */
0x04, /* e */
0x04, /* z */
0x05, /* ne */
0x05, /* nz */
0x06, /* be */
0x06, /* na */
0x07, /* nbe */
0x07, /* a */
0x08, /* s */
0x09, /* ns */
0x0a, /* p */
0x0a, /* pe */
0x0b, /* np */
0x0b, /* po */
0x0c, /* l */
0x0c, /* nge */
0x0d, /* nl */
0x0d, /* ge */
0x0e, /* le */
0x0e, /* ng */
0x0f, /* nle */
0x0f, /* g */
};
 
static const ASMInstr asm_instrs[] = {
#define ALT(x) x
#define DEF_ASM_OP0(name, opcode)
#define DEF_ASM_OP0L(name, opcode, group, instr_type) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 0 },
#define DEF_ASM_OP1(name, opcode, group, instr_type, op0) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 1, { op0 }},
#define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 2, { op0, op1 }},
#define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 3, { op0, op1, op2 }},
#include "i386-asm.h"
 
/* last operation */
{ 0, },
};
 
static const uint16_t op0_codes[] = {
#define ALT(x)
#define DEF_ASM_OP0(x, opcode) opcode,
#define DEF_ASM_OP0L(name, opcode, group, instr_type)
#define DEF_ASM_OP1(name, opcode, group, instr_type, op0)
#define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1)
#define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2)
#include "i386-asm.h"
};
 
static inline int get_reg_shift(TCCState *s1)
{
int shift, v;
 
v = asm_int_expr(s1);
switch(v) {
case 1:
shift = 0;
break;
case 2:
shift = 1;
break;
case 4:
shift = 2;
break;
case 8:
shift = 3;
break;
default:
expect("1, 2, 4 or 8 constant");
shift = 0;
break;
}
return shift;
}
 
static int asm_parse_reg(void)
{
int reg;
if (tok != '%')
goto error_32;
next();
if (tok >= TOK_ASM_eax && tok <= TOK_ASM_edi) {
reg = tok - TOK_ASM_eax;
next();
return reg;
} else {
error_32:
expect("32 bit register");
return 0;
}
}
 
static void parse_operand(TCCState *s1, Operand *op)
{
ExprValue e;
int reg, indir;
const char *p;
 
indir = 0;
if (tok == '*') {
next();
indir = OP_INDIR;
}
 
if (tok == '%') {
next();
if (tok >= TOK_ASM_al && tok <= TOK_ASM_db7) {
reg = tok - TOK_ASM_al;
op->type = 1 << (reg >> 3); /* WARNING: do not change constant order */
op->reg = reg & 7;
if ((op->type & OP_REG) && op->reg == TREG_EAX)
op->type |= OP_EAX;
else if (op->type == OP_REG8 && op->reg == TREG_ECX)
op->type |= OP_CL;
else if (op->type == OP_REG16 && op->reg == TREG_EDX)
op->type |= OP_DX;
} else if (tok >= TOK_ASM_dr0 && tok <= TOK_ASM_dr7) {
op->type = OP_DB;
op->reg = tok - TOK_ASM_dr0;
} else if (tok >= TOK_ASM_es && tok <= TOK_ASM_gs) {
op->type = OP_SEG;
op->reg = tok - TOK_ASM_es;
} else if (tok == TOK_ASM_st) {
op->type = OP_ST;
op->reg = 0;
next();
if (tok == '(') {
next();
if (tok != TOK_PPNUM)
goto reg_error;
p = tokc.cstr->data;
reg = p[0] - '0';
if ((unsigned)reg >= 8 || p[1] != '\0')
goto reg_error;
op->reg = reg;
next();
skip(')');
}
if (op->reg == 0)
op->type |= OP_ST0;
goto no_skip;
} else {
reg_error:
error("unknown register");
}
next();
no_skip: ;
} else if (tok == '$') {
/* constant value */
next();
asm_expr(s1, &e);
op->type = OP_IM32;
op->e.v = e.v;
op->e.sym = e.sym;
if (!op->e.sym) {
if (op->e.v == (uint8_t)op->e.v)
op->type |= OP_IM8;
if (op->e.v == (int8_t)op->e.v)
op->type |= OP_IM8S;
if (op->e.v == (uint16_t)op->e.v)
op->type |= OP_IM16;
}
} else {
/* address(reg,reg2,shift) with all variants */
op->type = OP_EA;
op->reg = -1;
op->reg2 = -1;
op->shift = 0;
if (tok != '(') {
asm_expr(s1, &e);
op->e.v = e.v;
op->e.sym = e.sym;
} else {
op->e.v = 0;
op->e.sym = NULL;
}
if (tok == '(') {
next();
if (tok != ',') {
op->reg = asm_parse_reg();
}
if (tok == ',') {
next();
if (tok != ',') {
op->reg2 = asm_parse_reg();
}
skip(',');
op->shift = get_reg_shift(s1);
}
skip(')');
}
if (op->reg == -1 && op->reg2 == -1)
op->type |= OP_ADDR;
}
op->type |= indir;
}
 
/* XXX: unify with C code output ? */
static void gen_expr32(ExprValue *pe)
{
if (pe->sym)
greloc(cur_text_section, pe->sym, ind, R_386_32);
gen_le32(pe->v);
}
 
/* XXX: unify with C code output ? */
static void gen_disp32(ExprValue *pe)
{
Sym *sym;
sym = pe->sym;
if (sym) {
if (sym->r == cur_text_section->sh_num) {
/* same section: we can output an absolute value. Note
that the TCC compiler behaves differently here because
it always outputs a relocation to ease (future) code
elimination in the linker */
gen_le32(pe->v + (long)sym->next - ind - 4);
} else {
greloc(cur_text_section, sym, ind, R_386_PC32);
gen_le32(pe->v - 4);
}
} else {
/* put an empty PC32 relocation */
put_elf_reloc(symtab_section, cur_text_section,
ind, R_386_PC32, 0);
gen_le32(pe->v - 4);
}
}
 
 
static void gen_le16(int v)
{
g(v);
g(v >> 8);
}
 
/* generate the modrm operand */
static inline void asm_modrm(int reg, Operand *op)
{
int mod, reg1, reg2, sib_reg1;
 
if (op->type & (OP_REG | OP_MMX | OP_SSE)) {
g(0xc0 + (reg << 3) + op->reg);
} else if (op->reg == -1 && op->reg2 == -1) {
/* displacement only */
g(0x05 + (reg << 3));
gen_expr32(&op->e);
} else {
sib_reg1 = op->reg;
/* fist compute displacement encoding */
if (sib_reg1 == -1) {
sib_reg1 = 5;
mod = 0x00;
} else if (op->e.v == 0 && !op->e.sym && op->reg != 5) {
mod = 0x00;
} else if (op->e.v == (int8_t)op->e.v && !op->e.sym) {
mod = 0x40;
} else {
mod = 0x80;
}
/* compute if sib byte needed */
reg1 = op->reg;
if (op->reg2 != -1)
reg1 = 4;
g(mod + (reg << 3) + reg1);
if (reg1 == 4) {
/* add sib byte */
reg2 = op->reg2;
if (reg2 == -1)
reg2 = 4; /* indicate no index */
g((op->shift << 6) + (reg2 << 3) + sib_reg1);
}
 
/* add offset */
if (mod == 0x40) {
g(op->e.v);
} else if (mod == 0x80 || op->reg == -1) {
gen_expr32(&op->e);
}
}
}
 
static void asm_opcode(TCCState *s1, int opcode)
{
const ASMInstr *pa;
int i, modrm_index, reg, v, op1, is_short_jmp;
int nb_ops, s, ss;
Operand ops[MAX_OPERANDS], *pop;
int op_type[3]; /* decoded op type */
 
/* get operands */
pop = ops;
nb_ops = 0;
for(;;) {
if (tok == ';' || tok == TOK_LINEFEED)
break;
if (nb_ops >= MAX_OPERANDS) {
error("incorrect number of operands");
}
parse_operand(s1, pop);
pop++;
nb_ops++;
if (tok != ',')
break;
next();
}
 
is_short_jmp = 0;
s = 0; /* avoid warning */
/* optimize matching by using a lookup table (no hashing is needed
!) */
for(pa = asm_instrs; pa->sym != 0; pa++) {
s = 0;
if (pa->instr_type & OPC_FARITH) {
v = opcode - pa->sym;
if (!((unsigned)v < 8 * 6 && (v % 6) == 0))
continue;
} else if (pa->instr_type & OPC_ARITH) {
if (!(opcode >= pa->sym && opcode < pa->sym + 8 * 4))
continue;
goto compute_size;
} else if (pa->instr_type & OPC_SHIFT) {
if (!(opcode >= pa->sym && opcode < pa->sym + 7 * 4))
continue;
goto compute_size;
} else if (pa->instr_type & OPC_TEST) {
if (!(opcode >= pa->sym && opcode < pa->sym + NB_TEST_OPCODES))
continue;
} else if (pa->instr_type & OPC_B) {
if (!(opcode >= pa->sym && opcode <= pa->sym + 3))
continue;
compute_size:
s = (opcode - pa->sym) & 3;
} else if (pa->instr_type & OPC_WL) {
if (!(opcode >= pa->sym && opcode <= pa->sym + 2))
continue;
s = opcode - pa->sym + 1;
} else {
if (pa->sym != opcode)
continue;
}
if (pa->nb_ops != nb_ops)
continue;
/* now decode and check each operand */
for(i = 0; i < nb_ops; i++) {
int op1, op2;
op1 = pa->op_type[i];
op2 = op1 & 0x1f;
switch(op2) {
case OPT_IM:
v = OP_IM8 | OP_IM16 | OP_IM32;
break;
case OPT_REG:
v = OP_REG8 | OP_REG16 | OP_REG32;
break;
case OPT_REGW:
v = OP_REG16 | OP_REG32;
break;
case OPT_IMW:
v = OP_IM16 | OP_IM32;
break;
default:
v = 1 << op2;
break;
}
if (op1 & OPT_EA)
v |= OP_EA;
op_type[i] = v;
if ((ops[i].type & v) == 0)
goto next;
}
/* all is matching ! */
break;
next: ;
}
if (pa->sym == 0) {
if (opcode >= TOK_ASM_pusha && opcode <= TOK_ASM_emms) {
int b;
b = op0_codes[opcode - TOK_ASM_pusha];
if (b & 0xff00)
g(b >> 8);
g(b);
return;
} else {
error("unknown opcode '%s'",
get_tok_str(opcode, NULL));
}
}
/* if the size is unknown, then evaluate it (OPC_B or OPC_WL case) */
if (s == 3) {
for(i = 0; s == 3 && i < nb_ops; i++) {
if ((ops[i].type & OP_REG) && !(op_type[i] & (OP_CL | OP_DX)))
s = reg_to_size[ops[i].type & OP_REG];
}
if (s == 3) {
if ((opcode == TOK_ASM_push || opcode == TOK_ASM_pop) &&
(ops[0].type & (OP_SEG | OP_IM8S | OP_IM32)))
s = 2;
else
error("cannot infer opcode suffix");
}
}
 
/* generate data16 prefix if needed */
ss = s;
if (s == 1 || (pa->instr_type & OPC_D16))
g(WORD_PREFIX_OPCODE);
else if (s == 2)
s = 1;
/* now generates the operation */
if (pa->instr_type & OPC_FWAIT)
g(0x9b);
 
v = pa->opcode;
if (v == 0x69 || v == 0x69) {
/* kludge for imul $im, %reg */
nb_ops = 3;
ops[2] = ops[1];
} else if (v == 0xcd && ops[0].e.v == 3 && !ops[0].e.sym) {
v--; /* int $3 case */
nb_ops = 0;
} else if ((v == 0x06 || v == 0x07)) {
if (ops[0].reg >= 4) {
/* push/pop %fs or %gs */
v = 0x0fa0 + (v - 0x06) + ((ops[0].reg - 4) << 3);
} else {
v += ops[0].reg << 3;
}
nb_ops = 0;
} else if (v <= 0x05) {
/* arith case */
v += ((opcode - TOK_ASM_addb) >> 2) << 3;
} else if ((pa->instr_type & (OPC_FARITH | OPC_MODRM)) == OPC_FARITH) {
/* fpu arith case */
v += ((opcode - pa->sym) / 6) << 3;
}
if (pa->instr_type & OPC_REG) {
for(i = 0; i < nb_ops; i++) {
if (op_type[i] & (OP_REG | OP_ST)) {
v += ops[i].reg;
break;
}
}
/* mov $im, %reg case */
if (pa->opcode == 0xb0 && s >= 1)
v += 7;
}
if (pa->instr_type & OPC_B)
v += s;
if (pa->instr_type & OPC_TEST)
v += test_bits[opcode - pa->sym];
if (pa->instr_type & OPC_SHORTJMP) {
Sym *sym;
int jmp_disp;
 
/* see if we can really generate the jump with a byte offset */
sym = ops[0].e.sym;
if (!sym)
goto no_short_jump;
if (sym->r != cur_text_section->sh_num)
goto no_short_jump;
jmp_disp = ops[0].e.v + (long)sym->next - ind - 2;
if (jmp_disp == (int8_t)jmp_disp) {
/* OK to generate jump */
is_short_jmp = 1;
ops[0].e.v = jmp_disp;
} else {
no_short_jump:
if (pa->instr_type & OPC_JMP) {
/* long jump will be allowed. need to modify the
opcode slightly */
if (v == 0xeb)
v = 0xe9;
else
v += 0x0f10;
} else {
error("invalid displacement");
}
}
}
op1 = v >> 8;
if (op1)
g(op1);
g(v);
/* search which operand will used for modrm */
modrm_index = 0;
if (pa->instr_type & OPC_SHIFT) {
reg = (opcode - pa->sym) >> 2;
if (reg == 6)
reg = 7;
} else if (pa->instr_type & OPC_ARITH) {
reg = (opcode - pa->sym) >> 2;
} else if (pa->instr_type & OPC_FARITH) {
reg = (opcode - pa->sym) / 6;
} else {
reg = (pa->instr_type >> OPC_GROUP_SHIFT) & 7;
}
if (pa->instr_type & OPC_MODRM) {
/* first look for an ea operand */
for(i = 0;i < nb_ops; i++) {
if (op_type[i] & OP_EA)
goto modrm_found;
}
/* then if not found, a register or indirection (shift instructions) */
for(i = 0;i < nb_ops; i++) {
if (op_type[i] & (OP_REG | OP_MMX | OP_SSE | OP_INDIR))
goto modrm_found;
}
#ifdef ASM_DEBUG
error("bad op table");
#endif
modrm_found:
modrm_index = i;
/* if a register is used in another operand then it is
used instead of group */
for(i = 0;i < nb_ops; i++) {
v = op_type[i];
if (i != modrm_index &&
(v & (OP_REG | OP_MMX | OP_SSE | OP_CR | OP_TR | OP_DB | OP_SEG))) {
reg = ops[i].reg;
break;
}
}
 
asm_modrm(reg, &ops[modrm_index]);
}
 
/* emit constants */
if (pa->opcode == 0x9a || pa->opcode == 0xea) {
/* ljmp or lcall kludge */
gen_expr32(&ops[1].e);
if (ops[0].e.sym)
error("cannot relocate");
gen_le16(ops[0].e.v);
} else {
for(i = 0;i < nb_ops; i++) {
v = op_type[i];
if (v & (OP_IM8 | OP_IM16 | OP_IM32 | OP_IM8S | OP_ADDR)) {
/* if multiple sizes are given it means we must look
at the op size */
if (v == (OP_IM8 | OP_IM16 | OP_IM32) ||
v == (OP_IM16 | OP_IM32)) {
if (ss == 0)
v = OP_IM8;
else if (ss == 1)
v = OP_IM16;
else
v = OP_IM32;
}
if (v & (OP_IM8 | OP_IM8S)) {
if (ops[i].e.sym)
goto error_relocate;
g(ops[i].e.v);
} else if (v & OP_IM16) {
if (ops[i].e.sym) {
error_relocate:
error("cannot relocate");
}
gen_le16(ops[i].e.v);
} else {
if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) {
if (is_short_jmp)
g(ops[i].e.v);
else
gen_disp32(&ops[i].e);
} else {
gen_expr32(&ops[i].e);
}
}
}
}
}
}
 
#define NB_SAVED_REGS 3
#define NB_ASM_REGS 8
 
/* return the constraint priority (we allocate first the lowest
numbered constraints) */
static inline int constraint_priority(const char *str)
{
int priority, c, pr;
 
/* we take the lowest priority */
priority = 0;
for(;;) {
c = *str;
if (c == '\0')
break;
str++;
switch(c) {
case 'A':
pr = 0;
break;
case 'a':
case 'b':
case 'c':
case 'd':
case 'S':
case 'D':
pr = 1;
break;
case 'q':
pr = 2;
break;
case 'r':
pr = 3;
break;
case 'N':
case 'M':
case 'I':
case 'i':
case 'm':
case 'g':
pr = 4;
break;
default:
error("unknown constraint '%c'", c);
pr = 0;
}
if (pr > priority)
priority = pr;
}
return priority;
}
 
static const char *skip_constraint_modifiers(const char *p)
{
while (*p == '=' || *p == '&' || *p == '+' || *p == '%')
p++;
return p;
}
 
#define REG_OUT_MASK 0x01
#define REG_IN_MASK 0x02
 
#define is_reg_allocated(reg) (regs_allocated[reg] & reg_mask)
 
static void asm_compute_constraints(ASMOperand *operands,
int nb_operands, int nb_outputs,
const uint8_t *clobber_regs,
int *pout_reg)
{
ASMOperand *op;
int sorted_op[MAX_ASM_OPERANDS];
int i, j, k, p1, p2, tmp, reg, c, reg_mask;
const char *str;
uint8_t regs_allocated[NB_ASM_REGS];
/* init fields */
for(i=0;i<nb_operands;i++) {
op = &operands[i];
op->input_index = -1;
op->ref_index = -1;
op->reg = -1;
op->is_memory = 0;
op->is_rw = 0;
}
/* compute constraint priority and evaluate references to output
constraints if input constraints */
for(i=0;i<nb_operands;i++) {
op = &operands[i];
str = op->constraint;
str = skip_constraint_modifiers(str);
if (isnum(*str) || *str == '[') {
/* this is a reference to another constraint */
k = find_constraint(operands, nb_operands, str, NULL);
if ((unsigned)k >= i || i < nb_outputs)
error("invalid reference in constraint %d ('%s')",
i, str);
op->ref_index = k;
if (operands[k].input_index >= 0)
error("cannot reference twice the same operand");
operands[k].input_index = i;
op->priority = 5;
} else {
op->priority = constraint_priority(str);
}
}
/* sort operands according to their priority */
for(i=0;i<nb_operands;i++)
sorted_op[i] = i;
for(i=0;i<nb_operands - 1;i++) {
for(j=i+1;j<nb_operands;j++) {
p1 = operands[sorted_op[i]].priority;
p2 = operands[sorted_op[j]].priority;
if (p2 < p1) {
tmp = sorted_op[i];
sorted_op[i] = sorted_op[j];
sorted_op[j] = tmp;
}
}
}
 
for(i = 0;i < NB_ASM_REGS; i++) {
if (clobber_regs[i])
regs_allocated[i] = REG_IN_MASK | REG_OUT_MASK;
else
regs_allocated[i] = 0;
}
/* esp cannot be used */
regs_allocated[4] = REG_IN_MASK | REG_OUT_MASK;
/* ebp cannot be used yet */
regs_allocated[5] = REG_IN_MASK | REG_OUT_MASK;
 
/* allocate registers and generate corresponding asm moves */
for(i=0;i<nb_operands;i++) {
j = sorted_op[i];
op = &operands[j];
str = op->constraint;
/* no need to allocate references */
if (op->ref_index >= 0)
continue;
/* select if register is used for output, input or both */
if (op->input_index >= 0) {
reg_mask = REG_IN_MASK | REG_OUT_MASK;
} else if (j < nb_outputs) {
reg_mask = REG_OUT_MASK;
} else {
reg_mask = REG_IN_MASK;
}
try_next:
c = *str++;
switch(c) {
case '=':
goto try_next;
case '+':
op->is_rw = 1;
/* FALL THRU */
case '&':
if (j >= nb_outputs)
error("'%c' modifier can only be applied to outputs", c);
reg_mask = REG_IN_MASK | REG_OUT_MASK;
goto try_next;
case 'A':
/* allocate both eax and edx */
if (is_reg_allocated(TREG_EAX) ||
is_reg_allocated(TREG_EDX))
goto try_next;
op->is_llong = 1;
op->reg = TREG_EAX;
regs_allocated[TREG_EAX] |= reg_mask;
regs_allocated[TREG_EDX] |= reg_mask;
break;
case 'a':
reg = TREG_EAX;
goto alloc_reg;
case 'b':
reg = 3;
goto alloc_reg;
case 'c':
reg = TREG_ECX;
goto alloc_reg;
case 'd':
reg = TREG_EDX;
goto alloc_reg;
case 'S':
reg = 6;
goto alloc_reg;
case 'D':
reg = 7;
alloc_reg:
if (is_reg_allocated(reg))
goto try_next;
goto reg_found;
case 'q':
/* eax, ebx, ecx or edx */
for(reg = 0; reg < 4; reg++) {
if (!is_reg_allocated(reg))
goto reg_found;
}
goto try_next;
case 'r':
/* any general register */
for(reg = 0; reg < 8; reg++) {
if (!is_reg_allocated(reg))
goto reg_found;
}
goto try_next;
reg_found:
/* now we can reload in the register */
op->is_llong = 0;
op->reg = reg;
regs_allocated[reg] |= reg_mask;
break;
case 'i':
if (!((op->vt->r & (VT_VALMASK | VT_LVAL)) == VT_CONST))
goto try_next;
break;
case 'I':
case 'N':
case 'M':
if (!((op->vt->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST))
goto try_next;
break;
case 'm':
case 'g':
/* nothing special to do because the operand is already in
memory, except if the pointer itself is stored in a
memory variable (VT_LLOCAL case) */
/* XXX: fix constant case */
/* if it is a reference to a memory zone, it must lie
in a register, so we reserve the register in the
input registers and a load will be generated
later */
if (j < nb_outputs || c == 'm') {
if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
/* any general register */
for(reg = 0; reg < 8; reg++) {
if (!(regs_allocated[reg] & REG_IN_MASK))
goto reg_found1;
}
goto try_next;
reg_found1:
/* now we can reload in the register */
regs_allocated[reg] |= REG_IN_MASK;
op->reg = reg;
op->is_memory = 1;
}
}
break;
default:
error("asm constraint %d ('%s') could not be satisfied",
j, op->constraint);
break;
}
/* if a reference is present for that operand, we assign it too */
if (op->input_index >= 0) {
operands[op->input_index].reg = op->reg;
operands[op->input_index].is_llong = op->is_llong;
}
}
/* compute out_reg. It is used to store outputs registers to memory
locations references by pointers (VT_LLOCAL case) */
*pout_reg = -1;
for(i=0;i<nb_operands;i++) {
op = &operands[i];
if (op->reg >= 0 &&
(op->vt->r & VT_VALMASK) == VT_LLOCAL &&
!op->is_memory) {
for(reg = 0; reg < 8; reg++) {
if (!(regs_allocated[reg] & REG_OUT_MASK))
goto reg_found2;
}
error("could not find free output register for reloading");
reg_found2:
*pout_reg = reg;
break;
}
}
/* print sorted constraints */
#ifdef ASM_DEBUG
for(i=0;i<nb_operands;i++) {
j = sorted_op[i];
op = &operands[j];
printf("%%%d [%s]: \"%s\" r=0x%04x reg=%d\n",
j,
op->id ? get_tok_str(op->id, NULL) : "",
op->constraint,
op->vt->r,
op->reg);
}
if (*pout_reg >= 0)
printf("out_reg=%d\n", *pout_reg);
#endif
}
 
static void subst_asm_operand(CString *add_str,
SValue *sv, int modifier)
{
int r, reg, size, val;
char buf[64];
 
r = sv->r;
if ((r & VT_VALMASK) == VT_CONST) {
if (!(r & VT_LVAL) && modifier != 'c' && modifier != 'n')
cstr_ccat(add_str, '$');
if (r & VT_SYM) {
cstr_cat(add_str, get_tok_str(sv->sym->v, NULL));
if (sv->c.i != 0) {
cstr_ccat(add_str, '+');
} else {
return;
}
}
val = sv->c.i;
if (modifier == 'n')
val = -val;
snprintf(buf, sizeof(buf), "%d", sv->c.i);
cstr_cat(add_str, buf);
} else if ((r & VT_VALMASK) == VT_LOCAL) {
snprintf(buf, sizeof(buf), "%d(%%ebp)", sv->c.i);
cstr_cat(add_str, buf);
} else if (r & VT_LVAL) {
reg = r & VT_VALMASK;
if (reg >= VT_CONST)
error("internal compiler error");
snprintf(buf, sizeof(buf), "(%%%s)",
get_tok_str(TOK_ASM_eax + reg, NULL));
cstr_cat(add_str, buf);
} else {
/* register case */
reg = r & VT_VALMASK;
if (reg >= VT_CONST)
error("internal compiler error");
 
/* choose register operand size */
if ((sv->type.t & VT_BTYPE) == VT_BYTE)
size = 1;
else if ((sv->type.t & VT_BTYPE) == VT_SHORT)
size = 2;
else
size = 4;
if (size == 1 && reg >= 4)
size = 4;
 
if (modifier == 'b') {
if (reg >= 4)
error("cannot use byte register");
size = 1;
} else if (modifier == 'h') {
if (reg >= 4)
error("cannot use byte register");
size = -1;
} else if (modifier == 'w') {
size = 2;
}
 
switch(size) {
case -1:
reg = TOK_ASM_ah + reg;
break;
case 1:
reg = TOK_ASM_al + reg;
break;
case 2:
reg = TOK_ASM_ax + reg;
break;
default:
reg = TOK_ASM_eax + reg;
break;
}
snprintf(buf, sizeof(buf), "%%%s", get_tok_str(reg, NULL));
cstr_cat(add_str, buf);
}
}
 
/* generate prolog and epilog code for asm statment */
static void asm_gen_code(ASMOperand *operands, int nb_operands,
int nb_outputs, int is_output,
uint8_t *clobber_regs,
int out_reg)
{
uint8_t regs_allocated[NB_ASM_REGS];
ASMOperand *op;
int i, reg;
static uint8_t reg_saved[NB_SAVED_REGS] = { 3, 6, 7 };
 
/* mark all used registers */
memcpy(regs_allocated, clobber_regs, sizeof(regs_allocated));
for(i = 0; i < nb_operands;i++) {
op = &operands[i];
if (op->reg >= 0)
regs_allocated[op->reg] = 1;
}
if (!is_output) {
/* generate reg save code */
for(i = 0; i < NB_SAVED_REGS; i++) {
reg = reg_saved[i];
if (regs_allocated[reg])
g(0x50 + reg);
}
 
/* generate load code */
for(i = 0; i < nb_operands; i++) {
op = &operands[i];
if (op->reg >= 0) {
if ((op->vt->r & VT_VALMASK) == VT_LLOCAL &&
op->is_memory) {
/* memory reference case (for both input and
output cases) */
SValue sv;
sv = *op->vt;
sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
load(op->reg, &sv);
} else if (i >= nb_outputs || op->is_rw) {
/* load value in register */
load(op->reg, op->vt);
if (op->is_llong) {
SValue sv;
sv = *op->vt;
sv.c.ul += 4;
load(TREG_EDX, &sv);
}
}
}
}
} else {
/* generate save code */
for(i = 0 ; i < nb_outputs; i++) {
op = &operands[i];
if (op->reg >= 0) {
if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
if (!op->is_memory) {
SValue sv;
sv = *op->vt;
sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
load(out_reg, &sv);
 
sv.r = (sv.r & ~VT_VALMASK) | out_reg;
store(op->reg, &sv);
}
} else {
store(op->reg, op->vt);
if (op->is_llong) {
SValue sv;
sv = *op->vt;
sv.c.ul += 4;
store(TREG_EDX, &sv);
}
}
}
}
/* generate reg restore code */
for(i = NB_SAVED_REGS - 1; i >= 0; i--) {
reg = reg_saved[i];
if (regs_allocated[reg])
g(0x58 + reg);
}
}
}
 
static void asm_clobber(uint8_t *clobber_regs, const char *str)
{
int reg;
TokenSym *ts;
 
if (!strcmp(str, "memory") ||
!strcmp(str, "cc"))
return;
ts = tok_alloc(str, strlen(str));
reg = ts->tok;
if (reg >= TOK_ASM_eax && reg <= TOK_ASM_edi) {
reg -= TOK_ASM_eax;
} else if (reg >= TOK_ASM_ax && reg <= TOK_ASM_di) {
reg -= TOK_ASM_ax;
} else {
error("invalid clobber register '%s'", str);
}
clobber_regs[reg] = 1;
}
/programs/develop/metcc/trunk/source/i386-asm.h
0,0 → 1,446
DEF_ASM_OP0(pusha, 0x60) /* must be first OP0 */
DEF_ASM_OP0(popa, 0x61)
DEF_ASM_OP0(clc, 0xf8)
DEF_ASM_OP0(cld, 0xfc)
DEF_ASM_OP0(cli, 0xfa)
DEF_ASM_OP0(clts, 0x0f06)
DEF_ASM_OP0(cmc, 0xf5)
DEF_ASM_OP0(lahf, 0x9f)
DEF_ASM_OP0(sahf, 0x9e)
DEF_ASM_OP0(pushfl, 0x9c)
DEF_ASM_OP0(popfl, 0x9d)
DEF_ASM_OP0(pushf, 0x9c)
DEF_ASM_OP0(popf, 0x9d)
DEF_ASM_OP0(stc, 0xf9)
DEF_ASM_OP0(std, 0xfd)
DEF_ASM_OP0(sti, 0xfb)
DEF_ASM_OP0(aaa, 0x37)
DEF_ASM_OP0(aas, 0x3f)
DEF_ASM_OP0(daa, 0x27)
DEF_ASM_OP0(das, 0x2f)
DEF_ASM_OP0(aad, 0xd50a)
DEF_ASM_OP0(aam, 0xd40a)
DEF_ASM_OP0(cbw, 0x6698)
DEF_ASM_OP0(cwd, 0x6699)
DEF_ASM_OP0(cwde, 0x98)
DEF_ASM_OP0(cdq, 0x99)
DEF_ASM_OP0(cbtw, 0x6698)
DEF_ASM_OP0(cwtl, 0x98)
DEF_ASM_OP0(cwtd, 0x6699)
DEF_ASM_OP0(cltd, 0x99)
DEF_ASM_OP0(int3, 0xcc)
DEF_ASM_OP0(into, 0xce)
DEF_ASM_OP0(iret, 0xcf)
DEF_ASM_OP0(rsm, 0x0faa)
DEF_ASM_OP0(hlt, 0xf4)
DEF_ASM_OP0(wait, 0x9b)
DEF_ASM_OP0(nop, 0x90)
DEF_ASM_OP0(xlat, 0xd7)
 
/* strings */
ALT(DEF_ASM_OP0L(cmpsb, 0xa6, 0, OPC_BWL))
ALT(DEF_ASM_OP0L(scmpb, 0xa6, 0, OPC_BWL))
 
ALT(DEF_ASM_OP0L(insb, 0x6c, 0, OPC_BWL))
ALT(DEF_ASM_OP0L(outsb, 0x6e, 0, OPC_BWL))
 
ALT(DEF_ASM_OP0L(lodsb, 0xac, 0, OPC_BWL))
ALT(DEF_ASM_OP0L(slodb, 0xac, 0, OPC_BWL))
 
ALT(DEF_ASM_OP0L(movsb, 0xa4, 0, OPC_BWL))
ALT(DEF_ASM_OP0L(smovb, 0xa4, 0, OPC_BWL))
 
ALT(DEF_ASM_OP0L(scasb, 0xae, 0, OPC_BWL))
ALT(DEF_ASM_OP0L(sscab, 0xae, 0, OPC_BWL))
 
ALT(DEF_ASM_OP0L(stosb, 0xaa, 0, OPC_BWL))
ALT(DEF_ASM_OP0L(sstob, 0xaa, 0, OPC_BWL))
 
/* bits */
ALT(DEF_ASM_OP2(bsfw, 0x0fbc, 0, OPC_MODRM | OPC_WL, OPT_REGW | OPT_EA, OPT_REGW))
ALT(DEF_ASM_OP2(bsrw, 0x0fbd, 0, OPC_MODRM | OPC_WL, OPT_REGW | OPT_EA, OPT_REGW))
 
ALT(DEF_ASM_OP2(btw, 0x0fa3, 0, OPC_MODRM | OPC_WL, OPT_REGW, OPT_REGW | OPT_EA))
ALT(DEF_ASM_OP2(btw, 0x0fba, 4, OPC_MODRM | OPC_WL, OPT_IM8, OPT_REGW | OPT_EA))
 
ALT(DEF_ASM_OP2(btsw, 0x0fab, 0, OPC_MODRM | OPC_WL, OPT_REGW, OPT_REGW | OPT_EA))
ALT(DEF_ASM_OP2(btsw, 0x0fba, 5, OPC_MODRM | OPC_WL, OPT_IM8, OPT_REGW | OPT_EA))
 
ALT(DEF_ASM_OP2(btrw, 0x0fb3, 0, OPC_MODRM | OPC_WL, OPT_REGW, OPT_REGW | OPT_EA))
ALT(DEF_ASM_OP2(btrw, 0x0fba, 6, OPC_MODRM | OPC_WL, OPT_IM8, OPT_REGW | OPT_EA))
 
ALT(DEF_ASM_OP2(btcw, 0x0fbb, 0, OPC_MODRM | OPC_WL, OPT_REGW, OPT_REGW | OPT_EA))
ALT(DEF_ASM_OP2(btcw, 0x0fba, 7, OPC_MODRM | OPC_WL, OPT_IM8, OPT_REGW | OPT_EA))
 
/* prefixes */
DEF_ASM_OP0(aword, 0x67)
DEF_ASM_OP0(addr16, 0x67)
DEF_ASM_OP0(word, 0x66)
DEF_ASM_OP0(data16, 0x66)
DEF_ASM_OP0(lock, 0xf0)
DEF_ASM_OP0(rep, 0xf3)
DEF_ASM_OP0(repe, 0xf3)
DEF_ASM_OP0(repz, 0xf3)
DEF_ASM_OP0(repne, 0xf2)
DEF_ASM_OP0(repnz, 0xf2)
DEF_ASM_OP0(invd, 0x0f08)
DEF_ASM_OP0(wbinvd, 0x0f09)
DEF_ASM_OP0(cpuid, 0x0fa2)
DEF_ASM_OP0(wrmsr, 0x0f30)
DEF_ASM_OP0(rdtsc, 0x0f31)
DEF_ASM_OP0(rdmsr, 0x0f32)
DEF_ASM_OP0(rdpmc, 0x0f33)
DEF_ASM_OP0(ud2, 0x0f0b)
 
/* NOTE: we took the same order as gas opcode definition order */
ALT(DEF_ASM_OP2(movb, 0xa0, 0, OPC_BWL, OPT_ADDR, OPT_EAX))
ALT(DEF_ASM_OP2(movb, 0xa2, 0, OPC_BWL, OPT_EAX, OPT_ADDR))
ALT(DEF_ASM_OP2(movb, 0x88, 0, OPC_MODRM | OPC_BWL, OPT_REG, OPT_EA | OPT_REG))
ALT(DEF_ASM_OP2(movb, 0x8a, 0, OPC_MODRM | OPC_BWL, OPT_EA | OPT_REG, OPT_REG))
ALT(DEF_ASM_OP2(movb, 0xb0, 0, OPC_REG | OPC_BWL, OPT_IM, OPT_REG))
ALT(DEF_ASM_OP2(movb, 0xc6, 0, OPC_MODRM | OPC_BWL, OPT_IM, OPT_REG | OPT_EA))
 
ALT(DEF_ASM_OP2(movw, 0x8c, 0, OPC_MODRM | OPC_WL, OPT_SEG, OPT_EA | OPT_REG))
ALT(DEF_ASM_OP2(movw, 0x8e, 0, OPC_MODRM | OPC_WL, OPT_EA | OPT_REG, OPT_SEG))
 
ALT(DEF_ASM_OP2(movw, 0x0f20, 0, OPC_MODRM | OPC_WL, OPT_CR, OPT_REG32))
ALT(DEF_ASM_OP2(movw, 0x0f21, 0, OPC_MODRM | OPC_WL, OPT_DB, OPT_REG32))
ALT(DEF_ASM_OP2(movw, 0x0f24, 0, OPC_MODRM | OPC_WL, OPT_TR, OPT_REG32))
ALT(DEF_ASM_OP2(movw, 0x0f22, 0, OPC_MODRM | OPC_WL, OPT_REG32, OPT_CR))
ALT(DEF_ASM_OP2(movw, 0x0f23, 0, OPC_MODRM | OPC_WL, OPT_REG32, OPT_DB))
ALT(DEF_ASM_OP2(movw, 0x0f26, 0, OPC_MODRM | OPC_WL, OPT_REG32, OPT_TR))
 
ALT(DEF_ASM_OP2(movsbl, 0x0fbe, 0, OPC_MODRM, OPT_REG8 | OPT_EA, OPT_REG32))
ALT(DEF_ASM_OP2(movsbw, 0x0fbe, 0, OPC_MODRM | OPC_D16, OPT_REG8 | OPT_EA, OPT_REG16))
ALT(DEF_ASM_OP2(movswl, 0x0fbf, 0, OPC_MODRM, OPT_REG16 | OPT_EA, OPT_REG32))
ALT(DEF_ASM_OP2(movzbw, 0x0fb6, 0, OPC_MODRM | OPC_WL, OPT_REG8 | OPT_EA, OPT_REGW))
ALT(DEF_ASM_OP2(movzwl, 0x0fb7, 0, OPC_MODRM, OPT_REG16 | OPT_EA, OPT_REG32))
 
ALT(DEF_ASM_OP1(pushw, 0x50, 0, OPC_REG | OPC_WL, OPT_REGW))
ALT(DEF_ASM_OP1(pushw, 0xff, 6, OPC_MODRM | OPC_WL, OPT_REGW | OPT_EA))
ALT(DEF_ASM_OP1(pushw, 0x6a, 0, OPC_WL, OPT_IM8S))
ALT(DEF_ASM_OP1(pushw, 0x68, 0, OPC_WL, OPT_IM32))
ALT(DEF_ASM_OP1(pushw, 0x06, 0, OPC_WL, OPT_SEG))
 
ALT(DEF_ASM_OP1(popw, 0x58, 0, OPC_REG | OPC_WL, OPT_REGW))
ALT(DEF_ASM_OP1(popw, 0x8f, 0, OPC_MODRM | OPC_WL, OPT_REGW | OPT_EA))
ALT(DEF_ASM_OP1(popw, 0x07, 0, OPC_WL, OPT_SEG))
 
ALT(DEF_ASM_OP2(xchgw, 0x90, 0, OPC_REG | OPC_WL, OPT_REG, OPT_EAX))
ALT(DEF_ASM_OP2(xchgw, 0x90, 0, OPC_REG | OPC_WL, OPT_EAX, OPT_REG))
ALT(DEF_ASM_OP2(xchgb, 0x86, 0, OPC_MODRM | OPC_BWL, OPT_REG, OPT_EA | OPT_REG))
ALT(DEF_ASM_OP2(xchgb, 0x86, 0, OPC_MODRM | OPC_BWL, OPT_EA | OPT_REG, OPT_REG))
 
ALT(DEF_ASM_OP2(inb, 0xe4, 0, OPC_BWL, OPT_IM8, OPT_EAX))
ALT(DEF_ASM_OP1(inb, 0xe4, 0, OPC_BWL, OPT_IM8))
ALT(DEF_ASM_OP2(inb, 0xec, 0, OPC_BWL, OPT_DX, OPT_EAX))
ALT(DEF_ASM_OP1(inb, 0xec, 0, OPC_BWL, OPT_DX))
 
ALT(DEF_ASM_OP2(outb, 0xe6, 0, OPC_BWL, OPT_EAX, OPT_IM8))
ALT(DEF_ASM_OP1(outb, 0xe6, 0, OPC_BWL, OPT_IM8))
ALT(DEF_ASM_OP2(outb, 0xee, 0, OPC_BWL, OPT_EAX, OPT_DX))
ALT(DEF_ASM_OP1(outb, 0xee, 0, OPC_BWL, OPT_DX))
 
ALT(DEF_ASM_OP2(leaw, 0x8d, 0, OPC_MODRM | OPC_WL, OPT_EA, OPT_REG))
 
ALT(DEF_ASM_OP2(les, 0xc4, 0, OPC_MODRM, OPT_EA, OPT_REG32))
ALT(DEF_ASM_OP2(lds, 0xc5, 0, OPC_MODRM, OPT_EA, OPT_REG32))
ALT(DEF_ASM_OP2(lss, 0x0fb2, 0, OPC_MODRM, OPT_EA, OPT_REG32))
ALT(DEF_ASM_OP2(lfs, 0x0fb4, 0, OPC_MODRM, OPT_EA, OPT_REG32))
ALT(DEF_ASM_OP2(lgs, 0x0fb5, 0, OPC_MODRM, OPT_EA, OPT_REG32))
 
/* arith */
ALT(DEF_ASM_OP2(addb, 0x00, 0, OPC_ARITH | OPC_MODRM | OPC_BWL, OPT_REG, OPT_EA | OPT_REG)) /* XXX: use D bit ? */
ALT(DEF_ASM_OP2(addb, 0x02, 0, OPC_ARITH | OPC_MODRM | OPC_BWL, OPT_EA | OPT_REG, OPT_REG))
ALT(DEF_ASM_OP2(addb, 0x04, 0, OPC_ARITH | OPC_BWL, OPT_IM, OPT_EAX))
ALT(DEF_ASM_OP2(addb, 0x80, 0, OPC_ARITH | OPC_MODRM | OPC_BWL, OPT_IM, OPT_EA | OPT_REG))
ALT(DEF_ASM_OP2(addw, 0x83, 0, OPC_ARITH | OPC_MODRM | OPC_WL, OPT_IM8S, OPT_EA | OPT_REG))
 
ALT(DEF_ASM_OP2(testb, 0x84, 0, OPC_MODRM | OPC_BWL, OPT_EA | OPT_REG, OPT_REG))
ALT(DEF_ASM_OP2(testb, 0x84, 0, OPC_MODRM | OPC_BWL, OPT_REG, OPT_EA | OPT_REG))
ALT(DEF_ASM_OP2(testb, 0xa8, 0, OPC_BWL, OPT_IM, OPT_EAX))
ALT(DEF_ASM_OP2(testb, 0xf6, 0, OPC_MODRM | OPC_BWL, OPT_IM, OPT_EA | OPT_REG))
 
ALT(DEF_ASM_OP1(incw, 0x40, 0, OPC_REG | OPC_WL, OPT_REGW))
ALT(DEF_ASM_OP1(incb, 0xfe, 0, OPC_MODRM | OPC_BWL, OPT_REG | OPT_EA))
ALT(DEF_ASM_OP1(decw, 0x48, 0, OPC_REG | OPC_WL, OPT_REGW))
ALT(DEF_ASM_OP1(decb, 0xfe, 1, OPC_MODRM | OPC_BWL, OPT_REG | OPT_EA))
 
ALT(DEF_ASM_OP1(notb, 0xf6, 2, OPC_MODRM | OPC_BWL, OPT_REG | OPT_EA))
ALT(DEF_ASM_OP1(negb, 0xf6, 3, OPC_MODRM | OPC_BWL, OPT_REG | OPT_EA))
 
ALT(DEF_ASM_OP1(mulb, 0xf6, 4, OPC_MODRM | OPC_BWL, OPT_REG | OPT_EA))
ALT(DEF_ASM_OP1(imulb, 0xf6, 5, OPC_MODRM | OPC_BWL, OPT_REG | OPT_EA))
 
ALT(DEF_ASM_OP2(imulw, 0x0faf, 0, OPC_MODRM | OPC_WL, OPT_REG | OPT_EA, OPT_REG))
ALT(DEF_ASM_OP3(imulw, 0x6b, 0, OPC_MODRM | OPC_WL, OPT_IM8S, OPT_REGW | OPT_EA, OPT_REGW))
ALT(DEF_ASM_OP2(imulw, 0x6b, 0, OPC_MODRM | OPC_WL, OPT_IM8S, OPT_REGW))
ALT(DEF_ASM_OP3(imulw, 0x69, 0, OPC_MODRM | OPC_WL, OPT_IMW, OPT_REGW | OPT_EA, OPT_REGW))
ALT(DEF_ASM_OP2(imulw, 0x69, 0, OPC_MODRM | OPC_WL, OPT_IMW, OPT_REGW))
 
ALT(DEF_ASM_OP1(divb, 0xf6, 6, OPC_MODRM | OPC_BWL, OPT_REG | OPT_EA))
ALT(DEF_ASM_OP2(divb, 0xf6, 6, OPC_MODRM | OPC_BWL, OPT_REG | OPT_EA, OPT_EAX))
ALT(DEF_ASM_OP1(idivb, 0xf6, 7, OPC_MODRM | OPC_BWL, OPT_REG | OPT_EA))
ALT(DEF_ASM_OP2(idivb, 0xf6, 7, OPC_MODRM | OPC_BWL, OPT_REG | OPT_EA, OPT_EAX))
 
/* shifts */
ALT(DEF_ASM_OP2(rolb, 0xc0, 0, OPC_MODRM | OPC_BWL | OPC_SHIFT, OPT_IM8, OPT_EA | OPT_REG))
ALT(DEF_ASM_OP2(rolb, 0xd2, 0, OPC_MODRM | OPC_BWL | OPC_SHIFT, OPT_CL, OPT_EA | OPT_REG))
ALT(DEF_ASM_OP1(rolb, 0xd0, 0, OPC_MODRM | OPC_BWL | OPC_SHIFT, OPT_EA | OPT_REG))
 
ALT(DEF_ASM_OP3(shldw, 0x0fa4, 0, OPC_MODRM | OPC_WL, OPT_IM8, OPT_REGW, OPT_EA | OPT_REGW))
ALT(DEF_ASM_OP3(shldw, 0x0fa5, 0, OPC_MODRM | OPC_WL, OPT_CL, OPT_REGW, OPT_EA | OPT_REGW))
ALT(DEF_ASM_OP2(shldw, 0x0fa5, 0, OPC_MODRM | OPC_WL, OPT_REGW, OPT_EA | OPT_REGW))
ALT(DEF_ASM_OP3(shrdw, 0x0fac, 0, OPC_MODRM | OPC_WL, OPT_IM8, OPT_REGW, OPT_EA | OPT_REGW))
ALT(DEF_ASM_OP3(shrdw, 0x0fad, 0, OPC_MODRM | OPC_WL, OPT_CL, OPT_REGW, OPT_EA | OPT_REGW))
ALT(DEF_ASM_OP2(shrdw, 0x0fad, 0, OPC_MODRM | OPC_WL, OPT_REGW, OPT_EA | OPT_REGW))
 
ALT(DEF_ASM_OP1(call, 0xff, 2, OPC_MODRM, OPT_INDIR))
ALT(DEF_ASM_OP1(call, 0xe8, 0, OPC_JMP, OPT_ADDR))
ALT(DEF_ASM_OP1(jmp, 0xff, 4, OPC_MODRM, OPT_INDIR))
ALT(DEF_ASM_OP1(jmp, 0xeb, 0, OPC_SHORTJMP | OPC_JMP, OPT_ADDR))
 
ALT(DEF_ASM_OP2(lcall, 0x9a, 0, 0, OPT_IM16, OPT_IM32))
ALT(DEF_ASM_OP1(lcall, 0xff, 3, 0, OPT_EA))
ALT(DEF_ASM_OP2(ljmp, 0xea, 0, 0, OPT_IM16, OPT_IM32))
ALT(DEF_ASM_OP1(ljmp, 0xff, 5, 0, OPT_EA))
 
ALT(DEF_ASM_OP1(int, 0xcd, 0, 0, OPT_IM8))
ALT(DEF_ASM_OP1(seto, 0x0f90, 0, OPC_MODRM | OPC_TEST, OPT_REG8 | OPT_EA))
DEF_ASM_OP2(enter, 0xc8, 0, 0, OPT_IM16, OPT_IM8)
DEF_ASM_OP0(leave, 0xc9)
DEF_ASM_OP0(ret, 0xc3)
ALT(DEF_ASM_OP1(ret, 0xc2, 0, 0, OPT_IM16))
DEF_ASM_OP0(lret, 0xcb)
ALT(DEF_ASM_OP1(lret, 0xca, 0, 0, OPT_IM16))
 
ALT(DEF_ASM_OP1(jo, 0x70, 0, OPC_SHORTJMP | OPC_JMP | OPC_TEST, OPT_ADDR))
DEF_ASM_OP1(loopne, 0xe0, 0, OPC_SHORTJMP, OPT_ADDR)
DEF_ASM_OP1(loopnz, 0xe0, 0, OPC_SHORTJMP, OPT_ADDR)
DEF_ASM_OP1(loope, 0xe1, 0, OPC_SHORTJMP, OPT_ADDR)
DEF_ASM_OP1(loopz, 0xe1, 0, OPC_SHORTJMP, OPT_ADDR)
DEF_ASM_OP1(loop, 0xe2, 0, OPC_SHORTJMP, OPT_ADDR)
DEF_ASM_OP1(jecxz, 0xe3, 0, OPC_SHORTJMP, OPT_ADDR)
/* float */
/* specific fcomp handling */
ALT(DEF_ASM_OP0L(fcomp, 0xd8d9, 0, 0))
 
ALT(DEF_ASM_OP1(fadd, 0xd8c0, 0, OPC_FARITH | OPC_REG, OPT_ST))
ALT(DEF_ASM_OP2(fadd, 0xd8c0, 0, OPC_FARITH | OPC_REG, OPT_ST, OPT_ST0))
ALT(DEF_ASM_OP0L(fadd, 0xdec1, 0, OPC_FARITH))
ALT(DEF_ASM_OP1(faddp, 0xdec0, 0, OPC_FARITH | OPC_REG, OPT_ST))
ALT(DEF_ASM_OP2(faddp, 0xdec0, 0, OPC_FARITH | OPC_REG, OPT_ST, OPT_ST0))
ALT(DEF_ASM_OP2(faddp, 0xdec0, 0, OPC_FARITH | OPC_REG, OPT_ST0, OPT_ST))
ALT(DEF_ASM_OP0L(faddp, 0xdec1, 0, OPC_FARITH))
ALT(DEF_ASM_OP1(fadds, 0xd8, 0, OPC_FARITH | OPC_MODRM, OPT_EA))
ALT(DEF_ASM_OP1(fiaddl, 0xda, 0, OPC_FARITH | OPC_MODRM, OPT_EA))
ALT(DEF_ASM_OP1(faddl, 0xdc, 0, OPC_FARITH | OPC_MODRM, OPT_EA))
ALT(DEF_ASM_OP1(fiadds, 0xde, 0, OPC_FARITH | OPC_MODRM, OPT_EA))
 
DEF_ASM_OP0(fucompp, 0xdae9)
DEF_ASM_OP0(ftst, 0xd9e4)
DEF_ASM_OP0(fxam, 0xd9e5)
DEF_ASM_OP0(fld1, 0xd9e8)
DEF_ASM_OP0(fldl2t, 0xd9e9)
DEF_ASM_OP0(fldl2e, 0xd9ea)
DEF_ASM_OP0(fldpi, 0xd9eb)
DEF_ASM_OP0(fldlg2, 0xd9ec)
DEF_ASM_OP0(fldln2, 0xd9ed)
DEF_ASM_OP0(fldz, 0xd9ee)
 
DEF_ASM_OP0(f2xm1, 0xd9f0)
DEF_ASM_OP0(fyl2x, 0xd9f1)
DEF_ASM_OP0(fptan, 0xd9f2)
DEF_ASM_OP0(fpatan, 0xd9f3)
DEF_ASM_OP0(fxtract, 0xd9f4)
DEF_ASM_OP0(fprem1, 0xd9f5)
DEF_ASM_OP0(fdecstp, 0xd9f6)
DEF_ASM_OP0(fincstp, 0xd9f7)
DEF_ASM_OP0(fprem, 0xd9f8)
DEF_ASM_OP0(fyl2xp1, 0xd9f9)
DEF_ASM_OP0(fsqrt, 0xd9fa)
DEF_ASM_OP0(fsincos, 0xd9fb)
DEF_ASM_OP0(frndint, 0xd9fc)
DEF_ASM_OP0(fscale, 0xd9fd)
DEF_ASM_OP0(fsin, 0xd9fe)
DEF_ASM_OP0(fcos, 0xd9ff)
DEF_ASM_OP0(fchs, 0xd9e0)
DEF_ASM_OP0(fabs, 0xd9e1)
DEF_ASM_OP0(fninit, 0xdbe3)
DEF_ASM_OP0(fnclex, 0xdbe2)
DEF_ASM_OP0(fnop, 0xd9d0)
DEF_ASM_OP0(fwait, 0x9b)
 
/* fp load */
DEF_ASM_OP1(fld, 0xd9c0, 0, OPC_REG, OPT_ST)
DEF_ASM_OP1(fldl, 0xd9c0, 0, OPC_REG, OPT_ST)
DEF_ASM_OP1(flds, 0xd9, 0, OPC_MODRM, OPT_EA)
ALT(DEF_ASM_OP1(fldl, 0xdd, 0, OPC_MODRM, OPT_EA))
DEF_ASM_OP1(fildl, 0xdb, 0, OPC_MODRM, OPT_EA)
DEF_ASM_OP1(fildq, 0xdf, 5, OPC_MODRM, OPT_EA)
DEF_ASM_OP1(fildll, 0xdf, 5, OPC_MODRM,OPT_EA)
DEF_ASM_OP1(fldt, 0xdb, 5, OPC_MODRM, OPT_EA)
DEF_ASM_OP1(fbld, 0xdf, 4, OPC_MODRM, OPT_EA)
/* fp store */
DEF_ASM_OP1(fst, 0xddd0, 0, OPC_REG, OPT_ST)
DEF_ASM_OP1(fstl, 0xddd0, 0, OPC_REG, OPT_ST)
DEF_ASM_OP1(fsts, 0xd9, 2, OPC_MODRM, OPT_EA)
DEF_ASM_OP1(fstps, 0xd9, 3, OPC_MODRM, OPT_EA)
ALT(DEF_ASM_OP1(fstl, 0xdd, 2, OPC_MODRM, OPT_EA))
DEF_ASM_OP1(fstpl, 0xdd, 3, OPC_MODRM, OPT_EA)
DEF_ASM_OP1(fist, 0xdf, 2, OPC_MODRM, OPT_EA)
DEF_ASM_OP1(fistp, 0xdf, 3, OPC_MODRM, OPT_EA)
DEF_ASM_OP1(fistl, 0xdb, 2, OPC_MODRM, OPT_EA)
DEF_ASM_OP1(fistpl, 0xdb, 3, OPC_MODRM, OPT_EA)
 
DEF_ASM_OP1(fstp, 0xddd8, 0, OPC_REG, OPT_ST)
DEF_ASM_OP1(fistpq, 0xdf, 7, OPC_MODRM, OPT_EA)
DEF_ASM_OP1(fistpll, 0xdf, 7, OPC_MODRM, OPT_EA)
DEF_ASM_OP1(fstpt, 0xdb, 7, OPC_MODRM, OPT_EA)
DEF_ASM_OP1(fbstp, 0xdf, 6, OPC_MODRM, OPT_EA)
 
/* exchange */
DEF_ASM_OP0(fxch, 0xd9c9)
ALT(DEF_ASM_OP1(fxch, 0xd9c8, 0, OPC_REG, OPT_ST))
 
/* misc FPU */
DEF_ASM_OP1(fucom, 0xdde0, 0, OPC_REG, OPT_ST )
DEF_ASM_OP1(fucomp, 0xdde8, 0, OPC_REG, OPT_ST )
 
DEF_ASM_OP0L(finit, 0xdbe3, 0, OPC_FWAIT)
DEF_ASM_OP1(fldcw, 0xd9, 5, OPC_MODRM, OPT_EA )
DEF_ASM_OP1(fnstcw, 0xd9, 7, OPC_MODRM, OPT_EA )
DEF_ASM_OP1(fstcw, 0xd9, 7, OPC_MODRM | OPC_FWAIT, OPT_EA )
DEF_ASM_OP0(fnstsw, 0xdfe0)
ALT(DEF_ASM_OP1(fnstsw, 0xdfe0, 0, 0, OPT_EAX ))
ALT(DEF_ASM_OP1(fnstsw, 0xdd, 7, OPC_MODRM, OPT_EA ))
DEF_ASM_OP1(fstsw, 0xdfe0, 0, OPC_FWAIT, OPT_EAX )
ALT(DEF_ASM_OP0L(fstsw, 0xdfe0, 0, OPC_FWAIT))
ALT(DEF_ASM_OP1(fstsw, 0xdd, 7, OPC_MODRM | OPC_FWAIT, OPT_EA ))
DEF_ASM_OP0L(fclex, 0xdbe2, 0, OPC_FWAIT)
DEF_ASM_OP1(fnstenv, 0xd9, 6, OPC_MODRM, OPT_EA )
DEF_ASM_OP1(fstenv, 0xd9, 6, OPC_MODRM | OPC_FWAIT, OPT_EA )
DEF_ASM_OP1(fldenv, 0xd9, 4, OPC_MODRM, OPT_EA )
DEF_ASM_OP1(fnsave, 0xdd, 6, OPC_MODRM, OPT_EA )
DEF_ASM_OP1(fsave, 0xdd, 6, OPC_MODRM | OPC_FWAIT, OPT_EA )
DEF_ASM_OP1(frstor, 0xdd, 4, OPC_MODRM, OPT_EA )
DEF_ASM_OP1(ffree, 0xddc0, 4, OPC_REG, OPT_ST )
DEF_ASM_OP1(ffreep, 0xdfc0, 4, OPC_REG, OPT_ST )
DEF_ASM_OP1(fxsave, 0x0fae, 0, OPC_MODRM, OPT_EA )
DEF_ASM_OP1(fxrstor, 0x0fae, 1, OPC_MODRM, OPT_EA )
 
/* segments */
DEF_ASM_OP2(arpl, 0x63, 0, OPC_MODRM, OPT_REG16, OPT_REG16 | OPT_EA)
DEF_ASM_OP2(lar, 0x0f02, 0, OPC_MODRM, OPT_REG32 | OPT_EA, OPT_REG32)
DEF_ASM_OP1(lgdt, 0x0f01, 2, OPC_MODRM, OPT_EA)
DEF_ASM_OP1(lidt, 0x0f01, 3, OPC_MODRM, OPT_EA)
DEF_ASM_OP1(lldt, 0x0f00, 2, OPC_MODRM, OPT_EA | OPT_REG)
DEF_ASM_OP1(lmsw, 0x0f01, 6, OPC_MODRM, OPT_EA | OPT_REG)
ALT(DEF_ASM_OP2(lslw, 0x0f03, 0, OPC_MODRM | OPC_WL, OPT_EA | OPT_REG, OPT_REG))
DEF_ASM_OP1(ltr, 0x0f00, 3, OPC_MODRM, OPT_EA | OPT_REG)
DEF_ASM_OP1(sgdt, 0x0f01, 0, OPC_MODRM, OPT_EA)
DEF_ASM_OP1(sidt, 0x0f01, 1, OPC_MODRM, OPT_EA)
DEF_ASM_OP1(sldt, 0x0f00, 0, OPC_MODRM, OPT_REG | OPT_EA)
DEF_ASM_OP1(smsw, 0x0f01, 4, OPC_MODRM, OPT_REG | OPT_EA)
DEF_ASM_OP1(str, 0x0f00, 1, OPC_MODRM, OPT_REG16| OPT_EA)
DEF_ASM_OP1(verr, 0x0f00, 4, OPC_MODRM, OPT_REG | OPT_EA)
DEF_ASM_OP1(verw, 0x0f00, 5, OPC_MODRM, OPT_REG | OPT_EA)
 
/* 486 */
DEF_ASM_OP1(bswap, 0x0fc8, 0, OPC_REG, OPT_REG32 )
ALT(DEF_ASM_OP2(xaddb, 0x0fc0, 0, OPC_MODRM | OPC_BWL, OPT_REG, OPT_REG | OPT_EA ))
ALT(DEF_ASM_OP2(cmpxchgb, 0x0fb0, 0, OPC_MODRM | OPC_BWL, OPT_REG, OPT_REG | OPT_EA ))
DEF_ASM_OP1(invlpg, 0x0f01, 7, OPC_MODRM, OPT_EA )
 
DEF_ASM_OP2(boundl, 0x62, 0, OPC_MODRM, OPT_REG32, OPT_EA)
DEF_ASM_OP2(boundw, 0x62, 0, OPC_MODRM | OPC_D16, OPT_REG16, OPT_EA)
 
/* pentium */
DEF_ASM_OP1(cmpxchg8b, 0x0fc7, 1, OPC_MODRM, OPT_EA )
/* pentium pro */
ALT(DEF_ASM_OP2(cmovo, 0x0f40, 0, OPC_MODRM | OPC_TEST, OPT_REG32 | OPT_EA, OPT_REG32))
 
DEF_ASM_OP2(fcmovb, 0xdac0, 0, OPC_REG, OPT_ST, OPT_ST0 )
DEF_ASM_OP2(fcmove, 0xdac8, 0, OPC_REG, OPT_ST, OPT_ST0 )
DEF_ASM_OP2(fcmovbe, 0xdad0, 0, OPC_REG, OPT_ST, OPT_ST0 )
DEF_ASM_OP2(fcmovu, 0xdad8, 0, OPC_REG, OPT_ST, OPT_ST0 )
DEF_ASM_OP2(fcmovnb, 0xdbc0, 0, OPC_REG, OPT_ST, OPT_ST0 )
DEF_ASM_OP2(fcmovne, 0xdbc8, 0, OPC_REG, OPT_ST, OPT_ST0 )
DEF_ASM_OP2(fcmovnbe, 0xdbd0, 0, OPC_REG, OPT_ST, OPT_ST0 )
DEF_ASM_OP2(fcmovnu, 0xdbd8, 0, OPC_REG, OPT_ST, OPT_ST0 )
 
DEF_ASM_OP2(fucomi, 0xdbe8, 0, OPC_REG, OPT_ST, OPT_ST0 )
DEF_ASM_OP2(fcomi, 0xdbf0, 0, OPC_REG, OPT_ST, OPT_ST0 )
DEF_ASM_OP2(fucomip, 0xdfe8, 0, OPC_REG, OPT_ST, OPT_ST0 )
DEF_ASM_OP2(fcomip, 0xdff0, 0, OPC_REG, OPT_ST, OPT_ST0 )
 
/* mmx */
DEF_ASM_OP0(emms, 0x0f77) /* must be last OP0 */
DEF_ASM_OP2(movd, 0x0f6e, 0, OPC_MODRM, OPT_EA | OPT_REG32, OPT_MMX )
ALT(DEF_ASM_OP2(movd, 0x0f7e, 0, OPC_MODRM, OPT_MMX, OPT_EA | OPT_REG32 ))
DEF_ASM_OP2(movq, 0x0f6f, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
ALT(DEF_ASM_OP2(movq, 0x0f7f, 0, OPC_MODRM, OPT_MMX, OPT_EA | OPT_MMX ))
DEF_ASM_OP2(packssdw, 0x0f6b, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(packsswb, 0x0f63, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(packuswb, 0x0f67, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(paddb, 0x0ffc, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(paddw, 0x0ffd, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(paddd, 0x0ffe, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(paddsb, 0x0fec, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(paddsw, 0x0fed, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(paddusb, 0x0fdc, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(paddusw, 0x0fdd, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(pand, 0x0fdb, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(pandn, 0x0fdf, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(pcmpeqb, 0x0f74, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(pcmpeqw, 0x0f75, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(pcmpeqd, 0x0f76, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(pcmpgtb, 0x0f64, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(pcmpgtw, 0x0f65, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(pcmpgtd, 0x0f66, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(pmaddwd, 0x0ff5, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(pmulhw, 0x0fe5, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(pmullw, 0x0fd5, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(por, 0x0feb, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(psllw, 0x0ff1, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
ALT(DEF_ASM_OP2(psllw, 0x0f71, 6, OPC_MODRM, OPT_IM8, OPT_MMX ))
DEF_ASM_OP2(pslld, 0x0ff2, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
ALT(DEF_ASM_OP2(pslld, 0x0f72, 6, OPC_MODRM, OPT_IM8, OPT_MMX ))
DEF_ASM_OP2(psllq, 0x0ff3, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
ALT(DEF_ASM_OP2(psllq, 0x0f73, 6, OPC_MODRM, OPT_IM8, OPT_MMX ))
DEF_ASM_OP2(psraw, 0x0fe1, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
ALT(DEF_ASM_OP2(psraw, 0x0f71, 4, OPC_MODRM, OPT_IM8, OPT_MMX ))
DEF_ASM_OP2(psrad, 0x0fe2, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
ALT(DEF_ASM_OP2(psrad, 0x0f72, 4, OPC_MODRM, OPT_IM8, OPT_MMX ))
DEF_ASM_OP2(psrlw, 0x0fd1, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
ALT(DEF_ASM_OP2(psrlw, 0x0f71, 2, OPC_MODRM, OPT_IM8, OPT_MMX ))
DEF_ASM_OP2(psrld, 0x0fd2, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
ALT(DEF_ASM_OP2(psrld, 0x0f72, 2, OPC_MODRM, OPT_IM8, OPT_MMX ))
DEF_ASM_OP2(psrlq, 0x0fd3, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
ALT(DEF_ASM_OP2(psrlq, 0x0f73, 2, OPC_MODRM, OPT_IM8, OPT_MMX ))
DEF_ASM_OP2(psubb, 0x0ff8, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(psubw, 0x0ff9, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(psubd, 0x0ffa, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(psubsb, 0x0fe8, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(psubsw, 0x0fe9, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(psubusb, 0x0fd8, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(psubusw, 0x0fd9, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(punpckhbw, 0x0f68, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(punpckhwd, 0x0f69, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(punpckhdq, 0x0f6a, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(punpcklbw, 0x0f60, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(punpcklwd, 0x0f61, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(punpckldq, 0x0f62, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
DEF_ASM_OP2(pxor, 0x0fef, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX )
 
#undef ALT
#undef DEF_ASM_OP0
#undef DEF_ASM_OP0L
#undef DEF_ASM_OP1
#undef DEF_ASM_OP2
#undef DEF_ASM_OP3
/programs/develop/metcc/trunk/source/i386-gen.c
0,0 → 1,1017
/*
* X86 code generator for TCC
*
* Copyright (c) 2001-2004 Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
 
/* number of available registers */
#define NB_REGS 4
 
/* a register can belong to several classes. The classes must be
sorted from more general to more precise (see gv2() code which does
assumptions on it). */
#define RC_INT 0x0001 /* generic integer register */
#define RC_FLOAT 0x0002 /* generic float register */
#define RC_EAX 0x0004
#define RC_ST0 0x0008
#define RC_ECX 0x0010
#define RC_EDX 0x0020
#define RC_IRET RC_EAX /* function return: integer register */
#define RC_LRET RC_EDX /* function return: second integer register */
#define RC_FRET RC_ST0 /* function return: float register */
 
/* pretty names for the registers */
enum {
TREG_EAX = 0,
TREG_ECX,
TREG_EDX,
TREG_ST0,
};
 
int reg_classes[NB_REGS] = {
/* eax */ RC_INT | RC_EAX,
/* ecx */ RC_INT | RC_ECX,
/* edx */ RC_INT | RC_EDX,
/* st0 */ RC_FLOAT | RC_ST0,
};
 
/* return registers for function */
#define REG_IRET TREG_EAX /* single word int return register */
#define REG_LRET TREG_EDX /* second word return register (for long long) */
#define REG_FRET TREG_ST0 /* float return register */
 
/* defined if function parameters must be evaluated in reverse order */
#define INVERT_FUNC_PARAMS
 
/* defined if structures are passed as pointers. Otherwise structures
are directly pushed on stack. */
//#define FUNC_STRUCT_PARAM_AS_PTR
 
/* pointer size, in bytes */
#define PTR_SIZE 4
 
/* long double size and alignment, in bytes */
#define LDOUBLE_SIZE 12
#define LDOUBLE_ALIGN 4
/* maximum alignment (for aligned attribute support) */
#define MAX_ALIGN 8
 
/******************************************************/
/* ELF defines */
 
#define EM_TCC_TARGET EM_386
 
/* relocation type for 32 bit data relocation */
#define R_DATA_32 R_386_32
#define R_JMP_SLOT R_386_JMP_SLOT
#define R_COPY R_386_COPY
 
#define ELF_START_ADDR 0x08048000
#define ELF_PAGE_SIZE 0x1000
 
/******************************************************/
 
static unsigned long func_sub_sp_offset;
static unsigned long func_bound_offset;
static int func_ret_sub;
 
/* XXX: make it faster ? */
void g(int c)
{
int ind1;
ind1 = ind + 1;
if (ind1 > cur_text_section->data_allocated)
section_realloc(cur_text_section, ind1);
cur_text_section->data[ind] = c;
ind = ind1;
}
 
void o(unsigned int c)
{
while (c) {
g(c);
c = c >> 8;
}
}
 
void gen_le32(int c)
{
g(c);
g(c >> 8);
g(c >> 16);
g(c >> 24);
}
 
/* output a symbol and patch all calls to it */
void gsym_addr(int t, int a)
{
int n, *ptr;
while (t) {
ptr = (int *)(cur_text_section->data + t);
n = *ptr; /* next value */
*ptr = a - t - 4;
t = n;
}
}
 
void gsym(int t)
{
gsym_addr(t, ind);
}
 
/* psym is used to put an instruction with a data field which is a
reference to a symbol. It is in fact the same as oad ! */
#define psym oad
 
/* instruction + 4 bytes data. Return the address of the data */
static int oad(int c, int s)
{
int ind1;
 
o(c);
ind1 = ind + 4;
if (ind1 > cur_text_section->data_allocated)
section_realloc(cur_text_section, ind1);
*(int *)(cur_text_section->data + ind) = s;
s = ind;
ind = ind1;
return s;
}
 
/* output constant with relocation if 'r & VT_SYM' is true */
static void gen_addr32(int r, Sym *sym, int c)
{
if (r & VT_SYM)
greloc(cur_text_section, sym, ind, R_386_32);
gen_le32(c);
}
 
/* generate a modrm reference. 'op_reg' contains the addtionnal 3
opcode bits */
static void gen_modrm(int op_reg, int r, Sym *sym, int c)
{
op_reg = op_reg << 3;
if ((r & VT_VALMASK) == VT_CONST) {
/* constant memory reference */
o(0x05 | op_reg);
gen_addr32(r, sym, c);
} else if ((r & VT_VALMASK) == VT_LOCAL) {
/* currently, we use only ebp as base */
if (c == (char)c) {
/* short reference */
o(0x45 | op_reg);
g(c);
} else {
oad(0x85 | op_reg, c);
}
} else {
g(0x00 | op_reg | (r & VT_VALMASK));
}
}
 
 
/* load 'r' from value 'sv' */
void load(int r, SValue *sv)
{
int v, t, ft, fc, fr;
SValue v1;
 
fr = sv->r;
ft = sv->type.t;
fc = sv->c.ul;
 
v = fr & VT_VALMASK;
if (fr & VT_LVAL) {
if (v == VT_LLOCAL) {
v1.type.t = VT_INT;
v1.r = VT_LOCAL | VT_LVAL;
v1.c.ul = fc;
load(r, &v1);
fr = r;
}
if ((ft & VT_BTYPE) == VT_FLOAT) {
o(0xd9); /* flds */
r = 0;
} else if ((ft & VT_BTYPE) == VT_DOUBLE) {
o(0xdd); /* fldl */
r = 0;
} else if ((ft & VT_BTYPE) == VT_LDOUBLE) {
o(0xdb); /* fldt */
r = 5;
} else if ((ft & VT_TYPE) == VT_BYTE) {
o(0xbe0f); /* movsbl */
} else if ((ft & VT_TYPE) == (VT_BYTE | VT_UNSIGNED)) {
o(0xb60f); /* movzbl */
} else if ((ft & VT_TYPE) == VT_SHORT) {
o(0xbf0f); /* movswl */
} else if ((ft & VT_TYPE) == (VT_SHORT | VT_UNSIGNED)) {
o(0xb70f); /* movzwl */
} else {
o(0x8b); /* movl */
}
gen_modrm(r, fr, sv->sym, fc);
} else {
if (v == VT_CONST) {
o(0xb8 + r); /* mov $xx, r */
gen_addr32(fr, sv->sym, fc);
} else if (v == VT_LOCAL) {
o(0x8d); /* lea xxx(%ebp), r */
gen_modrm(r, VT_LOCAL, sv->sym, fc);
} else if (v == VT_CMP) {
oad(0xb8 + r, 0); /* mov $0, r */
o(0x0f); /* setxx %br */
o(fc);
o(0xc0 + r);
} else if (v == VT_JMP || v == VT_JMPI) {
t = v & 1;
oad(0xb8 + r, t); /* mov $1, r */
o(0x05eb); /* jmp after */
gsym(fc);
oad(0xb8 + r, t ^ 1); /* mov $0, r */
} else if (v != r) {
o(0x89);
o(0xc0 + r + v * 8); /* mov v, r */
}
}
}
 
/* store register 'r' in lvalue 'v' */
void store(int r, SValue *v)
{
int fr, bt, ft, fc;
 
ft = v->type.t;
fc = v->c.ul;
fr = v->r & VT_VALMASK;
bt = ft & VT_BTYPE;
/* XXX: incorrect if float reg to reg */
if (bt == VT_FLOAT) {
o(0xd9); /* fsts */
r = 2;
} else if (bt == VT_DOUBLE) {
o(0xdd); /* fstpl */
r = 2;
} else if (bt == VT_LDOUBLE) {
o(0xc0d9); /* fld %st(0) */
o(0xdb); /* fstpt */
r = 7;
} else {
if (bt == VT_SHORT)
o(0x66);
if (bt == VT_BYTE || bt == VT_BOOL)
o(0x88);
else
o(0x89);
}
if (fr == VT_CONST ||
fr == VT_LOCAL ||
(v->r & VT_LVAL)) {
gen_modrm(r, v->r, v->sym, fc);
} else if (fr != r) {
o(0xc0 + fr + r * 8); /* mov r, fr */
}
}
 
static void gadd_sp(int val)
{
if (val == (char)val) {
o(0xc483);
g(val);
} else {
oad(0xc481, val); /* add $xxx, %esp */
}
}
 
/* 'is_jmp' is '1' if it is a jump */
static void gcall_or_jmp(int is_jmp)
{
int r;
if ((vtop->r & (VT_VALMASK | VT_LVAL)) == VT_CONST) {
/* constant case */
if (vtop->r & VT_SYM) {
/* relocation case */
greloc(cur_text_section, vtop->sym,
ind + 1, R_386_PC32);
} else {
/* put an empty PC32 relocation */
put_elf_reloc(symtab_section, cur_text_section,
ind + 1, R_386_PC32, 0);
}
oad(0xe8 + is_jmp, vtop->c.ul - 4); /* call/jmp im */
} else {
/* otherwise, indirect call */
r = gv(RC_INT);
o(0xff); /* call/jmp *r */
o(0xd0 + r + (is_jmp << 4));
}
}
 
static uint8_t fastcall_regs[3] = { TREG_EAX, TREG_EDX, TREG_ECX };
 
/* Generate function call. The function address is pushed first, then
all the parameters in call order. This functions pops all the
parameters and the function address. */
void gfunc_call(int nb_args)
{
int size, align, r, args_size, i, func_call;
Sym *func_sym;
args_size = 0;
for(i = 0;i < nb_args; i++) {
if ((vtop->type.t & VT_BTYPE) == VT_STRUCT) {
size = type_size(&vtop->type, &align);
/* align to stack align size */
size = (size + 3) & ~3;
/* allocate the necessary size on stack */
oad(0xec81, size); /* sub $xxx, %esp */
/* generate structure store */
r = get_reg(RC_INT);
o(0x89); /* mov %esp, r */
o(0xe0 + r);
vset(&vtop->type, r | VT_LVAL, 0);
vswap();
vstore();
args_size += size;
} else if (is_float(vtop->type.t)) {
gv(RC_FLOAT); /* only one float register */
if ((vtop->type.t & VT_BTYPE) == VT_FLOAT)
size = 4;
else if ((vtop->type.t & VT_BTYPE) == VT_DOUBLE)
size = 8;
else
size = 12;
oad(0xec81, size); /* sub $xxx, %esp */
if (size == 12)
o(0x7cdb);
else
o(0x5cd9 + size - 4); /* fstp[s|l] 0(%esp) */
g(0x24);
g(0x00);
args_size += size;
} else {
/* simple type (currently always same size) */
/* XXX: implicit cast ? */
r = gv(RC_INT);
if ((vtop->type.t & VT_BTYPE) == VT_LLONG) {
size = 8;
o(0x50 + vtop->r2); /* push r */
} else {
size = 4;
}
o(0x50 + r); /* push r */
args_size += size;
}
vtop--;
}
save_regs(0); /* save used temporary registers */
func_sym = vtop->type.ref;
func_call = func_sym->r;
/* fast call case */
if (func_call >= FUNC_FASTCALL1 && func_call <= FUNC_FASTCALL3) {
int fastcall_nb_regs;
fastcall_nb_regs = func_call - FUNC_FASTCALL1 + 1;
for(i = 0;i < fastcall_nb_regs; i++) {
if (args_size <= 0)
break;
o(0x58 + fastcall_regs[i]); /* pop r */
/* XXX: incorrect for struct/floats */
args_size -= 4;
}
}
gcall_or_jmp(0);
if (args_size && func_sym->r != FUNC_STDCALL)
gadd_sp(args_size);
vtop--;
}
 
#ifdef TCC_TARGET_PE
#define FUNC_PROLOG_SIZE 10
#else
#define FUNC_PROLOG_SIZE 9
#endif
 
/* generate function prolog of type 't' */
void gfunc_prolog(CType *func_type)
{
int addr, align, size, func_call, fastcall_nb_regs;
int param_index, param_addr;
Sym *sym;
CType *type;
 
sym = func_type->ref;
func_call = sym->r;
addr = 8;
loc = 0;
if (func_call >= FUNC_FASTCALL1 && func_call <= FUNC_FASTCALL3) {
fastcall_nb_regs = func_call - FUNC_FASTCALL1 + 1;
} else {
fastcall_nb_regs = 0;
}
param_index = 0;
 
ind += FUNC_PROLOG_SIZE;
func_sub_sp_offset = ind;
/* if the function returns a structure, then add an
implicit pointer parameter */
func_vt = sym->type;
if ((func_vt.t & VT_BTYPE) == VT_STRUCT) {
/* XXX: fastcall case ? */
func_vc = addr;
addr += 4;
param_index++;
}
/* define parameters */
while ((sym = sym->next) != NULL) {
type = &sym->type;
size = type_size(type, &align);
size = (size + 3) & ~3;
#ifdef FUNC_STRUCT_PARAM_AS_PTR
/* structs are passed as pointer */
if ((type->t & VT_BTYPE) == VT_STRUCT) {
size = 4;
}
#endif
if (param_index < fastcall_nb_regs) {
/* save FASTCALL register */
loc -= 4;
o(0x89); /* movl */
gen_modrm(fastcall_regs[param_index], VT_LOCAL, NULL, loc);
param_addr = loc;
} else {
param_addr = addr;
addr += size;
}
sym_push(sym->v & ~SYM_FIELD, type,
VT_LOCAL | VT_LVAL, param_addr);
param_index++;
}
func_ret_sub = 0;
/* pascal type call ? */
if (func_call == FUNC_STDCALL)
func_ret_sub = addr - 8;
 
/* leave some room for bound checking code */
if (do_bounds_check) {
oad(0xb8, 0); /* lbound section pointer */
oad(0xb8, 0); /* call to function */
func_bound_offset = lbounds_section->data_offset;
}
}
 
/* generate function epilog */
void gfunc_epilog(void)
{
int v, saved_ind;
 
#ifdef CONFIG_TCC_BCHECK
if (do_bounds_check && func_bound_offset != lbounds_section->data_offset) {
int saved_ind;
int *bounds_ptr;
Sym *sym, *sym_data;
/* add end of table info */
bounds_ptr = section_ptr_add(lbounds_section, sizeof(int));
*bounds_ptr = 0;
/* generate bound local allocation */
saved_ind = ind;
ind = func_sub_sp_offset;
sym_data = get_sym_ref(&char_pointer_type, lbounds_section,
func_bound_offset, lbounds_section->data_offset);
greloc(cur_text_section, sym_data,
ind + 1, R_386_32);
oad(0xb8, 0); /* mov %eax, xxx */
sym = external_global_sym(TOK___bound_local_new, &func_old_type, 0);
greloc(cur_text_section, sym,
ind + 1, R_386_PC32);
oad(0xe8, -4);
ind = saved_ind;
/* generate bound check local freeing */
o(0x5250); /* save returned value, if any */
greloc(cur_text_section, sym_data,
ind + 1, R_386_32);
oad(0xb8, 0); /* mov %eax, xxx */
sym = external_global_sym(TOK___bound_local_delete, &func_old_type, 0);
greloc(cur_text_section, sym,
ind + 1, R_386_PC32);
oad(0xe8, -4);
o(0x585a); /* restore returned value, if any */
}
#endif
o(0xc9); /* leave */
if (func_ret_sub == 0) {
o(0xc3); /* ret */
} else {
o(0xc2); /* ret n */
g(func_ret_sub);
g(func_ret_sub >> 8);
}
/* align local size to word & save local variables */
v = (-loc + 3) & -4;
saved_ind = ind;
ind = func_sub_sp_offset - FUNC_PROLOG_SIZE;
#ifdef TCC_TARGET_PE
if (v >= 4096) {
Sym *sym = external_global_sym(TOK___chkstk, &func_old_type, 0);
oad(0xb8, v); /* mov stacksize, %eax */
oad(0xe8, -4); /* call __chkstk, (does the stackframe too) */
greloc(cur_text_section, sym, ind-4, R_386_PC32);
} else
#endif
{
o(0xe58955); /* push %ebp, mov %esp, %ebp */
o(0xec81); /* sub esp, stacksize */
gen_le32(v);
#if FUNC_PROLOG_SIZE == 10
o(0x90); /* adjust to FUNC_PROLOG_SIZE */
#endif
}
ind = saved_ind;
}
 
/* generate a jump to a label */
int gjmp(int t)
{
return psym(0xe9, t);
}
 
/* generate a jump to a fixed address */
void gjmp_addr(int a)
{
int r;
r = a - ind - 2;
if (r == (char)r) {
g(0xeb);
g(r);
} else {
oad(0xe9, a - ind - 5);
}
}
 
/* generate a test. set 'inv' to invert test. Stack entry is popped */
int gtst(int inv, int t)
{
int v, *p;
 
v = vtop->r & VT_VALMASK;
if (v == VT_CMP) {
/* fast case : can jump directly since flags are set */
g(0x0f);
t = psym((vtop->c.i - 16) ^ inv, t);
} else if (v == VT_JMP || v == VT_JMPI) {
/* && or || optimization */
if ((v & 1) == inv) {
/* insert vtop->c jump list in t */
p = &vtop->c.i;
while (*p != 0)
p = (int *)(cur_text_section->data + *p);
*p = t;
t = vtop->c.i;
} else {
t = gjmp(t);
gsym(vtop->c.i);
}
} else {
if (is_float(vtop->type.t)) {
vpushi(0);
gen_op(TOK_NE);
}
if ((vtop->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST) {
/* constant jmp optimization */
if ((vtop->c.i != 0) != inv)
t = gjmp(t);
} else {
v = gv(RC_INT);
o(0x85);
o(0xc0 + v * 9);
g(0x0f);
t = psym(0x85 ^ inv, t);
}
}
vtop--;
return t;
}
 
/* generate an integer binary operation */
void gen_opi(int op)
{
int r, fr, opc, c;
 
switch(op) {
case '+':
case TOK_ADDC1: /* add with carry generation */
opc = 0;
gen_op8:
if ((vtop->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST) {
/* constant case */
vswap();
r = gv(RC_INT);
vswap();
c = vtop->c.i;
if (c == (char)c) {
/* XXX: generate inc and dec for smaller code ? */
o(0x83);
o(0xc0 | (opc << 3) | r);
g(c);
} else {
o(0x81);
oad(0xc0 | (opc << 3) | r, c);
}
} else {
gv2(RC_INT, RC_INT);
r = vtop[-1].r;
fr = vtop[0].r;
o((opc << 3) | 0x01);
o(0xc0 + r + fr * 8);
}
vtop--;
if (op >= TOK_ULT && op <= TOK_GT) {
vtop->r = VT_CMP;
vtop->c.i = op;
}
break;
case '-':
case TOK_SUBC1: /* sub with carry generation */
opc = 5;
goto gen_op8;
case TOK_ADDC2: /* add with carry use */
opc = 2;
goto gen_op8;
case TOK_SUBC2: /* sub with carry use */
opc = 3;
goto gen_op8;
case '&':
opc = 4;
goto gen_op8;
case '^':
opc = 6;
goto gen_op8;
case '|':
opc = 1;
goto gen_op8;
case '*':
gv2(RC_INT, RC_INT);
r = vtop[-1].r;
fr = vtop[0].r;
vtop--;
o(0xaf0f); /* imul fr, r */
o(0xc0 + fr + r * 8);
break;
case TOK_SHL:
opc = 4;
goto gen_shift;
case TOK_SHR:
opc = 5;
goto gen_shift;
case TOK_SAR:
opc = 7;
gen_shift:
opc = 0xc0 | (opc << 3);
if ((vtop->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST) {
/* constant case */
vswap();
r = gv(RC_INT);
vswap();
c = vtop->c.i & 0x1f;
o(0xc1); /* shl/shr/sar $xxx, r */
o(opc | r);
g(c);
} else {
/* we generate the shift in ecx */
gv2(RC_INT, RC_ECX);
r = vtop[-1].r;
o(0xd3); /* shl/shr/sar %cl, r */
o(opc | r);
}
vtop--;
break;
case '/':
case TOK_UDIV:
case TOK_PDIV:
case '%':
case TOK_UMOD:
case TOK_UMULL:
/* first operand must be in eax */
/* XXX: need better constraint for second operand */
gv2(RC_EAX, RC_ECX);
r = vtop[-1].r;
fr = vtop[0].r;
vtop--;
save_reg(TREG_EDX);
if (op == TOK_UMULL) {
o(0xf7); /* mul fr */
o(0xe0 + fr);
vtop->r2 = TREG_EDX;
r = TREG_EAX;
} else {
if (op == TOK_UDIV || op == TOK_UMOD) {
o(0xf7d231); /* xor %edx, %edx, div fr, %eax */
o(0xf0 + fr);
} else {
o(0xf799); /* cltd, idiv fr, %eax */
o(0xf8 + fr);
}
if (op == '%' || op == TOK_UMOD)
r = TREG_EDX;
else
r = TREG_EAX;
}
vtop->r = r;
break;
default:
opc = 7;
goto gen_op8;
}
}
 
/* generate a floating point operation 'v = t1 op t2' instruction. The
two operands are guaranted to have the same floating point type */
/* XXX: need to use ST1 too */
void gen_opf(int op)
{
int a, ft, fc, swapped, r;
 
/* convert constants to memory references */
if ((vtop[-1].r & (VT_VALMASK | VT_LVAL)) == VT_CONST) {
vswap();
gv(RC_FLOAT);
vswap();
}
if ((vtop[0].r & (VT_VALMASK | VT_LVAL)) == VT_CONST)
gv(RC_FLOAT);
 
/* must put at least one value in the floating point register */
if ((vtop[-1].r & VT_LVAL) &&
(vtop[0].r & VT_LVAL)) {
vswap();
gv(RC_FLOAT);
vswap();
}
swapped = 0;
/* swap the stack if needed so that t1 is the register and t2 is
the memory reference */
if (vtop[-1].r & VT_LVAL) {
vswap();
swapped = 1;
}
if (op >= TOK_ULT && op <= TOK_GT) {
/* load on stack second operand */
load(TREG_ST0, vtop);
save_reg(TREG_EAX); /* eax is used by FP comparison code */
if (op == TOK_GE || op == TOK_GT)
swapped = !swapped;
else if (op == TOK_EQ || op == TOK_NE)
swapped = 0;
if (swapped)
o(0xc9d9); /* fxch %st(1) */
o(0xe9da); /* fucompp */
o(0xe0df); /* fnstsw %ax */
if (op == TOK_EQ) {
o(0x45e480); /* and $0x45, %ah */
o(0x40fC80); /* cmp $0x40, %ah */
} else if (op == TOK_NE) {
o(0x45e480); /* and $0x45, %ah */
o(0x40f480); /* xor $0x40, %ah */
op = TOK_NE;
} else if (op == TOK_GE || op == TOK_LE) {
o(0x05c4f6); /* test $0x05, %ah */
op = TOK_EQ;
} else {
o(0x45c4f6); /* test $0x45, %ah */
op = TOK_EQ;
}
vtop--;
vtop->r = VT_CMP;
vtop->c.i = op;
} else {
/* no memory reference possible for long double operations */
if ((vtop->type.t & VT_BTYPE) == VT_LDOUBLE) {
load(TREG_ST0, vtop);
swapped = !swapped;
}
switch(op) {
default:
case '+':
a = 0;
break;
case '-':
a = 4;
if (swapped)
a++;
break;
case '*':
a = 1;
break;
case '/':
a = 6;
if (swapped)
a++;
break;
}
ft = vtop->type.t;
fc = vtop->c.ul;
if ((ft & VT_BTYPE) == VT_LDOUBLE) {
o(0xde); /* fxxxp %st, %st(1) */
o(0xc1 + (a << 3));
} else {
/* if saved lvalue, then we must reload it */
r = vtop->r;
if ((r & VT_VALMASK) == VT_LLOCAL) {
SValue v1;
r = get_reg(RC_INT);
v1.type.t = VT_INT;
v1.r = VT_LOCAL | VT_LVAL;
v1.c.ul = fc;
load(r, &v1);
fc = 0;
}
 
if ((ft & VT_BTYPE) == VT_DOUBLE)
o(0xdc);
else
o(0xd8);
gen_modrm(a, r, vtop->sym, fc);
}
vtop--;
}
}
 
/* convert integers to fp 't' type. Must handle 'int', 'unsigned int'
and 'long long' cases. */
void gen_cvt_itof(int t)
{
save_reg(TREG_ST0);
gv(RC_INT);
if ((vtop->type.t & VT_BTYPE) == VT_LLONG) {
/* signed long long to float/double/long double (unsigned case
is handled generically) */
o(0x50 + vtop->r2); /* push r2 */
o(0x50 + (vtop->r & VT_VALMASK)); /* push r */
o(0x242cdf); /* fildll (%esp) */
o(0x08c483); /* add $8, %esp */
} else if ((vtop->type.t & (VT_BTYPE | VT_UNSIGNED)) ==
(VT_INT | VT_UNSIGNED)) {
/* unsigned int to float/double/long double */
o(0x6a); /* push $0 */
g(0x00);
o(0x50 + (vtop->r & VT_VALMASK)); /* push r */
o(0x242cdf); /* fildll (%esp) */
o(0x08c483); /* add $8, %esp */
} else {
/* int to float/double/long double */
o(0x50 + (vtop->r & VT_VALMASK)); /* push r */
o(0x2404db); /* fildl (%esp) */
o(0x04c483); /* add $4, %esp */
}
vtop->r = TREG_ST0;
}
 
/* convert fp to int 't' type */
/* XXX: handle long long case */
void gen_cvt_ftoi(int t)
{
int r, r2, size;
Sym *sym;
CType ushort_type;
 
ushort_type.t = VT_SHORT | VT_UNSIGNED;
 
gv(RC_FLOAT);
if (t != VT_INT)
size = 8;
else
size = 4;
o(0x2dd9); /* ldcw xxx */
sym = external_global_sym(TOK___tcc_int_fpu_control,
&ushort_type, VT_LVAL);
greloc(cur_text_section, sym,
ind, R_386_32);
gen_le32(0);
oad(0xec81, size); /* sub $xxx, %esp */
if (size == 4)
o(0x1cdb); /* fistpl */
else
o(0x3cdf); /* fistpll */
o(0x24);
o(0x2dd9); /* ldcw xxx */
sym = external_global_sym(TOK___tcc_fpu_control,
&ushort_type, VT_LVAL);
greloc(cur_text_section, sym,
ind, R_386_32);
gen_le32(0);
 
r = get_reg(RC_INT);
o(0x58 + r); /* pop r */
if (size == 8) {
if (t == VT_LLONG) {
vtop->r = r; /* mark reg as used */
r2 = get_reg(RC_INT);
o(0x58 + r2); /* pop r2 */
vtop->r2 = r2;
} else {
o(0x04c483); /* add $4, %esp */
}
}
vtop->r = r;
}
 
/* convert from one floating point type to another */
void gen_cvt_ftof(int t)
{
/* all we have to do on i386 is to put the float in a register */
gv(RC_FLOAT);
}
 
/* computed goto support */
void ggoto(void)
{
gcall_or_jmp(1);
vtop--;
}
 
/* bound check support functions */
#ifdef CONFIG_TCC_BCHECK
 
/* generate a bounded pointer addition */
void gen_bounded_ptr_add(void)
{
Sym *sym;
 
/* prepare fast i386 function call (args in eax and edx) */
gv2(RC_EAX, RC_EDX);
/* save all temporary registers */
vtop -= 2;
save_regs(0);
/* do a fast function call */
sym = external_global_sym(TOK___bound_ptr_add, &func_old_type, 0);
greloc(cur_text_section, sym,
ind + 1, R_386_PC32);
oad(0xe8, -4);
/* returned pointer is in eax */
vtop++;
vtop->r = TREG_EAX | VT_BOUNDED;
/* address of bounding function call point */
vtop->c.ul = (cur_text_section->reloc->data_offset - sizeof(Elf32_Rel));
}
 
/* patch pointer addition in vtop so that pointer dereferencing is
also tested */
void gen_bounded_ptr_deref(void)
{
int func;
int size, align;
Elf32_Rel *rel;
Sym *sym;
 
size = 0;
/* XXX: put that code in generic part of tcc */
if (!is_float(vtop->type.t)) {
if (vtop->r & VT_LVAL_BYTE)
size = 1;
else if (vtop->r & VT_LVAL_SHORT)
size = 2;
}
if (!size)
size = type_size(&vtop->type, &align);
switch(size) {
case 1: func = TOK___bound_ptr_indir1; break;
case 2: func = TOK___bound_ptr_indir2; break;
case 4: func = TOK___bound_ptr_indir4; break;
case 8: func = TOK___bound_ptr_indir8; break;
case 12: func = TOK___bound_ptr_indir12; break;
case 16: func = TOK___bound_ptr_indir16; break;
default:
error("unhandled size when derefencing bounded pointer");
func = 0;
break;
}
 
/* patch relocation */
/* XXX: find a better solution ? */
rel = (Elf32_Rel *)(cur_text_section->reloc->data + vtop->c.ul);
sym = external_global_sym(func, &func_old_type, 0);
if (!sym->c)
put_extern_sym(sym, NULL, 0, 0);
rel->r_info = ELF32_R_INFO(sym->c, ELF32_R_TYPE(rel->r_info));
}
#endif
 
/* end of X86 code generator */
/*********