/drivers/video/drm/radeon/cayman_blit_shaders.c |
---|
File deleted |
/drivers/video/drm/radeon/cayman_blit_shaders.h |
---|
File deleted |
/drivers/video/drm/radeon/radeon_irq_kms.c |
---|
File deleted |
/drivers/video/drm/radeon/radeon_trace.h |
---|
File deleted |
/drivers/video/drm/radeon/Makefile.lto |
---|
55,23 → 55,20 |
radeon_device.c \ |
evergreen.c \ |
evergreen_blit_shaders.c \ |
cayman_blit_shaders.c \ |
radeon_clocks.c \ |
radeon_i2c.c \ |
atom.c \ |
ni.c \ |
radeon_gem.c \ |
radeon_atombios.c \ |
radeon_agp.c \ |
radeon_asic.c \ |
radeon_atombios.c \ |
radeon_bios.c \ |
radeon_combios.c \ |
radeon_connectors.c \ |
atombios_crtc.c \ |
atombios_dp.c \ |
radeon_encoders.c \ |
radeon_fence.c \ |
radeon_gem.c \ |
radeon_i2c.c \ |
radeon_irq_kms.c \ |
radeon_connectors.c \ |
radeon_bios.c \ |
radeon_combios.c \ |
radeon_legacy_crtc.c \ |
radeon_legacy_encoders.c \ |
radeon_legacy_tv.c \ |
/drivers/video/drm/radeon/Makefile |
---|
55,23 → 55,20 |
radeon_device.c \ |
evergreen.c \ |
evergreen_blit_shaders.c \ |
cayman_blit_shaders.c \ |
radeon_clocks.c \ |
radeon_i2c.c \ |
atom.c \ |
ni.c \ |
radeon_gem.c \ |
radeon_atombios.c \ |
radeon_agp.c \ |
radeon_asic.c \ |
radeon_atombios.c \ |
radeon_bios.c \ |
radeon_combios.c \ |
radeon_connectors.c \ |
atombios_crtc.c \ |
atombios_dp.c \ |
radeon_encoders.c \ |
radeon_fence.c \ |
radeon_gem.c \ |
radeon_i2c.c \ |
radeon_irq_kms.c \ |
radeon_connectors.c \ |
radeon_bios.c \ |
radeon_combios.c \ |
radeon_legacy_crtc.c \ |
radeon_legacy_encoders.c \ |
radeon_legacy_tv.c \ |
/drivers/video/drm/radeon/evergreen.c |
---|
281,6 → 281,7 |
} |
} |
#if 0 |
void evergreen_hpd_init(struct radeon_device *rdev) |
{ |
struct drm_device *dev = rdev->ddev; |
319,12 → 320,10 |
break; |
} |
} |
// if (rdev->irq.installed) |
// evergreen_irq_set(rdev); |
if (rdev->irq.installed) |
evergreen_irq_set(rdev); |
} |
#if 0 |
void evergreen_hpd_fini(struct radeon_device *rdev) |
{ |
struct drm_device *dev = rdev->ddev; |
2241,9 → 2240,6 |
/* Get VRAM informations */ |
rdev->mc.vram_is_ddr = true; |
if (rdev->flags & RADEON_IS_IGP) |
tmp = RREG32(FUS_MC_ARB_RAMCFG); |
else |
tmp = RREG32(MC_ARB_RAMCFG); |
if (tmp & CHANSIZE_OVERRIDE) { |
chansize = 16; |
/drivers/video/drm/radeon/fwblob.asm |
---|
114,29 → 114,11 |
dd SUMOME_START |
dd (SUMOME_END - SUMOME_START) |
dd FIRMWARE_SUMO2_ME |
dd SUMO2ME_START |
dd (SUMO2ME_END - SUMO2ME_START) |
macro ni_code [arg] |
{ |
dd FIRMWARE_#arg#_ME |
dd arg#ME_START |
dd (arg#ME_END - arg#ME_START) |
dd FIRMWARE_#arg#_PFP |
dd arg#PFP_START |
dd (arg#PFP_END - arg#PFP_START) |
dd FIRMWARE_#arg#_MC |
dd arg#MC_START |
dd (arg#MC_END - arg#MC_START) |
} |
ni_code BARTS, TURKS, CAICOS, CAYMAN |
dd FIRMWARE_RV610_PFP |
dd RV610PFP_START |
dd (RV610PFP_END - RV610PFP_START) |
198,9 → 180,6 |
dd SUMO2PFP_START |
dd (SUMO2PFP_END - SUMO2PFP_START) |
dd FIRMWARE_BARTS_PFP |
dd BARTSPFP_START |
dd (BARTSPFP_END - BARTSPFP_START) |
dd FIRMWARE_R600_RLC |
227,15 → 206,10 |
dd JUNIPERRLC_START |
dd (JUNIPERRLC_END - JUNIPERRLC_START) |
dd FIRMWARE_BTC_RLC |
dd BTCRLC_START |
dd (BTCRLC_END - BTCRLC_START) |
dd FIRMWARE_SUMO_RLC |
dd SUMORLC_START |
dd (SUMORLC_END - SUMORLC_START) |
___end_builtin_fw: |
249,6 → 223,7 |
FIRMWARE_RS690_CP db 'radeon/RS690_cp.bin',0 |
FIRMWARE_RS780_ME db 'radeon/RS780_me.bin',0 |
FIRMWARE_RS780_PFP db 'radeon/RS780_pfp.bin',0 |
FIRMWARE_R600_ME db 'radeon/RV600_me.bin',0 |
FIRMWARE_RV610_ME db 'radeon/RV610_me.bin',0 |
259,7 → 234,6 |
FIRMWARE_RV710_ME db 'radeon/RV710_me.bin',0 |
FIRMWARE_RV730_ME db 'radeon/RV730_me.bin',0 |
FIRMWARE_RV770_ME db 'radeon/RV770_me.bin',0 |
FIRMWARE_CYPRESS_ME db 'radeon/CYPRESS_me.bin',0 |
FIRMWARE_REDWOOD_ME db 'radeon/REDWOOD_me.bin',0 |
FIRMWARE_CEDAR_ME db 'radeon/CEDAR_me.bin',0 |
268,13 → 242,7 |
FIRMWARE_SUMO_ME db 'radeon/SUMO_me.bin',0 |
FIRMWARE_SUMO2_ME db 'radeon/SUMO2_me.bin',0 |
FIRMWARE_BARTS_ME db 'radeon/BARTS_me.bin',0 |
FIRMWARE_TURKS_ME db 'radeon/TURKS_me.bin',0 |
FIRMWARE_CAICOS_ME db 'radeon/CAICOS_me.bin',0 |
FIRMWARE_CAYMAN_ME db 'radeon/CAYMAN_me.bin',0 |
FIRMWARE_RS780_PFP db 'radeon/RS780_pfp.bin',0 |
FIRMWARE_R600_PFP db 'radeon/R600_pfp.bin',0 |
FIRMWARE_RV610_PFP db 'radeon/RV610_pfp.bin',0 |
FIRMWARE_RV620_PFP db 'radeon/RV620_pfp.bin',0 |
284,7 → 252,6 |
FIRMWARE_RV710_PFP db 'radeon/RV710_pfp.bin',0 |
FIRMWARE_RV730_PFP db 'radeon/RV730_pfp.bin',0 |
FIRMWARE_RV770_PFP db 'radeon/RV770_pfp.bin',0 |
FIRMWARE_CYPRESS_PFP db 'radeon/CYPRESS_pfp.bin',0 |
FIRMWARE_REDWOOD_PFP db 'radeon/REDWOOD_pfp.bin',0 |
FIRMWARE_CEDAR_PFP db 'radeon/CEDAR_pfp.bin',0 |
293,12 → 260,7 |
FIRMWARE_SUMO_PFP db 'radeon/SUMO_pfp.bin',0 |
FIRMWARE_SUMO2_PFP db 'radeon/SUMO2_pfp.bin',0 |
FIRMWARE_BARTS_PFP db 'radeon/BARTS_pfp.bin',0 |
FIRMWARE_TURKS_PFP db 'radeon/TURKS_pfp.bin',0 |
FIRMWARE_CAICOS_PFP db 'radeon/CAICOS_pfp.bin',0 |
FIRMWARE_CAYMAN_PFP db 'radeon/CAYMAN_pfp.bin',0 |
FIRMWARE_R600_RLC db 'radeon/R600_rlc.bin',0 |
FIRMWARE_R700_RLC db 'radeon/R700_rlc.bin',0 |
FIRMWARE_CYPRESS_RLC db 'radeon/CYPRESS_rlc.bin',0 |
306,16 → 268,8 |
FIRMWARE_CEDAR_RLC db 'radeon/CEDAR_rlc.bin',0 |
FIRMWARE_JUNIPER_RLC db 'radeon/JUNIPER_rlc.bin',0 |
FIRMWARE_SUMO_RLC db 'radeon/SUMO_rlc.bin',0 |
FIRMWARE_BTC_RLC db 'radeon/BTC_rlc.bin',0 |
FIRMWARE_CAYMAN_RLC db 'radeon/CAYMAN_rlc.bin',0 |
FIRMWARE_BARTS_MC db 'radeon/BARTS_mc.bin',0 |
FIRMWARE_TURKS_MC db 'radeon/TURKS_mc.bin',0 |
FIRMWARE_CAICOS_MC db 'radeon/CAICOS_mc.bin',0 |
FIRMWARE_CAYMAN_MC db 'radeon/CAYMAN_mc.bin',0 |
align 16 |
R100CP_START: |
file 'firmware/R100_cp.bin' |
442,28 → 396,8 |
file 'firmware/SUMO2_me.bin' |
SUMO2ME_END: |
align 16 |
BARTSME_START: |
file 'firmware/BARTS_me.bin' |
BARTSME_END: |
align 16 |
TURKSME_START: |
file 'firmware/TURKS_me.bin' |
TURKSME_END: |
align 16 |
CAICOSME_START: |
file 'firmware/CAICOS_me.bin' |
CAICOSME_END: |
align 16 |
CAYMANME_START: |
file 'firmware/CAYMAN_me.bin' |
CAYMANME_END: |
align 16 |
RV610PFP_START: |
file 'firmware/RV610_pfp.bin' |
RV610PFP_END: |
542,27 → 476,9 |
file 'firmware/SUMO2_pfp.bin' |
SUMO2PFP_END: |
align 16 |
BARTSPFP_START: |
file 'firmware/BARTS_pfp.bin' |
BARTSPFP_END: |
align 16 |
TURKSPFP_START: |
file 'firmware/TURKS_pfp.bin' |
TURKSPFP_END: |
align 16 |
CAICOSPFP_START: |
file 'firmware/CAICOS_pfp.bin' |
CAICOSPFP_END: |
align 16 |
CAYMANPFP_START: |
file 'firmware/CAYMAN_pfp.bin' |
CAYMANPFP_END: |
align 16 |
R600RLC_START: |
file 'firmware/R600_rlc.bin' |
R600RLC_END: |
596,34 → 512,3 |
SUMORLC_START: |
file 'firmware/SUMO_rlc.bin' |
SUMORLC_END: |
align 16 |
BTCRLC_START: |
file 'firmware/BTC_rlc.bin' |
BTCRLC_END: |
align 16 |
CAYMANRLC_START: |
file 'firmware/CAYMAN_rlc.bin' |
CAYMANRLC_END: |
align 16 |
BARTSMC_START: |
file 'firmware/BARTS_mc.bin' |
BARTSMC_END: |
align 16 |
TURKSMC_START: |
file 'firmware/TURKS_mc.bin' |
TURKSMC_END: |
align 16 |
CAICOSMC_START: |
file 'firmware/CAICOS_mc.bin' |
CAICOSMC_END: |
align 16 |
CAYMANMC_START: |
file 'firmware/CAYMAN_mc.bin' |
CAYMANMC_END: |
/drivers/video/drm/radeon/ni.c |
---|
31,7 → 31,7 |
#include "nid.h" |
#include "atom.h" |
#include "ni_reg.h" |
#include "cayman_blit_shaders.h" |
//#include "cayman_blit_shaders.h" |
extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); |
extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); |
389,6 → 389,7 |
return err; |
} |
#if 0 |
/* |
* Core functions |
*/ |
1028,6 → 1029,12 |
} |
} |
void cayman_pcie_gart_fini(struct radeon_device *rdev) |
{ |
cayman_pcie_gart_disable(rdev); |
radeon_gart_table_vram_free(rdev); |
radeon_gart_fini(rdev); |
} |
/* |
* CP. |
1037,6 → 1044,7 |
if (enable) |
WREG32(CP_ME_CNTL, 0); |
else { |
radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); |
WREG32(SCRATCH_UMSK, 0); |
} |
1134,8 → 1142,12 |
return 0; |
} |
static void cayman_cp_fini(struct radeon_device *rdev) |
{ |
cayman_cp_enable(rdev, false); |
radeon_ring_fini(rdev); |
} |
int cayman_cp_resume(struct radeon_device *rdev) |
{ |
u32 tmp; |
1376,10 → 1388,26 |
return r; |
cayman_gpu_init(rdev); |
r = evergreen_blit_init(rdev); |
if (r) { |
evergreen_blit_fini(rdev); |
rdev->asic->copy = NULL; |
dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); |
} |
/* allocate wb buffer */ |
r = radeon_wb_init(rdev); |
if (r) |
return r; |
/* Enable IRQ */ |
r = r600_irq_init(rdev); |
if (r) { |
DRM_ERROR("radeon: IH init failed (%d).\n", r); |
radeon_irq_kms_fini(rdev); |
return r; |
} |
evergreen_irq_set(rdev); |
r = radeon_ring_init(rdev, rdev->cp.ring_size); |
if (r) |
1394,10 → 1422,54 |
return 0; |
} |
int cayman_resume(struct radeon_device *rdev) |
{ |
int r; |
/* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, |
* posting will perform necessary task to bring back GPU into good |
* shape. |
*/ |
/* post card */ |
atom_asic_init(rdev->mode_info.atom_context); |
r = cayman_startup(rdev); |
if (r) { |
DRM_ERROR("cayman startup failed on resume\n"); |
return r; |
} |
r = r600_ib_test(rdev); |
if (r) { |
DRM_ERROR("radeon: failled testing IB (%d).\n", r); |
return r; |
} |
return r; |
} |
int cayman_suspend(struct radeon_device *rdev) |
{ |
int r; |
/* FIXME: we should wait for ring to be empty */ |
cayman_cp_enable(rdev, false); |
rdev->cp.ready = false; |
evergreen_irq_suspend(rdev); |
radeon_wb_disable(rdev); |
cayman_pcie_gart_disable(rdev); |
/* unpin shaders bo */ |
r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); |
if (likely(r == 0)) { |
radeon_bo_unpin(rdev->r600_blit.shader_obj); |
radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
} |
return 0; |
} |
/* Plan is to move initialization in that function and use |
* helper function so that radeon_device_init pretty much |
* do nothing more than calling asic specific function. This |
1442,6 → 1514,9 |
/* Initialize clocks */ |
radeon_get_clock_info(rdev->ddev); |
/* Fence driver */ |
r = radeon_fence_driver_init(rdev); |
if (r) |
return r; |
/* initialize memory controller */ |
r = evergreen_mc_init(rdev); |
if (r) |
1451,10 → 1526,15 |
if (r) |
return r; |
r = radeon_irq_kms_init(rdev); |
if (r) |
return r; |
rdev->cp.ring_obj = NULL; |
r600_ring_init(rdev, 1024 * 1024); |
rdev->ih.ring_obj = NULL; |
r600_ih_ring_init(rdev, 64 * 1024); |
r = r600_pcie_gart_init(rdev); |
if (r) |
1464,10 → 1544,25 |
r = cayman_startup(rdev); |
if (r) { |
dev_err(rdev->dev, "disabling GPU acceleration\n"); |
cayman_cp_fini(rdev); |
r600_irq_fini(rdev); |
radeon_wb_fini(rdev); |
radeon_irq_kms_fini(rdev); |
cayman_pcie_gart_fini(rdev); |
rdev->accel_working = false; |
} |
if (rdev->accel_working) { |
r = radeon_ib_pool_init(rdev); |
if (r) { |
DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r); |
rdev->accel_working = false; |
} |
r = r600_ib_test(rdev); |
if (r) { |
DRM_ERROR("radeon: failed testing IB (%d).\n", r); |
rdev->accel_working = false; |
} |
} |
/* Don't start up if the MC ucode is missing. |
* The default clocks and voltages before the MC ucode |
1481,3 → 1576,19 |
return 0; |
} |
void cayman_fini(struct radeon_device *rdev) |
{ |
evergreen_blit_fini(rdev); |
cayman_cp_fini(rdev); |
r600_irq_fini(rdev); |
radeon_wb_fini(rdev); |
radeon_irq_kms_fini(rdev); |
cayman_pcie_gart_fini(rdev); |
radeon_gem_fini(rdev); |
radeon_fence_driver_fini(rdev); |
radeon_bo_fini(rdev); |
radeon_atombios_fini(rdev); |
kfree(rdev->bios); |
rdev->bios = NULL; |
} |
#endif |
/drivers/video/drm/radeon/nid.h |
---|
320,7 → 320,7 |
#define CGTS_USER_TCC_DISABLE 0x914C |
#define TCC_DISABLE_MASK 0xFFFF0000 |
#define TCC_DISABLE_SHIFT 16 |
#define CGTS_SM_CTRL_REG 0x9150 |
#define CGTS_SM_CTRL_REG 0x915C |
#define OVERRIDE (1 << 21) |
#define TA_CNTL_AUX 0x9508 |
/drivers/video/drm/radeon/radeon_asic.c |
---|
518,8 → 518,8 |
.gart_set_page = &rs600_gart_set_page, |
.ring_test = &r600_ring_test, |
// .ring_ib_execute = &r600_ring_ib_execute, |
.irq_set = &r600_irq_set, |
.irq_process = &r600_irq_process, |
// .irq_set = &r600_irq_set, |
// .irq_process = &r600_irq_process, |
.fence_ring_emit = &r600_fence_ring_emit, |
// .cs_parse = &r600_cs_parse, |
// .copy_blit = &r600_copy_blit, |
555,8 → 555,8 |
.gart_set_page = &rs600_gart_set_page, |
.ring_test = &r600_ring_test, |
// .ring_ib_execute = &r600_ring_ib_execute, |
.irq_set = &r600_irq_set, |
.irq_process = &r600_irq_process, |
// .irq_set = &r600_irq_set, |
// .irq_process = &r600_irq_process, |
.fence_ring_emit = &r600_fence_ring_emit, |
// .cs_parse = &r600_cs_parse, |
// .copy_blit = &r600_copy_blit, |
589,9 → 589,9 |
.gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
.gart_set_page = &rs600_gart_set_page, |
.ring_test = &r600_ring_test, |
.ring_ib_execute = &r600_ring_ib_execute, |
.irq_set = &r600_irq_set, |
.irq_process = &r600_irq_process, |
// .ring_ib_execute = &r600_ring_ib_execute, |
// .irq_set = &r600_irq_set, |
// .irq_process = &r600_irq_process, |
.fence_ring_emit = &r600_fence_ring_emit, |
// .cs_parse = &r600_cs_parse, |
// .copy_blit = &r600_copy_blit, |
706,24 → 706,26 |
.set_surface_reg = r600_set_surface_reg, |
.clear_surface_reg = r600_clear_surface_reg, |
.bandwidth_update = &evergreen_bandwidth_update, |
.hpd_init = &evergreen_hpd_init, |
.hpd_sense = &evergreen_hpd_sense, |
}; |
#if 0 |
static struct radeon_asic cayman_asic = { |
.init = &cayman_init, |
// .fini = &evergreen_fini, |
// .suspend = &evergreen_suspend, |
// .resume = &evergreen_resume, |
.fini = &cayman_fini, |
.suspend = &cayman_suspend, |
.resume = &cayman_resume, |
.cp_commit = &r600_cp_commit, |
.gpu_is_lockup = &cayman_gpu_is_lockup, |
.asic_reset = &cayman_asic_reset, |
.vga_set_state = &r600_vga_set_state, |
.gart_tlb_flush = &cayman_pcie_gart_tlb_flush, |
.gart_set_page = &rs600_gart_set_page, |
.ring_test = &r600_ring_test, |
// .ring_ib_execute = &r600_ring_ib_execute, |
// .irq_set = &r600_irq_set, |
// .irq_process = &r600_irq_process, |
.ring_ib_execute = &evergreen_ring_ib_execute, |
.irq_set = &evergreen_irq_set, |
.irq_process = &evergreen_irq_process, |
.get_vblank_counter = &evergreen_get_vblank_counter, |
.fence_ring_emit = &r600_fence_ring_emit, |
// .cs_parse = &r600_cs_parse, |
// .copy_blit = &r600_copy_blit, |
733,13 → 735,22 |
.set_engine_clock = &radeon_atom_set_engine_clock, |
.get_memory_clock = &radeon_atom_get_memory_clock, |
.set_memory_clock = &radeon_atom_set_memory_clock, |
.get_pcie_lanes = NULL, |
.set_pcie_lanes = NULL, |
.set_clock_gating = NULL, |
.set_surface_reg = r600_set_surface_reg, |
.clear_surface_reg = r600_clear_surface_reg, |
.bandwidth_update = &evergreen_bandwidth_update, |
.gui_idle = &r600_gui_idle, |
.pm_misc = &evergreen_pm_misc, |
.pm_prepare = &evergreen_pm_prepare, |
.pm_finish = &evergreen_pm_finish, |
.pm_init_profile = &r600_pm_init_profile, |
.pm_get_dynpm_state = &r600_pm_get_dynpm_state, |
.pre_page_flip = &evergreen_pre_page_flip, |
.page_flip = &evergreen_page_flip, |
.post_page_flip = &evergreen_post_page_flip, |
}; |
#endif |
int radeon_asic_init(struct radeon_device *rdev) |
{ |
852,11 → 863,7 |
rdev->num_crtc = 6; |
rdev->asic = &btc_asic; |
break; |
case CHIP_CAYMAN: |
rdev->asic = &cayman_asic; |
/* set num crtcs */ |
rdev->num_crtc = 6; |
break; |
default: |
/* FIXME: not supported yet */ |
return -EINVAL; |
/drivers/video/drm/radeon/radeon_device.c |
---|
197,93 → 197,6 |
} |
} |
void radeon_wb_disable(struct radeon_device *rdev) |
{ |
int r; |
if (rdev->wb.wb_obj) { |
r = radeon_bo_reserve(rdev->wb.wb_obj, false); |
if (unlikely(r != 0)) |
return; |
radeon_bo_kunmap(rdev->wb.wb_obj); |
radeon_bo_unpin(rdev->wb.wb_obj); |
radeon_bo_unreserve(rdev->wb.wb_obj); |
} |
rdev->wb.enabled = false; |
} |
void radeon_wb_fini(struct radeon_device *rdev) |
{ |
radeon_wb_disable(rdev); |
if (rdev->wb.wb_obj) { |
radeon_bo_unref(&rdev->wb.wb_obj); |
rdev->wb.wb = NULL; |
rdev->wb.wb_obj = NULL; |
} |
} |
int radeon_wb_init(struct radeon_device *rdev) |
{ |
int r; |
if (rdev->wb.wb_obj == NULL) { |
r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, |
RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj); |
if (r) { |
dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); |
return r; |
} |
} |
r = radeon_bo_reserve(rdev->wb.wb_obj, false); |
if (unlikely(r != 0)) { |
radeon_wb_fini(rdev); |
return r; |
} |
r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, |
&rdev->wb.gpu_addr); |
if (r) { |
radeon_bo_unreserve(rdev->wb.wb_obj); |
dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); |
radeon_wb_fini(rdev); |
return r; |
} |
r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); |
radeon_bo_unreserve(rdev->wb.wb_obj); |
if (r) { |
dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); |
radeon_wb_fini(rdev); |
return r; |
} |
/* cle |