| /drivers/video/drm/drm_crtc.c |
|---|
| 886,9 → 886,6 |
| total_objects += dev->mode_config.num_connector; |
| total_objects += dev->mode_config.num_encoder; |
| if (total_objects == 0) |
| return -EINVAL; |
| group->id_list = kzalloc(total_objects * sizeof(uint32_t), GFP_KERNEL); |
| if (!group->id_list) |
| return -ENOMEM; |
| /drivers/video/drm/drm_edid.c |
|---|
| 184,9 → 184,9 |
| bad: |
| if (raw_edid) { |
| DRM_ERROR("Raw EDID:\n"); |
| printk(KERN_ERR "Raw EDID:\n"); |
| // print_hex_dump_bytes(KERN_ERR, DUMP_PREFIX_NONE, raw_edid, EDID_LENGTH); |
| // printk("\n"); |
| printk(KERN_ERR "\n"); |
| } |
| return 0; |
| } |
| 258,6 → 258,17 |
| return ret == 2 ? 0 : -1; |
| } |
| static bool drm_edid_is_zero(u8 *in_edid, int length) |
| { |
| int i; |
| u32 *raw_edid = (u32 *)in_edid; |
| for (i = 0; i < length / 4; i++) |
| if (*(raw_edid + i) != 0) |
| return false; |
| return true; |
| } |
| static u8 * |
| drm_do_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) |
| { |
| 274,6 → 285,10 |
| goto out; |
| if (drm_edid_block_valid(block)) |
| break; |
| if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) { |
| connector->null_edid_counter++; |
| goto carp; |
| } |
| } |
| if (i == 4) |
| goto carp; |
| /drivers/video/drm/drm_fb_helper.c |
|---|
| 924,7 → 924,7 |
| /* clean out all the encoder/crtc combos */ |
| list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| // encoder->crtc = NULL; |
| encoder->crtc = NULL; |
| } |
| crtcs = kcalloc(dev->mode_config.num_connector, |
| /drivers/video/drm/radeon/Makefile |
|---|
| 55,20 → 55,23 |
| radeon_device.c \ |
| evergreen.c \ |
| evergreen_blit_shaders.c \ |
| cayman_blit_shaders.c \ |
| radeon_clocks.c \ |
| radeon_i2c.c \ |
| atom.c \ |
| ni.c \ |
| radeon_gem.c \ |
| radeon_atombios.c \ |
| radeon_agp.c \ |
| radeon_asic.c \ |
| radeon_atombios.c \ |
| radeon_bios.c \ |
| radeon_combios.c \ |
| radeon_connectors.c \ |
| atombios_crtc.c \ |
| atombios_dp.c \ |
| radeon_encoders.c \ |
| radeon_connectors.c \ |
| radeon_bios.c \ |
| radeon_combios.c \ |
| radeon_fence.c \ |
| radeon_gem.c \ |
| radeon_i2c.c \ |
| radeon_irq_kms.c \ |
| radeon_legacy_crtc.c \ |
| radeon_legacy_encoders.c \ |
| radeon_legacy_tv.c \ |
| /drivers/video/drm/radeon/Makefile.lto |
|---|
| 55,20 → 55,23 |
| radeon_device.c \ |
| evergreen.c \ |
| evergreen_blit_shaders.c \ |
| cayman_blit_shaders.c \ |
| radeon_clocks.c \ |
| radeon_i2c.c \ |
| atom.c \ |
| ni.c \ |
| radeon_gem.c \ |
| radeon_atombios.c \ |
| radeon_agp.c \ |
| radeon_asic.c \ |
| radeon_atombios.c \ |
| radeon_bios.c \ |
| radeon_combios.c \ |
| radeon_connectors.c \ |
| atombios_crtc.c \ |
| atombios_dp.c \ |
| radeon_encoders.c \ |
| radeon_connectors.c \ |
| radeon_bios.c \ |
| radeon_combios.c \ |
| radeon_fence.c \ |
| radeon_gem.c \ |
| radeon_i2c.c \ |
| radeon_irq_kms.c \ |
| radeon_legacy_crtc.c \ |
| radeon_legacy_encoders.c \ |
| radeon_legacy_tv.c \ |
| /drivers/video/drm/radeon/cayman_blit_shaders.c |
|---|
| 0,0 → 1,373 |
| /* |
| * Copyright 2010 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| * DEALINGS IN THE SOFTWARE. |
| * |
| * Authors: |
| * Alex Deucher <alexander.deucher@amd.com> |
| */ |
| #include <linux/types.h> |
| #include <linux/kernel.h> |
| /* |
| * evergreen cards need to use the 3D engine to blit data which requires |
| * quite a bit of hw state setup. Rather than pull the whole 3D driver |
| * (which normally generates the 3D state) into the DRM, we opt to use |
| * statically generated state tables. The regsiter state and shaders |
| * were hand generated to support blitting functionality. See the 3D |
| * driver or documentation for descriptions of the registers and |
| * shader instructions. |
| */ |
| const u32 cayman_default_state[] = |
| { |
| 0xc0066900, |
| 0x00000000, |
| 0x00000060, /* DB_RENDER_CONTROL */ |
| 0x00000000, /* DB_COUNT_CONTROL */ |
| 0x00000000, /* DB_DEPTH_VIEW */ |
| 0x0000002a, /* DB_RENDER_OVERRIDE */ |
| 0x00000000, /* DB_RENDER_OVERRIDE2 */ |
| 0x00000000, /* DB_HTILE_DATA_BASE */ |
| 0xc0026900, |
| 0x0000000a, |
| 0x00000000, /* DB_STENCIL_CLEAR */ |
| 0x00000000, /* DB_DEPTH_CLEAR */ |
| 0xc0036900, |
| 0x0000000f, |
| 0x00000000, /* DB_DEPTH_INFO */ |
| 0x00000000, /* DB_Z_INFO */ |
| 0x00000000, /* DB_STENCIL_INFO */ |
| 0xc0016900, |
| 0x00000080, |
| 0x00000000, /* PA_SC_WINDOW_OFFSET */ |
| 0xc00d6900, |
| 0x00000083, |
| 0x0000ffff, /* PA_SC_CLIPRECT_RULE */ |
| 0x00000000, /* PA_SC_CLIPRECT_0_TL */ |
| 0x20002000, /* PA_SC_CLIPRECT_0_BR */ |
| 0x00000000, |
| 0x20002000, |
| 0x00000000, |
| 0x20002000, |
| 0x00000000, |
| 0x20002000, |
| 0xaaaaaaaa, /* PA_SC_EDGERULE */ |
| 0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */ |
| 0x0000000f, /* CB_TARGET_MASK */ |
| 0x0000000f, /* CB_SHADER_MASK */ |
| 0xc0226900, |
| 0x00000094, |
| 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */ |
| 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */ |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x00000000, /* PA_SC_VPORT_ZMIN_0 */ |
| 0x3f800000, /* PA_SC_VPORT_ZMAX_0 */ |
| 0xc0016900, |
| 0x000000d4, |
| 0x00000000, /* SX_MISC */ |
| 0xc0026900, |
| 0x000000d9, |
| 0x00000000, /* CP_RINGID */ |
| 0x00000000, /* CP_VMID */ |
| 0xc0096900, |
| 0x00000100, |
| 0x00ffffff, /* VGT_MAX_VTX_INDX */ |
| 0x00000000, /* VGT_MIN_VTX_INDX */ |
| 0x00000000, /* VGT_INDX_OFFSET */ |
| 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */ |
| 0x00000000, /* SX_ALPHA_TEST_CONTROL */ |
| 0x00000000, /* CB_BLEND_RED */ |
| 0x00000000, /* CB_BLEND_GREEN */ |
| 0x00000000, /* CB_BLEND_BLUE */ |
| 0x00000000, /* CB_BLEND_ALPHA */ |
| 0xc0016900, |
| 0x00000187, |
| 0x00000100, /* SPI_VS_OUT_ID_0 */ |
| 0xc0026900, |
| 0x00000191, |
| 0x00000100, /* SPI_PS_INPUT_CNTL_0 */ |
| 0x00000101, /* SPI_PS_INPUT_CNTL_1 */ |
| 0xc0016900, |
| 0x000001b1, |
| 0x00000000, /* SPI_VS_OUT_CONFIG */ |
| 0xc0106900, |
| 0x000001b3, |
| 0x20000001, /* SPI_PS_IN_CONTROL_0 */ |
| 0x00000000, /* SPI_PS_IN_CONTROL_1 */ |
| 0x00000000, /* SPI_INTERP_CONTROL_0 */ |
| 0x00000000, /* SPI_INPUT_Z */ |
| 0x00000000, /* SPI_FOG_CNTL */ |
| 0x00100000, /* SPI_BARYC_CNTL */ |
| 0x00000000, /* SPI_PS_IN_CONTROL_2 */ |
| 0x00000000, /* SPI_COMPUTE_INPUT_CNTL */ |
| 0x00000000, /* SPI_COMPUTE_NUM_THREAD_X */ |
| 0x00000000, /* SPI_COMPUTE_NUM_THREAD_Y */ |
| 0x00000000, /* SPI_COMPUTE_NUM_THREAD_Z */ |
| 0x00000000, /* SPI_GPR_MGMT */ |
| 0x00000000, /* SPI_LDS_MGMT */ |
| 0x00000000, /* SPI_STACK_MGMT */ |
| 0x00000000, /* SPI_WAVE_MGMT_1 */ |
| 0x00000000, /* SPI_WAVE_MGMT_2 */ |
| 0xc0016900, |
| 0x000001e0, |
| 0x00000000, /* CB_BLEND0_CONTROL */ |
| 0xc00e6900, |
| 0x00000200, |
| 0x00000000, /* DB_DEPTH_CONTROL */ |
| 0x00000000, /* DB_EQAA */ |
| 0x00cc0010, /* CB_COLOR_CONTROL */ |
| 0x00000210, /* DB_SHADER_CONTROL */ |
| 0x00010000, /* PA_CL_CLIP_CNTL */ |
| 0x00000004, /* PA_SU_SC_MODE_CNTL */ |
| 0x00000100, /* PA_CL_VTE_CNTL */ |
| 0x00000000, /* PA_CL_VS_OUT_CNTL */ |
| 0x00000000, /* PA_CL_NANINF_CNTL */ |
| 0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */ |
| 0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */ |
| 0x00000000, /* PA_SU_PRIM_FILTER_CNTL */ |
| 0x00000000, /* */ |
| 0x00000000, /* */ |
| 0xc0026900, |
| 0x00000229, |
| 0x00000000, /* SQ_PGM_START_FS */ |
| 0x00000000, |
| 0xc0016900, |
| 0x0000023b, |
| 0x00000000, /* SQ_LDS_ALLOC_PS */ |
| 0xc0066900, |
| 0x00000240, |
| 0x00000000, /* SQ_ESGS_RING_ITEMSIZE */ |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0xc0046900, |
| 0x00000247, |
| 0x00000000, /* SQ_GS_VERT_ITEMSIZE */ |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0xc0116900, |
| 0x00000280, |
| 0x00000000, /* PA_SU_POINT_SIZE */ |
| 0x00000000, /* PA_SU_POINT_MINMAX */ |
| 0x00000008, /* PA_SU_LINE_CNTL */ |
| 0x00000000, /* PA_SC_LINE_STIPPLE */ |
| 0x00000000, /* VGT_OUTPUT_PATH_CNTL */ |
| 0x00000000, /* VGT_HOS_CNTL */ |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, /* VGT_GS_MODE */ |
| 0xc0026900, |
| 0x00000292, |
| 0x00000000, /* PA_SC_MODE_CNTL_0 */ |
| 0x00000000, /* PA_SC_MODE_CNTL_1 */ |
| 0xc0016900, |
| 0x000002a1, |
| 0x00000000, /* VGT_PRIMITIVEID_EN */ |
| 0xc0016900, |
| 0x000002a5, |
| 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */ |
| 0xc0026900, |
| 0x000002a8, |
| 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */ |
| 0x00000000, |
| 0xc0026900, |
| 0x000002ad, |
| 0x00000000, /* VGT_REUSE_OFF */ |
| 0x00000000, |
| 0xc0016900, |
| 0x000002d5, |
| 0x00000000, /* VGT_SHADER_STAGES_EN */ |
| 0xc0016900, |
| 0x000002dc, |
| 0x0000aa00, /* DB_ALPHA_TO_MASK */ |
| 0xc0066900, |
| 0x000002de, |
| 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */ |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0xc0026900, |
| 0x000002e5, |
| 0x00000000, /* VGT_STRMOUT_CONFIG */ |
| 0x00000000, |
| 0xc01b6900, |
| 0x000002f5, |
| 0x76543210, /* PA_SC_CENTROID_PRIORITY_0 */ |
| 0xfedcba98, /* PA_SC_CENTROID_PRIORITY_1 */ |
| 0x00000000, /* PA_SC_LINE_CNTL */ |
| 0x00000000, /* PA_SC_AA_CONFIG */ |
| 0x00000005, /* PA_SU_VTX_CNTL */ |
| 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */ |
| 0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */ |
| 0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */ |
| 0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */ |
| 0x00000000, /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */ |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0xffffffff, /* PA_SC_AA_MASK_X0Y0_X1Y0 */ |
| 0xffffffff, |
| 0xc0026900, |
| 0x00000316, |
| 0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */ |
| 0x00000010, /* */ |
| }; |
| const u32 cayman_vs[] = |
| { |
| 0x00000004, |
| 0x80400400, |
| 0x0000a03c, |
| 0x95000688, |
| 0x00004000, |
| 0x15000688, |
| 0x00000000, |
| 0x88000000, |
| 0x04000000, |
| 0x67961001, |
| #ifdef __BIG_ENDIAN |
| 0x00020000, |
| #else |
| 0x00000000, |
| #endif |
| 0x00000000, |
| 0x04000000, |
| 0x67961000, |
| #ifdef __BIG_ENDIAN |
| 0x00020008, |
| #else |
| 0x00000008, |
| #endif |
| 0x00000000, |
| }; |
| const u32 cayman_ps[] = |
| { |
| 0x00000004, |
| 0xa00c0000, |
| 0x00000008, |
| 0x80400000, |
| 0x00000000, |
| 0x95000688, |
| 0x00000000, |
| 0x88000000, |
| 0x00380400, |
| 0x00146b10, |
| 0x00380000, |
| 0x20146b10, |
| 0x00380400, |
| 0x40146b00, |
| 0x80380000, |
| 0x60146b00, |
| 0x00000010, |
| 0x000d1000, |
| 0xb0800000, |
| 0x00000000, |
| }; |
| const u32 cayman_ps_size = ARRAY_SIZE(cayman_ps); |
| const u32 cayman_vs_size = ARRAY_SIZE(cayman_vs); |
| const u32 cayman_default_size = ARRAY_SIZE(cayman_default_state); |
| /drivers/video/drm/radeon/cayman_blit_shaders.h |
|---|
| 0,0 → 1,35 |
| /* |
| * Copyright 2010 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| * DEALINGS IN THE SOFTWARE. |
| * |
| */ |
| #ifndef CAYMAN_BLIT_SHADERS_H |
| #define CAYMAN_BLIT_SHADERS_H |
| extern const u32 cayman_ps[]; |
| extern const u32 cayman_vs[]; |
| extern const u32 cayman_default_state[]; |
| extern const u32 cayman_ps_size, cayman_vs_size; |
| extern const u32 cayman_default_size; |
| #endif |
| /drivers/video/drm/radeon/evergreen.c |
|---|
| 281,7 → 281,6 |
| } |
| } |
| #if 0 |
| void evergreen_hpd_init(struct radeon_device *rdev) |
| { |
| struct drm_device *dev = rdev->ddev; |
| 320,10 → 319,12 |
| break; |
| } |
| } |
| if (rdev->irq.installed) |
| evergreen_irq_set(rdev); |
| // if (rdev->irq.installed) |
| // evergreen_irq_set(rdev); |
| } |
| #if 0 |
| void evergreen_hpd_fini(struct radeon_device *rdev) |
| { |
| struct drm_device *dev = rdev->ddev; |
| 2240,6 → 2241,9 |
| /* Get VRAM informations */ |
| rdev->mc.vram_is_ddr = true; |
| if (rdev->flags & RADEON_IS_IGP) |
| tmp = RREG32(FUS_MC_ARB_RAMCFG); |
| else |
| tmp = RREG32(MC_ARB_RAMCFG); |
| if (tmp & CHANSIZE_OVERRIDE) { |
| chansize = 16; |
| /drivers/video/drm/radeon/evergreend.h |
|---|
| 466,7 → 466,7 |
| #define IH_RB_WPTR_ADDR_LO 0x3e14 |
| #define IH_CNTL 0x3e18 |
| # define ENABLE_INTR (1 << 0) |
| # define IH_MC_SWAP(x) ((x) << 2) |
| # define IH_MC_SWAP(x) ((x) << 1) |
| # define IH_MC_SWAP_NONE 0 |
| # define IH_MC_SWAP_16BIT 1 |
| # define IH_MC_SWAP_32BIT 2 |
| 547,7 → 547,7 |
| # define LB_D5_VBLANK_INTERRUPT (1 << 3) |
| # define DC_HPD5_INTERRUPT (1 << 17) |
| # define DC_HPD5_RX_INTERRUPT (1 << 18) |
| #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6050 |
| #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 |
| # define LB_D6_VLINE_INTERRUPT (1 << 2) |
| # define LB_D6_VBLANK_INTERRUPT (1 << 3) |
| # define DC_HPD6_INTERRUPT (1 << 17) |
| /drivers/video/drm/radeon/fwblob.asm |
|---|
| 114,11 → 114,29 |
| dd SUMOME_START |
| dd (SUMOME_END - SUMOME_START) |
| dd FIRMWARE_SUMO2_ME |
| dd SUMO2ME_START |
| dd (SUMO2ME_END - SUMO2ME_START) |
| macro ni_code [arg] |
| { |
| dd FIRMWARE_#arg#_ME |
| dd arg#ME_START |
| dd (arg#ME_END - arg#ME_START) |
| dd FIRMWARE_#arg#_PFP |
| dd arg#PFP_START |
| dd (arg#PFP_END - arg#PFP_START) |
| dd FIRMWARE_#arg#_MC |
| dd arg#MC_START |
| dd (arg#MC_END - arg#MC_START) |
| } |
| ni_code BARTS, TURKS, CAICOS, CAYMAN |
| dd FIRMWARE_RV610_PFP |
| dd RV610PFP_START |
| dd (RV610PFP_END - RV610PFP_START) |
| 180,6 → 198,9 |
| dd SUMO2PFP_START |
| dd (SUMO2PFP_END - SUMO2PFP_START) |
| dd FIRMWARE_BARTS_PFP |
| dd BARTSPFP_START |
| dd (BARTSPFP_END - BARTSPFP_START) |
| dd FIRMWARE_R600_RLC |
| 206,10 → 227,15 |
| dd JUNIPERRLC_START |
| dd (JUNIPERRLC_END - JUNIPERRLC_START) |
| dd FIRMWARE_BTC_RLC |
| dd BTCRLC_START |
| dd (BTCRLC_END - BTCRLC_START) |
| dd FIRMWARE_SUMO_RLC |
| dd SUMORLC_START |
| dd (SUMORLC_END - SUMORLC_START) |
| ___end_builtin_fw: |
| 223,7 → 249,6 |
| FIRMWARE_RS690_CP db 'radeon/RS690_cp.bin',0 |
| FIRMWARE_RS780_ME db 'radeon/RS780_me.bin',0 |
| FIRMWARE_RS780_PFP db 'radeon/RS780_pfp.bin',0 |
| FIRMWARE_R600_ME db 'radeon/RV600_me.bin',0 |
| FIRMWARE_RV610_ME db 'radeon/RV610_me.bin',0 |
| 234,6 → 259,7 |
| FIRMWARE_RV710_ME db 'radeon/RV710_me.bin',0 |
| FIRMWARE_RV730_ME db 'radeon/RV730_me.bin',0 |
| FIRMWARE_RV770_ME db 'radeon/RV770_me.bin',0 |
| FIRMWARE_CYPRESS_ME db 'radeon/CYPRESS_me.bin',0 |
| FIRMWARE_REDWOOD_ME db 'radeon/REDWOOD_me.bin',0 |
| FIRMWARE_CEDAR_ME db 'radeon/CEDAR_me.bin',0 |
| 242,7 → 268,13 |
| FIRMWARE_SUMO_ME db 'radeon/SUMO_me.bin',0 |
| FIRMWARE_SUMO2_ME db 'radeon/SUMO2_me.bin',0 |
| FIRMWARE_BARTS_ME db 'radeon/BARTS_me.bin',0 |
| FIRMWARE_TURKS_ME db 'radeon/TURKS_me.bin',0 |
| FIRMWARE_CAICOS_ME db 'radeon/CAICOS_me.bin',0 |
| FIRMWARE_CAYMAN_ME db 'radeon/CAYMAN_me.bin',0 |
| FIRMWARE_RS780_PFP db 'radeon/RS780_pfp.bin',0 |
| FIRMWARE_R600_PFP db 'radeon/R600_pfp.bin',0 |
| FIRMWARE_RV610_PFP db 'radeon/RV610_pfp.bin',0 |
| FIRMWARE_RV620_PFP db 'radeon/RV620_pfp.bin',0 |
| 252,6 → 284,7 |
| FIRMWARE_RV710_PFP db 'radeon/RV710_pfp.bin',0 |
| FIRMWARE_RV730_PFP db 'radeon/RV730_pfp.bin',0 |
| FIRMWARE_RV770_PFP db 'radeon/RV770_pfp.bin',0 |
| FIRMWARE_CYPRESS_PFP db 'radeon/CYPRESS_pfp.bin',0 |
| FIRMWARE_REDWOOD_PFP db 'radeon/REDWOOD_pfp.bin',0 |
| FIRMWARE_CEDAR_PFP db 'radeon/CEDAR_pfp.bin',0 |
| 260,7 → 293,12 |
| FIRMWARE_SUMO_PFP db 'radeon/SUMO_pfp.bin',0 |
| FIRMWARE_SUMO2_PFP db 'radeon/SUMO2_pfp.bin',0 |
| FIRMWARE_BARTS_PFP db 'radeon/BARTS_pfp.bin',0 |
| FIRMWARE_TURKS_PFP db 'radeon/TURKS_pfp.bin',0 |
| FIRMWARE_CAICOS_PFP db 'radeon/CAICOS_pfp.bin',0 |
| FIRMWARE_CAYMAN_PFP db 'radeon/CAYMAN_pfp.bin',0 |
| FIRMWARE_R600_RLC db 'radeon/R600_rlc.bin',0 |
| FIRMWARE_R700_RLC db 'radeon/R700_rlc.bin',0 |
| FIRMWARE_CYPRESS_RLC db 'radeon/CYPRESS_rlc.bin',0 |
| 268,8 → 306,16 |
| FIRMWARE_CEDAR_RLC db 'radeon/CEDAR_rlc.bin',0 |
| FIRMWARE_JUNIPER_RLC db 'radeon/JUNIPER_rlc.bin',0 |
| FIRMWARE_SUMO_RLC db 'radeon/SUMO_rlc.bin',0 |
| FIRMWARE_BTC_RLC db 'radeon/BTC_rlc.bin',0 |
| FIRMWARE_CAYMAN_RLC db 'radeon/CAYMAN_rlc.bin',0 |
| FIRMWARE_BARTS_MC db 'radeon/BARTS_mc.bin',0 |
| FIRMWARE_TURKS_MC db 'radeon/TURKS_mc.bin',0 |