| /drivers/video/drm/drm_crtc_helper.c |
|---|
| 32,7 → 32,6 |
| #include "drmP.h" |
| #include "drm_crtc.h" |
| #include "drm_crtc_helper.h" |
| #include "drm_fb_helper.h" |
| static void drm_mode_validate_flag(struct drm_connector *connector, |
| int flags) |
| 91,14 → 90,6 |
| list_for_each_entry_safe(mode, t, &connector->modes, head) |
| mode->status = MODE_UNVERIFIED; |
| if (connector->force) { |
| if (connector->force == DRM_FORCE_ON) |
| connector->status = connector_status_connected; |
| else |
| connector->status = connector_status_disconnected; |
| if (connector->funcs->force) |
| connector->funcs->force(connector); |
| } else |
| connector->status = connector->funcs->detect(connector); |
| if (connector->status == connector_status_disconnected) { |
| 276,65 → 267,6 |
| return NULL; |
| } |
| static bool drm_has_cmdline_mode(struct drm_connector *connector) |
| { |
| struct drm_fb_helper_connector *fb_help_conn = connector->fb_helper_private; |
| struct drm_fb_helper_cmdline_mode *cmdline_mode; |
| if (!fb_help_conn) |
| return false; |
| cmdline_mode = &fb_help_conn->cmdline_mode; |
| return cmdline_mode->specified; |
| } |
| static struct drm_display_mode *drm_pick_cmdline_mode(struct drm_connector *connector, int width, int height) |
| { |
| struct drm_fb_helper_connector *fb_help_conn = connector->fb_helper_private; |
| struct drm_fb_helper_cmdline_mode *cmdline_mode; |
| struct drm_display_mode *mode = NULL; |
| if (!fb_help_conn) |
| return mode; |
| cmdline_mode = &fb_help_conn->cmdline_mode; |
| if (cmdline_mode->specified == false) |
| return mode; |
| /* attempt to find a matching mode in the list of modes |
| * we have gotten so far, if not add a CVT mode that conforms |
| */ |
| if (cmdline_mode->rb || cmdline_mode->margins) |
| goto create_mode; |
| list_for_each_entry(mode, &connector->modes, head) { |
| /* check width/height */ |
| if (mode->hdisplay != cmdline_mode->xres || |
| mode->vdisplay != cmdline_mode->yres) |
| continue; |
| if (cmdline_mode->refresh_specified) { |
| if (mode->vrefresh != cmdline_mode->refresh) |
| continue; |
| } |
| if (cmdline_mode->interlace) { |
| if (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) |
| continue; |
| } |
| return mode; |
| } |
| create_mode: |
| mode = drm_cvt_mode(connector->dev, cmdline_mode->xres, |
| cmdline_mode->yres, |
| cmdline_mode->refresh_specified ? cmdline_mode->refresh : 60, |
| cmdline_mode->rb, cmdline_mode->interlace, |
| cmdline_mode->margins); |
| list_add(&mode->head, &connector->modes); |
| return mode; |
| } |
| static bool drm_connector_enabled(struct drm_connector *connector, bool strict) |
| { |
| bool enable; |
| 385,16 → 317,10 |
| continue; |
| } |
| DRM_DEBUG_KMS("looking for cmdline mode on connector %d\n", |
| DRM_DEBUG_KMS("looking for preferred mode on connector %d\n", |
| connector->base.id); |
| /* got for command line mode first */ |
| modes[i] = drm_pick_cmdline_mode(connector, width, height); |
| if (!modes[i]) { |
| DRM_DEBUG_KMS("looking for preferred mode on connector %d\n", |
| connector->base.id); |
| modes[i] = drm_has_preferred_mode(connector, width, height); |
| } |
| /* No preferred modes, pick one off the list */ |
| if (!modes[i] && !list_empty(&connector->modes)) { |
| list_for_each_entry(modes[i], &connector->modes, head) |
| 443,8 → 369,6 |
| my_score = 1; |
| if (connector->status == connector_status_connected) |
| my_score++; |
| if (drm_has_cmdline_mode(connector)) |
| my_score++; |
| if (drm_has_preferred_mode(connector, width, height)) |
| my_score++; |
| 544,6 → 468,7 |
| DRM_DEBUG_KMS("desired mode %s set on crtc %d\n", |
| mode->name, crtc->base.id); |
| crtc->desired_mode = mode; |
| crtc->enabled = true; |
| connector->encoder->crtc = crtc; |
| } else { |
| connector->encoder->crtc = NULL; |
| /drivers/video/drm/radeon/r600d.h |
|---|
| File deleted |
| /drivers/video/drm/radeon/rdisplay.c |
|---|
| File deleted |
| /drivers/video/drm/radeon/atikms.asm |
|---|
| File deleted |
| /drivers/video/drm/radeon/radeon_agp.c |
|---|
| File deleted |
| /drivers/video/drm/radeon/rs100d.h |
|---|
| File deleted |
| /drivers/video/drm/radeon/rv200d.h |
|---|
| File deleted |
| /drivers/video/drm/radeon/rv250d.h |
|---|
| File deleted |
| /drivers/video/drm/radeon/rv350d.h |
|---|
| File deleted |
| /drivers/video/drm/radeon/rs400d.h |
|---|
| File deleted |
| /drivers/video/drm/radeon/rs600d.h |
|---|
| File deleted |
| /drivers/video/drm/radeon/rs690d.h |
|---|
| File deleted |
| /drivers/video/drm/radeon/rv770d.h |
|---|
| File deleted |
| /drivers/video/drm/radeon/r520d.h |
|---|
| File deleted |
| /drivers/video/drm/radeon/atombios_crtc.c |
|---|
| 736,7 → 736,6 |
| .mode_set_base = atombios_crtc_set_base, |
| .prepare = atombios_crtc_prepare, |
| .commit = atombios_crtc_commit, |
| .load_lut = radeon_crtc_load_lut, |
| }; |
| void radeon_atombios_init_crtc(struct drm_device *dev, |
| /drivers/video/drm/radeon/makefile |
|---|
| 18,9 → 18,9 |
| HFILES:= $(DRM_INCLUDES)/linux/types.h \ |
| $(DRM_INCLUDES)/linux/list.h \ |
| $(DRM_INCLUDES)/pci.h \ |
| $(DRM_INCLUDES)/drm/drm.h \ |
| $(DRM_INCLUDES)/drm.h \ |
| $(DRM_INCLUDES)/drm/drmP.h \ |
| $(DRM_INCLUDES)/drm/drm_edid.h \ |
| $(DRM_INCLUDES)/drm_edid.h \ |
| $(DRM_INCLUDES)/drm/drm_crtc.h \ |
| $(DRM_INCLUDES)/drm/drm_mode.h \ |
| $(DRM_INCLUDES)/drm/drm_mm.h \ |
| 45,7 → 45,6 |
| radeon_i2c.c \ |
| atom.c \ |
| radeon_atombios.c \ |
| radeon_agp.c \ |
| atombios_crtc.c \ |
| radeon_encoders.c \ |
| radeon_connectors.c \ |
| 55,6 → 54,7 |
| radeon_legacy_encoders.c \ |
| radeon_legacy_tv.c \ |
| radeon_display.c \ |
| radeon_cursor.c \ |
| radeon_object.c \ |
| radeon_gart.c \ |
| radeon_ring.c \ |
| 64,6 → 64,7 |
| r420.c \ |
| rv515.c \ |
| r520.c \ |
| r600.c \ |
| rs400.c \ |
| rs600.c \ |
| rs690.c \ |
| /drivers/video/drm/radeon/radeon_device.c |
|---|
| 29,14 → 29,12 |
| #include <drm/drmP.h> |
| #include <drm/drm_crtc_helper.h> |
| #include <drm/radeon_drm.h> |
| #include "radeon_drm.h" |
| #include "radeon_reg.h" |
| #include "radeon.h" |
| #include "radeon_asic.h" |
| #include "atom.h" |
| #include <drm/drm_pciids.h> |
| #include <syscall.h> |
| int radeon_dynclks = -1; |
| 275,14 → 273,14 |
| rdev->mc_rreg = &rs400_mc_rreg; |
| rdev->mc_wreg = &rs400_mc_wreg; |
| } |
| if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { |
| rdev->mc_rreg = &rs690_mc_rreg; |
| rdev->mc_wreg = &rs690_mc_wreg; |
| } |
| if (rdev->family == CHIP_RS600) { |
| rdev->mc_rreg = &rs600_mc_rreg; |
| rdev->mc_wreg = &rs600_mc_wreg; |
| } |
| // if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { |
| // rdev->mc_rreg = &rs690_mc_rreg; |
| // rdev->mc_wreg = &rs690_mc_wreg; |
| // } |
| // if (rdev->family == CHIP_RS600) { |
| // rdev->mc_rreg = &rs600_mc_rreg; |
| // rdev->mc_wreg = &rs600_mc_wreg; |
| // } |
| // if (rdev->family >= CHIP_R600) { |
| // rdev->pciep_rreg = &r600_pciep_rreg; |
| // rdev->pciep_wreg = &r600_pciep_wreg; |
| 314,6 → 312,10 |
| case CHIP_RV380: |
| rdev->asic = &r300_asic; |
| if (rdev->flags & RADEON_IS_PCIE) { |
| rdev->asic->gart_init = &rv370_pcie_gart_init; |
| rdev->asic->gart_fini = &rv370_pcie_gart_fini; |
| rdev->asic->gart_enable = &rv370_pcie_gart_enable; |
| rdev->asic->gart_disable = &rv370_pcie_gart_disable; |
| rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; |
| rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; |
| } |
| 328,11 → 330,11 |
| rdev->asic = &rs400_asic; |
| break; |
| case CHIP_RS600: |
| rdev->asic = &rs600_asic; |
| // rdev->asic = &rs600_asic; |
| break; |
| case CHIP_RS690: |
| case CHIP_RS740: |
| rdev->asic = &rs690_asic; |
| // rdev->asic = &rs690_asic; |
| break; |
| case CHIP_RV515: |
| rdev->asic = &rv515_asic; |
| 351,15 → 353,9 |
| case CHIP_RV635: |
| case CHIP_RV670: |
| case CHIP_RS780: |
| case CHIP_RS880: |
| // rdev->asic = &r600_asic; |
| break; |
| case CHIP_RV770: |
| case CHIP_RV730: |
| case CHIP_RV710: |
| case CHIP_RV740: |
| // rdev->asic = &rv770_asic; |
| break; |
| default: |
| /* FIXME: not supported yet */ |
| return -EINVAL; |
| 476,27 → 472,6 |
| int radeon_modeset_init(struct radeon_device *rdev); |
| void radeon_modeset_fini(struct radeon_device *rdev); |
| void radeon_agp_disable(struct radeon_device *rdev) |
| { |
| rdev->flags &= ~RADEON_IS_AGP; |
| if (rdev->family >= CHIP_R600) { |
| DRM_INFO("Forcing AGP to PCIE mode\n"); |
| rdev->flags |= RADEON_IS_PCIE; |
| } else if (rdev->family >= CHIP_RV515 || |
| rdev->family == CHIP_RV380 || |
| rdev->family == CHIP_RV410 || |
| rdev->family == CHIP_R423) { |
| DRM_INFO("Forcing AGP to PCIE mode\n"); |
| rdev->flags |= RADEON_IS_PCIE; |
| rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; |
| rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; |
| } else { |
| DRM_INFO("Forcing AGP to PCI mode\n"); |
| rdev->flags |= RADEON_IS_PCI; |
| rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; |
| rdev->asic->gart_set_page = &r100_pci_gart_set_page; |
| } |
| } |
| /* |
| * Radeon device. |
| 506,7 → 481,7 |
| struct pci_dev *pdev, |
| uint32_t flags) |
| { |
| int r; |
| int r, ret; |
| int dma_bits; |
| ENTER(); |
| 521,7 → 496,6 |
| rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; |
| rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
| rdev->gpu_lockup = false; |
| rdev->accel_working = false; |
| /* mutex initialization are all done here so we |
| * can recall function without having locking issues */ |
| // mutex_init(&rdev->cs_mutex); |
| 536,8 → 510,30 |
| } |
| if (radeon_agpmode == -1) { |
| radeon_agp_disable(rdev); |
| rdev->flags &= ~RADEON_IS_AGP; |
| if (rdev->family >= CHIP_RV515 || |
| rdev->family == CHIP_RV380 || |
| rdev->family == CHIP_RV410 || |
| rdev->family == CHIP_R423) { |
| DRM_INFO("Forcing AGP to PCIE mode\n"); |
| rdev->flags |= RADEON_IS_PCIE; |
| rdev->asic->gart_init = &rv370_pcie_gart_init; |
| rdev->asic->gart_fini = &rv370_pcie_gart_fini; |
| rdev->asic->gart_enable = &rv370_pcie_gart_enable; |
| rdev->asic->gart_disable = &rv370_pcie_gart_disable; |
| rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; |
| rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; |
| } else { |
| DRM_INFO("Forcing AGP to PCI mode\n"); |
| rdev->flags |= RADEON_IS_PCI; |
| rdev->asic->gart_init = &r100_pci_gart_init; |
| rdev->asic->gart_fini = &r100_pci_gart_fini; |
| rdev->asic->gart_enable = &r100_pci_gart_enable; |
| rdev->asic->gart_disable = &r100_pci_gart_disable; |
| rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; |
| rdev->asic->gart_set_page = &r100_pci_gart_set_page; |
| } |
| } |
| /* set DMA mask + need_dma32 flags. |
| * PCIE - can handle 40-bits. |
| 572,27 → 568,98 |
| DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); |
| DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); |
| /* if we have > 1 VGA cards, then disable the radeon VGA resources */ |
| // r = vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); |
| // if (r) { |
| // return -EINVAL; |
| // } |
| rdev->new_init_path = false; |
| r = radeon_init(rdev); |
| if (r) { |
| return r; |
| } |
| r = radeon_init(rdev); |
| if (!rdev->new_init_path) { |
| /* Setup errata flags */ |
| radeon_errata(rdev); |
| /* Initialize scratch registers */ |
| radeon_scratch_init(rdev); |
| /* Initialize surface registers */ |
| radeon_surface_init(rdev); |
| /* BIOS*/ |
| if (!radeon_get_bios(rdev)) { |
| if (ASIC_IS_AVIVO(rdev)) |
| return -EINVAL; |
| } |
| if (rdev->is_atom_bios) { |
| r = radeon_atombios_init(rdev); |
| if (r) { |
| return r; |
| } |
| } else { |
| r = radeon_combios_init(rdev); |
| if (r) { |
| return r; |
| } |
| } |
| /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
| if (radeon_gpu_reset(rdev)) { |
| /* FIXME: what do we want to do here ? */ |
| } |
| /* check if cards are posted or not */ |
| if (!radeon_card_posted(rdev) && rdev->bios) { |
| DRM_INFO("GPU not posted. posting now...\n"); |
| if (rdev->is_atom_bios) { |
| atom_asic_init(rdev->mode_info.atom_context); |
| } else { |
| radeon_combios_asic_init(rdev->ddev); |
| } |
| } |
| /* Get clock & vram information */ |
| radeon_get_clock_info(rdev->ddev); |
| radeon_vram_info(rdev); |
| /* Initialize clocks */ |
| r = radeon_clocks_init(rdev); |
| if (r) { |
| return r; |
| } |
| /* Initialize memory controller (also test AGP) */ |
| r = radeon_mc_init(rdev); |
| if (r) { |
| return r; |
| } |
| /* Memory manager */ |
| r = radeon_object_init(rdev); |
| if (r) { |
| return r; |
| } |
| r = radeon_gpu_gart_init(rdev); |
| if (r) |
| return r; |
| /* Initialize GART (initialize after TTM so we can allocate |
| * memory through TTM but finalize after TTM) */ |
| r = radeon_gart_enable(rdev); |
| if (r) |
| return 0; |
| r = radeon_gem_init(rdev); |
| if (r) |
| return 0; |
| if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { |
| /* Acceleration not working on AGP card try again |
| * with fallback to PCI or PCIE GART |
| */ |
| radeon_gpu_reset(rdev); |
| radeon_fini(rdev); |
| radeon_agp_disable(rdev); |
| r = radeon_init(rdev); |
| /* 1M ring buffer */ |
| // r = radeon_cp_init(rdev, 1024 * 1024); |
| // if (r) |
| // return 0; |
| #if 0 |
| r = radeon_wb_init(rdev); |
| if (r) |
| return r; |
| DRM_ERROR("radeon: failled initializing WB (%d).\n", r); |
| r = radeon_ib_pool_init(rdev); |
| if (r) |
| return 0; |
| r = radeon_ib_test(rdev); |
| if (r) |
| return 0; |
| #endif |
| rdev->accel_working = true; |
| } |
| DRM_INFO("radeon: kernel modesetting successfully initialized.\n"); |
| // if (radeon_testing) { |
| // radeon_test_moves(rdev); |
| // } |
| 646,8 → 713,73 |
| return retval; |
| }; |
| /* |
| static struct drm_driver kms_driver = { |
| .driver_features = |
| DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | |
| DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED | DRIVER_GEM, |
| .dev_priv_size = 0, |
| .load = radeon_driver_load_kms, |
| .firstopen = radeon_driver_firstopen_kms, |
| .open = radeon_driver_open_kms, |
| .preclose = radeon_driver_preclose_kms, |
| .postclose = radeon_driver_postclose_kms, |
| .lastclose = radeon_driver_lastclose_kms, |
| .unload = radeon_driver_unload_kms, |
| .suspend = radeon_suspend_kms, |
| .resume = radeon_resume_kms, |
| .get_vblank_counter = radeon_get_vblank_counter_kms, |
| .enable_vblank = radeon_enable_vblank_kms, |
| .disable_vblank = radeon_disable_vblank_kms, |
| .master_create = radeon_master_create_kms, |
| .master_destroy = radeon_master_destroy_kms, |
| #if defined(CONFIG_DEBUG_FS) |
| .debugfs_init = radeon_debugfs_init, |
| .debugfs_cleanup = radeon_debugfs_cleanup, |
| #endif |
| .irq_preinstall = radeon_driver_irq_preinstall_kms, |
| .irq_postinstall = radeon_driver_irq_postinstall_kms, |
| .irq_uninstall = radeon_driver_irq_uninstall_kms, |
| .irq_handler = radeon_driver_irq_handler_kms, |
| .reclaim_buffers = drm_core_reclaim_buffers, |
| .get_map_ofs = drm_core_get_map_ofs, |
| .get_reg_ofs = drm_core_get_reg_ofs, |
| .ioctls = radeon_ioctls_kms, |
| .gem_init_object = radeon_gem_object_init, |
| .gem_free_object = radeon_gem_object_free, |
| .dma_ioctl = radeon_dma_ioctl_kms, |
| .fops = { |
| .owner = THIS_MODULE, |
| .open = drm_open, |
| .release = drm_release, |
| .ioctl = drm_ioctl, |
| .mmap = radeon_mmap, |
| .poll = drm_poll, |
| .fasync = drm_fasync, |
| #ifdef CONFIG_COMPAT |
| .compat_ioctl = NULL, |
| #endif |
| }, |
| .pci_driver = { |
| .name = DRIVER_NAME, |
| .id_table = pciidlist, |
| .probe = radeon_pci_probe, |
| .remove = radeon_pci_remove, |
| .suspend = radeon_pci_suspend, |
| .resume = radeon_pci_resume, |
| }, |
| .name = DRIVER_NAME, |
| .desc = DRIVER_DESC, |
| .date = DRIVER_DATE, |
| .major = KMS_DRIVER_MAJOR, |
| .minor = KMS_DRIVER_MINOR, |
| .patchlevel = KMS_DRIVER_PATCHLEVEL, |
| }; |
| */ |
| /* |
| * Driver load/unload |
| */ |
| 701,7 → 833,7 |
| struct drm_device *dev; |
| int ret; |
| ENTER(); |
| dbgprintf("%s\n",__FUNCTION__); |
| dev = malloc(sizeof(*dev)); |
| if (!dev) |
| 750,8 → 882,6 |
| set_mode(dev, 1280, 1024); |
| LEAVE(); |
| return 0; |
| err_g4: |
| 764,8 → 894,6 |
| //err_g1: |
| free(dev); |
| LEAVE(); |
| return ret; |
| } |
| 813,3 → 941,8 |
| return rem; |
| } |
| /drivers/video/drm/radeon/radeon_display.c |
|---|
| 106,33 → 106,24 |
| legacy_crtc_load_lut(crtc); |
| } |
| /** Sets the color ramps on behalf of fbcon */ |
| /** Sets the color ramps on behalf of RandR */ |
| void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
| u16 blue, int regno) |
| { |
| struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| if (regno == 0) |
| DRM_DEBUG("gamma set %d\n", radeon_crtc->crtc_id); |
| radeon_crtc->lut_r[regno] = red >> 6; |
| radeon_crtc->lut_g[regno] = green >> 6; |
| radeon_crtc->lut_b[regno] = blue >> 6; |
| } |
| /** Gets the color ramps on behalf of fbcon */ |
| void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
| u16 *blue, int regno) |
| { |
| struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| *red = radeon_crtc->lut_r[regno] << 6; |
| *green = radeon_crtc->lut_g[regno] << 6; |
| *blue = radeon_crtc->lut_b[regno] << 6; |
| } |
| static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
| u16 *blue, uint32_t size) |
| { |
| struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| int i; |
| int i, j; |
| if (size != 256) { |
| return; |
| 141,12 → 132,24 |
| return; |
| } |
| /* userspace palettes are always correct as is */ |
| if (crtc->fb->depth == 16) { |
| for (i = 0; i < 64; i++) { |
| if (i <= 31) { |
| for (j = 0; j < 8; j++) { |
| radeon_crtc->lut_r[i * 8 + j] = red[i] >> 6; |
| radeon_crtc->lut_b[i * 8 + j] = blue[i] >> 6; |
| } |
| } |
| for (j = 0; j < 4; j++) |
| radeon_crtc->lut_g[i * 4 + j] = green[i] >> 6; |
| } |
| } else { |
| for (i = 0; i < 256; i++) { |
| radeon_crtc->lut_r[i] = red[i] >> 6; |
| radeon_crtc->lut_g[i] = green[i] >> 6; |
| radeon_crtc->lut_b[i] = blue[i] >> 6; |
| } |
| } |
| radeon_crtc_load_lut(crtc); |
| } |
| 160,8 → 163,8 |
| } |
| static const struct drm_crtc_funcs radeon_crtc_funcs = { |
| .cursor_set = NULL, |
| .cursor_move = NULL, |
| // .cursor_set = radeon_crtc_cursor_set, |
| .cursor_move = radeon_crtc_cursor_move, |
| .gamma_set = radeon_crtc_gamma_set, |
| .set_config = drm_crtc_helper_set_config, |
| .destroy = radeon_crtc_destroy, |
| 724,11 → 727,7 |
| if (ret) { |
| return ret; |
| } |
| if (rdev->flags & RADEON_SINGLE_CRTC) |
| num_crtc = 1; |
| /* allocate crtcs */ |
| /* allocate crtcs - TODO single crtc */ |
| for (i = 0; i < num_crtc; i++) { |
| radeon_crtc_init(rdev->ddev, i); |
| } |
| /drivers/video/drm/radeon/radeon_encoders.c |
|---|
| 1345,7 → 1345,6 |
| void |
| radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device) |
| { |
| struct radeon_device *rdev = dev->dev_private; |
| struct drm_encoder *encoder; |
| struct radeon_encoder *radeon_encoder; |
| 1365,9 → 1364,6 |
| return; |
| encoder = &radeon_encoder->base; |
| if (rdev->flags & RADEON_SINGLE_CRTC) |
| encoder->possible_crtcs = 0x1; |
| else |
| encoder->possible_crtcs = 0x3; |
| encoder->possible_clones = 0; |
| /drivers/video/drm/radeon/radeon_fb.c |
|---|
| 42,7 → 42,7 |
| #include <drm_mm.h> |
| #include "radeon_object.h" |
| struct fb_info *framebuffer_alloc(size_t size, void *dev); |
| struct fb_info *framebuffer_alloc(size_t size); |
| struct radeon_fb_device { |
| struct drm_fb_helper helper; |
| 60,7 → 60,6 |
| // .fb_imageblit = cfb_imageblit, |
| // .fb_pan_display = drm_fb_helper_pan_display, |
| .fb_blank = drm_fb_helper_blank, |
| .fb_setcmap = drm_fb_helper_setcmap, |
| }; |
| /** |
| 129,13 → 128,11 |
| static struct drm_fb_helper_funcs radeon_fb_helper_funcs = { |
| .gamma_set = radeon_crtc_fb_gamma_set, |
| .gamma_get = radeon_crtc_fb_gamma_get, |
| }; |
| int radeonfb_create(struct drm_device *dev, |
| uint32_t fb_width, uint32_t fb_height, |
| uint32_t surface_width, uint32_t surface_height, |
| uint32_t surface_depth, uint32_t surface_bpp, |
| struct drm_framebuffer **fb_p) |
| { |
| struct radeon_device *rdev = dev->dev_private; |
| 146,7 → 143,7 |
| struct drm_mode_fb_cmd mode_cmd; |
| struct drm_gem_object *gobj = NULL; |
| struct radeon_object *robj = NULL; |
| void *device = NULL; //&rdev->pdev->dev; |
| // struct device *device = &rdev->pdev->dev; |
| int size, aligned_size, ret; |
| u64 fb_gpuaddr; |
| void *fbptr = NULL; |
| 153,19 → 150,13 |
| unsigned long tmp; |
| bool fb_tiled = false; /* useful for testing */ |
| u32 tiling_flags = 0; |
| int crtc_count; |
| mode_cmd.width = surface_width; |
| mode_cmd.height = surface_height; |
| /* avivo can't scanout real 24bpp */ |
| if ((surface_bpp == 24) && ASIC_IS_AVIVO(rdev)) |
| surface_bpp = 32; |
| mode_cmd.bpp = 32; |
| /* need to align pitch with crtc limits */ |
| mode_cmd.pitch = radeon_align_pitch(rdev, mode_cmd.width, mode_cmd.bpp, fb_tiled) * ((mode_cmd.bpp + 1) / 8); |
| mode_cmd.depth = surface_depth; |
| mode_cmd.depth = 24; |
| size = mode_cmd.pitch * mode_cmd.height; |
| aligned_size = ALIGN(size, PAGE_SIZE); |
| 174,6 → 165,7 |
| RADEON_GEM_DOMAIN_VRAM, |
| false, 0, |
| false, &gobj); |
| if (ret) { |
| printk(KERN_ERR "failed to allocate framebuffer (%d %d)\n", |
| surface_width, surface_height); |
| 203,7 → 195,7 |
| rdev->fbdev_rfb = rfb; |
| rdev->fbdev_robj = robj; |
| info = framebuffer_alloc(sizeof(struct radeon_fb_device), device); |
| info = framebuffer_alloc(sizeof(struct radeon_fb_device)); |
| if (info == NULL) { |
| ret = -ENOMEM; |
| goto out_unref; |
| 213,11 → 205,7 |
| rfbdev = info->par; |
| rfbdev->helper.funcs = &radeon_fb_helper_funcs; |
| rfbdev->helper.dev = dev; |
| if (rdev->flags & RADEON_SINGLE_CRTC) |
| crtc_count = 1; |
| else |
| crtc_count = 2; |
| ret = drm_fb_helper_init_crtc_count(&rfbdev->helper, crtc_count, |
| ret = drm_fb_helper_init_crtc_count(&rfbdev->helper, 2, |
| RADEONFB_CONN_LIMIT); |
| if (ret) |
| goto out_unref; |
| 232,7 → 220,7 |
| strcpy(info->fix.id, "radeondrmfb"); |
| drm_fb_helper_fill_fix(info, fb->pitch, fb->depth); |
| drm_fb_helper_fill_fix(info, fb->pitch); |
| info->flags = FBINFO_DEFAULT; |
| info->fbops = &radeonfb_ops; |
| 293,8 → 281,11 |
| int radeonfb_probe(struct drm_device *dev) |
| { |
| return drm_fb_helper_single_fb_probe(dev, 32, &radeonfb_create); |
| int ret; |
| ret = drm_fb_helper_single_fb_probe(dev, &radeonfb_create); |
| return ret; |
| } |
| EXPORT_SYMBOL(radeonfb_probe); |
| int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb) |
| { |
| 410,7 → 401,7 |
| } |
| struct fb_info *framebuffer_alloc(size_t size, void *dev) |
| struct fb_info *framebuffer_alloc(size_t size) |
| { |
| #define BYTES_PER_LONG (BITS_PER_LONG/8) |
| #define PADDING (BYTES_PER_LONG - (sizeof(struct fb_info) % BYTES_PER_LONG)) |
| 455,8 → 446,6 |
| bool ret = false; |
| ENTER(); |
| list_for_each_entry(connector, &dev->mode_config.connector_list, head) |
| { |
| struct drm_display_mode *mode; |
| 476,7 → 465,7 |
| if(crtc == NULL) |
| continue; |
| /* |
| list_for_each_entry(mode, &connector->modes, head) |
| { |
| if (mode->type & DRM_MODE_TYPE_PREFERRED); |
| 483,6 → 472,7 |
| break; |
| }; |
| /* |
| struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| struct radeon_native_mode *native_mode = &radeon_encoder->native_mode; |
| 546,14 → 536,10 |
| DRM_ERROR("failed to set mode %d_%d on crtc %p\n", |
| fb->width, fb->height, crtc); |
| }; |
| LEAVE(); |
| return ret; |
| }; |
| } |
| }; |
| LEAVE(); |
| return ret; |
| }; |
| /drivers/video/drm/radeon/avivod.h |
|---|
| 57,4 → 57,13 |
| #define VGA_RENDER_CONTROL 0x0300 |
| #define VGA_VSTATUS_CNTL_MASK 0x00030000 |
| /* AVIVO disable VGA rendering */ |
| static inline void radeon_avivo_vga_render_disable(struct radeon_device *rdev) |
| { |
| u32 vga_render; |
| vga_render = RREG32(VGA_RENDER_CONTROL); |
| vga_render &= ~VGA_VSTATUS_CNTL_MASK; |
| WREG32(VGA_RENDER_CONTROL, vga_render); |
| } |
| #endif |
| /drivers/video/drm/radeon/r100.c |
|---|
| 29,40 → 29,28 |
| #include "drmP.h" |
| #include "drm.h" |
| #include "radeon_drm.h" |
| #include "radeon_microcode.h" |
| #include "radeon_reg.h" |
| #include "radeon.h" |
| #include "r100d.h" |
| #include "rs100d.h" |
| #include "rv200d.h" |
| #include "rv250d.h" |
| #include <linux/firmware.h> |
| #include "r100_reg_safe.h" |
| #include "rn50_reg_safe.h" |
| /* Firmware Names */ |
| #define FIRMWARE_R100 "radeon/R100_cp.bin" |
| #define FIRMWARE_R200 "radeon/R200_cp.bin" |
| #define FIRMWARE_R300 "radeon/R300_cp.bin" |
| #define FIRMWARE_R420 "radeon/R420_cp.bin" |
| #define FIRMWARE_RS690 "radeon/RS690_cp.bin" |
| #define FIRMWARE_RS600 "radeon/RS600_cp.bin" |
| #define FIRMWARE_R520 "radeon/R520_cp.bin" |
| MODULE_FIRMWARE(FIRMWARE_R100); |
| MODULE_FIRMWARE(FIRMWARE_R200); |
| MODULE_FIRMWARE(FIRMWARE_R300); |
| MODULE_FIRMWARE(FIRMWARE_R420); |
| MODULE_FIRMWARE(FIRMWARE_RS690); |
| MODULE_FIRMWARE(FIRMWARE_RS600); |
| MODULE_FIRMWARE(FIRMWARE_R520); |
| /* This files gather functions specifics to: |
| * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 |
| * |
| * Some of these functions might be used by newer ASICs. |
| */ |
| int r200_init(struct radeon_device *rdev); |
| void r100_hdp_reset(struct radeon_device *rdev); |
| void r100_gpu_init(struct radeon_device *rdev); |
| int r100_gui_wait_for_idle(struct radeon_device *rdev); |
| int r100_mc_wait_for_idle(struct radeon_device *rdev); |
| void r100_gpu_wait_for_vsync(struct radeon_device *rdev); |
| void r100_gpu_wait_for_vsync2(struct radeon_device *rdev); |
| int r100_debugfs_mc_info_init(struct radeon_device *rdev); |
| /* |
| * PCI GART |
| */ |
| 143,31 → 131,133 |
| } |
| void r100_irq_disable(struct radeon_device *rdev) |
| /* |
| * MC |
| */ |
| void r100_mc_disable_clients(struct radeon_device *rdev) |
| { |
| u32 tmp; |
| uint32_t ov0_scale_cntl, crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl; |
| WREG32(R_000040_GEN_INT_CNTL, 0); |
| /* Wait and acknowledge irq */ |
| mdelay(1); |
| tmp = RREG32(R_000044_GEN_INT_STATUS); |
| WREG32(R_000044_GEN_INT_STATUS, tmp); |
| /* FIXME: is this function correct for rs100,rs200,rs300 ? */ |
| if (r100_gui_wait_for_idle(rdev)) { |
| printk(KERN_WARNING "Failed to wait GUI idle while " |
| "programming pipes. Bad things might happen.\n"); |
| } |
| static inline uint32_t r100_irq_ack(struct radeon_device *rdev) |
| /* stop display and memory access */ |
| ov0_scale_cntl = RREG32(RADEON_OV0_SCALE_CNTL); |
| WREG32(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE); |
| crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); |
| WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS); |
| crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); |
| r100_gpu_wait_for_vsync(rdev); |
| WREG32(RADEON_CRTC_GEN_CNTL, |
| (crtc_gen_cntl & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN)) | |
| RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN); |
| if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
| crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); |
| r100_gpu_wait_for_vsync2(rdev); |
| WREG32(RADEON_CRTC2_GEN_CNTL, |
| (crtc2_gen_cntl & |
| ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN)) | |
| RADEON_CRTC2_DISP_REQ_EN_B); |
| } |
| udelay(500); |
| } |
| void r100_mc_setup(struct radeon_device *rdev) |
| { |
| uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); |
| uint32_t irq_mask = RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT | |
| RADEON_CRTC2_VBLANK_STAT; |
| uint32_t tmp; |
| int r; |
| if (irqs) { |
| WREG32(RADEON_GEN_INT_STATUS, irqs); |
| r = r100_debugfs_mc_info_init(rdev); |
| if (r) { |
| DRM_ERROR("Failed to register debugfs file for R100 MC !\n"); |
| } |
| return irqs & irq_mask; |
| /* Write VRAM size in case we are limiting it */ |
| WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
| /* Novell bug 204882 for RN50/M6/M7 with 8/16/32MB VRAM, |
| * if the aperture is 64MB but we have 32MB VRAM |
| * we report only 32MB VRAM but we have to set MC_FB_LOCATION |
| * to 64MB, otherwise the gpu accidentially dies */ |
| tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
| tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16); |
| tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16); |
| WREG32(RADEON_MC_FB_LOCATION, tmp); |
| /* Enable bus mastering */ |
| tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; |
| WREG32(RADEON_BUS_CNTL, tmp); |
| if (rdev->flags & RADEON_IS_AGP) { |
| tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
| tmp = REG_SET(RADEON_MC_AGP_TOP, tmp >> 16); |
| tmp |= REG_SET(RADEON_MC_AGP_START, rdev->mc.gtt_location >> 16); |
| WREG32(RADEON_MC_AGP_LOCATION, tmp); |
| WREG32(RADEON_AGP_BASE, rdev->mc.agp_base); |
| } else { |
| WREG32(RADEON_MC_AGP_LOCATION, 0x0FFFFFFF); |
| WREG32(RADEON_AGP_BASE, 0); |
| } |
| tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL; |
| tmp |= (7 << 28); |
| WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE); |
| (void)RREG32(RADEON_HOST_PATH_CNTL); |
| WREG32(RADEON_HOST_PATH_CNTL, tmp); |
| (void)RREG32(RADEON_HOST_PATH_CNTL); |
| } |
| int r100_mc_init(struct radeon_device *rdev) |
| { |
| int r; |
| if (r100_debugfs_rbbm_init(rdev)) { |
| DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
| } |
| r100_gpu_init(rdev); |
| /* Disable gart which also disable out of gart access */ |
| r100_pci_gart_disable(rdev); |
| /* Setup GPU memory space */ |
| rdev->mc.gtt_location = 0xFFFFFFFFUL; |
| r = radeon_mc_setup(rdev); |
| if (r) { |
| return r; |
| } |
| r100_mc_disable_clients(rdev); |
| if (r100_mc_wait_for_idle(rdev)) { |
| printk(KERN_WARNING "Failed to wait MC idle while " |
| "programming pipes. Bad things might happen.\n"); |
| } |
| r100_mc_setup(rdev); |
| return 0; |
| } |
| void r100_mc_fini(struct radeon_device *rdev) |
| { |
| } |
| u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) |
| { |
| if (crtc == 0) |
| return RREG32(RADEON_CRTC_CRNT_FRAME); |
| else |
| return RREG32(RADEON_CRTC2_CRNT_FRAME); |
| } |
| /* |
| * Fence emission |
| */ |
| void r100_fence_ring_emit(struct radeon_device *rdev, |
| struct radeon_fence *fence) |
| { |
| 312,7 → 402,9 |
| #endif |
| /* |
| * CP |
| */ |
| static int r100_cp_wait_for_idle(struct radeon_device *rdev) |
| { |
| unsigned i; |
| 345,33 → 437,33 |
| radeon_ring_unlock_commit(rdev); |
| } |
| /* Load the microcode for the CP */ |
| static int r100_cp_init_microcode(struct radeon_device *rdev) |
| static void r100_cp_load_microcode(struct radeon_device *rdev) |
| { |
| struct platform_device *pdev; |
| const char *fw_name = NULL; |
| int err; |
| int i; |
| DRM_DEBUG("\n"); |
| if (r100_gui_wait_for_idle(rdev)) { |
| printk(KERN_WARNING "Failed to wait GUI idle while " |
| "programming pipes. Bad things might happen.\n"); |
| } |
| // pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); |
| // err = IS_ERR(pdev); |
| // if (err) { |
| // printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); |
| // return -EINVAL; |
| // } |
| WREG32(RADEON_CP_ME_RAM_ADDR, 0); |
| if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || |
| (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || |
| (rdev->family == CHIP_RS200)) { |
| DRM_INFO("Loading R100 Microcode\n"); |
| fw_name = FIRMWARE_R100; |
| for (i = 0; i < 256; i++) { |
| WREG32(RADEON_CP_ME_RAM_DATAH, R100_cp_microcode[i][1]); |
| WREG32(RADEON_CP_ME_RAM_DATAL, R100_cp_microcode[i][0]); |
| } |
| } else if ((rdev->family == CHIP_R200) || |
| (rdev->family == CHIP_RV250) || |
| (rdev->family == CHIP_RV280) || |
| (rdev->family == CHIP_RS300)) { |
| DRM_INFO("Loading R200 Microcode\n"); |
| fw_name = FIRMWARE_R200; |
| for (i = 0; i < 256; i++) { |
| WREG32(RADEON_CP_ME_RAM_DATAH, R200_cp_microcode[i][1]); |
| WREG32(RADEON_CP_ME_RAM_DATAL, R200_cp_microcode[i][0]); |
| } |
| } else if ((rdev->family == CHIP_R300) || |
| (rdev->family == CHIP_R350) || |
| (rdev->family == CHIP_RV350) || |
| 379,19 → 471,31 |
| (rdev->family == CHIP_RS400) || |
| (rdev->family == CHIP_RS480)) { |
| DRM_INFO("Loading R300 Microcode\n"); |
| fw_name = FIRMWARE_R300; |
| for (i = 0; i < 256; i++) { |
| WREG32(RADEON_CP_ME_RAM_DATAH, R300_cp_microcode[i][1]); |
| WREG32(RADEON_CP_ME_RAM_DATAL, R300_cp_microcode[i][0]); |
| } |
| } else if ((rdev->family == CHIP_R420) || |
| (rdev->family == CHIP_R423) || |
| (rdev->family == CHIP_RV410)) { |
| DRM_INFO("Loading R400 Microcode\n"); |
| fw_name = FIRMWARE_R420; |
| for (i = 0; i < 256; i++) { |
| WREG32(RADEON_CP_ME_RAM_DATAH, R420_cp_microcode[i][1]); |
| WREG32(RADEON_CP_ME_RAM_DATAL, R420_cp_microcode[i][0]); |
| } |
| } else if ((rdev->family == CHIP_RS690) || |
| (rdev->family == CHIP_RS740)) { |
| DRM_INFO("Loading RS690/RS740 Microcode\n"); |
| fw_name = FIRMWARE_RS690; |
| for (i = 0; i < 256; i++) { |
| WREG32(RADEON_CP_ME_RAM_DATAH, RS690_cp_microcode[i][1]); |
| WREG32(RADEON_CP_ME_RAM_DATAL, RS690_cp_microcode[i][0]); |
| } |
| } else if (rdev->family == CHIP_RS600) { |
| DRM_INFO("Loading RS600 Microcode\n"); |
| fw_name = FIRMWARE_RS600; |
| for (i = 0; i < 256; i++) { |
| WREG32(RADEON_CP_ME_RAM_DATAH, RS600_cp_microcode[i][1]); |
| WREG32(RADEON_CP_ME_RAM_DATAL, RS600_cp_microcode[i][0]); |
| } |
| } else if ((rdev->family == CHIP_RV515) || |
| (rdev->family == CHIP_R520) || |
| (rdev->family == CHIP_RV530) || |
| 399,62 → 503,19 |
| (rdev->family == CHIP_RV560) || |
| (rdev->family == CHIP_RV570)) { |
| DRM_INFO("Loading R500 Microcode\n"); |
| fw_name = FIRMWARE_R520; |
| for (i = 0; i < 256; i++) { |
| WREG32(RADEON_CP_ME_RAM_DATAH, R520_cp_microcode[i][1]); |
| WREG32(RADEON_CP_ME_RAM_DATAL, R520_cp_microcode[i][0]); |
| } |
| // err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); |
| // platform_device_unregister(pdev); |
| if (err) { |
| printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n", |
| fw_name); |
| } else if (rdev->me_fw->size % 8) { |
| printk(KERN_ERR |
| "radeon_cp: Bogus length %zu in firmware \"%s\"\n", |
| rdev->me_fw->size, fw_name); |
| err = -EINVAL; |
| release_firmware(rdev->me_fw); |
| rdev->me_fw = NULL; |
| } |
| return err; |
| } |
| static inline __u32 __swab32(__u32 x) |
| static int r100_cp_init_microcode(struct radeon_device *rdev) |
| { |
| asm("bswapl %0" : |
| "=&r" (x) |
| :"r" (x)); |
| return x; |
| return 0; |
| } |
| static inline __u32 be32_to_cpup(const __be32 *p) |
| { |
| return __swab32(*(__u32 *)p); |
| } |
| static void r100_cp_load_microcode(struct radeon_device *rdev) |
| { |
| const __be32 *fw_data; |
| int i, size; |
| if (r100_gui_wait_for_idle(rdev)) { |
| printk(KERN_WARNING "Failed to wait GUI idle while " |
| "programming pipes. Bad things might happen.\n"); |
| } |
| if (rdev->me_fw) { |
| size = rdev->me_fw->size / 4; |
| fw_data = (const __be32 *)&rdev->me_fw->data[0]; |
| WREG32(RADEON_CP_ME_RAM_ADDR, 0); |
| for (i = 0; i < size; i += 2) { |
| WREG32(RADEON_CP_ME_RAM_DATAH, |
| be32_to_cpup(&fw_data[i])); |
| WREG32(RADEON_CP_ME_RAM_DATAL, |
| be32_to_cpup(&fw_data[i + 1])); |
| } |
| } |
| } |
| int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) |
| { |
| unsigned rb_bufsz; |
| 686,11 → 747,13 |
| void r100_cs_dump_packet(struct radeon_cs_parser *p, |
| struct radeon_cs_packet *pkt) |
| { |
| struct radeon_cs_chunk *ib_chunk; |
| volatile uint32_t *ib; |
| unsigned i; |
| unsigned idx; |
| ib = p->ib->ptr; |
| ib_chunk = &p->chunks[p->chunk_ib_idx]; |
| idx = pkt->idx; |
| for (i = 0; i <= (pkt->count + 1); i++, idx++) { |
| DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); |
| 717,7 → 780,7 |
| idx, ib_chunk->length_dw); |
| return -EINVAL; |
| } |
| header = radeon_get_ib_value(p, idx); |
| header = ib_chunk->kdata[idx]; |
| pkt->idx = idx; |
| pkt->type = CP_PACKET_GET_TYPE(header); |
| pkt->count = CP_PACKET_GET_COUNT(header); |
| 760,6 → 823,7 |
| */ |
| int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) |
| { |
| struct radeon_cs_chunk *ib_chunk; |
| struct drm_mode_object *obj; |
| struct drm_crtc *crtc; |
| struct radeon_crtc *radeon_crtc; |
| 767,9 → 831,8 |
| int crtc_id; |
| int r; |
| uint32_t header, h_idx, reg; |
| volatile uint32_t *ib; |
| ib = p->ib->ptr; |
| ib_chunk = &p->chunks[p->chunk_ib_idx]; |
| /* parse the wait until */ |
| r = r100_cs_packet_parse(p, &waitreloc, p->idx); |
| 784,7 → 847,7 |
| return r; |
| } |
| if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { |
| if (ib_chunk->kdata[waitreloc.idx + 1] != RADEON_WAIT_CRTC_VLINE) { |
| DRM_ERROR("vline wait had illegal wait until\n"); |
| r = -EINVAL; |
| return r; |
| 791,17 → 854,17 |
| } |
| /* jump over the NOP */ |
| r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); |
| r = r100_cs_packet_parse(p, &p3reloc, p->idx); |
| if (r) |
| return r; |
| h_idx = p->idx - 2; |
| p->idx += waitreloc.count + 2; |
| p->idx += p3reloc.count + 2; |
| p->idx += waitreloc.count; |
| p->idx += p3reloc.count; |
| header = radeon_get_ib_value(p, h_idx); |
| crtc_id = radeon_get_ib_value(p, h_idx + 5); |
| reg = CP_PACKET0_GET_REG(header); |
| header = ib_chunk->kdata[h_idx]; |
| crtc_id = ib_chunk->kdata[h_idx + 5]; |
| reg = ib_chunk->kdata[h_idx] >> 2; |
| mutex_lock(&p->rdev->ddev->mode_config.mutex); |
| obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); |
| if (!obj) { |
| 815,16 → 878,16 |
| if (!crtc->enabled) { |
| /* if the CRTC isn't enabled - we need to nop out the wait until */ |
| ib[h_idx + 2] = PACKET2(0); |
| ib[h_idx + 3] = PACKET2(0); |
| ib_chunk->kdata[h_idx + 2] = PACKET2(0); |
| ib_chunk->kdata[h_idx + 3] = PACKET2(0); |
| } else if (crtc_id == 1) { |
| switch (reg) { |
| case AVIVO_D1MODE_VLINE_START_END: |
| header &= ~R300_CP_PACKET0_REG_MASK; |
| header &= R300_CP_PACKET0_REG_MASK; |
| header |= AVIVO_D2MODE_VLINE_START_END >> 2; |
| break; |
| case RADEON_CRTC_GUI_TRIG_VLINE: |
| header &= ~R300_CP_PACKET0_REG_MASK; |
| header &= R300_CP_PACKET0_REG_MASK; |
| header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; |
| break; |
| default: |
| 832,8 → 895,8 |
| r = -EINVAL; |
| goto out; |
| } |
| ib[h_idx] = header; |
| ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; |
| ib_chunk->kdata[h_idx] = header; |
| ib_chunk->kdata[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; |
| } |
| out: |
| mutex_unlock(&p->rdev->ddev->mode_config.mutex); |
| 854,6 → 917,7 |
| int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, |
| struct radeon_cs_reloc **cs_reloc) |
| { |
| struct radeon_cs_chunk *ib_chunk; |
| struct radeon_cs_chunk *relocs_chunk; |
| struct radeon_cs_packet p3reloc; |
| unsigned idx; |
| 864,6 → 928,7 |
| return -EINVAL; |
| } |
| *cs_reloc = NULL; |
| ib_chunk = &p->chunks[p->chunk_ib_idx]; |
| relocs_chunk = &p->chunks[p->chunk_relocs_idx]; |
| r = r100_cs_packet_parse(p, &p3reloc, p->idx); |
| if (r) { |
| 876,7 → 941,7 |
| r100_cs_dump_packet(p, &p3reloc); |
| return -EINVAL; |
| } |
| idx = radeon_get_ib_value(p, p3reloc.idx + 1); |
| idx = ib_chunk->kdata[p3reloc.idx + 1]; |
| if (idx >= relocs_chunk->length_dw) { |
| DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", |
| idx, relocs_chunk->length_dw); |
| 945,6 → 1010,7 |
| struct radeon_cs_packet *pkt, |
| unsigned idx, unsigned reg) |
| { |
| struct radeon_cs_chunk *ib_chunk; |
| struct radeon_cs_reloc *reloc; |
| struct r100_cs_track *track; |
| volatile uint32_t *ib; |
| 952,13 → 1018,11 |
| int r; |
| int i, face; |
| u32 tile_flags = 0; |
| u32 idx_value; |
| ib = p->ib->ptr; |
| ib_chunk = &p->chunks[p->chunk_ib_idx]; |
| track = (struct r100_cs_track *)p->track; |
| idx_value = radeon_get_ib_value(p, idx); |
| switch (reg) { |
| case RADEON_CRTC_GUI_TRIG_VLINE: |
| r = r100_cs_packet_parse_vline(p); |
| 986,8 → 1050,8 |
| return r; |
| } |
| track->zb.robj = reloc->robj; |
| track->zb.offset = idx_value; |
| ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
| track->zb.offset = ib_chunk->kdata[idx]; |
| ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
| break; |
| case RADEON_RB3D_COLOROFFSET: |
| r = r100_cs_packet_next_reloc(p, &reloc); |
| 998,8 → 1062,8 |
| return r; |
| } |
| track->cb[0].robj = reloc->robj; |
| track->cb[0].offset = idx_value; |
| ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
| track->cb[0].offset = ib_chunk->kdata[idx]; |
| ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
| break; |
| case RADEON_PP_TXOFFSET_0: |
| case RADEON_PP_TXOFFSET_1: |
| 1012,7 → 1076,7 |
| r100_cs_dump_packet(p, pkt); |
| return r; |
| } |
| ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
| ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
| track->textures[i].robj = reloc->robj; |
| break; |
| case RADEON_PP_CUBIC_OFFSET_T0_0: |
| 1028,8 → 1092,8 |
| r100_cs_dump_packet(p, pkt); |
| return r; |
| } |
| track->textures[0].cube_info[i].offset = idx_value; |
| ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
| track->textures[0].cube_info[i].offset = ib_chunk->kdata[idx]; |
| ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
| track->textures[0].cube_info[i].robj = reloc->robj; |
| break; |
| case RADEON_PP_CUBIC_OFFSET_T1_0: |
| 1045,8 → 1109,8 |
| r100_cs_dump_packet(p, pkt); |
| return r; |
| } |
| track->textures[1].cube_info[i].offset = idx_value; |
| ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
| track->textures[1].cube_info[i].offset = ib_chunk->kdata[idx]; |
| ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
| track->textures[1].cube_info[i].robj = reloc->robj; |
| break; |
| case RADEON_PP_CUBIC_OFFSET_T2_0: |
| 1062,12 → 1126,12 |
| r100_cs_dump_packet(p, pkt); |
| return r; |
| } |
| track->textures[2].cube_info[i].offset = idx_value; |
| ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
| track->textures[2].cube_info[i].offset = ib_chunk->kdata[idx]; |
| ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
| track->textures[2].cube_info[i].robj = reloc->robj; |
| break; |
| case RADEON_RE_WIDTH_HEIGHT: |
| track->maxy = ((idx_value >> 16) & 0x7FF); |
| track->maxy = ((ib_chunk->kdata[idx] >> 16) & 0x7FF); |
| break; |
| case RADEON_RB3D_COLORPITCH: |
| r = r100_cs_packet_next_reloc(p, &reloc); |
| 1083,17 → 1147,17 |
| if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
| tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; |
| tmp = idx_value & ~(0x7 << 16); |
| tmp = ib_chunk->kdata[idx] & ~(0x7 << 16); |
| tmp |= tile_flags; |
| ib[idx] = tmp; |
| track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; |
| track->cb[0].pitch = ib_chunk->kdata[idx] & RADEON_COLORPITCH_MASK; |
| break; |
| case RADEON_RB3D_DEPTHPITCH: |
| track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; |
| track->zb.pitch = ib_chunk->kdata[idx] & RADEON_DEPTHPITCH_MASK; |
| break; |
| case RADEON_RB3D_CNTL: |
| switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { |
| switch ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { |
| case 7: |
| case 8: |
| case 9: |
| 1111,13 → 1175,13 |
| break; |
| default: |
| DRM_ERROR("Invalid color buffer format (%d) !\n", |
| ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); |
| ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); |
| return -EINVAL; |
| } |
| track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); |
| track->z_enabled = !!(ib_chunk->kdata[idx] & RADEON_Z_ENABLE); |
| break; |
| case RADEON_RB3D_ZSTENCILCNTL: |
| switch (idx_value & 0xf) { |
| switch (ib_chunk->kdata[idx] & 0xf) { |
| case 0: |
| track->zb.cpp = 2; |
| break; |
| 1141,44 → 1205,44 |
| r100_cs_dump_packet(p, pkt); |
| return r; |
| } |
| ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
| ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
| break; |
| case RADEON_PP_CNTL: |
| { |
| uint32_t temp = idx_value >> 4; |
| uint32_t temp = ib_chunk->kdata[idx] >> 4; |
| for (i = 0; i < track->num_texture; i++) |
| track->textures[i].enabled = !!(temp & (1 << i)); |
| } |
| break; |
| case RADEON_SE_VF_CNTL: |
| track->vap_vf_cntl = idx_value; |
| track->vap_vf_cntl = ib_chunk->kdata[idx]; |
| break; |
| case RADEON_SE_VTX_FMT: |
| track->vtx_size = r100_get_vtx_size(idx_value); |
| track->vtx_size = r100_get_vtx_size(ib_chunk->kdata[idx]); |
| break; |
| case RADEON_PP_TEX_SIZE_0: |
| case RADEON_PP_TEX_SIZE_1: |
| case RADEON_PP_TEX_SIZE_2: |
| i = (reg - RADEON_PP_TEX_SIZE_0) / 8; |
| track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; |
| track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; |
| track->textures[i].width = (ib_chunk->kdata[idx] & RADEON_TEX_USIZE_MASK) + 1; |
| track->textures[i].height = ((ib_chunk->kdata[idx] & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; |
| break; |
| case RADEON_PP_TEX_PITCH_0: |
| case RADEON_PP_TEX_PITCH_1: |
| case RADEON_PP_TEX_PITCH_2: |
| i = (reg - RADEON_PP_TEX_PITCH_0) / 8; |
| track->textures[i].pitch = idx_value + 32; |
| track->textures[i].pitch = ib_chunk->kdata[idx] + 32; |
| break; |
| case RADEON_PP_TXFILTER_0: |
| case RADEON_PP_TXFILTER_1: |
| case RADEON_PP_TXFILTER_2: |
| i = (reg - RADEON_PP_TXFILTER_0) / 24; |
| track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) |
| track->textures[i].num_levels = ((ib_chunk->kdata[idx] & RADEON_MAX_MIP_LEVEL_MASK) |
| >> RADEON_MAX_MIP_LEVEL_SHIFT); |
| tmp = (idx_value >> 23) & 0x7; |
| tmp = (ib_chunk->kdata[idx] >> 23) & 0x7; |
| if (tmp == 2 || tmp == 6) |
| track->textures[i].roundup_w = false; |
| tmp = (idx_value >> 27) & 0x7; |
| tmp = (ib_chunk->kdata[idx] >> 27) & 0x7; |
| if (tmp == 2 || tmp == 6) |
| track->textures[i].roundup_h = false; |
| break; |
| 1186,16 → 1250,16 |
| case RADEON_PP_TXFORMAT_1: |
| case RADEON_PP_TXFORMAT_2: |
| i = (reg - RADEON_PP_TXFORMAT_0) / 24; |
| if (idx_value & RADEON_TXFORMAT_NON_POWER2) { |
| if (ib_chunk->kdata[idx] & RADEON_TXFORMAT_NON_POWER2) { |
| track->textures[i].use_pitch = 1; |
| } else { |
| track->textures[i].use_pitch = 0; |
| track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); |
| track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); |
| track->textures[i].width = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); |
| track->textures[i].height = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); |
| } |
| if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) |
| if (ib_chunk->kdata[idx] & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) |
| track->textures[i].tex_coord_type = 2; |
| switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { |
| switch ((ib_chunk->kdata[idx] & RADEON_TXFORMAT_FORMAT_MASK)) { |
| case RADEON_TXFORMAT_I8: |
| case RADEON_TXFORMAT_RGB332: |
| case RADEON_TXFORMAT_Y8: |
| 1222,13 → 1286,13 |
| track->textures[i].cpp = 4; |
| break; |
| } |
| track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); |
| track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); |
| track->textures[i].cube_info[4].width = 1 << ((ib_chunk->kdata[idx] >> 16) & 0xf); |
| track->textures[i].cube_info[4].height = 1 << ((ib_chunk->kdata[idx] >> 20) & 0xf); |
| break; |
| case RADEON_PP_CUBIC_FACES_0: |
| case RADEON_PP_CUBIC_FACES_1: |
| case RADEON_PP_CUBIC_FACES_2: |
| tmp = idx_value; |
| tmp = ib_chunk->kdata[idx]; |
| i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; |
| for (face = 0; face < 4; face++) { |
| track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); |
| 1247,14 → 1311,15 |
| struct radeon_cs_packet *pkt, |
| struct radeon_object *robj) |
| { |
| struct radeon_cs_chunk *ib_chunk; |
| unsigned idx; |
| u32 value; |
| ib_chunk = &p->chunks[p->chunk_ib_idx]; |
| idx = pkt->idx + 1; |
| value = radeon_get_ib_value(p, idx + 2); |
| if ((value + 1) > radeon_object_size(robj)) { |
| if ((ib_chunk->kdata[idx+2] + 1) > radeon_object_size(robj)) { |
| DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " |
| "(need %u have %lu) !\n", |
| value + 1, |
| ib_chunk->kdata[idx+2] + 1, |
| radeon_object_size(robj)); |
| return -EINVAL; |
| } |
| 1264,20 → 1329,59 |
| static int r100_packet3_check(struct radeon_cs_parser *p, |
| struct radeon_cs_packet *pkt) |
| { |
| struct radeon_cs_chunk *ib_chunk; |
| struct radeon_cs_reloc *reloc; |
| struct r100_cs_track *track; |
| unsigned idx; |
| unsigned i, c; |
| volatile uint32_t *ib; |
| int r; |
| ib = p->ib->ptr; |
| ib_chunk = &p->chunks[p->chunk_ib_idx]; |
| idx = pkt->idx + 1; |
| track = (struct r100_cs_track *)p->track; |
| switch (pkt->opcode) { |
| case PACKET3_3D_LOAD_VBPNTR: |
| r = r100_packet3_load_vbpntr(p, pkt, idx); |
| if (r) |
| c = ib_chunk->kdata[idx++]; |
| track->num_arrays = c; |
| for (i = 0; i < (c - 1); i += 2, idx += 3) { |
| r = r100_cs_packet_next_reloc(p, &reloc); |
| if (r) { |
| DRM_ERROR("No reloc for packet3 %d\n", |
| pkt->opcode); |
| r100_cs_dump_packet(p, pkt); |
| return r; |
| } |
| ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); |
| track->arrays[i + 0].robj = reloc->robj; |
| track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8; |
| track->arrays[i + 0].esize &= 0x7F; |
| r = r100_cs_packet_next_reloc(p, &reloc); |
| if (r) { |
| DRM_ERROR("No reloc for packet3 %d\n", |
| pkt->opcode); |
| r100_cs_dump_packet(p, pkt); |
| return r; |
| } |
| ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset); |
| track->arrays[i + 1].robj = reloc->robj; |
| track->arrays[i + 1].esize = ib_chunk->kdata[idx] >> 24; |
| track->arrays[i + 1].esize &= 0x7F; |
| } |
| if (c & 1) { |
| r = r100_cs_packet_next_reloc(p, &reloc); |
| if (r) { |
| DRM_ERROR("No reloc for packet3 %d\n", |
| pkt->opcode); |
| r100_cs_dump_packet(p, pkt); |
| return r; |
| } |
| ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); |
| track->arrays[i + 0].robj = reloc->robj; |
| track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8; |
| track->arrays[i + 0].esize &= 0x7F; |
| } |
| break; |
| case PACKET3_INDX_BUFFER: |
| r = r100_cs_packet_next_reloc(p, &reloc); |
| 1286,7 → 1390,7 |
| r100_cs_dump_packet(p, pkt); |
| return r; |
| } |
| ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset); |
| ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); |
| r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); |
| if (r) { |
| return r; |
| 1300,16 → 1404,16 |
| r100_cs_dump_packet(p, pkt); |
| return r; |
| } |
| ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset); |
| ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
| track->num_arrays = 1; |
| track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); |
| track->vtx_size = r100_get_vtx_size(ib_chunk->kdata[idx+2]); |
| track->arrays[0].robj = reloc->robj; |
| track->arrays[0].esize = track->vtx_size; |
| track->max_indx = radeon_get_ib_value(p, idx+1); |
| track->max_indx = ib_chunk->kdata[idx+1]; |
| track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); |
| track->vap_vf_cntl = ib_chunk->kdata[idx+3]; |
| track->immd_dwords = pkt->count - 1; |
| r = r100_cs_track_check(p->rdev, track); |
| if (r) |
| 1316,11 → 1420,11 |
| return r; |
| break; |
| case PACKET3_3D_DRAW_IMMD: |
| if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { |
| if (((ib_chunk->kdata[idx+1] >> 4) & 0x3) != 3) { |
| DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
| return -EINVAL; |
| } |
| track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
| track->vap_vf_cntl = ib_chunk->kdata[idx+1]; |
| track->immd_dwords = pkt->count - 1; |
| r = r100_cs_track_check(p->rdev, track); |
| if (r) |
| 1328,11 → 1432,11 |
| break; |
| /* triggers drawing using in-packet vertex data */ |
| case PACKET3_3D_DRAW_IMMD_2: |
| if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { |
| if (((ib_chunk->kdata[idx] >> 4) & 0x3) != 3) { |
| DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
| return -EINVAL; |
| } |
| track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
| track->vap_vf_cntl = ib_chunk->kdata[idx]; |
| track->immd_dwords = pkt->count; |
| r = r100_cs_track_check(p->rdev, track); |
| if (r) |
| 1340,7 → 1444,7 |
| break; |
| /* triggers drawing using in-packet vertex data */ |
| case PACKET3_3D_DRAW_VBUF_2: |
| track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
| track->vap_vf_cntl = ib_chunk->kdata[idx]; |
| r = r100_cs_track_check(p->rdev, track); |
| if (r) |
| return r; |
| 1347,7 → 1451,7 |
| break; |
| /* triggers drawing of vertex buffers setup elsewhere */ |
| case PACKET3_3D_DRAW_INDX_2: |
| track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
| track->vap_vf_cntl = ib_chunk->kdata[idx]; |
| r = r100_cs_track_check(p->rdev, track); |
| if (r) |
| return r; |
| 1354,7 → 1458,7 |
| break; |
| /* triggers drawing using indices to vertex buffer */ |
| case PACKET3_3D_DRAW_VBUF: |
| track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
| track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; |
| r = r100_cs_track_check(p->rdev, track); |
| if (r) |
| return r; |
| 1361,7 → 1465,7 |
| break; |
| /* triggers drawing of vertex buffers setup elsewhere */ |
| case PACKET3_3D_DRAW_INDX: |
| track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
| track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; |
| r = r100_cs_track_check(p->rdev, track); |
| if (r) |
| return r; |
| 1818,7 → 1922,7 |
| r100_pll_errata_after_data(rdev); |
| } |
| void r100_set_safe_registers(struct radeon_device *rdev) |
| int r100_init(struct radeon_device *rdev) |
| { |
| if (ASIC_IS_RN50(rdev)) { |
| rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; |
| 1827,8 → 1931,9 |
| rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; |
| rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); |
| } else { |
| r200_set_safe_registers(rdev); |
| return r200_init(rdev); |
| } |
| return 0; |
| } |
| /* |
| 2126,12 → 2231,10 |
| mode1 = &rdev->mode_info.crtcs[0]->base.mode; |
| pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8; |
| } |
| if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
| if (rdev->mode_info.crtcs[1]->base.enabled) { |
| mode2 = &rdev->mode_info.crtcs[1]->base.mode; |
| pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8; |
| } |
| } |
| min_mem_eff.full = rfixed_const_8(0); |
| /* get modes */ |
| 2548,7 → 2651,7 |
| WREG32(R_000740_CP_CSQ_CNTL, 0); |
| /* Save few CRTC registers */ |
| save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); |
| save->GENMO_WT = RREG32(R_0003C0_GENMO_WT); |
| save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); |
| save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); |
| save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); |
| 2558,7 → 2661,7 |
| } |
| /* Disable VGA aperture access */ |
| WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); |
| WREG32(R_0003C0_GENMO_WT, C_0003C0_VGA_RAM_EN & save->GENMO_WT); |
| /* Disable cursor, overlay, crtc */ |
| WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); |
| WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | |
| 2590,7 → 2693,7 |
| rdev->mc.vram_location); |
| } |
| /* Restore CRTC registers */ |
| WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); |
| WREG32(R_0003C0_GENMO_WT, save->GENMO_WT); |
| WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); |
| WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); |
| if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
| 2598,24 → 2701,6 |
| } |
| } |
| void r100_vga_render_disable(struct radeon_device *rdev) |
| { |
| u32 tmp; |
| tmp = RREG8(R_0003C2_GENMO_WT); |
| WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); |
| } |
| static void r100_debugfs(struct radeon_device *rdev) |
| { |
| int r; |
| r = r100_debugfs_mc_info_init(rdev); |
| if (r) |
| dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n"); |
| } |
| int drm_order(unsigned long size) |
| { |
| int order; |
| 2629,193 → 2714,3 |
| return order; |
| } |
| static void r100_mc_program(struct radeon_device *rdev) |
| { |
| struct r100_mc_save save; |
| /* Stops all mc clients */ |
| r100_mc_stop(rdev, &save); |
| if (rdev->flags & RADEON_IS_AGP) { |
| WREG32(R_00014C_MC_AGP_LOCATION, |
| S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | |
| S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); |
| WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); |
| if (rdev->family > CHIP_RV200) |
| WREG32(R_00015C_AGP_BASE_2, |
| upper_32_bits(rdev->mc.agp_base) & 0xff); |
| } else { |
| WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); |
| WREG32(R_000170_AGP_BASE, 0); |
| if (rdev->family > CHIP_RV200) |
| WREG32(R_00015C_AGP_BASE_2, 0); |
| } |
| /* Wait for mc idle */ |
| if (r100_mc_wait_for_idle(rdev)) |
| dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); |
| /* Program MC, should be a 32bits limited address space */ |
| WREG32(R_000148_MC_FB_LOCATION, |
| S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | |
| S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
| r100_mc_resume(rdev, &save); |
| } |
| void r100_clock_startup(struct radeon_device *rdev) |
| { |
| u32 tmp; |
| if (radeon_dynclks != -1 && radeon_dynclks) |
| radeon_legacy_set_clock_gating(rdev, 1); |
| /* We need to force on some of the block */ |
| tmp = RREG32_PLL(R_00000D_SCLK_CNTL); |
| tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); |
| if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) |
| tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1); |
| WREG32_PLL(R_00000D_SCLK_CNTL, tmp); |
| } |
| static int r100_startup(struct radeon_device *rdev) |
| { |
| int r; |
| r100_mc_program(rdev); |
| /* Resume clock */ |
| r100_clock_startup(rdev); |
| /* Initialize GPU configuration (# pipes, ...) */ |
| r100_gpu_init(rdev); |
| /* Initialize GART (initialize after TTM so we can allocate |
| * memory through TTM but finalize after TTM) */ |
| if (rdev->flags & RADEON_IS_PCI) { |
| r = r100_pci_gart_enable(rdev); |
| if (r) |
| return r; |
| } |
| /* Enable IRQ */ |
| // rdev->irq.sw_int = true; |
| // r100_irq_set(rdev); |
| /* 1M ring buffer */ |
| // r = r100_cp_init(rdev, 1024 * 1024); |
| // if (r) { |
| // dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
| // return r; |
| // } |
| // r = r100_wb_init(rdev); |
| // if (r) |
| // dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
| // r = r100_ib_init(rdev); |
| // if (r) { |
| // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
| // return r; |
| // } |
| return 0; |
| } |
| int r100_mc_init(struct radeon_device *rdev) |
| { |
| int r; |
| u32 tmp; |
| /* Setup GPU memory space */ |
| rdev->mc.vram_location = 0xFFFFFFFFUL; |
| rdev->mc.gtt_location = 0xFFFFFFFFUL; |
| if (rdev->flags & RADEON_IS_IGP) { |
| tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM)); |
| rdev->mc.vram_location = tmp << 16; |
| } |
| if (rdev->flags & RADEON_IS_AGP) { |
| r = radeon_agp_init(rdev); |
| if (r) { |
| printk(KERN_WARNING "[drm] Disabling AGP\n"); |
| rdev->flags &= ~RADEON_IS_AGP; |
| rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
| } else { |
| rdev->mc.gtt_location = rdev->mc.agp_base; |
| } |
| } |
| r = radeon_mc_setup(rdev); |
| if (r) |
| return r; |
| return 0; |
| } |
| int r100_init(struct radeon_device *rdev) |
| { |
| int r; |
| /* Register debugfs file specific to this group of asics */ |
| r100_debugfs(rdev); |
| /* Disable VGA */ |
| r100_vga_render_disable(rdev); |
| /* Initialize scratch registers */ |
| radeon_scratch_init(rdev); |
| /* Initialize surface registers */ |
| radeon_surface_init(rdev); |
| /* TODO: disable VGA need to use VGA request */ |
| /* BIOS*/ |
| if (!radeon_get_bios(rdev)) { |
| if (ASIC_IS_AVIVO(rdev)) |
| return -EINVAL; |
| } |
| if (rdev->is_atom_bios) { |
| dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); |
| return -EINVAL; |
| } else { |
| r = radeon_combios_init(rdev); |
| if (r) |
| return r; |
| } |
| /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
| if (radeon_gpu_reset(rdev)) { |
| dev_warn(rdev->dev, |
| "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
| RREG32(R_000E40_RBBM_STATUS), |
| RREG32(R_0007C0_CP_STAT)); |
| } |
| /* check if cards are posted or not */ |
| if (!radeon_card_posted(rdev) && rdev->bios) { |
| DRM_INFO("GPU not posted. posting now...\n"); |
| radeon_combios_asic_init(rdev->ddev); |
| } |
| /* Set asic errata */ |
| r100_errata(rdev); |
| /* Initialize clocks */ |
| radeon_get_clock_info(rdev->ddev); |
| /* Get vram informations */ |
| r100_vram_info(rdev); |
| /* Initialize memory controller (also test AGP) */ |
| r = r100_mc_init(rdev); |
| if (r) |
| return r; |
| /* Fence driver */ |
| // r = radeon_fence_driver_init(rdev); |
| // if (r) |
| // return r; |
| // r = radeon_irq_kms_init(rdev); |
| // if (r) |
| // return r; |
| /* Memory manager */ |
| r = radeon_object_init(rdev); |
| if (r) |
| return r; |
| if (rdev->flags & RADEON_IS_PCI) { |
| r = r100_pci_gart_init(rdev); |
| if (r) |
| return r; |
| } |
| r100_set_safe_registers(rdev); |
| rdev->accel_working = true; |
| r = r100_startup(rdev); |
| if (r) { |
| /* Somethings want wront with the accel init stop accel */ |
| dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
| // r100_suspend(rdev); |
| // r100_cp_fini(rdev); |
| // r100_wb_fini(rdev); |
| // r100_ib_fini(rdev); |
| if (rdev->flags & RADEON_IS_PCI) |
| r100_pci_gart_fini(rdev); |
| // radeon_irq_kms_fini(rdev); |
| rdev->accel_working = false; |
| } |
| return 0; |
| } |
| /drivers/video/drm/radeon/r100d.h |
|---|
| 381,24 → 381,6 |
| #define S_000054_VCRTC_IDX_MASTER(x) (((x) & 0x7F) << 24) |
| #define G_000054_VCRTC_IDX_MASTER(x) (((x) >> 24) & 0x7F) |
| #define C_000054_VCRTC_IDX_MASTER 0x80FFFFFF |
| #define R_000148_MC_FB_LOCATION 0x000148 |
| #define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) |
| #define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF) |
| #define C_000148_MC_FB_START 0xFFFF0000 |
| #define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) |
| #define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) |
| #define C_000148_MC_FB_TOP 0x0000FFFF |
| #define R_00014C_MC_AGP_LOCATION 0x00014C |
| #define S_00014C_MC_AGP_START(x) (((x) & 0xFFFF) << 0) |
| #define G_00014C_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) |
| #define C_00014C_MC_AGP_START 0xFFFF0000 |
| #define S_00014C_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) |
| #define G_00014C_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) |
| #define C_00014C_MC_AGP_TOP 0x0000FFFF |
| #define R_000170_AGP_BASE 0x000170 |
| #define S_000170_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) |
| #define G_000170_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) |
| #define C_000170_AGP_BASE_ADDR 0x00000000 |
| #define R_00023C_DISPLAY_BASE_ADDR 0x00023C |
| #define S_00023C_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) |
| #define G_00023C_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) |
| 421,25 → 403,25 |
| #define S_000360_CUR2_LOCK(x) (((x) & 0x1) << 31) |
| #define G_000360_CUR2_LOCK(x) (((x) >> 31) & 0x1) |
| #define C_000360_CUR2_LOCK 0x7FFFFFFF |
| #define R_0003C2_GENMO_WT 0x0003C0 |
| #define S_0003C2_GENMO_MONO_ADDRESS_B(x) (((x) & 0x1) << 0) |
| #define G_0003C2_GENMO_MONO_ADDRESS_B(x) (((x) >> 0) & 0x1) |
| #define C_0003C2_GENMO_MONO_ADDRESS_B 0xFE |
| #define S_0003C2_VGA_RAM_EN(x) (((x) & 0x1) << 1) |
| #define G_0003C2_VGA_RAM_EN(x) (((x) >> 1) & 0x1) |
| #define C_0003C2_VGA_RAM_EN 0xFD |
| #define S_0003C2_VGA_CKSEL(x) (((x) & 0x3) << 2) |
| #define G_0003C2_VGA_CKSEL(x) (((x) >> 2) & 0x3) |
| #define C_0003C2_VGA_CKSEL 0xF3 |
| #define S_0003C2_ODD_EVEN_MD_PGSEL(x) (((x) & 0x1) << 5) |
| #define G_0003C2_ODD_EVEN_MD_PGSEL(x) (((x) >> 5) & 0x1) |
| #define C_0003C2_ODD_EVEN_MD_PGSEL 0xDF |
| #define S_0003C2_VGA_HSYNC_POL(x) (((x) & 0x1) << 6) |
| #define G_0003C2_VGA_HSYNC_POL(x) (((x) >> 6) & 0x1) |
| #define C_0003C2_VGA_HSYNC_POL 0xBF |
| #define S_0003C2_VGA_VSYNC_POL(x) (((x) & 0x1) << 7) |
| #define G_0003C2_VGA_VSYNC_POL(x) (((x) >> 7) & 0x1) |
| #define C_0003C2_VGA_VSYNC_POL 0x7F |
| #define R_0003C0_GENMO_WT 0x0003C0 |
| #define S_0003C0_GENMO_MONO_ADDRESS_B(x) (((x) & 0x1) << 0) |
| #define G_0003C0_GENMO_MONO_ADDRESS_B(x) (((x) >> 0) & 0x1) |
| #define C_0003C0_GENMO_MONO_ADDRESS_B 0xFFFFFFFE |
| #define S_0003C0_VGA_RAM_EN(x) (((x) & 0x1) << 1) |
| #define G_0003C0_VGA_RAM_EN(x) (((x) >> 1) & 0x1) |
| #define C_0003C0_VGA_RAM_EN 0xFFFFFFFD |
| #define S_0003C0_VGA_CKSEL(x) (((x) & 0x3) << 2) |
| #define G_0003C0_VGA_CKSEL(x) (((x) >> 2) & 0x3) |
| #define C_0003C0_VGA_CKSEL 0xFFFFFFF3 |
| #define S_0003C0_ODD_EVEN_MD_PGSEL(x) (((x) & 0x1) << 5) |
| #define G_0003C0_ODD_EVEN_MD_PGSEL(x) (((x) >> 5) & 0x1) |
| #define C_0003C0_ODD_EVEN_MD_PGSEL 0xFFFFFFDF |
| #define S_0003C0_VGA_HSYNC_POL(x) (((x) & 0x1) << 6) |
| #define G_0003C0_VGA_HSYNC_POL(x) (((x) >> 6) & 0x1) |
| #define C_0003C0_VGA_HSYNC_POL 0xFFFFFFBF |
| #define S_0003C0_VGA_VSYNC_POL(x) (((x) & 0x1) << 7) |
| #define G_0003C0_VGA_VSYNC_POL(x) (((x) >> 7) & 0x1) |
| #define C_0003C0_VGA_VSYNC_POL 0xFFFFFF7F |
| #define R_0003F8_CRTC2_GEN_CNTL 0x0003F8 |
| #define S_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) & 0x1) << 0) |
| #define G_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) >> 0) & 0x1) |
| 563,46 → 545,6 |
| #define S_000774_SCRATCH_ADDR(x) (((x) & 0x7FFFFFF) << 5) |
| #define G_000774_SCRATCH_ADDR(x) (((x) >> 5) & 0x7FFFFFF) |
| #define C_000774_SCRATCH_ADDR 0x0000001F |
| #define R_0007C0_CP_STAT 0x0007C0 |
| #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) |
| #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) |
| #define C_0007C0_MRU_BUSY 0xFFFFFFFE |
| #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) |
| #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) |
| #define C_0007C0_MWU_BUSY 0xFFFFFFFD |
| #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) |
| #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) |
| #define C_0007C0_RSIU_BUSY 0xFFFFFFFB |
| #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) |
| #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) |
| #define C_0007C0_RCIU_BUSY 0xFFFFFFF7 |
| #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) |
| #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) |
| #define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF |
| #define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10) |
| #define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1) |
| #define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF |
| #define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11) |
| #define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1) |
| #define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF |
| #define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12) |
| #define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1) |
| #define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF |
| #define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13) |
| #define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1) |
| #define C_0007C0_CSI_BUSY 0xFFFFDFFF |
| #define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28) |
| #define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1) |
| #define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF |
| #define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29) |
| #define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1) |
| #define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF |
| #define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30) |
| #define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1) |
| #define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF |
| #define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31) |
| #define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1) |
| #define C_0007C0_CP_BUSY 0x7FFFFFFF |
| #define R_000E40_RBBM_STATUS 0x000E40 |
| #define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) |
| #define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) |
| 662,53 → 604,4 |
| #define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) |
| #define C_000E40_GUI_ACTIVE 0x7FFFFFFF |
| #define R_00000D_SCLK_CNTL 0x00000D |
| #define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0) |
| #define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7) |
| #define C_00000D_SCLK_SRC_SEL 0xFFFFFFF8 |
| #define S_00000D_TCLK_SRC_SEL(x) (((x) & 0x7) << 8) |
| #define G_00000D_TCLK_SRC_SEL(x) (((x) >> 8) & 0x7) |
| #define C_00000D_TCLK_SRC_SEL 0xFFFFF8FF |
| #define S_00000D_FORCE_CP(x) (((x) & 0x1) << 16) |
| #define G_00000D_FORCE_CP(x) (((x) >> 16) & 0x1) |
| #define C_00000D_FORCE_CP 0xFFFEFFFF |
| #define S_00000D_FORCE_HDP(x) (((x) & 0x1) << 17) |
| #define G_00000D_FORCE_HDP(x) (((x) >> 17) & 0x1) |
| #define C_00000D_FORCE_HDP 0xFFFDFFFF |
| #define S_00000D_FORCE_DISP(x) (((x) & 0x1) << 18) |
| #define G_00000D_FORCE_DISP(x) (((x) >> 18) & 0x1) |
| #define C_00000D_FORCE_DISP 0xFFFBFFFF |
| #define S_00000D_FORCE_TOP(x) (((x) & 0x1) << 19) |
| #define G_00000D_FORCE_TOP(x) (((x) >> 19) & 0x1) |
| #define C_00000D_FORCE_TOP 0xFFF7FFFF |
| #define S_00000D_FORCE_E2(x) (((x) & 0x1) << 20) |
| #define G_00000D_FORCE_E2(x) (((x) >> 20) & 0x1) |
| #define C_00000D_FORCE_E2 0xFFEFFFFF |
| #define S_00000D_FORCE_SE(x) (((x) & 0x1) << 21) |
| #define G_00000D_FORCE_SE(x) (((x) >> 21) & 0x1) |
| #define C_00000D_FORCE_SE 0xFFDFFFFF |
| #define S_00000D_FORCE_IDCT(x) (((x) & 0x1) << 22) |
| #define G_00000D_FORCE_IDCT(x) (((x) >> 22) & 0x1) |
| #define C_00000D_FORCE_IDCT 0xFFBFFFFF |
| #define S_00000D_FORCE_VIP(x) (((x) & 0x1) << 23) |
| #define G_00000D_FORCE_VIP(x) (((x) >> 23) & 0x1) |
| #define C_00000D_FORCE_VIP 0xFF7FFFFF |
| #define S_00000D_FORCE_RE(x) (((x) & 0x1) << 24) |
| #define G_00000D_FORCE_RE(x) (((x) >> 24) & 0x1) |
| #define C_00000D_FORCE_RE 0xFEFFFFFF |
| #define S_00000D_FORCE_PB(x) (((x) & 0x1) << 25) |
| #define G_00000D_FORCE_PB(x) (((x) >> 25) & 0x1) |
| #define C_00000D_FORCE_PB 0xFDFFFFFF |
| #define S_00000D_FORCE_TAM(x) (((x) & 0x1) << 26) |
| #define G_00000D_FORCE_TAM(x) (((x) >> 26) & 0x1) |
| #define C_00000D_FORCE_TAM 0xFBFFFFFF |
| #define S_00000D_FORCE_TDM(x) (((x) & 0x1) << 27) |
| #define G_00000D_FORCE_TDM(x) (((x) >> 27) & 0x1) |
| #define C_00000D_FORCE_TDM 0xF7FFFFFF |
| #define S_00000D_FORCE_RB(x) (((x) & 0x1) << 28) |
| #define G_00000D_FORCE_RB(x) (((x) >> 28) & 0x1) |
| #define C_00000D_FORCE_RB 0xEFFFFFFF |
| #endif |
| /drivers/video/drm/radeon/r200.c |
|---|
| 97,6 → 97,7 |
| struct radeon_cs_packet *pkt, |
| unsigned idx, unsigned reg) |
| { |
| struct radeon_cs_chunk *ib_chunk; |
| struct radeon_cs_reloc *reloc; |
| struct r100_cs_track *track; |
| volatile uint32_t *ib; |
| 105,11 → 106,11 |
| int i; |
| int face; |
| u32 tile_flags = 0; |
| u32 idx_value; |
| ib = p->ib->ptr; |
| ib_chunk = &p->chunks[p->chunk_ib_idx]; |
| track = (struct r100_cs_track *)p->track; |
| idx_value = radeon_get_ib_value(p, idx); |
| switch (reg) { |
| case RADEON_CRTC_GUI_TRIG_VLINE: |
| r = r100_cs_packet_parse_vline(p); |
| 137,8 → 138,8 |
| return r; |
| } |
| track->zb.robj = reloc->robj; |
| track->zb.offset = idx_value; |
| ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
| track->zb.offset = ib_chunk->kdata[idx]; |
| ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
| break; |
| case RADEON_RB3D_COLOROFFSET: |
| r = r100_cs_packet_next_reloc(p, &reloc); |
| 149,8 → 150,8 |
| return r; |
| } |
| track->cb[0].robj = reloc->robj; |
| track->cb[0].offset = idx_value; |
| ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
| track->cb[0].offset = ib_chunk->kdata[idx]; |
| ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
| break; |
| case R200_PP_TXOFFSET_0: |
| case R200_PP_TXOFFSET_1: |
| 166,7 → 167,7 |
| r100_cs_dump_packet(p, pkt); |
| return r; |
| } |
| ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
| ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
| track->textures[i].robj = reloc->robj; |
| break; |
| case R200_PP_CUBIC_OFFSET_F1_0: |
| 208,12 → 209,12 |
| r100_cs_dump_packet(p, pkt); |
| return r; |
| } |
| track->textures[i].cube_info[face - 1].offset = idx_value; |
| ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
| track->textures[i].cube_info[face - 1].offset = ib_chunk->kdata[idx]; |
| ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
| track->textures[i].cube_info[face - 1].robj = reloc->robj; |
| break; |
| case RADEON_RE_WIDTH_HEIGHT: |
| track->maxy = ((idx_value >> 16) & 0x7FF); |
| track->maxy = ((ib_chunk->kdata[idx] >> 16) & 0x7FF); |
| break; |
| case RADEON_RB3D_COLORPITCH: |
| r = r100_cs_packet_next_reloc(p, &reloc); |
| 229,17 → 230,17 |
| if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
| tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; |
| tmp = idx_value & ~(0x7 << 16); |
| tmp = ib_chunk->kdata[idx] & ~(0x7 << 16); |
| tmp |= tile_flags; |
| ib[idx] = tmp; |
| track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; |
| track->cb[0].pitch = ib_chunk->kdata[idx] & RADEON_COLORPITCH_MASK; |
| break; |
| case RADEON_RB3D_DEPTHPITCH: |
| track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; |
| track->zb.pitch = ib_chunk->kdata[idx] & RADEON_DEPTHPITCH_MASK; |
| break; |
| case RADEON_RB3D_CNTL: |
| switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { |
| switch ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { |
| case 7: |
| case 8: |
| case 9: |
| 257,18 → 258,18 |
| break; |
| default: |
| DRM_ERROR("Invalid color buffer format (%d) !\n", |
| ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); |
| ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); |
| return -EINVAL; |
| } |
| if (idx_value & RADEON_DEPTHXY_OFFSET_ENABLE) { |
| if (ib_chunk->kdata[idx] & RADEON_DEPTHXY_OFFSET_ENABLE) { |
| DRM_ERROR("No support for depth xy offset in kms\n"); |
| return -EINVAL; |
| } |
| track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); |
| track->z_enabled = !!(ib_chunk->kdata[idx] & RADEON_Z_ENABLE); |
| break; |
| case RADEON_RB3D_ZSTENCILCNTL: |
| switch (idx_value & 0xf) { |
| switch (ib_chunk->kdata[idx] & 0xf) { |
| case 0: |
| track->zb.cpp = 2; |
| break; |
| 292,27 → 293,27 |
| r100_cs_dump_packet(p, pkt); |
| return r; |
| } |
| ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
| ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
| break; |
| case RADEON_PP_CNTL: |
| { |
| uint32_t temp = idx_value >> 4; |
| uint32_t temp = ib_chunk->kdata[idx] >> 4; |
| for (i = 0; i < track->num_texture; i++) |
| track->textures[i].enabled = !!(temp & (1 << i)); |
| } |
| break; |
| case RADEON_SE_VF_CNTL: |
| track->vap_vf_cntl = idx_value; |
| track->vap_vf_cntl = ib_chunk->kdata[idx]; |
| break; |
| case 0x210c: |
| /* VAP_VF_MAX_VTX_INDX */ |
| track->max_indx = idx_value & 0x00FFFFFFUL; |
| track->max_indx = ib_chunk->kdata[idx] & 0x00FFFFFFUL; |
| break; |
| case R200_SE_VTX_FMT_0: |
| track->vtx_size = r200_get_vtx_size_0(idx_value); |
| track->vtx_size = r200_get_vtx_size_0(ib_chunk->kdata[idx]); |
| break; |
| case R200_SE_VTX_FMT_1: |
| track->vtx_size += r200_get_vtx_size_1(idx_value); |
| track->vtx_size += r200_get_vtx_size_1(ib_chunk->kdata[idx]); |
| break; |
| case R200_PP_TXSIZE_0: |
| case R200_PP_TXSIZE_1: |
| 321,8 → 322,8 |
| case R200_PP_TXSIZE_4: |
| case R200_PP_TXSIZE_5: |
| i = (reg - R200_PP_TXSIZE_0) / 32; |
| track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; |
| track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; |
| track->textures[i].width = (ib_chunk->kdata[idx] & RADEON_TEX_USIZE_MASK) + 1; |
| track->textures[i].height = ((ib_chunk->kdata[idx] & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; |
| break; |
| case R200_PP_TXPITCH_0: |
| case R200_PP_TXPITCH_1: |
| 331,7 → 332,7 |
| case R200_PP_TXPITCH_4: |
| case R200_PP_TXPITCH_5: |
| i = (reg - R200_PP_TXPITCH_0) / 32; |
| track->textures[i].pitch = idx_value + 32; |
| track->textures[i].pitch = ib_chunk->kdata[idx] + 32; |
| break; |
| case R200_PP_TXFILTER_0: |
| case R200_PP_TXFILTER_1: |
| 340,12 → 341,12 |
| case R200_PP_TXFILTER_4: |
| case R200_PP_TXFILTER_5: |
| i = (reg - R200_PP_TXFILTER_0) / 32; |
| track->textures[i].num_levels = ((idx_value & R200_MAX_MIP_LEVEL_MASK) |
| track->textures[i].num_levels = ((ib_chunk->kdata[idx] & R200_MAX_MIP_LEVEL_MASK) |
| >> R200_MAX_MIP_LEVEL_SHIFT); |
| tmp = (idx_value >> 23) & 0x7; |
| tmp = (ib_chunk->kdata[idx] >> 23) & 0x7; |
| if (tmp == 2 || tmp == 6) |
| track->textures[i].roundup_w = false; |
| tmp = (idx_value >> 27) & 0x7; |
| tmp = (ib_chunk->kdata[idx] >> 27) & 0x7; |
| if (tmp == 2 || tmp == 6) |
| track->textures[i].roundup_h = false; |
| break; |
| 364,8 → 365,8 |
| case R200_PP_TXFORMAT_X_4: |
| case R200_PP_TXFORMAT_X_5: |
| i = (reg - R200_PP_TXFORMAT_X_0) / 32; |
| track->textures[i].txdepth = idx_value & 0x7; |
| tmp = (idx_value >> 16) & 0x3; |
| track->textures[i].txdepth = ib_chunk->kdata[idx] & 0x7; |
| tmp = (ib_chunk->kdata[idx] >> 16) & 0x3; |
| /* 2D, 3D, CUBE */ |
| switch (tmp) { |
| case 0: |
| 389,14 → 390,14 |
| case R200_PP_TXFORMAT_4: |
| case R200_PP_TXFORMAT_5: |
| i = (reg - R200_PP_TXFORMAT_0) / 32; |
| if (idx_value & R200_TXFORMAT_NON_POWER2) { |
| if (ib_chunk->kdata[idx] & R200_TXFORMAT_NON_POWER2) { |
| track->textures[i].use_pitch = 1; |
| } else { |
| track->textures[i].use_pitch = 0; |
| track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); |
| track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); |
| track->textures[i].width = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); |
| track->textures[i].height = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); |
| } |
| switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { |
| switch ((ib_chunk->kdata[idx] & RADEON_TXFORMAT_FORMAT_MASK)) { |
| case R200_TXFORMAT_I8: |
| case R200_TXFORMAT_RGB332: |
| case R200_TXFORMAT_Y8: |
| 424,8 → 425,8 |
| track->textures[i].cpp = 4; |
| break; |
| } |
| track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); |
| track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); |
| track->textures[i].cube_info[4].width = 1 << ((ib_chunk->kdata[idx] >> 16) & 0xf); |
| track->textures[i].cube_info[4].height = 1 << ((ib_chunk->kdata[idx] >> 20) & 0xf); |
| break; |
| case R200_PP_CUBIC_FACES_0: |
| case R200_PP_CUBIC_FACES_1: |
| 433,7 → 434,7 |
| case R200_PP_CUBIC_FACES_3: |
| case R200_PP_CUBIC_FACES_4: |
| case R200_PP_CUBIC_FACES_5: |
| tmp = idx_value; |
| tmp = ib_chunk->kdata[idx]; |
| i = (reg - R200_PP_CUBIC_FACES_0) / 32; |
| for (face = 0; face < 4; face++) { |
| track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); |
| 449,8 → 450,9 |
| } |
| #endif |
| void r200_set_safe_registers(struct radeon_device *rdev) |
| int r200_init(struct radeon_device *rdev) |
| { |
| rdev->config.r100.reg_safe_bm = r200_reg_safe_bm; |
| rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r200_reg_safe_bm); |
| return 0; |
| } |
| /drivers/video/drm/radeon/r300.c |
|---|
| 33,16 → 33,43 |
| #include "radeon_drm.h" |
| #include "r300d.h" |
| #include "rv350d.h" |
| #include "r300_reg_safe.h" |
| /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 */ |
| /* r300,r350,rv350,rv370,rv380 depends on : */ |
| void r100_hdp_reset(struct radeon_device *rdev); |
| int r100_cp_reset(struct radeon_device *rdev); |
| int r100_rb2d_reset(struct radeon_device *rdev); |
| int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); |
| int r100_pci_gart_enable(struct radeon_device *rdev); |
| void r100_mc_setup(struct radeon_device *rdev); |
| void r100_mc_disable_clients(struct radeon_device *rdev); |
| int r100_gui_wait_for_idle(struct radeon_device *rdev); |
| int r100_cs_packet_parse(struct radeon_cs_parser *p, |
| struct radeon_cs_packet *pkt, |
| unsigned idx); |
| int r100_cs_packet_parse_vline(struct radeon_cs_parser *p); |
| int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
| struct radeon_cs_packet *pkt, |
| const unsigned *auth, unsigned n, |
| radeon_packet0_check_t check); |
| int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
| struct radeon_cs_packet *pkt, |
| struct radeon_object *robj); |
| /* This files gather functions specifics to: |
| * r300,r350,rv350,rv370,rv380 |
| * |
| * Some of these functions might be used by newer ASICs. |
| */ |
| void r300_gpu_init(struct radeon_device *rdev); |
| int r300_mc_wait_for_idle(struct radeon_device *rdev); |
| int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev); |
| /* |
| * rv370,rv380 PCIE GART |
| */ |
| static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev); |
| void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) |
| { |
| uint32_t tmp; |
| 155,6 → 182,49 |
| radeon_gart_fini(rdev); |
| } |
| /* |
| * MC |
| */ |
| int r300_mc_init(struct radeon_device *rdev) |
| { |
| int r; |
| if (r100_debugfs_rbbm_init(rdev)) { |
| DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
| } |
| r300_gpu_init(rdev); |
| r100_pci_gart_disable(rdev); |
| if (rdev->flags & RADEON_IS_PCIE) { |
| rv370_pcie_gart_disable(rdev); |
| } |
| /* Setup GPU memory space */ |
| rdev->mc.vram_location = 0xFFFFFFFFUL; |
| rdev->mc.gtt_location = 0xFFFFFFFFUL; |
| r = radeon_mc_setup(rdev); |
| if (r) { |
| return r; |
| } |
| /* Program GPU memory space */ |
| r100_mc_disable_clients(rdev); |
| if (r300_mc_wait_for_idle(rdev)) { |
| printk(KERN_WARNING "Failed to wait MC idle while " |
| "programming pipes. Bad things might happen.\n"); |
| } |
| r100_mc_setup(rdev); |
| return 0; |
| } |
| void r300_mc_fini(struct radeon_device *rdev) |
| { |
| } |
| /* |
| * Fence emission |
| */ |
| void r300_fence_ring_emit(struct radeon_device *rdev, |
| struct radeon_fence *fence) |
| { |
| 183,7 → 253,9 |
| #if 0 |
| /* |
| * Global GPU functions |
| */ |
| int r300_copy_dma(struct radeon_device *rdev, |
| uint64_t src_offset, |
| uint64_t dst_offset, |
| 504,6 → 576,11 |
| r100_vram_init_sizes(rdev); |
| } |
| /* |
| * PCIE Lanes |
| */ |
| void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) |
| { |
| uint32_t link_width_cntl, mask; |
| 563,6 → 640,10 |
| } |
| /* |
| * Debugfs info |
| */ |
| #if defined(CONFIG_DEBUG_FS) |
| static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data) |
| { |
| 593,7 → 674,7 |
| }; |
| #endif |
| static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) |
| int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) |
| { |
| #if defined(CONFIG_DEBUG_FS) |
| return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1); |
| 604,11 → 685,14 |
| #if 0 |
| /* |
| * CS functions |
| */ |
| static int r300_packet0_check(struct radeon_cs_parser *p, |
| struct radeon_cs_packet *pkt, |
| unsigned idx, unsigned reg) |
| { |
| struct radeon_cs_chunk *ib_chunk; |
| struct radeon_cs_reloc *reloc; |
| struct r100_cs_track *track; |
| volatile uint32_t *ib; |
| 615,12 → 699,10 |
| uint32_t tmp, tile_flags = 0; |
| unsigned i; |
| int r; |
| u32 idx_value; |
| ib = p->ib->ptr; |
| ib_chunk = &p->chunks[p->chunk_ib_idx]; |
| track = (struct r100_cs_track *)p->track; |
| idx_value = radeon_get_ib_value(p, idx); |
| switch(reg) { |
| case AVIVO_D1MODE_VLINE_START_END: |
| case RADEON_CRTC_GUI_TRIG_VLINE: |
| 651,8 → 733,8 |
| return r; |
| } |
| track->cb[i].robj = reloc->robj; |
| track->cb[i].offset = idx_value; |
| ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
| track->cb[i].offset = ib_chunk->kdata[idx]; |
| ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
| break; |
| case R300_ZB_DEPTHOFFSET: |
| r = r100_cs_packet_next_reloc(p, &reloc); |
| 663,8 → 745,8 |
| return r; |
| } |
| track->zb.robj = reloc->robj; |
| track->zb.offset = idx_value; |
| ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
| track->zb.offset = ib_chunk->kdata[idx]; |
| ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
| break; |
| case R300_TX_OFFSET_0: |
| case R300_TX_OFFSET_0+4: |
| 690,25 → 772,25 |
| r100_cs_dump_packet(p, pkt); |
| return r; |
| } |
| ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
| ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
| track->textures[i].robj = reloc->robj; |
| break; |
| /* Tracked registers */ |
| case 0x2084: |
| /* VAP_VF_CNTL */ |
| track->vap_vf_cntl = idx_value; |
| track->vap_vf_cntl = ib_chunk->kdata[idx]; |
| break; |
| case 0x20B4: |
| /* VAP_VTX_SIZE */ |
| track->vtx_size = idx_value & 0x7F; |
| track->vtx_size = ib_chunk->kdata[idx] & 0x7F; |
| break; |
| case 0x2134: |
| /* VAP_VF_MAX_VTX_INDX */ |
| track->max_indx = idx_value & 0x00FFFFFFUL; |
| track->max_indx = ib_chunk->kdata[idx] & 0x00FFFFFFUL; |
| break; |
| case 0x43E4: |
| /* SC_SCISSOR1 */ |
| track->maxy = ((idx_value >> 13) & 0x1FFF) + 1; |
| track->maxy = ((ib_chunk->kdata[idx] >> 13) & 0x1FFF) + 1; |
| if (p->rdev->family < CHIP_RV515) { |
| track->maxy -= 1440; |
| } |
| 715,7 → 797,7 |
| break; |
| case 0x4E00: |
| /* RB3D_CCTL */ |
| track->num_cb = ((idx_value >> 5) & 0x3) + 1; |
| track->num_cb = ((ib_chunk->kdata[idx] >> 5) & 0x3) + 1; |
| break; |
| case 0x4E38: |
| case 0x4E3C: |
| 738,13 → 820,13 |
| if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
| tile_flags |= R300_COLOR_MICROTILE_ENABLE; |
| tmp = idx_value & ~(0x7 << 16); |
| tmp = ib_chunk->kdata[idx] & ~(0x7 << 16); |
| tmp |= tile_flags; |
| ib[idx] = tmp; |
| i = (reg - 0x4E38) >> 2; |
| track->cb[i].pitch = idx_value & 0x3FFE; |
| switch (((idx_value >> 21) & 0xF)) { |
| track->cb[i].pitch = ib_chunk->kdata[idx] & 0x3FFE; |
| switch (((ib_chunk->kdata[idx] >> 21) & 0xF)) { |
| case 9: |
| case 11: |
| case 12: |
| 767,13 → 849,13 |
| break; |
| default: |
| DRM_ERROR("Invalid color buffer format (%d) !\n", |
| ((idx_value >> 21) & 0xF)); |
| ((ib_chunk->kdata[idx] >> 21) & 0xF)); |
| return -EINVAL; |
| } |
| break; |
| case 0x4F00: |
| /* ZB_CNTL */ |
| if (idx_value & 2) { |
| if (ib_chunk->kdata[idx] & 2) { |
| track->z_enabled = true; |
| } else { |
| track->z_enabled = false; |
| 781,7 → 863,7 |
| break; |
| case 0x4F10: |
| /* ZB_FORMAT */ |
| switch ((idx_value & 0xF)) { |
| switch ((ib_chunk->kdata[idx] & 0xF)) { |
| case 0: |
| case 1: |
| track->zb.cpp = 2; |
| 791,7 → 873,7 |
| break; |
| default: |
| DRM_ERROR("Invalid z buffer format (%d) !\n", |
| (idx_value & 0xF)); |
| (ib_chunk->kdata[idx] & 0xF)); |
| return -EINVAL; |
| } |
| break; |
| 810,17 → 892,17 |
| if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
| tile_flags |= R300_DEPTHMICROTILE_TILED;; |
| tmp = idx_value & ~(0x7 << 16); |
| tmp = ib_chunk->kdata[idx] & ~(0x7 << 16); |
| tmp |= tile_flags; |
| ib[idx] = tmp; |
| track->zb.pitch = idx_value & 0x3FFC; |
| track->zb.pitch = ib_chunk->kdata[idx] & 0x3FFC; |
| break; |
| case 0x4104: |
| for (i = 0; i < 16; i++) { |
| bool enabled; |
| enabled = !!(idx_value & (1 << i)); |
| enabled = !!(ib_chunk->kdata[idx] & (1 << i)); |
| track->textures[i].enabled = enabled; |
| } |
| break; |
| 842,9 → 924,9 |
| case 0x44FC: |
| /* TX_FORMAT1_[0-15] */ |
| i = (reg - 0x44C0) >> 2; |
| tmp = (idx_value >> 25) & 0x3; |
| tmp = (ib_chunk->kdata[idx] >> 25) & 0x3; |
| track->textures[i].tex_coord_type = tmp; |
| switch ((idx_value & 0x1F)) { |
| switch ((ib_chunk->kdata[idx] & 0x1F)) { |
| case R300_TX_FORMAT_X8: |
| case R300_TX_FORMAT_Y4X4: |
| case R300_TX_FORMAT_Z3Y3X2: |
| 884,7 → 966,7 |
| break; |
| default: |
| DRM_ERROR("Invalid texture format %u\n", |
| (idx_value & 0x1F)); |
| (ib_chunk->kdata[idx] & 0x1F)); |
| return -EINVAL; |
| break; |
| } |
| 907,11 → 989,11 |
| case 0x443C: |
| /* TX_FILTER0_[0-15] */ |
| i = (reg - 0x4400) >> 2; |
| tmp = idx_value & 0x7; |
| tmp = ib_chunk->kdata[idx] & 0x7; |
| if (tmp == 2 || tmp == 4 || tmp == 6) { |
| track->textures[i].roundup_w = false; |
| } |
| tmp = (idx_value >> 3) & 0x7; |
| tmp = (ib_chunk->kdata[idx] >> 3) & 0x7; |
| if (tmp == 2 || tmp == 4 || tmp == 6) { |
| track->textures[i].roundup_h = false; |
| } |
| 934,12 → 1016,12 |
| case 0x453C: |
| /* TX_FORMAT2_[0-15] */ |
| i = (reg - 0x4500) >> 2; |
| tmp = idx_value & 0x3FFF; |
| tmp = ib_chunk->kdata[idx] & 0x3FFF; |
| track->textures[i].pitch = tmp + 1; |
| if (p->rdev->family >= CHIP_RV515) { |
| tmp = ((idx_value >> 15) & 1) << 11; |
| tmp = ((ib_chunk->kdata[idx] >> 15) & 1) << 11; |
| track->textures[i].width_11 = tmp; |
| tmp = ((idx_value >> 16) & 1) << 11; |
| tmp = ((ib_chunk->kdata[idx] >> 16) & 1) << 11; |
| track->textures[i].height_11 = tmp; |
| } |
| break; |
| 961,15 → 1043,15 |
| case 0x44BC: |
| /* TX_FORMAT0_[0-15] */ |
| i = (reg - 0x4480) >> 2; |
| tmp = idx_value & 0x7FF; |
| tmp = ib_chunk->kdata[idx] & 0x7FF; |
| track->textures[i].width = tmp + 1; |
| tmp = (idx_value >> 11) & 0x7FF; |
| tmp = (ib_chunk->kdata[idx] >> 11) & 0x7FF; |
| track->textures[i].height = tmp + 1; |
| tmp = (idx_value >> 26) & 0xF; |
| tmp = (ib_chunk->kdata[idx] >> 26) & 0xF; |
| track->textures[i].num_levels = tmp; |
| tmp = idx_value & (1 << 31); |
| tmp = ib_chunk->kdata[idx] & (1 << 31); |
| track->textures[i].use_pitch = !!tmp; |
| tmp = (idx_value >> 22) & 0xF; |
| tmp = (ib_chunk->kdata[idx] >> 22) & 0xF; |
| track->textures[i].txdepth = tmp; |
| break; |
| case R300_ZB_ZPASS_ADDR: |
| 980,7 → 1062,7 |
| r100_cs_dump_packet(p, pkt); |
| return r; |
| } |
| ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
| ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
| break; |
| case 0x4be8: |
| /* valid register only on RV530 */ |
| 998,20 → 1080,60 |
| static int r300_packet3_check(struct radeon_cs_parser *p, |
| struct radeon_cs_packet *pkt) |
| { |
| struct radeon_cs_chunk *ib_chunk; |
| struct radeon_cs_reloc *reloc; |
| struct r100_cs_track *track; |
| volatile uint32_t *ib; |
| unsigned idx; |
| unsigned i, c; |
| int r; |
| ib = p->ib->ptr; |
| ib_chunk = &p->chunks[p->chunk_ib_idx]; |
| idx = pkt->idx + 1; |
| track = (struct r100_cs_track *)p->track; |
| switch(pkt->opcode) { |
| case PACKET3_3D_LOAD_VBPNTR: |
| r = r100_packet3_load_vbpntr(p, pkt, idx); |
| if (r) |
| c = ib_chunk->kdata[idx++] & 0x1F; |
| track->num_arrays = c; |
| for (i = 0; i < (c - 1); i+=2, idx+=3) { |
| r = r100_cs_packet_next_reloc(p, &reloc); |
| if (r) { |
| DRM_ERROR("No reloc for packet3 %d\n", |
| pkt->opcode); |
| r100_cs_dump_packet(p, pkt); |
| return r; |
| } |
| ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); |
| track->arrays[i + 0].robj = reloc->robj; |
| track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8; |
| track->arrays[i + 0].esize &= 0x7F; |
| r = r100_cs_packet_next_reloc(p, &reloc); |
| if (r) { |
| DRM_ERROR("No reloc for packet3 %d\n", |
| pkt->opcode); |
| r100_cs_dump_packet(p, pkt); |
| return r; |
| } |
| ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset); |
| track->arrays[i + 1].robj = reloc->robj; |
| track->arrays[i + 1].esize = ib_chunk->kdata[idx] >> 24; |
| track->arrays[i + 1].esize &= 0x7F; |
| } |
| if (c & 1) { |
| r = r100_cs_packet_next_reloc(p, &reloc); |
| if (r) { |
| DRM_ERROR("No reloc for packet3 %d\n", |
| pkt->opcode); |
| r100_cs_dump_packet(p, pkt); |
| return r; |
| } |
| ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); |
| track->arrays[i + 0].robj = reloc->robj; |
| track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8; |
| track->arrays[i + 0].esize &= 0x7F; |
| } |
| break; |
| case PACKET3_INDX_BUFFER: |
| r = r100_cs_packet_next_reloc(p, &reloc); |
| 1020,7 → 1142,7 |
| r100_cs_dump_packet(p, pkt); |
| return r; |
| } |
| ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); |
| ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); |
| r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); |
| if (r) { |
| return r; |
| 1031,11 → 1153,11 |
| /* Number of dwords is vtx_size * (num_vertices - 1) |
| * PRIM_WALK must be equal to 3 vertex data in embedded |
| * in cmd stream */ |
| if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { |
| if (((ib_chunk->kdata[idx+1] >> 4) & 0x3) != 3) { |
| DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
| return -EINVAL; |
| } |
| track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
| track->vap_vf_cntl = ib_chunk->kdata[idx+1]; |
| track->immd_dwords = pkt->count - 1; |
| r = r100_cs_track_check(p->rdev, track); |
| if (r) { |
| 1046,11 → 1168,11 |
| /* Number of dwords is vtx_size * (num_vertices - 1) |
| * PRIM_WALK must be equal to 3 vertex data in embedded |
| * in cmd stream */ |
| if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { |
| if (((ib_chunk->kdata[idx] >> 4) & 0x3) != 3) { |
| DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
| return -EINVAL; |
| } |
| track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
| track->vap_vf_cntl = ib_chunk->kdata[idx]; |
| track->immd_dwords = pkt->count; |
| r = r100_cs_track_check(p->rdev, track); |
| if (r) { |
| 1058,7 → 1180,7 |
| } |
| break; |
| case PACKET3_3D_DRAW_VBUF: |
| track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
| track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; |
| r = r100_cs_track_check(p->rdev, track); |
| if (r) { |
| return r; |
| 1065,7 → 1187,7 |
| } |
| break; |
| case PACKET3_3D_DRAW_VBUF_2: |
| track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
| track->vap_vf_cntl = ib_chunk->kdata[idx]; |
| r = r100_cs_track_check(p->rdev, track); |
| if (r) { |
| return r; |
| 1072,7 → 1194,7 |
| } |
| break; |
| case PACKET3_3D_DRAW_INDX: |
| track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
| track->vap_vf_cntl = ib_chunk->kdata[idx + 1]; |
| r = r100_cs_track_check(p->rdev, track); |
| if (r) { |
| return r; |
| 1079,7 → 1201,7 |
| } |
| break; |
| case PACKET3_3D_DRAW_INDX_2: |
| track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
| track->vap_vf_cntl = ib_chunk->kdata[idx]; |
| r = r100_cs_track_check(p->rdev, track); |
| if (r) { |
| return r; |
| 1140,6 → 1262,12 |
| rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm); |
| } |
| int r300_init(struct radeon_device *rdev) |
| { |
| r300_set_reg_safe(rdev); |
| return 0; |
| } |
| void r300_mc_program(struct radeon_device *rdev) |
| { |
| struct r100_mc_save save; |
| 1173,149 → 1301,3 |
| S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
| r100_mc_resume(rdev, &save); |
| } |
| void r300_clock_startup(struct radeon_device *rdev) |
| { |
| u32 tmp; |
| if (radeon_dynclks != -1 && radeon_dynclks) |
| radeon_legacy_set_clock_gating(rdev, 1); |
| /* We need to force on some of the block */ |
| tmp = RREG32_PLL(R_00000D_SCLK_CNTL); |
| tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); |
| if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380)) |
| tmp |= S_00000D_FORCE_VAP(1); |
| WREG32_PLL(R_00000D_SCLK_CNTL, tmp); |
| } |
| static int r300_startup(struct radeon_device *rdev) |
| { |
| int r; |
| r300_mc_program(rdev); |
| /* Resume clock */ |
| r300_clock_startup(rdev); |
| /* Initialize GPU configuration (# pipes, ...) */ |
| r300_gpu_init(rdev); |
| /* Initialize GART (initialize after TTM so we can allocate |
| * memory through TTM but finalize after TTM) */ |
| if (rdev->flags & RADEON_IS_PCIE) { |
| r = rv370_pcie_gart_enable(rdev); |
| if (r) |
| return r; |
| } |
| if (rdev->flags & RADEON_IS_PCI) { |
| r = r100_pci_gart_enable(rdev); |
| if (r) |
| return r; |
| } |
| /* Enable IRQ */ |
| // rdev->irq.sw_int = true; |
| // r100_irq_set(rdev); |
| /* 1M ring buffer */ |
| // r = r100_cp_init(rdev, 1024 * 1024); |
| // if (r) { |
| // dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
| // return r; |
| // } |
| // r = r100_wb_init(rdev); |
| // if (r) |
| // dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
| // r = r100_ib_init(rdev); |
| // if (r) { |
| // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
| // return r; |
| // } |
| return 0; |
| } |
| int r300_init(struct radeon_device *rdev) |
| { |
| int r; |
| /* Disable VGA */ |
| r100_vga_render_disable(rdev); |
| /* Initialize scratch registers */ |
| radeon_scratch_init(rdev); |
| /* Initialize surface registers */ |
| radeon_surface_init(rdev); |
| /* TODO: disable VGA need to use VGA request */ |
| /* BIOS*/ |
| if (!radeon_get_bios(rdev)) { |
| if (ASIC_IS_AVIVO(rdev)) |
| return -EINVAL; |
| } |
| if (rdev->is_atom_bios) { |
| dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); |
| return -EINVAL; |
| } else { |
| r = radeon_combios_init(rdev); |
| if (r) |
| return r; |
| } |
| /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
| if (radeon_gpu_reset(rdev)) { |
| dev_warn(rdev->dev, |
| "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
| RREG32(R_000E40_RBBM_STATUS), |
| RREG32(R_0007C0_CP_STAT)); |
| } |
| /* check if cards are posted or not */ |
| if (!radeon_card_posted(rdev) && rdev->bios) { |
| DRM_INFO("GPU not posted. posting now...\n"); |
| radeon_combios_asic_init(rdev->ddev); |
| } |
| /* Set asic errata */ |
| r300_errata(rdev); |
| /* Initialize clocks */ |
| radeon_get_clock_info(rdev->ddev); |
| /* Get vram informations */ |
| r300_vram_info(rdev); |
| /* Initialize memory controller (also test AGP) */ |
| r = r420_mc_init(rdev); |
| if (r) |
| return r; |
| /* Fence driver */ |
| // r = radeon_fence_driver_init(rdev); |
| // if (r) |
| // return r; |
| // r = radeon_irq_kms_init(rdev); |
| // if (r) |
| // return r; |
| /* Memory manager */ |
| r = radeon_object_init(rdev); |
| if (r) |
| return r; |
| if (rdev->flags & RADEON_IS_PCIE) { |
| r = rv370_pcie_gart_init(rdev); |
| if (r) |
| return r; |
| } |
| if (rdev->flags & RADEON_IS_PCI) { |
| r = r100_pci_gart_init(rdev); |
| if (r) |
| return r; |
| } |
| r300_set_reg_safe(rdev); |
| rdev->accel_working = true; |
| r = r300_startup(rdev); |
| if (r) { |
| /* Somethings want wront with the accel init stop accel */ |
| dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
| // r300_suspend(rdev); |
| // r100_cp_fini(rdev); |
| // r100_wb_fini(rdev); |
| // r100_ib_fini(rdev); |
| if (rdev->flags & RADEON_IS_PCIE) |
| rv370_pcie_gart_fini(rdev); |
| if (rdev->flags & RADEON_IS_PCI) |
| r100_pci_gart_fini(rdev); |
| // radeon_irq_kms_fini(rdev); |
| rdev->accel_working = false; |
| } |
| return 0; |
| } |
| /drivers/video/drm/radeon/r300d.h |
|---|
| 96,211 → 96,6 |
| #define S_000170_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) |
| #define G_000170_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) |
| #define C_000170_AGP_BASE_ADDR 0x00000000 |
| #define R_0007C0_CP_STAT 0x0007C0 |
| #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) |
| #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) |
| #define C_0007C0_MRU_BUSY 0xFFFFFFFE |
| #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) |
| #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) |
| #define C_0007C0_MWU_BUSY 0xFFFFFFFD |
| #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) |
| #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) |
| #define C_0007C0_RSIU_BUSY 0xFFFFFFFB |
| #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) |
| #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) |
| #define C_0007C0_RCIU_BUSY 0xFFFFFFF7 |
| #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) |
| #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) |
| #define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF |
| #define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10) |
| #define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1) |
| #define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF |
| #define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11) |
| #define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1) |
| #define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF |
| #define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12) |
| #define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1) |
| #define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF |
| #define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13) |
| #define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1) |
| #define C_0007C0_CSI_BUSY 0xFFFFDFFF |
| #define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14) |
| #define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1) |
| #define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF |
| #define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15) |
| #define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1) |
| #define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF |
| #define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28) |
| #define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1) |
| #define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF |
| #define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29) |
| #define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1) |
| #define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF |
| #define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30) |
| #define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1) |
| #define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF |
| #define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31) |
| #define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1) |
| #define C_0007C0_CP_BUSY 0x7FFFFFFF |
| #define R_000E40_RBBM_STATUS 0x000E40 |
| #define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) |
| #define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) |
| #define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 |
| #define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) |
| #define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) |
| #define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF |
| #define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) |
| #define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) |
| #define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF |
| #define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) |
| #define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) |
| #define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF |
| #define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) |
| #define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) |
| #define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF |
| #define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) |
| #define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) |
| #define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF |
| #define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) |
| #define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) |
| #define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF |
| #define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) |
| #define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) |
| #define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF |
| #define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) |
| #define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) |
| #define C_000E40_ENG_EV_BUSY 0xFFFF7FFF |
| #define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) |
| #define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) |
| #define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF |
| #define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) |
| #define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) |
| #define C_000E40_E2_BUSY 0xFFFDFFFF |
| #define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) |
| #define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) |
| #define C_000E40_RB2D_BUSY 0xFFFBFFFF |
| #define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) |
| #define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) |
| #define C_000E40_RB3D_BUSY 0xFFF7FFFF |
| #define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20) |
| #define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1) |
| #define C_000E40_VAP_BUSY 0xFFEFFFFF |
| #define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) |
| #define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) |
| #define C_000E40_RE_BUSY 0xFFDFFFFF |
| #define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) |
| #define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) |
| #define C_000E40_TAM_BUSY 0xFFBFFFFF |
| #define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) |
| #define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) |
| #define C_000E40_TDM_BUSY 0xFF7FFFFF |
| #define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) |
| #define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) |
| #define C_000E40_PB_BUSY 0xFEFFFFFF |
| #define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25) |
| #define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1) |
| #define C_000E40_TIM_BUSY 0xFDFFFFFF |
| #define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26) |
| #define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1) |
| #define C_000E40_GA_BUSY 0xFBFFFFFF |
| #define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27) |
| #define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1) |
| #define C_000E40_CBA2D_BUSY 0xF7FFFFFF |
| #define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) |
| #define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) |
| #define C_000E40_GUI_ACTIVE 0x7FFFFFFF |
| #define R_00000D_SCLK_CNTL 0x00000D |
| #define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0) |
| #define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7) |
| #define C_00000D_SCLK_SRC_SEL 0xFFFFFFF8 |
| #define S_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 3) |
| #define G_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) >> 3) & 0x1) |
| #define C_00000D_CP_MAX_DYN_STOP_LAT 0xFFFFFFF7 |
| #define S_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 4) |
| #define G_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) >> 4) & 0x1) |
| #define C_00000D_HDP_MAX_DYN_STOP_LAT 0xFFFFFFEF |
| #define S_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 5) |
| #define G_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) >> 5) & 0x1) |
| #define C_00000D_TV_MAX_DYN_STOP_LAT 0xFFFFFFDF |
| #define S_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 6) |
| #define G_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) >> 6) & 0x1) |
| #define C_00000D_E2_MAX_DYN_STOP_LAT 0xFFFFFFBF |
| #define S_00000D_SE_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 7) |
| #define G_00000D_SE_MAX_DYN_STOP_LAT(x) (((x) >> 7) & 0x1) |
| #define C_00000D_SE_MAX_DYN_STOP_LAT 0xFFFFFF7F |
| #define S_00000D_IDCT_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 8) |
| #define G_00000D_IDCT_MAX_DYN_STOP_LAT(x) (((x) >> 8) & 0x1) |
| #define C_00000D_IDCT_MAX_DYN_STOP_LAT 0xFFFFFEFF |
| #define S_00000D_VIP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 9) |
| #define G_00000D_VIP_MAX_DYN_STOP_LAT(x) (((x) >> 9) & 0x1) |
| #define C_00000D_VIP_MAX_DYN_STOP_LAT 0xFFFFFDFF |
| #define S_00000D_RE_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 10) |
| #define G_00000D_RE_MAX_DYN_STOP_LAT(x) (((x) >> 10) & 0x1) |
| #define C_00000D_RE_MAX_DYN_STOP_LAT 0xFFFFFBFF |
| #define S_00000D_PB_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 11) |
| #define G_00000D_PB_MAX_DYN_STOP_LAT(x) (((x) >> 11) & 0x1) |
| #define C_00000D_PB_MAX_DYN_STOP_LAT 0xFFFFF7FF |
| #define S_00000D_TAM_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 12) |
| #define G_00000D_TAM_MAX_DYN_STOP_LAT(x) (((x) >> 12) & 0x1) |
| #define C_00000D_TAM_MAX_DYN_STOP_LAT 0xFFFFEFFF |
| #define S_00000D_TDM_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 13) |
| #define G_00000D_TDM_MAX_DYN_STOP_LAT(x) (((x) >> 13) & 0x1) |
| #define C_00000D_TDM_MAX_DYN_STOP_LAT 0xFFFFDFFF |
| #define S_00000D_RB_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 14) |
| #define G_00000D_RB_MAX_DYN_STOP_LAT(x) (((x) >> 14) & 0x1) |
| #define C_00000D_RB_MAX_DYN_STOP_LAT 0xFFFFBFFF |
| #define S_00000D_FORCE_DISP2(x) (((x) & 0x1) << 15) |
| #define G_00000D_FORCE_DISP2(x) (((x) >> 15) & 0x1) |
| #define C_00000D_FORCE_DISP2 0xFFFF7FFF |
| #define S_00000D_FORCE_CP(x) (((x) & 0x1) << 16) |
| #define G_00000D_FORCE_CP(x) (((x) >> 16) & 0x1) |
| #define C_00000D_FORCE_CP 0xFFFEFFFF |
| #define S_00000D_FORCE_HDP(x) (((x) & 0x1) << 17) |
| #define G_00000D_FORCE_HDP(x) (((x) >> 17) & 0x1) |
| #define C_00000D_FORCE_HDP 0xFFFDFFFF |
| #define S_00000D_FORCE_DISP1(x) (((x) & 0x1) << 18) |
| #define G_00000D_FORCE_DISP1(x) (((x) >> 18) & 0x1) |
| #define C_00000D_FORCE_DISP1 0xFFFBFFFF |
| #define S_00000D_FORCE_TOP(x) (((x) & 0x1) << 19) |
| #define G_00000D_FORCE_TOP(x) (((x) >> 19) & 0x1) |
| #define C_00000D_FORCE_TOP 0xFFF7FFFF |
| #define S_00000D_FORCE_E2(x) (((x) & 0x1) << 20) |
| #define G_00000D_FORCE_E2(x) (((x) >> 20) & 0x1) |
| #define C_00000D_FORCE_E2 0xFFEFFFFF |
| #define S_00000D_FORCE_SE(x) (((x) & 0x1) << 21) |
| #define G_00000D_FORCE_SE(x) (((x) >> 21) & 0x1) |
| #define C_00000D_FORCE_SE 0xFFDFFFFF |
| #define S_00000D_FORCE_IDCT(x) (((x) & 0x1) << 22) |
| #define G_00000D_FORCE_IDCT(x) (((x) >> 22) & 0x1) |
| #define C_00000D_FORCE_IDCT 0xFFBFFFFF |
| #define S_00000D_FORCE_VIP(x) (((x) & 0x1) << 23) |
| #define G_00000D_FORCE_VIP(x) (((x) >> 23) & 0x1) |
| #define C_00000D_FORCE_VIP 0xFF7FFFFF |
| #define S_00000D_FORCE_RE(x) (((x) & 0x1) << 24) |
| #define G_00000D_FORCE_RE(x) (((x) >> 24) & 0x1) |
| #define C_00000D_FORCE_RE 0xFEFFFFFF |
| #define S_00000D_FORCE_PB(x) (((x) & 0x1) << 25) |
| #define G_00000D_FORCE_PB(x) (((x) >> 25) & 0x1) |
| #define C_00000D_FORCE_PB 0xFDFFFFFF |
| #define S_00000D_FORCE_TAM(x) (((x) & 0x1) << 26) |
| #define G_00000D_FORCE_TAM(x) (((x) >> 26) & 0x1) |
| #define C_00000D_FORCE_TAM 0xFBFFFFFF |
| #define S_00000D_FORCE_TDM(x) (((x) & 0x1) << 27) |
| #define G_00000D_FORCE_TDM(x) (((x) >> 27) & 0x1) |
| #define C_00000D_FORCE_TDM 0xF7FFFFFF |
| #define S_00000D_FORCE_RB(x) (((x) & 0x1) << 28) |
| #define G_00000D_FORCE_RB(x) (((x) >> 28) & 0x1) |
| #define C_00000D_FORCE_RB 0xEFFFFFFF |
| #define S_00000D_FORCE_TV_SCLK(x) (((x) & 0x1) << 29) |
| #define G_00000D_FORCE_TV_SCLK(x) (((x) >> 29) & 0x1) |
| #define C_00000D_FORCE_TV_SCLK 0xDFFFFFFF |
| #define S_00000D_FORCE_SUBPIC(x) (((x) & 0x1) << 30) |
| #define G_00000D_FORCE_SUBPIC(x) (((x) >> 30) & 0x1) |
| #define C_00000D_FORCE_SUBPIC 0xBFFFFFFF |
| #define S_00000D_FORCE_OV0(x) (((x) & 0x1) << 31) |
| #define G_00000D_FORCE_OV0(x) (((x) >> 31) & 0x1) |
| #define C_00000D_FORCE_OV0 0x7FFFFFFF |
| #endif |
| /drivers/video/drm/radeon/r420.c |
|---|
| 39,16 → 39,6 |
| /* Setup GPU memory space */ |
| rdev->mc.vram_location = 0xFFFFFFFFUL; |
| rdev->mc.gtt_location = 0xFFFFFFFFUL; |
| if (rdev->flags & RADEON_IS_AGP) { |
| r = radeon_agp_init(rdev); |
| if (r) { |
| printk(KERN_WARNING "[drm] Disabling AGP\n"); |
| rdev->flags &= ~RADEON_IS_AGP; |
| rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
| } else { |
| rdev->mc.gtt_location = rdev->mc.agp_base; |
| } |
| } |
| r = radeon_mc_setup(rdev); |
| if (r) { |
| return r; |
| 155,9 → 145,6 |
| static void r420_clock_resume(struct radeon_device *rdev) |
| { |
| u32 sclk_cntl; |
| if (radeon_dynclks != -1 && radeon_dynclks) |
| radeon_atom_set_clock_gating(rdev, 1); |
| sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); |
| sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); |
| if (rdev->family == CHIP_R420) |
| 170,8 → 157,6 |
| int r; |
| r300_mc_program(rdev); |
| /* Resume clock */ |
| r420_clock_resume(rdev); |
| /* Initialize GART (initialize after TTM so we can allocate |
| * memory through TTM but finalize after TTM) */ |
| if (rdev->flags & RADEON_IS_PCIE) { |
| 189,11 → 174,11 |
| // rdev->irq.sw_int = true; |
| // r100_irq_set(rdev); |
| /* 1M ring buffer */ |
| // r = r100_cp_init(rdev, 1024 * 1024); |
| // if (r) { |
| // dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
| // return r; |
| // } |
| r = r100_cp_init(rdev, 1024 * 1024); |
| if (r) { |
| dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
| return r; |
| } |
| // r = r100_wb_init(rdev); |
| // if (r) { |
| // dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
| 233,12 → 218,46 |
| return r420_startup(rdev); |
| } |
| int r420_suspend(struct radeon_device *rdev) |
| { |
| r100_cp_disable(rdev); |
| // r100_wb_disable(rdev); |
| // r100_irq_disable(rdev); |
| if (rdev->flags & RADEON_IS_PCIE) |
| rv370_pcie_gart_disable(rdev); |
| if (rdev->flags & RADEON_IS_PCI) |
| r100_pci_gart_disable(rdev); |
| return 0; |
| } |
| void r420_fini(struct radeon_device *rdev) |
| { |
| r100_cp_fini(rdev); |
| // r100_wb_fini(rdev); |
| // r100_ib_fini(rdev); |
| radeon_gem_fini(rdev); |
| if (rdev->flags & RADEON_IS_PCIE) |
| rv370_pcie_gart_fini(rdev); |
| if (rdev->flags & RADEON_IS_PCI) |
| r100_pci_gart_fini(rdev); |
| // radeon_agp_fini(rdev); |
| // radeon_irq_kms_fini(rdev); |
| // radeon_fence_driver_fini(rdev); |
| // radeon_object_fini(rdev); |
| if (rdev->is_atom_bios) { |
| radeon_atombios_fini(rdev); |
| } else { |
| radeon_combios_fini(rdev); |
| } |
| kfree(rdev->bios); |
| rdev->bios = NULL; |
| } |
| int r420_init(struct radeon_device *rdev) |
| { |
| int r; |
| rdev->new_init_path = true; |
| /* Initialize scratch registers */ |
| radeon_scratch_init(rdev); |
| /* Initialize surface registers */ |
| 316,7 → 335,7 |
| if (r) { |
| /* Somethings want wront with the accel init stop accel */ |
| dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
| // r420_suspend(rdev); |
| r420_suspend(rdev); |
| // r100_cp_fini(rdev); |
| // r100_wb_fini(rdev); |
| // r100_ib_fini(rdev); |
| /drivers/video/drm/radeon/r420d.h |
|---|
| 212,9 → 212,9 |
| #define S_00000D_FORCE_E2(x) (((x) & 0x1) << 20) |
| #define G_00000D_FORCE_E2(x) (((x) >> 20) & 0x1) |
| #define C_00000D_FORCE_E2 0xFFEFFFFF |
| #define S_00000D_FORCE_VAP(x) (((x) & 0x1) << 21) |
| #define G_00000D_FORCE_VAP(x) (((x) >> 21) & 0x1) |
| #define C_00000D_FORCE_VAP 0xFFDFFFFF |
| #define S_00000D_FORCE_SE(x) (((x) & 0x1) << 21) |
| #define G_00000D_FORCE_SE(x) (((x) >> 21) & 0x1) |
| #define C_00000D_FORCE_SE 0xFFDFFFFF |
| #define S_00000D_FORCE_IDCT(x) (((x) & 0x1) << 22) |
| #define G_00000D_FORCE_IDCT(x) (((x) >> 22) & 0x1) |
| #define C_00000D_FORCE_IDCT 0xFFBFFFFF |
| 224,9 → 224,9 |
| #define S_00000D_FORCE_RE(x) (((x) & 0x1) << 24) |
| #define G_00000D_FORCE_RE(x) (((x) >> 24) & 0x1) |
| #define C_00000D_FORCE_RE 0xFEFFFFFF |
| #define S_00000D_FORCE_SR(x) (((x) & 0x1) << 25) |
| #define G_00000D_FORCE_SR(x) (((x) >> 25) & 0x1) |
| #define C_00000D_FORCE_SR 0xFDFFFFFF |
| #define S_00000D_FORCE_PB(x) (((x) & 0x1) << 25) |
| #define G_00000D_FORCE_PB(x) (((x) >> 25) & 0x1) |
| #define C_00000D_FORCE_PB 0xFDFFFFFF |
| #define S_00000D_FORCE_PX(x) (((x) & 0x1) << 26) |
| #define G_00000D_FORCE_PX(x) (((x) >> 26) & 0x1) |
| #define C_00000D_FORCE_PX 0xFBFFFFFF |
| 233,15 → 233,15 |
| #define S_00000D_FORCE_TX(x) (((x) & 0x1) << 27) |
| #define G_00000D_FORCE_TX(x) (((x) >> 27) & 0x1) |
| #define C_00000D_FORCE_TX 0xF7FFFFFF |
| #define S_00000D_FORCE_US(x) (((x) & 0x1) << 28) |
| #define G_00000D_FORCE_US(x) (((x) >> 28) & 0x1) |
| #define C_00000D_FORCE_US 0xEFFFFFFF |
| #define S_00000D_FORCE_RB(x) (((x) & 0x1) << 28) |
| #define G_00000D_FORCE_RB(x) (((x) >> 28) & 0x1) |
| #define C_00000D_FORCE_RB 0xEFFFFFFF |
| #define S_00000D_FORCE_TV_SCLK(x) (((x) & 0x1) << 29) |
| #define G_00000D_FORCE_TV_SCLK(x) (((x) >> 29) & 0x1) |
| #define C_00000D_FORCE_TV_SCLK 0xDFFFFFFF |
| #define S_00000D_FORCE_SU(x) (((x) & 0x1) << 30) |
| #define G_00000D_FORCE_SU(x) (((x) >> 30) & 0x1) |
| #define C_00000D_FORCE_SU 0xBFFFFFFF |
| #define S_00000D_FORCE_SUBPIC(x) (((x) & 0x1) << 30) |
| #define G_00000D_FORCE_SUBPIC(x) (((x) >> 30) & 0x1) |
| #define C_00000D_FORCE_SUBPIC 0xBFFFFFFF |
| #define S_00000D_FORCE_OV0(x) (((x) & 0x1) << 31) |
| #define G_00000D_FORCE_OV0(x) (((x) >> 31) & 0x1) |
| #define C_00000D_FORCE_OV0 0x7FFFFFFF |
| /drivers/video/drm/radeon/r500_reg.h |
|---|
| 445,8 → 445,6 |
| #define AVIVO_D1MODE_VBLANK_STATUS 0x6534 |
| # define AVIVO_VBLANK_ACK (1 << 4) |
| #define AVIVO_D1MODE_VLINE_START_END 0x6538 |
| #define AVIVO_D1MODE_VLINE_STATUS 0x653c |
| # define AVIVO_D1MODE_VLINE_STAT (1 << 12) |
| #define AVIVO_DxMODE_INT_MASK 0x6540 |
| # define AVIVO_D1MODE_INT_MASK (1 << 0) |
| # define AVIVO_D2MODE_INT_MASK (1 << 8) |
| 504,7 → 502,6 |
| #define AVIVO_D2MODE_VBLANK_STATUS 0x6d34 |
| #define AVIVO_D2MODE_VLINE_START_END 0x6d38 |
| #define AVIVO_D2MODE_VLINE_STATUS 0x6d3c |
| #define AVIVO_D2MODE_VIEWPORT_START 0x6d80 |
| #define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84 |
| #define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88 |
| /drivers/video/drm/radeon/r520.c |
|---|
| 26,14 → 26,104 |
| * Jerome Glisse |
| */ |
| #include "drmP.h" |
| #include "radeon_reg.h" |
| #include "radeon.h" |
| #include "atom.h" |
| #include "r520d.h" |
| /* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */ |
| /* r520,rv530,rv560,rv570,r580 depends on : */ |
| void r100_hdp_reset(struct radeon_device *rdev); |
| void r420_pipes_init(struct radeon_device *rdev); |
| void rs600_mc_disable_clients(struct radeon_device *rdev); |
| void rs600_disable_vga(struct radeon_device *rdev); |
| int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); |
| int rv515_debugfs_ga_info_init(struct radeon_device *rdev); |
| static int r520_mc_wait_for_idle(struct radeon_device *rdev) |
| /* This files gather functions specifics to: |
| * r520,rv530,rv560,rv570,r580 |
| * |
| * Some of these functions might be used by newer ASICs. |
| */ |
| void r520_gpu_init(struct radeon_device *rdev); |
| int r520_mc_wait_for_idle(struct radeon_device *rdev); |
| /* |
| * MC |
| */ |
| int r520_mc_init(struct radeon_device *rdev) |
| { |
| uint32_t tmp; |
| int r; |
| ENTER(); |
| if (r100_debugfs_rbbm_init(rdev)) { |
| DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
| } |
| if (rv515_debugfs_pipes_info_init(rdev)) { |
| DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
| } |
| if (rv515_debugfs_ga_info_init(rdev)) { |
| DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
| } |
| r520_gpu_init(rdev); |
| rv370_pcie_gart_disable(rdev); |
| /* Setup GPU memory space */ |
| rdev->mc.vram_location = 0xFFFFFFFFUL; |
| rdev->mc.gtt_location = 0xFFFFFFFFUL; |
| r = radeon_mc_setup(rdev); |
| if (r) { |
| return r; |
| } |
| /* Program GPU memory space */ |
| rs600_mc_disable_clients(rdev); |
| if (r520_mc_wait_for_idle(rdev)) { |
| printk(KERN_WARNING "Failed to wait MC idle while " |
| "programming pipes. Bad things might happen.\n"); |
| } |
| /* Write VRAM size in case we are limiting it */ |
| WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
| tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
| tmp = REG_SET(R520_MC_FB_TOP, tmp >> 16); |
| tmp |= REG_SET(R520_MC_FB_START, rdev->mc.vram_location >> 16); |
| WREG32_MC(R520_MC_FB_LOCATION, tmp); |
| WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16); |
| WREG32(0x310, rdev->mc.vram_location); |
| if (rdev->flags & RADEON_IS_AGP) { |
| tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
| tmp = REG_SET(R520_MC_AGP_TOP, tmp >> 16); |
| tmp |= REG_SET(R520_MC_AGP_START, rdev->mc.gtt_location >> 16); |
| WREG32_MC(R520_MC_AGP_LOCATION, tmp); |
| WREG32_MC(R520_MC_AGP_BASE, rdev->mc.agp_base); |
| WREG32_MC(R520_MC_AGP_BASE_2, 0); |
| } else { |
| WREG32_MC(R520_MC_AGP_LOCATION, 0x0FFFFFFF); |
| WREG32_MC(R520_MC_AGP_BASE, 0); |
| WREG32_MC(R520_MC_AGP_BASE_2, 0); |
| } |
| LEAVE(); |
| return 0; |
| } |
| void r520_mc_fini(struct radeon_device *rdev) |
| { |
| } |
| /* |
| * Global GPU functions |
| */ |
| void r520_errata(struct radeon_device *rdev) |
| { |
| rdev->pll_errata = 0; |
| } |
| int r520_mc_wait_for_idle(struct radeon_device *rdev) |
| { |
| unsigned i; |
| uint32_t tmp; |
| 48,13 → 138,13 |
| return -1; |
| } |
| static void r520_gpu_init(struct radeon_device *rdev) |
| void r520_gpu_init(struct radeon_device *rdev) |
| { |
| unsigned pipe_select_current, gb_pipe_select, tmp; |
| ENTER(); |
| r100_hdp_reset(rdev); |
| rv515_vga_render_disable(rdev); |
| rs600_disable_vga(rdev); |
| /* |
| * DST_PIPE_CONFIG 0x170C |
| * GB_TILE_CONFIG 0x4018 |
| 92,6 → 182,10 |
| } |
| } |
| /* |
| * VRAM info |
| */ |
| static void r520_vram_get_type(struct radeon_device *rdev) |
| { |
| uint32_t tmp; |
| 136,154 → 230,7 |
| rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); |
| } |
| void r520_mc_program(struct radeon_device *rdev) |
| void r520_bandwidth_update(struct radeon_device *rdev) |
| { |
| struct rv515_mc_save save; |
| /* Stops all mc clients */ |
| rv515_mc_stop(rdev, &save); |
| /* Wait for mc idle */ |
| if (r520_mc_wait_for_idle(rdev)) |
| dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
| /* Write VRAM size in case we are limiting it */ |
| WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
| /* Program MC, should be a 32bits limited address space */ |
| WREG32_MC(R_000004_MC_FB_LOCATION, |
| S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | |
| S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
| WREG32(R_000134_HDP_FB_LOCATION, |
| S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); |
| if (rdev->flags & RADEON_IS_AGP) { |
| WREG32_MC(R_000005_MC_AGP_LOCATION, |
| S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) | |
| S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); |
| WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); |
| WREG32_MC(R_000007_AGP_BASE_2, |
| S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); |
| } else { |
| WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF); |
| WREG32_MC(R_000006_AGP_BASE, 0); |
| WREG32_MC(R_000007_AGP_BASE_2, 0); |
| rv515_bandwidth_avivo_update(rdev); |
| } |
| rv515_mc_resume(rdev, &save); |
| } |
| static int r520_startup(struct radeon_device *rdev) |
| { |
| int r; |
| r520_mc_program(rdev); |
| /* Resume clock */ |
| rv515_clock_startup(rdev); |
| /* Initialize GPU configuration (# pipes, ...) */ |
| r520_gpu_init(rdev); |
| /* Initialize GART (initialize after TTM so we can allocate |
| * memory through TTM but finalize after TTM) */ |
| if (rdev->flags & RADEON_IS_PCIE) { |
| r = rv370_pcie_gart_enable(rdev); |
| if (r) |
| return r; |
| } |
| /* Enable IRQ */ |
| // rdev->irq.sw_int = true; |
| // rs600_irq_set(rdev); |
| /* 1M ring buffer */ |
| // r = r100_cp_init(rdev, 1024 * 1024); |
| // if (r) { |
| // dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
| // return r; |
| // } |
| // r = r100_wb_init(rdev); |
| // if (r) |
| // dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
| // r = r100_ib_init(rdev); |
| // if (r) { |
| // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
| // return r; |
| // } |
| return 0; |
| } |
| int r520_init(struct radeon_device *rdev) |
| { |
| int r; |
| ENTER(); |
| /* Initialize scratch registers */ |
| radeon_scratch_init(rdev); |
| /* Initialize surface registers */ |
| radeon_surface_init(rdev); |
| /* TODO: disable VGA need to use VGA request */ |
| /* BIOS*/ |
| if (!radeon_get_bios(rdev)) { |
| if (ASIC_IS_AVIVO(rdev)) |
| return -EINVAL; |
| } |
| if (rdev->is_atom_bios) { |
| r = radeon_atombios_init(rdev); |
| if (r) |
| return r; |
| } else { |
| dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); |
| return -EINVAL; |
| } |
| /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
| if (radeon_gpu_reset(rdev)) { |
| dev_warn(rdev->dev, |
| "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
| RREG32(R_000E40_RBBM_STATUS), |
| RREG32(R_0007C0_CP_STAT)); |
| } |
| /* check if cards are posted or not */ |
| if (!radeon_card_posted(rdev) && rdev->bios) { |
| DRM_INFO("GPU not posted. posting now...\n"); |
| atom_asic_init(rdev->mode_info.atom_context); |
| } |
| /* Initialize clocks */ |
| radeon_get_clock_info(rdev->ddev); |
| /* Get vram informations */ |
| r520_vram_info(rdev); |
| /* Initialize memory controller (also test AGP) */ |
| r = r420_mc_init(rdev); |
| if (r) |
| return r; |
| rv515_debugfs(rdev); |
| /* Fence driver */ |
| // r = radeon_fence_driver_init(rdev); |
| // if (r) |
| // return r; |
| // r = radeon_irq_kms_init(rdev); |
| // if (r) |
| // return r; |
| /* Memory manager */ |
| r = radeon_object_init(rdev); |
| if (r) |
| return r; |
| r = rv370_pcie_gart_init(rdev); |
| if (r) |
| return r; |
| rv515_set_safe_registers(rdev); |
| rdev->accel_working = true; |
| r = r520_startup(rdev); |
| if (r) { |
| /* Somethings want wront with the accel init stop accel */ |
| dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
| // rv515_suspend(rdev); |
| // r100_cp_fini(rdev); |
| // r100_wb_fini(rdev); |
| // r100_ib_fini(rdev); |
| rv370_pcie_gart_fini(rdev); |
| // radeon_agp_fini(rdev); |
| // radeon_irq_kms_fini(rdev); |
| rdev->accel_working = false; |
| } |
| LEAVE(); |
| return 0; |
| } |
| /drivers/video/drm/radeon/r600.c |
|---|
| 25,329 → 25,101 |
| * Alex Deucher |
| * Jerome Glisse |
| */ |
| #include <errno.h> |
| #include <linux/firmware.h> |
| #include "drmP.h" |
| #include "radeon_drm.h" |
| #include "radeon_reg.h" |
| #include "radeon.h" |
| #include "radeon_mode.h" |
| #include "r600d.h" |
| #include "atom.h" |
| #include "avivod.h" |
| #define PFP_UCODE_SIZE 576 |
| #define PM4_UCODE_SIZE 1792 |
| #define R700_PFP_UCODE_SIZE 848 |
| #define R700_PM4_UCODE_SIZE 1360 |
| /* r600,rv610,rv630,rv620,rv635,rv670 depends on : */ |
| void rs600_mc_disable_clients(struct radeon_device *rdev); |
| /* Firmware Names */ |
| MODULE_FIRMWARE("radeon/R600_pfp.bin"); |
| MODULE_FIRMWARE("radeon/R600_me.bin"); |
| MODULE_FIRMWARE("radeon/RV610_pfp.bin"); |
| MODULE_FIRMWARE("radeon/RV610_me.bin"); |
| MODULE_FIRMWARE("radeon/RV630_pfp.bin"); |
| MODULE_FIRMWARE("radeon/RV630_me.bin"); |
| MODULE_FIRMWARE("radeon/RV620_pfp.bin"); |
| MODULE_FIRMWARE("radeon/RV620_me.bin"); |
| MODULE_FIRMWARE("radeon/RV635_pfp.bin"); |
| MODULE_FIRMWARE("radeon/RV635_me.bin"); |
| MODULE_FIRMWARE("radeon/RV670_pfp.bin"); |
| MODULE_FIRMWARE("radeon/RV670_me.bin"); |
| MODULE_FIRMWARE("radeon/RS780_pfp.bin"); |
| MODULE_FIRMWARE("radeon/RS780_me.bin"); |
| MODULE_FIRMWARE("radeon/RV770_pfp.bin"); |
| MODULE_FIRMWARE("radeon/RV770_me.bin"); |
| MODULE_FIRMWARE("radeon/RV730_pfp.bin"); |
| MODULE_FIRMWARE("radeon/RV730_me.bin"); |
| MODULE_FIRMWARE("radeon/RV710_pfp.bin"); |
| MODULE_FIRMWARE("radeon/RV710_me.bin"); |
| int r600_debugfs_mc_info_init(struct radeon_device *rdev); |
| /* r600,rv610,rv630,rv620,rv635,rv670 */ |
| /* This files gather functions specifics to: |
| * r600,rv610,rv630,rv620,rv635,rv670 |
| * |
| * Some of these functions might be used by newer ASICs. |
| */ |
| int r600_mc_wait_for_idle(struct radeon_device *rdev); |
| void r600_gpu_init(struct radeon_device *rdev); |
| void r600_fini(struct radeon_device *rdev); |
| /* |
| * R600 PCIE GART |
| * MC |
| */ |
| int r600_gart_clear_page(struct radeon_device *rdev, int i) |
| int r600_mc_init(struct radeon_device *rdev) |
| { |
| void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; |
| u64 pte; |
| uint32_t tmp; |
| if (i < 0 || i > rdev->gart.num_gpu_pages) |
| return -EINVAL; |
| pte = 0; |
| writeq(pte, ((void __iomem *)ptr) + (i * 8)); |
| return 0; |
| } |
| r600_gpu_init(rdev); |
| void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) |
| { |
| unsigned i; |
| u32 tmp; |
| /* setup the gart before changing location so we can ask to |
| * discard unmapped mc request |
| */ |
| /* FIXME: disable out of gart access */ |
| tmp = rdev->mc.gtt_location / 4096; |
| tmp = REG_SET(R600_LOGICAL_PAGE_NUMBER, tmp); |
| WREG32(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, tmp); |
| tmp = (rdev->mc.gtt_location + rdev->mc.gtt_size) / 4096; |
| tmp = REG_SET(R600_LOGICAL_PAGE_NUMBER, tmp); |
| WREG32(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, tmp); |
| WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); |
| WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); |
| WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); |
| for (i = 0; i < rdev->usec_timeout; i++) { |
| /* read MC_STATUS */ |
| tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); |
| tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; |
| if (tmp == 2) { |
| printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); |
| return; |
| rs600_mc_disable_clients(rdev); |
| if (r600_mc_wait_for_idle(rdev)) { |
| printk(KERN_WARNING "Failed to wait MC idle while " |
| "programming pipes. Bad things might happen.\n"); |
| } |
| if (tmp) { |
| return; |
| } |
| udelay(1); |
| } |
| } |
| int r600_pcie_gart_init(struct radeon_device *rdev) |
| { |
| int r; |
| if (rdev->gart.table.vram.robj) { |
| WARN(1, "R600 PCIE GART already initialized.\n"); |
| tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
| tmp = REG_SET(R600_MC_FB_TOP, tmp >> 24); |
| tmp |= REG_SET(R600_MC_FB_BASE, rdev->mc.vram_location >> 24); |
| WREG32(R600_MC_VM_FB_LOCATION, tmp); |
| tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
| tmp = REG_SET(R600_MC_AGP_TOP, tmp >> 22); |
| WREG32(R600_MC_VM_AGP_TOP, tmp); |
| tmp = REG_SET(R600_MC_AGP_BOT, rdev->mc.gtt_location >> 22); |
| WREG32(R600_MC_VM_AGP_BOT, tmp); |
| return 0; |
| } |
| /* Initialize common gart structure */ |
| r = radeon_gart_init(rdev); |
| if (r) |
| return r; |
| rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; |
| return radeon_gart_table_vram_alloc(rdev); |
| } |
| int r600_pcie_gart_enable(struct radeon_device *rdev) |
| void r600_mc_fini(struct radeon_device *rdev) |
| { |
| u32 tmp; |
| int r, i; |
| if (rdev->gart.table.vram.robj == NULL) { |
| dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
| return -EINVAL; |
| /* FIXME: implement */ |
| } |
| r = radeon_gart_table_vram_pin(rdev); |
| if (r) |
| return r; |
| /* Setup L2 cache */ |
| WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | |
| ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
| EFFECTIVE_L2_QUEUE_SIZE(7)); |
| WREG32(VM_L2_CNTL2, 0); |
| WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); |
| /* Setup TLB control */ |
| tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | |
| SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
| EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | |
| ENABLE_WAIT_L2_QUERY; |
| WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); |
| WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); |
| WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); |
| WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); |
| WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); |
| WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); |
| WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | |
| RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); |
| WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, |
| (u32)(rdev->dummy_page.addr >> 12)); |
| for (i = 1; i < 7; i++) |
| WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
| r600_pcie_gart_tlb_flush(rdev); |
| rdev->gart.ready = true; |
| return 0; |
| } |
| void r600_pcie_gart_disable(struct radeon_device *rdev) |
| /* |
| * Global GPU functions |
| */ |
| void r600_errata(struct radeon_device *rdev) |
| { |
| u32 tmp; |
| int i; |
| /* Disable all tables */ |
| for (i = 0; i < 7; i++) |
| WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
| /* Disable L2 cache */ |
| WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | |
| EFFECTIVE_L2_QUEUE_SIZE(7)); |
| WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); |
| /* Setup L1 TLB control */ |
| tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | |
| ENABLE_WAIT_L2_QUERY; |
| WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); |
| if (rdev->gart.table.vram.robj) { |
| radeon_object_kunmap(rdev->gart.table.vram.robj); |
| radeon_object_unpin(rdev->gart.table.vram.robj); |
| rdev->pll_errata = 0; |
| } |
| } |
| void r600_pcie_gart_fini(struct radeon_device *rdev) |
| { |
| r600_pcie_gart_disable(rdev); |
| radeon_gart_table_vram_free(rdev); |
| radeon_gart_fini(rdev); |
| } |
| void r600_agp_enable(struct radeon_device *rdev) |
| { |
| u32 tmp; |
| int i; |
| /* Setup L2 cache */ |
| WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | |
| ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
| EFFECTIVE_L2_QUEUE_SIZE(7)); |
| WREG32(VM_L2_CNTL2, 0); |
| WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); |
| /* Setup TLB control */ |
| tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | |
| SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
| EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | |
| ENABLE_WAIT_L2_QUERY; |
| WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); |
| WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); |
| WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); |
| WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); |
| for (i = 0; i < 7; i++) |
| WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
| } |
| int r600_mc_wait_for_idle(struct radeon_device *rdev) |
| { |
| unsigned i; |
| u32 tmp; |
| for (i = 0; i < rdev->usec_timeout; i++) { |
| /* read MC_STATUS */ |
| tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; |
| if (!tmp) |
| /* FIXME: implement */ |
| return 0; |
| udelay(1); |
| } |
| return -1; |
| } |
| static void r600_mc_program(struct radeon_device *rdev) |
| void r600_gpu_init(struct radeon_device *rdev) |
| { |
| struct rv515_mc_save save; |
| u32 tmp; |
| int i, j; |
| /* Initialize HDP */ |
| for (i = 0, j = 0; i < 32; i++, j += 0x18) { |
| WREG32((0x2c14 + j), 0x00000000); |
| WREG32((0x2c18 + j), 0x00000000); |
| WREG32((0x2c1c + j), 0x00000000); |
| WREG32((0x2c20 + j), 0x00000000); |
| WREG32((0x2c24 + j), 0x00000000); |
| /* FIXME: implement */ |
| } |
| WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); |
| rv515_mc_stop(rdev, &save); |
| if (r600_mc_wait_for_idle(rdev)) { |
| dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
| } |
| /* Lockout access through VGA aperture (doesn't exist before R600) */ |
| WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); |
| /* Update configuration */ |
| if (rdev->flags & RADEON_IS_AGP) { |
| if (rdev->mc.vram_start < rdev->mc.gtt_start) { |
| /* VRAM before AGP */ |
| WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
| rdev->mc.vram_start >> 12); |
| WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
| rdev->mc.gtt_end >> 12); |
| } else { |
| /* VRAM after AGP */ |
| WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
| rdev->mc.gtt_start >> 12); |
| WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
| rdev->mc.vram_end >> 12); |
| } |
| } else { |
| WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); |
| WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); |
| } |
| WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); |
| tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; |
| tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); |
| WREG32(MC_VM_FB_LOCATION, tmp); |
| WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); |
| WREG32(HDP_NONSURFACE_INFO, (2 << 7)); |
| WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF); |
| if (rdev->flags & RADEON_IS_AGP) { |
| WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); |
| WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); |
| WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); |
| } else { |
| WREG32(MC_VM_AGP_BASE, 0); |
| WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); |
| WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); |
| } |
| if (r600_mc_wait_for_idle(rdev)) { |
| dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
| } |
| rv515_mc_resume(rdev, &save); |
| /* we need to own VRAM, so turn off the VGA renderer here |
| * to stop it overwriting our objects */ |
| rv515_vga_render_disable(rdev); |
| } |
| int r600_mc_init(struct radeon_device *rdev) |
| /* |
| * VRAM info |
| */ |
| void r600_vram_get_type(struct radeon_device *rdev) |
| { |
| fixed20_12 a; |
| u32 tmp; |
| uint32_t tmp; |
| int chansize; |
| int r; |
| /* Get VRAM informations */ |
| rdev->mc.vram_width = 128; |
| rdev->mc.vram_is_ddr = true; |
| tmp = RREG32(RAMCFG); |
| if (tmp & CHANSIZE_OVERRIDE) { |
| tmp = RREG32(R600_RAMCFG); |
| if (tmp & R600_CHANSIZE_OVERRIDE) { |
| chansize = 16; |
| } else if (tmp & CHANSIZE_MASK) { |
| } else if (tmp & R600_CHANSIZE) { |
| chansize = 64; |
| } else { |
| chansize = 32; |
| 363,1026 → 135,36 |
| (rdev->family == CHIP_RV635)) { |
| rdev->mc.vram_width = 2 * chansize; |
| } |
| /* Could aper size report 0 ? */ |
| rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
| rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
| /* Setup GPU memory space */ |
| rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); |
| rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); |
| if (rdev->mc.mc_vram_size > rdev->mc.aper_size) |
| rdev->mc.mc_vram_size = rdev->mc.aper_size; |
| if (rdev->mc.real_vram_size > rdev->mc.aper_size) |
| rdev->mc.real_vram_size = rdev->mc.aper_size; |
| if (rdev->flags & RADEON_IS_AGP) { |
| r = radeon_agp_init(rdev); |
| if (r) |
| return r; |
| /* gtt_size is setup by radeon_agp_init */ |
| rdev->mc.gtt_location = rdev->mc.agp_base; |
| tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size; |
| /* Try to put vram before or after AGP because we |
| * we want SYSTEM_APERTURE to cover both VRAM and |
| * AGP so that GPU can catch out of VRAM/AGP access |
| */ |
| if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) { |
| /* Enought place before */ |
| rdev->mc.vram_location = rdev->mc.gtt_location - |
| rdev->mc.mc_vram_size; |
| } else if (tmp > rdev->mc.mc_vram_size) { |
| /* Enought place after */ |
| rdev->mc.vram_location = rdev->mc.gtt_location + |
| rdev->mc.gtt_size; |
| } else { |
| /* Try to setup VRAM then AGP might not |
| * not work on some card |
| */ |
| rdev->mc.vram_location = 0x00000000UL; |
| rdev->mc.gtt_location = rdev->mc.mc_vram_size; |
| } |
| } else { |
| if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { |
| rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) & |
| 0xFFFF) << 24; |
| rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
| tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size; |
| if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) { |
| /* Enough place after vram */ |
| rdev->mc.gtt_location = tmp; |
| } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) { |
| /* Enough place before vram */ |
| rdev->mc.gtt_location = 0; |
| } else { |
| /* Not enough place after or before shrink |
| * gart size |
| */ |
| if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) { |
| rdev->mc.gtt_location = 0; |
| rdev->mc.gtt_size = rdev->mc.vram_location; |
| } else { |
| rdev->mc.gtt_location = tmp; |
| rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp; |
| } |
| } |
| rdev->mc.gtt_location = rdev->mc.mc_vram_size; |
| } else { |
| rdev->mc.vram_location = 0x00000000UL; |
| rdev->mc.gtt_location = rdev->mc.mc_vram_size; |
| rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
| } |
| } |
| rdev->mc.vram_start = rdev->mc.vram_location; |
| rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
| rdev->mc.gtt_start = rdev->mc.gtt_location; |
| rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
| /* FIXME: we should enforce default clock in case GPU is not in |
| * default setup |
| */ |
| a.full = rfixed_const(100); |
| rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); |
| rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); |
| return 0; |
| } |
| /* We doesn't check that the GPU really needs a reset we simply do the |
| * reset, it's up to the caller to determine if the GPU needs one. We |
| * might add an helper function to check that. |
| */ |
| int r600_gpu_soft_reset(struct radeon_device *rdev) |
| void r600_vram_info(struct radeon_device *rdev) |
| { |
| struct rv515_mc_save save; |
| u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) | |
| S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) | |
| S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) | |
| S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) | |
| S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) | |
| S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) | |
| S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) | |
| S_008010_GUI_ACTIVE(1); |
| u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) | |
| S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) | |
| S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) | |
| S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) | |
| S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) | |
| S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) | |
| S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) | |
| S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1); |
| u32 srbm_reset = 0; |
| u32 tmp; |
| r600_vram_get_type(rdev); |
| rdev->mc.real_vram_size = RREG32(R600_CONFIG_MEMSIZE); |
| rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
| dev_info(rdev->dev, "GPU softreset \n"); |
| dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n", |
| RREG32(R_008010_GRBM_STATUS)); |
| dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", |
| RREG32(R_008014_GRBM_STATUS2)); |
| dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", |
| RREG32(R_000E50_SRBM_STATUS)); |
| rv515_mc_stop(rdev, &save); |
| if (r600_mc_wait_for_idle(rdev)) { |
| dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
| /* Could aper size report 0 ? */ |
| rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
| rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
| } |
| /* Disable CP parsing/prefetching */ |
| WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff)); |
| /* Check if any of the rendering block is busy and reset it */ |
| if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) || |
| (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) { |
| tmp = S_008020_SOFT_RESET_CR(1) | |
| S_008020_SOFT_RESET_DB(1) | |
| S_008020_SOFT_RESET_CB(1) | |
| S_008020_SOFT_RESET_PA(1) | |
| S_008020_SOFT_RESET_SC(1) | |
| S_008020_SOFT_RESET_SMX(1) | |
| S_008020_SOFT_RESET_SPI(1) | |
| S_008020_SOFT_RESET_SX(1) | |
| S_008020_SOFT_RESET_SH(1) | |
| S_008020_SOFT_RESET_TC(1) | |
| S_008020_SOFT_RESET_TA(1) | |
| S_008020_SOFT_RESET_VC(1) | |
| S_008020_SOFT_RESET_VGT(1); |
| dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); |
| WREG32(R_008020_GRBM_SOFT_RESET, tmp); |
| (void)RREG32(R_008020_GRBM_SOFT_RESET); |
| udelay(50); |
| WREG32(R_008020_GRBM_SOFT_RESET, 0); |
| (void)RREG32(R_008020_GRBM_SOFT_RESET); |
| } |
| /* Reset CP (we always reset CP) */ |
| tmp = S_008020_SOFT_RESET_CP(1); |
| dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); |
| WREG32(R_008020_GRBM_SOFT_RESET, tmp); |
| (void)RREG32(R_008020_GRBM_SOFT_RESET); |
| udelay(50); |
| WREG32(R_008020_GRBM_SOFT_RESET, 0); |
| (void)RREG32(R_008020_GRBM_SOFT_RESET); |
| /* Reset others GPU block if necessary */ |
| if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS))) |
| srbm_reset |= S_000E60_SOFT_RESET_RLC(1); |
| if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS))) |
| srbm_reset |= S_000E60_SOFT_RESET_GRBM(1); |
| if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS))) |
| srbm_reset |= S_000E60_SOFT_RESET_IH(1); |
| if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS))) |
| srbm_reset |= S_000E60_SOFT_RESET_VMC(1); |
| if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS))) |
| srbm_reset |= S_000E60_SOFT_RESET_MC(1); |
| if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS))) |
| srbm_reset |= S_000E60_SOFT_RESET_MC(1); |
| if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS))) |
| srbm_reset |= S_000E60_SOFT_RESET_MC(1); |
| if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS))) |
| srbm_reset |= S_000E60_SOFT_RESET_MC(1); |
| if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS))) |
| srbm_reset |= S_000E60_SOFT_RESET_MC(1); |
| if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS))) |
| srbm_reset |= S_000E60_SOFT_RESET_RLC(1); |
| if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS))) |
| srbm_reset |= S_000E60_SOFT_RESET_SEM(1); |
| if (G_000E50_BIF_BUSY(RREG32(R_000E50_SRBM_STATUS))) |
| srbm_reset |= S_000E60_SOFT_RESET_BIF(1); |
| dev_info(rdev->dev, " R_000E60_SRBM_SOFT_RESET=0x%08X\n", srbm_reset); |
| WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset); |
| (void)RREG32(R_000E60_SRBM_SOFT_RESET); |
| udelay(50); |
| WREG32(R_000E60_SRBM_SOFT_RESET, 0); |
| (void)RREG32(R_000E60_SRBM_SOFT_RESET); |
| WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset); |
| (void)RREG32(R_000E60_SRBM_SOFT_RESET); |
| udelay(50); |
| WREG32(R_000E60_SRBM_SOFT_RESET, 0); |
| (void)RREG32(R_000E60_SRBM_SOFT_RESET); |
| /* Wait a little for things to settle down */ |
| udelay(50); |
| dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n", |
| RREG32(R_008010_GRBM_STATUS)); |
| dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", |
| RREG32(R_008014_GRBM_STATUS2)); |
| dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", |
| RREG32(R_000E50_SRBM_STATUS)); |
| /* After reset we need to reinit the asic as GPU often endup in an |
| * incoherent state. |
| */ |
| atom_asic_init(rdev->mode_info.atom_context); |
| rv515_mc_resume(rdev, &save); |
| return 0; |
| } |
| int r600_gpu_reset(struct radeon_device *rdev) |
| { |
| return r600_gpu_soft_reset(rdev); |
| } |
| static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes, |
| u32 num_backends, |
| u32 backend_disable_mask) |
| { |
| u32 backend_map = 0; |
| u32 enabled_backends_mask; |
| u32 enabled_backends_count; |
| u32 cur_pipe; |
| u32 swizzle_pipe[R6XX_MAX_PIPES]; |
| u32 cur_backend; |
| u32 i; |
| if (num_tile_pipes > R6XX_MAX_PIPES) |
| num_tile_pipes = R6XX_MAX_PIPES; |
| if (num_tile_pipes < 1) |
| num_tile_pipes = 1; |
| if (num_backends > R6XX_MAX_BACKENDS) |
| num_backends = R6XX_MAX_BACKENDS; |
| if (num_backends < 1) |
| num_backends = 1; |
| enabled_backends_mask = 0; |
| enabled_backends_count = 0; |
| for (i = 0; i < R6XX_MAX_BACKENDS; ++i) { |
| if (((backend_disable_mask >> i) & 1) == 0) { |
| enabled_backends_mask |= (1 << i); |
| ++enabled_backends_count; |
| } |
| if (enabled_backends_count == num_backends) |
| break; |
| } |
| if (enabled_backends_count == 0) { |
| enabled_backends_mask = 1; |
| enabled_backends_count = 1; |
| } |
| if (enabled_backends_count != num_backends) |
| num_backends = enabled_backends_count; |
| memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES); |
| switch (num_tile_pipes) { |
| case 1: |
| swizzle_pipe[0] = 0; |
| break; |
| case 2: |
| swizzle_pipe[0] = 0; |
| swizzle_pipe[1] = 1; |
| break; |
| case 3: |
| swizzle_pipe[0] = 0; |
| swizzle_pipe[1] = 1; |
| swizzle_pipe[2] = 2; |
| break; |
| case 4: |
| swizzle_pipe[0] = 0; |
| swizzle_pipe[1] = 1; |
| swizzle_pipe[2] = 2; |
| swizzle_pipe[3] = 3; |
| break; |
| case 5: |
| swizzle_pipe[0] = 0; |
| swizzle_pipe[1] = 1; |
| swizzle_pipe[2] = 2; |
| swizzle_pipe[3] = 3; |
| swizzle_pipe[4] = 4; |
| break; |
| case 6: |
| swizzle_pipe[0] = 0; |
| swizzle_pipe[1] = 2; |
| swizzle_pipe[2] = 4; |
| swizzle_pipe[3] = 5; |
| swizzle_pipe[4] = 1; |
| swizzle_pipe[5] = 3; |
| break; |
| case 7: |
| swizzle_pipe[0] = 0; |
| swizzle_pipe[1] = 2; |
| swizzle_pipe[2] = 4; |
| swizzle_pipe[3] = 6; |
| swizzle_pipe[4] = 1; |
| swizzle_pipe[5] = 3; |
| swizzle_pipe[6] = 5; |
| break; |
| case 8: |
| swizzle_pipe[0] = 0; |
| swizzle_pipe[1] = 2; |
| swizzle_pipe[2] = 4; |
| swizzle_pipe[3] = 6; |
| swizzle_pipe[4] = 1; |
| swizzle_pipe[5] = 3; |
| swizzle_pipe[6] = 5; |
| swizzle_pipe[7] = 7; |
| break; |
| } |
| cur_backend = 0; |
| for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { |
| while (((1 << cur_backend) & enabled_backends_mask) == 0) |
| cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; |
| backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); |
| cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; |
| } |
| return backend_map; |
| } |
| int r600_count_pipe_bits(uint32_t val) |
| { |
| int i, ret = 0; |
| for (i = 0; i < 32; i++) { |
| ret += val & 1; |
| val >>= 1; |
| } |
| return ret; |
| } |
| void r600_gpu_init(struct radeon_device *rdev) |
| { |
| u32 tiling_config; |
| u32 ramcfg; |
| u32 tmp; |
| int i, j; |
| u32 sq_config; |
| u32 sq_gpr_resource_mgmt_1 = 0; |
| u32 sq_gpr_resource_mgmt_2 = 0; |
| u32 sq_thread_resource_mgmt = 0; |
| u32 sq_stack_resource_mgmt_1 = 0; |
| u32 sq_stack_resource_mgmt_2 = 0; |
| /* FIXME: implement */ |
| switch (rdev->family) { |
| case CHIP_R600: |
| rdev->config.r600.max_pipes = 4; |
| rdev->config.r600.max_tile_pipes = 8; |
| rdev->config.r600.max_simds = 4; |
| rdev->config.r600.max_backends = 4; |
| rdev->config.r600.max_gprs = 256; |
| rdev->config.r600.max_threads = 192; |
| rdev->config.r600.max_stack_entries = 256; |
| rdev->config.r600.max_hw_contexts = 8; |
| rdev->config.r600.max_gs_threads = 16; |
| rdev->config.r600.sx_max_export_size = 128; |
| rdev->config.r600.sx_max_export_pos_size = 16; |
| rdev->config.r600.sx_max_export_smx_size = 128; |
| rdev->config.r600.sq_num_cf_insts = 2; |
| break; |
| case CHIP_RV630: |
| case CHIP_RV635: |
| rdev->config.r600.max_pipes = 2; |
| rdev->config.r600.max_tile_pipes = 2; |
| rdev->config.r600.max_simds = 3; |
| rdev->config.r600.max_backends = 1; |
| rdev->config.r600.max_gprs = 128; |
| rdev->config.r600.max_threads = 192; |
| rdev->config.r600.max_stack_entries = 128; |
| rdev->config.r600.max_hw_contexts = 8; |
| rdev->config.r600.max_gs_threads = 4; |
| rdev->config.r600.sx_max_export_size = 128; |
| rdev->config.r600.sx_max_export_pos_size = 16; |
| rdev->config.r600.sx_max_export_smx_size = 128; |
| rdev->config.r600.sq_num_cf_insts = 2; |
| break; |
| case CHIP_RV610: |
| case CHIP_RV620: |
| case CHIP_RS780: |
| case CHIP_RS880: |
| rdev->config.r600.max_pipes = 1; |
| rdev->config.r600.max_tile_pipes = 1; |
| rdev->config.r600.max_simds = 2; |
| rdev->config.r600.max_backends = 1; |
| rdev->config.r600.max_gprs = 128; |
| rdev->config.r600.max_threads = 192; |
| rdev->config.r600.max_stack_entries = 128; |
| rdev->config.r600.max_hw_contexts = 4; |
| rdev->config.r600.max_gs_threads = 4; |
| rdev->config.r600.sx_max_export_size = 128; |
| rdev->config.r600.sx_max_export_pos_size = 16; |
| rdev->config.r600.sx_max_export_smx_size = 128; |
| rdev->config.r600.sq_num_cf_insts = 1; |
| break; |
| case CHIP_RV670: |
| rdev->config.r600.max_pipes = 4; |
| rdev->config.r600.max_tile_pipes = 4; |
| rdev->config.r600.max_simds = 4; |
| rdev->config.r600.max_backends = 4; |
| rdev->config.r600.max_gprs = 192; |
| rdev->config.r600.max_threads = 192; |
| rdev->config.r600.max_stack_entries = 256; |
| rdev->config.r600.max_hw_contexts = 8; |
| rdev->config.r600.max_gs_threads = 16; |
| rdev->config.r600.sx_max_export_size = 128; |
| rdev->config.r600.sx_max_export_pos_size = 16; |
| rdev->config.r600.sx_max_export_smx_size = 128; |
| rdev->config.r600.sq_num_cf_insts = 2; |
| break; |
| default: |
| break; |
| } |
| /* Initialize HDP */ |
| for (i = 0, j = 0; i < 32; i++, j += 0x18) { |
| WREG32((0x2c14 + j), 0x00000000); |
| WREG32((0x2c18 + j), 0x00000000); |
| WREG32((0x2c1c + j), 0x00000000); |
| WREG32((0x2c20 + j), 0x00000000); |
| WREG32((0x2c24 + j), 0x00000000); |
| } |
| WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); |
| /* Setup tiling */ |
| tiling_config = 0; |
| ramcfg = RREG32(RAMCFG); |
| switch (rdev->config.r600.max_tile_pipes) { |
| case 1: |
| tiling_config |= PIPE_TILING(0); |
| break; |
| case 2: |
| tiling_config |= PIPE_TILING(1); |
| break; |
| case 4: |
| tiling_config |= PIPE_TILING(2); |
| break; |
| case 8: |
| tiling_config |= PIPE_TILING(3); |
| break; |
| default: |
| break; |
| } |
| tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); |
| tiling_config |= GROUP_SIZE(0); |
| tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; |
| if (tmp > 3) { |
| tiling_config |= ROW_TILING(3); |
| tiling_config |= SAMPLE_SPLIT(3); |
| } else { |
| tiling_config |= ROW_TILING(tmp); |
| tiling_config |= SAMPLE_SPLIT(tmp); |
| } |
| tiling_config |= BANK_SWAPS(1); |
| tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes, |
| rdev->config.r600.max_backends, |
| (0xff << rdev->config.r600.max_backends) & 0xff); |
| tiling_config |= BACKEND_MAP(tmp); |
| WREG32(GB_TILING_CONFIG, tiling_config); |
| WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); |
| WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); |
| tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK); |
| WREG32(CC_RB_BACKEND_DISABLE, tmp); |
| /* Setup pipes */ |
| tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK); |
| tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK); |
| WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp); |
| WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp); |
| tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK); |
| WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); |
| WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); |
| /* Setup some CP states */ |
| WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); |
| WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); |
| WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | |
| SYNC_WALKER | SYNC_ALIGNER)); |
| /* Setup various GPU states */ |
| if (rdev->family == CHIP_RV670) |
| WREG32(ARB_GDEC_RD_CNTL, 0x00000021); |
| tmp = RREG32(SX_DEBUG_1); |
| tmp |= SMX_EVENT_RELEASE; |
| if ((rdev->family > CHIP_R600)) |
| tmp |= ENABLE_NEW_SMX_ADDRESS; |
| WREG32(SX_DEBUG_1, tmp); |
| if (((rdev->family) == CHIP_R600) || |
| ((rdev->family) == CHIP_RV630) || |
| ((rdev->family) == CHIP_RV610) || |
| ((rdev->family) == CHIP_RV620) || |
| ((rdev->family) == CHIP_RS780)) { |
| WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); |
| } else { |
| WREG32(DB_DEBUG, 0); |
| } |
| WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | |
| DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); |
| WREG32(PA_SC_MULTI_CHIP_CNTL, 0); |
| WREG32(VGT_NUM_INSTANCES, 0); |
| WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); |
| WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); |
| tmp = RREG32(SQ_MS_FIFO_SIZES); |
| if (((rdev->family) == CHIP_RV610) || |
| ((rdev->family) == CHIP_RV620) || |
| ((rdev->family) == CHIP_RS780)) { |
| tmp = (CACHE_FIFO_SIZE(0xa) | |
| FETCH_FIFO_HIWATER(0xa) | |
| DONE_FIFO_HIWATER(0xe0) | |
| ALU_UPDATE_FIFO_HIWATER(0x8)); |
| } else if (((rdev->family) == CHIP_R600) || |
| ((rdev->family) == CHIP_RV630)) { |
| tmp &= ~DONE_FIFO_HIWATER(0xff); |
| tmp |= DONE_FIFO_HIWATER(0x4); |
| } |
| WREG32(SQ_MS_FIFO_SIZES, tmp); |
| /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT |
| * should be adjusted as needed by the 2D/3D drivers. This just sets default values |
| */ |
| sq_config = RREG32(SQ_CONFIG); |
| sq_config &= ~(PS_PRIO(3) | |
| VS_PRIO(3) | |
| GS_PRIO(3) | |
| ES_PRIO(3)); |
| sq_config |= (DX9_CONSTS | |
| VC_ENABLE | |
| PS_PRIO(0) | |
| VS_PRIO(1) | |
| GS_PRIO(2) | |
| ES_PRIO(3)); |
| if ((rdev->family) == CHIP_R600) { |
| sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | |
| NUM_VS_GPRS(124) | |
| NUM_CLAUSE_TEMP_GPRS(4)); |
| sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | |
| NUM_ES_GPRS(0)); |
| sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | |
| NUM_VS_THREADS(48) | |
| NUM_GS_THREADS(4) | |
| NUM_ES_THREADS(4)); |
| sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | |
| NUM_VS_STACK_ENTRIES(128)); |
| sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | |
| NUM_ES_STACK_ENTRIES(0)); |
| } else if (((rdev->family) == CHIP_RV610) || |
| ((rdev->family) == CHIP_RV620) || |
| ((rdev->family) == CHIP_RS780)) { |
| /* no vertex cache */ |
| sq_config &= ~VC_ENABLE; |
| sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | |
| NUM_VS_GPRS(44) | |
| NUM_CLAUSE_TEMP_GPRS(2)); |
| sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | |
| NUM_ES_GPRS(17)); |
| sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | |
| NUM_VS_THREADS(78) | |
| NUM_GS_THREADS(4) | |
| NUM_ES_THREADS(31)); |
| sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | |
| NUM_VS_STACK_ENTRIES(40)); |
| sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | |
| NUM_ES_STACK_ENTRIES(16)); |
| } else if (((rdev->family) == CHIP_RV630) || |
| ((rdev->family) == CHIP_RV635)) { |
| sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | |
| NUM_VS_GPRS(44) | |
| NUM_CLAUSE_TEMP_GPRS(2)); |
| sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | |
| NUM_ES_GPRS(18)); |
| sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | |
| NUM_VS_THREADS(78) | |
| NUM_GS_THREADS(4) | |
| NUM_ES_THREADS(31)); |
| sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | |
| NUM_VS_STACK_ENTRIES(40)); |
| sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | |
| NUM_ES_STACK_ENTRIES(16)); |
| } else if ((rdev->family) == CHIP_RV670) { |
| sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | |
| NUM_VS_GPRS(44) | |
| NUM_CLAUSE_TEMP_GPRS(2)); |
| sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | |
| NUM_ES_GPRS(17)); |
| sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | |
| NUM_VS_THREADS(78) | |
| NUM_GS_THREADS(4) | |
| NUM_ES_THREADS(31)); |
| sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | |
| NUM_VS_STACK_ENTRIES(64)); |
| sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | |
| NUM_ES_STACK_ENTRIES(64)); |
| } |
| WREG32(SQ_CONFIG, sq_config); |
| WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); |
| WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); |
| WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); |
| WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); |
| WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); |
| if (((rdev->family) == CHIP_RV610) || |
| ((rdev->family) == CHIP_RV620) || |
| ((rdev->family) == CHIP_RS780)) { |
| WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); |
| } else { |
| WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); |
| } |
| /* More default values. 2D/3D driver should adjust as needed */ |
| WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | |
| S1_X(0x4) | S1_Y(0xc))); |
| WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | |
| S1_X(0x2) | S1_Y(0x2) | |
| S2_X(0xa) | S2_Y(0x6) | |
| S3_X(0x6) | S3_Y(0xa))); |
| WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | |
| S1_X(0x4) | S1_Y(0xc) | |
| S2_X(0x1) | S2_Y(0x6) | |
| S3_X(0xa) | S3_Y(0xe))); |
| WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | |
| S5_X(0x0) | S5_Y(0x0) | |
| S6_X(0xb) | S6_Y(0x4) | |
| S7_X(0x7) | S7_Y(0x8))); |
| WREG32(VGT_STRMOUT_EN, 0); |
| tmp = rdev->config.r600.max_pipes * 16; |
| switch (rdev->family) { |
| case CHIP_RV610: |
| case CHIP_RS780: |
| case CHIP_RV620: |
| tmp += 32; |
| break; |
| case CHIP_RV670: |
| tmp += 128; |
| break; |
| default: |
| break; |
| } |
| if (tmp > 256) { |
| tmp = 256; |
| } |
| WREG32(VGT_ES_PER_GS, 128); |
| WREG32(VGT_GS_PER_ES, tmp); |
| WREG32(VGT_GS_PER_VS, 2); |
| WREG32(VGT_GS_VERTEX_REUSE, 16); |
| /* more default values. 2D/3D driver should adjust as needed */ |
| WREG32(PA_SC_LINE_STIPPLE_STATE, 0); |
| WREG32(VGT_STRMOUT_EN, 0); |
| WREG32(SX_MISC, 0); |
| WREG32(PA_SC_MODE_CNTL, 0); |
| WREG32(PA_SC_AA_CONFIG, 0); |
| WREG32(PA_SC_LINE_STIPPLE, 0); |
| WREG32(SPI_INPUT_Z, 0); |
| WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); |
| WREG32(CB_COLOR7_FRAG, 0); |
| /* Clear render buffer base addresses */ |
| WREG32(CB_COLOR0_BASE, 0); |
| WREG32(CB_COLOR1_BASE, 0); |
| WREG32(CB_COLOR2_BASE, 0); |
| WREG32(CB_COLOR3_BASE, 0); |
| WREG32(CB_COLOR4_BASE, 0); |
| WREG32(CB_COLOR5_BASE, 0); |
| WREG32(CB_COLOR6_BASE, 0); |
| WREG32(CB_COLOR7_BASE, 0); |
| WREG32(CB_COLOR7_FRAG, 0); |
| switch (rdev->family) { |
| case CHIP_RV610: |
| case CHIP_RS780: |
| case CHIP_RV620: |
| tmp = TC_L2_SIZE(8); |
| break; |
| case CHIP_RV630: |
| case CHIP_RV635: |
| tmp = TC_L2_SIZE(4); |
| break; |
| case CHIP_R600: |
| tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; |
| break; |
| default: |
| tmp = TC_L2_SIZE(0); |
| break; |
| } |
| WREG32(TC_CNTL, tmp); |
| tmp = RREG32(HDP_HOST_PATH_CNTL); |
| WREG32(HDP_HOST_PATH_CNTL, tmp); |
| tmp = RREG32(ARB_POP); |
| tmp |= ENABLE_TC128; |
| WREG32(ARB_POP, tmp); |
| WREG32(PA_SC_MULTI_CHIP_CNTL, 0); |
| WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | |
| NUM_CLIP_SEQ(3))); |
| WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); |
| } |
| /* |
| * Indirect registers accessor |
| */ |
| u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) |
| uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg) |
| { |
| u32 r; |
| uint32_t r; |
| WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); |
| (void)RREG32(PCIE_PORT_INDEX); |
| r = RREG32(PCIE_PORT_DATA); |
| WREG32(R600_PCIE_PORT_INDEX, ((reg) & 0xff)); |
| (void)RREG32(R600_PCIE_PORT_INDEX); |
| r = RREG32(R600_PCIE_PORT_DATA); |
| return r; |
| } |
| void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
| void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| { |
| WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); |
| (void)RREG32(PCIE_PORT_INDEX); |
| WREG32(PCIE_PORT_DATA, (v)); |
| (void)RREG32(PCIE_PORT_DATA); |
| WREG32(R600_PCIE_PORT_INDEX, ((reg) & 0xff)); |
| (void)RREG32(R600_PCIE_PORT_INDEX); |
| WREG32(R600_PCIE_PORT_DATA, (v)); |
| (void)RREG32(R600_PCIE_PORT_DATA); |
| } |
| /* |
| * CP & Ring |
| */ |
| void r600_cp_stop(struct radeon_device *rdev) |
| { |
| WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); |
| } |
| int r600_cp_start(struct radeon_device *rdev) |
| { |
| int r; |
| uint32_t cp_me; |
| r = radeon_ring_lock(rdev, 7); |
| if (r) { |
| DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
| return r; |
| } |
| radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); |
| radeon_ring_write(rdev, 0x1); |
| if (rdev->family < CHIP_RV770) { |
| radeon_ring_write(rdev, 0x3); |
| radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1); |
| } else { |
| radeon_ring_write(rdev, 0x0); |
| radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1); |
| } |
| radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_unlock_commit(rdev); |
| cp_me = 0xff; |
| WREG32(R_0086D8_CP_ME_CNTL, cp_me); |
| return 0; |
| } |
| void r600_cp_commit(struct radeon_device *rdev) |
| { |
| WREG32(CP_RB_WPTR, rdev->cp.wptr); |
| (void)RREG32(CP_RB_WPTR); |
| } |
| int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
| uint32_t tiling_flags, uint32_t pitch, |
| uint32_t offset, uint32_t obj_size) |
| { |
| /* FIXME: implement */ |
| return 0; |
| } |
| void r600_clear_surface_reg(struct radeon_device *rdev, int reg) |
| { |
| /* FIXME: implement */ |
| } |
| bool r600_card_posted(struct radeon_device *rdev) |
| { |
| uint32_t reg; |
| /* first check CRTCs */ |
| reg = RREG32(D1CRTC_CONTROL) | |
| RREG32(D2CRTC_CONTROL); |
| if (reg & CRTC_EN) |
| return true; |
| /* then check MEM_SIZE, in case the crtcs are off */ |
| if (RREG32(CONFIG_MEMSIZE)) |
| return true; |
| return false; |
| } |
| int r600_startup(struct radeon_device *rdev) |
| { |
| int r; |
| r600_mc_program(rdev); |
| if (rdev->flags & RADEON_IS_AGP) { |
| r600_agp_enable(rdev); |
| } else { |
| r = r600_pcie_gart_enable(rdev); |
| if (r) |
| return r; |
| } |
| r600_gpu_init(rdev); |
| r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, |
| &rdev->r600_blit.shader_gpu_addr); |
| if (r) { |
| DRM_ERROR("failed to pin blit object %d\n", r); |
| return r; |
| } |
| r = radeon_ring_init(rdev, rdev->cp.ring_size); |
| if (r) |
| return r; |
| r = r600_cp_load_microcode(rdev); |
| if (r) |
| return r; |
| r = r600_cp_resume(rdev); |
| if (r) |
| return r; |
| /* write back buffer are not vital so don't worry about failure */ |
| r600_wb_enable(rdev); |
| return 0; |
| } |
| void r600_vga_set_state(struct radeon_device *rdev, bool state) |
| { |
| uint32_t temp; |
| temp = RREG32(CONFIG_CNTL); |
| if (state == false) { |
| temp &= ~(1<<0); |
| temp |= (1<<1); |
| } else { |
| temp &= ~(1<<1); |
| } |
| WREG32(CONFIG_CNTL, temp); |
| } |
| /* Plan is to move initialization in that function and use |
| * helper function so that radeon_device_init pretty much |
| * do nothing more than calling asic specific function. This |
| * should also allow to remove a bunch of callback function |
| * like vram_info. |
| */ |
| int r600_init(struct radeon_device *rdev) |
| { |
| int r; |
| r = radeon_dummy_page_init(rdev); |
| if (r) |
| return r; |
| if (r600_debugfs_mc_info_init(rdev)) { |
| DRM_ERROR("Failed to register debugfs file for mc !\n"); |
| } |
| /* This don't do much */ |
| r = radeon_gem_init(rdev); |
| if (r) |
| return r; |
| /* Read BIOS */ |
| if (!radeon_get_bios(rdev)) { |
| if (ASIC_IS_AVIVO(rdev)) |
| return -EINVAL; |
| } |
| /* Must be an ATOMBIOS */ |
| if (!rdev->is_atom_bios) { |
| dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); |
| return -EINVAL; |
| } |
| r = radeon_atombios_init(rdev); |
| if (r) |
| return r; |
| /* Post card if necessary */ |
| if (!r600_card_posted(rdev) && rdev->bios) { |
| DRM_INFO("GPU not posted. posting now...\n"); |
| atom_asic_init(rdev->mode_info.atom_context); |
| } |
| /* Initialize scratch registers */ |
| r600_scratch_init(rdev); |
| /* Initialize surface registers */ |
| radeon_surface_init(rdev); |
| radeon_get_clock_info(rdev->ddev); |
| r = radeon_clocks_init(rdev); |
| if (r) |
| return r; |
| /* Fence driver */ |
| // r = radeon_fence_driver_init(rdev); |
| // if (r) |
| // return r; |
| r = r600_mc_init(rdev); |
| if (r) |
| return r; |
| /* Memory manager */ |
| r = radeon_object_init(rdev); |
| if (r) |
| return r; |
| rdev->cp.ring_obj = NULL; |
| r600_ring_init(rdev, 1024 * 1024); |
| if (!rdev->me_fw || !rdev->pfp_fw) { |
| r = r600_cp_init_microcode(rdev); |
| if (r) { |
| DRM_ERROR("Failed to load firmware!\n"); |
| return r; |
| } |
| } |
| r = r600_pcie_gart_init(rdev); |
| if (r) |
| return r; |
| rdev->accel_working = true; |
| r = r600_blit_init(rdev); |
| if (r) { |
| DRM_ERROR("radeon: failled blitter (%d).\n", r); |
| return r; |
| } |
| r = r600_startup(rdev); |
| if (r) { |
| // r600_suspend(rdev); |
| // r600_wb_fini(rdev); |
| // radeon_ring_fini(rdev); |
| r600_pcie_gart_fini(rdev); |
| rdev->accel_working = false; |
| } |
| if (rdev->accel_working) { |
| // r = radeon_ib_pool_init(rdev); |
| // if (r) { |
| // DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r); |
| // rdev->accel_working = false; |
| // } |
| // r = r600_ib_test(rdev); |
| // if (r) { |
| // DRM_ERROR("radeon: failled testing IB (%d).\n", r); |
| // rdev->accel_working = false; |
| // } |
| } |
| return 0; |
| } |
| /* |
| * Debugfs info |
| */ |
| #if defined(CONFIG_DEBUG_FS) |
| static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data) |
| { |
| struct drm_info_node *node = (struct drm_info_node *) m->private; |
| struct drm_device *dev = node->minor->dev; |
| struct radeon_device *rdev = dev->dev_private; |
| uint32_t rdp, wdp; |
| unsigned count, i, j; |
| radeon_ring_free_size(rdev); |
| rdp = RREG32(CP_RB_RPTR); |
| wdp = RREG32(CP_RB_WPTR); |
| count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask; |
| seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT)); |
| seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); |
| seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); |
| seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw); |
| seq_printf(m, "%u dwords in ring\n", count); |
| for (j = 0; j <= count; j++) { |
| i = (rdp + j) & rdev->cp.ptr_mask; |
| seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]); |
| } |
| return 0; |
| } |
| static int r600_debugfs_mc_info(struct seq_file *m, void *data) |
| { |
| struct drm_info_node *node = (struct drm_info_node *) m->private; |
| struct drm_device *dev = node->minor->dev; |
| struct radeon_device *rdev = dev->dev_private; |
| DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); |
| DREG32_SYS(m, rdev, VM_L2_STATUS); |
| return 0; |
| } |
| static struct drm_info_list r600_mc_info_list[] = { |
| {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, |
| {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL}, |
| }; |
| #endif |
| int r600_debugfs_mc_info_init(struct radeon_device *rdev) |
| { |
| #if defined(CONFIG_DEBUG_FS) |
| return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); |
| #else |
| return 0; |
| #endif |
| } |
| /drivers/video/drm/radeon/radeon.h |
|---|
| 44,28 → 44,7 |
| * - TESTING, TESTING, TESTING |
| */ |
| /* Initialization path: |
| * We expect that acceleration initialization might fail for various |
| * reasons even thought we work hard to make it works on most |
| * configurations. In order to still have a working userspace in such |
| * situation the init path must succeed up to the memory controller |
| * initialization point. Failure before this point are considered as |
| * fatal error. Here is the init callchain : |
| * radeon_device_init perform common structure, mutex initialization |
| * asic_init setup the GPU memory layout and perform all |
| * one time initialization (failure in this |
| * function are considered fatal) |
| * asic_startup setup the GPU acceleration, in order to |
| * follow guideline the first thing this |
| * function should do is setting the GPU |
| * memory controller (only MC setup failure |
| * are considered as fatal) |
| */ |
| #include <types.h> |
| #include <linux/list.h> |
| #include <pci.h> |
| 141,7 → 120,11 |
| #define writel __raw_writel |
| #define writeq __raw_writeq |
| //#define writeb(b,addr) *(volatile uint8_t* ) addr = (uint8_t)b |
| //#define writew(b,addr) *(volatile uint16_t*) addr = (uint16_t)b |
| //#define writel(b,addr) *(volatile uint32_t*) addr = (uint32_t)b |
| /* |
| * Copy from radeon_drv.h so we don't have to include both and have conflicting |
| * symbol; |
| 390,7 → 373,7 |
| unsigned long idx; |
| uint64_t gpu_addr; |
| struct radeon_fence *fence; |
| uint32_t *ptr; |
| volatile uint32_t *ptr; |
| uint32_t length_dw; |
| }; |
| 463,12 → 446,7 |
| struct radeon_cs_chunk { |
| uint32_t chunk_id; |
| uint32_t length_dw; |
| int kpage_idx[2]; |
| uint32_t *kpage[2]; |
| uint32_t *kdata; |
| void __user *user_ptr; |
| int last_copied_page; |
| int last_page_index; |
| }; |
| struct radeon_cs_parser { |
| 491,38 → 469,8 |
| struct radeon_ib *ib; |
| void *track; |
| unsigned family; |
| int parser_error; |
| }; |
| extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); |
| extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); |
| static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) |
| { |
| struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; |
| u32 pg_idx, pg_offset; |
| u32 idx_value = 0; |
| int new_page; |
| pg_idx = (idx * 4) / PAGE_SIZE; |
| pg_offset = (idx * 4) % PAGE_SIZE; |
| if (ibc->kpage_idx[0] == pg_idx) |
| return ibc->kpage[0][pg_offset/4]; |
| if (ibc->kpage_idx[1] == pg_idx) |
| return ibc->kpage[1][pg_offset/4]; |
| new_page = radeon_cs_update_pages(p, pg_idx); |
| if (new_page < 0) { |
| p->parser_error = new_page; |
| return 0; |
| } |
| idx_value = ibc->kpage[new_page][pg_offset/4]; |
| return idx_value; |
| } |
| struct radeon_cs_packet { |
| unsigned idx; |
| unsigned type; |
| 596,8 → 544,18 |
| void (*fini)(struct radeon_device *rdev); |
| int (*resume)(struct radeon_device *rdev); |
| int (*suspend)(struct radeon_device *rdev); |
| void (*errata)(struct radeon_device *rdev); |
| void (*vram_info)(struct radeon_device *rdev); |
| void (*vga_set_state)(struct radeon_device *rdev, bool state); |
| int (*gpu_reset)(struct radeon_device *rdev); |
| int (*mc_init)(struct radeon_device *rdev); |
| void (*mc_fini)(struct radeon_device *rdev); |
| int (*wb_init)(struct radeon_device *rdev); |
| void (*wb_fini)(struct radeon_device *rdev); |
| int (*gart_init)(struct radeon_device *rdev); |
| void (*gart_fini)(struct radeon_device *rdev); |
| int (*gart_enable)(struct radeon_device *rdev); |
| void (*gart_disable)(struct radeon_device *rdev); |
| void (*gart_tlb_flush)(struct radeon_device *rdev); |
| int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); |
| int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); |
| 607,6 → 565,7 |
| void (*ring_start)(struct radeon_device *rdev); |
| int (*ring_test)(struct radeon_device *rdev); |
| void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); |
| int (*ib_test)(struct radeon_device *rdev); |
| int (*irq_set)(struct radeon_device *rdev); |
| int (*irq_process)(struct radeon_device *rdev); |
| u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
| 707,7 → 666,6 |
| typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); |
| struct radeon_device { |
| void *dev; |
| struct drm_device *ddev; |
| struct pci_dev *pdev; |
| /* ASIC */ |
| 760,6 → 718,7 |
| bool shutdown; |
| bool suspend; |
| bool need_dma32; |
| bool new_init_path; |
| bool accel_working; |
| struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
| const struct firmware *me_fw; /* all family ME firmware */ |
| 854,6 → 813,371 |
| #define radeon_PCI_IDS \ |
| {0x1002, 0x3150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x3152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x3154, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x3E50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x3E54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x4136, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS100|RADEON_IS_IGP}, \ |
| {0x1002, 0x4137, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP}, \ |
| {0x1002, 0x4144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
| {0x1002, 0x4145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
| {0x1002, 0x4146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
| {0x1002, 0x4147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
| {0x1002, 0x4148, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
| {0x1002, 0x4149, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
| {0x1002, 0x414A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
| {0x1002, 0x414B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
| {0x1002, 0x4150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
| {0x1002, 0x4151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
| {0x1002, 0x4152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
| {0x1002, 0x4153, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
| {0x1002, 0x4154, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
| {0x1002, 0x4155, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
| {0x1002, 0x4156, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
| {0x1002, 0x4237, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP}, \ |
| {0x1002, 0x4242, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ |
| {0x1002, 0x4243, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ |
| {0x1002, 0x4336, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS100|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x4337, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x4437, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x4966, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250}, \ |
| {0x1002, 0x4967, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250}, \ |
| {0x1002, 0x4A48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x4A49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x4A4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x4A4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x4A4C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x4A4D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x4A4E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x4A4F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x4A50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x4A54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x4B49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x4B4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x4B4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x4B4C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x4C57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x4C58, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x4C59, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x4C5A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x4C64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x4C66, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x4C67, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x4E44, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
| {0x1002, 0x4E45, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
| {0x1002, 0x4E46, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
| {0x1002, 0x4E47, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
| {0x1002, 0x4E48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
| {0x1002, 0x4E49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
| {0x1002, 0x4E4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
| {0x1002, 0x4E4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
| {0x1002, 0x4E50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x4E51, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x4E52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x4E53, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x4E54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x4E56, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x5144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \ |
| {0x1002, 0x5145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \ |
| {0x1002, 0x5146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \ |
| {0x1002, 0x5147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \ |
| {0x1002, 0x5148, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ |
| {0x1002, 0x514C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ |
| {0x1002, 0x514D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ |
| {0x1002, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200}, \ |
| {0x1002, 0x5158, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200}, \ |
| {0x1002, 0x5159, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ |
| {0x1002, 0x515A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ |
| {0x1002, 0x515E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ |
| {0x1002, 0x5460, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x5462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x5464, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x5657, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5548, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5549, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x554A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x554B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x554C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x554D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x554E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x554F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5550, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5551, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5554, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x564A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x564B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x564F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP}, \ |
| {0x1002, 0x5835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
| {0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
| {0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
| {0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
| {0x1002, 0x5960, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ |
| {0x1002, 0x5961, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ |
| {0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ |
| {0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ |
| {0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ |
| {0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ |
| {0x1002, 0x5a41, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART}, \ |
| {0x1002, 0x5a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
| {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART}, \ |
| {0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
| {0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5b64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5b65, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5c61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x5c63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x5d48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5d49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5d4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5d4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5d4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5d4e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5d4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5d50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5d52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5d57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5e48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5e4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5e4b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5e4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5e4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5e4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x710A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x710B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x710C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x710E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x710F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7140, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7141, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7142, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7143, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7149, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x714A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x714B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x714C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x714D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x714E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x714F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7153, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x715E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x715F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7181, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7183, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7186, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7187, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7188, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x718A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x718B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x718C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x718D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x718F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7193, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7196, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x719B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x719F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71CE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71D2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71D4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71D5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71D6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7243, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7244, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7245, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7247, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7248, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7249, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x724A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x724B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x724C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x724D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x724E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x724F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7280, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7281, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7283, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7284, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7287, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7289, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x728B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x728C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7290, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7291, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7293, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7297, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x791e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ |
| {0x1002, 0x791f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ |
| {0x1002, 0x793f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7941, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7942, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x796c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ |
| {0x1002, 0x796d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ |
| {0x1002, 0x796e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ |
| {0x1002, 0x796f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ |
| {0x1002, 0x9400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9401, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9402, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9403, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x940A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x940B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x940F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9441, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9442, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9444, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x944A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x944B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x944C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x944E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9450, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9452, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9456, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x945A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x945B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9460, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x946A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x946B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x947A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x947B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9480, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9487, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9488, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9489, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x948F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9490, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9491, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9498, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x949C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x949E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x949F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x94C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x94C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x94C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x94C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x94C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x94C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x94C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x94C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x94C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x94CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x94CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x94CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9504, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9505, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9506, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9507, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9508, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9509, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x950F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9515, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9517, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9519, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9540, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9542, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x954E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x954F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9553, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9555, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9580, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9581, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9583, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9586, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9587, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9588, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9589, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x958A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x958B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x958C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x958D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x958E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x958F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9590, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9593, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9595, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9596, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9597, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9598, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9599, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x959B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x95C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x95C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x95C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x95C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x95C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x95C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x95C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x95CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x95CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x95CE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x95CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
| {0x1002, 0x9611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
| {0x1002, 0x9612, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
| {0x1002, 0x9613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
| {0x1002, 0x9614, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
| {0x1002, 0x9615, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
| {0x1002, 0x9616, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
| {0, 0, 0} |
| enum chipset_type { |
| NOT_SUPPORTED, |
| SUPPORTED, |
| 900,7 → 1224,9 |
| }; |
| #define radeon_errata(rdev) (rdev)->asic->errata((rdev)) |
| /* |
| * ASICs helpers. |
| */ |
| 943,6 → 1269,51 |
| /* |
| * RING helpers. |
| */ |
| #define CP_PACKET0 0x00000000 |
| #define PACKET0_BASE_INDEX_SHIFT 0 |
| #define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) |
| #define PACKET0_COUNT_SHIFT 16 |
| #define PACKET0_COUNT_MASK (0x3fff << 16) |
| #define CP_PACKET1 0x40000000 |
| #define CP_PACKET2 0x80000000 |
| #define PACKET2_PAD_SHIFT 0 |
| #define PACKET2_PAD_MASK (0x3fffffff << 0) |
| #define CP_PACKET3 0xC0000000 |
| #define PACKET3_IT_OPCODE_SHIFT 8 |
| #define PACKET3_IT_OPCODE_MASK (0xff << 8) |
| #define PACKET3_COUNT_SHIFT 16 |
| #define PACKET3_COUNT_MASK (0x3fff << 16) |
| /* PACKET3 op code */ |
| #define PACKET3_NOP 0x10 |
| #define PACKET3_3D_DRAW_VBUF 0x28 |
| #define PACKET3_3D_DRAW_IMMD 0x29 |
| #define PACKET3_3D_DRAW_INDX 0x2A |
| #define PACKET3_3D_LOAD_VBPNTR 0x2F |
| #define PACKET3_INDX_BUFFER 0x33 |
| #define PACKET3_3D_DRAW_VBUF_2 0x34 |
| #define PACKET3_3D_DRAW_IMMD_2 0x35 |
| #define PACKET3_3D_DRAW_INDX_2 0x36 |
| #define PACKET3_BITBLT_MULTI 0x9B |
| #define PACKET0(reg, n) (CP_PACKET0 | \ |
| REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ |
| REG_SET(PACKET0_COUNT, (n))) |
| #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) |
| #define PACKET3(op, n) (CP_PACKET3 | \ |
| REG_SET(PACKET3_IT_OPCODE, (op)) | \ |
| REG_SET(PACKET3_COUNT, (n))) |
| #define PACKET_TYPE0 0 |
| #define PACKET_TYPE1 1 |
| #define PACKET_TYPE2 2 |
| #define PACKET_TYPE3 3 |
| #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) |
| #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) |
| #define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2) |
| #define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) |
| #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) |
| static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) |
| { |
| #if DRM_DEBUG_CODE |
| 965,14 → 1336,28 |
| #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) |
| #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) |
| #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
| #define radeon_errata(rdev) (rdev)->asic->errata((rdev)) |
| #define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev)) |
| #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
| #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev)) |
| #define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev)) |
| #define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev)) |
| #define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev)) |
| #define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev)) |
| #define radeon_gpu_gart_init(rdev) (rdev)->asic->gart_init((rdev)) |
| #define radeon_gpu_gart_fini(rdev) (rdev)->asic->gart_fini((rdev)) |
| #define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev)) |
| #define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev)) |
| #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
| #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) |
| #define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize)) |
| #define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev)) |
| #define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev)) |
| #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) |
| #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) |
| #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) |
| #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) |
| #define radeon_ib_test(rdev) (rdev)->asic->ib_test((rdev)) |
| #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) |
| #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) |
| #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) |
| 998,8 → 1383,6 |
| extern void radeon_scratch_init(struct radeon_device *rdev); |
| extern void radeon_surface_init(struct radeon_device *rdev); |
| extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
| extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
| extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
| /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ |
| struct r100_mc_save { |
| 1031,30 → 1414,11 |
| extern void r100_wb_disable(struct radeon_device *rdev); |
| extern void r100_wb_fini(struct radeon_device *rdev); |
| extern int r100_wb_init(struct radeon_device *rdev); |
| extern void r100_hdp_reset(struct radeon_device *rdev); |
| extern int r100_rb2d_reset(struct radeon_device *rdev); |
| extern int r100_cp_reset(struct radeon_device *rdev); |
| extern void r100_vga_render_disable(struct radeon_device *rdev); |
| extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
| struct radeon_cs_packet *pkt, |
| struct radeon_object *robj); |
| extern int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
| struct radeon_cs_packet *pkt, |
| const unsigned *auth, unsigned n, |
| radeon_packet0_check_t check); |
| extern int r100_cs_packet_parse(struct radeon_cs_parser *p, |
| struct radeon_cs_packet *pkt, |
| unsigned idx); |
| /* rv200,rv250,rv280 */ |
| extern void r200_set_safe_registers(struct radeon_device *rdev); |
| /* r300,r350,rv350,rv370,rv380 */ |
| extern void r300_set_reg_safe(struct radeon_device *rdev); |
| extern void r300_mc_program(struct radeon_device *rdev); |
| extern void r300_vram_info(struct radeon_device *rdev); |
| extern void r300_clock_startup(struct radeon_device *rdev); |
| extern int r300_mc_wait_for_idle(struct radeon_device *rdev); |
| extern int rv370_pcie_gart_init(struct radeon_device *rdev); |
| extern void rv370_pcie_gart_fini(struct radeon_device *rdev); |
| extern int rv370_pcie_gart_enable(struct radeon_device *rdev); |
| 1061,42 → 1425,13 |
| extern void rv370_pcie_gart_disable(struct radeon_device *rdev); |
| /* r420,r423,rv410 */ |
| extern int r420_mc_init(struct radeon_device *rdev); |
| extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
| extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
| extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); |
| extern void r420_pipes_init(struct radeon_device *rdev); |
| /* rv515 */ |
| struct rv515_mc_save { |
| u32 d1vga_control; |
| u32 d2vga_control; |
| u32 vga_render_control; |
| u32 vga_hdp_control; |
| u32 d1crtc_control; |
| u32 d2crtc_control; |
| }; |
| extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
| extern void rv515_vga_render_disable(struct radeon_device *rdev); |
| extern void rv515_set_safe_registers(struct radeon_device *rdev); |
| extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); |
| extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); |
| extern void rv515_clock_startup(struct radeon_device *rdev); |
| extern void rv515_debugfs(struct radeon_device *rdev); |
| extern int rv515_suspend(struct radeon_device *rdev); |
| /* rs400 */ |
| extern int rs400_gart_init(struct radeon_device *rdev); |
| extern int rs400_gart_enable(struct radeon_device *rdev); |
| extern void rs400_gart_adjust_size(struct radeon_device *rdev); |
| extern void rs400_gart_disable(struct radeon_device *rdev); |
| extern void rs400_gart_fini(struct radeon_device *rdev); |
| /* rs600 */ |
| extern void rs600_set_safe_registers(struct radeon_device *rdev); |
| extern int rs600_irq_set(struct radeon_device *rdev); |
| extern void rs600_irq_disable(struct radeon_device *rdev); |
| /* rs690, rs740 */ |
| extern void rs690_line_buffer_adjust(struct radeon_device *rdev, |
| struct drm_display_mode *mode1, |
| 1114,9 → 1449,8 |
| extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| extern int r600_ib_test(struct radeon_device *rdev); |
| extern int r600_ring_test(struct radeon_device *rdev); |
| extern int r600_wb_init(struct radeon_device *rdev); |
| extern void r600_wb_fini(struct radeon_device *rdev); |
| extern int r600_wb_enable(struct radeon_device *rdev); |
| extern void r600_wb_disable(struct radeon_device *rdev); |
| extern void r600_scratch_init(struct radeon_device *rdev); |
| extern int r600_blit_init(struct radeon_device *rdev); |
| extern void r600_blit_fini(struct radeon_device *rdev); |
| /drivers/video/drm/radeon/radeon_asic.h |
|---|
| 41,17 → 41,28 |
| /* |
| * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 |
| */ |
| extern int r100_init(struct radeon_device *rdev); |
| extern void r100_fini(struct radeon_device *rdev); |
| extern int r100_suspend(struct radeon_device *rdev); |
| extern int r100_resume(struct radeon_device *rdev); |
| int r100_init(struct radeon_device *rdev); |
| int r200_init(struct radeon_device *rdev); |
| uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg); |
| void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| void r100_errata(struct radeon_device *rdev); |
| void r100_vram_info(struct radeon_device *rdev); |
| void r100_vga_set_state(struct radeon_device *rdev, bool state); |
| int r100_gpu_reset(struct radeon_device *rdev); |
| int r100_mc_init(struct radeon_device *rdev); |
| void r100_mc_fini(struct radeon_device *rdev); |
| u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); |
| int r100_wb_init(struct radeon_device *rdev); |
| void r100_wb_fini(struct radeon_device *rdev); |
| int r100_pci_gart_init(struct radeon_device *rdev); |
| void r100_pci_gart_fini(struct radeon_device *rdev); |
| int r100_pci_gart_enable(struct radeon_device *rdev); |
| void r100_pci_gart_disable(struct radeon_device *rdev); |
| void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
| int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
| int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); |
| void r100_cp_fini(struct radeon_device *rdev); |
| void r100_cp_disable(struct radeon_device *rdev); |
| void r100_cp_commit(struct radeon_device *rdev); |
| void r100_ring_start(struct radeon_device *rdev); |
| int r100_irq_set(struct radeon_device *rdev); |
| 72,33 → 83,37 |
| int r100_clear_surface_reg(struct radeon_device *rdev, int reg); |
| void r100_bandwidth_update(struct radeon_device *rdev); |
| void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| int r100_ib_test(struct radeon_device *rdev); |
| int r100_ring_test(struct radeon_device *rdev); |
| static struct radeon_asic r100_asic = { |
| .init = &r100_init, |
| // .fini = &r100_fini, |
| // .suspend = &r100_suspend, |
| // .resume = &r100_resume, |
| // .vga_set_state = &r100_vga_set_state, |
| .errata = &r100_errata, |
| .vram_info = &r100_vram_info, |
| .gpu_reset = &r100_gpu_reset, |
| .mc_init = &r100_mc_init, |
| .mc_fini = &r100_mc_fini, |
| // .wb_init = &r100_wb_init, |
| // .wb_fini = &r100_wb_fini, |
| .gart_enable = &r100_pci_gart_enable, |
| .gart_disable = &r100_pci_gart_disable, |
| .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
| .gart_set_page = &r100_pci_gart_set_page, |
| .cp_commit = &r100_cp_commit, |
| // .ring_start = &r100_ring_start, |
| // .ring_test = &r100_ring_test, |
| // .ring_ib_execute = &r100_ring_ib_execute, |
| .cp_init = &r100_cp_init, |
| // .cp_fini = &r100_cp_fini, |
| // .cp_disable = &r100_cp_disable, |
| .ring_start = &r100_ring_start, |
| // .irq_set = &r100_irq_set, |
| // .irq_process = &r100_irq_process, |
| // .get_vblank_counter = &r100_get_vblank_counter, |
| // .fence_ring_emit = &r100_fence_ring_emit, |
| // .cs_parse = &r100_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = NULL, |
| // .copy = &r100_copy_blit, |
| .set_engine_clock = &radeon_legacy_set_engine_clock, |
| .set_memory_clock = NULL, |
| .set_pcie_lanes = NULL, |
| .set_clock_gating = &radeon_legacy_set_clock_gating, |
| // .set_engine_clock = &radeon_legacy_set_engine_clock, |
| // .set_memory_clock = NULL, |
| // .set_pcie_lanes = NULL, |
| // .set_clock_gating = &radeon_legacy_set_clock_gating, |
| .set_surface_reg = r100_set_surface_reg, |
| .clear_surface_reg = r100_clear_surface_reg, |
| .bandwidth_update = &r100_bandwidth_update, |
| 108,50 → 123,60 |
| /* |
| * r300,r350,rv350,rv380 |
| */ |
| extern int r300_init(struct radeon_device *rdev); |
| extern void r300_fini(struct radeon_device *rdev); |
| extern int r300_suspend(struct radeon_device *rdev); |
| extern int r300_resume(struct radeon_device *rdev); |
| extern int r300_gpu_reset(struct radeon_device *rdev); |
| extern void r300_ring_start(struct radeon_device *rdev); |
| extern void r300_fence_ring_emit(struct radeon_device *rdev, |
| int r300_init(struct radeon_device *rdev); |
| void r300_errata(struct radeon_device *rdev); |
| void r300_vram_info(struct radeon_device *rdev); |
| int r300_gpu_reset(struct radeon_device *rdev); |
| int r300_mc_init(struct radeon_device *rdev); |
| void r300_mc_fini(struct radeon_device *rdev); |
| void r300_ring_start(struct radeon_device *rdev); |
| void r300_fence_ring_emit(struct radeon_device *rdev, |
| struct radeon_fence *fence); |
| extern int r300_cs_parse(struct radeon_cs_parser *p); |
| extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
| extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); |
| extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
| extern int r300_copy_dma(struct radeon_device *rdev, |
| int r300_cs_parse(struct radeon_cs_parser *p); |
| int rv370_pcie_gart_init(struct radeon_device *rdev); |
| void rv370_pcie_gart_fini(struct radeon_device *rdev); |
| int rv370_pcie_gart_enable(struct radeon_device *rdev); |
| void rv370_pcie_gart_disable(struct radeon_device *rdev); |
| void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
| uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); |
| void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
| int r300_copy_dma(struct radeon_device *rdev, |
| uint64_t src_offset, |
| uint64_t dst_offset, |
| unsigned num_pages, |
| struct radeon_fence *fence); |
| static struct radeon_asic r300_asic = { |
| .init = &r300_init, |
| // .fini = &r300_fini, |
| // .suspend = &r300_suspend, |
| // .resume = &r300_resume, |
| // .vga_set_state = &r100_vga_set_state, |
| .errata = &r300_errata, |
| .vram_info = &r300_vram_info, |
| .vga_set_state = &r100_vga_set_state, |
| .gpu_reset = &r300_gpu_reset, |
| .mc_init = &r300_mc_init, |
| .mc_fini = &r300_mc_fini, |
| // .wb_init = &r100_wb_init, |
| // .wb_fini = &r100_wb_fini, |
| .gart_enable = &r100_pci_gart_enable, |
| .gart_disable = &r100_pci_gart_disable, |
| .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
| .gart_set_page = &r100_pci_gart_set_page, |
| // .cp_commit = &r100_cp_commit, |
| // .ring_start = &r300_ring_start, |
| // .ring_test = &r100_ring_test, |
| // .ring_ib_execute = &r100_ring_ib_execute, |
| .cp_init = &r100_cp_init, |
| // .cp_fini = &r100_cp_fini, |
| // .cp_disable = &r100_cp_disable, |
| .ring_start = &r300_ring_start, |
| // .irq_set = &r100_irq_set, |
| // .irq_process = &r100_irq_process, |
| // .get_vblank_counter = &r100_get_vblank_counter, |
| // .fence_ring_emit = &r300_fence_ring_emit, |
| // .cs_parse = &r300_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = &r300_copy_dma, |
| // .copy = &r100_copy_blit, |
| .set_engine_clock = &radeon_legacy_set_engine_clock, |
| .set_memory_clock = NULL, |
| .set_pcie_lanes = &rv370_set_pcie_lanes, |
| .set_clock_gating = &radeon_legacy_set_clock_gating, |
| // .set_engine_clock = &radeon_legacy_set_engine_clock, |
| // .set_memory_clock = NULL, |
| // .set_pcie_lanes = &rv370_set_pcie_lanes, |
| // .set_clock_gating = &radeon_legacy_set_clock_gating, |
| .set_surface_reg = r100_set_surface_reg, |
| .clear_surface_reg = r100_clear_surface_reg, |
| .bandwidth_update = &r100_bandwidth_update, |
| 166,29 → 191,36 |
| extern int r420_resume(struct radeon_device *rdev); |
| static struct radeon_asic r420_asic = { |
| .init = &r420_init, |
| // .fini = &r420_fini, |
| // .suspend = &r420_suspend, |
| // .resume = &r420_resume, |
| // .vga_set_state = &r100_vga_set_state, |
| .fini = &r420_fini, |
| .suspend = &r420_suspend, |
| .resume = &r420_resume, |
| .errata = NULL, |
| .vram_info = NULL, |
| .vga_set_state = &r100_vga_set_state, |
| .gpu_reset = &r300_gpu_reset, |
| .mc_init = NULL, |
| .mc_fini = NULL, |
| .wb_init = NULL, |
| .wb_fini = NULL, |
| .gart_enable = NULL, |
| .gart_disable = NULL, |
| .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
| .gart_set_page = &rv370_pcie_gart_set_page, |
| // .cp_commit = &r100_cp_commit, |
| // .ring_start = &r300_ring_start, |
| // .ring_test = &r100_ring_test, |
| // .ring_ib_execute = &r100_ring_ib_execute, |
| .cp_init = NULL, |
| .cp_fini = NULL, |
| .cp_disable = NULL, |
| .ring_start = &r300_ring_start, |
| // .irq_set = &r100_irq_set, |
| // .irq_process = &r100_irq_process, |
| // .get_vblank_counter = &r100_get_vblank_counter, |
| // .fence_ring_emit = &r300_fence_ring_emit, |
| // .cs_parse = &r300_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = &r300_copy_dma, |
| // .copy = &r100_copy_blit, |
| .set_engine_clock = &radeon_atom_set_engine_clock, |
| .set_memory_clock = &radeon_atom_set_memory_clock, |
| .set_pcie_lanes = &rv370_set_pcie_lanes, |
| .set_clock_gating = &radeon_atom_set_clock_gating, |
| // .set_engine_clock = &radeon_atom_set_engine_clock, |
| // .set_memory_clock = &radeon_atom_set_memory_clock, |
| // .set_pcie_lanes = &rv370_set_pcie_lanes, |
| // .set_clock_gating = &radeon_atom_set_clock_gating, |
| .set_surface_reg = r100_set_surface_reg, |
| .clear_surface_reg = r100_clear_surface_reg, |
| .bandwidth_update = &r100_bandwidth_update, |
| 198,39 → 230,50 |
| /* |
| * rs400,rs480 |
| */ |
| extern int rs400_init(struct radeon_device *rdev); |
| extern void rs400_fini(struct radeon_device *rdev); |
| extern int rs400_suspend(struct radeon_device *rdev); |
| extern int rs400_resume(struct radeon_device *rdev); |
| void rs400_errata(struct radeon_device *rdev); |
| void rs400_vram_info(struct radeon_device *rdev); |
| int rs400_mc_init(struct radeon_device *rdev); |
| void rs400_mc_fini(struct radeon_device *rdev); |
| int rs400_gart_init(struct radeon_device *rdev); |
| void rs400_gart_fini(struct radeon_device *rdev); |
| int rs400_gart_enable(struct radeon_device *rdev); |
| void rs400_gart_disable(struct radeon_device *rdev); |
| void rs400_gart_tlb_flush(struct radeon_device *rdev); |
| int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
| uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| static struct radeon_asic rs400_asic = { |
| .init = &rs400_init, |
| // .fini = &rs400_fini, |
| // .suspend = &rs400_suspend, |
| // .resume = &rs400_resume, |
| // .vga_set_state = &r100_vga_set_state, |
| .init = &r300_init, |
| .errata = &rs400_errata, |
| .vram_info = &rs400_vram_info, |
| .vga_set_state = &r100_vga_set_state, |
| .gpu_reset = &r300_gpu_reset, |
| .mc_init = &rs400_mc_init, |
| .mc_fini = &rs400_mc_fini, |
| // .wb_init = &r100_wb_init, |
| // .wb_fini = &r100_wb_fini, |
| .gart_init = &rs400_gart_init, |
| .gart_fini = &rs400_gart_fini, |
| .gart_enable = &rs400_gart_enable, |
| .gart_disable = &rs400_gart_disable, |
| .gart_tlb_flush = &rs400_gart_tlb_flush, |
| .gart_set_page = &rs400_gart_set_page, |
| // .cp_commit = &r100_cp_commit, |
| // .ring_start = &r300_ring_start, |
| // .ring_test = &r100_ring_test, |
| // .ring_ib_execute = &r100_ring_ib_execute, |
| .cp_init = &r100_cp_init, |
| // .cp_fini = &r100_cp_fini, |
| // .cp_disable = &r100_cp_disable, |
| .cp_commit = &r100_cp_commit, |
| .ring_start = &r300_ring_start, |
| // .irq_set = &r100_irq_set, |
| // .irq_process = &r100_irq_process, |
| // .get_vblank_counter = &r100_get_vblank_counter, |
| // .fence_ring_emit = &r300_fence_ring_emit, |
| // .cs_parse = &r300_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = &r300_copy_dma, |
| // .copy = &r100_copy_blit, |
| .set_engine_clock = &radeon_legacy_set_engine_clock, |
| .set_memory_clock = NULL, |
| .set_pcie_lanes = NULL, |
| .set_clock_gating = &radeon_legacy_set_clock_gating, |
| // .set_engine_clock = &radeon_legacy_set_engine_clock, |
| // .set_memory_clock = NULL, |
| // .set_pcie_lanes = NULL, |
| // .set_clock_gating = &radeon_legacy_set_clock_gating, |
| .set_surface_reg = r100_set_surface_reg, |
| .clear_surface_reg = r100_clear_surface_reg, |
| .bandwidth_update = &r100_bandwidth_update, |
| 240,13 → 283,18 |
| /* |
| * rs600. |
| */ |
| extern int rs600_init(struct radeon_device *rdev); |
| extern void rs600_fini(struct radeon_device *rdev); |
| extern int rs600_suspend(struct radeon_device *rdev); |
| extern int rs600_resume(struct radeon_device *rdev); |
| int rs600_init(struct radeon_device *rdev); |
| void rs600_errata(struct radeon_device *rdev); |
| void rs600_vram_info(struct radeon_device *rdev); |
| int rs600_mc_init(struct radeon_device *rdev); |
| void rs600_mc_fini(struct radeon_device *rdev); |
| int rs600_irq_set(struct radeon_device *rdev); |
| int rs600_irq_process(struct radeon_device *rdev); |
| u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); |
| int rs600_gart_init(struct radeon_device *rdev); |
| void rs600_gart_fini(struct radeon_device *rdev); |
| int rs600_gart_enable(struct radeon_device *rdev); |
| void rs600_gart_disable(struct radeon_device *rdev); |
| void rs600_gart_tlb_flush(struct radeon_device *rdev); |
| int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
| uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| 254,29 → 302,36 |
| void rs600_bandwidth_update(struct radeon_device *rdev); |
| static struct radeon_asic rs600_asic = { |
| .init = &rs600_init, |
| // .fini = &rs600_fini, |
| // .suspend = &rs600_suspend, |
| // .resume = &rs600_resume, |
| // .vga_set_state = &r100_vga_set_state, |
| .errata = &rs600_errata, |
| .vram_info = &rs600_vram_info, |
| .vga_set_state = &r100_vga_set_state, |
| .gpu_reset = &r300_gpu_reset, |
| .mc_init = &rs600_mc_init, |
| .mc_fini = &rs600_mc_fini, |
| // .wb_init = &r100_wb_init, |
| // .wb_fini = &r100_wb_fini, |
| .gart_init = &rs600_gart_init, |
| .gart_fini = &rs600_gart_fini, |
| .gart_enable = &rs600_gart_enable, |
| .gart_disable = &rs600_gart_disable, |
| .gart_tlb_flush = &rs600_gart_tlb_flush, |
| .gart_set_page = &rs600_gart_set_page, |
| // .cp_commit = &r100_cp_commit, |
| // .ring_start = &r300_ring_start, |
| // .ring_test = &r100_ring_test, |
| // .ring_ib_execute = &r100_ring_ib_execute, |
| .cp_init = &r100_cp_init, |
| // .cp_fini = &r100_cp_fini, |
| // .cp_disable = &r100_cp_disable, |
| .cp_commit = &r100_cp_commit, |
| .ring_start = &r300_ring_start, |
| // .irq_set = &rs600_irq_set, |
| // .irq_process = &rs600_irq_process, |
| // .get_vblank_counter = &rs600_get_vblank_counter, |
| // .irq_process = &r100_irq_process, |
| // .fence_ring_emit = &r300_fence_ring_emit, |
| // .cs_parse = &r300_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = &r300_copy_dma, |
| // .copy = &r100_copy_blit, |
| .set_engine_clock = &radeon_atom_set_engine_clock, |
| .set_memory_clock = &radeon_atom_set_memory_clock, |
| .set_pcie_lanes = NULL, |
| .set_clock_gating = &radeon_atom_set_clock_gating, |
| // .set_engine_clock = &radeon_atom_set_engine_clock, |
| // .set_memory_clock = &radeon_atom_set_memory_clock, |
| // .set_pcie_lanes = NULL, |
| // .set_clock_gating = &radeon_atom_set_clock_gating, |
| .bandwidth_update = &rs600_bandwidth_update, |
| }; |
| 284,38 → 339,45 |
| /* |
| * rs690,rs740 |
| */ |
| int rs690_init(struct radeon_device *rdev); |
| void rs690_fini(struct radeon_device *rdev); |
| int rs690_resume(struct radeon_device *rdev); |
| int rs690_suspend(struct radeon_device *rdev); |
| void rs690_errata(struct radeon_device *rdev); |
| void rs690_vram_info(struct radeon_device *rdev); |
| int rs690_mc_init(struct radeon_device *rdev); |
| void rs690_mc_fini(struct radeon_device *rdev); |
| uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| void rs690_bandwidth_update(struct radeon_device *rdev); |
| static struct radeon_asic rs690_asic = { |
| .init = &rs690_init, |
| // .fini = &rs690_fini, |
| // .suspend = &rs690_suspend, |
| // .resume = &rs690_resume, |
| // .vga_set_state = &r100_vga_set_state, |
| .init = &rs600_init, |
| .errata = &rs690_errata, |
| .vram_info = &rs690_vram_info, |
| .vga_set_state = &r100_vga_set_state, |
| .gpu_reset = &r300_gpu_reset, |
| .mc_init = &rs690_mc_init, |
| .mc_fini = &rs690_mc_fini, |
| // .wb_init = &r100_wb_init, |
| // .wb_fini = &r100_wb_fini, |
| .gart_init = &rs400_gart_init, |
| .gart_fini = &rs400_gart_fini, |
| .gart_enable = &rs400_gart_enable, |
| .gart_disable = &rs400_gart_disable, |
| .gart_tlb_flush = &rs400_gart_tlb_flush, |
| .gart_set_page = &rs400_gart_set_page, |
| // .cp_commit = &r100_cp_commit, |
| // .ring_start = &r300_ring_start, |
| // .ring_test = &r100_ring_test, |
| // .ring_ib_execute = &r100_ring_ib_execute, |
| .cp_init = &r100_cp_init, |
| // .cp_fini = &r100_cp_fini, |
| // .cp_disable = &r100_cp_disable, |
| .cp_commit = &r100_cp_commit, |
| .ring_start = &r300_ring_start, |
| // .irq_set = &rs600_irq_set, |
| // .irq_process = &rs600_irq_process, |
| // .get_vblank_counter = &rs600_get_vblank_counter, |
| // .irq_process = &r100_irq_process, |
| // .fence_ring_emit = &r300_fence_ring_emit, |
| // .cs_parse = &r300_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = &r300_copy_dma, |
| // .copy = &r300_copy_dma, |
| .set_engine_clock = &radeon_atom_set_engine_clock, |
| .set_memory_clock = &radeon_atom_set_memory_clock, |
| .set_pcie_lanes = NULL, |
| .set_clock_gating = &radeon_atom_set_clock_gating, |
| // .set_engine_clock = &radeon_atom_set_engine_clock, |
| // .set_memory_clock = &radeon_atom_set_memory_clock, |
| // .set_pcie_lanes = NULL, |
| // .set_clock_gating = &radeon_atom_set_clock_gating, |
| .set_surface_reg = r100_set_surface_reg, |
| .clear_surface_reg = r100_clear_surface_reg, |
| .bandwidth_update = &rs690_bandwidth_update, |
| 326,8 → 388,11 |
| * rv515 |
| */ |
| int rv515_init(struct radeon_device *rdev); |
| void rv515_fini(struct radeon_device *rdev); |
| void rv515_errata(struct radeon_device *rdev); |
| void rv515_vram_info(struct radeon_device *rdev); |
| int rv515_gpu_reset(struct radeon_device *rdev); |
| int rv515_mc_init(struct radeon_device *rdev); |
| void rv515_mc_fini(struct radeon_device *rdev); |
| uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| void rv515_ring_start(struct radeon_device *rdev); |
| 334,33 → 399,38 |
| uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg); |
| void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| void rv515_bandwidth_update(struct radeon_device *rdev); |
| int rv515_resume(struct radeon_device *rdev); |
| int rv515_suspend(struct radeon_device *rdev); |
| static struct radeon_asic rv515_asic = { |
| .init = &rv515_init, |
| // .fini = &rv515_fini, |
| // .suspend = &rv515_suspend, |
| // .resume = &rv515_resume, |
| // .vga_set_state = &r100_vga_set_state, |
| .errata = &rv515_errata, |
| .vram_info = &rv515_vram_info, |
| .vga_set_state = &r100_vga_set_state, |
| .gpu_reset = &rv515_gpu_reset, |
| .mc_init = &rv515_mc_init, |
| .mc_fini = &rv515_mc_fini, |
| // .wb_init = &r100_wb_init, |
| // .wb_fini = &r100_wb_fini, |
| .gart_init = &rv370_pcie_gart_init, |
| .gart_fini = &rv370_pcie_gart_fini, |
| .gart_enable = &rv370_pcie_gart_enable, |
| .gart_disable = &rv370_pcie_gart_disable, |
| .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
| .gart_set_page = &rv370_pcie_gart_set_page, |
| // .cp_commit = &r100_cp_commit, |
| // .ring_start = &rv515_ring_start, |
| // .ring_test = &r100_ring_test, |
| // .ring_ib_execute = &r100_ring_ib_execute, |
| // .irq_set = &rs600_irq_set, |
| // .irq_process = &rs600_irq_process, |
| // .get_vblank_counter = &rs600_get_vblank_counter, |
| .cp_init = &r100_cp_init, |
| // .cp_fini = &r100_cp_fini, |
| // .cp_disable = &r100_cp_disable, |
| .cp_commit = &r100_cp_commit, |
| .ring_start = &rv515_ring_start, |
| // .irq_set = &r100_irq_set, |
| // .irq_process = &r100_irq_process, |
| // .fence_ring_emit = &r300_fence_ring_emit, |
| // .cs_parse = &r300_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = &r300_copy_dma, |
| // .copy = &r100_copy_blit, |
| .set_engine_clock = &radeon_atom_set_engine_clock, |
| .set_memory_clock = &radeon_atom_set_memory_clock, |
| .set_pcie_lanes = &rv370_set_pcie_lanes, |
| .set_clock_gating = &radeon_atom_set_clock_gating, |
| // .set_engine_clock = &radeon_atom_set_engine_clock, |
| // .set_memory_clock = &radeon_atom_set_memory_clock, |
| // .set_pcie_lanes = &rv370_set_pcie_lanes, |
| // .set_clock_gating = &radeon_atom_set_clock_gating, |
| .set_surface_reg = r100_set_surface_reg, |
| .clear_surface_reg = r100_clear_surface_reg, |
| .bandwidth_update = &rv515_bandwidth_update, |
| 370,40 → 440,50 |
| /* |
| * r520,rv530,rv560,rv570,r580 |
| */ |
| int r520_init(struct radeon_device *rdev); |
| int r520_resume(struct radeon_device *rdev); |
| void r520_errata(struct radeon_device *rdev); |
| void r520_vram_info(struct radeon_device *rdev); |
| int r520_mc_init(struct radeon_device *rdev); |
| void r520_mc_fini(struct radeon_device *rdev); |
| void r520_bandwidth_update(struct radeon_device *rdev); |
| static struct radeon_asic r520_asic = { |
| .init = &r520_init, |
| // .fini = &rv515_fini, |
| // .suspend = &rv515_suspend, |
| // .resume = &r520_resume, |
| // .vga_set_state = &r100_vga_set_state, |
| .init = &rv515_init, |
| .errata = &r520_errata, |
| .vram_info = &r520_vram_info, |
| .vga_set_state = &r100_vga_set_state, |
| .gpu_reset = &rv515_gpu_reset, |
| .mc_init = &r520_mc_init, |
| .mc_fini = &r520_mc_fini, |
| // .wb_init = &r100_wb_init, |
| // .wb_fini = &r100_wb_fini, |
| .gart_init = &rv370_pcie_gart_init, |
| .gart_fini = &rv370_pcie_gart_fini, |
| .gart_enable = &rv370_pcie_gart_enable, |
| .gart_disable = &rv370_pcie_gart_disable, |
| .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
| .gart_set_page = &rv370_pcie_gart_set_page, |
| // .cp_commit = &r100_cp_commit, |
| // .ring_start = &rv515_ring_start, |
| // .ring_test = &r100_ring_test, |
| // .ring_ib_execute = &r100_ring_ib_execute, |
| // .irq_set = &rs600_irq_set, |
| // .irq_process = &rs600_irq_process, |
| // .get_vblank_counter = &rs600_get_vblank_counter, |
| .cp_init = &r100_cp_init, |
| // .cp_fini = &r100_cp_fini, |
| // .cp_disable = &r100_cp_disable, |
| .cp_commit = &r100_cp_commit, |
| .ring_start = &rv515_ring_start, |
| // .irq_set = &r100_irq_set, |
| // .irq_process = &r100_irq_process, |
| // .fence_ring_emit = &r300_fence_ring_emit, |
| // .cs_parse = &r300_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = &r300_copy_dma, |
| // .copy = &r100_copy_blit, |
| .set_engine_clock = &radeon_atom_set_engine_clock, |
| .set_memory_clock = &radeon_atom_set_memory_clock, |
| .set_pcie_lanes = &rv370_set_pcie_lanes, |
| .set_clock_gating = &radeon_atom_set_clock_gating, |
| // .set_engine_clock = &radeon_atom_set_engine_clock, |
| // .set_memory_clock = &radeon_atom_set_memory_clock, |
| // .set_pcie_lanes = &rv370_set_pcie_lanes, |
| // .set_clock_gating = &radeon_atom_set_clock_gating, |
| .set_surface_reg = r100_set_surface_reg, |
| .clear_surface_reg = r100_clear_surface_reg, |
| .bandwidth_update = &rv515_bandwidth_update, |
| .bandwidth_update = &r520_bandwidth_update, |
| }; |
| /* |
| * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 |
| * r600,rv610,rv630,rv620,rv635,rv670,rs780,rv770,rv730,rv710 |
| */ |
| int r600_init(struct radeon_device *rdev); |
| void r600_fini(struct radeon_device *rdev); |
| /drivers/video/drm/radeon/radeon_atombios.c |
|---|
| 272,9 → 272,12 |
| (le16_to_cpu(path->usConnObjectId) & |
| OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; |
| /* TODO CV support */ |
| if (le16_to_cpu(path->usDeviceTag) == |
| ATOM_DEVICE_CV_SUPPORT) |
| if ((le16_to_cpu(path->usDeviceTag) == |
| ATOM_DEVICE_TV1_SUPPORT) |
| || (le16_to_cpu(path->usDeviceTag) == |
| ATOM_DEVICE_TV2_SUPPORT) |
| || (le16_to_cpu(path->usDeviceTag) == |
| ATOM_DEVICE_CV_SUPPORT)) |
| continue; |
| if ((rdev->family == CHIP_RS780) && |
| /drivers/video/drm/radeon/radeon_bios.c |
|---|
| 39,8 → 39,7 |
| size_t size; |
| rdev->bios = NULL; |
| /* XXX: some cards may return 0 for rom size? ddx has a workaround */ |
| bios = pci_map_rom(rdev->pdev, &size); |
| bios = (uint8_t*)pci_map_rom(rdev->pdev, &size); |
| if (!bios) { |
| return false; |
| } |
| /drivers/video/drm/radeon/radeon_clocks.c |
|---|
| 411,7 → 411,7 |
| R300_PIXCLK_TRANS_ALWAYS_ONb | |
| R300_PIXCLK_TVO_ALWAYS_ONb | |
| R300_P2G2CLK_ALWAYS_ONb | |
| R300_P2G2CLK_DAC_ALWAYS_ONb); |
| R300_P2G2CLK_ALWAYS_ONb); |
| WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
| } else if (rdev->family >= CHIP_RV350) { |
| tmp = RREG32_PLL(R300_SCLK_CNTL2); |
| 464,7 → 464,7 |
| R300_PIXCLK_TRANS_ALWAYS_ONb | |
| R300_PIXCLK_TVO_ALWAYS_ONb | |
| R300_P2G2CLK_ALWAYS_ONb | |
| R300_P2G2CLK_DAC_ALWAYS_ONb); |
| R300_P2G2CLK_ALWAYS_ONb); |
| WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
| tmp = RREG32_PLL(RADEON_MCLK_MISC); |
| 654,7 → 654,7 |
| R300_PIXCLK_TRANS_ALWAYS_ONb | |
| R300_PIXCLK_TVO_ALWAYS_ONb | |
| R300_P2G2CLK_ALWAYS_ONb | |
| R300_P2G2CLK_DAC_ALWAYS_ONb | |
| R300_P2G2CLK_ALWAYS_ONb | |
| R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF); |
| WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
| } else if (rdev->family >= CHIP_RV350) { |
| 705,7 → 705,7 |
| R300_PIXCLK_TRANS_ALWAYS_ONb | |
| R300_PIXCLK_TVO_ALWAYS_ONb | |
| R300_P2G2CLK_ALWAYS_ONb | |
| R300_P2G2CLK_DAC_ALWAYS_ONb | |
| R300_P2G2CLK_ALWAYS_ONb | |
| R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF); |
| WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
| } else { |
| /drivers/video/drm/radeon/radeon_combios.c |
|---|
| 745,6 → 745,7 |
| tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); |
| found = 1; |
| } |
| tv_dac->tv_std = radeon_combios_get_tv_info(encoder); |
| } |
| if (!found) { |
| 774,7 → 775,6 |
| DRM_INFO("No TV DAC info found in BIOS\n"); |
| } |
| } |
| out: |
| if (!found) /* fallback to defaults */ |
| radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac); |
| /drivers/video/drm/radeon/radeon_connectors.c |
|---|
| 26,7 → 26,6 |
| #include "drmP.h" |
| #include "drm_edid.h" |
| #include "drm_crtc_helper.h" |
| #include "drm_fb_helper.h" |
| #include "radeon_drm.h" |
| #include "radeon.h" |
| #include "atom.h" |
| 246,7 → 245,7 |
| if (common_modes[i].w < 320 || common_modes[i].h < 200) |
| continue; |
| mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); |
| mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false); |
| drm_mode_probed_add(connector, mode); |
| } |
| } |
| 560,7 → 559,7 |
| radeon_add_common_modes(encoder, connector); |
| else { |
| /* only 800x600 is supported right now on pre-avivo chips */ |
| tv_mode = drm_cvt_mode(dev, 800, 600, 60, false, false, false); |
| tv_mode = drm_cvt_mode(dev, 800, 600, 60, false, false); |
| tv_mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; |
| drm_mode_probed_add(connector, tv_mode); |
| } |
| 744,15 → 743,6 |
| return NULL; |
| } |
| static void radeon_dvi_force(struct drm_connector *connector) |
| { |
| struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| if (connector->force == DRM_FORCE_ON) |
| radeon_connector->use_digital = false; |
| if (connector->force == DRM_FORCE_ON_DIGITAL) |
| radeon_connector->use_digital = true; |
| } |
| struct drm_connector_helper_funcs radeon_dvi_connector_helper_funcs = { |
| .get_modes = radeon_dvi_get_modes, |
| .mode_valid = radeon_vga_mode_valid, |
| 765,7 → 755,6 |
| .fill_modes = drm_helper_probe_single_connector_modes, |
| .set_property = radeon_connector_set_property, |
| .destroy = radeon_connector_destroy, |
| .force = radeon_dvi_force, |
| }; |
| void |
| 782,7 → 771,6 |
| struct radeon_connector *radeon_connector; |
| struct radeon_connector_atom_dig *radeon_dig_connector; |
| uint32_t subpixel_order = SubPixelNone; |
| int ret; |
| /* fixme - tv/cv/din */ |
| if (connector_type == DRM_MODE_CONNECTOR_Unknown) |
| 808,15 → 796,12 |
| switch (connector_type) { |
| case DRM_MODE_CONNECTOR_VGA: |
| drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); |
| ret = drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); |
| if (ret) |
| goto failed; |
| drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); |
| if (i2c_bus->valid) { |
| radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "VGA"); |
| if (!radeon_connector->ddc_bus) |
| goto failed; |
| } |
| radeon_connector->dac_load_detect = true; |
| drm_connector_attach_property(&radeon_connector->base, |
| rdev->mode_info.load_detect_property, |
| 1); |
| 823,15 → 808,12 |
| break; |
| case DRM_MODE_CONNECTOR_DVIA: |
| drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); |
| ret = drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); |
| if (ret) |
| goto failed; |
| drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); |
| if (i2c_bus->valid) { |
| radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI"); |
| if (!radeon_connector->ddc_bus) |
| goto failed; |
| } |
| radeon_connector->dac_load_detect = true; |
| drm_connector_attach_property(&radeon_connector->base, |
| rdev->mode_info.load_detect_property, |
| 1); |
| 845,9 → 827,7 |
| radeon_dig_connector->igp_lane_info = igp_lane_info; |
| radeon_connector->con_priv = radeon_dig_connector; |
| drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); |
| ret = drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); |
| if (ret) |
| goto failed; |
| drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); |
| if (i2c_bus->valid) { |
| radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI"); |
| if (!radeon_connector->ddc_bus) |
| 857,7 → 837,6 |
| drm_connector_attach_property(&radeon_connector->base, |
| rdev->mode_info.coherent_mode_property, |
| 1); |
| radeon_connector->dac_load_detect = true; |
| drm_connector_attach_property(&radeon_connector->base, |
| rdev->mode_info.load_detect_property, |
| 1); |
| 871,9 → 850,7 |
| radeon_dig_connector->igp_lane_info = igp_lane_info; |
| radeon_connector->con_priv = radeon_dig_connector; |
| drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); |
| ret = drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); |
| if (ret) |
| goto failed; |
| drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); |
| if (i2c_bus->valid) { |
| radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "HDMI"); |
| if (!radeon_connector->ddc_bus) |
| 892,9 → 869,7 |
| radeon_dig_connector->igp_lane_info = igp_lane_info; |
| radeon_connector->con_priv = radeon_dig_connector; |
| drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); |
| ret = drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); |
| if (ret) |
| goto failed; |
| drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); |
| if (i2c_bus->valid) { |
| radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DP"); |
| if (!radeon_connector->ddc_bus) |
| 907,14 → 882,11 |
| case DRM_MODE_CONNECTOR_9PinDIN: |
| if (radeon_tv == 1) { |
| drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type); |
| ret = drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs); |
| if (ret) |
| goto failed; |
| radeon_connector->dac_load_detect = true; |
| drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs); |
| } |
| drm_connector_attach_property(&radeon_connector->base, |
| rdev->mode_info.load_detect_property, |
| 1); |
| } |
| break; |
| case DRM_MODE_CONNECTOR_LVDS: |
| radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); |
| 924,9 → 896,7 |
| radeon_dig_connector->igp_lane_info = igp_lane_info; |
| radeon_connector->con_priv = radeon_dig_connector; |
| drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type); |
| ret = drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs); |
| if (ret) |
| goto failed; |
| drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs); |
| if (i2c_bus->valid) { |
| radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "LVDS"); |
| if (!radeon_connector->ddc_bus) |
| 962,7 → 932,6 |
| struct drm_connector *connector; |
| struct radeon_connector *radeon_connector; |
| uint32_t subpixel_order = SubPixelNone; |
| int ret; |
| /* fixme - tv/cv/din */ |
| if (connector_type == DRM_MODE_CONNECTOR_Unknown) |
| 988,15 → 957,12 |
| switch (connector_type) { |
| case DRM_MODE_CONNECTOR_VGA: |
| drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); |
| ret = drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); |
| if (ret) |
| goto failed; |
| drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); |
| if (i2c_bus->valid) { |
| radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "VGA"); |
| if (!radeon_connector->ddc_bus) |
| goto failed; |
| } |
| radeon_connector->dac_load_detect = true; |
| drm_connector_attach_property(&radeon_connector->base, |
| rdev->mode_info.load_detect_property, |
| 1); |
| 1003,15 → 969,12 |
| break; |
| case DRM_MODE_CONNECTOR_DVIA: |
| drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); |
| ret = drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); |
| if (ret) |
| goto failed; |
| drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); |
| if (i2c_bus->valid) { |
| radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI"); |
| if (!radeon_connector->ddc_bus) |
| goto failed; |
| } |
| radeon_connector->dac_load_detect = true; |
| drm_connector_attach_property(&radeon_connector->base, |
| rdev->mode_info.load_detect_property, |
| 1); |
| 1019,14 → 982,11 |
| case DRM_MODE_CONNECTOR_DVII: |
| case DRM_MODE_CONNECTOR_DVID: |
| drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); |
| ret = drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); |
| if (ret) |
| goto failed; |
| drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); |
| if (i2c_bus->valid) { |
| radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI"); |
| if (!radeon_connector->ddc_bus) |
| goto failed; |
| radeon_connector->dac_load_detect = true; |
| drm_connector_attach_property(&radeon_connector->base, |
| rdev->mode_info.load_detect_property, |
| 1); |
| 1038,10 → 998,7 |
| case DRM_MODE_CONNECTOR_9PinDIN: |
| if (radeon_tv == 1) { |
| drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type); |
| ret = drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs); |
| if (ret) |
| goto failed; |
| radeon_connector->dac_load_detect = true; |
| drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs); |
| drm_connector_attach_property(&radeon_connector->base, |
| rdev->mode_info.load_detect_property, |
| 1); |
| 1049,9 → 1006,7 |
| break; |
| case DRM_MODE_CONNECTOR_LVDS: |
| drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type); |
| ret = drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs); |
| if (ret) |
| goto failed; |
| drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs); |
| if (i2c_bus->valid) { |
| radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "LVDS"); |
| if (!radeon_connector->ddc_bus) |
| /drivers/video/drm/radeon/radeon_legacy_crtc.c |
|---|
| 1053,7 → 1053,6 |
| .mode_set_base = radeon_crtc_set_base, |
| .prepare = radeon_crtc_prepare, |
| .commit = radeon_crtc_commit, |
| .load_lut = radeon_crtc_load_lut, |
| }; |
| /drivers/video/drm/radeon/radeon_legacy_encoders.c |
|---|
| 881,7 → 881,7 |
| R420_TV_DAC_DACADJ_MASK | |
| R420_TV_DAC_RDACPD | |
| R420_TV_DAC_GDACPD | |
| R420_TV_DAC_BDACPD | |
| R420_TV_DAC_GDACPD | |
| R420_TV_DAC_TVENABLE); |
| } else { |
| tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK | |
| 889,7 → 889,7 |
| RADEON_TV_DAC_DACADJ_MASK | |
| RADEON_TV_DAC_RDACPD | |
| RADEON_TV_DAC_GDACPD | |
| RADEON_TV_DAC_BDACPD); |
| RADEON_TV_DAC_GDACPD); |
| } |
| /* FIXME TV */ |
| 1318,9 → 1318,6 |
| return; |
| encoder = &radeon_encoder->base; |
| if (rdev->flags & RADEON_SINGLE_CRTC) |
| encoder->possible_crtcs = 0x1; |
| else |
| encoder->possible_crtcs = 0x3; |
| encoder->possible_clones = 0; |
| /drivers/video/drm/radeon/radeon_mode.h |
|---|
| 407,8 → 407,6 |
| radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); |
| extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
| u16 blue, int regno); |
| extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
| u16 *blue, int regno); |
| struct drm_framebuffer *radeon_framebuffer_create(struct drm_device *dev, |
| struct drm_mode_fb_cmd *mode_cmd, |
| struct drm_gem_object *obj); |
| /drivers/video/drm/radeon/radeon_reg.h |
|---|
| 3333,7 → 3333,6 |
| # define RADEON_CP_PACKET_MAX_DWORDS (1 << 12) |
| # define RADEON_CP_PACKET0_REG_MASK 0x000007ff |
| # define R300_CP_PACKET0_REG_MASK 0x00001fff |
| # define R600_CP_PACKET0_REG_MASK 0x0000ffff |
| # define RADEON_CP_PACKET1_REG0_MASK 0x000007ff |
| # define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 |
| /drivers/video/drm/radeon/rs400.c |
|---|
| 27,12 → 27,27 |
| */ |
| #include <linux/seq_file.h> |
| #include <drm/drmP.h> |
| #include "radeon_reg.h" |
| #include "radeon.h" |
| #include "rs400d.h" |
| /* This files gather functions specifics to : rs400,rs480 */ |
| static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev); |
| /* rs400,rs480 depends on : */ |
| void r100_hdp_reset(struct radeon_device *rdev); |
| void r100_mc_disable_clients(struct radeon_device *rdev); |
| int r300_mc_wait_for_idle(struct radeon_device *rdev); |
| void r420_pipes_init(struct radeon_device *rdev); |
| /* This files gather functions specifics to : |
| * rs400,rs480 |
| * |
| * Some of these functions might be used by newer ASICs. |
| */ |
| void rs400_gpu_init(struct radeon_device *rdev); |
| int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev); |
| /* |
| * GART functions. |
| */ |
| void rs400_gart_adjust_size(struct radeon_device *rdev) |
| { |
| /* Check gart size */ |
| 223,6 → 238,61 |
| return 0; |
| } |
| /* |
| * MC functions. |
| */ |
| int rs400_mc_init(struct radeon_device *rdev) |
| { |
| uint32_t tmp; |
| int r; |
| if (r100_debugfs_rbbm_init(rdev)) { |
| DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
| } |
| rs400_gpu_init(rdev); |
| rs400_gart_disable(rdev); |
| rdev->mc.gtt_location = rdev->mc.mc_vram_size; |
| rdev->mc.gtt_location += (rdev->mc.gtt_size - 1); |
| rdev->mc.gtt_location &= ~(rdev->mc.gtt_size - 1); |
| r = radeon_mc_setup(rdev); |
| if (r) { |
| return r; |
| } |
| r100_mc_disable_clients(rdev); |
| if (r300_mc_wait_for_idle(rdev)) { |
| printk(KERN_WARNING "Failed to wait MC idle while " |
| "programming pipes. Bad things might happen.\n"); |
| } |
| tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
| tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16); |
| tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16); |
| WREG32(RADEON_MC_FB_LOCATION, tmp); |
| tmp = RREG32(RADEON_HOST_PATH_CNTL) | RADEON_HP_LIN_RD_CACHE_DIS; |
| WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE); |
| (void)RREG32(RADEON_HOST_PATH_CNTL); |
| WREG32(RADEON_HOST_PATH_CNTL, tmp); |
| (void)RREG32(RADEON_HOST_PATH_CNTL); |
| return 0; |
| } |
| void rs400_mc_fini(struct radeon_device *rdev) |
| { |
| } |
| /* |
| * Global GPU functions |
| */ |
| void rs400_errata(struct radeon_device *rdev) |
| { |
| rdev->pll_errata = 0; |
| } |
| void rs400_gpu_init(struct radeon_device *rdev) |
| { |
| /* FIXME: HDP same place on rs400 ? */ |
| 235,6 → 305,10 |
| } |
| } |
| /* |
| * VRAM info. |
| */ |
| void rs400_vram_info(struct radeon_device *rdev) |
| { |
| rs400_gart_adjust_size(rdev); |
| 245,6 → 319,10 |
| r100_vram_init_sizes(rdev); |
| } |
| /* |
| * Indirect registers accessor |
| */ |
| uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
| { |
| uint32_t r; |
| 262,6 → 340,10 |
| WREG32(RS480_NB_MC_INDEX, 0xff); |
| } |
| /* |
| * Debugfs info |
| */ |
| #if defined(CONFIG_DEBUG_FS) |
| static int rs400_debugfs_gart_info(struct seq_file *m, void *data) |
| { |
| 337,7 → 419,7 |
| }; |
| #endif |
| static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev) |
| int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev) |
| { |
| #if defined(CONFIG_DEBUG_FS) |
| return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1); |
| 345,147 → 427,3 |
| return 0; |
| #endif |
| } |
| static int rs400_mc_init(struct radeon_device *rdev) |
| { |
| int r; |
| u32 tmp; |
| /* Setup GPU memory space */ |
| tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM)); |
| rdev->mc.vram_location = G_00015C_MC_FB_START(tmp) << 16; |
| rdev->mc.gtt_location = 0xFFFFFFFFUL; |
| r = radeon_mc_setup(rdev); |
| if (r) |
| return r; |
| return 0; |
| } |
| void rs400_mc_program(struct radeon_device *rdev) |
| { |
| struct r100_mc_save save; |
| /* Stops all mc clients */ |
| r100_mc_stop(rdev, &save); |
| /* Wait for mc idle */ |
| if (r300_mc_wait_for_idle(rdev)) |
| dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
| WREG32(R_000148_MC_FB_LOCATION, |
| S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | |
| S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
| r100_mc_resume(rdev, &save); |
| } |
| static int rs400_startup(struct radeon_device *rdev) |
| { |
| int r; |
| rs400_mc_program(rdev); |
| /* Resume clock */ |
| r300_clock_startup(rdev); |
| /* Initialize GPU configuration (# pipes, ...) */ |
| rs400_gpu_init(rdev); |
| /* Initialize GART (initialize after TTM so we can allocate |
| * memory through TTM but finalize after TTM) */ |
| r = rs400_gart_enable(rdev); |
| if (r) |
| return r; |
| /* Enable IRQ */ |
| // rdev->irq.sw_int = true; |
| // r100_irq_set(rdev); |
| /* 1M ring buffer */ |
| // r = r100_cp_init(rdev, 1024 * 1024); |
| // if (r) { |
| // dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
| // return r; |
| // } |
| // r = r100_wb_init(rdev); |
| // if (r) |
| // dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
| // r = r100_ib_init(rdev); |
| // if (r) { |
| // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
| // return r; |
| // } |
| return 0; |
| } |
| int rs400_init(struct radeon_device *rdev) |
| { |
| int r; |
| /* Disable VGA */ |
| r100_vga_render_disable(rdev); |
| /* Initialize scratch registers */ |
| radeon_scratch_init(rdev); |
| /* Initialize surface registers */ |
| radeon_surface_init(rdev); |
| /* TODO: disable VGA need to use VGA request */ |
| /* BIOS*/ |
| if (!radeon_get_bios(rdev)) { |
| if (ASIC_IS_AVIVO(rdev)) |
| return -EINVAL; |
| } |
| if (rdev->is_atom_bios) { |
| dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); |
| return -EINVAL; |
| } else { |
| r = radeon_combios_init(rdev); |
| if (r) |
| return r; |
| } |
| /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
| if (radeon_gpu_reset(rdev)) { |
| dev_warn(rdev->dev, |
| "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
| RREG32(R_000E40_RBBM_STATUS), |
| RREG32(R_0007C0_CP_STAT)); |
| } |
| /* check if cards are posted or not */ |
| if (!radeon_card_posted(rdev) && rdev->bios) { |
| DRM_INFO("GPU not posted. posting now...\n"); |
| radeon_combios_asic_init(rdev->ddev); |
| } |
| /* Initialize clocks */ |
| radeon_get_clock_info(rdev->ddev); |
| /* Get vram informations */ |
| rs400_vram_info(rdev); |
| /* Initialize memory controller (also test AGP) */ |
| r = rs400_mc_init(rdev); |
| if (r) |
| return r; |
| /* Fence driver */ |
| // r = radeon_fence_driver_init(rdev); |
| // if (r) |
| // return r; |
| // r = radeon_irq_kms_init(rdev); |
| // if (r) |
| // return r; |
| /* Memory manager */ |
| r = radeon_object_init(rdev); |
| if (r) |
| return r; |
| r = rs400_gart_init(rdev); |
| if (r) |
| return r; |
| r300_set_reg_safe(rdev); |
| rdev->accel_working = true; |
| r = rs400_startup(rdev); |
| if (r) { |
| /* Somethings want wront with the accel init stop accel */ |
| dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
| // rs400_suspend(rdev); |
| // r100_cp_fini(rdev); |
| // r100_wb_fini(rdev); |
| // r100_ib_fini(rdev); |
| rs400_gart_fini(rdev); |
| // radeon_irq_kms_fini(rdev); |
| rdev->accel_working = false; |
| } |
| return 0; |
| } |
| /drivers/video/drm/radeon/rs600.c |
|---|
| 25,26 → 25,29 |
| * Alex Deucher |
| * Jerome Glisse |
| */ |
| /* RS600 / Radeon X1250/X1270 integrated GPU |
| * |
| * This file gather function specific to RS600 which is the IGP of |
| * the X1250/X1270 family supporting intel CPU (while RS690/RS740 |
| * is the X1250/X1270 supporting AMD CPU). The display engine are |
| * the avivo one, bios is an atombios, 3D block are the one of the |
| * R4XX family. The GART is different from the RS400 one and is very |
| * close to the one of the R600 family (R600 likely being an evolution |
| * of the RS600 GART block). |
| */ |
| #include "drmP.h" |
| #include "radeon_reg.h" |
| #include "radeon.h" |
| #include "atom.h" |
| #include "rs600d.h" |
| #include "avivod.h" |
| #include "rs600_reg_safe.h" |
| /* rs600 depends on : */ |
| void r100_hdp_reset(struct radeon_device *rdev); |
| int r100_gui_wait_for_idle(struct radeon_device *rdev); |
| int r300_mc_wait_for_idle(struct radeon_device *rdev); |
| void r420_pipes_init(struct radeon_device *rdev); |
| /* This files gather functions specifics to : |
| * rs600 |
| * |
| * Some of these functions might be used by newer ASICs. |
| */ |
| void rs600_gpu_init(struct radeon_device *rdev); |
| int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
| void rs600_disable_vga(struct radeon_device *rdev); |
| /* |
| * GART. |
| */ |
| 52,28 → 55,26 |
| { |
| uint32_t tmp; |
| tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
| tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; |
| WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
| tmp = RREG32_MC(RS600_MC_PT0_CNTL); |
| tmp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE); |
| WREG32_MC(RS600_MC_PT0_CNTL, tmp); |
| tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
| tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1); |
| WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
| tmp = RREG32_MC(RS600_MC_PT0_CNTL); |
| tmp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE; |
| WREG32_MC(RS600_MC_PT0_CNTL, tmp); |
| tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
| tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; |
| WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
| tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
| tmp = RREG32_MC(RS600_MC_PT0_CNTL); |
| tmp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE); |
| WREG32_MC(RS600_MC_PT0_CNTL, tmp); |
| tmp = RREG32_MC(RS600_MC_PT0_CNTL); |
| } |
| int rs600_gart_init(struct radeon_device *rdev) |
| int rs600_gart_enable(struct radeon_device *rdev) |
| { |
| uint32_t tmp; |
| int i; |
| int r; |
| if (rdev->gart.table.vram.robj) { |
| WARN(1, "RS600 GART already initialized.\n"); |
| return 0; |
| } |
| /* Initialize common gart structure */ |
| r = radeon_gart_init(rdev); |
| if (r) { |
| 80,65 → 81,50 |
| return r; |
| } |
| rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; |
| return radeon_gart_table_vram_alloc(rdev); |
| r = radeon_gart_table_vram_alloc(rdev); |
| if (r) { |
| return r; |
| } |
| int rs600_gart_enable(struct radeon_device *rdev) |
| { |
| u32 tmp; |
| int r, i; |
| if (rdev->gart.table.vram.robj == NULL) { |
| dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
| return -EINVAL; |
| } |
| r = radeon_gart_table_vram_pin(rdev); |
| if (r) |
| return r; |
| /* Enable bus master */ |
| tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS; |
| WREG32(R_00004C_BUS_CNTL, tmp); |
| /* FIXME: setup default page */ |
| WREG32_MC(R_000100_MC_PT0_CNTL, |
| (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | |
| S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); |
| WREG32_MC(RS600_MC_PT0_CNTL, |
| (RS600_EFFECTIVE_L2_CACHE_SIZE(6) | |
| RS600_EFFECTIVE_L2_QUEUE_SIZE(6))); |
| for (i = 0; i < 19; i++) { |
| WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, |
| S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | |
| S_00016C_SYSTEM_ACCESS_MODE_MASK( |
| V_00016C_SYSTEM_ACCESS_MODE_IN_SYS) | |
| S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( |
| V_00016C_SYSTEM_APERTURE_UNMAPPED_DEFAULT_PAGE) | |
| S_00016C_EFFECTIVE_L1_CACHE_SIZE(1) | |
| S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | |
| S_00016C_EFFECTIVE_L1_QUEUE_SIZE(1)); |
| WREG32_MC(RS600_MC_PT0_CLIENT0_CNTL + i, |
| (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE | |
| RS600_SYSTEM_ACCESS_MODE_IN_SYS | |
| RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE | |
| RS600_EFFECTIVE_L1_CACHE_SIZE(3) | |
| RS600_ENABLE_FRAGMENT_PROCESSING | |
| RS600_EFFECTIVE_L1_QUEUE_SIZE(3))); |
| } |
| /* System context map to GART space */ |
| WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.gtt_start); |
| WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.gtt_end); |
| WREG32_MC(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.gtt_location); |
| tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
| WREG32_MC(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, tmp); |
| /* enable first context */ |
| WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); |
| WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); |
| WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, |
| S_000102_ENABLE_PAGE_TABLE(1) | |
| S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); |
| WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_location); |
| tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
| WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR, tmp); |
| WREG32_MC(RS600_MC_PT0_CONTEXT0_CNTL, |
| (RS600_ENABLE_PAGE_TABLE | RS600_PAGE_TABLE_TYPE_FLAT)); |
| /* disable all other contexts */ |
| for (i = 1; i < 8; i++) { |
| WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); |
| WREG32_MC(RS600_MC_PT0_CONTEXT0_CNTL + i, 0); |
| } |
| /* setup the page table */ |
| WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, |
| WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, |
| rdev->gart.table_addr); |
| WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); |
| WREG32_MC(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); |
| /* enable page tables */ |
| tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
| WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); |
| tmp = RREG32_MC(R_000009_MC_CNTL1); |
| WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); |
| tmp = RREG32_MC(RS600_MC_PT0_CNTL); |
| WREG32_MC(RS600_MC_PT0_CNTL, (tmp | RS600_ENABLE_PT)); |
| tmp = RREG32_MC(RS600_MC_CNTL1); |
| WREG32_MC(RS600_MC_CNTL1, (tmp | RS600_ENABLE_PAGE_TABLES)); |
| rs600_gart_tlb_flush(rdev); |
| rdev->gart.ready = true; |
| return 0; |
| 149,22 → 135,14 |
| uint32_t tmp; |
| /* FIXME: disable out of gart access */ |
| WREG32_MC(R_000100_MC_PT0_CNTL, 0); |
| tmp = RREG32_MC(R_000009_MC_CNTL1); |
| WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); |
| if (rdev->gart.table.vram.robj) { |
| WREG32_MC(RS600_MC_PT0_CNTL, 0); |
| tmp = RREG32_MC(RS600_MC_CNTL1); |
| tmp &= ~RS600_ENABLE_PAGE_TABLES; |
| WREG32_MC(RS600_MC_CNTL1, tmp); |
| // radeon_object_kunmap(rdev->gart.table.vram.robj); |
| // radeon_object_unpin(rdev->gart.table.vram.robj); |
| } |
| } |
| void rs600_gart_fini(struct radeon_device *rdev) |
| { |
| rs600_gart_disable(rdev); |
| radeon_gart_table_vram_free(rdev); |
| radeon_gart_fini(rdev); |
| } |
| #define R600_PTE_VALID (1 << 0) |
| #define R600_PTE_SYSTEM (1 << 1) |
| #define R600_PTE_SNOOPED (1 << 2) |
| 186,75 → 164,139 |
| } |
| static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int) |
| /* |
| * MC. |
| */ |
| void rs600_mc_disable_clients(struct radeon_device *rdev) |
| { |
| uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); |
| uint32_t irq_mask = ~C_000044_SW_INT; |
| unsigned tmp; |
| if (G_000044_DISPLAY_INT_STAT(irqs)) { |
| *r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); |
| if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) { |
| WREG32(R_006534_D1MODE_VBLANK_STATUS, |
| S_006534_D1MODE_VBLANK_ACK(1)); |
| if (r100_gui_wait_for_idle(rdev)) { |
| printk(KERN_WARNING "Failed to wait GUI idle while " |
| "programming pipes. Bad things might happen.\n"); |
| } |
| if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) { |
| WREG32(R_006D34_D2MODE_VBLANK_STATUS, |
| S_006D34_D2MODE_VBLANK_ACK(1)); |
| tmp = RREG32(AVIVO_D1VGA_CONTROL); |
| WREG32(AVIVO_D1VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); |
| tmp = RREG32(AVIVO_D2VGA_CONTROL); |
| WREG32(AVIVO_D2VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); |
| tmp = RREG32(AVIVO_D1CRTC_CONTROL); |
| WREG32(AVIVO_D1CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN); |
| tmp = RREG32(AVIVO_D2CRTC_CONTROL); |
| WREG32(AVIVO_D2CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN); |
| /* make sure all previous write got through */ |
| tmp = RREG32(AVIVO_D2CRTC_CONTROL); |
| mdelay(1); |
| } |
| } else { |
| *r500_disp_int = 0; |
| int rs600_mc_init(struct radeon_device *rdev) |
| { |
| uint32_t tmp; |
| int r; |
| if (r100_debugfs_rbbm_init(rdev)) { |
| DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
| } |
| if (irqs) { |
| WREG32(R_000044_GEN_INT_STATUS, irqs); |
| rs600_gpu_init(rdev); |
| rs600_gart_disable(rdev); |
| /* Setup GPU memory space */ |
| rdev->mc.vram_location = 0xFFFFFFFFUL; |
| rdev->mc.gtt_location = 0xFFFFFFFFUL; |
| r = radeon_mc_setup(rdev); |
| if (r) { |
| return r; |
| } |
| return irqs & irq_mask; |
| /* Program GPU memory space */ |
| /* Enable bus master */ |
| tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; |
| WREG32(RADEON_BUS_CNTL, tmp); |
| /* FIXME: What does AGP means for such chipset ? */ |
| WREG32_MC(RS600_MC_AGP_LOCATION, 0x0FFFFFFF); |
| /* FIXME: are this AGP reg in indirect MC range ? */ |
| WREG32_MC(RS600_MC_AGP_BASE, 0); |
| WREG32_MC(RS600_MC_AGP_BASE_2, 0); |
| rs600_mc_disable_clients(rdev); |
| if (rs600_mc_wait_for_idle(rdev)) { |
| printk(KERN_WARNING "Failed to wait MC idle while " |
| "programming pipes. Bad things might happen.\n"); |
| } |
| tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
| tmp = REG_SET(RS600_MC_FB_TOP, tmp >> 16); |
| tmp |= REG_SET(RS600_MC_FB_START, rdev->mc.vram_location >> 16); |
| WREG32_MC(RS600_MC_FB_LOCATION, tmp); |
| WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16); |
| return 0; |
| } |
| void rs600_irq_disable(struct radeon_device *rdev) |
| void rs600_mc_fini(struct radeon_device *rdev) |
| { |
| u32 tmp; |
| WREG32(R_000040_GEN_INT_CNTL, 0); |
| WREG32(R_006540_DxMODE_INT_MASK, 0); |
| /* Wait and acknowledge irq */ |
| mdelay(1); |
| rs600_irq_ack(rdev, &tmp); |
| rs600_gart_disable(rdev); |
| radeon_gart_table_vram_free(rdev); |
| radeon_gart_fini(rdev); |
| } |
| u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) |
| /* |
| * Global GPU functions |
| */ |
| void rs600_disable_vga(struct radeon_device *rdev) |
| { |
| if (crtc == 0) |
| return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); |
| else |
| return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); |
| unsigned tmp; |
| WREG32(0x330, 0); |
| WREG32(0x338, 0); |
| tmp = RREG32(0x300); |
| tmp &= ~(3 << 16); |
| WREG32(0x300, tmp); |
| WREG32(0x308, (1 << 8)); |
| WREG32(0x310, rdev->mc.vram_location); |
| WREG32(0x594, 0); |
| } |
| int rs600_mc_wait_for_idle(struct radeon_device *rdev) |
| { |
| unsigned i; |
| uint32_t tmp; |
| for (i = 0; i < rdev->usec_timeout; i++) { |
| if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) |
| /* read MC_STATUS */ |
| tmp = RREG32_MC(RS600_MC_STATUS); |
| if (tmp & RS600_MC_STATUS_IDLE) { |
| return 0; |
| udelay(1); |
| } |
| DRM_UDELAY(1); |
| } |
| return -1; |
| } |
| void rs600_errata(struct radeon_device *rdev) |
| { |
| rdev->pll_errata = 0; |
| } |
| void rs600_gpu_init(struct radeon_device *rdev) |
| { |
| /* FIXME: HDP same place on rs600 ? */ |
| r100_hdp_reset(rdev); |
| rs600_disable_vga(rdev); |
| /* FIXME: is this correct ? */ |
| r420_pipes_init(rdev); |
| /* Wait for mc idle */ |
| if (rs600_mc_wait_for_idle(rdev)) |
| dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
| if (rs600_mc_wait_for_idle(rdev)) { |
| printk(KERN_WARNING "Failed to wait MC idle while " |
| "programming pipes. Bad things might happen.\n"); |
| } |
| } |
| /* |
| * VRAM info. |
| */ |
| void rs600_vram_info(struct radeon_device *rdev) |
| { |
| /* FIXME: to do or is these values sane ? */ |
| 267,164 → 309,24 |
| /* FIXME: implement, should this be like rs690 ? */ |
| } |
| /* |
| * Indirect registers accessor |
| */ |
| uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
| { |
| WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
| S_000070_MC_IND_CITF_ARB0(1)); |
| return RREG32(R_000074_MC_IND_DATA); |
| } |
| uint32_t r; |
| void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| { |
| WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
| S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); |
| WREG32(R_000074_MC_IND_DATA, v); |
| } |
| void rs600_debugfs(struct radeon_device *rdev) |
| { |
| if (r100_debugfs_rbbm_init(rdev)) |
| DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
| } |
| void rs600_set_safe_registers(struct radeon_device *rdev) |
| { |
| rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; |
| rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); |
| } |
| static void rs600_mc_program(struct radeon_device *rdev) |
| { |
| struct rv515_mc_save save; |
| /* Stops all mc clients */ |
| rv515_mc_stop(rdev, &save); |
| /* Wait for mc idle */ |
| if (rs600_mc_wait_for_idle(rdev)) |
| dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
| /* FIXME: What does AGP means for such chipset ? */ |
| WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); |
| WREG32_MC(R_000006_AGP_BASE, 0); |
| WREG32_MC(R_000007_AGP_BASE_2, 0); |
| /* Program MC */ |
| WREG32_MC(R_000004_MC_FB_LOCATION, |
| S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | |
| S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
| WREG32(R_000134_HDP_FB_LOCATION, |
| S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); |
| rv515_mc_resume(rdev, &save); |
| } |
| static int rs600_startup(struct radeon_device *rdev) |
| { |
| int r; |
| rs600_mc_program(rdev); |
| /* Resume clock */ |
| rv515_clock_startup(rdev); |
| /* Initialize GPU configuration (# pipes, ...) */ |
| rs600_gpu_init(rdev); |
| /* Initialize GART (initialize after TTM so we can allocate |
| * memory through TTM but finalize after TTM) */ |
| r = rs600_gart_enable(rdev); |
| if (r) |
| WREG32(RS600_MC_INDEX, |
| ((reg & RS600_MC_ADDR_MASK) | RS600_MC_IND_CITF_ARB0)); |
| r = RREG32(RS600_MC_DATA); |
| return r; |
| /* Enable IRQ */ |
| // rdev->irq.sw_int = true; |
| // rs600_irq_set(rdev); |
| /* 1M ring buffer */ |
| // r = r100_cp_init(rdev, 1024 * 1024); |
| // if (r) { |
| // dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
| // return r; |
| // } |
| // r = r100_wb_init(rdev); |
| // if (r) |
| // dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
| // r = r100_ib_init(rdev); |
| // if (r) { |
| // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
| // return r; |
| // } |
| return 0; |
| } |
| int rs600_init(struct radeon_device *rdev) |
| void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| { |
| int r; |
| /* Disable VGA */ |
| rv515_vga_render_disable(rdev); |
| /* Initialize scratch registers */ |
| radeon_scratch_init(rdev); |
| /* Initialize surface registers */ |
| radeon_surface_init(rdev); |
| /* BIOS */ |
| if (!radeon_get_bios(rdev)) { |
| if (ASIC_IS_AVIVO(rdev)) |
| return -EINVAL; |
| WREG32(RS600_MC_INDEX, |
| RS600_MC_IND_WR_EN | RS600_MC_IND_CITF_ARB0 | |
| ((reg) & RS600_MC_ADDR_MASK)); |
| WREG32(RS600_MC_DATA, v); |
| } |
| if (rdev->is_atom_bios) { |
| r = radeon_atombios_init(rdev); |
| if (r) |
| return r; |
| } else { |
| dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); |
| return -EINVAL; |
| } |
| /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
| if (radeon_gpu_reset(rdev)) { |
| dev_warn(rdev->dev, |
| "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
| RREG32(R_000E40_RBBM_STATUS), |
| RREG32(R_0007C0_CP_STAT)); |
| } |
| /* check if cards are posted or not */ |
| if (!radeon_card_posted(rdev) && rdev->bios) { |
| DRM_INFO("GPU not posted. posting now...\n"); |
| atom_asic_init(rdev->mode_info.atom_context); |
| } |
| /* Initialize clocks */ |
| radeon_get_clock_info(rdev->ddev); |
| /* Get vram informations */ |
| rs600_vram_info(rdev); |
| /* Initialize memory controller (also test AGP) */ |
| r = r420_mc_init(rdev); |
| if (r) |
| return r; |
| rs600_debugfs(rdev); |
| /* Fence driver */ |
| // r = radeon_fence_driver_init(rdev); |
| // if (r) |
| // return r; |
| // r = radeon_irq_kms_init(rdev); |
| // if (r) |
| // return r; |
| /* Memory manager */ |
| r = radeon_object_init(rdev); |
| if (r) |
| return r; |
| r = rs600_gart_init(rdev); |
| if (r) |
| return r; |
| rs600_set_safe_registers(rdev); |
| rdev->accel_working = true; |
| r = rs600_startup(rdev); |
| if (r) { |
| /* Somethings want wront with the accel init stop accel */ |
| dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
| // rs600_suspend(rdev); |
| // r100_cp_fini(rdev); |
| // r100_wb_fini(rdev); |
| // r100_ib_fini(rdev); |
| rs600_gart_fini(rdev); |
| // radeon_irq_kms_fini(rdev); |
| rdev->accel_working = false; |
| } |
| return 0; |
| } |
| /drivers/video/drm/radeon/rs690.c |
|---|
| 26,29 → 26,106 |
| * Jerome Glisse |
| */ |
| #include "drmP.h" |
| #include "radeon_reg.h" |
| #include "radeon.h" |
| #include "rs690r.h" |
| #include "atom.h" |
| #include "rs690d.h" |
| #include "atom-bits.h" |
| static int rs690_mc_wait_for_idle(struct radeon_device *rdev) |
| /* rs690,rs740 depends on : */ |
| void r100_hdp_reset(struct radeon_device *rdev); |
| int r300_mc_wait_for_idle(struct radeon_device *rdev); |
| void r420_pipes_init(struct radeon_device *rdev); |
| void rs400_gart_disable(struct radeon_device *rdev); |
| int rs400_gart_enable(struct radeon_device *rdev); |
| void rs400_gart_adjust_size(struct radeon_device *rdev); |
| void rs600_mc_disable_clients(struct radeon_device *rdev); |
| void rs600_disable_vga(struct radeon_device *rdev); |
| /* This files gather functions specifics to : |
| * rs690,rs740 |
| * |
| * Some of these functions might be used by newer ASICs. |
| */ |
| void rs690_gpu_init(struct radeon_device *rdev); |
| int rs690_mc_wait_for_idle(struct radeon_device *rdev); |
| /* |
| * MC functions. |
| */ |
| int rs690_mc_init(struct radeon_device *rdev) |
| { |
| uint32_t tmp; |
| int r; |
| if (r100_debugfs_rbbm_init(rdev)) { |
| DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
| } |
| rs690_gpu_init(rdev); |
| rs400_gart_disable(rdev); |
| /* Setup GPU memory space */ |
| rdev->mc.gtt_location = rdev->mc.mc_vram_size; |
| rdev->mc.gtt_location += (rdev->mc.gtt_size - 1); |
| rdev->mc.gtt_location &= ~(rdev->mc.gtt_size - 1); |
| rdev->mc.vram_location = 0xFFFFFFFFUL; |
| r = radeon_mc_setup(rdev); |
| if (r) { |
| return r; |
| } |
| /* Program GPU memory space */ |
| rs600_mc_disable_clients(rdev); |
| if (rs690_mc_wait_for_idle(rdev)) { |
| printk(KERN_WARNING "Failed to wait MC idle while " |
| "programming pipes. Bad things might happen.\n"); |
| } |
| tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
| tmp = REG_SET(RS690_MC_FB_TOP, tmp >> 16); |
| tmp |= REG_SET(RS690_MC_FB_START, rdev->mc.vram_location >> 16); |
| WREG32_MC(RS690_MCCFG_FB_LOCATION, tmp); |
| /* FIXME: Does this reg exist on RS480,RS740 ? */ |
| WREG32(0x310, rdev->mc.vram_location); |
| WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16); |
| return 0; |
| } |
| void rs690_mc_fini(struct radeon_device *rdev) |
| { |
| } |
| /* |
| * Global GPU functions |
| */ |
| int rs690_mc_wait_for_idle(struct radeon_device *rdev) |
| { |
| unsigned i; |
| uint32_t tmp; |
| for (i = 0; i < rdev->usec_timeout; i++) { |
| /* read MC_STATUS */ |
| tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS); |
| if (G_000090_MC_SYSTEM_IDLE(tmp)) |
| tmp = RREG32_MC(RS690_MC_STATUS); |
| if (tmp & RS690_MC_STATUS_IDLE) { |
| return 0; |
| udelay(1); |
| } |
| DRM_UDELAY(1); |
| } |
| return -1; |
| } |
| static void rs690_gpu_init(struct radeon_device *rdev) |
| void rs690_errata(struct radeon_device *rdev) |
| { |
| rdev->pll_errata = 0; |
| } |
| void rs690_gpu_init(struct radeon_device *rdev) |
| { |
| /* FIXME: HDP same place on rs690 ? */ |
| r100_hdp_reset(rdev); |
| rs600_disable_vga(rdev); |
| /* FIXME: is this correct ? */ |
| r420_pipes_init(rdev); |
| if (rs690_mc_wait_for_idle(rdev)) { |
| 57,6 → 134,10 |
| } |
| } |
| /* |
| * VRAM info. |
| */ |
| void rs690_pm_info(struct radeon_device *rdev) |
| { |
| int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); |
| 170,7 → 251,7 |
| /* |
| * Line Buffer Setup |
| * There is a single line buffer shared by both display controllers. |
| * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between |
| * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between |
| * the display controllers. The paritioning can either be done |
| * manually or via one of four preset allocations specified in bits 1:0: |
| * 0 - line buffer is divided in half and shared between crtc |
| 177,32 → 258,32 |
| * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4 |
| * 2 - D1 gets the whole buffer |
| * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4 |
| * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual |
| * Setting bit 2 of DC_LB_MEMORY_SPLIT controls switches to manual |
| * allocation mode. In manual allocation mode, D1 always starts at 0, |
| * D1 end/2 is specified in bits 14:4; D2 allocation follows D1. |
| */ |
| tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT; |
| tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE; |
| tmp = RREG32(DC_LB_MEMORY_SPLIT) & ~DC_LB_MEMORY_SPLIT_MASK; |
| tmp &= ~DC_LB_MEMORY_SPLIT_SHIFT_MODE; |
| /* auto */ |
| if (mode1 && mode2) { |
| if (mode1->hdisplay > mode2->hdisplay) { |
| if (mode1->hdisplay > 2560) |
| tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q; |
| tmp |= DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q; |
| else |
| tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; |
| tmp |= DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; |
| } else if (mode2->hdisplay > mode1->hdisplay) { |
| if (mode2->hdisplay > 2560) |
| tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; |
| tmp |= DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; |
| else |
| tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; |
| tmp |= DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; |
| } else |
| tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; |
| tmp |= AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; |
| } else if (mode1) { |
| tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY; |
| tmp |= DC_LB_MEMORY_SPLIT_D1_ONLY; |
| } else if (mode2) { |
| tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; |
| tmp |= DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; |
| } |
| WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp); |
| WREG32(DC_LB_MEMORY_SPLIT, tmp); |
| } |
| struct rs690_watermark { |
| 407,21 → 488,21 |
| * option. |
| */ |
| if (rdev->disp_priority == 2) { |
| tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER); |
| tmp &= C_000104_MC_DISP0R_INIT_LAT; |
| tmp &= C_000104_MC_DISP1R_INIT_LAT; |
| tmp = RREG32_MC(MC_INIT_MISC_LAT_TIMER); |
| tmp &= ~MC_DISP1R_INIT_LAT_MASK; |
| tmp &= ~MC_DISP0R_INIT_LAT_MASK; |
| if (mode1) |
| tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT); |
| if (mode0) |
| tmp |= S_000104_MC_DISP0R_INIT_LAT(1); |
| if (mode1) |
| tmp |= S_000104_MC_DISP1R_INIT_LAT(1); |
| WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp); |
| tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT); |
| WREG32_MC(MC_INIT_MISC_LAT_TIMER, tmp); |
| } |
| rs690_line_buffer_adjust(rdev, mode0, mode1); |
| if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) |
| WREG32(R_006C9C_DCP_CONTROL, 0); |
| WREG32(DCP_CONTROL, 0); |
| if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) |
| WREG32(R_006C9C_DCP_CONTROL, 2); |
| WREG32(DCP_CONTROL, 2); |
| rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0); |
| rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1); |
| 428,7 → 509,7 |
| tmp = (wm0.lb_request_fifo_depth - 1); |
| tmp |= (wm1.lb_request_fifo_depth - 1) << 16; |
| WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp); |
| WREG32(LB_MAX_REQ_OUTSTANDING, tmp); |
| if (mode0 && mode1) { |
| if (rfixed_trunc(wm0.dbpp) > 64) |
| 481,10 → 562,10 |
| priority_mark12.full = 0; |
| if (wm1.priority_mark_max.full > priority_mark12.full) |
| priority_mark12.full = wm1.priority_mark_max.full; |
| WREG32(R_006548_D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); |
| WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); |
| WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); |
| WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); |
| WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); |
| WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); |
| WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); |
| WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); |
| } else if (mode0) { |
| if (rfixed_trunc(wm0.dbpp) > 64) |
| a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair); |
| 511,12 → 592,10 |
| priority_mark02.full = 0; |
| if (wm0.priority_mark_max.full > priority_mark02.full) |
| priority_mark02.full = wm0.priority_mark_max.full; |
| WREG32(R_006548_D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); |
| WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); |
| WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, |
| S_006D48_D2MODE_PRIORITY_A_OFF(1)); |
| WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, |
| S_006D4C_D2MODE_PRIORITY_B_OFF(1)); |
| WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); |
| WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); |
| WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); |
| WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); |
| } else { |
| if (rfixed_trunc(wm1.dbpp) > 64) |
| a.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair); |
| 543,162 → 622,30 |
| priority_mark12.full = 0; |
| if (wm1.priority_mark_max.full > priority_mark12.full) |
| priority_mark12.full = wm1.priority_mark_max.full; |
| WREG32(R_006548_D1MODE_PRIORITY_A_CNT, |
| S_006548_D1MODE_PRIORITY_A_OFF(1)); |
| WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, |
| S_00654C_D1MODE_PRIORITY_B_OFF(1)); |
| WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); |
| WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); |
| WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); |
| WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); |
| WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); |
| WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); |
| } |
| } |
| /* |
| * Indirect registers accessor |
| */ |
| uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
| { |
| uint32_t r; |
| WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg)); |
| r = RREG32(R_00007C_MC_DATA); |
| WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR); |
| WREG32(RS690_MC_INDEX, (reg & RS690_MC_INDEX_MASK)); |
| r = RREG32(RS690_MC_DATA); |
| WREG32(RS690_MC_INDEX, RS690_MC_INDEX_MASK); |
| return r; |
| } |
| void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| { |
| WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) | |
| S_000078_MC_IND_WR_EN(1)); |
| WREG32(R_00007C_MC_DATA, v); |
| WREG32(R_000078_MC_INDEX, 0x7F); |
| WREG32(RS690_MC_INDEX, |
| RS690_MC_INDEX_WR_EN | ((reg) & RS690_MC_INDEX_MASK)); |
| WREG32(RS690_MC_DATA, v); |
| WREG32(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); |
| } |
| void rs690_mc_program(struct radeon_device *rdev) |
| { |
| struct rv515_mc_save save; |
| /* Stops all mc clients */ |
| rv515_mc_stop(rdev, &save); |
| /* Wait for mc idle */ |
| if (rs690_mc_wait_for_idle(rdev)) |
| dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
| /* Program MC, should be a 32bits limited address space */ |
| WREG32_MC(R_000100_MCCFG_FB_LOCATION, |
| S_000100_MC_FB_START(rdev->mc.vram_start >> 16) | |
| S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
| WREG32(R_000134_HDP_FB_LOCATION, |
| S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); |
| rv515_mc_resume(rdev, &save); |
| } |
| static int rs690_startup(struct radeon_device *rdev) |
| { |
| int r; |
| rs690_mc_program(rdev); |
| /* Resume clock */ |
| rv515_clock_startup(rdev); |
| /* Initialize GPU configuration (# pipes, ...) */ |
| rs690_gpu_init(rdev); |
| /* Initialize GART (initialize after TTM so we can allocate |
| * memory through TTM but finalize after TTM) */ |
| r = rs400_gart_enable(rdev); |
| if (r) |
| return r; |
| /* Enable IRQ */ |
| // rdev->irq.sw_int = true; |
| // rs600_irq_set(rdev); |
| /* 1M ring buffer */ |
| // r = r100_cp_init(rdev, 1024 * 1024); |
| // if (r) { |
| // dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
| // return r; |
| // } |
| // r = r100_wb_init(rdev); |
| // if (r) |
| // dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
| // r = r100_ib_init(rdev); |
| // if (r) { |
| // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
| // return r; |
| // } |
| return 0; |
| } |
| int rs690_init(struct radeon_device *rdev) |
| { |
| int r; |
| /* Disable VGA */ |
| rv515_vga_render_disable(rdev); |
| /* Initialize scratch registers */ |
| radeon_scratch_init(rdev); |
| /* Initialize surface registers */ |
| radeon_surface_init(rdev); |
| /* TODO: disable VGA need to use VGA request */ |
| /* BIOS*/ |
| if (!radeon_get_bios(rdev)) { |
| if (ASIC_IS_AVIVO(rdev)) |
| return -EINVAL; |
| } |
| if (rdev->is_atom_bios) { |
| r = radeon_atombios_init(rdev); |
| if (r) |
| return r; |
| } else { |
| dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); |
| return -EINVAL; |
| } |
| /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
| if (radeon_gpu_reset(rdev)) { |
| dev_warn(rdev->dev, |
| "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
| RREG32(R_000E40_RBBM_STATUS), |
| RREG32(R_0007C0_CP_STAT)); |
| } |
| /* check if cards are posted or not */ |
| if (!radeon_card_posted(rdev) && rdev->bios) { |
| DRM_INFO("GPU not posted. posting now...\n"); |
| atom_asic_init(rdev->mode_info.atom_context); |
| } |
| /* Initialize clocks */ |
| radeon_get_clock_info(rdev->ddev); |
| /* Get vram informations */ |
| rs690_vram_info(rdev); |
| /* Initialize memory controller (also test AGP) */ |
| r = r420_mc_init(rdev); |
| if (r) |
| return r; |
| rv515_debugfs(rdev); |
| /* Fence driver */ |
| // r = radeon_fence_driver_init(rdev); |
| // if (r) |
| // return r; |
| // r = radeon_irq_kms_init(rdev); |
| // if (r) |
| // return r; |
| /* Memory manager */ |
| r = radeon_object_init(rdev); |
| if (r) |
| return r; |
| r = rs400_gart_init(rdev); |
| if (r) |
| return r; |
| rs600_set_safe_registers(rdev); |
| rdev->accel_working = true; |
| r = rs690_startup(rdev); |
| if (r) { |
| /* Somethings want wront with the accel init stop accel */ |
| dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
| // rs690_suspend(rdev); |
| // r100_cp_fini(rdev); |
| // r100_wb_fini(rdev); |
| // r100_ib_fini(rdev); |
| rs400_gart_fini(rdev); |
| // radeon_irq_kms_fini(rdev); |
| rdev->accel_working = false; |
| } |
| return 0; |
| } |
| /drivers/video/drm/radeon/rv515.c |
|---|
| 29,17 → 29,37 |
| #include "drmP.h" |
| #include "rv515d.h" |
| #include "radeon.h" |
| #include "atom.h" |
| #include "rv515_reg_safe.h" |
| /* rv515 depends on : */ |
| void r100_hdp_reset(struct radeon_device *rdev); |
| int r100_cp_reset(struct radeon_device *rdev); |
| int r100_rb2d_reset(struct radeon_device *rdev); |
| int r100_gui_wait_for_idle(struct radeon_device *rdev); |
| int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); |
| void r420_pipes_init(struct radeon_device *rdev); |
| void rs600_mc_disable_clients(struct radeon_device *rdev); |
| void rs600_disable_vga(struct radeon_device *rdev); |
| /* This files gather functions specifics to: rv515 */ |
| /* This files gather functions specifics to: |
| * rv515 |
| * |
| * Some of these functions might be used by newer ASICs. |
| */ |
| int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); |
| int rv515_debugfs_ga_info_init(struct radeon_device *rdev); |
| void rv515_gpu_init(struct radeon_device *rdev); |
| int rv515_mc_wait_for_idle(struct radeon_device *rdev); |
| void rv515_debugfs(struct radeon_device *rdev) |
| /* |
| * MC |
| */ |
| int rv515_mc_init(struct radeon_device *rdev) |
| { |
| uint32_t tmp; |
| int r; |
| if (r100_debugfs_rbbm_init(rdev)) { |
| DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
| } |
| 49,8 → 69,67 |
| if (rv515_debugfs_ga_info_init(rdev)) { |
| DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
| } |
| rv515_gpu_init(rdev); |
| rv370_pcie_gart_disable(rdev); |
| /* Setup GPU memory space */ |
| rdev->mc.vram_location = 0xFFFFFFFFUL; |
| rdev->mc.gtt_location = 0xFFFFFFFFUL; |
| // if (rdev->flags & RADEON_IS_AGP) { |
| // r = radeon_agp_init(rdev); |
| // if (r) { |
| // printk(KERN_WARNING "[drm] Disabling AGP\n"); |
| // rdev->flags &= ~RADEON_IS_AGP; |
| // rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
| // } else { |
| // rdev->mc.gtt_location = rdev->mc.agp_base; |
| // } |
| // } |
| r = radeon_mc_setup(rdev); |
| if (r) { |
| return r; |
| } |
| /* Program GPU memory space */ |
| rs600_mc_disable_clients(rdev); |
| if (rv515_mc_wait_for_idle(rdev)) { |
| printk(KERN_WARNING "Failed to wait MC idle while " |
| "programming pipes. Bad things might happen.\n"); |
| } |
| /* Write VRAM size in case we are limiting it */ |
| WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
| tmp = REG_SET(MC_FB_START, rdev->mc.vram_location >> 16); |
| WREG32(0x134, tmp); |
| tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
| tmp = REG_SET(MC_FB_TOP, tmp >> 16); |
| tmp |= REG_SET(MC_FB_START, rdev->mc.vram_location >> 16); |
| WREG32_MC(MC_FB_LOCATION, tmp); |
| WREG32(HDP_FB_LOCATION, rdev->mc.vram_location >> 16); |
| WREG32(0x310, rdev->mc.vram_location); |
| if (rdev->flags & RADEON_IS_AGP) { |
| tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
| tmp = REG_SET(MC_AGP_TOP, tmp >> 16); |
| tmp |= REG_SET(MC_AGP_START, rdev->mc.gtt_location >> 16); |
| WREG32_MC(MC_AGP_LOCATION, tmp); |
| WREG32_MC(MC_AGP_BASE, rdev->mc.agp_base); |
| WREG32_MC(MC_AGP_BASE_2, 0); |
| } else { |
| WREG32_MC(MC_AGP_LOCATION, 0x0FFFFFFF); |
| WREG32_MC(MC_AGP_BASE, 0); |
| WREG32_MC(MC_AGP_BASE_2, 0); |
| } |
| return 0; |
| } |
| void rv515_mc_fini(struct radeon_device *rdev) |
| { |
| } |
| /* |
| * Global GPU functions |
| */ |
| void rv515_ring_start(struct radeon_device *rdev) |
| { |
| int r; |
| 124,6 → 203,11 |
| } |
| void rv515_errata(struct radeon_device *rdev) |
| { |
| rdev->pll_errata = 0; |
| } |
| int rv515_mc_wait_for_idle(struct radeon_device *rdev) |
| { |
| unsigned i; |
| 140,12 → 224,6 |
| return -1; |
| } |
| void rv515_vga_render_disable(struct radeon_device *rdev) |
| { |
| WREG32(R_000300_VGA_RENDER_CONTROL, |
| RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); |
| } |
| void rv515_gpu_init(struct radeon_device *rdev) |
| { |
| unsigned pipe_select_current, gb_pipe_select, tmp; |
| 158,7 → 236,7 |
| "reseting GPU. Bad things might happen.\n"); |
| } |
| rv515_vga_render_disable(rdev); |
| rs600_disable_vga(rdev); |
| r420_pipes_init(rdev); |
| gb_pipe_select = RREG32(0x402C); |
| 266,6 → 344,10 |
| return 0; |
| } |
| /* |
| * VRAM info |
| */ |
| static void rv515_vram_get_type(struct radeon_device *rdev) |
| { |
| uint32_t tmp; |
| 301,6 → 383,10 |
| rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); |
| } |
| /* |
| * Indirect registers accessor |
| */ |
| uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
| { |
| uint32_t r; |
| 318,6 → 404,9 |
| WREG32(MC_IND_INDEX, 0); |
| } |
| /* |
| * Debugfs info |
| */ |
| #if defined(CONFIG_DEBUG_FS) |
| static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) |
| { |
| 379,211 → 468,15 |
| #endif |
| } |
| void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) |
| /* |
| * Asic initialization |
| */ |
| int rv515_init(struct radeon_device *rdev) |
| { |
| save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL); |
| save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL); |
| save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); |
| save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); |
| save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL); |
| save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL); |
| ENTER(); |
| /* Stop all video */ |
| WREG32(R_000330_D1VGA_CONTROL, 0); |
| WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); |
| WREG32(R_000300_VGA_RENDER_CONTROL, 0); |
| WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); |
| WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); |
| WREG32(R_006080_D1CRTC_CONTROL, 0); |
| WREG32(R_006880_D2CRTC_CONTROL, 0); |
| WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); |
| WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); |
| } |
| void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) |
| { |
| WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start); |
| WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start); |
| WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start); |
| WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start); |
| WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start); |
| /* Unlock host access */ |
| WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); |
| mdelay(1); |
| /* Restore video state */ |
| WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); |
| WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); |
| WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control); |
| WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control); |
| WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); |
| WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); |
| WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control); |
| WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control); |
| WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); |
| } |
| void rv515_mc_program(struct radeon_device *rdev) |
| { |
| struct rv515_mc_save save; |
| /* Stops all mc clients */ |
| rv515_mc_stop(rdev, &save); |
| /* Wait for mc idle */ |
| if (rv515_mc_wait_for_idle(rdev)) |
| dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
| /* Write VRAM size in case we are limiting it */ |
| WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
| /* Program MC, should be a 32bits limited address space */ |
| WREG32_MC(R_000001_MC_FB_LOCATION, |
| S_000001_MC_FB_START(rdev->mc.vram_start >> 16) | |
| S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
| WREG32(R_000134_HDP_FB_LOCATION, |
| S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); |
| if (rdev->flags & RADEON_IS_AGP) { |
| WREG32_MC(R_000002_MC_AGP_LOCATION, |
| S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) | |
| S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); |
| WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); |
| WREG32_MC(R_000004_MC_AGP_BASE_2, |
| S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); |
| } else { |
| WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF); |
| WREG32_MC(R_000003_MC_AGP_BASE, 0); |
| WREG32_MC(R_000004_MC_AGP_BASE_2, 0); |
| } |
| rv515_mc_resume(rdev, &save); |
| } |
| void rv515_clock_startup(struct radeon_device *rdev) |
| { |
| if (radeon_dynclks != -1 && radeon_dynclks) |
| radeon_atom_set_clock_gating(rdev, 1); |
| /* We need to force on some of the block */ |
| WREG32_PLL(R_00000F_CP_DYN_CNTL, |
| RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); |
| WREG32_PLL(R_000011_E2_DYN_CNTL, |
| RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); |
| WREG32_PLL(R_000013_IDCT_DYN_CNTL, |
| RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1)); |
| } |
| static int rv515_startup(struct radeon_device *rdev) |
| { |
| int r; |
| rv515_mc_program(rdev); |
| /* Resume clock */ |
| rv515_clock_startup(rdev); |
| /* Initialize GPU configuration (# pipes, ...) */ |
| rv515_gpu_init(rdev); |
| /* Initialize GART (initialize after TTM so we can allocate |
| * memory through TTM but finalize after TTM) */ |
| if (rdev->flags & RADEON_IS_PCIE) { |
| r = rv370_pcie_gart_enable(rdev); |
| if (r) |
| return r; |
| } |
| /* Enable IRQ */ |
| // rdev->irq.sw_int = true; |
| // rs600_irq_set(rdev); |
| /* 1M ring buffer */ |
| // r = r100_cp_init(rdev, 1024 * 1024); |
| // if (r) { |
| // dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
| // return r; |
| // } |
| // r = r100_wb_init(rdev); |
| // if (r) |
| // dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
| // r = r100_ib_init(rdev); |
| // if (r) { |
| // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
| // return r; |
| // } |
| return 0; |
| } |
| void rv515_set_safe_registers(struct radeon_device *rdev) |
| { |
| rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm; |
| rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm); |
| } |
| int rv515_init(struct radeon_device *rdev) |
| { |
| int r; |
| /* Initialize scratch registers */ |
| radeon_scratch_init(rdev); |
| /* Initialize surface registers */ |
| radeon_surface_init(rdev); |
| /* TODO: disable VGA need to use VGA request */ |
| /* BIOS*/ |
| if (!radeon_get_bios(rdev)) { |
| if (ASIC_IS_AVIVO(rdev)) |
| return -EINVAL; |
| } |
| if (rdev->is_atom_bios) { |
| r = radeon_atombios_init(rdev); |
| if (r) |
| return r; |
| } else { |
| dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); |
| return -EINVAL; |
| } |
| /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
| if (radeon_gpu_reset(rdev)) { |
| dev_warn(rdev->dev, |
| "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
| RREG32(R_000E40_RBBM_STATUS), |
| RREG32(R_0007C0_CP_STAT)); |
| } |
| /* check if cards are posted or not */ |
| if (!radeon_card_posted(rdev) && rdev->bios) { |
| DRM_INFO("GPU not posted. posting now...\n"); |
| atom_asic_init(rdev->mode_info.atom_context); |
| } |
| /* Initialize clocks */ |
| radeon_get_clock_info(rdev->ddev); |
| /* Get vram informations */ |
| rv515_vram_info(rdev); |
| /* Initialize memory controller (also test AGP) */ |
| r = r420_mc_init(rdev); |
| if (r) |
| return r; |
| rv515_debugfs(rdev); |
| /* Fence driver */ |
| // r = radeon_fence_driver_init(rdev); |
| // if (r) |
| // return r; |
| // r = radeon_irq_kms_init(rdev); |
| // if (r) |
| // return r; |
| /* Memory manager */ |
| r = radeon_object_init(rdev); |
| if (r) |
| return r; |
| r = rv370_pcie_gart_init(rdev); |
| if (r) |
| return r; |
| rv515_set_safe_registers(rdev); |
| rdev->accel_working = true; |
| r = rv515_startup(rdev); |
| if (r) { |
| /* Somethings want wront with the accel init stop accel */ |
| dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
| // rv515_suspend(rdev); |
| // r100_cp_fini(rdev); |
| // r100_wb_fini(rdev); |
| // r100_ib_fini(rdev); |
| rv370_pcie_gart_fini(rdev); |
| // radeon_agp_fini(rdev); |
| // radeon_irq_kms_fini(rdev); |
| rdev->accel_working = false; |
| } |
| return 0; |
| } |
| /drivers/video/drm/radeon/rv515d.h |
|---|
| 216,388 → 216,5 |
| #define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) |
| #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) |
| /* Registers */ |
| #define R_0000F8_CONFIG_MEMSIZE 0x0000F8 |
| #define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0) |
| #define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF) |
| #define C_0000F8_CONFIG_MEMSIZE 0x00000000 |
| #define R_000134_HDP_FB_LOCATION 0x000134 |
| #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) |
| #define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF) |
| #define C_000134_HDP_FB_START 0xFFFF0000 |
| #define R_000300_VGA_RENDER_CONTROL 0x000300 |
| #define S_000300_VGA_BLINK_RATE(x) (((x) & 0x1F) << 0) |
| #define G_000300_VGA_BLINK_RATE(x) (((x) >> 0) & 0x1F) |
| #define C_000300_VGA_BLINK_RATE 0xFFFFFFE0 |
| #define S_000300_VGA_BLINK_MODE(x) (((x) & 0x3) << 5) |
| #define G_000300_VGA_BLINK_MODE(x) (((x) >> 5) & 0x3) |
| #define C_000300_VGA_BLINK_MODE 0xFFFFFF9F |
| #define S_000300_VGA_CURSOR_BLINK_INVERT(x) (((x) & 0x1) << 7) |
| #define G_000300_VGA_CURSOR_BLINK_INVERT(x) (((x) >> 7) & 0x1) |
| #define C_000300_VGA_CURSOR_BLINK_INVERT 0xFFFFFF7F |
| #define S_000300_VGA_EXTD_ADDR_COUNT_ENABLE(x) (((x) & 0x1) << 8) |
| #define G_000300_VGA_EXTD_ADDR_COUNT_ENABLE(x) (((x) >> 8) & 0x1) |
| #define C_000300_VGA_EXTD_ADDR_COUNT_ENABLE 0xFFFFFEFF |
| #define S_000300_VGA_VSTATUS_CNTL(x) (((x) & 0x3) << 16) |
| #define G_000300_VGA_VSTATUS_CNTL(x) (((x) >> 16) & 0x3) |
| #define C_000300_VGA_VSTATUS_CNTL 0xFFFCFFFF |
| #define S_000300_VGA_LOCK_8DOT(x) (((x) & 0x1) << 24) |
| #define G_000300_VGA_LOCK_8DOT(x) (((x) >> 24) & 0x1) |
| #define C_000300_VGA_LOCK_8DOT 0xFEFFFFFF |
| #define S_000300_VGAREG_LINECMP_COMPATIBILITY_SEL(x) (((x) & 0x1) << 25) |
| #define G_000300_VGAREG_LINECMP_COMPATIBILITY_SEL(x) (((x) >> 25) & 0x1) |
| #define C_000300_VGAREG_LINECMP_COMPATIBILITY_SEL 0xFDFFFFFF |
| #define R_000310_VGA_MEMORY_BASE_ADDRESS 0x000310 |
| #define S_000310_VGA_MEMORY_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) |
| #define G_000310_VGA_MEMORY_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) |
| #define C_000310_VGA_MEMORY_BASE_ADDRESS 0x00000000 |
| #define R_000328_VGA_HDP_CONTROL 0x000328 |
| #define S_000328_VGA_MEM_PAGE_SELECT_EN(x) (((x) & 0x1) << 0) |
| #define G_000328_VGA_MEM_PAGE_SELECT_EN(x) (((x) >> 0) & 0x1) |
| #define C_000328_VGA_MEM_PAGE_SELECT_EN 0xFFFFFFFE |
| #define S_000328_VGA_RBBM_LOCK_DISABLE(x) (((x) & 0x1) << 8) |
| #define G_000328_VGA_RBBM_LOCK_DISABLE(x) (((x) >> 8) & 0x1) |
| #define C_000328_VGA_RBBM_LOCK_DISABLE 0xFFFFFEFF |
| #define S_000328_VGA_SOFT_RESET(x) (((x) & 0x1) << 16) |
| #define G_000328_VGA_SOFT_RESET(x) (((x) >> 16) & 0x1) |
| #define C_000328_VGA_SOFT_RESET 0xFFFEFFFF |
| #define S_000328_VGA_TEST_RESET_CONTROL(x) (((x) & 0x1) << 24) |
| #define G_000328_VGA_TEST_RESET_CONTROL(x) (((x) >> 24) & 0x1) |
| #define C_000328_VGA_TEST_RESET_CONTROL 0xFEFFFFFF |
| #define R_000330_D1VGA_CONTROL 0x000330 |
| #define S_000330_D1VGA_MODE_ENABLE(x) (((x) & 0x1) << 0) |
| #define G_000330_D1VGA_MODE_ENABLE(x) (((x) >> 0) & 0x1) |
| #define C_000330_D1VGA_MODE_ENABLE 0xFFFFFFFE |
| #define S_000330_D1VGA_TIMING_SELECT(x) (((x) & 0x1) << 8) |
| #define G_000330_D1VGA_TIMING_SELECT(x) (((x) >> 8) & 0x1) |
| #define C_000330_D1VGA_TIMING_SELECT 0xFFFFFEFF |
| #define S_000330_D1VGA_SYNC_POLARITY_SELECT(x) (((x) & 0x1) << 9) |
| #define G_000330_D1VGA_SYNC_POLARITY_SELECT(x) (((x) >> 9) & 0x1) |
| #define C_000330_D1VGA_SYNC_POLARITY_SELECT 0xFFFFFDFF |
| #define S_000330_D1VGA_OVERSCAN_TIMING_SELECT(x) (((x) & 0x1) << 10) |
| #define G_000330_D1VGA_OVERSCAN_TIMING_SELECT(x) (((x) >> 10) & 0x1) |
| #define C_000330_D1VGA_OVERSCAN_TIMING_SELECT 0xFFFFFBFF |
| #define S_000330_D1VGA_OVERSCAN_COLOR_EN(x) (((x) & 0x1) << 16) |
| #define G_000330_D1VGA_OVERSCAN_COLOR_EN(x) (((x) >> 16) & 0x1) |
| #define C_000330_D1VGA_OVERSCAN_COLOR_EN 0xFFFEFFFF |
| #define S_000330_D1VGA_ROTATE(x) (((x) & 0x3) << 24) |
| #define G_000330_D1VGA_ROTATE(x) (((x) >> 24) & 0x3) |
| #define C_000330_D1VGA_ROTATE 0xFCFFFFFF |
| #define R_000338_D2VGA_CONTROL 0x000338 |
| #define S_000338_D2VGA_MODE_ENABLE(x) (((x) & 0x1) << 0) |
| #define G_000338_D2VGA_MODE_ENABLE(x) (((x) >> 0) & 0x1) |
| #define C_000338_D2VGA_MODE_ENABLE 0xFFFFFFFE |
| #define S_000338_D2VGA_TIMING_SELECT(x) (((x) & 0x1) << 8) |
| #define G_000338_D2VGA_TIMING_SELECT(x) (((x) >> 8) & 0x1) |
| #define C_000338_D2VGA_TIMING_SELECT 0xFFFFFEFF |
| #define S_000338_D2VGA_SYNC_POLARITY_SELECT(x) (((x) & 0x1) << 9) |
| #define G_000338_D2VGA_SYNC_POLARITY_SELECT(x) (((x) >> 9) & 0x1) |
| #define C_000338_D2VGA_SYNC_POLARITY_SELECT 0xFFFFFDFF |
| #define S_000338_D2VGA_OVERSCAN_TIMING_SELECT(x) (((x) & 0x1) << 10) |
| #define G_000338_D2VGA_OVERSCAN_TIMING_SELECT(x) (((x) >> 10) & 0x1) |
| #define C_000338_D2VGA_OVERSCAN_TIMING_SELECT 0xFFFFFBFF |
| #define S_000338_D2VGA_OVERSCAN_COLOR_EN(x) (((x) & 0x1) << 16) |
| #define G_000338_D2VGA_OVERSCAN_COLOR_EN(x) (((x) >> 16) & 0x1) |
| #define C_000338_D2VGA_OVERSCAN_COLOR_EN 0xFFFEFFFF |
| #define S_000338_D2VGA_ROTATE(x) (((x) & 0x3) << 24) |
| #define G_000338_D2VGA_ROTATE(x) (((x) >> 24) & 0x3) |
| #define C_000338_D2VGA_ROTATE 0xFCFFFFFF |
| #define R_0007C0_CP_STAT 0x0007C0 |
| #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) |
| #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) |
| #define C_0007C0_MRU_BUSY 0xFFFFFFFE |
| #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) |
| #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) |
| #define C_0007C0_MWU_BUSY 0xFFFFFFFD |
| #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) |
| #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) |
| #define C_0007C0_RSIU_BUSY 0xFFFFFFFB |
| #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) |
| #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) |
| #define C_0007C0_RCIU_BUSY 0xFFFFFFF7 |
| #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) |
| #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) |
| #define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF |
| #define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10) |
| #define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1) |
| #define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF |
| #define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11) |
| #define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1) |
| #define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF |
| #define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12) |
| #define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1) |
| #define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF |
| #define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13) |
| #define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1) |
| #define C_0007C0_CSI_BUSY 0xFFFFDFFF |
| #define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14) |
| #define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1) |
| #define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF |
| #define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15) |
| #define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1) |
| #define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF |
| #define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28) |
| #define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1) |
| #define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF |
| #define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29) |
| #define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1) |
| #define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF |
| #define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30) |
| #define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1) |
| #define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF |
| #define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31) |
| #define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1) |
| #define C_0007C0_CP_BUSY 0x7FFFFFFF |
| #define R_000E40_RBBM_STATUS 0x000E40 |
| #define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) |
| #define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) |
| #define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 |
| #define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) |
| #define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) |
| #define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF |
| #define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) |
| #define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) |
| #define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF |
| #define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) |
| #define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) |
| #define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF |
| #define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) |
| #define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) |
| #define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF |
| #define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) |
| #define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) |
| #define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF |
| #define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) |
| #define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) |
| #define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF |
| #define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) |
| #define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) |
| #define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF |
| #define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) |
| #define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) |
| #define C_000E40_ENG_EV_BUSY 0xFFFF7FFF |
| #define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) |
| #define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) |
| #define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF |
| #define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) |
| #define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) |
| #define C_000E40_E2_BUSY 0xFFFDFFFF |
| #define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) |
| #define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) |
| #define C_000E40_RB2D_BUSY 0xFFFBFFFF |
| #define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) |
| #define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) |
| #define C_000E40_RB3D_BUSY 0xFFF7FFFF |
| #define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20) |
| #define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1) |
| #define C_000E40_VAP_BUSY 0xFFEFFFFF |
| #define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) |
| #define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) |
| #define C_000E40_RE_BUSY 0xFFDFFFFF |
| #define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) |
| #define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) |
| #define C_000E40_TAM_BUSY 0xFFBFFFFF |
| #define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) |
| #define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) |
| #define C_000E40_TDM_BUSY 0xFF7FFFFF |
| #define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) |
| #define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) |
| #define C_000E40_PB_BUSY 0xFEFFFFFF |
| #define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25) |
| #define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1) |
| #define C_000E40_TIM_BUSY 0xFDFFFFFF |
| #define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26) |
| #define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1) |
| #define C_000E40_GA_BUSY 0xFBFFFFFF |
| #define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27) |
| #define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1) |
| #define C_000E40_CBA2D_BUSY 0xF7FFFFFF |
| #define S_000E40_RBBM_HIBUSY(x) (((x) & 0x1) << 28) |
| #define G_000E40_RBBM_HIBUSY(x) (((x) >> 28) & 0x1) |
| #define C_000E40_RBBM_HIBUSY 0xEFFFFFFF |
| #define S_000E40_SKID_CFBUSY(x) (((x) & 0x1) << 29) |
| #define G_000E40_SKID_CFBUSY(x) (((x) >> 29) & 0x1) |
| #define C_000E40_SKID_CFBUSY 0xDFFFFFFF |
| #define S_000E40_VAP_VF_BUSY(x) (((x) & 0x1) << 30) |
| #define G_000E40_VAP_VF_BUSY(x) (((x) >> 30) & 0x1) |
| #define C_000E40_VAP_VF_BUSY 0xBFFFFFFF |
| #define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) |
| #define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) |
| #define C_000E40_GUI_ACTIVE 0x7FFFFFFF |
| #define R_006080_D1CRTC_CONTROL 0x006080 |
| #define S_006080_D1CRTC_MASTER_EN(x) (((x) & 0x1) << 0) |
| #define G_006080_D1CRTC_MASTER_EN(x) (((x) >> 0) & 0x1) |
| #define C_006080_D1CRTC_MASTER_EN 0xFFFFFFFE |
| #define S_006080_D1CRTC_SYNC_RESET_SEL(x) (((x) & 0x1) << 4) |
| #define G_006080_D1CRTC_SYNC_RESET_SEL(x) (((x) >> 4) & 0x1) |
| #define C_006080_D1CRTC_SYNC_RESET_SEL 0xFFFFFFEF |
| #define S_006080_D1CRTC_DISABLE_POINT_CNTL(x) (((x) & 0x3) << 8) |
| #define G_006080_D1CRTC_DISABLE_POINT_CNTL(x) (((x) >> 8) & 0x3) |
| #define C_006080_D1CRTC_DISABLE_POINT_CNTL 0xFFFFFCFF |
| #define S_006080_D1CRTC_CURRENT_MASTER_EN_STATE(x) (((x) & 0x1) << 16) |
| #define G_006080_D1CRTC_CURRENT_MASTER_EN_STATE(x) (((x) >> 16) & 0x1) |
| #define C_006080_D1CRTC_CURRENT_MASTER_EN_STATE 0xFFFEFFFF |
| #define S_006080_D1CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) & 0x1) << 24) |
| #define G_006080_D1CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) >> 24) & 0x1) |
| #define C_006080_D1CRTC_DISP_READ_REQUEST_DISABLE 0xFEFFFFFF |
| #define R_0060E8_D1CRTC_UPDATE_LOCK 0x0060E8 |
| #define S_0060E8_D1CRTC_UPDATE_LOCK(x) (((x) & 0x1) << 0) |
| #define G_0060E8_D1CRTC_UPDATE_LOCK(x) (((x) >> 0) & 0x1) |
| #define C_0060E8_D1CRTC_UPDATE_LOCK 0xFFFFFFFE |
| #define R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x006110 |
| #define S_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) |
| #define G_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) |
| #define C_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x00000000 |
| #define R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x006118 |
| #define S_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) |
| #define G_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) |
| #define C_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x00000000 |
| #define R_006880_D2CRTC_CONTROL 0x006880 |
| #define S_006880_D2CRTC_MASTER_EN(x) (((x) & 0x1) << 0) |
| #define G_006880_D2CRTC_MASTER_EN(x) (((x) >> 0) & 0x1) |
| #define C_006880_D2CRTC_MASTER_EN 0xFFFFFFFE |
| #define S_006880_D2CRTC_SYNC_RESET_SEL(x) (((x) & 0x1) << 4) |
| #define G_006880_D2CRTC_SYNC_RESET_SEL(x) (((x) >> 4) & 0x1) |
| #define C_006880_D2CRTC_SYNC_RESET_SEL 0xFFFFFFEF |
| #define S_006880_D2CRTC_DISABLE_POINT_CNTL(x) (((x) & 0x3) << 8) |
| #define G_006880_D2CRTC_DISABLE_POINT_CNTL(x) (((x) >> 8) & 0x3) |
| #define C_006880_D2CRTC_DISABLE_POINT_CNTL 0xFFFFFCFF |
| #define S_006880_D2CRTC_CURRENT_MASTER_EN_STATE(x) (((x) & 0x1) << 16) |
| #define G_006880_D2CRTC_CURRENT_MASTER_EN_STATE(x) (((x) >> 16) & 0x1) |
| #define C_006880_D2CRTC_CURRENT_MASTER_EN_STATE 0xFFFEFFFF |
| #define S_006880_D2CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) & 0x1) << 24) |
| #define G_006880_D2CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) >> 24) & 0x1) |
| #define C_006880_D2CRTC_DISP_READ_REQUEST_DISABLE 0xFEFFFFFF |
| #define R_0068E8_D2CRTC_UPDATE_LOCK 0x0068E8 |
| #define S_0068E8_D2CRTC_UPDATE_LOCK(x) (((x) & 0x1) << 0) |
| #define G_0068E8_D2CRTC_UPDATE_LOCK(x) (((x) >> 0) & 0x1) |
| #define C_0068E8_D2CRTC_UPDATE_LOCK 0xFFFFFFFE |
| #define R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x006910 |
| #define S_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) |
| #define G_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) |
| #define C_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x00000000 |
| #define R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x006918 |
| #define S_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) |
| #define G_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) |
| #define C_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x00000000 |
| #endif |
| #define R_000001_MC_FB_LOCATION 0x000001 |
| #define S_000001_MC_FB_START(x) (((x) & 0xFFFF) << 0) |
| #define G_000001_MC_FB_START(x) (((x) >> 0) & 0xFFFF) |
| #define C_000001_MC_FB_START 0xFFFF0000 |
| #define S_000001_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) |
| #define G_000001_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) |
| #define C_000001_MC_FB_TOP 0x0000FFFF |
| #define R_000002_MC_AGP_LOCATION 0x000002 |
| #define S_000002_MC_AGP_START(x) (((x) & 0xFFFF) << 0) |
| #define G_000002_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) |
| #define C_000002_MC_AGP_START 0xFFFF0000 |
| #define S_000002_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) |
| #define G_000002_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) |
| #define C_000002_MC_AGP_TOP 0x0000FFFF |
| #define R_000003_MC_AGP_BASE 0x000003 |
| #define S_000003_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) |
| #define G_000003_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) |
| #define C_000003_AGP_BASE_ADDR 0x00000000 |
| #define R_000004_MC_AGP_BASE_2 0x000004 |
| #define S_000004_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) |
| #define G_000004_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) |
| #define C_000004_AGP_BASE_ADDR_2 0xFFFFFFF0 |
| #define R_00000F_CP_DYN_CNTL 0x00000F |
| #define S_00000F_CP_FORCEON(x) (((x) & 0x1) << 0) |
| #define G_00000F_CP_FORCEON(x) (((x) >> 0) & 0x1) |
| #define C_00000F_CP_FORCEON 0xFFFFFFFE |
| #define S_00000F_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1) |
| #define G_00000F_CP_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1) |
| #define C_00000F_CP_MAX_DYN_STOP_LAT 0xFFFFFFFD |
| #define S_00000F_CP_CLOCK_STATUS(x) (((x) & 0x1) << 2) |
| #define G_00000F_CP_CLOCK_STATUS(x) (((x) >> 2) & 0x1) |
| #define C_00000F_CP_CLOCK_STATUS 0xFFFFFFFB |
| #define S_00000F_CP_PROG_SHUTOFF(x) (((x) & 0x1) << 3) |
| #define G_00000F_CP_PROG_SHUTOFF(x) (((x) >> 3) & 0x1) |
| #define C_00000F_CP_PROG_SHUTOFF 0xFFFFFFF7 |
| #define S_00000F_CP_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4) |
| #define G_00000F_CP_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF) |
| #define C_00000F_CP_PROG_DELAY_VALUE 0xFFFFF00F |
| #define S_00000F_CP_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12) |
| #define G_00000F_CP_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF) |
| #define C_00000F_CP_LOWER_POWER_IDLE 0xFFF00FFF |
| #define S_00000F_CP_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20) |
| #define G_00000F_CP_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1) |
| #define C_00000F_CP_LOWER_POWER_IGNORE 0xFFEFFFFF |
| #define S_00000F_CP_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21) |
| #define G_00000F_CP_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1) |
| #define C_00000F_CP_NORMAL_POWER_IGNORE 0xFFDFFFFF |
| #define S_00000F_SPARE(x) (((x) & 0x3) << 22) |
| #define G_00000F_SPARE(x) (((x) >> 22) & 0x3) |
| #define C_00000F_SPARE 0xFF3FFFFF |
| #define S_00000F_CP_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24) |
| #define G_00000F_CP_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF) |
| #define C_00000F_CP_NORMAL_POWER_BUSY 0x00FFFFFF |
| #define R_000011_E2_DYN_CNTL 0x000011 |
| #define S_000011_E2_FORCEON(x) (((x) & 0x1) << 0) |
| #define G_000011_E2_FORCEON(x) (((x) >> 0) & 0x1) |
| #define C_000011_E2_FORCEON 0xFFFFFFFE |
| #define S_000011_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1) |
| #define G_000011_E2_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1) |
| #define C_000011_E2_MAX_DYN_STOP_LAT 0xFFFFFFFD |
| #define S_000011_E2_CLOCK_STATUS(x) (((x) & 0x1) << 2) |
| #define G_000011_E2_CLOCK_STATUS(x) (((x) >> 2) & 0x1) |
| #define C_000011_E2_CLOCK_STATUS 0xFFFFFFFB |
| #define S_000011_E2_PROG_SHUTOFF(x) (((x) & 0x1) << 3) |
| #define G_000011_E2_PROG_SHUTOFF(x) (((x) >> 3) & 0x1) |
| #define C_000011_E2_PROG_SHUTOFF 0xFFFFFFF7 |
| #define S_000011_E2_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4) |
| #define G_000011_E2_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF) |
| #define C_000011_E2_PROG_DELAY_VALUE 0xFFFFF00F |
| #define S_000011_E2_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12) |
| #define G_000011_E2_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF) |
| #define C_000011_E2_LOWER_POWER_IDLE 0xFFF00FFF |
| #define S_000011_E2_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20) |
| #define G_000011_E2_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1) |
| #define C_000011_E2_LOWER_POWER_IGNORE 0xFFEFFFFF |
| #define S_000011_E2_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21) |
| #define G_000011_E2_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1) |
| #define C_000011_E2_NORMAL_POWER_IGNORE 0xFFDFFFFF |
| #define S_000011_SPARE(x) (((x) & 0x3) << 22) |
| #define G_000011_SPARE(x) (((x) >> 22) & 0x3) |
| #define C_000011_SPARE 0xFF3FFFFF |
| #define S_000011_E2_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24) |
| #define G_000011_E2_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF) |
| #define C_000011_E2_NORMAL_POWER_BUSY 0x00FFFFFF |
| #define R_000013_IDCT_DYN_CNTL 0x000013 |
| #define S_000013_IDCT_FORCEON(x) (((x) & 0x1) << 0) |
| #define G_000013_IDCT_FORCEON(x) (((x) >> 0) & 0x1) |
| #define C_000013_IDCT_FORCEON 0xFFFFFFFE |
| #define S_000013_IDCT_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1) |
| #define G_000013_IDCT_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1) |
| #define C_000013_IDCT_MAX_DYN_STOP_LAT 0xFFFFFFFD |
| #define S_000013_IDCT_CLOCK_STATUS(x) (((x) & 0x1) << 2) |
| #define G_000013_IDCT_CLOCK_STATUS(x) (((x) >> 2) & 0x1) |
| #define C_000013_IDCT_CLOCK_STATUS 0xFFFFFFFB |
| #define S_000013_IDCT_PROG_SHUTOFF(x) (((x) & 0x1) << 3) |
| #define G_000013_IDCT_PROG_SHUTOFF(x) (((x) >> 3) & 0x1) |
| #define C_000013_IDCT_PROG_SHUTOFF 0xFFFFFFF7 |
| #define S_000013_IDCT_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4) |
| #define G_000013_IDCT_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF) |
| #define C_000013_IDCT_PROG_DELAY_VALUE 0xFFFFF00F |
| #define S_000013_IDCT_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12) |
| #define G_000013_IDCT_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF) |
| #define C_000013_IDCT_LOWER_POWER_IDLE 0xFFF00FFF |
| #define S_000013_IDCT_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20) |
| #define G_000013_IDCT_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1) |
| #define C_000013_IDCT_LOWER_POWER_IGNORE 0xFFEFFFFF |
| #define S_000013_IDCT_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21) |
| #define G_000013_IDCT_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1) |
| #define C_000013_IDCT_NORMAL_POWER_IGNORE 0xFFDFFFFF |
| #define S_000013_SPARE(x) (((x) & 0x3) << 22) |
| #define G_000013_SPARE(x) (((x) >> 22) & 0x3) |
| #define C_000013_SPARE 0xFF3FFFFF |
| #define S_000013_IDCT_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24) |
| #define G_000013_IDCT_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF) |
| #define C_000013_IDCT_NORMAL_POWER_BUSY 0x00FFFFFF |
| #endif |
| /drivers/video/drm/radeon/radeon_drv.c |
|---|
| 0,0 → 1,98 |
| #include "radeon_reg.h" |
| #include "radeon.h" |
| #include "radeon_asic.h" |
| #include "syscall.h" |
| int radeon_dynclks = -1; |
| static struct pci_device_id pciidlist[] = { |
| radeon_PCI_IDS |
| }; |
| static struct drm_driver kms_driver = { |
| .driver_features = |
| DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | |
| DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED | DRIVER_GEM, |
| .dev_priv_size = 0, |
| .load = radeon_driver_load_kms, |
| .firstopen = radeon_driver_firstopen_kms, |
| .open = radeon_driver_open_kms, |
| .preclose = radeon_driver_preclose_kms, |
| .postclose = radeon_driver_postclose_kms, |
| .lastclose = radeon_driver_lastclose_kms, |
| .unload = radeon_driver_unload_kms, |
| .suspend = radeon_suspend_kms, |
| .resume = radeon_resume_kms, |
| .get_vblank_counter = radeon_get_vblank_counter_kms, |
| .enable_vblank = radeon_enable_vblank_kms, |
| .disable_vblank = radeon_disable_vblank_kms, |
| .master_create = radeon_master_create_kms, |
| .master_destroy = radeon_master_destroy_kms, |
| .irq_preinstall = radeon_driver_irq_preinstall_kms, |
| .irq_postinstall = radeon_driver_irq_postinstall_kms, |
| .irq_uninstall = radeon_driver_irq_uninstall_kms, |
| .irq_handler = radeon_driver_irq_handler_kms, |
| .reclaim_buffers = drm_core_reclaim_buffers, |
| .get_map_ofs = drm_core_get_map_ofs, |
| .get_reg_ofs = drm_core_get_reg_ofs, |
| .ioctls = radeon_ioctls_kms, |
| .gem_init_object = radeon_gem_object_init, |
| .gem_free_object = radeon_gem_object_free, |
| .dma_ioctl = radeon_dma_ioctl_kms, |
| .fops = { |
| .owner = THIS_MODULE, |
| .open = drm_open, |
| .release = drm_release, |
| .ioctl = drm_ioctl, |
| .mmap = radeon_mmap, |
| .poll = drm_poll, |
| .fasync = drm_fasync, |
| }, |
| .pci_driver = { |
| .name = DRIVER_NAME, |
| .id_table = pciidlist, |
| .probe = radeon_pci_probe, |
| .remove = radeon_pci_remove, |
| .suspend = radeon_pci_suspend, |
| .resume = radeon_pci_resume, |
| }, |
| .name = DRIVER_NAME, |
| .desc = DRIVER_DESC, |
| .date = DRIVER_DATE, |
| .major = KMS_DRIVER_MAJOR, |
| .minor = KMS_DRIVER_MINOR, |
| .patchlevel = KMS_DRIVER_PATCHLEVEL, |
| }; |
| static int __init radeon_init(void) |
| { |
| radeon_modeset = 1; |
| driver = &kms_driver; |
| driver->driver_features |= DRIVER_MODESET; |
| driver->num_ioctls = radeon_max_kms_ioctl; |
| return drm_init(driver); |
| } |
| struct pci_driver |
| { |
| struct list_head node; |
| char *name; |
| const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ |
| int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ |
| void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ |
| int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ |
| int (*suspend_late) (struct pci_dev *dev, pm_message_t state); |
| int (*resume_early) (struct pci_dev *dev); |
| int (*resume) (struct pci_dev *dev); /* Device woken up */ |
| void (*shutdown) (struct pci_dev *dev); |
| struct pci_error_handlers *err_handler; |
| struct device_driver driver; |
| struct pci_dynids dynids; |
| }; |
| /drivers/video/drm/drm_crtc.c |
|---|
| 482,7 → 482,6 |
| list_for_each_entry_safe(mode, t, &connector->user_modes, head) |
| drm_mode_remove(connector, mode); |
| kfree(connector->fb_helper_private); |
| mutex_lock(&dev->mode_config.mutex); |
| drm_mode_object_put(dev, &connector->base); |
| list_del(&connector->head); |
| 1178,6 → 1177,7 |
| return ret; |
| } |
| /** |
| * drm_mode_getcrtc - get CRTC configuration |
| * @inode: inode from the ioctl |
| 1558,6 → 1558,8 |
| struct drm_crtc *crtc; |
| int ret = 0; |
| DRM_DEBUG_KMS("\n"); |
| if (!req->flags) { |
| DRM_ERROR("no operation set\n"); |
| return -EINVAL; |
| 1972,6 → 1974,9 |
| strncpy(property->name, name, DRM_PROP_NAME_LEN); |
| list_add_tail(&property->head, &dev->mode_config.property_list); |
| dbgprintf("%s %x name %s\n", __FUNCTION__, property, name); |
| return property; |
| fail: |
| kfree(property); |
| /drivers/video/drm/drm_edid.c |
|---|
| 26,7 → 26,10 |
| * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| * DEALINGS IN THE SOFTWARE. |
| */ |
| #include <linux/kernel.h> |
| //#include <linux/kernel.h> |
| #include <types.h> |
| #include <list.h> |
| #include <linux/i2c.h> |
| #include <linux/i2c-algo-bit.h> |
| #include "drmP.h" |
| 109,9 → 112,7 |
| /* Valid EDID header has these bytes */ |
| static const u8 edid_header[] = { |
| 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 |
| }; |
| static u8 edid_header[] = { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 }; |
| /** |
| * edid_is_valid - sanity check EDID data |
| 502,26 → 503,12 |
| } |
| return mode; |
| } |
| /* |
| * 0 is reserved. The spec says 0x01 fill for unused timings. Some old |
| * monitors fill with ascii space (0x20) instead. |
| */ |
| static int |
| bad_std_timing(u8 a, u8 b) |
| { |
| return (a == 0x00 && b == 0x00) || |
| (a == 0x01 && b == 0x01) || |
| (a == 0x20 && b == 0x20); |
| } |
| /** |
| * drm_mode_std - convert standard mode info (width, height, refresh) into mode |
| * @t: standard timing params |
| * @timing_level: standard timing level |
| * |
| * Take the standard timing params (in this case width, aspect, and refresh) |
| * and convert them into a real mode using CVT/GTF/DMT. |
| * and convert them into a real mode using CVT. |
| * |
| * Punts for now, but should eventually use the FB layer's CVT based mode |
| * generation code. |
| 528,7 → 515,6 |
| */ |
| struct drm_display_mode *drm_mode_std(struct drm_device *dev, |
| struct std_timing *t, |
| int revision, |
| int timing_level) |
| { |
| struct drm_display_mode *mode; |
| 539,20 → 525,15 |
| unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) |
| >> EDID_TIMING_VFREQ_SHIFT; |
| if (bad_std_timing(t->hsize, t->vfreq_aspect)) |
| return NULL; |
| /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ |
| hsize = t->hsize * 8 + 248; |
| /* vrefresh_rate = vfreq + 60 */ |
| vrefresh_rate = vfreq + 60; |
| /* the vdisplay is calculated based on the aspect ratio */ |
| if (aspect_ratio == 0) { |
| if (revision < 3) |
| vsize = hsize; |
| else |
| if (aspect_ratio == 0) |
| vsize = (hsize * 10) / 16; |
| } else if (aspect_ratio == 1) |
| else if (aspect_ratio == 1) |
| vsize = (hsize * 3) / 4; |
| else if (aspect_ratio == 2) |
| vsize = (hsize * 4) / 5; |
| 560,8 → 541,7 |
| vsize = (hsize * 9) / 16; |
| /* HDTV hack */ |
| if (hsize == 1360 && vsize == 765 && vrefresh_rate == 60) { |
| mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, |
| false); |
| mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); |
| mode->hdisplay = 1366; |
| mode->vsync_start = mode->vsync_start - 1; |
| mode->vsync_end = mode->vsync_end - 1; |
| 580,8 → 560,7 |
| mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); |
| break; |
| case LEVEL_CVT: |
| mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, |
| false); |
| mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); |
| break; |
| } |
| return mode; |
| 803,7 → 782,7 |
| continue; |
| newmode = drm_mode_std(dev, &edid->standard_timings[i], |
| edid->revision, timing_level); |
| timing_level); |
| if (newmode) { |
| drm_mode_probed_add(connector, newmode); |
| modes++; |
| 853,13 → 832,13 |
| case EDID_DETAIL_MONITOR_CPDATA: |
| break; |
| case EDID_DETAIL_STD_MODES: |
| for (j = 0; j < 6; i++) { |
| /* Five modes per detailed section */ |
| for (j = 0; j < 5; i++) { |
| struct std_timing *std; |
| struct drm_display_mode *newmode; |
| std = &data->data.timings[j]; |
| newmode = drm_mode_std(dev, std, |
| edid->revision, |
| timing_level); |
| if (newmode) { |
| drm_mode_probed_add(connector, newmode); |
| 988,9 → 967,7 |
| struct drm_display_mode *newmode; |
| std = &data->data.timings[j]; |
| newmode = drm_mode_std(dev, std, |
| edid->revision, |
| timing_level); |
| newmode = drm_mode_std(dev, std, timing_level); |
| if (newmode) { |
| drm_mode_probed_add(connector, newmode); |
| modes++; |
| 1037,6 → 1014,7 |
| if (i2c_transfer(adapter, msgs, 2) == 2) |
| return 0; |
| // dev_info(&adapter->dev, "unable to read EDID block.\n"); |
| return -1; |
| } |
| EXPORT_SYMBOL(drm_do_probe_ddc_edid); |
| /drivers/video/drm/drm_fb_helper.c |
|---|
| 40,16 → 40,6 |
| static LIST_HEAD(kernel_fb_helper_list); |
| int drm_fb_helper_add_connector(struct drm_connector *connector) |
| { |
| connector->fb_helper_private = kzalloc(sizeof(struct drm_fb_helper_connector), GFP_KERNEL); |
| if (!connector->fb_helper_private) |
| return -ENOMEM; |
| return 0; |
| } |
| EXPORT_SYMBOL(drm_fb_helper_add_connector); |
| bool drm_fb_helper_force_kernel_mode(void) |
| { |
| int i = 0; |
| 240,96 → 230,6 |
| } |
| EXPORT_SYMBOL(drm_fb_helper_init_crtc_count); |
| static void setcolreg(struct drm_crtc *crtc, u16 red, u16 green, |
| u16 blue, u16 regno, struct fb_info *info) |
| { |
| struct drm_fb_helper *fb_helper = info->par; |
| struct drm_framebuffer *fb = fb_helper->fb; |
| int pindex; |
| pindex = regno; |
| if (fb->bits_per_pixel == 16) { |
| pindex = regno << 3; |
| if (fb->depth == 16 && regno > 63) |
| return; |
| if (fb->depth == 15 && regno > 31) |
| return; |
| if (fb->depth == 16) { |
| u16 r, g, b; |
| int i; |
| if (regno < 32) { |
| for (i = 0; i < 8; i++) |
| fb_helper->funcs->gamma_set(crtc, red, |
| green, blue, pindex + i); |
| } |
| fb_helper->funcs->gamma_get(crtc, &r, |
| &g, &b, |
| pindex >> 1); |
| for (i = 0; i < 4; i++) |
| fb_helper->funcs->gamma_set(crtc, r, |
| green, b, |
| (pindex >> 1) + i); |
| } |
| } |
| if (fb->depth != 16) |
| fb_helper->funcs->gamma_set(crtc, red, green, blue, pindex); |
| if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) { |
| ((u32 *) fb->pseudo_palette)[regno] = |
| (regno << info->var.red.offset) | |
| (regno << info->var.green.offset) | |
| (regno << info->var.blue.offset); |
| } |
| } |
| int drm_fb_helper_setcmap(struct fb_cmap *cmap, struct fb_info *info) |
| { |
| struct drm_fb_helper *fb_helper = info->par; |
| struct drm_device *dev = fb_helper->dev; |
| u16 *red, *green, *blue, *transp; |
| struct drm_crtc *crtc; |
| int i, rc = 0; |
| int start; |
| list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; |
| for (i = 0; i < fb_helper->crtc_count; i++) { |
| if (crtc->base.id == fb_helper->crtc_info[i].crtc_id) |
| break; |
| } |
| if (i == fb_helper->crtc_count) |
| continue; |
| red = cmap->red; |
| green = cmap->green; |
| blue = cmap->blue; |
| transp = cmap->transp; |
| start = cmap->start; |
| for (i = 0; i < cmap->len; i++) { |
| u16 hred, hgreen, hblue, htransp = 0xffff; |
| hred = *red++; |
| hgreen = *green++; |
| hblue = *blue++; |
| if (transp) |
| htransp = *transp++; |
| setcolreg(crtc, hred, hgreen, hblue, start++, info); |
| } |
| crtc_funcs->load_lut(crtc); |
| } |
| return rc; |
| } |
| EXPORT_SYMBOL(drm_fb_helper_setcmap); |
| int drm_fb_helper_setcolreg(unsigned regno, |
| unsigned red, |
| unsigned green, |
| 342,11 → 242,9 |
| struct drm_crtc *crtc; |
| int i; |
| if (regno > 255) |
| return 1; |
| list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| struct drm_framebuffer *fb = fb_helper->fb; |
| list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; |
| for (i = 0; i < fb_helper->crtc_count; i++) { |
| if (crtc->base.id == fb_helper->crtc_info[i].crtc_id) |
| break; |
| 354,10 → 252,36 |
| if (i == fb_helper->crtc_count) |
| continue; |
| if (regno > 255) |
| return 1; |
| setcolreg(crtc, red, green, blue, regno, info); |
| crtc_funcs->load_lut(crtc); |
| if (fb->depth == 8) { |
| fb_helper->funcs->gamma_set(crtc, red, green, blue, regno); |
| return 0; |
| } |
| if (regno < 16) { |
| switch (fb->depth) { |
| case 15: |
| fb->pseudo_palette[regno] = ((red & 0xf800) >> 1) | |
| ((green & 0xf800) >> 6) | |
| ((blue & 0xf800) >> 11); |
| break; |
| case 16: |
| fb->pseudo_palette[regno] = (red & 0xf800) | |
| ((green & 0xfc00) >> 5) | |
| ((blue & 0xf800) >> 11); |
| break; |
| case 24: |
| case 32: |
| fb->pseudo_palette[regno] = |
| (((red >> 8) & 0xff) << info->var.red.offset) | |
| (((green >> 8) & 0xff) << info->var.green.offset) | |
| (((blue >> 8) & 0xff) << info->var.blue.offset); |
| break; |
| } |
| } |
| } |
| return 0; |
| } |
| EXPORT_SYMBOL(drm_fb_helper_setcolreg); |
| 526,14 → 450,11 |
| EXPORT_SYMBOL(drm_fb_helper_pan_display); |
| int drm_fb_helper_single_fb_probe(struct drm_device *dev, |
| int preferred_bpp, |
| int (*fb_create)(struct drm_device *dev, |
| uint32_t fb_width, |
| uint32_t fb_height, |
| uint32_t surface_width, |
| uint32_t surface_height, |
| uint32_t surface_depth, |
| uint32_t surface_bpp, |
| struct drm_framebuffer **fb_ptr)) |
| { |
| struct drm_crtc *crtc; |
| 547,48 → 468,8 |
| struct drm_framebuffer *fb; |
| struct drm_mode_set *modeset = NULL; |
| struct drm_fb_helper *fb_helper; |
| uint32_t surface_depth = 24, surface_bpp = 32; |
| /* if driver picks 8 or 16 by default use that |
| for both depth/bpp */ |
| if (preferred_bpp != surface_bpp) { |
| surface_depth = surface_bpp = preferred_bpp; |
| } |
| /* first up get a count of crtcs now in use and new min/maxes width/heights */ |
| list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| struct drm_fb_helper_connector *fb_help_conn = connector->fb_helper_private; |
| struct drm_fb_helper_cmdline_mode *cmdline_mode; |
| if (!fb_help_conn) |
| continue; |
| cmdline_mode = &fb_help_conn->cmdline_mode; |
| if (cmdline_mode->bpp_specified) { |
| switch (cmdline_mode->bpp) { |
| case 8: |
| surface_depth = surface_bpp = 8; |
| break; |
| case 15: |
| surface_depth = 15; |
| surface_bpp = 16; |
| break; |
| case 16: |
| surface_depth = surface_bpp = 16; |
| break; |
| case 24: |
| surface_depth = surface_bpp = 24; |
| break; |
| case 32: |
| surface_depth = 24; |
| surface_bpp = 32; |
| break; |
| } |
| break; |
| } |
| } |
| list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
| if (drm_helper_crtc_in_use(crtc)) { |
| if (crtc->desired_mode) { |
| 617,8 → 498,7 |
| /* do we have an fb already? */ |
| if (list_empty(&dev->mode_config.fb_kernel_list)) { |
| ret = (*fb_create)(dev, fb_width, fb_height, surface_width, |
| surface_height, surface_depth, surface_bpp, |
| &fb); |
| surface_height, &fb); |
| if (ret) |
| return -EINVAL; |
| new_fb = 1; |
| 697,12 → 577,10 |
| } |
| EXPORT_SYMBOL(drm_fb_helper_free); |
| void drm_fb_helper_fill_fix(struct fb_info *info, uint32_t pitch, |
| uint32_t depth) |
| void drm_fb_helper_fill_fix(struct fb_info *info, uint32_t pitch) |
| { |
| info->fix.type = FB_TYPE_PACKED_PIXELS; |
| info->fix.visual = depth == 8 ? FB_VISUAL_PSEUDOCOLOR : |
| FB_VISUAL_DIRECTCOLOR; |
| info->fix.visual = FB_VISUAL_TRUECOLOR; |
| info->fix.type_aux = 0; |
| info->fix.xpanstep = 1; /* doing it in hw */ |
| info->fix.ypanstep = 1; /* doing it in hw */ |
| /drivers/video/drm/drm_modes.c |
|---|
| 88,7 → 88,7 |
| #define HV_FACTOR 1000 |
| struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, int hdisplay, |
| int vdisplay, int vrefresh, |
| bool reduced, bool interlaced, bool margins) |
| bool reduced, bool interlaced) |
| { |
| /* 1) top/bottom margin size (% of height) - default: 1.8, */ |
| #define CVT_MARGIN_PERCENTAGE 18 |
| 101,6 → 101,7 |
| /* Pixel Clock step (kHz) */ |
| #define CVT_CLOCK_STEP 250 |
| struct drm_display_mode *drm_mode; |
| bool margins = false; |
| unsigned int vfieldrate, hperiod; |
| int hdisplay_rnd, hmargin, vdisplay_rnd, vmargin, vsync; |
| int interlace; |
| /drivers/video/drm/include/drm.h |
|---|
| 0,0 → 1,747 |
| /** |
| * \file drm.h |
| * Header for the Direct Rendering Manager |
| * |
| * \author Rickard E. (Rik) Faith <faith@valinux.com> |
| * |
| * \par Acknowledgments: |
| * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg. |
| */ |
| /* |
| * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. |
| * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. |
| * All rights reserved. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| #ifndef _DRM_H_ |
| #define _DRM_H_ |
| #include <linux/types.h> |
| #include <errno-base.h> |
| //#include <asm/ioctl.h> /* For _IO* macros */ |
| #define DRM_MAJOR 226 |
| #define DRM_MAX_MINOR 15 |
| #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ |
| #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ |
| #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ |
| #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */ |
| #define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ |
| #define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ |
| #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) |
| #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) |
| #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) |
| typedef unsigned int drm_handle_t; |
| typedef unsigned int drm_context_t; |
| typedef unsigned int drm_drawable_t; |
| typedef unsigned int drm_magic_t; |
| /** |
| * Cliprect. |
| * |
| * \warning: If you change this structure, make sure you change |
| * XF86DRIClipRectRec in the server as well |
| * |
| * \note KW: Actually it's illegal to change either for |
| * backwards-compatibility reasons. |
| */ |
| struct drm_clip_rect { |
| unsigned short x1; |
| unsigned short y1; |
| unsigned short x2; |
| unsigned short y2; |
| }; |
| /** |
| * Drawable information. |
| */ |
| struct drm_drawable_info { |
| unsigned int num_rects; |
| struct drm_clip_rect *rects; |
| }; |
| /** |
| * Texture region, |
| */ |
| struct drm_tex_region { |
| unsigned char next; |
| unsigned char prev; |
| unsigned char in_use; |
| unsigned char padding; |
| unsigned int age; |
| }; |
| /** |
| * Hardware lock. |
| * |
| * The lock structure is a simple cache-line aligned integer. To avoid |
| * processor bus contention on a multiprocessor system, there should not be any |
| * other data stored in the same cache line. |
| */ |
| struct drm_hw_lock { |
| __volatile__ unsigned int lock; /**< lock variable */ |
| char padding[60]; /**< Pad to cache line */ |
| }; |
| /** |
| * DRM_IOCTL_VERSION ioctl argument type. |
| * |
| * \sa drmGetVersion(). |
| */ |
| struct drm_version { |
| int version_major; /**< Major version */ |
| int version_minor; /**< Minor version */ |
| int version_patchlevel; /**< Patch level */ |
| size_t name_len; /**< Length of name buffer */ |
| char __user *name; /**< Name of driver */ |
| size_t date_len; /**< Length of date buffer */ |
| char __user *date; /**< User-space buffer to hold date */ |
| size_t desc_len; /**< Length of desc buffer */ |
| char __user *desc; /**< User-space buffer to hold desc */ |
| }; |
| /** |
| * DRM_IOCTL_GET_UNIQUE ioctl argument type. |
| * |
| * \sa drmGetBusid() and drmSetBusId(). |
| */ |
| struct drm_unique { |
| size_t unique_len; /**< Length of unique */ |
| char __user *unique; /**< Unique name for driver instantiation */ |
| }; |
| struct drm_list { |
| int count; /**< Length of user-space structures */ |
| struct drm_version __user *version; |
| }; |
| struct drm_block { |
| int unused; |
| }; |
| /** |
| * DRM_IOCTL_CONTROL ioctl argument type. |
| * |
| * \sa drmCtlInstHandler() and drmCtlUninstHandler(). |
| */ |
| struct drm_control { |
| enum { |
| DRM_ADD_COMMAND, |
| DRM_RM_COMMAND, |
| DRM_INST_HANDLER, |
| DRM_UNINST_HANDLER |
| } func; |
| int irq; |
| }; |
| /** |
| * Type of memory to map. |
| */ |
| enum drm_map_type { |
| _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ |
| _DRM_REGISTERS = 1, /**< no caching, no core dump */ |
| _DRM_SHM = 2, /**< shared, cached */ |
| _DRM_AGP = 3, /**< AGP/GART */ |
| _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */ |
| _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */ |
| _DRM_GEM = 6, /**< GEM object */ |
| }; |
| /** |
| * Memory mapping flags. |
| */ |
| enum drm_map_flags { |
| _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ |
| _DRM_READ_ONLY = 0x02, |
| _DRM_LOCKED = 0x04, /**< shared, cached, locked */ |
| _DRM_KERNEL = 0x08, /**< kernel requires access */ |
| _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ |
| _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ |
| _DRM_REMOVABLE = 0x40, /**< Removable mapping */ |
| _DRM_DRIVER = 0x80 /**< Managed by driver */ |
| }; |
| struct drm_ctx_priv_map { |
| unsigned int ctx_id; /**< Context requesting private mapping */ |
| void *handle; /**< Handle of map */ |
| }; |
| /** |
| * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls |
| * argument type. |
| * |
| * \sa drmAddMap(). |
| */ |
| struct drm_map { |
| unsigned long offset; /**< Requested physical address (0 for SAREA)*/ |
| unsigned long size; /**< Requested physical size (bytes) */ |
| enum drm_map_type type; /**< Type of memory to map */ |
| enum drm_map_flags flags; /**< Flags */ |
| void *handle; /**< User-space: "Handle" to pass to mmap() */ |
| /**< Kernel-space: kernel-virtual address */ |
| int mtrr; /**< MTRR slot used */ |
| /* Private data */ |
| }; |
| /** |
| * DRM_IOCTL_GET_CLIENT ioctl argument type. |
| */ |
| struct drm_client { |
| int idx; /**< Which client desired? */ |
| int auth; /**< Is client authenticated? */ |
| unsigned long pid; /**< Process ID */ |
| unsigned long uid; /**< User ID */ |
| unsigned long magic; /**< Magic */ |
| unsigned long iocs; /**< Ioctl count */ |
| }; |
| enum drm_stat_type { |
| _DRM_STAT_LOCK, |
| _DRM_STAT_OPENS, |
| _DRM_STAT_CLOSES, |
| _DRM_STAT_IOCTLS, |
| _DRM_STAT_LOCKS, |
| _DRM_STAT_UNLOCKS, |
| _DRM_STAT_VALUE, /**< Generic value */ |
| _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */ |
| _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */ |
| _DRM_STAT_IRQ, /**< IRQ */ |
| _DRM_STAT_PRIMARY, /**< Primary DMA bytes */ |
| _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */ |
| _DRM_STAT_DMA, /**< DMA */ |
| _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ |
| _DRM_STAT_MISSED /**< Missed DMA opportunity */ |
| /* Add to the *END* of the list */ |
| }; |
| /** |
| * DRM_IOCTL_GET_STATS ioctl argument type. |
| */ |
| struct drm_stats { |
| unsigned long count; |
| struct { |
| unsigned long value; |
| enum drm_stat_type type; |
| } data[15]; |
| }; |
| /** |
| * Hardware locking flags. |
| */ |
| enum drm_lock_flags { |
| _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ |
| _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ |
| _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ |
| _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ |
| /* These *HALT* flags aren't supported yet |
| -- they will be used to support the |
| full-screen DGA-like mode. */ |
| _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ |
| _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ |
| }; |
| /** |
| * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. |
| * |
| * \sa drmGetLock() and drmUnlock(). |
| */ |
| struct drm_lock { |
| int context; |
| enum drm_lock_flags flags; |
| }; |
| /** |
| * DMA flags |
| * |
| * \warning |
| * These values \e must match xf86drm.h. |
| * |
| * \sa drm_dma. |
| */ |
| enum drm_dma_flags { |
| /* Flags for DMA buffer dispatch */ |
| _DRM_DMA_BLOCK = 0x01, /**< |
| * Block until buffer dispatched. |
| * |
| * \note The buffer may not yet have |
| * been processed by the hardware -- |
| * getting a hardware lock with the |
| * hardware quiescent will ensure |
| * that the buffer has been |
| * processed. |
| */ |
| _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ |
| _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ |
| /* Flags for DMA buffer request */ |
| _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ |
| _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ |
| _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ |
| }; |
| /** |
| * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. |
| * |
| * \sa drmAddBufs(). |
| */ |
| struct drm_buf_desc { |
| int count; /**< Number of buffers of this size */ |
| int size; /**< Size in bytes */ |
| int low_mark; /**< Low water mark */ |
| int high_mark; /**< High water mark */ |
| enum { |
| _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ |
| _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ |
| _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ |
| _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */ |
| _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */ |
| } flags; |
| unsigned long agp_start; /**< |
| * Start address of where the AGP buffers are |
| * in the AGP aperture |
| */ |
| }; |
| /** |
| * DRM_IOCTL_INFO_BUFS ioctl argument type. |
| */ |
| struct drm_buf_info { |
| int count; /**< Entries in list */ |
| struct drm_buf_desc __user *list; |
| }; |
| /** |
| * DRM_IOCTL_FREE_BUFS ioctl argument type. |
| */ |
| struct drm_buf_free { |
| int count; |
| int __user *list; |
| }; |
| /** |
| * Buffer information |
| * |
| * \sa drm_buf_map. |
| */ |
| struct drm_buf_pub { |
| int idx; /**< Index into the master buffer list */ |
| int total; /**< Buffer size */ |
| int used; /**< Amount of buffer in use (for DMA) */ |
| void __user *address; /**< Address of buffer */ |
| }; |
| /** |
| * DRM_IOCTL_MAP_BUFS ioctl argument type. |
| */ |
| struct drm_buf_map { |
| int count; /**< Length of the buffer list */ |
| void __user *virtual; /**< Mmap'd area in user-virtual */ |
| struct drm_buf_pub __user *list; /**< Buffer information */ |
| }; |
| /** |
| * DRM_IOCTL_DMA ioctl argument type. |
| * |
| * Indices here refer to the offset into the buffer list in drm_buf_get. |
| * |
| * \sa drmDMA(). |
| */ |
| struct drm_dma { |
| int context; /**< Context handle */ |
| int send_count; /**< Number of buffers to send */ |
| int __user *send_indices; /**< List of handles to buffers */ |
| int __user *send_sizes; /**< Lengths of data to send */ |
| enum drm_dma_flags flags; /**< Flags */ |
| int request_count; /**< Number of buffers requested */ |
| int request_size; /**< Desired size for buffers */ |
| int __user *request_indices; /**< Buffer information */ |
| int __user *request_sizes; |
| int granted_count; /**< Number of buffers granted */ |
| }; |
| enum drm_ctx_flags { |
| _DRM_CONTEXT_PRESERVED = 0x01, |
| _DRM_CONTEXT_2DONLY = 0x02 |
| }; |
| /** |
| * DRM_IOCTL_ADD_CTX ioctl argument type. |
| * |
| * \sa drmCreateContext() and drmDestroyContext(). |
| */ |
| struct drm_ctx { |
| drm_context_t handle; |
| enum drm_ctx_flags flags; |
| }; |
| /** |
| * DRM_IOCTL_RES_CTX ioctl argument type. |
| */ |
| struct drm_ctx_res { |
| int count; |
| struct drm_ctx __user *contexts; |
| }; |
| /** |
| * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. |
| */ |
| struct drm_draw { |
| drm_drawable_t handle; |
| }; |
| /** |
| * DRM_IOCTL_UPDATE_DRAW ioctl argument type. |
| */ |
| typedef enum { |
| DRM_DRAWABLE_CLIPRECTS, |
| } drm_drawable_info_type_t; |
| struct drm_update_draw { |
| drm_drawable_t handle; |
| unsigned int type; |
| unsigned int num; |
| unsigned long long data; |
| }; |
| /** |
| * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. |
| */ |
| struct drm_auth { |
| drm_magic_t magic; |
| }; |
| /** |
| * DRM_IOCTL_IRQ_BUSID ioctl argument type. |
| * |
| * \sa drmGetInterruptFromBusID(). |
| */ |
| struct drm_irq_busid { |
| int irq; /**< IRQ number */ |
| int busnum; /**< bus number */ |
| int devnum; /**< device number */ |
| int funcnum; /**< function number */ |
| }; |
| enum drm_vblank_seq_type { |
| _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ |
| _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ |
| _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */ |
| _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ |
| _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ |
| _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */ |
| }; |
| #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) |
| #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | \ |
| _DRM_VBLANK_NEXTONMISS) |
| struct drm_wait_vblank_request { |
| enum drm_vblank_seq_type type; |
| unsigned int sequence; |
| unsigned long signal; |
| }; |
| struct drm_wait_vblank_reply { |
| enum drm_vblank_seq_type type; |
| unsigned int sequence; |
| long tval_sec; |
| long tval_usec; |
| }; |
| /** |
| * DRM_IOCTL_WAIT_VBLANK ioctl argument type. |
| * |
| * \sa drmWaitVBlank(). |
| */ |
| union drm_wait_vblank { |
| struct drm_wait_vblank_request request; |
| struct drm_wait_vblank_reply reply; |
| }; |
| #define _DRM_PRE_MODESET 1 |
| #define _DRM_POST_MODESET 2 |
| /** |
| * DRM_IOCTL_MODESET_CTL ioctl argument type |
| * |
| * \sa drmModesetCtl(). |
| */ |
| struct drm_modeset_ctl { |
| __u32 crtc; |
| __u32 cmd; |
| }; |
| /** |
| * DRM_IOCTL_AGP_ENABLE ioctl argument type. |
| * |
| * \sa drmAgpEnable(). |
| */ |
| struct drm_agp_mode { |
| unsigned long mode; /**< AGP mode */ |
| }; |
| /** |
| * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. |
| * |
| * \sa drmAgpAlloc() and drmAgpFree(). |
| */ |
| struct drm_agp_buffer { |
| unsigned long size; /**< In bytes -- will round to page boundary */ |
| unsigned long handle; /**< Used for binding / unbinding */ |
| unsigned long type; /**< Type of memory to allocate */ |
| unsigned long physical; /**< Physical used by i810 */ |
| }; |
| /** |
| * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. |
| * |
| * \sa drmAgpBind() and drmAgpUnbind(). |
| */ |
| struct drm_agp_binding { |
| unsigned long handle; /**< From drm_agp_buffer */ |
| unsigned long offset; /**< In bytes -- will round to page boundary */ |
| }; |
| /** |
| * DRM_IOCTL_AGP_INFO ioctl argument type. |
| * |
| * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), |
| * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), |
| * drmAgpVendorId() and drmAgpDeviceId(). |
| */ |
| struct drm_agp_info { |
| int agp_version_major; |
| int agp_version_minor; |
| unsigned long mode; |
| unsigned long aperture_base; /* physical address */ |
| unsigned long aperture_size; /* bytes */ |
| unsigned long memory_allowed; /* bytes */ |
| unsigned long memory_used; |
| /* PCI information */ |
| unsigned short id_vendor; |
| unsigned short id_device; |
| }; |
| /** |
| * DRM_IOCTL_SG_ALLOC ioctl argument type. |
| */ |
| struct drm_scatter_gather { |
| unsigned long size; /**< In bytes -- will round to page boundary */ |
| unsigned long handle; /**< Used for mapping / unmapping */ |
| }; |
| /** |
| * DRM_IOCTL_SET_VERSION ioctl argument type. |
| */ |
| struct drm_set_version { |
| int drm_di_major; |
| int drm_di_minor; |
| int drm_dd_major; |
| int drm_dd_minor; |
| }; |
| /** DRM_IOCTL_GEM_CLOSE ioctl argument type */ |
| struct drm_gem_close { |
| /** Handle of the object to be closed. */ |
| __u32 handle; |
| __u32 pad; |
| }; |
| /** DRM_IOCTL_GEM_FLINK ioctl argument type */ |
| struct drm_gem_flink { |
| /** Handle for the object being named */ |
| __u32 handle; |
| /** Returned global name */ |
| __u32 name; |
| }; |
| /** DRM_IOCTL_GEM_OPEN ioctl argument type */ |
| struct drm_gem_open { |
| /** Name of object being opened */ |
| __u32 name; |
| /** Returned handle for the object */ |
| __u32 handle; |
| /** Returned size of the object */ |
| __u64 size; |
| }; |
| #include "drm_mode.h" |
| /* |
| #define DRM_IOCTL_BASE 'd' |
| #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) |
| #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) |
| #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) |
| #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) |
| #define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version) |
| #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique) |
| #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth) |
| #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid) |
| #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map) |
| #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client) |
| #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats) |
| #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version) |
| #define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl) |
| #define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close) |
| #define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink) |
| #define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open) |
| #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique) |
| #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth) |
| #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block) |
| #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block) |
| #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control) |
| #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map) |
| #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc) |
| #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc) |
| #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info) |
| #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map) |
| #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free) |
| #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map) |
| #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map) |
| #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map) |
| #define DRM_IOCTL_SET_MASTER DRM_IO(0x1e) |
| #define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f) |
| #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx) |
| #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx) |
| #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx) |
| #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx) |
| #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx) |
| #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx) |
| #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res) |
| #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw) |
| #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw) |
| #define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma) |
| #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock) |
| #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock) |
| #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock) |
| #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) |
| #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) |
| #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode) |
| #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info) |
| #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer) |
| #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer) |
| #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) |
| #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) |
| #define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather) |
| #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) |
| #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) |
| #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw) |
| #define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res) |
| #define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc) |
| #define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc) |
| #define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor) |
| #define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut) |
| #define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut) |
| #define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder) |
| #define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector) |
| #define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd) |
| #define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) |
| #define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property) |
| #define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property) |
| #define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob) |
| #define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd) |
| #define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd) |
| #define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int) |
| */ |
| /** |
| * Device specific ioctls should only be in their respective headers |
| * The device specific ioctl range is from 0x40 to 0x99. |
| * Generic IOCTLS restart at 0xA0. |
| * |
| * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and |
| * drmCommandReadWrite(). |
| */ |
| #define DRM_COMMAND_BASE 0x40 |
| #define DRM_COMMAND_END 0xA0 |
| /* typedef area */ |
| #ifndef __KERNEL__ |
| typedef struct drm_clip_rect drm_clip_rect_t; |
| typedef struct drm_drawable_info drm_drawable_info_t; |
| typedef struct drm_tex_region drm_tex_region_t; |
| typedef struct drm_hw_lock drm_hw_lock_t; |
| typedef struct drm_version drm_version_t; |
| typedef struct drm_unique drm_unique_t; |
| typedef struct drm_list drm_list_t; |
| typedef struct drm_block drm_block_t; |
| typedef struct drm_control drm_control_t; |
| typedef enum drm_map_type drm_map_type_t; |
| typedef enum drm_map_flags drm_map_flags_t; |
| typedef struct drm_ctx_priv_map drm_ctx_priv_map_t; |
| typedef struct drm_map drm_map_t; |
| typedef struct drm_client drm_client_t; |
| typedef enum drm_stat_type drm_stat_type_t; |
| typedef struct drm_stats drm_stats_t; |
| typedef enum drm_lock_flags drm_lock_flags_t; |
| typedef struct drm_lock drm_lock_t; |
| typedef enum drm_dma_flags drm_dma_flags_t; |
| typedef struct drm_buf_desc drm_buf_desc_t; |
| typedef struct drm_buf_info drm_buf_info_t; |
| typedef struct drm_buf_free drm_buf_free_t; |
| typedef struct drm_buf_pub drm_buf_pub_t; |
| typedef struct drm_buf_map drm_buf_map_t; |
| typedef struct drm_dma drm_dma_t; |
| typedef union drm_wait_vblank drm_wait_vblank_t; |
| typedef struct drm_agp_mode drm_agp_mode_t; |
| typedef enum drm_ctx_flags drm_ctx_flags_t; |
| typedef struct drm_ctx drm_ctx_t; |
| typedef struct drm_ctx_res drm_ctx_res_t; |
| typedef struct drm_draw drm_draw_t; |
| typedef struct drm_update_draw drm_update_draw_t; |
| typedef struct drm_auth drm_auth_t; |
| typedef struct drm_irq_busid drm_irq_busid_t; |
| typedef enum drm_vblank_seq_type drm_vblank_seq_type_t; |
| typedef struct drm_agp_buffer drm_agp_buffer_t; |
| typedef struct drm_agp_binding drm_agp_binding_t; |
| typedef struct drm_agp_info drm_agp_info_t; |
| typedef struct drm_scatter_gather drm_scatter_gather_t; |
| typedef struct drm_set_version drm_set_version_t; |
| #endif |
| #define mutex_lock(x) |
| #define mutex_unlock(x) |
| #endif |
| /drivers/video/drm/include/linux/kernel.h |
|---|
| File deleted |
| /drivers/video/drm/include/linux/firmware.h |
|---|
| File deleted |
| /drivers/video/drm/include/linux/module.h |
|---|
| 3,4 → 3,3 |
| #include <list.h> |
| #include <syscall.h> |
| #define MODULE_FIRMWARE(x) |
| /drivers/video/drm/include/linux/types.h |
|---|
| 35,7 → 35,6 |
| typedef signed int __s32; |
| typedef signed long long __s64; |
| typedef __u32 __be32; |
| typedef unsigned char uint8_t; |
| typedef unsigned short uint16_t; |
| 201,23 → 200,21 |
| (void) (&_x == &_y); \ |
| _x > _y ? _x : _y; }) |
| #define do_div(n, base) \ |
| ({ \ |
| unsigned long __upper, __low, __high, __mod, __base; \ |
| __base = (base); \ |
| asm("":"=a" (__low), "=d" (__high) : "A" (n)); \ |
| __upper = __high; \ |
| if (__high) { \ |
| __upper = __high % (__base); \ |
| __high = __high / (__base); \ |
| } \ |
| asm("divl %2":"=a" (__low), "=d" (__mod) \ |
| : "rm" (__base), "0" (__low), "1" (__upper)); \ |
| asm("":"=A" (n) : "a" (__low), "d" (__high)); \ |
| __mod; \ |
| extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor); |
| # define do_div(n,base) ({ \ |
| uint32_t __base = (base); \ |
| uint32_t __rem; \ |
| (void)(((typeof((n)) *)0) == ((uint64_t *)0)); \ |
| if (likely(((n) >> 32) == 0)) { \ |
| __rem = (uint32_t)(n) % __base; \ |
| (n) = (uint32_t)(n) / __base; \ |
| } else \ |
| __rem = __div64_32(&(n), __base); \ |
| __rem; \ |
| }) |
| #define lower_32_bits(n) ((u32)(n)) |
| #define INT_MAX ((int)(~0U>>1)) |
| /drivers/video/drm/include/syscall.h |
|---|
| 42,8 → 42,6 |
| #define PG_NOCACHE 0x018 |
| void* STDCALL AllocKernelSpace(size_t size)__asm__("AllocKernelSpace"); |
| void STDCALL FreeKernelSpace(void *mem)__asm__("FreeKernelSpace"); |
| addr_t STDCALL MapIoMem(addr_t base, size_t size, u32_t flags)__asm__("MapIoMem"); |
| void* STDCALL KernelAlloc(size_t size)__asm__("KernelAlloc"); |
| void* STDCALL KernelFree(void *mem)__asm__("KernelFree"); |
| void* STDCALL UserAlloc(size_t size)__asm__("UserAlloc"); |
| 58,6 → 56,11 |
| int STDCALL AttachIntHandler(int irq, void *handler, u32_t access) __asm__("AttachIntHandler"); |
| //void *CreateObject(u32 pid, size_t size); |
| //void *DestroyObject(void *obj); |
| addr_t STDCALL MapIoMem(addr_t base, size_t size, u32_t flags)__asm__("MapIoMem"); |
| /////////////////////////////////////////////////////////////////////////////// |
| void STDCALL SetMouseData(int btn, int x, int y, |
| 164,30 → 167,26 |
| { |
| if( !delay ) |
| delay++; |
| delay*= 128; |
| delay*=1000; |
| while(delay--) |
| { |
| __asm__ __volatile__( |
| "xorl %%eax, %%eax \n\t" |
| "cpuid \n\t" |
| "xorl %%eax, %%eax" |
| :::"ebx","ecx","edx"); |
| :::"eax","ebx","ecx","edx"); |
| }; |
| }; |
| static inline void udelay(u32_t delay) |
| { |
| if(!delay) delay++; |
| delay*= 128; |
| delay*=500; |
| while(delay--) |
| { |
| __asm__ __volatile__( |
| "xorl %%eax, %%eax \n\t" |
| "cpuid \n\t" |
| "xorl %%eax, %%eax" |
| :::"ebx","ecx","edx" ); |
| "cpuid" |
| :::"eax","ebx","ecx","edx" ); |
| } |
| } |
| 205,7 → 204,7 |
| }; |
| static inline u32_t __PciApi(int cmd) |
| extern inline u32_t __PciApi(int cmd) |
| { |
| u32_t retval; |
| 217,7 → 216,7 |
| return retval; |
| }; |
| static inline void* __CreateObject(u32_t pid, size_t size) |
| extern inline void* __CreateObject(u32_t pid, size_t size) |
| { |
| void *retval; |
| 229,7 → 228,7 |
| return retval; |
| } |
| static inline void *__DestroyObject(void *obj) |
| extern inline void *__DestroyObject(void *obj) |
| { |
| __asm__ __volatile__ ( |
| "call *__imp__DestroyObject" |
| 257,7 → 256,7 |
| }; |
| */ |
| static inline u32_t safe_cli(void) |
| extern inline u32_t safe_cli(void) |
| { |
| u32_t ifl; |
| __asm__ __volatile__ ( |
| 268,7 → 267,7 |
| return ifl; |
| } |
| static inline void safe_sti(u32_t ifl) |
| extern inline void safe_sti(u32_t ifl) |
| { |
| __asm__ __volatile__ ( |
| "pushl %0\n\t" |
| 277,7 → 276,7 |
| ); |
| } |
| static inline void __clear (void * dst, unsigned len) |
| extern inline void __clear (void * dst, unsigned len) |
| { |
| u32_t tmp; |
| __asm__ __volatile__ ( |
| 289,25 → 288,25 |
| __asm__ __volatile__ ("":::"ecx","edi"); |
| }; |
| static inline void out8(const u16_t port, const u8_t val) |
| extern inline void out8(const u16_t port, const u8_t val) |
| { |
| __asm__ __volatile__ |
| ("outb %1, %0\n" : : "dN"(port), "a"(val)); |
| } |
| static inline void out16(const u16_t port, const u16_t val) |
| extern inline void out16(const u16_t port, const u16_t val) |
| { |
| __asm__ __volatile__ |
| ("outw %1, %0\n" : : "dN"(port), "a"(val)); |
| } |
| static inline void out32(const u16_t port, const u32_t val) |
| extern inline void out32(const u16_t port, const u32_t val) |
| { |
| __asm__ __volatile__ |
| ("outl %1, %0\n" : : "dN"(port), "a"(val)); |
| } |
| static inline u8_t in8(const u16_t port) |
| extern inline u8_t in8(const u16_t port) |
| { |
| u8_t tmp; |
| __asm__ __volatile__ |
| 315,7 → 314,7 |
| return tmp; |
| }; |
| static inline u16_t in16(const u16_t port) |
| extern inline u16_t in16(const u16_t port) |
| { |
| u16_t tmp; |
| __asm__ __volatile__ |
| 323,7 → 322,7 |
| return tmp; |
| }; |
| static inline u32_t in32(const u16_t port) |
| extern inline u32_t in32(const u16_t port) |
| { |
| u32_t tmp; |
| __asm__ __volatile__ |
| 331,7 → 330,7 |
| return tmp; |
| }; |
| static inline void delay(int time) |
| extern inline void delay(int time) |
| { |
| __asm__ __volatile__ ( |
| "call *__imp__Delay" |
| 341,7 → 340,7 |
| } |
| static inline void change_task() |
| extern inline void change_task() |
| { |
| __asm__ __volatile__ ( |
| "call *__imp__ChangeTask"); |
| /drivers/video/drm/include/drm_edid.h |
|---|
| 0,0 → 1,198 |
| /* |
| * Copyright © 2007-2008 Intel Corporation |
| * Jesse Barnes <jesse.barnes@intel.com> |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| #ifndef __DRM_EDID_H__ |
| #define __DRM_EDID_H__ |
| #include <types.h> |
| #define EDID_LENGTH 128 |
| #define DDC_ADDR 0x50 |
| struct est_timings { |
| u8 t1; |
| u8 t2; |
| u8 mfg_rsvd; |
| } __attribute__((packed)); |
| /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */ |
| #define EDID_TIMING_ASPECT_SHIFT 6 |
| #define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT) |
| /* need to add 60 */ |
| #define EDID_TIMING_VFREQ_SHIFT 0 |
| #define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT) |
| struct std_timing { |
| u8 hsize; /* need to multiply by 8 then add 248 */ |
| u8 vfreq_aspect; |
| } __attribute__((packed)); |
| #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) |
| #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2) |
| #define DRM_EDID_PT_SEPARATE_SYNC (3 << 3) |
| #define DRM_EDID_PT_STEREO (1 << 5) |
| #define DRM_EDID_PT_INTERLACED (1 << 7) |
| /* If detailed data is pixel timing */ |
| struct detailed_pixel_timing { |
| u8 hactive_lo; |
| u8 hblank_lo; |
| u8 hactive_hblank_hi; |
| u8 vactive_lo; |
| u8 vblank_lo; |
| u8 vactive_vblank_hi; |
| u8 hsync_offset_lo; |
| u8 hsync_pulse_width_lo; |
| u8 vsync_offset_pulse_width_lo; |
| u8 hsync_vsync_offset_pulse_width_hi; |
| u8 width_mm_lo; |
| u8 height_mm_lo; |
| u8 width_height_mm_hi; |
| u8 hborder; |
| u8 vborder; |
| u8 misc; |
| } __attribute__((packed)); |
| /* If it's not pixel timing, it'll be one of the below */ |
| struct detailed_data_string { |
| u8 str[13]; |
| } __attribute__((packed)); |
| struct detailed_data_monitor_range { |
| u8 min_vfreq; |
| u8 max_vfreq; |
| u8 min_hfreq_khz; |
| u8 max_hfreq_khz; |
| u8 pixel_clock_mhz; /* need to multiply by 10 */ |
| u16 sec_gtf_toggle; /* A000=use above, 20=use below */ |
| u8 hfreq_start_khz; /* need to multiply by 2 */ |
| u8 c; /* need to divide by 2 */ |
| u16 m; |
| u8 k; |
| u8 j; /* need to divide by 2 */ |
| } __attribute__((packed)); |
| struct detailed_data_wpindex { |
| u8 white_yx_lo; /* Lower 2 bits each */ |
| u8 white_x_hi; |
| u8 white_y_hi; |
| u8 gamma; /* need to divide by 100 then add 1 */ |
| } __attribute__((packed)); |
| struct detailed_data_color_point { |
| u8 windex1; |
| u8 wpindex1[3]; |
| u8 windex2; |
| u8 wpindex2[3]; |
| } __attribute__((packed)); |
| struct detailed_non_pixel { |
| u8 pad1; |
| u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name |
| fb=color point data, fa=standard timing data, |
| f9=undefined, f8=mfg. reserved */ |
| u8 pad2; |
| union { |
| struct detailed_data_string str; |
| struct detailed_data_monitor_range range; |
| struct detailed_data_wpindex color; |
| struct std_timing timings[5]; |
| } data; |
| } __attribute__((packed)); |
| #define EDID_DETAIL_STD_MODES 0xfa |
| #define EDID_DETAIL_MONITOR_CPDATA 0xfb |
| #define EDID_DETAIL_MONITOR_NAME 0xfc |
| #define EDID_DETAIL_MONITOR_RANGE 0xfd |
| #define EDID_DETAIL_MONITOR_STRING 0xfe |
| #define EDID_DETAIL_MONITOR_SERIAL 0xff |
| struct detailed_timing { |
| u16 pixel_clock; /* need to multiply by 10 KHz */ |
| union { |
| struct detailed_pixel_timing pixel_data; |
| struct detailed_non_pixel other_data; |
| } data; |
| } __attribute__((packed)); |
| #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0) |
| #define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1) |
| #define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2) |
| #define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3) |
| #define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4) |
| #define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5) |
| #define DRM_EDID_INPUT_DIGITAL (1 << 7) /* bits below must be zero if set */ |
| #define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0) |
| #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1) |
| #define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2) |
| #define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */ |
| #define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5) |
| #define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6) |
| #define DRM_EDID_FEATURE_PM_STANDBY (1 << 7) |
| struct edid { |
| u8 header[8]; |
| /* Vendor & product info */ |
| u8 mfg_id[2]; |
| u8 prod_code[2]; |
| u32 serial; /* FIXME: byte order */ |
| u8 mfg_week; |
| u8 mfg_year; |
| /* EDID version */ |
| u8 version; |
| u8 revision; |
| /* Display info: */ |
| u8 input; |
| u8 width_cm; |
| u8 height_cm; |
| u8 gamma; |
| u8 features; |
| /* Color characteristics */ |
| u8 red_green_lo; |
| u8 black_white_lo; |
| u8 red_x; |
| u8 red_y; |
| u8 green_x; |
| u8 green_y; |
| u8 blue_x; |
| u8 blue_y; |
| u8 white_x; |
| u8 white_y; |
| /* Est. timings and mfg rsvd timings*/ |
| struct est_timings established_timings; |
| /* Standard timings 1-8*/ |
| struct std_timing standard_timings[8]; |
| /* Detailing timings 1-4 */ |
| struct detailed_timing detailed_timings[4]; |
| /* Number of 128 byte ext. blocks */ |
| u8 extensions; |
| /* Checksum */ |
| u8 checksum; |
| } __attribute__((packed)); |
| #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) |
| #endif /* __DRM_EDID_H__ */ |
| /drivers/video/drm/include/drm_mm.h |
|---|
| 0,0 → 1,105 |
| /************************************************************************** |
| * |
| * Copyright 2006-2008 Tungsten Graphics, Inc., Cedar Park, TX. USA. |
| * All Rights Reserved. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the |
| * "Software"), to deal in the Software without restriction, including |
| * without limitation the rights to use, copy, modify, merge, publish, |
| * distribute, sub license, and/or sell copies of the Software, and to |
| * permit persons to whom the Software is furnished to do so, subject to |
| * the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the |
| * next paragraph) shall be included in all copies or substantial portions |
| * of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
| * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
| * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
| * USE OR OTHER DEALINGS IN THE SOFTWARE. |
| * |
| * |
| **************************************************************************/ |
| /* |
| * Authors: |
| * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> |
| */ |
| #ifndef _DRM_MM_H_ |
| #define _DRM_MM_H_ |
| /* |
| * Generic range manager structs |
| */ |
| #include <types.h> |
| #include <list.h> |
| #include <errno-base.h> |
| #define spin_lock_init(x) |
| #define spin_lock(x) |
| #define spin_unlock(x) |
| struct drm_mm_node { |
| struct list_head fl_entry; |
| struct list_head ml_entry; |
| int free; |
| unsigned long start; |
| unsigned long size; |
| struct drm_mm *mm; |
| void *private; |
| }; |
| struct drm_mm { |
| struct list_head fl_entry; |
| struct list_head ml_entry; |
| struct list_head unused_nodes; |
| int num_unused; |
| // spinlock_t unused_lock; |
| }; |
| /* |
| * Basic range manager support (drm_mm.c) |
| */ |
| extern struct drm_mm_node *drm_mm_get_block_generic(struct drm_mm_node *node, |
| unsigned long size, |
| unsigned alignment, |
| int atomic); |
| static inline struct drm_mm_node *drm_mm_get_block(struct drm_mm_node *parent, |
| unsigned long size, |
| unsigned alignment) |
| { |
| return drm_mm_get_block_generic(parent, size, alignment, 0); |
| } |
| static inline struct drm_mm_node *drm_mm_get_block_atomic(struct drm_mm_node *parent, |
| unsigned long size, |
| unsigned alignment) |
| { |
| return drm_mm_get_block_generic(parent, size, alignment, 1); |
| } |
| extern void drm_mm_put_block(struct drm_mm_node *cur); |
| extern struct drm_mm_node *drm_mm_search_free(const struct drm_mm *mm, |
| unsigned long size, |
| unsigned alignment, |
| int best_match); |
| extern int drm_mm_init(struct drm_mm *mm, unsigned long start, |
| unsigned long size); |
| extern void drm_mm_takedown(struct drm_mm *mm); |
| extern int drm_mm_clean(struct drm_mm *mm); |
| extern unsigned long drm_mm_tail_space(struct drm_mm *mm); |
| extern int drm_mm_remove_space_from_tail(struct drm_mm *mm, |
| unsigned long size); |
| extern int drm_mm_add_space_to_tail(struct drm_mm *mm, |
| unsigned long size, int atomic); |
| extern int drm_mm_pre_get(struct drm_mm *mm); |
| static inline struct drm_mm *drm_get_mm(struct drm_mm_node *block) |
| { |
| return block->mm; |
| } |
| #endif |