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Ignore whitespace Rev 1320 → Rev 1321

/drivers/video/drm/radeon/radeon.h
28,8 → 28,6
#ifndef __RADEON_H__
#define __RADEON_H__
 
//#include "radeon_object.h"
 
/* TODO: Here are things that needs to be done :
* - surface allocator & initializer : (bit like scratch reg) should
* initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
62,11 → 60,16
* are considered as fatal)
*/
 
#include <asm/atomic.h>
 
#include <types.h>
#include <linux/list.h>
#include <linux/kref.h>
 
#include <ttm/ttm_bo_api.h>
#include <ttm/ttm_bo_driver.h>
#include <ttm/ttm_placement.h>
#include <ttm/ttm_module.h>
 
#include <linux/list.h>
 
#include <pci.h>
 
93,7 → 96,9
extern int radeon_testing;
extern int radeon_connector_table;
extern int radeon_tv;
extern int radeon_new_pll;
 
 
typedef struct
{
int width;
100,7 → 105,7
int height;
int bpp;
int freq;
}mode_t;
}videomode_t;
 
static inline uint8_t __raw_readb(const volatile void __iomem *addr)
{
212,11 → 217,11
*/
struct radeon_fence_driver {
uint32_t scratch_reg;
// atomic_t seq;
atomic_t seq;
uint32_t last_seq;
unsigned long count_timeout;
// wait_queue_head_t queue;
// rwlock_t lock;
rwlock_t lock;
struct list_head created;
struct list_head emited;
struct list_head signaled;
224,7 → 229,7
 
struct radeon_fence {
struct radeon_device *rdev;
// struct kref kref;
struct kref kref;
struct list_head list;
/* protected by radeon_fence.lock */
uint32_t seq;
249,36 → 254,48
* Tiling registers
*/
struct radeon_surface_reg {
struct radeon_object *robj;
struct radeon_bo *bo;
};
 
#define RADEON_GEM_MAX_SURFACES 8
 
/*
* Radeon buffer.
* TTM.
*/
struct radeon_object;
struct radeon_mman {
struct ttm_bo_global_ref bo_global_ref;
struct ttm_global_reference mem_global_ref;
bool mem_global_referenced;
struct ttm_bo_device bdev;
};
 
struct radeon_object_list {
struct radeon_bo {
/* Protected by gem.mutex */
struct list_head list;
/* Protected by tbo.reserved */
u32 placements[3];
struct ttm_placement placement;
struct ttm_buffer_object tbo;
struct ttm_bo_kmap_obj kmap;
unsigned pin_count;
void *kptr;
u32 tiling_flags;
u32 pitch;
int surface_reg;
/* Constant after initialization */
struct radeon_device *rdev;
struct drm_gem_object *gobj;
};
 
struct radeon_bo_list {
struct list_head list;
struct radeon_object *robj;
struct radeon_bo *bo;
uint64_t gpu_offset;
unsigned rdomain;
unsigned wdomain;
uint32_t tiling_flags;
u32 tiling_flags;
};
 
int radeon_object_init(struct radeon_device *rdev);
void radeon_object_fini(struct radeon_device *rdev);
int radeon_object_create(struct radeon_device *rdev,
struct drm_gem_object *gobj,
unsigned long size,
bool kernel,
uint32_t domain,
bool interruptible,
struct radeon_object **robj_ptr);
 
 
/*
* GEM objects.
*/
291,7 → 308,6
int radeon_gem_object_create(struct radeon_device *rdev, int size,
int alignment, int initial_domain,
bool discardable, bool kernel,
bool interruptible,
struct drm_gem_object **obj);
int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
uint64_t *gpu_addr);
308,7 → 324,7
};
 
struct radeon_gart_table_vram {
struct radeon_object *robj;
struct radeon_bo *robj;
volatile uint32_t *ptr;
};
 
389,12 → 405,17
bool sw_int;
/* FIXME: use a define max crtc rather than hardcode it */
bool crtc_vblank_int[2];
/* FIXME: use defines for max hpd/dacs */
bool hpd[6];
spinlock_t sw_lock;
int sw_refcount;
};
 
int radeon_irq_kms_init(struct radeon_device *rdev);
void radeon_irq_kms_fini(struct radeon_device *rdev);
void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
 
 
/*
* CP & ring.
*/
413,7 → 434,7
*/
struct radeon_ib_pool {
// struct mutex mutex;
struct radeon_object *robj;
struct radeon_bo *robj;
struct list_head scheduled_ibs;
struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
bool ready;
421,7 → 442,7
};
 
struct radeon_cp {
struct radeon_object *ring_obj;
struct radeon_bo *ring_obj;
volatile uint32_t *ring;
unsigned rptr;
unsigned wptr;
436,8 → 457,25
bool ready;
};
 
/*
* R6xx+ IH ring
*/
struct r600_ih {
struct radeon_bo *ring_obj;
volatile uint32_t *ring;
unsigned rptr;
unsigned wptr;
unsigned wptr_old;
unsigned ring_size;
uint64_t gpu_addr;
uint32_t align_mask;
uint32_t ptr_mask;
spinlock_t lock;
bool enabled;
};
 
struct r600_blit {
struct radeon_object *shader_obj;
struct radeon_bo *shader_obj;
u64 shader_gpu_addr;
u32 vs_offset, ps_offset;
u32 state_offset;
467,8 → 505,8
*/
struct radeon_cs_reloc {
// struct drm_gem_object *gobj;
struct radeon_object *robj;
struct radeon_object_list lobj;
struct radeon_bo *robj;
// struct radeon_bo_list lobj;
uint32_t handle;
uint32_t flags;
};
556,6 → 594,7
* AGP
*/
int radeon_agp_init(struct radeon_device *rdev);
void radeon_agp_resume(struct radeon_device *rdev);
void radeon_agp_fini(struct radeon_device *rdev);
 
 
563,7 → 602,7
* Writeback
*/
struct radeon_wb {
struct radeon_object *wb_obj;
struct radeon_bo *wb_obj;
volatile uint32_t *wb;
uint64_t gpu_addr;
};
651,6 → 690,11
uint32_t offset, uint32_t obj_size);
int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
void (*bandwidth_update)(struct radeon_device *rdev);
void (*hdp_flush)(struct radeon_device *rdev);
void (*hpd_init)(struct radeon_device *rdev);
void (*hpd_fini)(struct radeon_device *rdev);
bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
};
 
/*
738,10 → 782,9
uint8_t *bios;
bool is_atom_bios;
uint16_t bios_header_start;
 
// struct radeon_object *stollen_vga_memory;
struct radeon_bo *stollen_vga_memory;
struct fb_info *fbdev_info;
struct radeon_object *fbdev_robj;
struct radeon_bo *fbdev_rbo;
struct radeon_framebuffer *fbdev_rfb;
/* Register mmio */
unsigned long rmmio_base;
759,7 → 802,7
struct radeon_gart gart;
struct radeon_mode_info mode_info;
struct radeon_scratch scratch;
// struct radeon_mman mman;
struct radeon_mman mman;
struct radeon_fence_driver fence_drv;
struct radeon_cp cp;
struct radeon_ib_pool ib_pool;
817,6 → 860,10
}
}
 
/*
* Cast helper
*/
#define to_radeon_fence(p) ((struct radeon_fence *)(p))
 
/*
* Registers read & write functions.
951,12 → 998,17
#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
#define radeon_hdp_flush(rdev) (rdev)->asic->hdp_flush((rdev))
#define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
 
/* Common functions */
extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
963,6 → 1015,7
extern int radeon_modeset_init(struct radeon_device *rdev);
extern void radeon_modeset_fini(struct radeon_device *rdev);
extern bool radeon_card_posted(struct radeon_device *rdev);
extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
extern int radeon_clocks_init(struct radeon_device *rdev);
extern void radeon_clocks_fini(struct radeon_device *rdev);
extern void radeon_scratch_init(struct radeon_device *rdev);
970,6 → 1023,7
extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
 
/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
struct r100_mc_save {
1007,7 → 1061,7
extern void r100_vga_render_disable(struct radeon_device *rdev);
extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
struct radeon_cs_packet *pkt,
struct radeon_object *robj);
struct radeon_bo *robj);
extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
struct radeon_cs_packet *pkt,
const unsigned *auth, unsigned n,
1015,6 → 1069,8
extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
struct radeon_cs_packet *pkt,
unsigned idx);
extern void r100_enable_bm(struct radeon_device *rdev);
extern void r100_set_common_regs(struct radeon_device *rdev);
 
/* rv200,rv250,rv280 */
extern void r200_set_safe_registers(struct radeon_device *rdev);
1090,11 → 1146,16
extern void r600_scratch_init(struct radeon_device *rdev);
extern int r600_blit_init(struct radeon_device *rdev);
extern void r600_blit_fini(struct radeon_device *rdev);
extern int r600_cp_init_microcode(struct radeon_device *rdev);
extern int r600_init_microcode(struct radeon_device *rdev);
extern int r600_gpu_reset(struct radeon_device *rdev);
/* r600 irq */
extern int r600_irq_init(struct radeon_device *rdev);
extern void r600_irq_fini(struct radeon_device *rdev);
extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
extern int r600_irq_set(struct radeon_device *rdev);
 
#include "radeon_object.h"
 
 
#define DRM_UDELAY(d) udelay(d)
 
resource_size_t