| 37,10 → 37,10 |
|---|
| #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE |
| |
| static char *voltage_names[] = { |
| "0.4V", "0.6V", "0.8V", "1.2V" |
| "0.4V", "0.6V", "0.8V", "1.2V" |
| }; |
| static char *pre_emph_names[] = { |
| "0dB", "3.5dB", "6dB", "9.5dB" |
| "0dB", "3.5dB", "6dB", "9.5dB" |
| }; |
| |
| /***** radeon AUX functions *****/ |
| 305,7 → 305,7 |
|---|
| /***** radeon specific DP functions *****/ |
| |
| int radeon_dp_get_dp_link_config(struct drm_connector *connector, |
| const u8 dpcd[DP_DPCD_SIZE], |
| const u8 dpcd[DP_DPCD_SIZE], |
| unsigned pix_clock, |
| unsigned *dp_lanes, unsigned *dp_rate) |
| { |
| 317,7 → 317,7 |
|---|
| |
| if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == |
| ENCODER_OBJECT_ID_NUTMEG) { |
| for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) { |
| for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) { |
| max_pix_clock = (lane_num * 270000 * 8) / bpp; |
| if (max_pix_clock >= pix_clock) { |
| *dp_lanes = lane_num; |
| 328,15 → 328,15 |
|---|
| } else { |
| for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) { |
| for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) { |
| max_pix_clock = (lane_num * link_rates[i] * 8) / bpp; |
| if (max_pix_clock >= pix_clock) { |
| *dp_lanes = lane_num; |
| *dp_rate = link_rates[i]; |
| return 0; |
| max_pix_clock = (lane_num * link_rates[i] * 8) / bpp; |
| if (max_pix_clock >= pix_clock) { |
| *dp_lanes = lane_num; |
| *dp_rate = link_rates[i]; |
| return 0; |
| } |
| } |
| } |
| } |
| } |
| } |
| } |
| |
| return -EINVAL; |
| } |