| 279,8 → 279,8 |
|---|
| DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n", |
| pipe_name(pipe)); |
| } |
| } |
| } |
| } |
| |
| /** |
| * ibx_display_interrupt_update - update SDEIMR |
| 1294,7 → 1294,7 |
|---|
| |
| if (pch_iir & SDE_ERROR_CPT) |
| cpt_serr_int_handler(dev); |
| } |
| } |
| |
| static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) |
| { |
| 1385,8 → 1385,8 |
|---|
| |
| /* clear PCH hotplug event before clear CPU irq */ |
| I915_WRITE(SDEIIR, pch_iir); |
| } |
| } |
| } |
| |
| static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
| { |
| 1427,7 → 1427,7 |
|---|
| if (err_int_reenable) |
| ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB); |
| spin_unlock(&dev_priv->irq_lock); |
| } |
| } |
| |
| gt_iir = I915_READ(GTIIR); |
| if (gt_iir) { |
| 1437,7 → 1437,7 |
|---|
| ilk_gt_irq_handler(dev, dev_priv, gt_iir); |
| I915_WRITE(GTIIR, gt_iir); |
| ret = IRQ_HANDLED; |
| } |
| } |
| |
| de_iir = I915_READ(DEIIR); |
| if (de_iir) { |
| 1456,7 → 1456,7 |
|---|
| I915_WRITE(GEN6_PMIIR, pm_iir); |
| ret = IRQ_HANDLED; |
| } |
| } |
| } |
| |
| if (err_int_reenable) { |
| spin_lock(&dev_priv->irq_lock); |
| 2122,8 → 2122,8 |
|---|
| I915_WRITE(GEN6_PMIMR, 0xffffffff); |
| I915_WRITE(GEN6_PMIER, 0x0); |
| POSTING_READ(GEN6_PMIER); |
| } |
| } |
| } |
| |
| /* drm_dma.h hooks |
| */ |