WebSVN – Kolibri OS – Path Comparison – / – /drivers/include/ Rev 1408 and /drivers/include/ Rev 1407

Regard whitespace Rev 1408 → Rev 1407

/drivers/include/drm/drmP.h
File deleted

/drivers/include/drm/drm.h
File deleted

/drivers/include/drm/drm_dp_helper.h
File deleted

/drivers/include/drm/drm_mode.h
File deleted

/drivers/include/drm/drm_edid.h
File deleted

/drivers/include/drm/drm_fb_helper.h
File deleted

/drivers/include/drm/radeon_drm.h
File deleted

/drivers/include/drm/drm_mm.h
File deleted

/drivers/include/drm/drm_hashtab.h
File deleted

/drivers/include/drm/drm_crtc_helper.h
File deleted

/drivers/include/drm/drm_pciids.h
File deleted

/drivers/include/drm/drm_crtc.h
File deleted

/drivers/include/drm/ttm/ttm_module.h
File deleted

/drivers/include/drm/ttm/ttm_memory.h
File deleted

/drivers/include/drm/ttm/ttm_placement.h
File deleted

/drivers/include/drm/ttm/ttm_bo_api.h
File deleted

/drivers/include/drm/ttm/ttm_bo_driver.h
File deleted

/drivers/include/errno-base.h
File deleted

/drivers/include/linux/bitops.h
File deleted

/drivers/include/linux/types.h
File deleted

/drivers/include/linux/i2c-id.h
File deleted

/drivers/include/linux/compiler.h
File deleted

/drivers/include/linux/spinlock_types_up.h
File deleted

/drivers/include/linux/list.h
File deleted

/drivers/include/linux/bitmap.h
File deleted

/drivers/include/linux/i2c.h
File deleted

/drivers/include/linux/idr.h
File deleted

/drivers/include/linux/lockdep.h
File deleted

/drivers/include/linux/module.h
File deleted

/drivers/include/linux/spinlock_up.h
File deleted

/drivers/include/linux/sched.h
File deleted

/drivers/include/linux/kref.h
File deleted

/drivers/include/linux/compiler-gcc4.h
File deleted

/drivers/include/linux/asm/string_32.h
File deleted

/drivers/include/linux/asm/atomic.h
File deleted

/drivers/include/linux/asm/alternative.h
File deleted

/drivers/include/linux/asm/atomic_32.h
File deleted

/drivers/include/linux/asm/asm.h
File deleted

/drivers/include/linux/asm/posix_types.h
File deleted

/drivers/include/linux/asm/bitsperlong.h
File deleted

/drivers/include/linux/asm/cmpxchg.h
File deleted

/drivers/include/linux/asm/posix_types_32.h
File deleted

/drivers/include/linux/asm/required-features.h
File deleted

/drivers/include/linux/asm/swab.h
File deleted

/drivers/include/linux/asm/cmpxchg_32.h
File deleted

/drivers/include/linux/asm/byteorder.h
File deleted

/drivers/include/linux/asm/bitops.h
File deleted

/drivers/include/linux/asm/cpufeature.h
File deleted

 /drivers/include/pci.h
 ,0 → 1,183
+#pragma pack(push, 1)
+typedef struct
+{
+     u16_t device;
+     u16_t ChipSet;
+}PciChipset_t;
+#pragma pack(pop)
+#define VENDOR_ATI                 0x1002
+#define PCI_CLASS_DISPLAY_VGA      0x0300
+/*
+ * Under PCI, each device has 256 bytes of configuration address space,
+ * of which the first 64 bytes are standardized as follows:
+ */
+#define PCI_VENDOR_ID                   0x000    /* 16 bits */
+#define PCI_DEVICE_ID                   0x002    /* 16 bits */
+#define PCI_COMMAND                     0x004    /* 16 bits */
+#define  PCI_COMMAND_IO                 0x001    /* Enable response in I/O space */
+#define  PCI_COMMAND_MEMORY             0x002    /* Enable response in Memory space */
+#define  PCI_COMMAND_MASTER             0x004    /* Enable bus mastering */
+#define  PCI_COMMAND_SPECIAL            0x008    /* Enable response to special cycles */
+#define  PCI_COMMAND_INVALIDATE         0x010    /* Use memory write and invalidate */
+#define  PCI_COMMAND_VGA_PALETTE        0x020    /* Enable palette snooping */
+#define  PCI_COMMAND_PARITY             0x040    /* Enable parity checking */
+#define  PCI_COMMAND_WAIT               0x080    /* Enable address/data stepping */
+#define  PCI_COMMAND_SERR               0x100    /* Enable SERR */
+#define  PCI_COMMAND_FAST_BACK          0x200    /* Enable back-to-back writes */
+#define  PCI_COMMAND_INTX_DISABLE       0x400    /* INTx Emulation Disable */
+#define PCI_STATUS                      0x006    /* 16 bits */
+#define  PCI_STATUS_CAP_LIST            0x010    /* Support Capability List */
+#define  PCI_STATUS_66MHZ               0x020    /* Support 66 Mhz PCI 2.1 bus */
+#define  PCI_STATUS_UDF                 0x040    /* Support User Definable Features [obsolete] */
+#define  PCI_STATUS_FAST_BACK           0x080    /* Accept fast-back to back */
+#define  PCI_STATUS_PARITY              0x100    /* Detected parity error */
+#define  PCI_STATUS_DEVSEL_MASK         0x600    /* DEVSEL timing */
+#define  PCI_STATUS_DEVSEL_FAST         0x000
+#define  PCI_STATUS_DEVSEL_MEDIUM       0x200
+#define  PCI_STATUS_DEVSEL_SLOW         0x400
+#define  PCI_STATUS_SIG_TARGET_ABORT    0x800    /* Set on target abort */
+#define  PCI_STATUS_REC_TARGET_ABORT    0x1000   /* Master ack of " */
+#define  PCI_STATUS_REC_MASTER_ABORT    0x2000   /* Set on master abort */
+#define  PCI_STATUS_SIG_SYSTEM_ERROR    0x4000   /* Set when we drive SERR */
+#define  PCI_STATUS_DETECTED_PARITY     0x8000   /* Set on parity error */
+#define PCI_CLASS_REVISION               0x08    /* High 24 bits are class, low 8 revision */
+#define PCI_REVISION_ID                  0x08    /* Revision ID */
+#define PCI_CLASS_PROG                   0x09    /* Reg. Level Programming Interface */
+#define PCI_CLASS_DEVICE                 0x0a    /* Device class */
+#define PCI_CACHE_LINE_SIZE              0x0c    /* 8 bits */
+#define PCI_LATENCY_TIMER                0x0d    /* 8 bits */
+#define PCI_HEADER_TYPE                  0x0e    /* 8 bits */
+#define  PCI_HEADER_TYPE_NORMAL             0
+#define  PCI_HEADER_TYPE_BRIDGE             1
+#define  PCI_HEADER_TYPE_CARDBUS            2
+#define PCI_BIST                         0x0f    /* 8 bits */
+#define  PCI_BIST_CODE_MASK              0x0f    /* Return result */
+#define  PCI_BIST_START                  0x40    /* 1 to start BIST, 2 secs or less */
+#define  PCI_BIST_CAPABLE                0x80    /* 1 if BIST capable */
+#define PCI_CAPABILITY_LIST              0x34    /* Offset of first capability list entry */
+#define PCI_CB_CAPABILITY_LIST           0x14
+/* Capability lists */
+#define PCI_CAP_LIST_ID                  0       /* Capability ID */
+#define  PCI_CAP_ID_PM                   0x01    /* Power Management */
+#define  PCI_CAP_ID_AGP                  0x02    /* Accelerated Graphics Port */
+#define  PCI_CAP_ID_VPD                  0x03    /* Vital Product Data */
+#define  PCI_CAP_ID_SLOTID               0x04    /* Slot Identification */
+#define  PCI_CAP_ID_MSI                  0x05    /* Message Signalled Interrupts */
+#define  PCI_CAP_ID_CHSWP                0x06    /* CompactPCI HotSwap */
+#define  PCI_CAP_ID_PCIX                 0x07    /* PCI-X */
+#define  PCI_CAP_ID_HT                   0x08    /* HyperTransport */
+#define  PCI_CAP_ID_VNDR                 0x09    /* Vendor specific capability */
+#define  PCI_CAP_ID_SHPC                 0x0C    /* PCI Standard Hot-Plug Controller */
+#define  PCI_CAP_ID_EXP                  0x10    /* PCI Express */
+#define  PCI_CAP_ID_MSIX                 0x11    /* MSI-X */
+#define PCI_CAP_LIST_NEXT                1       /* Next capability in the list */
+#define PCI_CAP_FLAGS                    2       /* Capability defined flags (16 bits) */
+#define PCI_CAP_SIZEOF                   4
+/* AGP registers */
+#define PCI_AGP_VERSION                     2   /* BCD version number */
+#define PCI_AGP_RFU                         3   /* Rest of capability flags */
+#define PCI_AGP_STATUS                      4   /* Status register */
+#define  PCI_AGP_STATUS_RQ_MASK        0xff000000  /* Maximum number of requests - 1 */
+#define  PCI_AGP_STATUS_SBA            0x0200   /* Sideband addressing supported */
+#define  PCI_AGP_STATUS_64BIT          0x0020   /* 64-bit addressing supported */
+#define  PCI_AGP_STATUS_FW             0x0010   /* FW transfers supported */
+#define  PCI_AGP_STATUS_RATE4          0x0004   /* 4x transfer rate supported */
+#define  PCI_AGP_STATUS_RATE2          0x0002   /* 2x transfer rate supported */
+#define  PCI_AGP_STATUS_RATE1          0x0001   /* 1x transfer rate supported */
+#define PCI_AGP_COMMAND                     8   /* Control register */
+#define  PCI_AGP_COMMAND_RQ_MASK    0xff000000  /* Master: Maximum number of requests */
+#define  PCI_AGP_COMMAND_SBA           0x0200   /* Sideband addressing enabled */
+#define  PCI_AGP_COMMAND_AGP           0x0100   /* Allow processing of AGP transactions */
+#define  PCI_AGP_COMMAND_64BIT         0x0020   /* Allow processing of 64-bit addresses */
+#define  PCI_AGP_COMMAND_FW            0x0010   /* Force FW transfers */
+#define  PCI_AGP_COMMAND_RATE4         0x0004   /* Use 4x rate */
+#define  PCI_AGP_COMMAND_RATE2         0x0002   /* Use 2x rate */
+#define  PCI_AGP_COMMAND_RATE1         0x0001   /* Use 1x rate */
+#define PCI_AGP_SIZEOF                     12
+#define PCI_MAP_REG_START                   0x10
+#define PCI_MAP_REG_END                     0x28
+#define PCI_MAP_ROM_REG                     0x30
+#define PCI_MAP_MEMORY                0x00000000
+#define PCI_MAP_IO                    0x00000001
+#define PCI_MAP_MEMORY_TYPE           0x00000007
+#define PCI_MAP_IO_TYPE               0x00000003
+#define PCI_MAP_MEMORY_TYPE_32BIT     0x00000000
+#define PCI_MAP_MEMORY_TYPE_32BIT_1M  0x00000002
+#define PCI_MAP_MEMORY_TYPE_64BIT     0x00000004
+#define PCI_MAP_MEMORY_TYPE_MASK      0x00000006
+#define PCI_MAP_MEMORY_CACHABLE       0x00000008
+#define PCI_MAP_MEMORY_ATTR_MASK      0x0000000e
+#define PCI_MAP_MEMORY_ADDRESS_MASK   0xfffffff0
+#define PCI_MAP_IO_ATTR_MASK          0x00000003
+#define PCI_MAP_IS_IO(b)  ((b) & PCI_MAP_IO)
+#define PCI_MAP_IS_MEM(b)       (!PCI_MAP_IS_IO(b))
+#define PCI_MAP_IS64BITMEM(b)   \
+        (((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT)
+#define PCIGETMEMORY(b)   ((b) & PCI_MAP_MEMORY_ADDRESS_MASK)
+#define PCIGETMEMORY64HIGH(b)   (*((CARD32*)&b + 1))
+#define PCIGETMEMORY64(b)       \
+        (PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32))
+#define PCI_MAP_IO_ADDRESS_MASK       0xfffffffc
+#define PCIGETIO(b)             ((b) & PCI_MAP_IO_ADDRESS_MASK)
+#define PCI_MAP_ROM_DECODE_ENABLE     0x00000001
+#define PCI_MAP_ROM_ADDRESS_MASK      0xfffff800
+#define PCIGETROM(b)            ((b) & PCI_MAP_ROM_ADDRESS_MASK)
+#ifndef PCI_DOM_MASK
+# define PCI_DOM_MASK 0x0ffu
+#endif
+#define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu)
+#define PCI_MAKE_TAG(b,d,f)  ((((b) & (PCI_DOMBUS_MASK)) << 16) | \
+                              (((d) & 0x00001fu) << 11) | \
+                              (((f) & 0x000007u) << 8))
+#define PCI_BUS_FROM_TAG(tag)  (((tag) >> 16) & (PCI_DOMBUS_MASK))
+#define PCI_DEV_FROM_TAG(tag)  (((tag) & 0x0000f800u) >> 11)
+#define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8)
+#define PCI_DFN_FROM_TAG(tag)  (((tag) & 0x0000ff00u) >> 8)
+#define PCI_CMD_STAT_REG        0x04
+typedef unsigned int PCITAG;
+extern inline PCITAG
+pciTag(int busnum, int devnum, int funcnum)
+{
+        return(PCI_MAKE_TAG(busnum,devnum,funcnum));
+}
+const PciChipset_t *PciDevMatch(u16_t dev,const PciChipset_t *list);
+u32_t pciGetBaseSize(int bus, int devfn, int index, Bool destructive, Bool *min);

 /drivers/include/syscall.h
 ,8 → 1,4
-#ifndef __SYSCALL_H__
-#define __SYSCALL_H__
 #define OS_BASE   0x80000000
 typedef struct
 ,7 → 17,7
 #define ERR_PARAM   -1
-u32_t drvEntry(int, char *)__asm__("_drvEntry");
+u32_t __stdcall drvEntry(int)__asm__("_drvEntry");
 ///////////////////////////////////////////////////////////////////////////////
 ,17 → 38,11
 #define PG_NOCACHE  0x018
 void*  STDCALL AllocKernelSpace(size_t size)__asm__("AllocKernelSpace");
-void   STDCALL FreeKernelSpace(void *mem)__asm__("FreeKernelSpace");
-addr_t STDCALL MapIoMem(addr_t base, size_t size, u32_t flags)__asm__("MapIoMem");
 void*  STDCALL KernelAlloc(size_t size)__asm__("KernelAlloc");
 void*  STDCALL KernelFree(void *mem)__asm__("KernelFree");
 void*  STDCALL UserAlloc(size_t size)__asm__("UserAlloc");
 int    STDCALL UserFree(void *mem)__asm__("UserFree");
-void*  STDCALL GetDisplay()__asm__("GetDisplay");
-addr_t STDCALL AllocPage()__asm__("AllocPage");
 addr_t STDCALL AllocPages(count_t count)__asm__("AllocPages");
 void* STDCALL CreateRingBuffer(size_t size, u32_t map)__asm__("CreateRingBuffer");
 ,6 → 52,11
 int   STDCALL AttachIntHandler(int irq, void *handler, u32_t access) __asm__("AttachIntHandler");
+//void *CreateObject(u32 pid, size_t size);
+//void *DestroyObject(void *obj);
+addr_t STDCALL MapIoMem(addr_t base, size_t size, u32_t flags)__asm__("MapIoMem");
 ///////////////////////////////////////////////////////////////////////////////
 void   STDCALL SetMouseData(int btn, int x, int y,
 ,7 → 98,7
 ///////////////////////////////////////////////////////////////////////////////
-static inline int GetScreenSize()
+extern inline int GetScreenSize()
 {
   int retval;
 ,7 → 108,7
   return retval;
 }
-static inline int GetScreenBpp()
+extern inline int GetScreenBpp()
 {
   int retval;
 ,7 → 118,7
   return retval;
 }
-static inline int GetScreenPitch()
+extern inline int GetScreenPitch()
 {
   int retval;
 ,7 → 128,7
   return retval;
 }
-static inline u32_t GetPgAddr(void *mem)
+extern inline u32_t GetPgAddr(void *mem)
 {
      u32_t retval;
 ,7 → 139,7
      return retval;
 };
-static inline void CommitPages(void *mem, u32_t page, u32_t size)
+extern inline void CommitPages(void *mem, u32_t page, u32_t size)
 {
      size = (size+4095) & ~4095;
      __asm__ __volatile__ (
 ,7 → 149,7
      __asm__ __volatile__ ("":::"eax","ebx","ecx");
 };
-static inline void UnmapPages(void *mem, size_t size)
+extern inline void UnmapPages(void *mem, size_t size)
 {
      size = (size+4095) & ~4095;
      __asm__ __volatile__ (
 ,11 → 159,11
      __asm__ __volatile__ ("":::"eax","ecx");
 };
-static inline void usleep(u32_t delay)
+extern inline void usleep(u32_t delay)
 {
      if( !delay )
         delay++;
-     delay*= 500;
+     delay*=1000;
      while(delay--)
         __asm__ __volatile__(
 ,36 → 172,8
         :::"eax","ebx","ecx","edx");
      };
-static inline void udelay(u32_t delay)
+extern inline u32_t __PciApi(int cmd)
 {
-    if(!delay) delay++;
-    delay*= 500;
-    while(delay--)
-    {
-        __asm__ __volatile__(
-        "xorl %%eax, %%eax \n\t"
-        "cpuid"
-        :::"eax","ebx","ecx","edx" );
-    }
-}
-static inline void mdelay(u32_t time)
-{
-    time /= 10;
-    if(!time) time = 1;
-     __asm__ __volatile__ (
-     "call *__imp__Delay"
-     ::"b" (time));
-     __asm__ __volatile__ (
-     "":::"ebx");
-};
-static inline u32_t __PciApi(int cmd)
-{
      u32_t retval;
      __asm__ __volatile__ (
 ,7 → 184,7
      return retval;
 };
-static inline void* __CreateObject(u32_t pid, size_t size)
+extern inline void* __CreateObject(u32_t pid, size_t size)
 {
      void *retval;
 ,15 → 196,13
      return retval;
 }
-static inline void __DestroyObject(void *obj)
+extern inline void *__DestroyObject(void *obj)
 {
      __asm__ __volatile__ (
-     "call *__imp__DestroyObject \n\t"
+     "call *__imp__DestroyObject"
      :
-     :"a" (obj));
-     __asm__ __volatile__ (
-     ""
-     :::"eax","ebx","ecx","edx","esi","edi","cc","memory");
+     :"a" (obj)
+     :"ebx","edx","esi","edi", "memory");
 }
 ,24 → 224,8
 };
 */
-static inline u32_t GetService(const char *name)
+extern inline u32_t safe_cli(void)
 {
-    u32_t handle;
-    __asm__ __volatile__
-    (
-     "pushl %%eax \n\t"
-     "call *__imp__GetService"
-     :"=eax" (handle)
-     :"a" (name)
-     :"ebx","ecx","edx","esi", "edi"
-  );
-  return handle;
-};
-static inline u32_t safe_cli(void)
-{
      u32_t ifl;
      __asm__ __volatile__ (
      "pushf\n\t"
 ,7 → 235,7
     return ifl;
 }
-static inline void safe_sti(u32_t ifl)
+extern inline void safe_sti(u32_t ifl)
 {
      __asm__ __volatile__ (
      "pushl %0\n\t"
 ,7 → 244,7
         );
 }
-static inline void __clear (void * dst, unsigned len)
+extern inline void __clear (void * dst, unsigned len)
 {
      u32_t tmp;
      __asm__ __volatile__ (
 ,25 → 256,25
      __asm__ __volatile__ ("":::"ecx","edi");
 };
-static inline void out8(const u16_t port, const u8_t val)
+extern inline void out8(const u16_t port, const u8_t val)
 {
     __asm__ __volatile__
     ("outb  %1, %0\n" : : "dN"(port), "a"(val));
 }
-static inline void out16(const u16_t port, const u16_t val)
+extern inline void out16(const u16_t port, const u16_t val)
 {
     __asm__ __volatile__
     ("outw  %1, %0\n" : : "dN"(port), "a"(val));
 }
-static inline void out32(const u16_t port, const u32_t val)
+extern inline void out32(const u16_t port, const u32_t val)
 {
     __asm__ __volatile__
     ("outl  %1, %0\n" : : "dN"(port), "a"(val));
 }
-static inline u8_t in8(const u16_t port)
+extern inline u8_t in8(const u16_t port)
 {
     u8_t tmp;
     __asm__ __volatile__
 ,7 → 282,7
     return tmp;
 };
-static inline u16_t in16(const u16_t port)
+extern inline u16_t in16(const u16_t port)
 {
     u16_t tmp;
     __asm__ __volatile__
 ,7 → 290,7
     return tmp;
 };
-static inline u32_t in32(const u16_t port)
+extern inline u32_t in32(const u16_t port)
 {
     u32_t tmp;
     __asm__ __volatile__
 ,7 → 298,7
     return tmp;
 };
-static inline void delay(int time)
+extern inline void delay(int time)
 {
      __asm__ __volatile__ (
      "call *__imp__Delay"
 ,49 → 308,9
 }
-static inline void change_task()
+extern inline void change_task()
 {
      __asm__ __volatile__ (
      "call *__imp__ChangeTask");
 }
-static inline sysSetScreen(int width, int height, int pitch)
-{
-    __asm__ __volatile__
-    (
-        "call *__imp__SetScreen"
-        :
-        :"a" (width-1),"d"(height-1), "c"(pitch)
-    );
-    __asm__ __volatile__
-    ("" :::"eax","ecx","edx");
-}
-int drm_order(unsigned long size);
-static inline void __iomem *ioremap(uint32_t offset, size_t size)
-{
-    return (void __iomem*) MapIoMem(offset, size, 3);
-}
-static inline void iounmap(void *addr)
-{
-    FreeKernelSpace(addr);
-}
-static inline void *
-pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
-                      addr_t *dma_handle)
-{
-    *dma_handle = AllocPages(size >> 12);
-    return (void*)MapIoMem(*dma_handle, size, PG_SW+PG_NOCACHE);
-}
-static inline void __SysMsgBoardStr(char *text)
-{
-    __asm__ __volatile__(
-    "call *__imp__SysMsgBoardStr"
-    ::"S" (text));
-};
-#endif

 /drivers/include/types.h
 ,0 → 1,24
+#define  NULL (void*)0
+typedef  unsigned char        u8_t;
+typedef  unsigned short int   u16_t;
+typedef  unsigned int         u32_t;
+typedef  unsigned long long   u64_t;
+typedef  signed char        i8_t;
+typedef  signed short int   i16_t;
+typedef  unsigned int         addr_t;
+typedef  unsigned int size_t;
+typedef  unsigned int count_t;
+typedef  unsigned int eflags_t;
+typedef  unsigned int Bool;
+#define  TRUE  (Bool)1
+#define  FALSE (Bool)0

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Regard whitespace Rev 1408 → Rev 1407