| 57,6 → 57,8 |
|---|
| and eax, not (1 shl 28) |
| invoke PciWrite32, [bus], [dev], 0xBC, eax |
| |
| DEBUGF 1,"1\n" |
| |
| ; Set ADC base address |
| mov ebx, [dev] |
| inc ebx |
| 66,11 → 68,15 |
|---|
| |
| invoke PciWrite32, [bus], ebx, 0xE0, 0x00500000 or ADC_ADDR |
| |
| DEBUGF 1,"2\n" |
| |
| ; set up ADC |
| mov dx, ADC_ADDR + 1 |
| xor al, al |
| out dx, al |
| |
| DEBUGF 1,"3\n" |
| |
| ; Empty FIFO |
| @@: |
| mov dx, ADC_ADDR + 2 ; Status register |
| 82,6 → 88,8 |
|---|
| jmp @r |
| @@: |
| |
| DEBUGF 1,"4\n" |
| |
| ; Enable GPIO0-9 |
| mov dx, GPIO_PORT_CONFIG_ADDR + 0 ; General-Purpose I/O Data & Direction Decode Enable |
| mov eax, 0x000001ff |
| 103,8 → 111,8 |
|---|
| dec ecx |
| jnz .gpio_init |
| |
| ; Set GPIO0 pin 0-7 as output |
| mov al, 0xff |
| ; Set GPIO0 pin 0 as output |
| mov al, 0x01 |
| mov dx, GPIO_DATA_ADDR + 0*4 + 2 |
| out dx, al |
| |
| 145,20 → 153,15 |
|---|
| xor eax, eax |
| ret |
| .no_gpiowrite: |
| cmp eax, 3 ; read single ADC channel |
| cmp eax, 3 ; read ADC channel 0 |
| jne .no_adcread |
| |
| mov ecx, [ebx + IOCTL.input] |
| cmp ecx, 8 |
| jae .fail |
| |
| mov dx, ADC_ADDR + 1 |
| mov al, 1 shl 3 ; Power down ADC |
| out dx, al |
| |
| mov dx, ADC_ADDR + 0 ; AUX channel select register |
| mov al, 1 |
| shl ax, cl |
| mov al, 1 shl 0 ; Enable AUX0 scan |
| out dx, al |
| |
| mov dx, ADC_ADDR + 1 |
| 172,7 → 175,8 |
|---|
| jz @r |
| |
| mov dx, ADC_ADDR + 4 |
| in ax, dx ; read the data from the FIFO and return to user call |
| in ax, dx ; read the data and return to user call |
| DEBUGF 1, "ADC read: 0x%x\n", eax:4 |
| ret |
| .no_adcread: |
| .fail: |