/drivers/video/drm/i915/sna/sna.h |
---|
File deleted |
/drivers/video/drm/i915/sna/kgem.h |
---|
File deleted |
/drivers/video/drm/i915/sna/sna_stream.c |
---|
File deleted |
/drivers/video/drm/i915/sna/gen6_render.c |
---|
File deleted |
/drivers/video/drm/i915/sna/compiler.h |
---|
File deleted |
/drivers/video/drm/i915/sna/sna.c |
---|
File deleted |
/drivers/video/drm/i915/sna/sna_reg.h |
---|
File deleted |
/drivers/video/drm/i915/sna/gen6_render.h |
---|
File deleted |
/drivers/video/drm/i915/sna/kgem.c |
---|
File deleted |
/drivers/video/drm/i915/sna/sna_render.h |
---|
File deleted |
/drivers/video/drm/i915/sna |
---|
Property changes: |
Deleted: bugtraq:number |
-true |
\ No newline at end of property |
/drivers/video/drm/i915/i915_trace.h |
---|
File deleted |
/drivers/video/drm/i915/render/exa_wm_src_affine.g6b |
---|
File deleted |
/drivers/video/drm/i915/render/exa_wm_src_projective.g6b |
---|
File deleted |
/drivers/video/drm/i915/render/exa_wm_src_sample_argb.g6b |
---|
File deleted |
/drivers/video/drm/i915/render/exa_wm_write.g6b |
---|
File deleted |
/drivers/video/drm/i915/render |
---|
Property changes: |
Deleted: bugtraq:number |
-true |
\ No newline at end of property |
/drivers/video/drm/i915/i915_irq.c |
---|
File deleted |
/drivers/video/drm/i915/bitmap.c |
---|
6,28 → 6,20 |
#include "intel_drv.h" |
#include "bitmap.h" |
#define DRIVER_CAPS_0 HW_BIT_BLIT | HW_TEX_BLIT; |
#define DRIVER_CAPS_1 0 |
extern struct drm_device *main_device; |
struct hman bm_man; |
void __attribute__((regparm(1))) destroy_bitmap(bitmap_t *bitmap) |
{ |
printf("destroy bitmap %d\n", bitmap->handle); |
free_handle(&bm_man, bitmap->handle); |
bitmap->handle = 0; |
bitmap->obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
bitmap->obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
mutex_lock(&main_device->struct_mutex); |
i915_gem_object_unpin(bitmap->obj); |
drm_gem_object_unreference(&bitmap->obj->base); |
mutex_unlock(&main_device->struct_mutex); |
__DestroyObject(bitmap); |
}; |
extern struct drm_device *main_device; |
struct hman bm_man; |
int init_bitmaps() |
{ |
int ret; |
132,12 → 124,10 |
{ |
*dst++ = (0xFFFFF000 & *src++) | 0x207 ; // map as shared page |
}; |
while(max_count--) |
*dst++ = 0; // cleanup unused space |
// while(max_count--) |
// *dst++ = 0; // cleanup unused space |
} |
obj->mapped = uaddr ; |
bitmap->handle = handle; |
bitmap->uaddr = uaddr; |
bitmap->pitch = pitch; |
231,83 → 221,3 |
}; |
void *drm_intel_bo_map(struct drm_i915_gem_object *obj, int write_enable) |
{ |
u8 *kaddr; |
kaddr = AllocKernelSpace(obj->base.size); |
if( kaddr != NULL) |
{ |
u32_t *src = (u32_t*)obj->pages; |
u32_t *dst = &((u32_t*)page_tabs)[(u32_t)kaddr >> 12]; |
u32 count = obj->base.size/4096; |
while(count--) |
{ |
*dst++ = (0xFFFFF000 & *src++) | 0x003 ; |
}; |
return kaddr; |
}; |
return NULL; |
} |
void destroy_gem_object(uint32_t handle) |
{ |
struct drm_i915_gem_object *obj = (void*)handle; |
drm_gem_object_unreference(&obj->base); |
}; |
void write_gem_object(uint32_t handle, u32 offset, u32 size, u8* src) |
{ |
struct drm_i915_gem_object *obj = (void*)handle; |
u8 *dst; |
int ret; |
ret = i915_gem_object_pin(obj, 4096, true); |
if (ret) |
return; |
dst = drm_intel_bo_map(obj, true); |
if( dst != NULL ) |
{ |
memmove(dst+offset, src, size); |
FreeKernelSpace(dst); |
}; |
}; |
u32 get_buffer_offset(uint32_t handle) |
{ |
struct drm_i915_gem_object *obj = (void*)handle; |
return obj->gtt_offset; |
}; |
int get_driver_caps(hwcaps_t *caps) |
{ |
int ret = 0; |
ENTER(); |
dbgprintf("caps ptr %x\n", caps); |
switch(caps->idx) |
{ |
case 0: |
caps->opt[0] = DRIVER_CAPS_0; |
caps->opt[1] = DRIVER_CAPS_1; |
break; |
case 1: |
caps->cap1.max_tex_width = 4096; |
caps->cap1.max_tex_height = 4096; |
break; |
default: |
ret = 1; |
}; |
caps->idx = 1; |
return ret; |
} |
/drivers/video/drm/i915/bitmap.h |
---|
66,25 → 66,6 |
u32 format; // reserved mbz |
}; |
typedef struct |
{ |
uint32_t idx; |
union |
{ |
uint32_t opt[2]; |
struct { |
uint32_t max_tex_width; |
uint32_t max_tex_height; |
}cap1; |
}; |
}hwcaps_t; |
#define HW_BIT_BLIT (1<<0) /* BGRX blitter */ |
#define HW_TEX_BLIT (1<<1) /* stretch blit */ |
#define HW_VID_BLIT (1<<2) /* planar and packed video */ |
/* 3 - 63 reserved */ |
int get_driver_caps(hwcaps_t *caps); |
int create_surface(struct io_call_10 *pbitmap); |
int init_bitmaps(); |
/drivers/video/drm/i915/i915_gem.c |
---|
29,7 → 29,7 |
#include "drm.h" |
#include "i915_drm.h" |
#include "i915_drv.h" |
#include "i915_trace.h" |
//#include "i915_trace.h" |
#include "intel_drv.h" |
//#include <linux/shmem_fs.h> |
#include <linux/slab.h> |
236,7 → 236,6 |
return 0; |
} |
#endif |
int |
i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
247,6 → 246,8 |
struct drm_i915_gem_object *obj; |
size_t pinned; |
if (!(dev->driver->driver_features & DRIVER_GEM)) |
return -ENODEV; |
pinned = 0; |
mutex_lock(&dev->struct_mutex); |
260,9 → 261,8 |
return 0; |
} |
#if 0 |
int i915_gem_create(struct drm_file *file, |
static int |
i915_gem_create(struct drm_file *file, |
struct drm_device *dev, |
uint64_t size, |
uint32_t *handle_p) |
290,7 → 290,6 |
/* drop reference from allocate - handle holds it now */ |
drm_gem_object_unreference(&obj->base); |
trace_i915_gem_object_create(obj); |
*handle_p = handle; |
return 0; |
746,6 → 745,8 |
static int |
i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
gfp_t gfpmask) |
793,6 → 794,8 |
int page_count = obj->base.size / PAGE_SIZE; |
int i; |
ENTER(); |
BUG_ON(obj->madv == __I915_MADV_PURGED); |
// if (obj->tiling_mode != I915_TILING_NONE) |
808,6 → 811,8 |
free(obj->pages); |
obj->pages = NULL; |
LEAVE(); |
} |
void |
989,13 → 994,9 |
old_read_domains = obj->base.read_domains; |
old_write_domain = obj->base.write_domain; |
obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; |
obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; |
trace_i915_gem_object_change_domain(obj, |
old_read_domains, |
old_write_domain); |
} |
/** |
1006,6 → 1007,7 |
{ |
int ret = 0; |
ENTER(); |
if (obj->gtt_space == NULL) |
return 0; |
1045,7 → 1047,6 |
if (ret == -ERESTARTSYS) |
return ret; |
trace_i915_gem_object_unbind(obj); |
i915_gem_gtt_unbind_object(obj); |
i915_gem_object_put_pages_gtt(obj); |
1062,6 → 1063,7 |
if (i915_gem_object_is_purgeable(obj)) |
i915_gem_object_truncate(obj); |
LEAVE(); |
return ret; |
} |
1075,7 → 1077,6 |
if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0) |
return 0; |
trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains); |
ret = ring->flush(ring, invalidate_domains, flush_domains); |
if (ret) |
1238,6 → 1239,9 |
/** |
* i915_gem_clear_fence_reg - clear out fence register info |
* @obj: object to clear |
1419,7 → 1423,6 |
obj->map_and_fenceable = mappable && fenceable; |
trace_i915_gem_object_bind(obj, map_and_fenceable); |
return 0; |
} |
1525,9 → 1528,6 |
old_write_domain = obj->base.write_domain; |
obj->base.write_domain = 0; |
trace_i915_gem_object_change_domain(obj, |
obj->base.read_domains, |
old_write_domain); |
} |
/** Flushes the CPU write domain for the object if it's dirty. */ |
1544,9 → 1544,6 |
old_write_domain = obj->base.write_domain; |
obj->base.write_domain = 0; |
trace_i915_gem_object_change_domain(obj, |
obj->base.read_domains, |
old_write_domain); |
} |
/** |
1594,10 → 1591,6 |
obj->dirty = 1; |
} |
trace_i915_gem_object_change_domain(obj, |
old_read_domains, |
old_write_domain); |
return 0; |
} |
1653,9 → 1646,6 |
obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
trace_i915_gem_object_change_domain(obj, |
old_read_domains, |
old_write_domain); |
} |
obj->cache_level = cache_level; |
1723,9 → 1713,6 |
BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
trace_i915_gem_object_change_domain(obj, |
old_read_domains, |
old_write_domain); |
return 0; |
} |
1803,9 → 1790,6 |
obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
} |
trace_i915_gem_object_change_domain(obj, |
old_read_domains, |
old_write_domain); |
return 0; |
} |
1949,6 → 1933,8 |
struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
size_t size) |
{ |
2014,6 → 2000,8 |
drm_i915_private_t *dev_priv = dev->dev_private; |
int ret; |
ENTER(); |
ret = i915_gem_object_unbind(obj); |
if (ret == -ERESTARTSYS) { |
list_move(&obj->mm_list, |
2021,7 → 2009,6 |
return; |
} |
trace_i915_gem_object_destroy(obj); |
// if (obj->base.map_list.map) |
// drm_gem_free_mmap_offset(&obj->base); |
2032,6 → 2019,7 |
kfree(obj->page_cpu_valid); |
kfree(obj->bit_17); |
kfree(obj); |
LEAVE(); |
} |
void i915_gem_free_object(struct drm_gem_object *gem_obj) |
2039,6 → 2027,7 |
struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
struct drm_device *dev = obj->base.dev; |
ENTER(); |
while (obj->pin_count > 0) |
i915_gem_object_unpin(obj); |
2046,6 → 2035,7 |
// i915_gem_detach_phys_object(dev, obj); |
i915_gem_free_object_tail(obj); |
LEAVE(); |
} |
2064,7 → 2054,7 |
{ |
drm_i915_private_t *dev_priv = dev->dev_private; |
int ret; |
ENTER(); |
ret = intel_init_render_ring_buffer(dev); |
if (ret) |
return ret; |
2082,7 → 2072,7 |
} |
dev_priv->next_seqno = 1; |
LEAVE(); |
return 0; |
cleanup_bsd_ring: |
/drivers/video/drm/i915/i915_gem_gtt.c |
---|
26,7 → 26,7 |
#include "drm.h" |
#include "i915_drm.h" |
#include "i915_drv.h" |
#include "i915_trace.h" |
//#include "i915_trace.h" |
#include "intel_drv.h" |
#define AGP_USER_TYPES (1 << 16) |
/drivers/video/drm/i915/intel_display.c |
---|
36,8 → 36,9 |
#include "intel_drv.h" |
#include "i915_drm.h" |
#include "i915_drv.h" |
#include "i915_trace.h" |
//#include "i915_trace.h" |
#include "drm_dp_helper.h" |
#include "drm_crtc_helper.h" |
phys_addr_t get_bus_addr(void); |
4509,6 → 4510,8 |
int fbc_wm, plane_wm, cursor_wm; |
unsigned int enabled; |
ENTER(); |
enabled = 0; |
if (g4x_compute_wm0(dev, 0, |
&sandybridge_display_wm_info, latency, |
4791,9 → 4794,10 |
static void intel_update_watermarks(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
ENTER(); |
if (dev_priv->display.update_wm) |
dev_priv->display.update_wm(dev); |
LEAVE(); |
} |
void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, |
/drivers/video/drm/i915/intel_ringbuffer.c |
---|
33,7 → 33,7 |
#include "drm.h" |
#include "i915_drv.h" |
#include "i915_drm.h" |
#include "i915_trace.h" |
//#include "i915_trace.h" |
#include "intel_drv.h" |
/* |
1139,6 → 1139,8 |
unsigned long end; |
u32 head; |
ENTER(); |
/* If the reported head position has wrapped or hasn't advanced, |
* fallback to the slow and accurate path. |
*/ |
1147,7 → 1149,10 |
ring->head = head; |
ring->space = ring_space(ring); |
if (ring->space >= n) |
{ |
LEAVE(); |
return 0; |
}; |
} |
1156,15 → 1161,20 |
ring->head = I915_READ_HEAD(ring); |
ring->space = ring_space(ring); |
if (ring->space >= n) { |
trace_i915_ring_wait_end(ring); |
// trace_i915_ring_wait_end(ring); |
LEAVE(); |
return 0; |
} |
msleep(1); |
if (atomic_read(&dev_priv->mm.wedged)) |
{ |
LEAVE(); |
return -EAGAIN; |
}; |
} while (!time_after(jiffies, end)); |
trace_i915_ring_wait_end(ring); |
LEAVE(); |
return -EBUSY; |
} |
/drivers/video/drm/i915/kms_display.c |
---|
17,9 → 17,7 |
#include "bitmap.h" |
extern struct drm_device *main_device; |
typedef struct |
{ |
kobj_t header; |
69,9 → 67,6 |
u32_t cmd_buffer; |
u32_t cmd_offset; |
void init_render(); |
int sna_init(); |
int init_cursor(cursor_t *cursor); |
static cursor_t* __stdcall select_cursor_kms(cursor_t *cursor); |
static void __stdcall move_cursor_kms(cursor_t *cursor, int x, int y); |
215,8 → 210,6 |
}; |
#endif |
main_device = dev; |
int err; |
err = init_bitmaps(); |
225,8 → 218,6 |
printf("Initialize bitmap manager\n"); |
}; |
sna_init(); |
LEAVE(); |
return 0; |
586,6 → 577,7 |
return old; |
}; |
extern struct drm_device *main_device; |
#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) |
756,7 → 748,6 |
#else |
u8* src_offset; |
u8* dst_offset; |
u32 ifl; |
src_offset = (u8*)(src_y*bitmap->pitch + src_x*4); |
src_offset += (u32)bitmap->uaddr; |
766,7 → 757,6 |
u32_t tmp_h = height; |
ifl = safe_cli(); |
while( tmp_h--) |
{ |
u32_t tmp_w = width; |
784,7 → 774,6 |
tmp_dst++; |
}; |
}; |
safe_sti(ifl); |
} |
#endif |
821,12 → 810,14 |
i915_gem_object_set_to_gtt_domain(bitmap->obj, false); |
if (HAS_BLT(main_device)) |
{ |
int ret; |
ring = &dev_priv->ring[BCS]; |
else |
ring = &dev_priv->ring[RCS]; |
ring = &dev_priv->ring[BCS]; |
ring->dispatch_execbuffer(ring, cmd_offset, n*4); |
int ret; |
ret = intel_ring_begin(ring, 4); |
if (ret) |
return ret; |
836,179 → 827,8 |
intel_ring_emit(ring, 0); |
intel_ring_emit(ring, MI_NOOP); |
intel_ring_advance(ring); |
} |
else |
{ |
ring = &dev_priv->ring[RCS]; |
ring->dispatch_execbuffer(ring, cmd_offset, n*4); |
ring->flush(ring, 0, I915_GEM_DOMAIN_RENDER); |
}; |
bitmap->obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
bitmap->obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
return 0; |
fail: |
return -1; |
}; |
/* For display hotplug interrupt */ |
static void |
ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
{ |
if ((dev_priv->irq_mask & mask) != 0) { |
dev_priv->irq_mask &= ~mask; |
I915_WRITE(DEIMR, dev_priv->irq_mask); |
POSTING_READ(DEIMR); |
} |
} |
static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
{ |
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
unsigned long irqflags; |
// if (!i915_pipe_enabled(dev, pipe)) |
// return -EINVAL; |
spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
ironlake_enable_display_irq(dev_priv, (pipe == 0) ? |
DE_PIPEA_VBLANK : DE_PIPEB_VBLANK); |
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
return 0; |
} |
static int i915_interrupt_info(struct drm_device *dev) |
{ |
drm_i915_private_t *dev_priv = dev->dev_private; |
int ret, i, pipe; |
if (!HAS_PCH_SPLIT(dev)) { |
dbgprintf("Interrupt enable: %08x\n", |
I915_READ(IER)); |
dbgprintf("Interrupt identity: %08x\n", |
I915_READ(IIR)); |
dbgprintf("Interrupt mask: %08x\n", |
I915_READ(IMR)); |
for_each_pipe(pipe) |
dbgprintf("Pipe %c stat: %08x\n", |
pipe_name(pipe), |
I915_READ(PIPESTAT(pipe))); |
} else { |
dbgprintf("North Display Interrupt enable: %08x\n", |
I915_READ(DEIER)); |
dbgprintf("North Display Interrupt identity: %08x\n", |
I915_READ(DEIIR)); |
dbgprintf("North Display Interrupt mask: %08x\n", |
I915_READ(DEIMR)); |
dbgprintf("South Display Interrupt enable: %08x\n", |
I915_READ(SDEIER)); |
dbgprintf("South Display Interrupt identity: %08x\n", |
I915_READ(SDEIIR)); |
dbgprintf("South Display Interrupt mask: %08x\n", |
I915_READ(SDEIMR)); |
dbgprintf("Graphics Interrupt enable: %08x\n", |
I915_READ(GTIER)); |
dbgprintf("Graphics Interrupt identity: %08x\n", |
I915_READ(GTIIR)); |
dbgprintf("Graphics Interrupt mask: %08x\n", |
I915_READ(GTIMR)); |
} |
dbgprintf("Interrupts received: %d\n", |
atomic_read(&dev_priv->irq_received)); |
for (i = 0; i < I915_NUM_RINGS; i++) { |
if (IS_GEN6(dev) || IS_GEN7(dev)) { |
printf("Graphics Interrupt mask (%s): %08x\n", |
dev_priv->ring[i].name, |
I915_READ_IMR(&dev_priv->ring[i])); |
} |
// i915_ring_seqno_info(m, &dev_priv->ring[i]); |
} |
return 0; |
} |
void execute_buffer (struct drm_i915_gem_object *buffer, uint32_t offset, |
int size) |
{ |
struct intel_ring_buffer *ring; |
drm_i915_private_t *dev_priv = main_device->dev_private; |
u32 invalidate; |
u32 seqno = 2; |
offset += buffer->gtt_offset; |
// dbgprintf("execute %x size %d\n", offset, size); |
// asm volatile( |
// "mfence \n" |
// "wbinvd \n" |
// "mfence \n" |
// :::"memory"); |
ring = &dev_priv->ring[RCS]; |
ring->dispatch_execbuffer(ring, offset, size); |
invalidate = I915_GEM_DOMAIN_COMMAND; |
if (INTEL_INFO(main_device)->gen >= 4) |
invalidate |= I915_GEM_DOMAIN_SAMPLER; |
if (ring->flush(ring, invalidate, 0)) |
i915_gem_next_request_seqno(ring); |
ring->irq_get(ring); |
ring->add_request(ring, &seqno); |
// i915_interrupt_info(main_device); |
// ironlake_enable_vblank(main_device, 0); |
}; |
int blit_textured(u32 hbitmap, int dst_x, int dst_y, |
int src_x, int src_y, u32 w, u32 h) |
{ |
drm_i915_private_t *dev_priv = main_device->dev_private; |
bitmap_t *src_bitmap, *dst_bitmap; |
bitmap_t screen; |
rect_t winrc; |
// dbgprintf(" handle: %d dx %d dy %d sx %d sy %d w %d h %d\n", |
// hbitmap, dst_x, dst_y, src_x, src_y, w, h); |
if(unlikely(hbitmap==0)) |
return -1; |
src_bitmap = (bitmap_t*)hman_get_data(&bm_man, hbitmap); |
// dbgprintf("bitmap %x\n", src_bitmap); |
if(unlikely(src_bitmap==NULL)) |
return -1; |
GetWindowRect(&winrc); |
screen.pitch = os_display->pitch; |
screen.gaddr = 0; |
screen.width = os_display->width; |
screen.height = os_display->height; |
screen.obj = (void*)-1; |
dst_bitmap = &screen; |
dst_x+= winrc.left; |
dst_y+= winrc.top; |
i915_gem_object_set_to_gtt_domain(src_bitmap->obj, false); |
sna_blit_copy(dst_bitmap, dst_x, dst_y, w, h, src_bitmap, src_x, src_y); |
src_bitmap->obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
src_bitmap->obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
}; |
/drivers/video/drm/i915/main.c |
---|
20,12 → 20,10 |
int _stdcall display_handler(ioctl_t *io); |
int init_agp(void); |
int blit_video(u32 hbitmap, int dst_x, int dst_y, |
int src_x, int src_y, u32 w, u32 h); |
int create_video(int width, int height, u32_t *outp); |
int video_blit(uint64_t src_offset, int x, int y, |
int w, int h, int pitch); |
int blit_textured(u32 hbitmap, int dst_x, int dst_y, |
int src_x, int src_y, u32 w, u32 h); |
static char log[256]; |
int x86_clflush_size; |
49,8 → 47,7 |
if(!dbg_open(log)) |
{ |
// strcpy(log, "/RD/1/DRIVERS/i915.log"); |
strcpy(log, "/HD1/2/i915.log"); |
strcpy(log, "/RD/1/DRIVERS/i915.log"); |
if(!dbg_open(log)) |
{ |
60,9 → 57,6 |
} |
dbgprintf("i915 blitter preview\n cmdline: %s\n", cmdline); |
cpu_detect(); |
dbgprintf("\ncache line size %d\n", x86_clflush_size); |
enum_pci_devices(); |
err = i915_init(); |
85,13 → 79,12 |
#define COMPATIBLE_API 0x0100 /* 1.00 */ |
#define API_VERSION (COMPATIBLE_API << 16) | CURRENT_API |
#define DISPLAY_VERSION API_VERSION |
#define DISPLAY_VERSION CURRENT_API |
#define SRV_GETVERSION 0 |
#define SRV_ENUM_MODES 1 |
#define SRV_SET_MODE 2 |
#define SRV_GET_CAPS 3 |
#define SRV_CREATE_SURFACE 10 |
139,10 → 132,6 |
retval = set_user_mode((videomode_t*)inp); |
break; |
case SRV_GET_CAPS: |
retval = get_driver_caps((hwcaps_t*)inp); |
break; |
case SRV_CREATE_SURFACE: |
// check_input(8); |
retval = create_surface((struct io_call_10*)inp); |
150,10 → 139,7 |
case SRV_BLIT_VIDEO: |
// blit_video( inp[0], inp[1], inp[2], |
// inp[3], inp[4], inp[5], inp[6]); |
blit_textured( inp[0], inp[1], inp[2], |
blit_video( inp[0], inp[1], inp[2], |
inp[3], inp[4], inp[5], inp[6]); |
retval = 0; |
225,22 → 211,19 |
}; |
}; |
static inline void __cpuid(unsigned int *eax, unsigned int *ebx, |
unsigned int *ecx, unsigned int *edx) |
{ |
/* ecx is often an input as well as an output. */ |
asm volatile("cpuid" |
asm volatile( |
"cpuid" |
: "=a" (*eax), |
"=b" (*ebx), |
"=c" (*ecx), |
"=d" (*edx) |
: "0" (*eax), "2" (*ecx) |
: "memory"); |
: "" (*eax), "2" (*ecx)); |
} |
static inline void cpuid(unsigned int op, |
unsigned int *eax, unsigned int *ebx, |
unsigned int *ecx, unsigned int *edx) |
/drivers/video/drm/i915/i915_dma.c |
---|
34,7 → 34,7 |
#include "i915_drm.h" |
#include "i915_drv.h" |
#include <drm/intel-gtt.h> |
#include "i915_trace.h" |
//#include "i915_trace.h" |
//#include "../../../platform/x86/intel_ips.h" |
#include <linux/pci.h> |
//#include <linux/vgaarb.h> |
241,9 → 241,9 |
intel_modeset_gem_init(dev); |
ret = drm_irq_install(dev); |
if (ret) |
goto cleanup_gem; |
// ret = drm_irq_install(dev); |
// if (ret) |
// goto cleanup_gem; |
/* Always safe in the mode setting case. */ |
/* FIXME: do pre/post-mode set stuff in core KMS code */ |
521,8 → 521,9 |
/* enable GEM by default */ |
dev_priv->has_gem = 1; |
intel_irq_init(dev); |
// intel_irq_init(dev); |
/* Try to make sure MCHBAR is enabled before poking at it */ |
intel_setup_mchbar(dev); |
intel_setup_gmbus(dev); |
/drivers/video/drm/i915/i915_drm.h |
---|
491,7 → 491,7 |
__u32 delta; |
/** Offset in the buffer the relocation entry will be written into */ |
__u32 offset; |
__u64 offset; |
/** |
* Offset value of the target buffer that the relocation entry was last |
501,7 → 501,7 |
* and writing the relocation. This value is written back out by |
* the execbuffer ioctl when the relocation is written. |
*/ |
__u32 presumed_offset; |
__u64 presumed_offset; |
/** |
* Target memory domains read by this operation. |
/drivers/video/drm/i915/i915_drv.c |
---|
444,6 → 444,8 |
if (ret) |
goto err_g4; |
main_device = dev; |
LEAVE(); |
return 0; |
/drivers/video/drm/i915/intel_dp.c |
---|
206,8 → 206,17 |
*/ |
static int |
intel_dp_link_required(int pixel_clock, int bpp) |
intel_dp_link_required(struct intel_dp *intel_dp, int pixel_clock, int check_bpp) |
{ |
struct drm_crtc *crtc = intel_dp->base.base.crtc; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
int bpp = 24; |
if (check_bpp) |
bpp = check_bpp; |
else if (intel_crtc) |
bpp = intel_crtc->bpp; |
return (pixel_clock * bpp + 9) / 10; |
} |
234,11 → 243,12 |
return MODE_PANEL; |
} |
mode_rate = intel_dp_link_required(mode->clock, 24); |
mode_rate = intel_dp_link_required(intel_dp, mode->clock, 0); |
max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); |
if (mode_rate > max_rate) { |
mode_rate = intel_dp_link_required(mode->clock, 18); |
mode_rate = intel_dp_link_required(intel_dp, |
mode->clock, 18); |
if (mode_rate > max_rate) |
return MODE_CLOCK_HIGH; |
else |
671,7 → 681,7 |
int lane_count, clock; |
int max_lane_count = intel_dp_max_lane_count(intel_dp); |
int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; |
int bpp = mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24; |
int bpp = mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 0; |
static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) { |
689,7 → 699,7 |
for (clock = 0; clock <= max_clock; clock++) { |
int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); |
if (intel_dp_link_required(mode->clock, bpp) |
if (intel_dp_link_required(intel_dp, mode->clock, bpp) |
<= link_avail) { |
intel_dp->link_bw = bws[clock]; |
intel_dp->lane_count = lane_count; |
/drivers/video/drm/i915/intel_lvds.c |
---|
622,7 → 622,7 |
.destroy = intel_encoder_destroy, |
}; |
static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
{ |
DRM_DEBUG_KMS("Skipping LVDS initialization for %s\n", id->ident); |
return 1; |
696,14 → 696,6 |
}, |
{ |
.callback = intel_no_lvds_dmi_callback, |
.ident = "AOpen i45GMx-I", |
.matches = { |
DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), |
DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), |
}, |
}, |
{ |
.callback = intel_no_lvds_dmi_callback, |
.ident = "Aopen i945GTt-VFA", |
.matches = { |
DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), |
/drivers/video/drm/i915/pci.c |
---|
350,11 → 350,11 |
hdr = PciRead8(busnr, devfn, PCI_HEADER_TYPE); |
dev = (pci_dev_t*)kzalloc(sizeof(pci_dev_t), 0); |
if(unlikely(dev == NULL)) |
return NULL; |
INIT_LIST_HEAD(&dev->link); |
if(unlikely(dev == NULL)) |
return NULL; |
dev->pci_dev.busnr = busnr; |
dev->pci_dev.devfn = devfn; |