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Regard whitespace Rev 2340 → Rev 2339

/drivers/video/drm/i915/bitmap.c
File deleted
/drivers/video/drm/i915/bitmap.h
File deleted
/drivers/video/drm/i915/Gtt/intel-agp.c
19,10 → 19,6
 
#define __devinit
#define PCI_VENDOR_ID_INTEL 0x8086
#define PCI_DEVICE_ID_INTEL_82915G_HB 0x2580
#define PCI_DEVICE_ID_INTEL_82915GM_HB 0x2590
#define PCI_DEVICE_ID_INTEL_82945G_HB 0x2770
#define PCI_DEVICE_ID_INTEL_82945GM_HB 0x27A0
 
 
int intel_gmch_probe(struct pci_dev *pdev,
84,40 → 80,9
.subvendor = PCI_ANY_ID, \
.subdevice = PCI_ANY_ID, \
}
ID(PCI_DEVICE_ID_INTEL_E7221_HB),
ID(PCI_DEVICE_ID_INTEL_82915G_HB),
ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
ID(PCI_DEVICE_ID_INTEL_82945G_HB),
ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
ID(PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB),
ID(PCI_DEVICE_ID_INTEL_PINEVIEW_HB),
ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
ID(PCI_DEVICE_ID_INTEL_82G35_HB),
ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
ID(PCI_DEVICE_ID_INTEL_82965G_HB),
ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
ID(PCI_DEVICE_ID_INTEL_G33_HB),
ID(PCI_DEVICE_ID_INTEL_Q35_HB),
ID(PCI_DEVICE_ID_INTEL_Q33_HB),
ID(PCI_DEVICE_ID_INTEL_GM45_HB),
ID(PCI_DEVICE_ID_INTEL_EAGLELAKE_HB),
ID(PCI_DEVICE_ID_INTEL_Q45_HB),
ID(PCI_DEVICE_ID_INTEL_G45_HB),
ID(PCI_DEVICE_ID_INTEL_G41_HB),
ID(PCI_DEVICE_ID_INTEL_B43_HB),
ID(PCI_DEVICE_ID_INTEL_B43_1_HB),
ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB),
ID(PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB),
ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB),
ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB),
ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB),
ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB),
ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB),
ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_HB),
ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB),
ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB),
{ }
};
 
/drivers/video/drm/i915/i915_drv.c
47,7 → 47,6
 
int init_display_kms(struct drm_device *dev);
 
struct drm_device *main_device;
 
int i915_panel_ignore_lid __read_mostly = 0;
 
376,7 → 375,7
 
int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
{
struct drm_device *dev;
static struct drm_device *dev;
int ret;
 
ENTER();
419,8 → 418,12
if (ret)
goto err_g4;
 
main_device = dev;
 
// if( radeon_modeset )
// init_display_kms(dev->dev_private, &usermode);
// else
// init_display(dev->dev_private, &usermode);
 
LEAVE();
 
return 0;
/drivers/video/drm/i915/intel_display.c
2196,6 → 2196,7
return 0;
 
#if 0
 
if (!dev->primary->master)
{
LEAVE();
3202,7 → 3203,6
 
dev_priv->display.dpms(crtc, mode);
 
#if 0
if (!dev->primary->master)
return;
 
3225,8 → 3225,6
DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
break;
}
#endif
 
}
 
static void intel_crtc_disable(struct drm_crtc *crtc)
6367,6 → 6365,8
struct intel_crtc *intel_crtc;
int i;
 
ENTER();
 
intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
if (intel_crtc == NULL)
return;
6409,6 → 6409,8
 
intel_crtc->busy = false;
 
LEAVE();
 
// setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
// (unsigned long)intel_crtc);
}
6734,6 → 6736,9
 
 
 
 
 
 
static unsigned long intel_pxfreq(u32 vidfreq)
{
unsigned long freq;
/drivers/video/drm/i915/intel_ringbuffer.c
147,6 → 147,8
struct drm_i915_gem_object *obj = ring->obj;
u32 head;
 
ENTER();
 
/* Stop the ring if it's running. */
I915_WRITE_CTL(ring, 0);
I915_WRITE_HEAD(ring, 0);
201,6 → 203,7
ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
ring->space = ring_space(ring);
 
LEAVE();
 
return 0;
}
282,6 → 285,9
{
struct drm_device *dev = ring->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
 
ENTER();
 
int ret = init_ring_common(ring);
 
if (INTEL_INFO(dev)->gen > 3) {
302,6 → 308,8
return ret;
}
 
LEAVE();
 
return ret;
}
 
553,7 → 561,6
}
spin_unlock(&ring->irq_lock);
}
#endif
 
void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
{
585,6 → 592,7
I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
POSTING_READ(mmio);
}
#endif
 
static int
bsd_ring_flush(struct intel_ring_buffer *ring,
698,7 → 706,6
}
spin_unlock(&ring->irq_lock);
}
#endif
 
static int
ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
794,7 → 801,7
}
 
ring->status_page.gfx_addr = obj->gtt_offset;
ring->status_page.page_addr = MapIoMem(obj->pages[0], 4096, PG_SW);
ring->status_page.page_addr = kmap(obj->pages[0]);
if (ring->status_page.page_addr == NULL) {
memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
goto err_unpin;
809,19 → 816,20
return 0;
 
err_unpin:
// i915_gem_object_unpin(obj);
i915_gem_object_unpin(obj);
err_unref:
// drm_gem_object_unreference(&obj->base);
drm_gem_object_unreference(&obj->base);
err:
return ret;
}
#endif
 
int intel_init_ring_buffer(struct drm_device *dev,
struct intel_ring_buffer *ring)
{
struct drm_i915_gem_object *obj;
struct drm_i915_gem_object *obj=NULL;
int ret;
 
ENTER();
ring->dev = dev;
INIT_LIST_HEAD(&ring->active_list);
INIT_LIST_HEAD(&ring->request_list);
832,9 → 840,9
ring->irq_mask = ~0;
 
if (I915_NEED_GFX_HWS(dev)) {
ret = init_status_page(ring);
if (ret)
return ret;
// ret = init_status_page(ring);
// if (ret)
// return ret;
}
 
obj = i915_gem_alloc_object(dev, ring->size);
878,7 → 886,7
ring->effective_size = ring->size;
if (IS_I830(ring->dev))
ring->effective_size -= 128;
 
LEAVE();
return 0;
 
err_unmap:
928,8 → 936,6
unsigned int *virt;
int rem = ring->size - ring->tail;
 
ENTER();
 
if (ring->space < rem) {
int ret = intel_wait_ring_buffer(ring, rem);
if (ret)
946,7 → 952,6
ring->tail = 0;
ring->space = ring_space(ring);
 
LEAVE();
return 0;
}
 
957,8 → 962,6
unsigned long end;
u32 head;
 
ENTER();
 
/* If the reported head position has wrapped or hasn't advanced,
* fallback to the slow and accurate path.
*/
967,10 → 970,7
ring->head = head;
ring->space = ring_space(ring);
if (ring->space >= n)
{
LEAVE();
return 0;
};
}
 
// trace_i915_ring_wait_begin(ring);
980,20 → 980,20
ring->space = ring_space(ring);
if (ring->space >= n) {
// trace_i915_ring_wait_end(ring);
LEAVE();
return 0;
}
 
if (dev->primary->master) {
struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
if (master_priv->sarea_priv)
master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
}
 
msleep(1);
if (atomic_read(&dev_priv->mm.wedged))
{
LEAVE();
return -EAGAIN;
};
} while (!time_after(jiffies, end));
// trace_i915_ring_wait_end(ring);
LEAVE();
 
return -EBUSY;
}
 
1004,8 → 1004,8
int n = 4*num_dwords;
int ret;
 
// if (unlikely(atomic_read(&dev_priv->mm.wedged)))
// return -EIO;
if (unlikely(atomic_read(&dev_priv->mm.wedged)))
return -EIO;
 
if (unlikely(ring->tail + n > ring->effective_size)) {
ret = intel_wrap_ring_buffer(ring);
1041,7 → 1041,7
// .get_seqno = ring_get_seqno,
// .irq_get = render_ring_get_irq,
// .irq_put = render_ring_put_irq,
.dispatch_execbuffer = render_ring_dispatch_execbuffer,
// .dispatch_execbuffer = render_ring_dispatch_execbuffer,
// .cleanup = render_ring_cleanup,
};
 
1059,7 → 1059,7
// .get_seqno = ring_get_seqno,
// .irq_get = bsd_ring_get_irq,
// .irq_put = bsd_ring_put_irq,
.dispatch_execbuffer = ring_dispatch_execbuffer,
// .dispatch_execbuffer = ring_dispatch_execbuffer,
};
 
 
1106,6 → 1106,7
return 0;
}
 
#if 0
static int
gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
u32 offset, u32 len)
1124,8 → 1125,6
return 0;
}
 
#if 0
 
static bool
gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
{
1173,7 → 1172,7
// .get_seqno = ring_get_seqno,
// .irq_get = gen6_bsd_ring_get_irq,
// .irq_put = gen6_bsd_ring_put_irq,
.dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
// .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
};
 
#if 0
1305,7 → 1304,7
// .get_seqno = ring_get_seqno,
// .irq_get = blt_ring_get_irq,
// .irq_put = blt_ring_put_irq,
.dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
// .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
// .cleanup = blt_ring_cleanup,
};
 
1313,7 → 1312,7
{
drm_i915_private_t *dev_priv = dev->dev_private;
struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
 
ENTER();
*ring = render_ring;
if (INTEL_INFO(dev)->gen >= 6) {
ring->add_request = gen6_add_request;
1328,7 → 1327,7
ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
memset(ring->status_page.page_addr, 0, PAGE_SIZE);
}
 
LEAVE();
return intel_init_ring_buffer(dev, ring);
}
 
/drivers/video/drm/i915/i915_drv.h
290,8 → 290,8
uint32_t next_seqno;
 
drm_dma_handle_t *status_page_dmah;
uint32_t counter;
drm_local_map_t hws_map;
// uint32_t counter;
// drm_local_map_t hws_map;
struct drm_i915_gem_object *pwrctx;
struct drm_i915_gem_object *renderctx;
 
883,6 → 883,7
atomic_t pending_flip;
};
 
 
#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
 
/**
1146,11 → 1147,11
/**
* Returns true if seq1 is later than seq2.
*/
static inline bool
i915_seqno_passed(uint32_t seq1, uint32_t seq2)
{
return (int32_t)(seq1 - seq2) >= 0;
}
//static inline bool
//i915_seqno_passed(uint32_t seq1, uint32_t seq2)
//{
// return (int32_t)(seq1 - seq2) >= 0;
//}
 
static inline u32
i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
1205,6 → 1206,7
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
enum i915_cache_level cache_level);
 
 
/* i915_gem_gtt.c */
void i915_gem_restore_gtt_mappings(struct drm_device *dev);
int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
/drivers/video/drm/i915/kms_display.c
1,6 → 1,3
 
#define iowrite32(v, addr) writel((v), (addr))
 
#include "drmP.h"
#include "drm.h"
#include "i915_drm.h"
7,6 → 4,7
#include "i915_drv.h"
#include "intel_drv.h"
 
 
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
15,8 → 13,17
 
#include <syscall.h>
 
#include "bitmap.h"
typedef struct tag_object kobj_t;
typedef struct tag_display display_t;
 
struct tag_object
{
uint32_t magic;
void *destroy;
kobj_t *fd;
kobj_t *bk;
uint32_t pid;
};
 
typedef struct
{
64,9 → 71,6
 
static display_t *os_display;
 
u32_t cmd_buffer;
u32_t cmd_offset;
 
int init_cursor(cursor_t *cursor);
static cursor_t* __stdcall select_cursor_kms(cursor_t *cursor);
static void __stdcall move_cursor_kms(cursor_t *cursor, int x, int y);
191,50 → 195,7
};
safe_sti(ifl);
 
{
#define XY_COLOR_BLT ((2<<29)|(0x50<<22)|(0x4))
#define BLT_WRITE_ALPHA (1<<21)
#define BLT_WRITE_RGB (1<<20)
 
drm_i915_private_t *dev_priv = dev->dev_private;
struct drm_i915_gem_object *obj;
struct intel_ring_buffer *ring;
 
u32_t br13, cmd, *b;
 
int n=0;
 
cmd = XY_COLOR_BLT | BLT_WRITE_ALPHA | BLT_WRITE_RGB;
br13 = os_display->pitch;
br13 |= 0xF0 << 16;
br13 |= 3 << 24;
 
obj = i915_gem_alloc_object(dev, 4096);
i915_gem_object_pin(obj, 4096, true);
 
cmd_buffer = MapIoMem(obj->pages[0], 4096, PG_SW|PG_NOCACHE);
cmd_offset = obj->gtt_offset;
 
b = (u32_t*)cmd_buffer;
b[n++] = cmd;
b[n++] = br13;
b[n++] = 0; // top, left
b[n++] = (128 << 16) | 128; // bottom, right
b[n++] = 0; // dst
b[n++] = 0x0000FF00;
b[n++] = MI_BATCH_BUFFER_END;
if( n & 1)
b[n++] = MI_NOOP;
 
// cmd_buffer = (u32_t)&b[n];
// i915_gem_object_set_to_gtt_domain(obj, false);
 
 
ring = &dev_priv->ring[BCS];
ring->dispatch_execbuffer(ring,cmd_offset, n*4);
 
};
 
LEAVE();
 
return 0;
472,7 → 433,7
 
// release old cursor
 
KernelFree(cursor->data);
// KernelFree(cursor->data);
 
cursor->data = bits;
 
588,138 → 549,62
return old;
};
 
extern struct drm_device *main_device;
 
#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
 
int video_blit(uint64_t src_offset, int x, int y,
int w, int h, int pitch)
#if 0
static void intel_crtc_update_cursor(struct drm_crtc *crtc,
bool on)
{
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int pipe = intel_crtc->pipe;
int x = intel_crtc->cursor_x;
int y = intel_crtc->cursor_y;
u32 base, pos;
bool visible;
 
drm_i915_private_t *dev_priv = main_device->dev_private;
struct intel_ring_buffer *ring;
pos = 0;
 
u32_t br13, cmd, *b;
u32_t offset;
if (on && crtc->enabled && crtc->fb) {
base = intel_crtc->cursor_addr;
if (x > (int) crtc->fb->width)
base = 0;
 
int n=0;
if (y > (int) crtc->fb->height)
base = 0;
} else
base = 0;
 
// if( cmd_buffer & 0xF80 )
// cmd_buffer&= 0xFFFFF000;
if (x < 0) {
if (x + intel_crtc->cursor_width < 0)
base = 0;
 
// b = (u32_t*)ALIGN(cmd_buffer,16);
pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
x = -x;
}
pos |= x << CURSOR_X_SHIFT;
 
// offset = cmd_offset + ((u32_t)b & 0xFFF);
if (y < 0) {
if (y + intel_crtc->cursor_height < 0)
base = 0;
 
b = cmd_buffer;
pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
y = -y;
}
pos |= y << CURSOR_Y_SHIFT;
 
cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGB;
br13 = os_display->pitch;
br13 |= 0xCC << 16;
br13 |= 3 << 24;
visible = base != 0;
if (!visible && !intel_crtc->cursor_visible)
return;
 
b[n++] = cmd;
b[n++] = br13;
b[n++] = (y << 16) | x;
b[n++] = ( (y+h) << 16) | (x+w); // bottom, right
b[n++] = 0; // dst_offset
b[n++] = 0; //src_top|src_left
I915_WRITE(CURPOS(pipe), pos);
if (IS_845G(dev) || IS_I865G(dev))
i845_update_cursor(crtc, base);
else
i9xx_update_cursor(crtc, base);
 
b[n++] = pitch;
b[n++] = (u32_t)src_offset;
if (visible)
intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
}
 
b[n++] = MI_BATCH_BUFFER_END;
if( n & 1)
b[n++] = MI_NOOP;
#endif
 
// i915_gem_object_set_to_gtt_domain(obj, false);
 
ring = &dev_priv->ring[BCS];
ring->dispatch_execbuffer(ring, cmd_offset, n*4);
 
intel_ring_begin(ring, 4);
// if (ret)
// return ret;
 
// cmd = MI_FLUSH_DW;
// if (invalidate & I915_GEM_GPU_DOMAINS)
// cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
intel_ring_emit(ring, MI_FLUSH_DW);
intel_ring_emit(ring, 0);
intel_ring_emit(ring, 0);
intel_ring_emit(ring, MI_NOOP);
intel_ring_advance(ring);
 
 
fail:
return -1;
};
 
 
int blit_video(u32 hbitmap, int dst_x, int dst_y,
int src_x, int src_y, u32 w, u32 h)
{
drm_i915_private_t *dev_priv = main_device->dev_private;
struct intel_ring_buffer *ring;
 
bitmap_t *bitmap;
u32_t br13, cmd, *b;
u32_t offset;
 
int n=0;
 
if(unlikely(hbitmap==0))
return -1;
 
bitmap = hman_get_data(&bm_man, hbitmap);
 
if(unlikely(bitmap==NULL))
return -1;
 
// if( cmd_buffer & 0xF80 )
// cmd_buffer&= 0xFFFFF000;
 
// b = (u32_t*)ALIGN(cmd_buffer,16);
 
// offset = cmd_offset + ((u32_t)b & 0xFFF);
 
b = cmd_buffer;
 
cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGB;
br13 = os_display->pitch;
br13 |= 0xCC << 16;
br13 |= 3 << 24;
 
b[n++] = cmd;
b[n++] = br13;
b[n++] = (dst_y << 16) | dst_x;
b[n++] = ( (dst_y+h) << 16) | (dst_x+w); // bottom, right
b[n++] = 0; // dst_offset
b[n++] = (src_y << 16) | src_x;
 
b[n++] = bitmap->pitch;
b[n++] = bitmap->gaddr;
 
b[n++] = MI_BATCH_BUFFER_END;
if( n & 1)
b[n++] = MI_NOOP;
 
// i915_gem_object_set_to_gtt_domain(obj, false);
 
ring = &dev_priv->ring[BCS];
ring->dispatch_execbuffer(ring, cmd_offset, n*4);
 
intel_ring_begin(ring, 4);
// if (ret)
// return ret;
 
intel_ring_emit(ring, MI_FLUSH_DW);
intel_ring_emit(ring, 0);
intel_ring_emit(ring, 0);
intel_ring_emit(ring, MI_NOOP);
intel_ring_advance(ring);
 
return 0;
fail:
return -1;
};
/drivers/video/drm/i915/main.c
12,17 → 12,9
#include <linux/pci.h>
#include <syscall.h>
 
typedef struct bitmap bitmap_t;
 
void parse_cmdline(char *cmdline, char *log);
int _stdcall display_handler(ioctl_t *io);
int init_agp(void);
 
int create_video(int width, int height, u32_t *outp);
int create_bitmap(bitmap_t **pbitmap, int width, int height);
int video_blit(uint64_t src_offset, int x, int y,
int w, int h, int pitch);
 
static char log[256];
 
int i915_modeset = 1;
39,12 → 31,12
if( GetService("DISPLAY") != 0 )
return 0;
 
if( cmdline && *cmdline )
parse_cmdline(cmdline, log);
// if( cmdline && *cmdline )
// parse_cmdline(cmdline, &usermode, log, &radeon_modeset);
 
if(!dbg_open(log))
{
strcpy(log, "/RD/1/DRIVERS/i915.log");
strcpy(log, "/HD1/2/i915.log");
 
if(!dbg_open(log))
{
52,7 → 44,7
return 0;
};
}
dbgprintf("i915_early_preview second edition\n cmdline: %s\n", cmdline);
dbgprintf("i915 RC01 cmdline %s\n", cmdline);
 
enum_pci_devices();
 
110,7 → 102,7
case SRV_ENUM_MODES:
dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n",
inp, io->inp_size, io->out_size );
check_output(4);
// check_output(4);
// check_input(*outp * sizeof(videomode_t));
if( i915_modeset)
retval = get_videomodes((videomode_t*)inp, outp);
124,14 → 116,13
retval = set_user_mode((videomode_t*)inp);
break;
 
/*
case SRV_CREATE_VIDEO:
check_input(2);
check_output(4);
retval = create_video(inp[0], inp[1], outp);
retval = r600_create_video(inp[0], inp[1], outp);
break;
 
case SRV_BLIT_VIDEO:
video_blit( ((uint64_t*)inp)[0], inp[2], inp[3],
r600_video_blit( ((uint64_t*)inp)[0], inp[2], inp[3],
inp[4], inp[5], inp[6]);
 
retval = 0;
140,9 → 131,9
case SRV_CREATE_BITMAP:
check_input(8);
check_output(4);
retval = create_bitmap((bitmap_t**)outp, inp[0], inp[1]);
retval = create_bitmap(outp, inp[0], inp[1]);
break;
 
*/
};
 
return retval;
175,38 → 166,3
}
return ret;
};
 
 
static char* parse_path(char *p, char *log)
{
char c;
 
while( (c = *p++) == ' ');
p--;
while( (c = *log++ = *p++) && (c != ' '));
*log = 0;
 
return p;
};
 
void parse_cmdline(char *cmdline, char *log)
{
char *p = cmdline;
 
char c = *p++;
 
while( c )
{
if( c == '-')
{
switch(*p++)
{
case 'l':
p = parse_path(p, log);
break;
};
};
c = *p++;
};
};
 
/drivers/video/drm/i915/i915_gem.c
727,6 → 727,8
int page_count, i;
struct page *page;
 
ENTER();
 
/* Get the list of pages out of our struct file. They'll be pinned
* at this point until we release them.
*/
748,8 → 750,8
// if (obj->tiling_mode != I915_TILING_NONE)
// i915_gem_object_do_bit_17_swizzle(obj);
 
LEAVE();
 
 
return 0;
 
err_pages:
1067,6 → 1069,8
bool mappable, fenceable;
int ret;
 
ENTER();
 
if (obj->madv != I915_MADV_WILLNEED) {
DRM_ERROR("Attempting to bind a purgeable object\n");
return -EINVAL;
1193,6 → 1197,7
 
obj->map_and_fenceable = mappable && fenceable;
 
LEAVE();
// trace_i915_gem_object_bind(obj, map_and_fenceable);
return 0;
}
1492,6 → 1497,8
struct drm_i915_private *dev_priv = dev->dev_private;
int ret;
 
ENTER();
 
BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
// WARN_ON(i915_verify_lists(dev));
 
1527,6 → 1534,8
}
obj->pin_mappable |= map_and_fenceable;
 
LEAVE();
 
// WARN_ON(i915_verify_lists(dev));
return 0;
}
1577,7 → 1586,7
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_i915_gem_object *obj;
 
ENTER();
obj = kzalloc(sizeof(*obj), GFP_KERNEL);
if (obj == NULL)
return NULL;
1620,7 → 1629,7
obj->madv = I915_MADV_WILLNEED;
/* Avoid an unnecessary call to unbind on the first bind. */
obj->map_and_fenceable = true;
 
LEAVE();
return obj;
}
 
/drivers/video/drm/i915/i915_gem_gtt.c
80,6 → 80,7
unsigned int agp_type = cache_level_to_agp_type(dev, obj->cache_level);
int ret;
 
ENTER();
// if (dev_priv->mm.gtt->needs_dmar) {
// ret = intel_gtt_map_memory(obj->pages,
// obj->base.size >> PAGE_SHIFT,
97,7 → 98,7
obj->base.size >> PAGE_SHIFT,
obj->pages,
agp_type);
 
LEAVE();
return 0;
}
 
/drivers/video/drm/i915/intel_sdvo.c
616,29 → 616,8
&outputs, sizeof(outputs));
}
 
static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
int mode)
{
u8 state = SDVO_ENCODER_STATE_ON;
 
switch (mode) {
case DRM_MODE_DPMS_ON:
state = SDVO_ENCODER_STATE_ON;
break;
case DRM_MODE_DPMS_STANDBY:
state = SDVO_ENCODER_STATE_STANDBY;
break;
case DRM_MODE_DPMS_SUSPEND:
state = SDVO_ENCODER_STATE_SUSPEND;
break;
case DRM_MODE_DPMS_OFF:
state = SDVO_ENCODER_STATE_OFF;
break;
}
 
return intel_sdvo_set_value(intel_sdvo,
SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
}
 
static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
int *clock_min,