/drivers/video/drm/radeon/ni.c |
---|
File deleted |
/drivers/video/drm/radeon/nid.h |
---|
File deleted |
/drivers/video/drm/radeon/fwblob.asm |
---|
110,15 → 110,7 |
dd PALMME_START |
dd (PALMME_END - PALMME_START) |
dd FIRMWARE_SUMO_ME |
dd SUMOME_START |
dd (SUMOME_END - SUMOME_START) |
dd FIRMWARE_SUMO2_ME |
dd SUMO2ME_START |
dd (SUMO2ME_END - SUMO2ME_START) |
dd FIRMWARE_RV610_PFP |
dd RV610PFP_START |
dd (RV610PFP_END - RV610PFP_START) |
172,16 → 164,8 |
dd PALMPFP_START |
dd (PALMPFP_END - PALMPFP_START) |
dd FIRMWARE_SUMO_PFP |
dd SUMOPFP_START |
dd (SUMOPFP_END - SUMOPFP_START) |
dd FIRMWARE_SUMO2_PFP |
dd SUMO2PFP_START |
dd (SUMO2PFP_END - SUMO2PFP_START) |
dd FIRMWARE_R600_RLC |
dd R600RLC_START |
dd (R600RLC_END - R600RLC_START) |
206,9 → 190,6 |
dd JUNIPERRLC_START |
dd (JUNIPERRLC_END - JUNIPERRLC_START) |
dd FIRMWARE_SUMO_RLC |
dd SUMORLC_START |
dd (SUMORLC_END - SUMORLC_START) |
___end_builtin_fw: |
239,8 → 220,6 |
FIRMWARE_CEDAR_ME db 'radeon/CEDAR_me.bin',0 |
FIRMWARE_JUNIPER_ME db 'radeon/JUNIPER_me.bin',0 |
FIRMWARE_PALM_ME db 'radeon/PALM_me.bin',0 |
FIRMWARE_SUMO_ME db 'radeon/SUMO_me.bin',0 |
FIRMWARE_SUMO2_ME db 'radeon/SUMO2_me.bin',0 |
FIRMWARE_R600_PFP db 'radeon/R600_pfp.bin',0 |
257,8 → 236,6 |
FIRMWARE_CEDAR_PFP db 'radeon/CEDAR_pfp.bin',0 |
FIRMWARE_JUNIPER_PFP db 'radeon/JUNIPER_pfp.bin',0 |
FIRMWARE_PALM_PFP db 'radeon/PALM_pfp.bin',0 |
FIRMWARE_SUMO_PFP db 'radeon/SUMO_pfp.bin',0 |
FIRMWARE_SUMO2_PFP db 'radeon/SUMO2_pfp.bin',0 |
FIRMWARE_R600_RLC db 'radeon/R600_rlc.bin',0 |
267,7 → 244,6 |
FIRMWARE_REDWOOD_RLC db 'radeon/REDWOOD_rlc.bin',0 |
FIRMWARE_CEDAR_RLC db 'radeon/CEDAR_rlc.bin',0 |
FIRMWARE_JUNIPER_RLC db 'radeon/JUNIPER_rlc.bin',0 |
FIRMWARE_SUMO_RLC db 'radeon/SUMO_rlc.bin',0 |
align 16 |
386,18 → 362,8 |
file 'firmware/PALM_me.bin' |
PALMME_END: |
align 16 |
SUMOME_START: |
file 'firmware/SUMO_me.bin' |
SUMOME_END: |
align 16 |
SUMO2ME_START: |
file 'firmware/SUMO2_me.bin' |
SUMO2ME_END: |
align 16 |
RV610PFP_START: |
file 'firmware/RV610_pfp.bin' |
RV610PFP_END: |
466,19 → 432,8 |
file 'firmware/PALM_pfp.bin' |
PALMPFP_END: |
align 16 |
SUMOPFP_START: |
file 'firmware/SUMO_pfp.bin' |
SUMOPFP_END: |
align 16 |
SUMO2PFP_START: |
file 'firmware/SUMO2_pfp.bin' |
SUMO2PFP_END: |
align 16 |
R600RLC_START: |
file 'firmware/R600_rlc.bin' |
R600RLC_END: |
508,7 → 463,3 |
file 'firmware/JUNIPER_rlc.bin' |
JUNIPERRLC_END: |
align 16 |
SUMORLC_START: |
file 'firmware/SUMO_rlc.bin' |
SUMORLC_END: |
/drivers/video/drm/radeon/Makefile |
---|
58,7 → 58,6 |
radeon_clocks.c \ |
radeon_i2c.c \ |
atom.c \ |
ni.c \ |
radeon_gem.c \ |
radeon_atombios.c \ |
radeon_agp.c \ |
/drivers/video/drm/radeon/evergreen.c |
---|
41,150 → 41,6 |
void evergreen_fini(struct radeon_device *rdev); |
static void evergreen_pcie_gen2_enable(struct radeon_device *rdev); |
u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) |
{ |
struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; |
u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset); |
/* Lock the graphics update lock */ |
tmp |= EVERGREEN_GRPH_UPDATE_LOCK; |
WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); |
/* update the scanout addresses */ |
WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, |
upper_32_bits(crtc_base)); |
WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
(u32)crtc_base); |
WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, |
upper_32_bits(crtc_base)); |
WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
(u32)crtc_base); |
/* Wait for update_pending to go high. */ |
while (!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)); |
DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); |
/* Unlock the lock, so double-buffering can take place inside vblank */ |
tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK; |
WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); |
/* Return current update_pending status: */ |
return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING; |
} |
/* get temperature in millidegrees */ |
int evergreen_get_temp(struct radeon_device *rdev) |
{ |
u32 temp, toffset; |
int actual_temp = 0; |
if (rdev->family == CHIP_JUNIPER) { |
toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >> |
TOFFSET_SHIFT; |
temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >> |
TS0_ADC_DOUT_SHIFT; |
if (toffset & 0x100) |
actual_temp = temp / 2 - (0x200 - toffset); |
else |
actual_temp = temp / 2 + toffset; |
actual_temp = actual_temp * 1000; |
} else { |
temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >> |
ASIC_T_SHIFT; |
if (temp & 0x400) |
actual_temp = -256; |
else if (temp & 0x200) |
actual_temp = 255; |
else if (temp & 0x100) { |
actual_temp = temp & 0x1ff; |
actual_temp |= ~0x1ff; |
} else |
actual_temp = temp & 0xff; |
actual_temp = (actual_temp * 1000) / 2; |
} |
return actual_temp; |
} |
int sumo_get_temp(struct radeon_device *rdev) |
{ |
u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff; |
int actual_temp = temp - 49; |
return actual_temp * 1000; |
} |
void evergreen_pm_misc(struct radeon_device *rdev) |
{ |
int req_ps_idx = rdev->pm.requested_power_state_index; |
int req_cm_idx = rdev->pm.requested_clock_mode_index; |
struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; |
struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; |
if (voltage->type == VOLTAGE_SW) { |
/* 0xff01 is a flag rather then an actual voltage */ |
if (voltage->voltage == 0xff01) |
return; |
if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) { |
radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); |
rdev->pm.current_vddc = voltage->voltage; |
DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage); |
} |
/* 0xff01 is a flag rather then an actual voltage */ |
if (voltage->vddci == 0xff01) |
return; |
if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) { |
radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI); |
rdev->pm.current_vddci = voltage->vddci; |
DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci); |
} |
} |
} |
void evergreen_pm_prepare(struct radeon_device *rdev) |
{ |
struct drm_device *ddev = rdev->ddev; |
struct drm_crtc *crtc; |
struct radeon_crtc *radeon_crtc; |
u32 tmp; |
/* disable any active CRTCs */ |
list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { |
radeon_crtc = to_radeon_crtc(crtc); |
if (radeon_crtc->enabled) { |
tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); |
tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; |
WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); |
} |
} |
} |
void evergreen_pm_finish(struct radeon_device *rdev) |
{ |
struct drm_device *ddev = rdev->ddev; |
struct drm_crtc *crtc; |
struct radeon_crtc *radeon_crtc; |
u32 tmp; |
/* enable any active CRTCs */ |
list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { |
radeon_crtc = to_radeon_crtc(crtc); |
if (radeon_crtc->enabled) { |
tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); |
tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; |
WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); |
} |
} |
} |
bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
{ |
bool connected = false; |
2443,24 → 2299,6 |
{ |
int r; |
/* enable pcie gen2 link */ |
if (!ASIC_IS_DCE5(rdev)) |
evergreen_pcie_gen2_enable(rdev); |
if (ASIC_IS_DCE5(rdev)) { |
if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { |
r = ni_init_microcode(rdev); |
if (r) { |
DRM_ERROR("Failed to load firmware!\n"); |
return r; |
} |
} |
r = ni_mc_load_microcode(rdev); |
if (r) { |
DRM_ERROR("Failed to load MC firmware!\n"); |
return r; |
} |
} else { |
if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { |
r = r600_init_microcode(rdev); |
if (r) { |
2468,7 → 2306,6 |
return r; |
} |
} |
} |
evergreen_mc_program(rdev); |
if (rdev->flags & RADEON_IS_AGP) { |
/drivers/video/drm/radeon/firmware/SUMO_me.bin |
---|
Cannot display: file marked as a binary type. |
svn:mime-type = application/octet-stream |
Property changes: |
Deleted: svn:mime-type |
-application/octet-stream |
\ No newline at end of property |
/drivers/video/drm/radeon/firmware/SUMO2_me.bin |
---|
Cannot display: file marked as a binary type. |
svn:mime-type = application/octet-stream |
Property changes: |
Deleted: svn:mime-type |
-application/octet-stream |
\ No newline at end of property |
/drivers/video/drm/radeon/firmware/SUMO_pfp.bin |
---|
Cannot display: file marked as a binary type. |
svn:mime-type = application/octet-stream |
Property changes: |
Deleted: svn:mime-type |
-application/octet-stream |
\ No newline at end of property |
/drivers/video/drm/radeon/firmware/SUMO2_pfp.bin |
---|
Cannot display: file marked as a binary type. |
svn:mime-type = application/octet-stream |
Property changes: |
Deleted: svn:mime-type |
-application/octet-stream |
\ No newline at end of property |
/drivers/video/drm/radeon/radeon_asic.c |
---|
644,26 → 644,28 |
.bandwidth_update = &evergreen_bandwidth_update, |
}; |
#if 0 |
static struct radeon_asic sumo_asic = { |
.init = &evergreen_init, |
// .fini = &evergreen_fini, |
// .suspend = &evergreen_suspend, |
// .resume = &evergreen_resume, |
.fini = &evergreen_fini, |
.suspend = &evergreen_suspend, |
.resume = &evergreen_resume, |
.cp_commit = &r600_cp_commit, |
.gpu_is_lockup = &evergreen_gpu_is_lockup, |
.asic_reset = &evergreen_asic_reset, |
.vga_set_state = &r600_vga_set_state, |
.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
.gart_set_page = &rs600_gart_set_page, |
.ring_test = &r600_ring_test, |
// .ring_ib_execute = &r600_ring_ib_execute, |
// .irq_set = &r600_irq_set, |
// .irq_process = &r600_irq_process, |
.ring_ib_execute = &evergreen_ring_ib_execute, |
.irq_set = &evergreen_irq_set, |
.irq_process = &evergreen_irq_process, |
.get_vblank_counter = &evergreen_get_vblank_counter, |
.fence_ring_emit = &r600_fence_ring_emit, |
// .cs_parse = &r600_cs_parse, |
// .copy_blit = &r600_copy_blit, |
// .copy_dma = &r600_copy_blit, |
// .copy = &r600_copy_blit, |
.cs_parse = &evergreen_cs_parse, |
.copy_blit = &evergreen_copy_blit, |
.copy_dma = &evergreen_copy_blit, |
.copy = &evergreen_copy_blit, |
.get_engine_clock = &radeon_atom_get_engine_clock, |
.set_engine_clock = &radeon_atom_set_engine_clock, |
.get_memory_clock = NULL, |
674,28 → 676,38 |
.set_surface_reg = r600_set_surface_reg, |
.clear_surface_reg = r600_clear_surface_reg, |
.bandwidth_update = &evergreen_bandwidth_update, |
.gui_idle = &r600_gui_idle, |
.pm_misc = &evergreen_pm_misc, |
.pm_prepare = &evergreen_pm_prepare, |
.pm_finish = &evergreen_pm_finish, |
.pm_init_profile = &rs780_pm_init_profile, |
.pm_get_dynpm_state = &r600_pm_get_dynpm_state, |
.pre_page_flip = &evergreen_pre_page_flip, |
.page_flip = &evergreen_page_flip, |
.post_page_flip = &evergreen_post_page_flip, |
}; |
static struct radeon_asic btc_asic = { |
.init = &evergreen_init, |
// .fini = &evergreen_fini, |
// .suspend = &evergreen_suspend, |
// .resume = &evergreen_resume, |
.fini = &evergreen_fini, |
.suspend = &evergreen_suspend, |
.resume = &evergreen_resume, |
.cp_commit = &r600_cp_commit, |
.gpu_is_lockup = &evergreen_gpu_is_lockup, |
.asic_reset = &evergreen_asic_reset, |
.vga_set_state = &r600_vga_set_state, |
.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
.gart_set_page = &rs600_gart_set_page, |
.ring_test = &r600_ring_test, |
.ring_test = NULL, |
// .ring_ib_execute = &r600_ring_ib_execute, |
// .irq_set = &r600_irq_set, |
// .irq_process = &r600_irq_process, |
.get_vblank_counter = &evergreen_get_vblank_counter, |
.fence_ring_emit = &r600_fence_ring_emit, |
// .cs_parse = &r600_cs_parse, |
// .copy_blit = &r600_copy_blit, |
// .copy_dma = &r600_copy_blit, |
// .copy = &r600_copy_blit, |
.cs_parse = &evergreen_cs_parse, |
.copy_blit = &evergreen_copy_blit, |
.copy_dma = &evergreen_copy_blit, |
.copy = &evergreen_copy_blit, |
.get_engine_clock = &radeon_atom_get_engine_clock, |
.set_engine_clock = &radeon_atom_set_engine_clock, |
.get_memory_clock = &radeon_atom_get_memory_clock, |
706,10 → 718,17 |
.set_surface_reg = r600_set_surface_reg, |
.clear_surface_reg = r600_clear_surface_reg, |
.bandwidth_update = &evergreen_bandwidth_update, |
.gui_idle = &r600_gui_idle, |
.pm_misc = &evergreen_pm_misc, |
.pm_prepare = &evergreen_pm_prepare, |
.pm_finish = &evergreen_pm_finish, |
.pm_init_profile = &r600_pm_init_profile, |
.pm_get_dynpm_state = &r600_pm_get_dynpm_state, |
.pre_page_flip = &evergreen_pre_page_flip, |
.page_flip = &evergreen_page_flip, |
.post_page_flip = &evergreen_post_page_flip, |
}; |
#if 0 |
static struct radeon_asic cayman_asic = { |
.init = &cayman_init, |
.fini = &cayman_fini, |
848,22 → 867,6 |
rdev->num_crtc = 6; |
rdev->asic = &evergreen_asic; |
break; |
case CHIP_PALM: |
case CHIP_SUMO: |
case CHIP_SUMO2: |
rdev->asic = &sumo_asic; |
break; |
case CHIP_BARTS: |
case CHIP_TURKS: |
case CHIP_CAICOS: |
/* set num crtcs */ |
if (rdev->family == CHIP_CAICOS) |
rdev->num_crtc = 4; |
else |
rdev->num_crtc = 6; |
rdev->asic = &btc_asic; |
break; |
default: |
/* FIXME: not supported yet */ |
return -EINVAL; |
/drivers/video/drm/radeon/radeon_device.c |
---|
957,7 → 957,7 |
if(!dbg_open(log)) |
{ |
strcpy(log, "/RD/1/DRIVERS/atikms.log"); |
strcpy(log, "/hd2/1/atikms.log"); |
if(!dbg_open(log)) |
{ |