Subversion Repositories Kolibri OS

Compare Revisions

Regard whitespace Rev 1602 → Rev 1601

/kernel/trunk/bus/pci/pci32.inc
1,6 → 1,6
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; ;;
;; Copyright (C) KolibriOS team 2004-2007. All rights reserved. ;;
;; Copyright (C) KolibriOS team 2004-2010. All rights reserved. ;;
;; Distributed under terms of the GNU General Public License ;;
;; ;;
;; ;;
35,14 → 35,14
iglobal
align 4
f62call:
dd pci_fn_0
dd pci_fn_1
dd pci_fn_2
dd pci_service_not_supported ;3
dd pci_api.0
dd pci_api.1
dd pci_api.2
dd pci_api.not_support ;3
dd pci_read_reg ;4 byte
dd pci_read_reg ;5 word
dd pci_read_reg ;6 dword
dd pci_service_not_supported ;7
dd pci_api.not_support ;7
dd pci_write_reg ;8 byte
dd pci_write_reg ;9 word
dd pci_write_reg ;10 dword
51,50 → 51,94
dd pci_mmio_map ;12
dd pci_mmio_unmap ;13
end if
 
f62_rcall:
dd pci_read_reg.0 ;4 byte
dd pci_read_reg.1 ;5 word
dd pci_read_reg.2 ;6 dword
f62_rcall2:
dd pci_read_reg_2.0 ;4 byte
dd pci_read_reg_2.1 ;5 word
dd pci_read_reg_2.2 ;6 dword
f62_wcall:
dd pci_write_reg.0 ;4 byte
dd pci_write_reg.1 ;5 word
dd pci_write_reg.2 ;6 dword
f62_wcall2:
dd pci_write_reg_2.0 ;4 byte
dd pci_write_reg_2.1 ;5 word
dd pci_write_reg_2.2 ;6 dword
endg
 
 
align 4
 
pci_api:
movzx eax,bl
cmp [pci_access_enabled],1
jne pci_service_not_supported
jne .no_pci_access_for_applications
 
;cross
mov eax,ebx
mov ebx,ecx
mov ecx,edx
;;;;;;;;;;;;;;;;;;;
 
if defined mmio_pci_addr
cmp eax, 13
jb pci_service_not_supported
jb .not_support
else
cmp eax, 10
jb pci_service_not_supported
jb .not_support
end if
call dword [f62call+eax*4]
mov dword [esp+32],eax
ret
;; ============================================
 
pci_fn_0:
 
 
; or al,al
; jnz pci_fn_1
; PCI function 0: get pci version (AH.AL)
.0:
movzx eax,word [BOOT_VAR+0x9022]
ret
 
pci_fn_1:
;pci_fn_1:
; cmp al,1
; jnz pci_fn_2
 
; PCI function 1: get last bus in AL
mov al,[BOOT_VAR+0x9021]
.1:
movzx eax, byte [BOOT_VAR+0x9021]
ret
 
pci_fn_2:
;pci_fn_2:
; cmp al,2
; jne pci_fn_3
; PCI function 2: get pci access mechanism
mov al,[BOOT_VAR+0x9020]
.2:
movzx eax, byte [BOOT_VAR+0x9020]
ret
;pci_fn_3:
 
pci_service_not_supported:
; cmp al,4
; jz pci_read_reg ;byte
; cmp al,5
; jz pci_read_reg ;word
; cmp al,6
; jz pci_read_reg ;dword
 
; cmp al,8
; jz pci_write_reg ;byte
; cmp al,9
; jz pci_write_reg ;word
; cmp al,10
; jz pci_write_reg ;dword
 
;if defined mmio_pci_addr
; cmp al,11 ; user-level MMIO functions
; jz pci_mmio_init
; cmp al,12
; jz pci_mmio_map
; cmp al,13
; jz pci_mmio_unmap
;end if
 
.not_support:
.no_pci_access_for_applications:
or eax,-1
ret
 
104,20 → 148,20
;
; Description
; creates a command dword for use with the PCI bus
; bus # in ah
; device+func in bh (dddddfff)
; register in bl
; bus # in bh;ah
; device+func in ch;bh (dddddfff)
; register in cl;bl
;
; command dword returned in eax ( 10000000 bbbbbbbb dddddfff rrrrrr00 )
; command dword returned in ebx;eax ( 10000000 bbbbbbbb dddddfff rrrrrr00 )
;***************************************************************************
 
align 4
 
pci_make_config_cmd:
shl eax,8 ; move bus to bits 16-23
mov ax,bx ; combine all
and eax,0xffffff
or eax,0x80000000
shl ebx,8;eax,8 ; move bus to bits 16-23
mov bx,cx;ax,bx ; combine all
and ebx,0xffffff;eax,0xffffff
or ebx,0x80000000;eax,0x80000000
ret
 
;***************************************************************************
126,8 → 170,8
;
; Description
; read a register from the PCI config space into EAX/AX/AL
; IN: ah=bus,device+func=bh,register address=bl
; number of bytes to read (1,2,4) coded into AL, bits 0-1
; IN: bh=bus,device+func=ch,register address=cl
; number of bytes to read (1,2,4) coded into BL, bits 0-1
; (0 - byte, 1 - word, 2 - dword)
;***************************************************************************
 
138,12 → 182,12
je pci_read_reg_2
 
; mechanism 1
push esi ; save register size into ESI
mov esi,eax
; push esi ; save register size into ESI
mov esi,ebx;eax
and esi,3
 
call pci_make_config_cmd
mov ebx,eax
mov eax,ebx;ebx,eax
; get current state
mov dx,0xcf8
in eax, dx
157,24 → 201,25
and bl,3
or dl,bl ; add to port address first 2 bits of register address
 
or esi,esi
jz pci_read_byte1
cmp esi,1
jz pci_read_word1
cmp esi,2
jz pci_read_dword1
jmp pci_fin_read1
; or esi,esi
; jz pci_read_byte1
; cmp esi,1
; jz pci_read_word1
; cmp esi,2
; jz pci_read_dword1
; jmp pci_fin_read1
jmp dword [f62_rcall+esi*4]
 
pci_read_byte1:
.0:
in al,dx
jmp pci_fin_read1
pci_read_word1:
jmp .pci_fin_read1
.1:
in ax,dx
jmp pci_fin_read1
pci_read_dword1:
jmp .pci_fin_read1
.2:
in eax,dx
jmp pci_fin_read1
pci_fin_read1:
; jmp pci_fin_read1
.pci_fin_read1:
; restore configuration control
xchg eax,[esp]
mov dx,0xcf8
181,18 → 226,19
out dx,eax
 
pop eax
pop esi
;pop esi
ret
pci_read_reg_2:
 
test bh,128 ;mech#2 only supports 16 devices per bus
jnz pci_read_reg_err
test ch,128;bh,128 ;mech#2 only supports 16 devices per bus
jnz pci_api.not_support
 
push esi ; save register size into ESI
mov esi,eax
; push esi ; save register size into ESI
mov esi,ebx;eax
and esi,3
 
push eax
push ebx;eax
mov eax,ebx
;store current state of config space
mov dx,0xcf8
in al,dx
209,29 → 255,31
mov al,0x80
out dx,al
; compute addr
shr bh,3 ; func is ignored in mechanism 2
or bh,0xc0
mov dx,bx
shr ch,3;bh,3 ; func is ignored in mechanism 2
or ch,0xc0;bh,0xc0
mov dx,cx;bx
 
or esi,esi
jz pci_read_byte2
cmp esi,1
jz pci_read_word2
cmp esi,2
jz pci_read_dword2
jmp pci_fin_read2
; or esi,esi
; jz pci_read_byte2
; cmp esi,1
; jz pci_read_word2
; cmp esi,2
; jz pci_read_dword2
; jmp pci_fin_read2
jmp dword [f62_rcall2+esi*4]
 
pci_read_byte2:
.0:
in al,dx
jmp pci_fin_read2
pci_read_word2:
jmp .pci_fin_read2
.1:
in ax,dx
jmp pci_fin_read2
pci_read_dword2:
jmp .pci_fin_read2
.2:
in eax,dx
; jmp pci_fin_read2
pci_fin_read2:
 
.pci_fin_read2:
 
; restore configuration space
xchg eax,[esp]
mov dx,0xcfa
241,13 → 289,12
out dx,al
 
pop eax
pop esi
; pop esi
ret
 
pci_read_reg_err:
xor eax,eax
dec eax
ret
;pci_read_reg_err:
; or dword [esp+32],-1
; ret
 
 
;***************************************************************************
256,9 → 303,9
;
; Description
; write a register from ECX/CX/CL into the PCI config space
; IN: ah=bus,device+func=bh,register address (dword aligned)=bl,
; value to write in ecx
; number of bytes to write (1,2,4) coded into AL, bits 0-1
; IN: bh=bus,device+func=ch,register address (dword aligned)=cl,
; value to write in edx
; number of bytes to write (1,2,4) coded into BL, bits 0-1
; (0 - byte, 1 - word, 2 - dword)
;***************************************************************************
 
269,12 → 316,13
je pci_write_reg_2
 
; mechanism 1
push esi ; save register size into ESI
mov esi,eax
and esi,3
; push esi ; save register size into ESI
mov esi,ebx;eax
and esi,3 ;not need
 
call pci_make_config_cmd
mov ebx,eax
mov eax,ebx;ebx,eax
mov ecx,edx ;cross registers
; get current state into ecx
mov dx,0xcf8
in eax, dx
289,24 → 337,23
or dl,bl
mov eax,ecx
 
or esi,esi
jz pci_write_byte1
cmp esi,1
jz pci_write_word1
cmp esi,2
jz pci_write_dword1
jmp pci_fin_write1
 
pci_write_byte1:
; or esi,esi
; jz pci_write_byte1
; cmp esi,1
; jz pci_write_word1
; cmp esi,2
; jz pci_write_dword1
; jmp pci_fin_write1
jmp dword [f62_wcall+esi*4]
.0:
out dx,al
jmp pci_fin_write1
pci_write_word1:
jmp .pci_fin_write1
.1:
out dx,ax
jmp pci_fin_write1
pci_write_dword1:
jmp .pci_fin_write1
.2:
out dx,eax
jmp pci_fin_write1
pci_fin_write1:
.pci_fin_write1:
 
; restore configuration control
pop eax
314,20 → 361,20
out dx,eax
 
xor eax,eax
pop esi
 
;pop esi
ret
pci_write_reg_2:
 
test bh,128 ;mech#2 only supports 16 devices per bus
jnz pci_write_reg_err
test ch,128;bh,128 ;mech#2 only supports 16 devices per bus
jnz pci_api.not_support
 
 
push esi ; save register size into ESI
; push esi ; save register size into ESI
mov esi,eax
and esi,3
and esi,3 ;not need
 
push eax
mov ecx,edx ;cross registers
;store current state of config space
mov dx,0xcf8
in al,dx
349,24 → 396,23
; write register
mov eax,ecx
 
or esi,esi
jz pci_write_byte2
cmp esi,1
jz pci_write_word2
cmp esi,2
jz pci_write_dword2
jmp pci_fin_write2
 
pci_write_byte2:
; or esi,esi
; jz pci_write_byte2
; cmp esi,1
; jz pci_write_word2
; cmp esi,2
; jz pci_write_dword2
; jmp pci_fin_write2
jmp dword [f62_wcall2+esi*4]
.0:
out dx,al
jmp pci_fin_write2
pci_write_word2:
jmp .pci_fin_write2
.1:
out dx,ax
jmp pci_fin_write2
pci_write_dword2:
jmp .pci_fin_write2
.2:
out dx,eax
jmp pci_fin_write2
pci_fin_write2:
.pci_fin_write2:
; restore configuration space
pop eax
mov dx,0xcfa
376,13 → 422,13
out dx,al
 
xor eax,eax
pop esi
;pop esi
ret
 
pci_write_reg_err:
xor eax,eax
dec eax
ret
;pci_write_reg_err:
; xor eax,eax
; dec eax
; ret
 
if defined mmio_pci_addr ; must be set above
;***************************************************************************
390,7 → 436,7
; pci_mmio_init
;
; Description
; IN: bx = device's PCI bus address (bbbbbbbbdddddfff)
; IN: cx = device's PCI bus address (bbbbbbbbdddddfff)
; Returns eax = user heap space available (bytes)
; Error codes
; eax = -1 : PCI user access blocked,
398,7 → 444,7
; eax = -3 : user heap initialization failure
;***************************************************************************
pci_mmio_init:
cmp bx, mmio_pci_addr
cmp cx, mmio_pci_addr
jz @f
mov eax,-2
ret
422,9 → 468,9
; WARNING! This VERY EXPERIMENTAL service is for one chosen PCI device only!
; The target device address should be set in kernel var mmio_pci_addr
;
; IN: ah = BAR#;
; IN: ebx = block size (bytes);
; IN: ecx = offset in MMIO block (in 4K-pages, to avoid misaligned pages);
; IN: bh = BAR#;
; IN: ecx = block size (bytes);
; IN: edx = offset in MMIO block (in 4K-pages, to avoid misaligned pages);
;
; Returns eax = MMIO block's linear address in the userspace (if no error)
;
439,7 → 485,7
 
pci_mmio_map:
and edx,0x0ffff
cmp ah,6
cmp bh, 6
jc .bar_0_5
jz .bar_rom
mov eax,-2
447,18 → 493,18
.bar_rom:
mov ah, 8 ; bar6 = Expansion ROM base address
.bar_0_5:
push edx
add ecx, 4095
and ecx, 0xFFFFF000 ; 4k-alignment
push ecx
add ebx, 4095
and ebx,-4096
push ebx
mov bl, ah ; bl = BAR# (0..5), however bl=8 for BAR6
shl bl, 1
shl bl, 1
add bl, 0x10 ; now bl = BAR offset in PCI config. space
mov cl, bh ; cl = BAR# (0..5), however cl=8 for BAR6
shl cl, 1
shl cl, 1
add cl, 0x10 ; now cl = BAR offset in PCI config. space
mov ax, mmio_pci_addr
mov bh, al ; bh = dddddfff
mov al, 2 ; al : DW to read
call pci_read_reg
mov ch, al ; ch = dddddfff
mov bl, 2 ; bl : DW to read
call pci_read_reg ; new call
or eax, eax
jnz @f
mov eax,-3 ; empty I/O space
471,7 → 517,7
@@:
pop ecx ; ecx = block size, bytes (expanded to whole page)
mov ebx, ecx ; user_alloc destroys eax, ecx, edx, but saves ebx
and eax, 0xFFFFFFF0
and al, 0xF0 ; clear flags
push eax ; store MMIO physical address + keep 2DWords in the stack
stdcall user_alloc, ecx
or eax, eax
491,9 → 537,7
pop edx ; edx = MMIO shift (pages)
shl edx, 12 ; edx = MMIO shift (bytes)
add eax, edx ; eax = uMMIO physical address
or eax, PG_SHARED
or eax, PG_UW
or eax, PG_NOCACHE
or eax, PG_SHARED+PG_UW+PG_NOCACHE
mov edi, ebx
call commit_pages
mov eax, edi
515,7 → 559,7
;***************************************************************************
 
pci_mmio_unmap:
stdcall user_free, ebx
stdcall user_free, ecx;ebx
ret
 
end if
591,17 → 635,18
jmp ..nxt2
 
.not_FIND_PCI_CLASS_CODE:
mov edx, ecx
cmp ebp, 8 ; READ_CONFIG_*
jb .not_READ_CONFIG
cmp ebp, 0x0A
ja .not_READ_CONFIG
mov eax, ebp
mov ah, bh
mov edx, edi
mov bh, bl
mov bl, dl
mov eax, ebp ; -- ??
; mov ah, bh ; bus
mov ecx, edi
mov ch, bl ; dev+fn
; mov cl, dl ; reg#
call pci_read_reg
mov ecx, eax
mov edx, eax
xor ah, ah ; SUCCESSFUL
jmp .return_abc
.not_READ_CONFIG:
610,10 → 655,10
cmp ebp, 0x0D
ja .not_WRITE_CONFIG
lea eax, [ebp+1]
mov ah, bh
mov edx, edi
mov bh, bl
mov bl, dl
; mov ah, bh ; bus
mov ecx, edi
mov ch, bl
; mov cl, dl
call pci_write_reg
xor ah, ah ; SUCCESSFUL
jmp .return_abc