/drivers/video/drm/i915/i915_dma.c |
---|
1015,11 → 1015,6 |
return -EINVAL; |
} |
// if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { |
// DRM_ERROR("DRM_COPY_TO_USER failed\n"); |
// return -EFAULT; |
// } |
*param->value = value; |
return 0; |
/drivers/video/drm/i915/i915_drv.c |
---|
959,139 → 959,4 |
} |
/* We give fast paths for the really cool registers */ |
#define NEEDS_FORCE_WAKE(dev_priv, reg) \ |
((HAS_FORCE_WAKE((dev_priv)->dev)) && \ |
((reg) < 0x40000) && \ |
((reg) != FORCEWAKE)) |
static bool IS_DISPLAYREG(u32 reg) |
{ |
/* |
* This should make it easier to transition modules over to the |
* new register block scheme, since we can do it incrementally. |
*/ |
if (reg >= VLV_DISPLAY_BASE) |
return false; |
if (reg >= RENDER_RING_BASE && |
reg < RENDER_RING_BASE + 0xff) |
return false; |
if (reg >= GEN6_BSD_RING_BASE && |
reg < GEN6_BSD_RING_BASE + 0xff) |
return false; |
if (reg >= BLT_RING_BASE && |
reg < BLT_RING_BASE + 0xff) |
return false; |
if (reg == PGTBL_ER) |
return false; |
if (reg >= IPEIR_I965 && |
reg < HWSTAM) |
return false; |
if (reg == MI_MODE) |
return false; |
if (reg == GFX_MODE_GEN7) |
return false; |
if (reg == RENDER_HWS_PGA_GEN7 || |
reg == BSD_HWS_PGA_GEN7 || |
reg == BLT_HWS_PGA_GEN7) |
return false; |
if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL || |
reg == GEN6_BSD_RNCID) |
return false; |
if (reg == GEN6_BLITTER_ECOSKPD) |
return false; |
if (reg >= 0x4000c && |
reg <= 0x4002c) |
return false; |
if (reg >= 0x4f000 && |
reg <= 0x4f08f) |
return false; |
if (reg >= 0x4f100 && |
reg <= 0x4f11f) |
return false; |
if (reg >= VLV_MASTER_IER && |
reg <= GEN6_PMIER) |
return false; |
if (reg >= FENCE_REG_SANDYBRIDGE_0 && |
reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8))) |
return false; |
if (reg >= VLV_IIR_RW && |
reg <= VLV_ISR) |
return false; |
if (reg == FORCEWAKE_VLV || |
reg == FORCEWAKE_ACK_VLV) |
return false; |
if (reg == GEN6_GDRST) |
return false; |
switch (reg) { |
case _3D_CHICKEN3: |
case IVB_CHICKEN3: |
case GEN7_COMMON_SLICE_CHICKEN1: |
case GEN7_L3CNTLREG1: |
case GEN7_L3_CHICKEN_MODE_REGISTER: |
case GEN7_ROW_CHICKEN2: |
case GEN7_L3SQCREG4: |
case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG: |
case GEN7_HALF_SLICE_CHICKEN1: |
case GEN6_MBCTL: |
case GEN6_UCGCTL2: |
return false; |
default: |
break; |
} |
return true; |
} |
/* We give fast paths for the really cool registers */ |
#define NEEDS_FORCE_WAKE(dev_priv, reg) \ |
((HAS_FORCE_WAKE((dev_priv)->dev)) && \ |
((reg) < 0x40000) && \ |
((reg) != FORCEWAKE)) |
static void |
ilk_dummy_write(struct drm_i915_private *dev_priv) |
{ |
/* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up |
* the chip from rc6 before touching it for real. MI_MODE is masked, |
* hence harmless to write 0 into. */ |
I915_WRITE_NOTRACE(MI_MODE, 0); |
} |
static void |
hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg) |
{ |
if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) && |
(I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { |
DRM_ERROR("Unknown unclaimed register before writing to %x\n", |
reg); |
I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
} |
} |
static void |
hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg) |
{ |
if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) && |
(I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { |
DRM_ERROR("Unclaimed write to %x\n", reg); |
I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
} |
} |
/drivers/video/drm/i915/intel_display.c |
---|
4560,9 → 4560,9 |
/* Enable DPIO clock input */ |
dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | |
DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; |
if (pipe) |
/* We should never disable this, set it here for state tracking */ |
if (pipe == PIPE_B) |
dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
dpll |= DPLL_VCO_ENABLE; |
crtc->config.dpll_hw_state.dpll = dpll; |
5022,6 → 5022,32 |
I915_READ(LVDS) & LVDS_BORDER_ENABLE; |
} |
static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
struct intel_crtc_config *pipe_config) |
{ |
struct drm_device *dev = crtc->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
int pipe = pipe_config->cpu_transcoder; |
intel_clock_t clock; |
u32 mdiv; |
int refclk = 100000; |
mutex_lock(&dev_priv->dpio_lock); |
mdiv = vlv_dpio_read(dev_priv, DPIO_DIV(pipe)); |
mutex_unlock(&dev_priv->dpio_lock); |
clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; |
clock.m2 = mdiv & DPIO_M2DIV_MASK; |
clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; |
clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; |
clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; |
clock.vco = refclk * clock.m1 * clock.m2 / clock.n; |
clock.dot = 2 * clock.vco / (clock.p1 * clock.p2); |
pipe_config->adjusted_mode.clock = clock.dot / 10; |
} |
static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
struct intel_crtc_config *pipe_config) |
{ |
5553,7 → 5579,7 |
uint16_t postoff = 0; |
if (intel_crtc->config.limited_color_range) |
postoff = (16 * (1 << 13) / 255) & 0x1fff; |
postoff = (16 * (1 << 12) / 255) & 0x1fff; |
I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); |
I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); |
6069,7 → 6095,7 |
/* Make sure we're not on PC8 state before disabling PC8, otherwise |
* we'll hang the machine! */ |
dev_priv->uncore.funcs.force_wake_get(dev_priv); |
gen6_gt_force_wake_get(dev_priv); |
if (val & LCPLL_POWER_DOWN_ALLOW) { |
val &= ~LCPLL_POWER_DOWN_ALLOW; |
6100,7 → 6126,7 |
DRM_ERROR("Switching back to LCPLL failed\n"); |
} |
dev_priv->uncore.funcs.force_wake_put(dev_priv); |
gen6_gt_force_wake_put(dev_priv); |
} |
void hsw_enable_pc8_work(struct work_struct *__work) |
9794,7 → 9820,7 |
dev_priv->display.update_plane = ironlake_update_plane; |
} else if (IS_VALLEYVIEW(dev)) { |
dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
dev_priv->display.get_clock = i9xx_crtc_clock_get; |
dev_priv->display.get_clock = vlv_crtc_clock_get; |
dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
dev_priv->display.crtc_enable = valleyview_crtc_enable; |
dev_priv->display.crtc_disable = i9xx_crtc_disable; |
10028,6 → 10054,8 |
void intel_modeset_init_hw(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
intel_init_power_well(dev); |
intel_prepare_ddi(dev); |
10034,11 → 10062,21 |
intel_init_clock_gating(dev); |
/* Enable the CRI clock source so we can get at the display */ |
if (IS_VALLEYVIEW(dev)) |
I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
DPLL_INTEGRATED_CRI_CLK_VLV); |
mutex_lock(&dev->struct_mutex); |
intel_enable_gt_powersave(dev); |
mutex_unlock(&dev->struct_mutex); |
} |
void intel_modeset_suspend_hw(struct drm_device *dev) |
{ |
intel_suspend_hw(dev); |
} |
void intel_modeset_init(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
/drivers/video/drm/i915/intel_dvo.c |
---|
171,11 → 171,16 |
{ |
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
u32 dvo_reg = intel_dvo->dev.dvo_reg; |
u32 temp = I915_READ(dvo_reg); |
I915_WRITE(dvo_reg, temp | DVO_ENABLE); |
I915_READ(dvo_reg); |
intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev, |
&crtc->config.requested_mode, |
&crtc->config.adjusted_mode); |
intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true); |
} |
184,6 → 189,7 |
{ |
struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
struct drm_crtc *crtc; |
struct intel_crtc_config *config; |
/* dvo supports only 2 dpms states. */ |
if (mode != DRM_MODE_DPMS_ON) |
204,10 → 210,16 |
/* We call connector dpms manually below in case pipe dpms doesn't |
* change due to cloning. */ |
if (mode == DRM_MODE_DPMS_ON) { |
config = &to_intel_crtc(crtc)->config; |
intel_dvo->base.connectors_active = true; |
intel_crtc_update_dpms(crtc); |
intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev, |
&config->requested_mode, |
&config->adjusted_mode); |
intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true); |
} else { |
intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false); |
299,10 → 311,6 |
break; |
} |
intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev, |
&crtc->config.requested_mode, |
adjusted_mode); |
/* Save the data order, since I don't know what it should be set to. */ |
dvo_val = I915_READ(dvo_reg) & |
(DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG); |
/drivers/video/drm/i915/kms_display.c |
---|
746,12 → 746,6 |
u32 slot; |
int ret=0; |
if(mask->handle == -2) |
{ |
printf("%s handle %d\n", __FUNCTION__, mask->handle); |
return 0; |
} |
obj = drm_gem_object_lookup(dev, file, mask->handle); |
if (obj == NULL) |
return -ENOENT; |
827,7 → 821,7 |
while( tmp_h--) |
{ |
int tmp_w = mask->bo_pitch; |
int tmp_w = mask->width; |
u8* tmp_src = src_offset; |
u8* tmp_dst = dst_offset; |
875,7 → 869,7 |
tmp_dst += 32; |
} |
while( tmp_w > 0 ) |
if( tmp_w >= 16 ) |
{ |
__asm__ __volatile__ ( |
"movdqu (%0), %%xmm0 \n" |
887,6 → 881,33 |
tmp_src += 16; |
tmp_dst += 16; |
} |
if( tmp_w >= 8 ) |
{ |
__asm__ __volatile__ ( |
"movq (%0), %%xmm0 \n" |
"pcmpeqb %%xmm6, %%xmm0 \n" |
"movq %%xmm0, (%%edi) \n" |
:: "r" (tmp_src), "D" (tmp_dst) |
:"xmm0"); |
tmp_w -= 8; |
tmp_src += 8; |
tmp_dst += 8; |
} |
if( tmp_w >= 4 ) |
{ |
__asm__ __volatile__ ( |
"movd (%0), %%xmm0 \n" |
"pcmpeqb %%xmm6, %%xmm0 \n" |
"movd %%xmm0, (%%edi) \n" |
:: "r" (tmp_src), "D" (tmp_dst) |
:"xmm0"); |
tmp_w -= 4; |
tmp_src += 4; |
tmp_dst += 4; |
} |
while(tmp_w--) |
*tmp_dst++ = (*tmp_src++ == (u8)slot) ? 0xFF:0x00; |
}; |
}; |
safe_sti(ifl); |
/drivers/video/drm/i915/main.c |
---|
167,8 → 167,9 |
if( GetService("DISPLAY") != 0 ) |
return 0; |
printf("i915 v3.12\n\nusage: i915 [options]\n" |
"-pm=<0,1> Enable powersavings, fbc, downclocking, etc. (default: 0 - false)\n"); |
printf("\ni915 v3.12.5 build %s %s\nusage: i915 [options]\n" |
"-pm=<0,1> Enable powersavings, fbc, downclocking, etc. (default: 0 - false)\n", |
__DATE__, __TIME__); |
printf("-rc6=<-1,0-7> Enable power-saving render C-state 6.\n" |
" Different stages can be selected via bitmask values\n" |
" (0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6).\n" |