/drivers/video/drm/i915/bitmap.c |
---|
6,20 → 6,28 |
#include "intel_drv.h" |
#include "bitmap.h" |
#define DRIVER_CAPS_0 HW_BIT_BLIT | HW_TEX_BLIT; |
#define DRIVER_CAPS_1 0 |
extern struct drm_device *main_device; |
struct hman bm_man; |
void __attribute__((regparm(1))) destroy_bitmap(bitmap_t *bitmap) |
{ |
printf("destroy bitmap %d\n", bitmap->handle); |
free_handle(&bm_man, bitmap->handle); |
bitmap->handle = 0; |
i915_gem_object_unpin(bitmap->obj); |
bitmap->obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
bitmap->obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
mutex_lock(&main_device->struct_mutex); |
drm_gem_object_unreference(&bitmap->obj->base); |
mutex_unlock(&main_device->struct_mutex); |
__DestroyObject(bitmap); |
}; |
extern struct drm_device *main_device; |
struct hman bm_man; |
int init_bitmaps() |
{ |
int ret; |
124,10 → 132,12 |
{ |
*dst++ = (0xFFFFF000 & *src++) | 0x207 ; // map as shared page |
}; |
// while(max_count--) |
// *dst++ = 0; // cleanup unused space |
while(max_count--) |
*dst++ = 0; // cleanup unused space |
} |
obj->mapped = uaddr ; |
bitmap->handle = handle; |
bitmap->uaddr = uaddr; |
bitmap->pitch = pitch; |
221,3 → 231,83 |
}; |
void *drm_intel_bo_map(struct drm_i915_gem_object *obj, int write_enable) |
{ |
u8 *kaddr; |
kaddr = AllocKernelSpace(obj->base.size); |
if( kaddr != NULL) |
{ |
u32_t *src = (u32_t*)obj->pages; |
u32_t *dst = &((u32_t*)page_tabs)[(u32_t)kaddr >> 12]; |
u32 count = obj->base.size/4096; |
while(count--) |
{ |
*dst++ = (0xFFFFF000 & *src++) | 0x003 ; |
}; |
return kaddr; |
}; |
return NULL; |
} |
void destroy_gem_object(uint32_t handle) |
{ |
struct drm_i915_gem_object *obj = (void*)handle; |
drm_gem_object_unreference(&obj->base); |
}; |
void write_gem_object(uint32_t handle, u32 offset, u32 size, u8* src) |
{ |
struct drm_i915_gem_object *obj = (void*)handle; |
u8 *dst; |
int ret; |
ret = i915_gem_object_pin(obj, 4096, true); |
if (ret) |
return; |
dst = drm_intel_bo_map(obj, true); |
if( dst != NULL ) |
{ |
memmove(dst+offset, src, size); |
FreeKernelSpace(dst); |
}; |
}; |
u32 get_buffer_offset(uint32_t handle) |
{ |
struct drm_i915_gem_object *obj = (void*)handle; |
return obj->gtt_offset; |
}; |
int get_driver_caps(hwcaps_t *caps) |
{ |
int ret = 0; |
ENTER(); |
dbgprintf("caps ptr %x\n", caps); |
switch(caps->idx) |
{ |
case 0: |
caps->opt[0] = DRIVER_CAPS_0; |
caps->opt[1] = DRIVER_CAPS_1; |
break; |
case 1: |
caps->cap1.max_tex_width = 4096; |
caps->cap1.max_tex_height = 4096; |
break; |
default: |
ret = 1; |
}; |
caps->idx = 1; |
return ret; |
} |
/drivers/video/drm/i915/bitmap.h |
---|
66,6 → 66,25 |
u32 format; // reserved mbz |
}; |
typedef struct |
{ |
uint32_t idx; |
union |
{ |
uint32_t opt[2]; |
struct { |
uint32_t max_tex_width; |
uint32_t max_tex_height; |
}cap1; |
}; |
}hwcaps_t; |
#define HW_BIT_BLIT (1<<0) /* BGRX blitter */ |
#define HW_TEX_BLIT (1<<1) /* stretch blit */ |
#define HW_VID_BLIT (1<<2) /* planar and packed video */ |
/* 3 - 63 reserved */ |
int get_driver_caps(hwcaps_t *caps); |
int create_surface(struct io_call_10 *pbitmap); |
int init_bitmaps(); |
/drivers/video/drm/i915/i915_dma.c |
---|
34,7 → 34,7 |
#include "i915_drm.h" |
#include "i915_drv.h" |
#include <drm/intel-gtt.h> |
//#include "i915_trace.h" |
#include "i915_trace.h" |
//#include "../../../platform/x86/intel_ips.h" |
#include <linux/pci.h> |
//#include <linux/vgaarb.h> |
241,9 → 241,9 |
intel_modeset_gem_init(dev); |
// ret = drm_irq_install(dev); |
// if (ret) |
// goto cleanup_gem; |
ret = drm_irq_install(dev); |
if (ret) |
goto cleanup_gem; |
/* Always safe in the mode setting case. */ |
/* FIXME: do pre/post-mode set stuff in core KMS code */ |
521,9 → 521,8 |
/* enable GEM by default */ |
dev_priv->has_gem = 1; |
intel_irq_init(dev); |
// intel_irq_init(dev); |
/* Try to make sure MCHBAR is enabled before poking at it */ |
intel_setup_mchbar(dev); |
intel_setup_gmbus(dev); |
/drivers/video/drm/i915/i915_drm.h |
---|
491,7 → 491,7 |
__u32 delta; |
/** Offset in the buffer the relocation entry will be written into */ |
__u64 offset; |
__u32 offset; |
/** |
* Offset value of the target buffer that the relocation entry was last |
501,7 → 501,7 |
* and writing the relocation. This value is written back out by |
* the execbuffer ioctl when the relocation is written. |
*/ |
__u64 presumed_offset; |
__u32 presumed_offset; |
/** |
* Target memory domains read by this operation. |
/drivers/video/drm/i915/i915_drv.c |
---|
444,8 → 444,6 |
if (ret) |
goto err_g4; |
main_device = dev; |
LEAVE(); |
return 0; |
/drivers/video/drm/i915/i915_gem.c |
---|
29,7 → 29,7 |
#include "drm.h" |
#include "i915_drm.h" |
#include "i915_drv.h" |
//#include "i915_trace.h" |
#include "i915_trace.h" |
#include "intel_drv.h" |
//#include <linux/shmem_fs.h> |
#include <linux/slab.h> |
236,6 → 236,7 |
return 0; |
} |
#endif |
int |
i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
246,8 → 247,6 |
struct drm_i915_gem_object *obj; |
size_t pinned; |
if (!(dev->driver->driver_features & DRIVER_GEM)) |
return -ENODEV; |
pinned = 0; |
mutex_lock(&dev->struct_mutex); |
261,8 → 260,9 |
return 0; |
} |
static int |
i915_gem_create(struct drm_file *file, |
#if 0 |
int i915_gem_create(struct drm_file *file, |
struct drm_device *dev, |
uint64_t size, |
uint32_t *handle_p) |
290,6 → 290,7 |
/* drop reference from allocate - handle holds it now */ |
drm_gem_object_unreference(&obj->base); |
trace_i915_gem_object_create(obj); |
*handle_p = handle; |
return 0; |
745,8 → 746,6 |
static int |
i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
gfp_t gfpmask) |
794,8 → 793,6 |
int page_count = obj->base.size / PAGE_SIZE; |
int i; |
ENTER(); |
BUG_ON(obj->madv == __I915_MADV_PURGED); |
// if (obj->tiling_mode != I915_TILING_NONE) |
811,8 → 808,6 |
free(obj->pages); |
obj->pages = NULL; |
LEAVE(); |
} |
void |
994,9 → 989,13 |
old_read_domains = obj->base.read_domains; |
old_write_domain = obj->base.write_domain; |
obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; |
obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; |
trace_i915_gem_object_change_domain(obj, |
old_read_domains, |
old_write_domain); |
} |
/** |
1007,7 → 1006,6 |
{ |
int ret = 0; |
ENTER(); |
if (obj->gtt_space == NULL) |
return 0; |
1047,6 → 1045,7 |
if (ret == -ERESTARTSYS) |
return ret; |
trace_i915_gem_object_unbind(obj); |
i915_gem_gtt_unbind_object(obj); |
i915_gem_object_put_pages_gtt(obj); |
1063,7 → 1062,6 |
if (i915_gem_object_is_purgeable(obj)) |
i915_gem_object_truncate(obj); |
LEAVE(); |
return ret; |
} |
1077,6 → 1075,7 |
if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0) |
return 0; |
trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains); |
ret = ring->flush(ring, invalidate_domains, flush_domains); |
if (ret) |
1239,9 → 1238,6 |
/** |
* i915_gem_clear_fence_reg - clear out fence register info |
* @obj: object to clear |
1423,6 → 1419,7 |
obj->map_and_fenceable = mappable && fenceable; |
trace_i915_gem_object_bind(obj, map_and_fenceable); |
return 0; |
} |
1528,6 → 1525,9 |
old_write_domain = obj->base.write_domain; |
obj->base.write_domain = 0; |
trace_i915_gem_object_change_domain(obj, |
obj->base.read_domains, |
old_write_domain); |
} |
/** Flushes the CPU write domain for the object if it's dirty. */ |
1544,6 → 1544,9 |
old_write_domain = obj->base.write_domain; |
obj->base.write_domain = 0; |
trace_i915_gem_object_change_domain(obj, |
obj->base.read_domains, |
old_write_domain); |
} |
/** |
1591,6 → 1594,10 |
obj->dirty = 1; |
} |
trace_i915_gem_object_change_domain(obj, |
old_read_domains, |
old_write_domain); |
return 0; |
} |
1646,6 → 1653,9 |
obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
trace_i915_gem_object_change_domain(obj, |
old_read_domains, |
old_write_domain); |
} |
obj->cache_level = cache_level; |
1713,6 → 1723,9 |
BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
trace_i915_gem_object_change_domain(obj, |
old_read_domains, |
old_write_domain); |
return 0; |
} |
1790,6 → 1803,9 |
obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
} |
trace_i915_gem_object_change_domain(obj, |
old_read_domains, |
old_write_domain); |
return 0; |
} |
1933,8 → 1949,6 |
struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
size_t size) |
{ |
2000,8 → 2014,6 |
drm_i915_private_t *dev_priv = dev->dev_private; |
int ret; |
ENTER(); |
ret = i915_gem_object_unbind(obj); |
if (ret == -ERESTARTSYS) { |
list_move(&obj->mm_list, |
2009,6 → 2021,7 |
return; |
} |
trace_i915_gem_object_destroy(obj); |
// if (obj->base.map_list.map) |
// drm_gem_free_mmap_offset(&obj->base); |
2019,7 → 2032,6 |
kfree(obj->page_cpu_valid); |
kfree(obj->bit_17); |
kfree(obj); |
LEAVE(); |
} |
void i915_gem_free_object(struct drm_gem_object *gem_obj) |
2027,7 → 2039,6 |
struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
struct drm_device *dev = obj->base.dev; |
ENTER(); |
while (obj->pin_count > 0) |
i915_gem_object_unpin(obj); |
2035,7 → 2046,6 |
// i915_gem_detach_phys_object(dev, obj); |
i915_gem_free_object_tail(obj); |
LEAVE(); |
} |
2054,7 → 2064,7 |
{ |
drm_i915_private_t *dev_priv = dev->dev_private; |
int ret; |
ENTER(); |
ret = intel_init_render_ring_buffer(dev); |
if (ret) |
return ret; |
2072,7 → 2082,7 |
} |
dev_priv->next_seqno = 1; |
LEAVE(); |
return 0; |
cleanup_bsd_ring: |
/drivers/video/drm/i915/i915_gem_gtt.c |
---|
26,7 → 26,7 |
#include "drm.h" |
#include "i915_drm.h" |
#include "i915_drv.h" |
//#include "i915_trace.h" |
#include "i915_trace.h" |
#include "intel_drv.h" |
#define AGP_USER_TYPES (1 << 16) |
/drivers/video/drm/i915/i915_irq.c |
---|
0,0 → 1,442 |
/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
*/ |
/* |
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
* All Rights Reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
* copy of this software and associated documentation files (the |
* "Software"), to deal in the Software without restriction, including |
* without limitation the rights to use, copy, modify, merge, publish, |
* distribute, sub license, and/or sell copies of the Software, and to |
* permit persons to whom the Software is furnished to do so, subject to |
* the following conditions: |
* |
* The above copyright notice and this permission notice (including the |
* next paragraph) shall be included in all copies or substantial portions |
* of the Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
* |
*/ |
#include <linux/irqreturn.h> |
//#include <linux/slab.h> |
#include "drmP.h" |
#include "drm.h" |
#include "i915_drm.h" |
#include "i915_drv.h" |
#include "i915_trace.h" |
#include "intel_drv.h" |
#define MAX_NOPID ((u32)~0) |
/** |
* Interrupts that are always left unmasked. |
* |
* Since pipe events are edge-triggered from the PIPESTAT register to IIR, |
* we leave them always unmasked in IMR and then control enabling them through |
* PIPESTAT alone. |
*/ |
#define I915_INTERRUPT_ENABLE_FIX \ |
(I915_ASLE_INTERRUPT | \ |
I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ |
I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ |
I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \ |
I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \ |
I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
/** Interrupts that we mask and unmask at runtime. */ |
#define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT) |
#define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ |
PIPE_VBLANK_INTERRUPT_STATUS) |
#define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\ |
PIPE_VBLANK_INTERRUPT_ENABLE) |
#define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ |
DRM_I915_VBLANK_PIPE_B) |
/* For display hotplug interrupt */ |
static void |
ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
{ |
if ((dev_priv->irq_mask & mask) != 0) { |
dev_priv->irq_mask &= ~mask; |
I915_WRITE(DEIMR, dev_priv->irq_mask); |
POSTING_READ(DEIMR); |
} |
} |
static inline void |
ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
{ |
if ((dev_priv->irq_mask & mask) != mask) { |
dev_priv->irq_mask |= mask; |
I915_WRITE(DEIMR, dev_priv->irq_mask); |
POSTING_READ(DEIMR); |
} |
} |
static int ironlake_irq_handler(struct drm_device *dev) |
{ |
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
int ret = IRQ_NONE; |
u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir; |
u32 hotplug_mask; |
struct drm_i915_master_private *master_priv; |
u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT; |
atomic_inc(&dev_priv->irq_received); |
if (IS_GEN6(dev)) |
bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT; |
/* disable master interrupt before clearing iir */ |
de_ier = I915_READ(DEIER); |
I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); |
POSTING_READ(DEIER); |
de_iir = I915_READ(DEIIR); |
gt_iir = I915_READ(GTIIR); |
pch_iir = I915_READ(SDEIIR); |
pm_iir = I915_READ(GEN6_PMIIR); |
if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && |
(!IS_GEN6(dev) || pm_iir == 0)) |
goto done; |
if (HAS_PCH_CPT(dev)) |
hotplug_mask = SDE_HOTPLUG_MASK_CPT; |
else |
hotplug_mask = SDE_HOTPLUG_MASK; |
ret = IRQ_HANDLED; |
// if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY)) |
// notify_ring(dev, &dev_priv->ring[RCS]); |
// if (gt_iir & bsd_usr_interrupt) |
// notify_ring(dev, &dev_priv->ring[VCS]); |
// if (gt_iir & GT_BLT_USER_INTERRUPT) |
// notify_ring(dev, &dev_priv->ring[BCS]); |
// if (de_iir & DE_GSE) |
// intel_opregion_gse_intr(dev); |
// if (de_iir & DE_PLANEA_FLIP_DONE) { |
// intel_prepare_page_flip(dev, 0); |
// intel_finish_page_flip_plane(dev, 0); |
// } |
// if (de_iir & DE_PLANEB_FLIP_DONE) { |
// intel_prepare_page_flip(dev, 1); |
// intel_finish_page_flip_plane(dev, 1); |
// } |
// if (de_iir & DE_PIPEA_VBLANK) |
// drm_handle_vblank(dev, 0); |
// if (de_iir & DE_PIPEB_VBLANK) |
// drm_handle_vblank(dev, 1); |
/* check event from PCH */ |
// if (de_iir & DE_PCH_EVENT) { |
// if (pch_iir & hotplug_mask) |
// queue_work(dev_priv->wq, &dev_priv->hotplug_work); |
// pch_irq_handler(dev); |
// } |
// if (de_iir & DE_PCU_EVENT) { |
// I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
// i915_handle_rps_change(dev); |
// } |
if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) { |
/* |
* IIR bits should never already be set because IMR should |
* prevent an interrupt from being shown in IIR. The warning |
* displays a case where we've unsafely cleared |
* dev_priv->pm_iir. Although missing an interrupt of the same |
* type is not a problem, it displays a problem in the logic. |
* |
* The mask bit in IMR is cleared by rps_work. |
*/ |
unsigned long flags; |
spin_lock_irqsave(&dev_priv->rps_lock, flags); |
WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n"); |
dev_priv->pm_iir |= pm_iir; |
I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir); |
POSTING_READ(GEN6_PMIMR); |
spin_unlock_irqrestore(&dev_priv->rps_lock, flags); |
// queue_work(dev_priv->wq, &dev_priv->rps_work); |
} |
/* should clear PCH hotplug event before clear CPU irq */ |
I915_WRITE(SDEIIR, pch_iir); |
I915_WRITE(GTIIR, gt_iir); |
I915_WRITE(DEIIR, de_iir); |
I915_WRITE(GEN6_PMIIR, pm_iir); |
done: |
I915_WRITE(DEIER, de_ier); |
POSTING_READ(DEIER); |
return ret; |
} |
/* drm_dma.h hooks |
*/ |
static void ironlake_irq_preinstall(struct drm_device *dev) |
{ |
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
atomic_set(&dev_priv->irq_received, 0); |
// INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
// INIT_WORK(&dev_priv->error_work, i915_error_work_func); |
// if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
// INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work); |
I915_WRITE(HWSTAM, 0xeffe); |
if (IS_GEN6(dev)) { |
/* Workaround stalls observed on Sandy Bridge GPUs by |
* making the blitter command streamer generate a |
* write to the Hardware Status Page for |
* MI_USER_INTERRUPT. This appears to serialize the |
* previous seqno write out before the interrupt |
* happens. |
*/ |
I915_WRITE(GEN6_BLITTER_HWSTAM, ~GEN6_BLITTER_USER_INTERRUPT); |
I915_WRITE(GEN6_BSD_HWSTAM, ~GEN6_BSD_USER_INTERRUPT); |
} |
/* XXX hotplug from PCH */ |
I915_WRITE(DEIMR, 0xffffffff); |
I915_WRITE(DEIER, 0x0); |
POSTING_READ(DEIER); |
/* and GT */ |
I915_WRITE(GTIMR, 0xffffffff); |
I915_WRITE(GTIER, 0x0); |
POSTING_READ(GTIER); |
/* south display irq */ |
I915_WRITE(SDEIMR, 0xffffffff); |
I915_WRITE(SDEIER, 0x0); |
POSTING_READ(SDEIER); |
} |
/* |
* Enable digital hotplug on the PCH, and configure the DP short pulse |
* duration to 2ms (which is the minimum in the Display Port spec) |
* |
* This register is the same on all known PCH chips. |
*/ |
static void ironlake_enable_pch_hotplug(struct drm_device *dev) |
{ |
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
u32 hotplug; |
hotplug = I915_READ(PCH_PORT_HOTPLUG); |
hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); |
hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; |
hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; |
hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; |
I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
} |
static int ironlake_irq_postinstall(struct drm_device *dev) |
{ |
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
/* enable kind of interrupts always enabled */ |
u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; |
u32 render_irqs; |
u32 hotplug_mask; |
// DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue); |
// if (HAS_BSD(dev)) |
// DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue); |
// if (HAS_BLT(dev)) |
// DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue); |
dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
dev_priv->irq_mask = ~display_mask; |
/* should always can generate irq */ |
I915_WRITE(DEIIR, I915_READ(DEIIR)); |
I915_WRITE(DEIMR, dev_priv->irq_mask); |
I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK); |
POSTING_READ(DEIER); |
dev_priv->gt_irq_mask = ~0; |
I915_WRITE(GTIIR, I915_READ(GTIIR)); |
I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
if (IS_GEN6(dev)) |
render_irqs = |
GT_USER_INTERRUPT | |
GT_GEN6_BSD_USER_INTERRUPT | |
GT_BLT_USER_INTERRUPT; |
else |
render_irqs = |
GT_USER_INTERRUPT | |
GT_PIPE_NOTIFY | |
GT_BSD_USER_INTERRUPT; |
I915_WRITE(GTIER, render_irqs); |
POSTING_READ(GTIER); |
if (HAS_PCH_CPT(dev)) { |
hotplug_mask = (SDE_CRT_HOTPLUG_CPT | |
SDE_PORTB_HOTPLUG_CPT | |
SDE_PORTC_HOTPLUG_CPT | |
SDE_PORTD_HOTPLUG_CPT); |
} else { |
hotplug_mask = (SDE_CRT_HOTPLUG | |
SDE_PORTB_HOTPLUG | |
SDE_PORTC_HOTPLUG | |
SDE_PORTD_HOTPLUG | |
SDE_AUX_MASK); |
} |
dev_priv->pch_irq_mask = ~hotplug_mask; |
I915_WRITE(SDEIIR, I915_READ(SDEIIR)); |
I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); |
I915_WRITE(SDEIER, hotplug_mask); |
POSTING_READ(SDEIER); |
ironlake_enable_pch_hotplug(dev); |
if (IS_IRONLAKE_M(dev)) { |
/* Clear & enable PCU event interrupts */ |
I915_WRITE(DEIIR, DE_PCU_EVENT); |
I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT); |
ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
} |
return 0; |
} |
void intel_irq_init(struct drm_device *dev) |
{ |
#if 0 |
if (IS_IVYBRIDGE(dev)) { |
/* Share pre & uninstall handlers with ILK/SNB */ |
dev->driver->irq_handler = ivybridge_irq_handler; |
dev->driver->irq_preinstall = ironlake_irq_preinstall; |
dev->driver->irq_postinstall = ivybridge_irq_postinstall; |
dev->driver->irq_uninstall = ironlake_irq_uninstall; |
dev->driver->enable_vblank = ivybridge_enable_vblank; |
dev->driver->disable_vblank = ivybridge_disable_vblank; |
} else if (HAS_PCH_SPLIT(dev)) { |
dev->driver->irq_handler = ironlake_irq_handler; |
dev->driver->irq_preinstall = ironlake_irq_preinstall; |
dev->driver->irq_postinstall = ironlake_irq_postinstall; |
dev->driver->irq_uninstall = ironlake_irq_uninstall; |
dev->driver->enable_vblank = ironlake_enable_vblank; |
dev->driver->disable_vblank = ironlake_disable_vblank; |
} else { |
dev->driver->irq_preinstall = i915_driver_irq_preinstall; |
dev->driver->irq_postinstall = i915_driver_irq_postinstall; |
dev->driver->irq_uninstall = i915_driver_irq_uninstall; |
dev->driver->irq_handler = i915_driver_irq_handler; |
dev->driver->enable_vblank = i915_enable_vblank; |
dev->driver->disable_vblank = i915_disable_vblank; |
} |
#endif |
} |
static struct drm_device *irq_device; |
void irq_handler_kms() |
{ |
// printf("%s\n",__FUNCTION__); |
ironlake_irq_handler(irq_device); |
} |
int drm_irq_install(struct drm_device *dev) |
{ |
int irq_line; |
int ret = 0; |
ENTER(); |
mutex_lock(&dev->struct_mutex); |
/* Driver must have been initialized */ |
if (!dev->dev_private) { |
mutex_unlock(&dev->struct_mutex); |
return -EINVAL; |
} |
if (dev->irq_enabled) { |
mutex_unlock(&dev->struct_mutex); |
return -EBUSY; |
} |
dev->irq_enabled = 1; |
mutex_unlock(&dev->struct_mutex); |
irq_device = dev; |
irq_line = drm_dev_to_irq(dev); |
DRM_DEBUG("irq=%d\n", drm_dev_to_irq(dev)); |
ironlake_irq_preinstall(dev); |
ret = AttachIntHandler(irq_line, irq_handler_kms, 2); |
if (ret == 0) { |
mutex_lock(&dev->struct_mutex); |
dev->irq_enabled = 0; |
mutex_unlock(&dev->struct_mutex); |
return ret; |
} |
ret = ironlake_irq_postinstall(dev); |
// if (ret < 0) { |
// mutex_lock(&dev->struct_mutex); |
// dev->irq_enabled = 0; |
// mutex_unlock(&dev->struct_mutex); |
// free_irq(drm_dev_to_irq(dev), dev); |
// } |
u16_t cmd = PciRead16(dev->pdev->busnr, dev->pdev->devfn, 4); |
cmd&= ~(1<<10); |
PciWrite16(dev->pdev->busnr, dev->pdev->devfn, 4, cmd); |
dbgprintf("PCI_CMD: %04x\n", cmd); |
DRM_INFO("i915: irq initialized.\n"); |
LEAVE(); |
return ret; |
} |
/drivers/video/drm/i915/i915_trace.h |
---|
0,0 → 1,17 |
#if !defined(_I915_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ) |
#define _I915_TRACE_H_ |
//#include <linux/stringify.h> |
#include <linux/types.h> |
//#include <linux/tracepoint.h> |
#define trace_i915_gem_object_create(x) |
#define trace_i915_gem_object_destroy(x) |
#define trace_i915_gem_object_change_domain(a, b, c) |
#define trace_i915_gem_object_unbind(x) |
#define trace_i915_gem_ring_flush(a, b, c) |
#define trace_i915_gem_object_bind(a, b) |
#define trace_i915_ring_wait_end(x) |
#endif |
/drivers/video/drm/i915/intel_display.c |
---|
36,9 → 36,8 |
#include "intel_drv.h" |
#include "i915_drm.h" |
#include "i915_drv.h" |
//#include "i915_trace.h" |
#include "i915_trace.h" |
#include "drm_dp_helper.h" |
#include "drm_crtc_helper.h" |
phys_addr_t get_bus_addr(void); |
4510,8 → 4509,6 |
int fbc_wm, plane_wm, cursor_wm; |
unsigned int enabled; |
ENTER(); |
enabled = 0; |
if (g4x_compute_wm0(dev, 0, |
&sandybridge_display_wm_info, latency, |
4794,10 → 4791,9 |
static void intel_update_watermarks(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
ENTER(); |
if (dev_priv->display.update_wm) |
dev_priv->display.update_wm(dev); |
LEAVE(); |
} |
void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, |
/drivers/video/drm/i915/intel_dp.c |
---|
206,17 → 206,8 |
*/ |
static int |
intel_dp_link_required(struct intel_dp *intel_dp, int pixel_clock, int check_bpp) |
intel_dp_link_required(int pixel_clock, int bpp) |
{ |
struct drm_crtc *crtc = intel_dp->base.base.crtc; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
int bpp = 24; |
if (check_bpp) |
bpp = check_bpp; |
else if (intel_crtc) |
bpp = intel_crtc->bpp; |
return (pixel_clock * bpp + 9) / 10; |
} |
243,12 → 234,11 |
return MODE_PANEL; |
} |
mode_rate = intel_dp_link_required(intel_dp, mode->clock, 0); |
mode_rate = intel_dp_link_required(mode->clock, 24); |
max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); |
if (mode_rate > max_rate) { |
mode_rate = intel_dp_link_required(intel_dp, |
mode->clock, 18); |
mode_rate = intel_dp_link_required(mode->clock, 18); |
if (mode_rate > max_rate) |
return MODE_CLOCK_HIGH; |
else |
681,7 → 671,7 |
int lane_count, clock; |
int max_lane_count = intel_dp_max_lane_count(intel_dp); |
int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; |
int bpp = mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 0; |
int bpp = mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24; |
static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) { |
699,7 → 689,7 |
for (clock = 0; clock <= max_clock; clock++) { |
int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); |
if (intel_dp_link_required(intel_dp, mode->clock, bpp) |
if (intel_dp_link_required(mode->clock, bpp) |
<= link_avail) { |
intel_dp->link_bw = bws[clock]; |
intel_dp->lane_count = lane_count; |
/drivers/video/drm/i915/intel_lvds.c |
---|
622,7 → 622,7 |
.destroy = intel_encoder_destroy, |
}; |
static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
{ |
DRM_DEBUG_KMS("Skipping LVDS initialization for %s\n", id->ident); |
return 1; |
696,6 → 696,14 |
}, |
{ |
.callback = intel_no_lvds_dmi_callback, |
.ident = "AOpen i45GMx-I", |
.matches = { |
DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), |
DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), |
}, |
}, |
{ |
.callback = intel_no_lvds_dmi_callback, |
.ident = "Aopen i945GTt-VFA", |
.matches = { |
DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), |
/drivers/video/drm/i915/intel_ringbuffer.c |
---|
33,7 → 33,7 |
#include "drm.h" |
#include "i915_drv.h" |
#include "i915_drm.h" |
//#include "i915_trace.h" |
#include "i915_trace.h" |
#include "intel_drv.h" |
/* |
1139,8 → 1139,6 |
unsigned long end; |
u32 head; |
ENTER(); |
/* If the reported head position has wrapped or hasn't advanced, |
* fallback to the slow and accurate path. |
*/ |
1149,10 → 1147,7 |
ring->head = head; |
ring->space = ring_space(ring); |
if (ring->space >= n) |
{ |
LEAVE(); |
return 0; |
}; |
} |
1161,20 → 1156,15 |
ring->head = I915_READ_HEAD(ring); |
ring->space = ring_space(ring); |
if (ring->space >= n) { |
// trace_i915_ring_wait_end(ring); |
LEAVE(); |
trace_i915_ring_wait_end(ring); |
return 0; |
} |
msleep(1); |
if (atomic_read(&dev_priv->mm.wedged)) |
{ |
LEAVE(); |
return -EAGAIN; |
}; |
} while (!time_after(jiffies, end)); |
LEAVE(); |
trace_i915_ring_wait_end(ring); |
return -EBUSY; |
} |
/drivers/video/drm/i915/kms_display.c |
---|
17,7 → 17,9 |
#include "bitmap.h" |
extern struct drm_device *main_device; |
typedef struct |
{ |
kobj_t header; |
67,6 → 69,9 |
u32_t cmd_buffer; |
u32_t cmd_offset; |
void init_render(); |
int sna_init(); |
int init_cursor(cursor_t *cursor); |
static cursor_t* __stdcall select_cursor_kms(cursor_t *cursor); |
static void __stdcall move_cursor_kms(cursor_t *cursor, int x, int y); |
210,6 → 215,8 |
}; |
#endif |
main_device = dev; |
int err; |
err = init_bitmaps(); |
218,6 → 225,8 |
printf("Initialize bitmap manager\n"); |
}; |
sna_init(); |
LEAVE(); |
return 0; |
577,7 → 586,6 |
return old; |
}; |
extern struct drm_device *main_device; |
#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) |
748,6 → 756,7 |
#else |
u8* src_offset; |
u8* dst_offset; |
u32 ifl; |
src_offset = (u8*)(src_y*bitmap->pitch + src_x*4); |
src_offset += (u32)bitmap->uaddr; |
757,6 → 766,7 |
u32_t tmp_h = height; |
ifl = safe_cli(); |
while( tmp_h--) |
{ |
u32_t tmp_w = width; |
774,6 → 784,7 |
tmp_dst++; |
}; |
}; |
safe_sti(ifl); |
} |
#endif |
810,14 → 821,12 |
i915_gem_object_set_to_gtt_domain(bitmap->obj, false); |
if (HAS_BLT(main_device)) |
{ |
int ret; |
ring = &dev_priv->ring[BCS]; |
else |
ring = &dev_priv->ring[RCS]; |
ring->dispatch_execbuffer(ring, cmd_offset, n*4); |
int ret; |
ret = intel_ring_begin(ring, 4); |
if (ret) |
return ret; |
827,8 → 836,179 |
intel_ring_emit(ring, 0); |
intel_ring_emit(ring, MI_NOOP); |
intel_ring_advance(ring); |
} |
else |
{ |
ring = &dev_priv->ring[RCS]; |
ring->dispatch_execbuffer(ring, cmd_offset, n*4); |
ring->flush(ring, 0, I915_GEM_DOMAIN_RENDER); |
}; |
bitmap->obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
bitmap->obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
return 0; |
fail: |
return -1; |
}; |
/* For display hotplug interrupt */ |
static void |
ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
{ |
if ((dev_priv->irq_mask & mask) != 0) { |
dev_priv->irq_mask &= ~mask; |
I915_WRITE(DEIMR, dev_priv->irq_mask); |
POSTING_READ(DEIMR); |
} |
} |
static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
{ |
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
unsigned long irqflags; |
// if (!i915_pipe_enabled(dev, pipe)) |
// return -EINVAL; |
spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
ironlake_enable_display_irq(dev_priv, (pipe == 0) ? |
DE_PIPEA_VBLANK : DE_PIPEB_VBLANK); |
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
return 0; |
} |
static int i915_interrupt_info(struct drm_device *dev) |
{ |
drm_i915_private_t *dev_priv = dev->dev_private; |
int ret, i, pipe; |
if (!HAS_PCH_SPLIT(dev)) { |
dbgprintf("Interrupt enable: %08x\n", |
I915_READ(IER)); |
dbgprintf("Interrupt identity: %08x\n", |
I915_READ(IIR)); |
dbgprintf("Interrupt mask: %08x\n", |
I915_READ(IMR)); |
for_each_pipe(pipe) |
dbgprintf("Pipe %c stat: %08x\n", |
pipe_name(pipe), |
I915_READ(PIPESTAT(pipe))); |
} else { |
dbgprintf("North Display Interrupt enable: %08x\n", |
I915_READ(DEIER)); |
dbgprintf("North Display Interrupt identity: %08x\n", |
I915_READ(DEIIR)); |
dbgprintf("North Display Interrupt mask: %08x\n", |
I915_READ(DEIMR)); |
dbgprintf("South Display Interrupt enable: %08x\n", |
I915_READ(SDEIER)); |
dbgprintf("South Display Interrupt identity: %08x\n", |
I915_READ(SDEIIR)); |
dbgprintf("South Display Interrupt mask: %08x\n", |
I915_READ(SDEIMR)); |
dbgprintf("Graphics Interrupt enable: %08x\n", |
I915_READ(GTIER)); |
dbgprintf("Graphics Interrupt identity: %08x\n", |
I915_READ(GTIIR)); |
dbgprintf("Graphics Interrupt mask: %08x\n", |
I915_READ(GTIMR)); |
} |
dbgprintf("Interrupts received: %d\n", |
atomic_read(&dev_priv->irq_received)); |
for (i = 0; i < I915_NUM_RINGS; i++) { |
if (IS_GEN6(dev) || IS_GEN7(dev)) { |
printf("Graphics Interrupt mask (%s): %08x\n", |
dev_priv->ring[i].name, |
I915_READ_IMR(&dev_priv->ring[i])); |
} |
// i915_ring_seqno_info(m, &dev_priv->ring[i]); |
} |
return 0; |
} |
void execute_buffer (struct drm_i915_gem_object *buffer, uint32_t offset, |
int size) |
{ |
struct intel_ring_buffer *ring; |
drm_i915_private_t *dev_priv = main_device->dev_private; |
u32 invalidate; |
u32 seqno = 2; |
offset += buffer->gtt_offset; |
// dbgprintf("execute %x size %d\n", offset, size); |
// asm volatile( |
// "mfence \n" |
// "wbinvd \n" |
// "mfence \n" |
// :::"memory"); |
ring = &dev_priv->ring[RCS]; |
ring->dispatch_execbuffer(ring, offset, size); |
invalidate = I915_GEM_DOMAIN_COMMAND; |
if (INTEL_INFO(main_device)->gen >= 4) |
invalidate |= I915_GEM_DOMAIN_SAMPLER; |
if (ring->flush(ring, invalidate, 0)) |
i915_gem_next_request_seqno(ring); |
ring->irq_get(ring); |
ring->add_request(ring, &seqno); |
// i915_interrupt_info(main_device); |
// ironlake_enable_vblank(main_device, 0); |
}; |
int blit_textured(u32 hbitmap, int dst_x, int dst_y, |
int src_x, int src_y, u32 w, u32 h) |
{ |
drm_i915_private_t *dev_priv = main_device->dev_private; |
bitmap_t *src_bitmap, *dst_bitmap; |
bitmap_t screen; |
rect_t winrc; |
// dbgprintf(" handle: %d dx %d dy %d sx %d sy %d w %d h %d\n", |
// hbitmap, dst_x, dst_y, src_x, src_y, w, h); |
if(unlikely(hbitmap==0)) |
return -1; |
src_bitmap = (bitmap_t*)hman_get_data(&bm_man, hbitmap); |
// dbgprintf("bitmap %x\n", src_bitmap); |
if(unlikely(src_bitmap==NULL)) |
return -1; |
GetWindowRect(&winrc); |
screen.pitch = os_display->pitch; |
screen.gaddr = 0; |
screen.width = os_display->width; |
screen.height = os_display->height; |
screen.obj = (void*)-1; |
dst_bitmap = &screen; |
dst_x+= winrc.left; |
dst_y+= winrc.top; |
i915_gem_object_set_to_gtt_domain(src_bitmap->obj, false); |
sna_blit_copy(dst_bitmap, dst_x, dst_y, w, h, src_bitmap, src_x, src_y); |
src_bitmap->obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
src_bitmap->obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
}; |
/drivers/video/drm/i915/main.c |
---|
20,10 → 20,12 |
int _stdcall display_handler(ioctl_t *io); |
int init_agp(void); |
int create_video(int width, int height, u32_t *outp); |
int video_blit(uint64_t src_offset, int x, int y, |
int w, int h, int pitch); |
int blit_video(u32 hbitmap, int dst_x, int dst_y, |
int src_x, int src_y, u32 w, u32 h); |
int blit_textured(u32 hbitmap, int dst_x, int dst_y, |
int src_x, int src_y, u32 w, u32 h); |
static char log[256]; |
int x86_clflush_size; |
47,7 → 49,8 |
if(!dbg_open(log)) |
{ |
strcpy(log, "/RD/1/DRIVERS/i915.log"); |
// strcpy(log, "/RD/1/DRIVERS/i915.log"); |
strcpy(log, "/HD1/2/i915.log"); |
if(!dbg_open(log)) |
{ |
57,6 → 60,9 |
} |
dbgprintf("i915 blitter preview\n cmdline: %s\n", cmdline); |
cpu_detect(); |
dbgprintf("\ncache line size %d\n", x86_clflush_size); |
enum_pci_devices(); |
err = i915_init(); |
79,12 → 85,13 |
#define COMPATIBLE_API 0x0100 /* 1.00 */ |
#define API_VERSION (COMPATIBLE_API << 16) | CURRENT_API |
#define DISPLAY_VERSION CURRENT_API |
#define DISPLAY_VERSION API_VERSION |
#define SRV_GETVERSION 0 |
#define SRV_ENUM_MODES 1 |
#define SRV_SET_MODE 2 |
#define SRV_GET_CAPS 3 |
#define SRV_CREATE_SURFACE 10 |
132,6 → 139,10 |
retval = set_user_mode((videomode_t*)inp); |
break; |
case SRV_GET_CAPS: |
retval = get_driver_caps((hwcaps_t*)inp); |
break; |
case SRV_CREATE_SURFACE: |
// check_input(8); |
retval = create_surface((struct io_call_10*)inp); |
139,7 → 150,10 |
case SRV_BLIT_VIDEO: |
blit_video( inp[0], inp[1], inp[2], |
// blit_video( inp[0], inp[1], inp[2], |
// inp[3], inp[4], inp[5], inp[6]); |
blit_textured( inp[0], inp[1], inp[2], |
inp[3], inp[4], inp[5], inp[6]); |
retval = 0; |
211,19 → 225,22 |
}; |
}; |
static inline void __cpuid(unsigned int *eax, unsigned int *ebx, |
unsigned int *ecx, unsigned int *edx) |
{ |
/* ecx is often an input as well as an output. */ |
asm volatile( |
"cpuid" |
asm volatile("cpuid" |
: "=a" (*eax), |
"=b" (*ebx), |
"=c" (*ecx), |
"=d" (*edx) |
: "" (*eax), "2" (*ecx)); |
: "0" (*eax), "2" (*ecx) |
: "memory"); |
} |
static inline void cpuid(unsigned int op, |
unsigned int *eax, unsigned int *ebx, |
unsigned int *ecx, unsigned int *edx) |
/drivers/video/drm/i915/pci.c |
---|
350,11 → 350,11 |
hdr = PciRead8(busnr, devfn, PCI_HEADER_TYPE); |
dev = (pci_dev_t*)kzalloc(sizeof(pci_dev_t), 0); |
if(unlikely(dev == NULL)) |
return NULL; |
INIT_LIST_HEAD(&dev->link); |
if(unlikely(dev == NULL)) |
return NULL; |
dev->pci_dev.busnr = busnr; |
dev->pci_dev.devfn = devfn; |
/drivers/video/drm/i915/render/exa_wm_src_affine.g6b |
---|
0,0 → 1,4 |
{ 0x0060005a, 0x204077be, 0x000000c0, 0x008d0040 }, |
{ 0x0060005a, 0x206077be, 0x000000c0, 0x008d0080 }, |
{ 0x0060005a, 0x208077be, 0x000000d0, 0x008d0040 }, |
{ 0x0060005a, 0x20a077be, 0x000000d0, 0x008d0080 }, |
/drivers/video/drm/i915/render/exa_wm_src_projective.g6b |
---|
0,0 → 1,12 |
{ 0x0060005a, 0x23c077bd, 0x000000e0, 0x008d0040 }, |
{ 0x0060005a, 0x23e077bd, 0x000000e0, 0x008d0080 }, |
{ 0x01600038, 0x218003bd, 0x008d03c0, 0x00000000 }, |
{ 0x01600038, 0x21a003bd, 0x008d03e0, 0x00000000 }, |
{ 0x0060005a, 0x23c077bd, 0x000000c0, 0x008d0040 }, |
{ 0x0060005a, 0x23e077bd, 0x000000c0, 0x008d0080 }, |
{ 0x00600041, 0x204077be, 0x008d03c0, 0x008d0180 }, |
{ 0x00600041, 0x206077be, 0x008d03e0, 0x008d01a0 }, |
{ 0x0060005a, 0x23c077bd, 0x000000d0, 0x008d0040 }, |
{ 0x0060005a, 0x23e077bd, 0x000000d0, 0x008d0080 }, |
{ 0x00600041, 0x208077be, 0x008d03c0, 0x008d0180 }, |
{ 0x00600041, 0x20a077be, 0x008d03e0, 0x008d01a0 }, |
/drivers/video/drm/i915/render/exa_wm_src_sample_argb.g6b |
---|
0,0 → 1,3 |
{ 0x00000201, 0x20080061, 0x00000000, 0x00000000 }, |
{ 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, |
{ 0x02800031, 0x21c01cc9, 0x00000020, 0x0a8a0001 }, |
/drivers/video/drm/i915/render/exa_wm_write.g6b |
---|
0,0 → 1,17 |
{ 0x00600001, 0x204003be, 0x008d01c0, 0x00000000 }, |
{ 0x00600001, 0x206003be, 0x008d01e0, 0x00000000 }, |
{ 0x00600001, 0x208003be, 0x008d0200, 0x00000000 }, |
{ 0x00600001, 0x20a003be, 0x008d0220, 0x00000000 }, |
{ 0x00600001, 0x20c003be, 0x008d0240, 0x00000000 }, |
{ 0x00600001, 0x20e003be, 0x008d0260, 0x00000000 }, |
{ 0x00600001, 0x210003be, 0x008d0280, 0x00000000 }, |
{ 0x00600001, 0x212003be, 0x008d02a0, 0x00000000 }, |
{ 0x05800031, 0x24001cc8, 0x00000040, 0x90019000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
/drivers/video/drm/i915/render |
---|
Property changes: |
Added: bugtraq:number |
+true |
\ No newline at end of property |
/drivers/video/drm/i915/sna/compiler.h |
---|
0,0 → 1,55 |
/* |
* Copyright (c) 2011 Intel Corporation |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
* copy of this software and associated documentation files (the "Software"), |
* to deal in the Software without restriction, including without limitation |
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
* and/or sell copies of the Software, and to permit persons to whom the |
* Software is furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice (including the next |
* paragraph) shall be included in all copies or substantial portions of the |
* Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
* SOFTWARE. |
* |
* Authors: |
* Chris Wilson <chris@chris-wilson.co.uk> |
* |
*/ |
#ifndef _SNA_COMPILER_H_ |
#define _SNA_COMPILER_H_ |
#if defined(__GNUC__) && (__GNUC__ > 2) && defined(__OPTIMIZE__) |
#define noinline __attribute__((noinline)) |
#define fastcall __attribute__((regparm(3))) |
#define must_check __attribute__((warn_unused_result)) |
#define constant __attribute__((const)) |
#else |
#define likely(expr) (expr) |
#define unlikely(expr) (expr) |
#define noinline |
#define fastcall |
#define must_check |
#define constant |
#endif |
#ifdef HAVE_VALGRIND |
#define VG(x) x |
#else |
#define VG(x) |
#endif |
#define VG_CLEAR(s) VG(memset(&s, 0, sizeof(s))) |
#define COMPILE_TIME_ASSERT(E) ((void)sizeof(char[1 - 2*!(E)])) |
#endif /* _SNA_COMPILER_H_ */ |
/drivers/video/drm/i915/sna/gen6_render.c |
---|
0,0 → 1,1990 |
/* |
* Copyright © 2006,2008,2011 Intel Corporation |
* Copyright © 2007 Red Hat, Inc. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
* copy of this software and associated documentation files (the "Software"), |
* to deal in the Software without restriction, including without limitation |
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
* and/or sell copies of the Software, and to permit persons to whom the |
* Software is furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice (including the next |
* paragraph) shall be included in all copies or substantial portions of the |
* Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
* SOFTWARE. |
* |
* Authors: |
* Wang Zhenyu <zhenyu.z.wang@sna.com> |
* Eric Anholt <eric@anholt.net> |
* Carl Worth <cworth@redhat.com> |
* Keith Packard <keithp@keithp.com> |
* Chris Wilson <chris@chris-wilson.co.uk> |
* |
*/ |
#include <drmP.h> |
#include <drm.h> |
#include "i915_drm.h" |
#include "i915_drv.h" |
#include "intel_drv.h" |
#include <linux/kernel.h> |
#include <linux/module.h> |
#include <errno-base.h> |
#include <memory.h> |
#include <syscall.h> |
#include "../bitmap.h" |
#include "sna.h" |
//#include "sna_reg.h" |
#include "sna_render.h" |
//#include "sna_render_inline.h" |
//#include "sna_video.h" |
#include "gen6_render.h" |
#define NO_COMPOSITE 0 |
#define NO_COMPOSITE_SPANS 0 |
#define NO_COPY 0 |
#define NO_COPY_BOXES 0 |
#define NO_FILL 0 |
#define NO_FILL_BOXES 0 |
#define NO_CLEAR 0 |
#define NO_RING_SWITCH 1 |
#define GEN6_MAX_SIZE 8192 |
static const uint32_t ps_kernel_nomask_affine[][4] = { |
#include "exa_wm_src_affine.g6b" |
#include "exa_wm_src_sample_argb.g6b" |
#include "exa_wm_write.g6b" |
}; |
static const uint32_t ps_kernel_nomask_projective[][4] = { |
#include "exa_wm_src_projective.g6b" |
#include "exa_wm_src_sample_argb.g6b" |
#include "exa_wm_write.g6b" |
}; |
#define KERNEL(kernel_enum, kernel, masked) \ |
[GEN6_WM_KERNEL_##kernel_enum] = {#kernel_enum, kernel, sizeof(kernel), masked} |
static const struct wm_kernel_info { |
const char *name; |
const void *data; |
unsigned int size; |
Bool has_mask; |
} wm_kernels[] = { |
KERNEL(NOMASK, ps_kernel_nomask_affine, FALSE), |
KERNEL(NOMASK_PROJECTIVE, ps_kernel_nomask_projective, FALSE), |
}; |
#undef KERNEL |
static const struct blendinfo { |
Bool src_alpha; |
uint32_t src_blend; |
uint32_t dst_blend; |
} gen6_blend_op[] = { |
/* Clear */ {0, GEN6_BLENDFACTOR_ZERO, GEN6_BLENDFACTOR_ZERO}, |
/* Src */ {0, GEN6_BLENDFACTOR_ONE, GEN6_BLENDFACTOR_ZERO}, |
/* Dst */ {0, GEN6_BLENDFACTOR_ZERO, GEN6_BLENDFACTOR_ONE}, |
/* Over */ {1, GEN6_BLENDFACTOR_ONE, GEN6_BLENDFACTOR_INV_SRC_ALPHA}, |
/* OverReverse */ {0, GEN6_BLENDFACTOR_INV_DST_ALPHA, GEN6_BLENDFACTOR_ONE}, |
/* In */ {0, GEN6_BLENDFACTOR_DST_ALPHA, GEN6_BLENDFACTOR_ZERO}, |
/* InReverse */ {1, GEN6_BLENDFACTOR_ZERO, GEN6_BLENDFACTOR_SRC_ALPHA}, |
/* Out */ {0, GEN6_BLENDFACTOR_INV_DST_ALPHA, GEN6_BLENDFACTOR_ZERO}, |
/* OutReverse */ {1, GEN6_BLENDFACTOR_ZERO, GEN6_BLENDFACTOR_INV_SRC_ALPHA}, |
/* Atop */ {1, GEN6_BLENDFACTOR_DST_ALPHA, GEN6_BLENDFACTOR_INV_SRC_ALPHA}, |
/* AtopReverse */ {1, GEN6_BLENDFACTOR_INV_DST_ALPHA, GEN6_BLENDFACTOR_SRC_ALPHA}, |
/* Xor */ {1, GEN6_BLENDFACTOR_INV_DST_ALPHA, GEN6_BLENDFACTOR_INV_SRC_ALPHA}, |
/* Add */ {0, GEN6_BLENDFACTOR_ONE, GEN6_BLENDFACTOR_ONE}, |
}; |
/** |
* Highest-valued BLENDFACTOR used in gen6_blend_op. |
* |
* This leaves out GEN6_BLENDFACTOR_INV_DST_COLOR, |
* GEN6_BLENDFACTOR_INV_CONST_{COLOR,ALPHA}, |
* GEN6_BLENDFACTOR_INV_SRC1_{COLOR,ALPHA} |
*/ |
#define GEN6_BLENDFACTOR_COUNT (GEN6_BLENDFACTOR_INV_DST_ALPHA + 1) |
/* FIXME: surface format defined in gen6_defines.h, shared Sampling engine |
* 1.7.2 |
static const struct formatinfo { |
CARD32 pict_fmt; |
uint32_t card_fmt; |
} gen6_tex_formats[] = { |
{PICT_a8, GEN6_SURFACEFORMAT_A8_UNORM}, |
{PICT_a8r8g8b8, GEN6_SURFACEFORMAT_B8G8R8A8_UNORM}, |
{PICT_x8r8g8b8, GEN6_SURFACEFORMAT_B8G8R8X8_UNORM}, |
{PICT_a8b8g8r8, GEN6_SURFACEFORMAT_R8G8B8A8_UNORM}, |
{PICT_x8b8g8r8, GEN6_SURFACEFORMAT_R8G8B8X8_UNORM}, |
{PICT_r8g8b8, GEN6_SURFACEFORMAT_R8G8B8_UNORM}, |
{PICT_r5g6b5, GEN6_SURFACEFORMAT_B5G6R5_UNORM}, |
{PICT_a1r5g5b5, GEN6_SURFACEFORMAT_B5G5R5A1_UNORM}, |
{PICT_a2r10g10b10, GEN6_SURFACEFORMAT_B10G10R10A2_UNORM}, |
{PICT_x2r10g10b10, GEN6_SURFACEFORMAT_B10G10R10X2_UNORM}, |
{PICT_a2b10g10r10, GEN6_SURFACEFORMAT_R10G10B10A2_UNORM}, |
{PICT_x2r10g10b10, GEN6_SURFACEFORMAT_B10G10R10X2_UNORM}, |
{PICT_a4r4g4b4, GEN6_SURFACEFORMAT_B4G4R4A4_UNORM}, |
}; |
*/ |
#define GEN6_BLEND_STATE_PADDED_SIZE ALIGN(sizeof(struct gen6_blend_state), 64) |
#define BLEND_OFFSET(s, d) \ |
(((s) * GEN6_BLENDFACTOR_COUNT + (d)) * GEN6_BLEND_STATE_PADDED_SIZE) |
#define SAMPLER_OFFSET(sf, se, mf, me) \ |
(((((sf) * EXTEND_COUNT + (se)) * FILTER_COUNT + (mf)) * EXTEND_COUNT + (me)) * 2 * sizeof(struct gen6_sampler_state)) |
#define OUT_BATCH(v) batch_emit(sna, v) |
#define OUT_VERTEX(x,y) vertex_emit_2s(sna, x,y) |
#define OUT_VERTEX_F(v) vertex_emit(sna, v) |
static inline bool too_large(int width, int height) |
{ |
return width > GEN6_MAX_SIZE || height > GEN6_MAX_SIZE; |
} |
static uint32_t gen6_get_blend(int op, |
bool has_component_alpha, |
uint32_t dst_format) |
{ |
uint32_t src, dst; |
src = GEN6_BLENDFACTOR_ONE; //gen6_blend_op[op].src_blend; |
dst = GEN6_BLENDFACTOR_ZERO; //gen6_blend_op[op].dst_blend; |
#if 0 |
/* If there's no dst alpha channel, adjust the blend op so that |
* we'll treat it always as 1. |
*/ |
if (PICT_FORMAT_A(dst_format) == 0) { |
if (src == GEN6_BLENDFACTOR_DST_ALPHA) |
src = GEN6_BLENDFACTOR_ONE; |
else if (src == GEN6_BLENDFACTOR_INV_DST_ALPHA) |
src = GEN6_BLENDFACTOR_ZERO; |
} |
/* If the source alpha is being used, then we should only be in a |
* case where the source blend factor is 0, and the source blend |
* value is the mask channels multiplied by the source picture's alpha. |
*/ |
if (has_component_alpha && gen6_blend_op[op].src_alpha) { |
if (dst == GEN6_BLENDFACTOR_SRC_ALPHA) |
dst = GEN6_BLENDFACTOR_SRC_COLOR; |
else if (dst == GEN6_BLENDFACTOR_INV_SRC_ALPHA) |
dst = GEN6_BLENDFACTOR_INV_SRC_COLOR; |
} |
DBG(("blend op=%d, dst=%x [A=%d] => src=%d, dst=%d => offset=%x\n", |
op, dst_format, PICT_FORMAT_A(dst_format), |
src, dst, (int)BLEND_OFFSET(src, dst))); |
#endif |
return BLEND_OFFSET(src, dst); |
} |
static uint32_t gen6_get_dest_format(CARD32 format) |
{ |
return GEN6_SURFACEFORMAT_B8G8R8A8_UNORM; |
/* |
switch (format) { |
default: |
assert(0); |
case PICT_a8r8g8b8: |
case PICT_x8r8g8b8: |
return GEN6_SURFACEFORMAT_B8G8R8A8_UNORM; |
case PICT_a8b8g8r8: |
case PICT_x8b8g8r8: |
return GEN6_SURFACEFORMAT_R8G8B8A8_UNORM; |
case PICT_a2r10g10b10: |
case PICT_x2r10g10b10: |
return GEN6_SURFACEFORMAT_B10G10R10A2_UNORM; |
case PICT_r5g6b5: |
return GEN6_SURFACEFORMAT_B5G6R5_UNORM; |
case PICT_x1r5g5b5: |
case PICT_a1r5g5b5: |
return GEN6_SURFACEFORMAT_B5G5R5A1_UNORM; |
case PICT_a8: |
return GEN6_SURFACEFORMAT_A8_UNORM; |
case PICT_a4r4g4b4: |
case PICT_x4r4g4b4: |
return GEN6_SURFACEFORMAT_B4G4R4A4_UNORM; |
} |
*/ |
} |
#if 0 |
static Bool gen6_check_dst_format(PictFormat format) |
{ |
switch (format) { |
case PICT_a8r8g8b8: |
case PICT_x8r8g8b8: |
case PICT_a8b8g8r8: |
case PICT_x8b8g8r8: |
case PICT_a2r10g10b10: |
case PICT_x2r10g10b10: |
case PICT_r5g6b5: |
case PICT_x1r5g5b5: |
case PICT_a1r5g5b5: |
case PICT_a8: |
case PICT_a4r4g4b4: |
case PICT_x4r4g4b4: |
return TRUE; |
} |
return FALSE; |
} |
static bool gen6_check_format(uint32_t format) |
{ |
switch (format) { |
case PICT_a8r8g8b8: |
case PICT_x8r8g8b8: |
case PICT_a8b8g8r8: |
case PICT_x8b8g8r8: |
case PICT_a2r10g10b10: |
case PICT_x2r10g10b10: |
case PICT_r8g8b8: |
case PICT_r5g6b5: |
case PICT_a1r5g5b5: |
case PICT_a8: |
case PICT_a4r4g4b4: |
case PICT_x4r4g4b4: |
return true; |
default: |
DBG(("%s: unhandled format: %x\n", __FUNCTION__, format)); |
return false; |
} |
} |
static uint32_t gen6_filter(uint32_t filter) |
{ |
switch (filter) { |
default: |
assert(0); |
case PictFilterNearest: |
return SAMPLER_FILTER_NEAREST; |
case PictFilterBilinear: |
return SAMPLER_FILTER_BILINEAR; |
} |
} |
static uint32_t gen6_check_filter(PicturePtr picture) |
{ |
switch (picture->filter) { |
case PictFilterNearest: |
case PictFilterBilinear: |
return TRUE; |
default: |
return FALSE; |
} |
} |
static uint32_t gen6_repeat(uint32_t repeat) |
{ |
switch (repeat) { |
default: |
assert(0); |
case RepeatNone: |
return SAMPLER_EXTEND_NONE; |
case RepeatNormal: |
return SAMPLER_EXTEND_REPEAT; |
case RepeatPad: |
return SAMPLER_EXTEND_PAD; |
case RepeatReflect: |
return SAMPLER_EXTEND_REFLECT; |
} |
} |
static bool gen6_check_repeat(PicturePtr picture) |
{ |
if (!picture->repeat) |
return TRUE; |
switch (picture->repeatType) { |
case RepeatNone: |
case RepeatNormal: |
case RepeatPad: |
case RepeatReflect: |
return TRUE; |
default: |
return FALSE; |
} |
} |
#endif |
static int |
gen6_choose_composite_kernel(int op, Bool has_mask, Bool is_ca, Bool is_affine) |
{ |
int base; |
if (has_mask) { |
/* |
if (is_ca) { |
if (gen6_blend_op[op].src_alpha) |
base = GEN6_WM_KERNEL_MASKCA_SRCALPHA; |
else |
base = GEN6_WM_KERNEL_MASKCA; |
} else |
base = GEN6_WM_KERNEL_MASK; |
*/ |
} else |
base = GEN6_WM_KERNEL_NOMASK; |
return base + !is_affine; |
} |
static void |
gen6_emit_urb(struct sna *sna) |
{ |
OUT_BATCH(GEN6_3DSTATE_URB | (3 - 2)); |
OUT_BATCH(((1 - 1) << GEN6_3DSTATE_URB_VS_SIZE_SHIFT) | |
(24 << GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT)); /* at least 24 on GEN6 */ |
OUT_BATCH((0 << GEN6_3DSTATE_URB_GS_SIZE_SHIFT) | |
(0 << GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT)); /* no GS thread */ |
} |
static void |
gen6_emit_state_base_address(struct sna *sna) |
{ |
OUT_BATCH(GEN6_STATE_BASE_ADDRESS | (10 - 2)); |
OUT_BATCH(0); /* general */ |
// OUT_BATCH(kgem_add_reloc(&sna->kgem, /* surface */ |
// sna->kgem.nbatch, |
// NULL, |
// I915_GEM_DOMAIN_INSTRUCTION << 16, |
// BASE_ADDRESS_MODIFY)); |
OUT_BATCH((sna->kgem.batch_obj->gtt_offset+ |
sna->kgem.batch_idx*4096)|BASE_ADDRESS_MODIFY); |
// OUT_BATCH(kgem_add_reloc(&sna->kgem, /* instruction */ |
// sna->kgem.nbatch, |
// sna->render_state.gen6.general_bo, |
// I915_GEM_DOMAIN_INSTRUCTION << 16, |
// BASE_ADDRESS_MODIFY)); |
OUT_BATCH(sna->render_state.gen6.general_bo->gaddr|BASE_ADDRESS_MODIFY); |
OUT_BATCH(0); /* indirect */ |
// OUT_BATCH(kgem_add_reloc(&sna->kgem, |
// sna->kgem.nbatch, |
// sna->render_state.gen6.general_bo, |
// I915_GEM_DOMAIN_INSTRUCTION << 16, |
// BASE_ADDRESS_MODIFY)); |
OUT_BATCH(sna->render_state.gen6.general_bo->gaddr|BASE_ADDRESS_MODIFY); |
/* upper bounds, disable */ |
OUT_BATCH(0); |
OUT_BATCH(BASE_ADDRESS_MODIFY); |
OUT_BATCH(0); |
OUT_BATCH(BASE_ADDRESS_MODIFY); |
} |
static void |
gen6_emit_viewports(struct sna *sna) |
{ |
OUT_BATCH(GEN6_3DSTATE_VIEWPORT_STATE_POINTERS | |
GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC | |
(4 - 2)); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(sna->render_state.gen6.cc_vp); |
} |
static void |
gen6_emit_vs(struct sna *sna) |
{ |
/* disable VS constant buffer */ |
OUT_BATCH(GEN6_3DSTATE_CONSTANT_VS | (5 - 2)); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(GEN6_3DSTATE_VS | (6 - 2)); |
OUT_BATCH(0); /* no VS kernel */ |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); /* pass-through */ |
} |
static void |
gen6_emit_gs(struct sna *sna) |
{ |
/* disable GS constant buffer */ |
OUT_BATCH(GEN6_3DSTATE_CONSTANT_GS | (5 - 2)); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(GEN6_3DSTATE_GS | (7 - 2)); |
OUT_BATCH(0); /* no GS kernel */ |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); /* pass-through */ |
} |
static void |
gen6_emit_clip(struct sna *sna) |
{ |
OUT_BATCH(GEN6_3DSTATE_CLIP | (4 - 2)); |
OUT_BATCH(0); |
OUT_BATCH(0); /* pass-through */ |
OUT_BATCH(0); |
} |
static void |
gen6_emit_wm_constants(struct sna *sna) |
{ |
/* disable WM constant buffer */ |
OUT_BATCH(GEN6_3DSTATE_CONSTANT_PS | (5 - 2)); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
} |
static void |
gen6_emit_null_depth_buffer(struct sna *sna) |
{ |
OUT_BATCH(GEN6_3DSTATE_DEPTH_BUFFER | (7 - 2)); |
OUT_BATCH(GEN6_SURFACE_NULL << GEN6_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT | |
GEN6_DEPTHFORMAT_D32_FLOAT << GEN6_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(GEN6_3DSTATE_CLEAR_PARAMS | (2 - 2)); |
OUT_BATCH(0); |
} |
static void |
gen6_emit_invariant(struct sna *sna) |
{ |
OUT_BATCH(GEN6_PIPELINE_SELECT | PIPELINE_SELECT_3D); |
OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | (3 - 2)); |
OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER | |
GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */ |
OUT_BATCH(0); |
OUT_BATCH(GEN6_3DSTATE_SAMPLE_MASK | (2 - 2)); |
OUT_BATCH(1); |
gen6_emit_urb(sna); |
gen6_emit_state_base_address(sna); |
gen6_emit_viewports(sna); |
gen6_emit_vs(sna); |
gen6_emit_gs(sna); |
gen6_emit_clip(sna); |
gen6_emit_wm_constants(sna); |
gen6_emit_null_depth_buffer(sna); |
sna->render_state.gen6.needs_invariant = FALSE; |
} |
static bool |
gen6_emit_cc(struct sna *sna, |
int op, bool has_component_alpha, uint32_t dst_format) |
{ |
struct gen6_render_state *render = &sna->render_state.gen6; |
uint32_t blend; |
blend = gen6_get_blend(op, has_component_alpha, dst_format); |
DBG(("%s(op=%d, ca=%d, format=%x): new=%x, current=%x\n", |
__FUNCTION__, |
op, has_component_alpha, dst_format, |
blend, render->blend)); |
if (render->blend == blend) |
return op <= PictOpSrc; |
OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2)); |
OUT_BATCH((render->cc_blend + blend) | 1); |
if (render->blend == (unsigned)-1) { |
OUT_BATCH(1); |
OUT_BATCH(1); |
} else { |
OUT_BATCH(0); |
OUT_BATCH(0); |
} |
render->blend = blend; |
return op <= PictOpSrc; |
} |
static void |
gen6_emit_sampler(struct sna *sna, uint32_t state) |
{ |
assert(state < |
2 * sizeof(struct gen6_sampler_state) * |
FILTER_COUNT * EXTEND_COUNT * |
FILTER_COUNT * EXTEND_COUNT); |
if (sna->render_state.gen6.samplers == state) |
return; |
sna->render_state.gen6.samplers = state; |
OUT_BATCH(GEN6_3DSTATE_SAMPLER_STATE_POINTERS | |
GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS | |
(4 - 2)); |
OUT_BATCH(0); /* VS */ |
OUT_BATCH(0); /* GS */ |
OUT_BATCH(sna->render_state.gen6.wm_state + state); |
} |
static void |
gen6_emit_sf(struct sna *sna, Bool has_mask) |
{ |
int num_sf_outputs = has_mask ? 2 : 1; |
if (sna->render_state.gen6.num_sf_outputs == num_sf_outputs) |
return; |
DBG(("%s: num_sf_outputs=%d, read_length=%d, read_offset=%d\n", |
__FUNCTION__, num_sf_outputs, 1, 0)); |
sna->render_state.gen6.num_sf_outputs = num_sf_outputs; |
OUT_BATCH(GEN6_3DSTATE_SF | (20 - 2)); |
OUT_BATCH(num_sf_outputs << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT | |
1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT | |
1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT); |
OUT_BATCH(0); |
OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE); |
OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); /* DW4 */ |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); /* DW9 */ |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); /* DW14 */ |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); /* DW19 */ |
} |
static void |
gen6_emit_wm(struct sna *sna, unsigned int kernel, int nr_surfaces, int nr_inputs) |
{ |
if (sna->render_state.gen6.kernel == kernel) |
return; |
sna->render_state.gen6.kernel = kernel; |
DBG(("%s: switching to %s\n", __FUNCTION__, wm_kernels[kernel].name)); |
OUT_BATCH(GEN6_3DSTATE_WM | (9 - 2)); |
OUT_BATCH(sna->render_state.gen6.wm_kernel[kernel]); |
OUT_BATCH(1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHIFT | |
nr_surfaces << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT); |
OUT_BATCH(0); |
OUT_BATCH(6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT); /* DW4 */ |
OUT_BATCH((40 - 1) << GEN6_3DSTATE_WM_MAX_THREADS_SHIFT | |
GEN6_3DSTATE_WM_DISPATCH_ENABLE | |
GEN6_3DSTATE_WM_16_DISPATCH_ENABLE); |
OUT_BATCH(nr_inputs << GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIFT | |
GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC); |
OUT_BATCH(0); |
OUT_BATCH(0); |
} |
static bool |
gen6_emit_binding_table(struct sna *sna, uint16_t offset) |
{ |
if (sna->render_state.gen6.surface_table == offset) |
return false; |
/* Binding table pointers */ |
OUT_BATCH(GEN6_3DSTATE_BINDING_TABLE_POINTERS | |
GEN6_3DSTATE_BINDING_TABLE_MODIFY_PS | |
(4 - 2)); |
OUT_BATCH(0); /* vs */ |
OUT_BATCH(0); /* gs */ |
/* Only the PS uses the binding table */ |
OUT_BATCH(offset*4); |
sna->render_state.gen6.surface_table = offset; |
return true; |
} |
static bool |
gen6_emit_drawing_rectangle(struct sna *sna, |
const struct sna_composite_op *op) |
{ |
uint32_t limit = (op->dst.height - 1) << 16 | (op->dst.width - 1); |
uint32_t offset = (uint16_t)op->dst.y << 16 | (uint16_t)op->dst.x; |
assert(!too_large(op->dst.x, op->dst.y)); |
assert(!too_large(op->dst.width, op->dst.height)); |
if (sna->render_state.gen6.drawrect_limit == limit && |
sna->render_state.gen6.drawrect_offset == offset) |
return false; |
/* [DevSNB-C+{W/A}] Before any depth stall flush (including those |
* produced by non-pipelined state commands), software needs to first |
* send a PIPE_CONTROL with no bits set except Post-Sync Operation != |
* 0. |
* |
* [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent |
* BEFORE the pipe-control with a post-sync op and no write-cache |
* flushes. |
*/ |
OUT_BATCH(GEN6_PIPE_CONTROL | (4 - 2)); |
OUT_BATCH(GEN6_PIPE_CONTROL_CS_STALL | |
GEN6_PIPE_CONTROL_STALL_AT_SCOREBOARD); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(GEN6_PIPE_CONTROL | (4 - 2)); |
OUT_BATCH(GEN6_PIPE_CONTROL_WRITE_TIME); |
// OUT_BATCH(kgem_add_reloc(&sna->kgem, sna->kgem.nbatch, |
// sna->render_state.gen6.general_bo, |
// I915_GEM_DOMAIN_INSTRUCTION << 16 | |
// I915_GEM_DOMAIN_INSTRUCTION, |
// 64)); |
OUT_BATCH(sna->render_state.gen6.general_bo->gaddr+64); |
OUT_BATCH(0); |
OUT_BATCH(GEN6_3DSTATE_DRAWING_RECTANGLE | (4 - 2)); |
OUT_BATCH(0); |
OUT_BATCH(limit); |
OUT_BATCH(offset); |
sna->render_state.gen6.drawrect_offset = offset; |
sna->render_state.gen6.drawrect_limit = limit; |
return true; |
} |
static void |
gen6_emit_vertex_elements(struct sna *sna, |
const struct sna_composite_op *op) |
{ |
/* |
* vertex data in vertex buffer |
* position: (x, y) |
* texture coordinate 0: (u0, v0) if (is_affine is TRUE) else (u0, v0, w0) |
* texture coordinate 1 if (has_mask is TRUE): same as above |
*/ |
struct gen6_render_state *render = &sna->render_state.gen6; |
int nelem = op->mask.bo ? 2 : 1; |
int selem = op->is_affine ? 2 : 3; |
uint32_t w_component; |
uint32_t src_format; |
int id = op->u.gen6.ve_id; |
if (render->ve_id == id) |
return; |
render->ve_id = id; |
if (op->is_affine) { |
src_format = GEN6_SURFACEFORMAT_R32G32_FLOAT; |
w_component = GEN6_VFCOMPONENT_STORE_1_FLT; |
} else { |
src_format = GEN6_SURFACEFORMAT_R32G32B32_FLOAT; |
w_component = GEN6_VFCOMPONENT_STORE_SRC; |
} |
/* The VUE layout |
* dword 0-3: pad (0.0, 0.0, 0.0. 0.0) |
* dword 4-7: position (x, y, 1.0, 1.0), |
* dword 8-11: texture coordinate 0 (u0, v0, w0, 1.0) |
* dword 12-15: texture coordinate 1 (u1, v1, w1, 1.0) |
* |
* dword 4-15 are fetched from vertex buffer |
*/ |
OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS | |
((2 * (2 + nelem)) + 1 - 2)); |
OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | |
GEN6_SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT | |
0 << VE0_OFFSET_SHIFT); |
OUT_BATCH(GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT | |
GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT | |
GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | |
GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT); |
/* x,y */ |
OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | |
GEN6_SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT | |
0 << VE0_OFFSET_SHIFT); /* offsets vb in bytes */ |
OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | |
GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | |
GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT | |
GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); |
/* u0, v0, w0 */ |
OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | |
src_format << VE0_FORMAT_SHIFT | |
4 << VE0_OFFSET_SHIFT); /* offset vb in bytes */ |
OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | |
GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | |
w_component << VE1_VFCOMPONENT_2_SHIFT | |
GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); |
/* u1, v1, w1 */ |
if (op->mask.bo) { |
OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | |
src_format << VE0_FORMAT_SHIFT | |
((1 + selem) * 4) << VE0_OFFSET_SHIFT); /* vb offset in bytes */ |
OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | |
GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | |
w_component << VE1_VFCOMPONENT_2_SHIFT | |
GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); |
} |
} |
static void |
gen6_emit_flush(struct sna *sna) |
{ |
OUT_BATCH(GEN6_PIPE_CONTROL | (4 - 2)); |
OUT_BATCH(GEN6_PIPE_CONTROL_WC_FLUSH | |
GEN6_PIPE_CONTROL_TC_FLUSH | |
GEN6_PIPE_CONTROL_CS_STALL); |
OUT_BATCH(0); |
OUT_BATCH(0); |
} |
static void |
gen6_emit_state(struct sna *sna, |
const struct sna_composite_op *op, |
uint16_t wm_binding_table) |
{ |
bool need_stall = wm_binding_table & 1; |
if (gen6_emit_cc(sna, op->op, op->has_component_alpha, op->dst.format)) |
need_stall = false; |
gen6_emit_sampler(sna, |
SAMPLER_OFFSET(op->src.filter, |
op->src.repeat, |
op->mask.filter, |
op->mask.repeat)); |
gen6_emit_sf(sna, op->mask.bo != NULL); |
gen6_emit_wm(sna, |
op->u.gen6.wm_kernel, |
op->u.gen6.nr_surfaces, |
op->u.gen6.nr_inputs); |
gen6_emit_vertex_elements(sna, op); |
need_stall |= gen6_emit_binding_table(sna, wm_binding_table & ~1); |
if (gen6_emit_drawing_rectangle(sna, op)) |
need_stall = false; |
// if (kgem_bo_is_dirty(op->src.bo) || kgem_bo_is_dirty(op->mask.bo)) { |
gen6_emit_flush(sna); |
kgem_clear_dirty(&sna->kgem); |
kgem_bo_mark_dirty(op->dst.bo); |
need_stall = false; |
// } |
if (need_stall) { |
OUT_BATCH(GEN6_PIPE_CONTROL | (4 - 2)); |
OUT_BATCH(GEN6_PIPE_CONTROL_CS_STALL | |
GEN6_PIPE_CONTROL_STALL_AT_SCOREBOARD); |
OUT_BATCH(0); |
OUT_BATCH(0); |
} |
} |
static void gen6_magic_ca_pass(struct sna *sna, |
const struct sna_composite_op *op) |
{ |
struct gen6_render_state *state = &sna->render_state.gen6; |
if (!op->need_magic_ca_pass) |
return; |
DBG(("%s: CA fixup (%d -> %d)\n", __FUNCTION__, |
sna->render.vertex_start, sna->render.vertex_index)); |
gen6_emit_flush(sna); |
gen6_emit_cc(sna, PictOpAdd, TRUE, op->dst.format); |
gen6_emit_wm(sna, |
gen6_choose_composite_kernel(PictOpAdd, |
TRUE, TRUE, |
op->is_affine), |
3, 2); |
OUT_BATCH(GEN6_3DPRIMITIVE | |
GEN6_3DPRIMITIVE_VERTEX_SEQUENTIAL | |
_3DPRIM_RECTLIST << GEN6_3DPRIMITIVE_TOPOLOGY_SHIFT | |
0 << 9 | |
4); |
OUT_BATCH(sna->render.vertex_index - sna->render.vertex_start); |
OUT_BATCH(sna->render.vertex_start); |
OUT_BATCH(1); /* single instance */ |
OUT_BATCH(0); /* start instance location */ |
OUT_BATCH(0); /* index buffer offset, ignored */ |
state->last_primitive = sna->kgem.nbatch; |
} |
static void gen6_vertex_flush(struct sna *sna) |
{ |
assert(sna->render_state.gen6.vertex_offset); |
DBG(("%s[%x] = %d\n", __FUNCTION__, |
4*sna->render_state.gen6.vertex_offset, |
sna->render.vertex_index - sna->render.vertex_start)); |
sna->kgem.batch[sna->render_state.gen6.vertex_offset] = |
sna->render.vertex_index - sna->render.vertex_start; |
sna->render_state.gen6.vertex_offset = 0; |
} |
static int gen6_vertex_finish(struct sna *sna) |
{ |
struct kgem_bo *bo; |
unsigned int i; |
DBG(("%s: used=%d / %d\n", __FUNCTION__, |
sna->render.vertex_used, sna->render.vertex_size)); |
assert(sna->render.vertex_used); |
/* Note: we only need dword alignment (currently) */ |
/* |
bo = sna->render.vbo; |
if (bo) { |
for (i = 0; i < ARRAY_SIZE(sna->render.vertex_reloc); i++) { |
if (sna->render.vertex_reloc[i]) { |
DBG(("%s: reloc[%d] = %d\n", __FUNCTION__, |
i, sna->render.vertex_reloc[i])); |
sna->kgem.batch[sna->render.vertex_reloc[i]] = |
kgem_add_reloc(&sna->kgem, |
sna->render.vertex_reloc[i], |
bo, |
I915_GEM_DOMAIN_VERTEX << 16, |
0); |
sna->kgem.batch[sna->render.vertex_reloc[i]+1] = |
kgem_add_reloc(&sna->kgem, |
sna->render.vertex_reloc[i]+1, |
bo, |
I915_GEM_DOMAIN_VERTEX << 16, |
0 + sna->render.vertex_used * 4 - 1); |
sna->render.vertex_reloc[i] = 0; |
} |
} |
sna->render.vertex_used = 0; |
sna->render.vertex_index = 0; |
sna->render_state.gen6.vb_id = 0; |
kgem_bo_destroy(&sna->kgem, bo); |
} |
*/ |
sna->render.vertices = NULL; |
sna->render.vbo = kgem_create_linear(&sna->kgem, 256*1024); |
if (sna->render.vbo) |
sna->render.vertices = kgem_bo_map__cpu(&sna->kgem, sna->render.vbo); |
if (sna->render.vertices == NULL) { |
kgem_bo_destroy(&sna->kgem, sna->render.vbo); |
sna->render.vbo = NULL; |
return 0; |
} |
// kgem_bo_sync__cpu(&sna->kgem, sna->render.vbo); |
if (sna->render.vertex_used) { |
DBG(("%s: copying initial buffer x %d to handle=%d\n", |
__FUNCTION__, |
sna->render.vertex_used, |
sna->render.vbo->handle)); |
memcpy(sna->render.vertices, |
sna->render.vertex_data, |
sizeof(float)*sna->render.vertex_used); |
} |
sna->render.vertex_size = 64 * 1024 - 1; |
return sna->render.vertex_size - sna->render.vertex_used; |
} |
static void gen6_vertex_close(struct sna *sna) |
{ |
struct kgem_bo *bo; |
unsigned int i, delta = 0; |
if (!sna->render.vertex_used) { |
assert(sna->render.vbo == NULL); |
assert(sna->render.vertices == sna->render.vertex_data); |
assert(sna->render.vertex_size == ARRAY_SIZE(sna->render.vertex_data)); |
return; |
} |
DBG(("%s: used=%d / %d\n", __FUNCTION__, |
sna->render.vertex_used, sna->render.vertex_size)); |
bo = sna->render.vbo; |
if (bo == NULL) { |
assert(sna->render.vertices == sna->render.vertex_data); |
assert(sna->render.vertex_used < ARRAY_SIZE(sna->render.vertex_data)); |
if (sna->kgem.nbatch + sna->render.vertex_used <= sna->kgem.surface) { |
DBG(("%s: copy to batch: %d @ %d\n", __FUNCTION__, |
sna->render.vertex_used, sna->kgem.nbatch)); |
memcpy(sna->kgem.batch + sna->kgem.nbatch, |
sna->render.vertex_data, |
sna->render.vertex_used * 4); |
delta = sna->kgem.nbatch * 4; |
bo = NULL; |
sna->kgem.nbatch += sna->render.vertex_used; |
} else { |
bo = kgem_create_linear(&sna->kgem, 4*sna->render.vertex_used); |
if (bo && !kgem_bo_write(&sna->kgem, bo, |
sna->render.vertex_data, |
4*sna->render.vertex_used)) { |
kgem_bo_destroy(&sna->kgem, bo); |
goto reset; |
} |
DBG(("%s: new vbo: %d\n", __FUNCTION__, |
sna->render.vertex_used)); |
} |
} |
for (i = 0; i < ARRAY_SIZE(sna->render.vertex_reloc); i++) { |
if (sna->render.vertex_reloc[i]) { |
DBG(("%s: reloc[%d] = %d\n", __FUNCTION__, |
i, sna->render.vertex_reloc[i])); |
// sna->kgem.batch[sna->render.vertex_reloc[i]] = |
// kgem_add_reloc(&sna->kgem, |
// sna->render.vertex_reloc[i], |
// bo, |
// I915_GEM_DOMAIN_VERTEX << 16, |
// delta); |
sna->kgem.batch[sna->render.vertex_reloc[i]] = |
sna->kgem.batch_obj->gtt_offset+delta+ |
sna->kgem.batch_idx*4096; |
// sna->kgem.batch[sna->render.vertex_reloc[i]+1] = |
// kgem_add_reloc(&sna->kgem, |
// sna->render.vertex_reloc[i]+1, |
// bo, |
// I915_GEM_DOMAIN_VERTEX << 16, |
// delta + sna->render.vertex_used * 4 - 1); |
sna->kgem.batch[sna->render.vertex_reloc[i]+1] = |
sna->kgem.batch_obj->gtt_offset+delta+ |
sna->kgem.batch_idx*4096+ |
sna->render.vertex_used * 4 - 1; |
sna->render.vertex_reloc[i] = 0; |
} |
} |
// if (bo) |
// kgem_bo_destroy(&sna->kgem, bo); |
reset: |
sna->render.vertex_used = 0; |
sna->render.vertex_index = 0; |
sna->render_state.gen6.vb_id = 0; |
sna->render.vbo = NULL; |
sna->render.vertices = sna->render.vertex_data; |
sna->render.vertex_size = ARRAY_SIZE(sna->render.vertex_data); |
} |
typedef struct gen6_surface_state_padded { |
struct gen6_surface_state state; |
char pad[32 - sizeof(struct gen6_surface_state)]; |
} gen6_surface_state_padded; |
static void null_create(struct sna_static_stream *stream) |
{ |
/* A bunch of zeros useful for legacy border color and depth-stencil */ |
sna_static_stream_map(stream, 64, 64); |
} |
static void scratch_create(struct sna_static_stream *stream) |
{ |
/* 64 bytes of scratch space for random writes, such as |
* the pipe-control w/a. |
*/ |
sna_static_stream_map(stream, 64, 64); |
} |
static void |
sampler_state_init(struct gen6_sampler_state *sampler_state, |
sampler_filter_t filter, |
sampler_extend_t extend) |
{ |
sampler_state->ss0.lod_preclamp = 1; /* GL mode */ |
/* We use the legacy mode to get the semantics specified by |
* the Render extension. */ |
sampler_state->ss0.border_color_mode = GEN6_BORDER_COLOR_MODE_LEGACY; |
switch (filter) { |
default: |
case SAMPLER_FILTER_NEAREST: |
sampler_state->ss0.min_filter = GEN6_MAPFILTER_NEAREST; |
sampler_state->ss0.mag_filter = GEN6_MAPFILTER_NEAREST; |
break; |
case SAMPLER_FILTER_BILINEAR: |
sampler_state->ss0.min_filter = GEN6_MAPFILTER_LINEAR; |
sampler_state->ss0.mag_filter = GEN6_MAPFILTER_LINEAR; |
break; |
} |
switch (extend) { |
default: |
case SAMPLER_EXTEND_NONE: |
sampler_state->ss1.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP_BORDER; |
sampler_state->ss1.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP_BORDER; |
sampler_state->ss1.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP_BORDER; |
break; |
case SAMPLER_EXTEND_REPEAT: |
sampler_state->ss1.r_wrap_mode = GEN6_TEXCOORDMODE_WRAP; |
sampler_state->ss1.s_wrap_mode = GEN6_TEXCOORDMODE_WRAP; |
sampler_state->ss1.t_wrap_mode = GEN6_TEXCOORDMODE_WRAP; |
break; |
case SAMPLER_EXTEND_PAD: |
sampler_state->ss1.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP; |
sampler_state->ss1.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP; |
sampler_state->ss1.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP; |
break; |
case SAMPLER_EXTEND_REFLECT: |
sampler_state->ss1.r_wrap_mode = GEN6_TEXCOORDMODE_MIRROR; |
sampler_state->ss1.s_wrap_mode = GEN6_TEXCOORDMODE_MIRROR; |
sampler_state->ss1.t_wrap_mode = GEN6_TEXCOORDMODE_MIRROR; |
break; |
} |
} |
static uint32_t gen6_create_cc_viewport(struct sna_static_stream *stream) |
{ |
struct gen6_cc_viewport vp; |
vp.min_depth = -1.e35; |
vp.max_depth = 1.e35; |
return sna_static_stream_add(stream, &vp, sizeof(vp), 32); |
} |
#if 0 |
static uint32_t gen6_get_card_format(PictFormat format) |
{ |
unsigned int i; |
for (i = 0; i < ARRAY_SIZE(gen6_tex_formats); i++) { |
if (gen6_tex_formats[i].pict_fmt == format) |
return gen6_tex_formats[i].card_fmt; |
} |
return -1; |
} |
#endif |
static uint32_t |
gen6_tiling_bits(uint32_t tiling) |
{ |
return 0; |
/* |
switch (tiling) { |
default: assert(0); |
case I915_TILING_NONE: return 0; |
case I915_TILING_X: return GEN6_SURFACE_TILED; |
case I915_TILING_Y: return GEN6_SURFACE_TILED | GEN6_SURFACE_TILED_Y; |
} |
*/ |
} |
/** |
* Sets up the common fields for a surface state buffer for the given |
* picture in the given surface state buffer. |
*/ |
static int |
gen6_bind_bo(struct sna *sna, |
struct kgem_bo *bo, |
uint32_t width, |
uint32_t height, |
uint32_t format, |
Bool is_dst) |
{ |
uint32_t *ss; |
uint32_t domains; |
uint16_t offset; |
/* After the first bind, we manage the cache domains within the batch */ |
if (is_dst) { |
domains = I915_GEM_DOMAIN_RENDER << 16 |I915_GEM_DOMAIN_RENDER; |
// kgem_bo_mark_dirty(bo); |
} else |
domains = I915_GEM_DOMAIN_SAMPLER << 16; |
// offset = kgem_bo_get_binding(bo, format); |
// if (offset) { |
// DBG(("[%x] bo(handle=%x), format=%d, reuse %s binding\n", |
// offset, bo->handle, format, |
// domains & 0xffff ? "render" : "sampler")); |
// return offset; |
// } |
offset = sna->kgem.surface - sizeof(struct gen6_surface_state_padded) / sizeof(uint32_t); |
offset *= sizeof(uint32_t); |
sna->kgem.surface -= |
sizeof(struct gen6_surface_state_padded) / sizeof(uint32_t); |
ss = sna->kgem.batch + sna->kgem.surface; |
ss[0] = (GEN6_SURFACE_2D << GEN6_SURFACE_TYPE_SHIFT | |
GEN6_SURFACE_BLEND_ENABLED | |
format << GEN6_SURFACE_FORMAT_SHIFT); |
ss[1] = bo->gaddr; |
ss[2] = ((width - 1) << GEN6_SURFACE_WIDTH_SHIFT | |
(height - 1) << GEN6_SURFACE_HEIGHT_SHIFT); |
assert(bo->pitch <= (1 << 18)); |
ss[3] = (gen6_tiling_bits(0) | |
(bo->pitch - 1) << GEN6_SURFACE_PITCH_SHIFT); |
ss[4] = 0; |
ss[5] = 0; |
// kgem_bo_set_binding(bo, format, offset); |
DBG(("[%x] bind bo(handle=%d, addr=%d), format=%d, width=%d, height=%d, pitch=%d, tiling=%d -> %s\n", |
offset, bo->handle, ss[1], |
format, width, height, bo->pitch, bo->tiling, |
domains & 0xffff ? "render" : "sampler")); |
return offset; |
} |
static void gen6_emit_vertex_buffer(struct sna *sna, |
const struct sna_composite_op *op) |
{ |
int id = op->u.gen6.ve_id; |
OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | 3); |
OUT_BATCH(id << VB0_BUFFER_INDEX_SHIFT | VB0_VERTEXDATA | |
4*op->floats_per_vertex << VB0_BUFFER_PITCH_SHIFT); |
sna->render.vertex_reloc[id] = sna->kgem.nbatch; |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
sna->render_state.gen6.vb_id |= 1 << id; |
} |
static void gen6_emit_primitive(struct sna *sna) |
{ |
if (sna->kgem.nbatch == sna->render_state.gen6.last_primitive) { |
DBG(("%s: continuing previous primitive, start=%d, index=%d\n", |
__FUNCTION__, |
sna->render.vertex_start, |
sna->render.vertex_index)); |
sna->render_state.gen6.vertex_offset = sna->kgem.nbatch - 5; |
return; |
} |
OUT_BATCH(GEN6_3DPRIMITIVE | |
GEN6_3DPRIMITIVE_VERTEX_SEQUENTIAL | |
_3DPRIM_RECTLIST << GEN6_3DPRIMITIVE_TOPOLOGY_SHIFT | |
0 << 9 | |
4); |
sna->render_state.gen6.vertex_offset = sna->kgem.nbatch; |
OUT_BATCH(0); /* vertex count, to be filled in later */ |
OUT_BATCH(sna->render.vertex_index); |
OUT_BATCH(1); /* single instance */ |
OUT_BATCH(0); /* start instance location */ |
OUT_BATCH(0); /* index buffer offset, ignored */ |
sna->render.vertex_start = sna->render.vertex_index; |
DBG(("%s: started new primitive: index=%d\n", |
__FUNCTION__, sna->render.vertex_start)); |
sna->render_state.gen6.last_primitive = sna->kgem.nbatch; |
} |
static bool gen6_rectangle_begin(struct sna *sna, |
const struct sna_composite_op *op) |
{ |
int id = 1 << op->u.gen6.ve_id; |
int ndwords; |
ndwords = op->need_magic_ca_pass ? 60 : 6; |
if ((sna->render_state.gen6.vb_id & id) == 0) |
ndwords += 5; |
if (!kgem_check_batch(&sna->kgem, ndwords)) |
return false; |
if ((sna->render_state.gen6.vb_id & id) == 0) |
gen6_emit_vertex_buffer(sna, op); |
gen6_emit_primitive(sna); |
return true; |
} |
static int gen6_get_rectangles__flush(struct sna *sna, |
const struct sna_composite_op *op) |
{ |
if (sna->render_state.gen6.vertex_offset) { |
gen6_vertex_flush(sna); |
gen6_magic_ca_pass(sna, op); |
} |
if (!kgem_check_batch(&sna->kgem, op->need_magic_ca_pass ? 65 : 5)) |
return 0; |
if (sna->kgem.nexec > KGEM_EXEC_SIZE(&sna->kgem) - 1) |
return 0; |
if (sna->kgem.nreloc > KGEM_RELOC_SIZE(&sna->kgem) - 2) |
return 0; |
return gen6_vertex_finish(sna); |
} |
inline static int gen6_get_rectangles(struct sna *sna, |
const struct sna_composite_op *op, |
int want) |
{ |
int rem = vertex_space(sna); |
if (rem < op->floats_per_rect) { |
DBG(("flushing vbo for %s: %d < %d\n", |
__FUNCTION__, rem, op->floats_per_rect)); |
rem = gen6_get_rectangles__flush(sna, op); |
if (rem == 0) |
return 0; |
} |
if (sna->render_state.gen6.vertex_offset == 0 && |
!gen6_rectangle_begin(sna, op)) |
return 0; |
if (want > 1 && want * op->floats_per_rect > rem) |
want = rem / op->floats_per_rect; |
assert(want > 0); |
sna->render.vertex_index += 3*want; |
return want; |
} |
inline static uint32_t *gen6_composite_get_binding_table(struct sna *sna, |
uint16_t *offset) |
{ |
uint32_t *table; |
sna->kgem.surface -= |
sizeof(struct gen6_surface_state_padded) / sizeof(uint32_t); |
/* Clear all surplus entries to zero in case of prefetch */ |
table = memset(sna->kgem.batch + sna->kgem.surface, |
0, sizeof(struct gen6_surface_state_padded)); |
DBG(("%s(%x)\n", __FUNCTION__, 4*sna->kgem.surface)); |
*offset = sna->kgem.surface; |
return table; |
} |
static uint32_t |
gen6_choose_composite_vertex_buffer(const struct sna_composite_op *op) |
{ |
int has_mask = op->mask.bo != NULL; |
int is_affine = op->is_affine; |
return has_mask << 1 | is_affine; |
} |
static void |
gen6_get_batch(struct sna *sna) |
{ |
kgem_set_mode(&sna->kgem, KGEM_RENDER); |
/* |
if (!kgem_check_batch_with_surfaces(&sna->kgem, 150, 4)) { |
DBG(("%s: flushing batch: %d < %d+%d\n", |
__FUNCTION__, sna->kgem.surface - sna->kgem.nbatch, |
150, 4*8)); |
kgem_submit(&sna->kgem); |
_kgem_set_mode(&sna->kgem, KGEM_RENDER); |
} |
*/ |
if (sna->render_state.gen6.needs_invariant) |
gen6_emit_invariant(sna); |
} |
static void |
gen6_align_vertex(struct sna *sna, const struct sna_composite_op *op) |
{ |
assert (sna->render_state.gen6.vertex_offset == 0); |
if (op->floats_per_vertex != sna->render_state.gen6.floats_per_vertex) { |
if (sna->render.vertex_size - sna->render.vertex_used < 2*op->floats_per_rect) |
/* XXX propagate failure */ |
gen6_vertex_finish(sna); |
DBG(("aligning vertex: was %d, now %d floats per vertex, %d->%d\n", |
sna->render_state.gen6.floats_per_vertex, |
op->floats_per_vertex, |
sna->render.vertex_index, |
(sna->render.vertex_used + op->floats_per_vertex - 1) / op->floats_per_vertex)); |
sna->render.vertex_index = (sna->render.vertex_used + op->floats_per_vertex - 1) / op->floats_per_vertex; |
sna->render.vertex_used = sna->render.vertex_index * op->floats_per_vertex; |
sna->render_state.gen6.floats_per_vertex = op->floats_per_vertex; |
} |
} |
#ifndef MAX |
#define MAX(a,b) ((a) > (b) ? (a) : (b)) |
#endif |
static uint32_t |
gen6_composite_create_blend_state(struct sna_static_stream *stream) |
{ |
char *base, *ptr; |
int src, dst; |
base = sna_static_stream_map(stream, |
GEN6_BLENDFACTOR_COUNT * GEN6_BLENDFACTOR_COUNT * GEN6_BLEND_STATE_PADDED_SIZE, |
64); |
ptr = base; |
for (src = 0; src < GEN6_BLENDFACTOR_COUNT; src++) { |
for (dst= 0; dst < GEN6_BLENDFACTOR_COUNT; dst++) { |
struct gen6_blend_state *blend = |
(struct gen6_blend_state *)ptr; |
blend->blend0.dest_blend_factor = dst; |
blend->blend0.source_blend_factor = src; |
blend->blend0.blend_func = GEN6_BLENDFUNCTION_ADD; |
blend->blend0.blend_enable = |
!(dst == GEN6_BLENDFACTOR_ZERO && src == GEN6_BLENDFACTOR_ONE); |
blend->blend1.post_blend_clamp_enable = 1; |
blend->blend1.pre_blend_clamp_enable = 1; |
ptr += GEN6_BLEND_STATE_PADDED_SIZE; |
} |
} |
return sna_static_stream_offsetof(stream, base); |
} |
#if 0 |
static uint32_t gen6_bind_video_source(struct sna *sna, |
struct kgem_bo *src_bo, |
uint32_t src_offset, |
int src_width, |
int src_height, |
int src_pitch, |
uint32_t src_surf_format) |
{ |
struct gen6_surface_state *ss; |
sna->kgem.surface -= sizeof(struct gen6_surface_state_padded) / sizeof(uint32_t); |
ss = memset(sna->kgem.batch + sna->kgem.surface, 0, sizeof(*ss)); |
ss->ss0.surface_type = GEN6_SURFACE_2D; |
ss->ss0.surface_format = src_surf_format; |
ss->ss1.base_addr = |
kgem_add_reloc(&sna->kgem, |
sna->kgem.surface + 1, |
src_bo, |
I915_GEM_DOMAIN_SAMPLER << 16, |
src_offset); |
ss->ss2.width = src_width - 1; |
ss->ss2.height = src_height - 1; |
ss->ss3.pitch = src_pitch - 1; |
return sna->kgem.surface * sizeof(uint32_t); |
} |
static void gen6_emit_video_state(struct sna *sna, |
struct sna_composite_op *op, |
struct sna_video_frame *frame) |
{ |
uint32_t src_surf_format; |
uint32_t src_surf_base[6]; |
int src_width[6]; |
int src_height[6]; |
int src_pitch[6]; |
uint32_t *binding_table; |
uint16_t offset; |
bool dirty; |
int n_src, n; |
gen6_get_batch(sna); |
dirty = kgem_bo_is_dirty(op->dst.bo); |
src_surf_base[0] = 0; |
src_surf_base[1] = 0; |
src_surf_base[2] = frame->VBufOffset; |
src_surf_base[3] = frame->VBufOffset; |
src_surf_base[4] = frame->UBufOffset; |
src_surf_base[5] = frame->UBufOffset; |
if (is_planar_fourcc(frame->id)) { |
src_surf_format = GEN6_SURFACEFORMAT_R8_UNORM; |
src_width[1] = src_width[0] = frame->width; |
src_height[1] = src_height[0] = frame->height; |
src_pitch[1] = src_pitch[0] = frame->pitch[1]; |
src_width[4] = src_width[5] = src_width[2] = src_width[3] = |
frame->width / 2; |
src_height[4] = src_height[5] = src_height[2] = src_height[3] = |
frame->height / 2; |
src_pitch[4] = src_pitch[5] = src_pitch[2] = src_pitch[3] = |
frame->pitch[0]; |
n_src = 6; |
} else { |
if (frame->id == FOURCC_UYVY) |
src_surf_format = GEN6_SURFACEFORMAT_YCRCB_SWAPY; |
else |
src_surf_format = GEN6_SURFACEFORMAT_YCRCB_NORMAL; |
src_width[0] = frame->width; |
src_height[0] = frame->height; |
src_pitch[0] = frame->pitch[0]; |
n_src = 1; |
} |
binding_table = gen6_composite_get_binding_table(sna, &offset); |
binding_table[0] = |
gen6_bind_bo(sna, |
op->dst.bo, op->dst.width, op->dst.height, |
gen6_get_dest_format(op->dst.format), |
TRUE); |
for (n = 0; n < n_src; n++) { |
binding_table[1+n] = |
gen6_bind_video_source(sna, |
frame->bo, |
src_surf_base[n], |
src_width[n], |
src_height[n], |
src_pitch[n], |
src_surf_format); |
} |
gen6_emit_state(sna, op, offset | dirty); |
} |
static Bool |
gen6_render_video(struct sna *sna, |
struct sna_video *video, |
struct sna_video_frame *frame, |
RegionPtr dstRegion, |
short src_w, short src_h, |
short drw_w, short drw_h, |
PixmapPtr pixmap) |
{ |
struct sna_composite_op tmp; |
int nbox, dxo, dyo, pix_xoff, pix_yoff; |
float src_scale_x, src_scale_y; |
struct sna_pixmap *priv; |
BoxPtr box; |
DBG(("%s: src=(%d, %d), dst=(%d, %d), %dx[(%d, %d), (%d, %d)...]\n", |
__FUNCTION__, src_w, src_h, drw_w, drw_h, |
REGION_NUM_RECTS(dstRegion), |
REGION_EXTENTS(NULL, dstRegion)->x1, |
REGION_EXTENTS(NULL, dstRegion)->y1, |
REGION_EXTENTS(NULL, dstRegion)->x2, |
REGION_EXTENTS(NULL, dstRegion)->y2)); |
priv = sna_pixmap_force_to_gpu(pixmap, MOVE_READ | MOVE_WRITE); |
if (priv == NULL) |
return FALSE; |
memset(&tmp, 0, sizeof(tmp)); |
tmp.op = PictOpSrc; |
tmp.dst.pixmap = pixmap; |
tmp.dst.width = pixmap->drawable.width; |
tmp.dst.height = pixmap->drawable.height; |
tmp.dst.format = sna_render_format_for_depth(pixmap->drawable.depth); |
tmp.dst.bo = priv->gpu_bo; |
tmp.src.bo = frame->bo; |
tmp.src.filter = SAMPLER_FILTER_BILINEAR; |
tmp.src.repeat = SAMPLER_EXTEND_PAD; |
tmp.mask.bo = NULL; |
tmp.is_affine = TRUE; |
tmp.floats_per_vertex = 3; |
tmp.floats_per_rect = 9; |
if (is_planar_fourcc(frame->id)) { |
tmp.u.gen6.wm_kernel = GEN6_WM_KERNEL_VIDEO_PLANAR; |
tmp.u.gen6.nr_surfaces = 7; |
} else { |
tmp.u.gen6.wm_kernel = GEN6_WM_KERNEL_VIDEO_PACKED; |
tmp.u.gen6.nr_surfaces = 2; |
} |
tmp.u.gen6.nr_inputs = 1; |
tmp.u.gen6.ve_id = 1; |
kgem_set_mode(&sna->kgem, KGEM_RENDER); |
if (!kgem_check_bo(&sna->kgem, tmp.dst.bo, frame->bo, NULL)) { |
kgem_submit(&sna->kgem); |
assert(kgem_check_bo(&sna->kgem, tmp.dst.bo, frame->bo, NULL)); |
_kgem_set_mode(&sna->kgem, KGEM_RENDER); |
} |
gen6_emit_video_state(sna, &tmp, frame); |
gen6_align_vertex(sna, &tmp); |
/* Set up the offset for translating from the given region (in screen |
* coordinates) to the backing pixmap. |
*/ |
#ifdef COMPOSITE |
pix_xoff = -pixmap->screen_x + pixmap->drawable.x; |
pix_yoff = -pixmap->screen_y + pixmap->drawable.y; |
#else |
pix_xoff = 0; |
pix_yoff = 0; |
#endif |
dxo = dstRegion->extents.x1; |
dyo = dstRegion->extents.y1; |
/* Use normalized texture coordinates */ |
src_scale_x = ((float)src_w / frame->width) / (float)drw_w; |
src_scale_y = ((float)src_h / frame->height) / (float)drw_h; |
box = REGION_RECTS(dstRegion); |
nbox = REGION_NUM_RECTS(dstRegion); |
while (nbox--) { |
BoxRec r; |
r.x1 = box->x1 + pix_xoff; |
r.x2 = box->x2 + pix_xoff; |
r.y1 = box->y1 + pix_yoff; |
r.y2 = box->y2 + pix_yoff; |
if (unlikely(!gen6_get_rectangles(sna, &tmp, 1))) { |
_kgem_submit(&sna->kgem); |
gen6_emit_video_state(sna, &tmp, frame); |
gen6_get_rectangles(sna, &tmp, 1); |
} |
OUT_VERTEX(r.x2, r.y2); |
OUT_VERTEX_F((box->x2 - dxo) * src_scale_x); |
OUT_VERTEX_F((box->y2 - dyo) * src_scale_y); |
OUT_VERTEX(r.x1, r.y2); |
OUT_VERTEX_F((box->x1 - dxo) * src_scale_x); |
OUT_VERTEX_F((box->y2 - dyo) * src_scale_y); |
OUT_VERTEX(r.x1, r.y1); |
OUT_VERTEX_F((box->x1 - dxo) * src_scale_x); |
OUT_VERTEX_F((box->y1 - dyo) * src_scale_y); |
if (!DAMAGE_IS_ALL(priv->gpu_damage)) { |
sna_damage_add_box(&priv->gpu_damage, &r); |
sna_damage_subtract_box(&priv->cpu_damage, &r); |
} |
box++; |
} |
priv->clear = false; |
gen6_vertex_flush(sna); |
return TRUE; |
} |
#endif |
static void gen6_render_composite_done(struct sna *sna, |
const struct sna_composite_op *op) |
{ |
DBG(("%s\n", __FUNCTION__)); |
if (sna->render_state.gen6.vertex_offset) { |
gen6_vertex_flush(sna); |
gen6_magic_ca_pass(sna, op); |
} |
// if (op->mask.bo) |
// kgem_bo_destroy(&sna->kgem, op->mask.bo); |
// if (op->src.bo) |
// kgem_bo_destroy(&sna->kgem, op->src.bo); |
// sna_render_composite_redirect_done(sna, op); |
} |
static void |
gen6_emit_copy_state(struct sna *sna, |
const struct sna_composite_op *op) |
{ |
uint32_t *binding_table; |
uint16_t offset; |
bool dirty; |
gen6_get_batch(sna); |
// dirty = kgem_bo_is_dirty(op->dst.bo); |
binding_table = gen6_composite_get_binding_table(sna, &offset); |
binding_table[0] = |
gen6_bind_bo(sna, |
op->dst.bo, op->dst.width, op->dst.height, |
GEN6_SURFACEFORMAT_B8G8R8A8_UNORM, |
TRUE); |
binding_table[1] = |
gen6_bind_bo(sna, |
op->src.bo, op->src.width, op->src.height, |
GEN6_SURFACEFORMAT_B8G8R8A8_UNORM, |
FALSE); |
if (sna->kgem.surface == offset && |
*(uint64_t *)(sna->kgem.batch + sna->render_state.gen6.surface_table) == *(uint64_t*)binding_table) { |
sna->kgem.surface += sizeof(struct gen6_surface_state_padded) / sizeof(uint32_t); |
offset = sna->render_state.gen6.surface_table; |
} |
gen6_emit_state(sna, op, offset | dirty); |
} |
static void |
gen6_render_copy_blt(struct sna *sna, |
const struct sna_composite_op *op, |
int16_t sx, int16_t sy, |
int16_t w, int16_t h, |
int16_t dx, int16_t dy) |
{ |
if (unlikely(!gen6_get_rectangles(sna, op, 1))) { |
_kgem_submit(&sna->kgem); |
gen6_emit_copy_state(sna, op); |
gen6_get_rectangles(sna, op, 1); |
} |
OUT_VERTEX(dx+w, dy+h); |
OUT_VERTEX_F((sx+w)*op->src.scale[0]); |
OUT_VERTEX_F((sy+h)*op->src.scale[1]); |
OUT_VERTEX(dx, dy+h); |
OUT_VERTEX_F(sx*op->src.scale[0]); |
OUT_VERTEX_F((sy+h)*op->src.scale[1]); |
OUT_VERTEX(dx, dy); |
OUT_VERTEX_F(sx*op->src.scale[0]); |
OUT_VERTEX_F(sy*op->src.scale[1]); |
} |
static void |
gen6_render_copy_done(struct sna *sna) |
{ |
DBG(("%s()\n", __FUNCTION__)); |
if (sna->render_state.gen6.vertex_offset) |
gen6_vertex_flush(sna); |
} |
static Bool |
gen6_render_copy(struct sna *sna, uint8_t alu, |
bitmap_t *src, struct kgem_bo *src_bo, |
bitmap_t *dst, struct kgem_bo *dst_bo, |
int dst_x, int dst_y, int src_x, int src_y, int w, int h) |
{ |
struct sna_composite_op op; |
memset(&op, 0, sizeof(op)); |
DBG(("%s (alu=%d, src=(%dx%d), dst=(%dx%d))\n", |
__FUNCTION__, alu, |
src->width, src->height, |
dst->width, dst->height)); |
// printf("%s %dx%d src=(%dx%d), dst=(%dx%d)\n", |
// __FUNCTION__,dst_x, dst_y, |
// src->width, src->height, |
// dst->width, dst->height); |
op.dst.format = 0; |
op.src.pict_format = 0; |
op.op = PictOpSrc; |
op.dst.pixmap = dst; |
op.dst.width = dst->width; |
op.dst.height = dst->height; |
op.dst.bo = dst_bo; |
op.src.bo = src_bo; |
op.src.card_format = GEN6_SURFACEFORMAT_B8G8R8X8_UNORM; |
op.src.width = src->width; |
op.src.height = src->height; |
// src_scale_x = ((float)src_w / frame->width) / (float)drw_w; |
// src_scale_y = ((float)src_h / frame->height) / (float)drw_h; |
op.src.scale[0] = 1.f/w; //src->width; |
op.src.scale[1] = 1.f/h; //src->height; |
op.src.filter = SAMPLER_FILTER_BILINEAR; |
op.src.repeat = SAMPLER_EXTEND_NONE; |
op.mask.bo = NULL; |
op.is_affine = true; |
op.floats_per_vertex = 3; |
op.floats_per_rect = 9; |
op.u.gen6.wm_kernel = GEN6_WM_KERNEL_NOMASK; |
op.u.gen6.nr_surfaces = 2; |
op.u.gen6.nr_inputs = 1; |
op.u.gen6.ve_id = 1; |
gen6_emit_copy_state(sna, &op); |
gen6_align_vertex(sna, &op); |
gen6_render_copy_blt(sna, &op, src_x, src_y, w, h, dst_x, dst_y); |
gen6_render_copy_done(sna); |
_kgem_submit(&sna->kgem); |
return TRUE; |
} |
static void |
gen6_emit_fill_state(struct sna *sna, const struct sna_composite_op *op) |
{ |
uint32_t *binding_table; |
uint16_t offset; |
bool dirty; |
gen6_get_batch(sna); |
// dirty = kgem_bo_is_dirty(op->dst.bo); |
binding_table = gen6_composite_get_binding_table(sna, &offset); |
binding_table[0] = |
gen6_bind_bo(sna, |
op->dst.bo, 1024, 768, |
GEN6_SURFACEFORMAT_B8G8R8A8_UNORM, |
TRUE); |
binding_table[1] = |
gen6_bind_bo(sna, |
op->src.bo, 1, 1, |
GEN6_SURFACEFORMAT_B8G8R8A8_UNORM, |
FALSE); |
if (sna->kgem.surface == offset && |
*(uint64_t *)(sna->kgem.batch + sna->render_state.gen6.surface_table) == *(uint64_t*)binding_table) { |
sna->kgem.surface += |
sizeof(struct gen6_surface_state_padded)/sizeof(uint32_t); |
offset = sna->render_state.gen6.surface_table; |
} |
gen6_emit_state(sna, op, offset | dirty); |
} |
static Bool |
gen6_render_clear(struct sna *sna, bitmap_t *dst, struct kgem_bo *bo) |
{ |
struct sna_composite_op tmp; |
DBG(("%s: %dx%d\n", |
__FUNCTION__, |
dst->width, |
dst->height)); |
tmp.op = PictOpSrc; |
tmp.dst.pixmap = dst; |
tmp.dst.width = dst->width; |
tmp.dst.height = dst->height; |
tmp.dst.format = 0; //PICT_a8r8g8b8; |
tmp.dst.bo = bo; |
tmp.dst.x = tmp.dst.y = 0; |
// tmp.src.bo = sna_render_get_solid(sna, 0); |
tmp.src.bo = bo; |
tmp.src.filter = SAMPLER_FILTER_NEAREST; |
tmp.src.repeat = SAMPLER_EXTEND_REPEAT; |
tmp.mask.bo = NULL; |
tmp.mask.filter = SAMPLER_FILTER_NEAREST; |
tmp.mask.repeat = SAMPLER_EXTEND_NONE; |
tmp.is_affine = TRUE; |
tmp.floats_per_vertex = 3; |
tmp.floats_per_rect = 9; |
tmp.has_component_alpha = 0; |
tmp.need_magic_ca_pass = FALSE; |
tmp.u.gen6.wm_kernel = GEN6_WM_KERNEL_NOMASK; |
tmp.u.gen6.nr_surfaces = 2; |
tmp.u.gen6.nr_inputs = 1; |
tmp.u.gen6.ve_id = 1; |
// if (!kgem_check_bo(&sna->kgem, bo, NULL)) { |
// _kgem_submit(&sna->kgem); |
// assert(kgem_check_bo(&sna->kgem, bo, NULL)); |
// } |
gen6_emit_fill_state(sna, &tmp); |
gen6_align_vertex(sna, &tmp); |
if (unlikely(!gen6_get_rectangles(sna, &tmp, 1))) { |
_kgem_submit(&sna->kgem); |
gen6_emit_fill_state(sna, &tmp); |
gen6_get_rectangles(sna, &tmp, 1); |
} |
OUT_VERTEX(dst->width, dst->height); |
OUT_VERTEX_F(1); |
OUT_VERTEX_F(1); |
OUT_VERTEX(0, dst->height); |
OUT_VERTEX_F(0); |
OUT_VERTEX_F(1); |
OUT_VERTEX(0, 0); |
OUT_VERTEX_F(0); |
OUT_VERTEX_F(0); |
gen6_vertex_flush(sna); |
// kgem_bo_destroy(&sna->kgem, tmp.src.bo); |
// gen6_render_composite_done(sna, &tmp); |
_kgem_submit(&sna->kgem); |
return TRUE; |
} |
static void gen6_render_flush(struct sna *sna) |
{ |
gen6_vertex_close(sna); |
} |
static void |
gen6_render_retire(struct kgem *kgem) |
{ |
if (kgem->ring && (kgem->has_semaphores || !kgem->need_retire)) |
kgem->ring = kgem->mode; |
} |
static void gen6_render_reset(struct sna *sna) |
{ |
sna->render_state.gen6.needs_invariant = TRUE; |
sna->render_state.gen6.vb_id = 0; |
sna->render_state.gen6.ve_id = -1; |
sna->render_state.gen6.last_primitive = -1; |
sna->render_state.gen6.num_sf_outputs = 0; |
sna->render_state.gen6.samplers = -1; |
sna->render_state.gen6.blend = -1; |
sna->render_state.gen6.kernel = -1; |
sna->render_state.gen6.drawrect_offset = -1; |
sna->render_state.gen6.drawrect_limit = -1; |
sna->render_state.gen6.surface_table = -1; |
} |
static void gen6_render_fini(struct sna *sna) |
{ |
// kgem_bo_destroy(&sna->kgem, sna->render_state.gen6.general_bo); |
} |
static Bool gen6_render_setup(struct sna *sna) |
{ |
struct gen6_render_state *state = &sna->render_state.gen6; |
struct sna_static_stream general; |
struct gen6_sampler_state *ss; |
int i, j, k, l, m; |
sna_static_stream_init(&general); |
/* Zero pad the start. If you see an offset of 0x0 in the batchbuffer |
* dumps, you know it points to zero. |
*/ |
null_create(&general); |
scratch_create(&general); |
for (m = 0; m < GEN6_KERNEL_COUNT; m++) |
state->wm_kernel[m] = |
sna_static_stream_add(&general, |
wm_kernels[m].data, |
wm_kernels[m].size, |
64); |
ss = sna_static_stream_map(&general, |
2 * sizeof(*ss) * |
FILTER_COUNT * EXTEND_COUNT * |
FILTER_COUNT * EXTEND_COUNT, |
32); |
state->wm_state = sna_static_stream_offsetof(&general, ss); |
for (i = 0; i < FILTER_COUNT; i++) { |
for (j = 0; j < EXTEND_COUNT; j++) { |
for (k = 0; k < FILTER_COUNT; k++) { |
for (l = 0; l < EXTEND_COUNT; l++) { |
sampler_state_init(ss++, i, j); |
sampler_state_init(ss++, k, l); |
} |
} |
} |
} |
state->cc_vp = gen6_create_cc_viewport(&general); |
state->cc_blend = gen6_composite_create_blend_state(&general); |
state->general_bo = sna_static_stream_fini(sna, &general); |
return state->general_bo != NULL; |
} |
Bool gen6_render_init(struct sna *sna) |
{ |
if (!gen6_render_setup(sna)) |
return FALSE; |
// sna->kgem.context_switch = gen6_render_context_switch; |
sna->kgem.retire = gen6_render_retire; |
// sna->render.composite = gen6_render_composite; |
// sna->render.video = gen6_render_video; |
// sna->render.copy_boxes = gen6_render_copy_boxes; |
sna->render.copy = gen6_render_copy; |
// sna->render.fill_boxes = gen6_render_fill_boxes; |
// sna->render.fill = gen6_render_fill; |
// sna->render.fill_one = gen6_render_fill_one; |
sna->render.clear = gen6_render_clear; |
sna->render.flush = gen6_render_flush; |
sna->render.reset = gen6_render_reset; |
// sna->render.fini = gen6_render_fini; |
sna->render.max_3d_size = GEN6_MAX_SIZE; |
sna->render.max_3d_pitch = 1 << 18; |
return TRUE; |
} |
/drivers/video/drm/i915/sna/gen6_render.h |
---|
0,0 → 1,1585 |
#ifndef GEN6_RENDER_H |
#define GEN6_RENDER_H |
#define GEN6_MASK(high, low) (((1 << ((high) - (low) + 1)) - 1) << (low)) |
#define GEN6_3D(Pipeline,Opcode,Subopcode) ((3 << 29) | \ |
((Pipeline) << 27) | \ |
((Opcode) << 24) | \ |
((Subopcode) << 16)) |
#define GEN6_STATE_BASE_ADDRESS GEN6_3D(0, 1, 1) |
#define GEN6_STATE_SIP GEN6_3D(0, 1, 2) |
#define GEN6_PIPELINE_SELECT GEN6_3D(1, 1, 4) |
#define GEN6_MEDIA_STATE_POINTERS GEN6_3D(2, 0, 0) |
#define GEN6_MEDIA_OBJECT GEN6_3D(2, 1, 0) |
#define GEN6_3DSTATE_BINDING_TABLE_POINTERS GEN6_3D(3, 0, 1) |
# define GEN6_3DSTATE_BINDING_TABLE_MODIFY_PS (1 << 12)/* for GEN6 */ |
# define GEN6_3DSTATE_BINDING_TABLE_MODIFY_GS (1 << 9) /* for GEN6 */ |
# define GEN6_3DSTATE_BINDING_TABLE_MODIFY_VS (1 << 8) /* for GEN6 */ |
#define GEN6_3DSTATE_VERTEX_BUFFERS GEN6_3D(3, 0, 8) |
#define GEN6_3DSTATE_VERTEX_ELEMENTS GEN6_3D(3, 0, 9) |
#define GEN6_3DSTATE_INDEX_BUFFER GEN6_3D(3, 0, 0xa) |
#define GEN6_3DSTATE_VF_STATISTICS GEN6_3D(3, 0, 0xb) |
#define GEN6_3DSTATE_DRAWING_RECTANGLE GEN6_3D(3, 1, 0) |
#define GEN6_3DSTATE_CONSTANT_COLOR GEN6_3D(3, 1, 1) |
#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD GEN6_3D(3, 1, 2) |
#define GEN6_3DSTATE_CHROMA_KEY GEN6_3D(3, 1, 4) |
#define GEN6_3DSTATE_DEPTH_BUFFER GEN6_3D(3, 1, 5) |
# define GEN6_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT 29 |
# define GEN6_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT 18 |
#define GEN6_3DSTATE_POLY_STIPPLE_OFFSET GEN6_3D(3, 1, 6) |
#define GEN6_3DSTATE_POLY_STIPPLE_PATTERN GEN6_3D(3, 1, 7) |
#define GEN6_3DSTATE_LINE_STIPPLE GEN6_3D(3, 1, 8) |
#define GEN6_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP GEN6_3D(3, 1, 9) |
/* These two are BLC and CTG only, not BW or CL */ |
#define GEN6_3DSTATE_AA_LINE_PARAMS GEN6_3D(3, 1, 0xa) |
#define GEN6_3DSTATE_GS_SVB_INDEX GEN6_3D(3, 1, 0xb) |
#define GEN6_3DPRIMITIVE GEN6_3D(3, 3, 0) |
#define GEN6_3DSTATE_CLEAR_PARAMS GEN6_3D(3, 1, 0x10) |
/* DW1 */ |
# define GEN6_3DSTATE_DEPTH_CLEAR_VALID (1 << 15) |
#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS GEN6_3D(3, 0, 0x02) |
# define GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS (1 << 12) |
# define GEN6_3DSTATE_SAMPLER_STATE_MODIFY_GS (1 << 9) |
# define GEN6_3DSTATE_SAMPLER_STATE_MODIFY_VS (1 << 8) |
#define GEN6_3DSTATE_URB GEN6_3D(3, 0, 0x05) |
/* DW1 */ |
# define GEN6_3DSTATE_URB_VS_SIZE_SHIFT 16 |
# define GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT 0 |
/* DW2 */ |
# define GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT 8 |
# define GEN6_3DSTATE_URB_GS_SIZE_SHIFT 0 |
#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS GEN6_3D(3, 0, 0x0d) |
# define GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC (1 << 12) |
# define GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_SF (1 << 11) |
# define GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CLIP (1 << 10) |
#define GEN6_3DSTATE_CC_STATE_POINTERS GEN6_3D(3, 0, 0x0e) |
#define GEN6_3DSTATE_VS GEN6_3D(3, 0, 0x10) |
#define GEN6_3DSTATE_GS GEN6_3D(3, 0, 0x11) |
/* DW4 */ |
# define GEN6_3DSTATE_GS_DISPATCH_START_GRF_SHIFT 0 |
#define GEN6_3DSTATE_CLIP GEN6_3D(3, 0, 0x12) |
#define GEN6_3DSTATE_SF GEN6_3D(3, 0, 0x13) |
/* DW1 */ |
# define GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT 22 |
# define GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT 11 |
# define GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT 4 |
/* DW2 */ |
/* DW3 */ |
# define GEN6_3DSTATE_SF_CULL_BOTH (0 << 29) |
# define GEN6_3DSTATE_SF_CULL_NONE (1 << 29) |
# define GEN6_3DSTATE_SF_CULL_FRONT (2 << 29) |
# define GEN6_3DSTATE_SF_CULL_BACK (3 << 29) |
/* DW4 */ |
# define GEN6_3DSTATE_SF_TRI_PROVOKE_SHIFT 29 |
# define GEN6_3DSTATE_SF_LINE_PROVOKE_SHIFT 27 |
# define GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT 25 |
#define GEN6_3DSTATE_WM GEN6_3D(3, 0, 0x14) |
/* DW2 */ |
# define GEN6_3DSTATE_WM_SAMPLER_COUNT_SHIFT 27 |
# define GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT 18 |
/* DW4 */ |
# define GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT 16 |
/* DW5 */ |
# define GEN6_3DSTATE_WM_MAX_THREADS_SHIFT 25 |
# define GEN6_3DSTATE_WM_DISPATCH_ENABLE (1 << 19) |
# define GEN6_3DSTATE_WM_16_DISPATCH_ENABLE (1 << 1) |
# define GEN6_3DSTATE_WM_8_DISPATCH_ENABLE (1 << 0) |
/* DW6 */ |
# define GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIFT 20 |
# define GEN6_3DSTATE_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 15) |
# define GEN6_3DSTATE_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC (1 << 14) |
# define GEN6_3DSTATE_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC (1 << 13) |
# define GEN6_3DSTATE_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 12) |
# define GEN6_3DSTATE_WM_PERSPECTIVE_CENTROID_BARYCENTRIC (1 << 11) |
# define GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC (1 << 10) |
#define GEN6_3DSTATE_CONSTANT_VS GEN6_3D(3, 0, 0x15) |
#define GEN6_3DSTATE_CONSTANT_GS GEN6_3D(3, 0, 0x16) |
#define GEN6_3DSTATE_CONSTANT_PS GEN6_3D(3, 0, 0x17) |
#define GEN6_3DSTATE_SAMPLE_MASK GEN6_3D(3, 0, 0x18) |
#define GEN6_3DSTATE_MULTISAMPLE GEN6_3D(3, 1, 0x0d) |
/* DW1 */ |
# define GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER (0 << 4) |
# define GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_UPPER_LEFT (1 << 4) |
# define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1 (0 << 1) |
# define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_4 (2 << 1) |
# define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_8 (3 << 1) |
#define PIPELINE_SELECT_3D 0 |
#define PIPELINE_SELECT_MEDIA 1 |
/* for GEN6_STATE_BASE_ADDRESS */ |
#define BASE_ADDRESS_MODIFY (1 << 0) |
/* VERTEX_BUFFER_STATE Structure */ |
#define VB0_BUFFER_INDEX_SHIFT 26 |
#define VB0_VERTEXDATA (0 << 20) |
#define VB0_INSTANCEDATA (1 << 20) |
#define VB0_BUFFER_PITCH_SHIFT 0 |
/* VERTEX_ELEMENT_STATE Structure */ |
#define VE0_VERTEX_BUFFER_INDEX_SHIFT 26 /* for GEN6 */ |
#define VE0_VALID (1 << 25) /* for GEN6 */ |
#define VE0_FORMAT_SHIFT 16 |
#define VE0_OFFSET_SHIFT 0 |
#define VE1_VFCOMPONENT_0_SHIFT 28 |
#define VE1_VFCOMPONENT_1_SHIFT 24 |
#define VE1_VFCOMPONENT_2_SHIFT 20 |
#define VE1_VFCOMPONENT_3_SHIFT 16 |
#define VE1_DESTINATION_ELEMENT_OFFSET_SHIFT 0 |
/* 3DPRIMITIVE bits */ |
#define GEN6_3DPRIMITIVE_VERTEX_SEQUENTIAL (0 << 15) |
#define GEN6_3DPRIMITIVE_VERTEX_RANDOM (1 << 15) |
/* Primitive types are in gen6_defines.h */ |
#define GEN6_3DPRIMITIVE_TOPOLOGY_SHIFT 10 |
#define GEN6_SVG_CTL 0x7400 |
#define GEN6_SVG_CTL_GS_BA (0 << 8) |
#define GEN6_SVG_CTL_SS_BA (1 << 8) |
#define GEN6_SVG_CTL_IO_BA (2 << 8) |
#define GEN6_SVG_CTL_GS_AUB (3 << 8) |
#define GEN6_SVG_CTL_IO_AUB (4 << 8) |
#define GEN6_SVG_CTL_SIP (5 << 8) |
#define GEN6_SVG_RDATA 0x7404 |
#define GEN6_SVG_WORK_CTL 0x7408 |
#define GEN6_VF_CTL 0x7500 |
#define GEN6_VF_CTL_SNAPSHOT_COMPLETE (1 << 31) |
#define GEN6_VF_CTL_SNAPSHOT_MUX_SELECT_THREADID (0 << 8) |
#define GEN6_VF_CTL_SNAPSHOT_MUX_SELECT_VF_DEBUG (1 << 8) |
#define GEN6_VF_CTL_SNAPSHOT_TYPE_VERTEX_SEQUENCE (0 << 4) |
#define GEN6_VF_CTL_SNAPSHOT_TYPE_VERTEX_INDEX (1 << 4) |
#define GEN6_VF_CTL_SKIP_INITIAL_PRIMITIVES (1 << 3) |
#define GEN6_VF_CTL_MAX_PRIMITIVES_LIMIT_ENABLE (1 << 2) |
#define GEN6_VF_CTL_VERTEX_RANGE_LIMIT_ENABLE (1 << 1) |
#define GEN6_VF_CTL_SNAPSHOT_ENABLE (1 << 0) |
#define GEN6_VF_STRG_VAL 0x7504 |
#define GEN6_VF_STR_VL_OVR 0x7508 |
#define GEN6_VF_VC_OVR 0x750c |
#define GEN6_VF_STR_PSKIP 0x7510 |
#define GEN6_VF_MAX_PRIM 0x7514 |
#define GEN6_VF_RDATA 0x7518 |
#define GEN6_VS_CTL 0x7600 |
#define GEN6_VS_CTL_SNAPSHOT_COMPLETE (1 << 31) |
#define GEN6_VS_CTL_SNAPSHOT_MUX_VERTEX_0 (0 << 8) |
#define GEN6_VS_CTL_SNAPSHOT_MUX_VERTEX_1 (1 << 8) |
#define GEN6_VS_CTL_SNAPSHOT_MUX_VALID_COUNT (2 << 8) |
#define GEN6_VS_CTL_SNAPSHOT_MUX_VS_KERNEL_POINTER (3 << 8) |
#define GEN6_VS_CTL_SNAPSHOT_ALL_THREADS (1 << 2) |
#define GEN6_VS_CTL_THREAD_SNAPSHOT_ENABLE (1 << 1) |
#define GEN6_VS_CTL_SNAPSHOT_ENABLE (1 << 0) |
#define GEN6_VS_STRG_VAL 0x7604 |
#define GEN6_VS_RDATA 0x7608 |
#define GEN6_SF_CTL 0x7b00 |
#define GEN6_SF_CTL_SNAPSHOT_COMPLETE (1 << 31) |
#define GEN6_SF_CTL_SNAPSHOT_MUX_VERTEX_0_FF_ID (0 << 8) |
#define GEN6_SF_CTL_SNAPSHOT_MUX_VERTEX_0_REL_COUNT (1 << 8) |
#define GEN6_SF_CTL_SNAPSHOT_MUX_VERTEX_1_FF_ID (2 << 8) |
#define GEN6_SF_CTL_SNAPSHOT_MUX_VERTEX_1_REL_COUNT (3 << 8) |
#define GEN6_SF_CTL_SNAPSHOT_MUX_VERTEX_2_FF_ID (4 << 8) |
#define GEN6_SF_CTL_SNAPSHOT_MUX_VERTEX_2_REL_COUNT (5 << 8) |
#define GEN6_SF_CTL_SNAPSHOT_MUX_VERTEX_COUNT (6 << 8) |
#define GEN6_SF_CTL_SNAPSHOT_MUX_SF_KERNEL_POINTER (7 << 8) |
#define GEN6_SF_CTL_MIN_MAX_PRIMITIVE_RANGE_ENABLE (1 << 4) |
#define GEN6_SF_CTL_DEBUG_CLIP_RECTANGLE_ENABLE (1 << 3) |
#define GEN6_SF_CTL_SNAPSHOT_ALL_THREADS (1 << 2) |
#define GEN6_SF_CTL_THREAD_SNAPSHOT_ENABLE (1 << 1) |
#define GEN6_SF_CTL_SNAPSHOT_ENABLE (1 << 0) |
#define GEN6_SF_STRG_VAL 0x7b04 |
#define GEN6_SF_RDATA 0x7b18 |
#define GEN6_WIZ_CTL 0x7c00 |
#define GEN6_WIZ_CTL_SNAPSHOT_COMPLETE (1 << 31) |
#define GEN6_WIZ_CTL_SUBSPAN_INSTANCE_SHIFT 16 |
#define GEN6_WIZ_CTL_SNAPSHOT_MUX_WIZ_KERNEL_POINTER (0 << 8) |
#define GEN6_WIZ_CTL_SNAPSHOT_MUX_SUBSPAN_INSTANCE (1 << 8) |
#define GEN6_WIZ_CTL_SNAPSHOT_MUX_PRIMITIVE_SEQUENCE (2 << 8) |
#define GEN6_WIZ_CTL_SINGLE_SUBSPAN_DISPATCH (1 << 6) |
#define GEN6_WIZ_CTL_IGNORE_COLOR_SCOREBOARD_STALLS (1 << 5) |
#define GEN6_WIZ_CTL_ENABLE_SUBSPAN_INSTANCE_COMPARE (1 << 4) |
#define GEN6_WIZ_CTL_USE_UPSTREAM_SNAPSHOT_FLAG (1 << 3) |
#define GEN6_WIZ_CTL_SNAPSHOT_ALL_THREADS (1 << 2) |
#define GEN6_WIZ_CTL_THREAD_SNAPSHOT_ENABLE (1 << 1) |
#define GEN6_WIZ_CTL_SNAPSHOT_ENABLE (1 << 0) |
#define GEN6_WIZ_STRG_VAL 0x7c04 |
#define GEN6_WIZ_RDATA 0x7c18 |
#define GEN6_TS_CTL 0x7e00 |
#define GEN6_TS_CTL_SNAPSHOT_COMPLETE (1 << 31) |
#define GEN6_TS_CTL_SNAPSHOT_MESSAGE_ERROR (0 << 8) |
#define GEN6_TS_CTL_SNAPSHOT_INTERFACE_DESCRIPTOR (3 << 8) |
#define GEN6_TS_CTL_SNAPSHOT_ALL_CHILD_THREADS (1 << 2) |
#define GEN6_TS_CTL_SNAPSHOT_ALL_ROOT_THREADS (1 << 1) |
#define GEN6_TS_CTL_SNAPSHOT_ENABLE (1 << 0) |
#define GEN6_TS_STRG_VAL 0x7e04 |
#define GEN6_TS_RDATA 0x7e08 |
#define GEN6_TD_CTL 0x8000 |
#define GEN6_TD_CTL_MUX_SHIFT 8 |
#define GEN6_TD_CTL_EXTERNAL_HALT_R0_DEBUG_MATCH (1 << 7) |
#define GEN6_TD_CTL_FORCE_EXTERNAL_HALT (1 << 6) |
#define GEN6_TD_CTL_EXCEPTION_MASK_OVERRIDE (1 << 5) |
#define GEN6_TD_CTL_FORCE_THREAD_BREAKPOINT_ENABLE (1 << 4) |
#define GEN6_TD_CTL_BREAKPOINT_ENABLE (1 << 2) |
#define GEN6_TD_CTL2 0x8004 |
#define GEN6_TD_CTL2_ILLEGAL_OPCODE_EXCEPTION_OVERRIDE (1 << 28) |
#define GEN6_TD_CTL2_MASKSTACK_EXCEPTION_OVERRIDE (1 << 26) |
#define GEN6_TD_CTL2_SOFTWARE_EXCEPTION_OVERRIDE (1 << 25) |
#define GEN6_TD_CTL2_ACTIVE_THREAD_LIMIT_SHIFT 16 |
#define GEN6_TD_CTL2_ACTIVE_THREAD_LIMIT_ENABLE (1 << 8) |
#define GEN6_TD_CTL2_THREAD_SPAWNER_EXECUTION_MASK_ENABLE (1 << 7) |
#define GEN6_TD_CTL2_WIZ_EXECUTION_MASK_ENABLE (1 << 6) |
#define GEN6_TD_CTL2_SF_EXECUTION_MASK_ENABLE (1 << 5) |
#define GEN6_TD_CTL2_CLIPPER_EXECUTION_MASK_ENABLE (1 << 4) |
#define GEN6_TD_CTL2_GS_EXECUTION_MASK_ENABLE (1 << 3) |
#define GEN6_TD_CTL2_VS_EXECUTION_MASK_ENABLE (1 << 0) |
#define GEN6_TD_VF_VS_EMSK 0x8008 |
#define GEN6_TD_GS_EMSK 0x800c |
#define GEN6_TD_CLIP_EMSK 0x8010 |
#define GEN6_TD_SF_EMSK 0x8014 |
#define GEN6_TD_WIZ_EMSK 0x8018 |
#define GEN6_TD_0_6_EHTRG_VAL 0x801c |
#define GEN6_TD_0_7_EHTRG_VAL 0x8020 |
#define GEN6_TD_0_6_EHTRG_MSK 0x8024 |
#define GEN6_TD_0_7_EHTRG_MSK 0x8028 |
#define GEN6_TD_RDATA 0x802c |
#define GEN6_TD_TS_EMSK 0x8030 |
#define GEN6_EU_CTL 0x8800 |
#define GEN6_EU_CTL_SELECT_SHIFT 16 |
#define GEN6_EU_CTL_DATA_MUX_SHIFT 8 |
#define GEN6_EU_ATT_0 0x8810 |
#define GEN6_EU_ATT_1 0x8814 |
#define GEN6_EU_ATT_DATA_0 0x8820 |
#define GEN6_EU_ATT_DATA_1 0x8824 |
#define GEN6_EU_ATT_CLR_0 0x8830 |
#define GEN6_EU_ATT_CLR_1 0x8834 |
#define GEN6_EU_RDATA 0x8840 |
#define GEN6_3D(Pipeline,Opcode,Subopcode) ((3 << 29) | \ |
((Pipeline) << 27) | \ |
((Opcode) << 24) | \ |
((Subopcode) << 16)) |
#define GEN6_STATE_BASE_ADDRESS GEN6_3D(0, 1, 1) |
#define GEN6_STATE_SIP GEN6_3D(0, 1, 2) |
#define GEN6_PIPELINE_SELECT GEN6_3D(1, 1, 4) |
#define GEN6_MEDIA_STATE_POINTERS GEN6_3D(2, 0, 0) |
#define GEN6_MEDIA_OBJECT GEN6_3D(2, 1, 0) |
#define GEN6_3DSTATE_BINDING_TABLE_POINTERS GEN6_3D(3, 0, 1) |
# define GEN6_3DSTATE_BINDING_TABLE_MODIFY_PS (1 << 12)/* for GEN6 */ |
# define GEN6_3DSTATE_BINDING_TABLE_MODIFY_GS (1 << 9) /* for GEN6 */ |
# define GEN6_3DSTATE_BINDING_TABLE_MODIFY_VS (1 << 8) /* for GEN6 */ |
#define GEN6_3DSTATE_VERTEX_BUFFERS GEN6_3D(3, 0, 8) |
#define GEN6_3DSTATE_VERTEX_ELEMENTS GEN6_3D(3, 0, 9) |
#define GEN6_3DSTATE_INDEX_BUFFER GEN6_3D(3, 0, 0xa) |
#define GEN6_3DSTATE_VF_STATISTICS GEN6_3D(3, 0, 0xb) |
#define GEN6_3DSTATE_DRAWING_RECTANGLE GEN6_3D(3, 1, 0) |
#define GEN6_3DSTATE_CONSTANT_COLOR GEN6_3D(3, 1, 1) |
#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD GEN6_3D(3, 1, 2) |
#define GEN6_3DSTATE_CHROMA_KEY GEN6_3D(3, 1, 4) |
#define GEN6_3DSTATE_DEPTH_BUFFER GEN6_3D(3, 1, 5) |
# define GEN6_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT 29 |
# define GEN6_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT 18 |
#define GEN6_3DSTATE_POLY_STIPPLE_OFFSET GEN6_3D(3, 1, 6) |
#define GEN6_3DSTATE_POLY_STIPPLE_PATTERN GEN6_3D(3, 1, 7) |
#define GEN6_3DSTATE_LINE_STIPPLE GEN6_3D(3, 1, 8) |
#define GEN6_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP GEN6_3D(3, 1, 9) |
/* These two are BLC and CTG only, not BW or CL */ |
#define GEN6_3DSTATE_AA_LINE_PARAMS GEN6_3D(3, 1, 0xa) |
#define GEN6_3DSTATE_GS_SVB_INDEX GEN6_3D(3, 1, 0xb) |
#define GEN6_3DPRIMITIVE GEN6_3D(3, 3, 0) |
#define GEN6_3DSTATE_CLEAR_PARAMS GEN6_3D(3, 1, 0x10) |
/* DW1 */ |
# define GEN6_3DSTATE_DEPTH_CLEAR_VALID (1 << 15) |
/* for GEN6+ */ |
#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS GEN6_3D(3, 0, 0x02) |
# define GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS (1 << 12) |
# define GEN6_3DSTATE_SAMPLER_STATE_MODIFY_GS (1 << 9) |
# define GEN6_3DSTATE_SAMPLER_STATE_MODIFY_VS (1 << 8) |
#define GEN6_3DSTATE_URB GEN6_3D(3, 0, 0x05) |
/* DW1 */ |
# define GEN6_3DSTATE_URB_VS_SIZE_SHIFT 16 |
# define GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT 0 |
/* DW2 */ |
# define GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT 8 |
# define GEN6_3DSTATE_URB_GS_SIZE_SHIFT 0 |
#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS GEN6_3D(3, 0, 0x0d) |
# define GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC (1 << 12) |
# define GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_SF (1 << 11) |
# define GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CLIP (1 << 10) |
#define GEN6_3DSTATE_CC_STATE_POINTERS GEN6_3D(3, 0, 0x0e) |
#define GEN6_3DSTATE_VS GEN6_3D(3, 0, 0x10) |
#define GEN6_3DSTATE_GS GEN6_3D(3, 0, 0x11) |
/* DW4 */ |
# define GEN6_3DSTATE_GS_DISPATCH_START_GRF_SHIFT 0 |
#define GEN6_3DSTATE_CLIP GEN6_3D(3, 0, 0x12) |
#define GEN6_3DSTATE_SF GEN6_3D(3, 0, 0x13) |
/* DW1 */ |
# define GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT 22 |
# define GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT 11 |
# define GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT 4 |
/* DW2 */ |
/* DW3 */ |
# define GEN6_3DSTATE_SF_CULL_BOTH (0 << 29) |
# define GEN6_3DSTATE_SF_CULL_NONE (1 << 29) |
# define GEN6_3DSTATE_SF_CULL_FRONT (2 << 29) |
# define GEN6_3DSTATE_SF_CULL_BACK (3 << 29) |
/* DW4 */ |
# define GEN6_3DSTATE_SF_TRI_PROVOKE_SHIFT 29 |
# define GEN6_3DSTATE_SF_LINE_PROVOKE_SHIFT 27 |
# define GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT 25 |
#define GEN6_3DSTATE_WM GEN6_3D(3, 0, 0x14) |
/* DW2 */ |
# define GEN6_3DSTATE_WM_SAMPLER_COUNT_SHITF 27 |
# define GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT 18 |
/* DW4 */ |
# define GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT 16 |
/* DW5 */ |
# define GEN6_3DSTATE_WM_MAX_THREADS_SHIFT 25 |
# define GEN6_3DSTATE_WM_DISPATCH_ENABLE (1 << 19) |
# define GEN6_3DSTATE_WM_16_DISPATCH_ENABLE (1 << 1) |
# define GEN6_3DSTATE_WM_8_DISPATCH_ENABLE (1 << 0) |
/* DW6 */ |
# define GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIFT 20 |
# define GEN6_3DSTATE_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 15) |
# define GEN6_3DSTATE_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC (1 << 14) |
# define GEN6_3DSTATE_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC (1 << 13) |
# define GEN6_3DSTATE_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 12) |
# define GEN6_3DSTATE_WM_PERSPECTIVE_CENTROID_BARYCENTRIC (1 << 11) |
# define GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC (1 << 10) |
#define GEN6_3DSTATE_CONSTANT_VS GEN6_3D(3, 0, 0x15) |
#define GEN6_3DSTATE_CONSTANT_GS GEN6_3D(3, 0, 0x16) |
#define GEN6_3DSTATE_CONSTANT_PS GEN6_3D(3, 0, 0x17) |
#define GEN6_3DSTATE_SAMPLE_MASK GEN6_3D(3, 0, 0x18) |
#define GEN6_3DSTATE_MULTISAMPLE GEN6_3D(3, 1, 0x0d) |
/* DW1 */ |
# define GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER (0 << 4) |
# define GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_UPPER_LEFT (1 << 4) |
# define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1 (0 << 1) |
# define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_4 (2 << 1) |
# define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_8 (3 << 1) |
#define PIPELINE_SELECT_3D 0 |
#define PIPELINE_SELECT_MEDIA 1 |
#define UF0_CS_REALLOC (1 << 13) |
#define UF0_VFE_REALLOC (1 << 12) |
#define UF0_SF_REALLOC (1 << 11) |
#define UF0_CLIP_REALLOC (1 << 10) |
#define UF0_GS_REALLOC (1 << 9) |
#define UF0_VS_REALLOC (1 << 8) |
#define UF1_CLIP_FENCE_SHIFT 20 |
#define UF1_GS_FENCE_SHIFT 10 |
#define UF1_VS_FENCE_SHIFT 0 |
#define UF2_CS_FENCE_SHIFT 20 |
#define UF2_VFE_FENCE_SHIFT 10 |
#define UF2_SF_FENCE_SHIFT 0 |
/* for GEN6_STATE_BASE_ADDRESS */ |
#define BASE_ADDRESS_MODIFY (1 << 0) |
/* for GEN6_3DSTATE_PIPELINED_POINTERS */ |
#define GEN6_GS_DISABLE 0 |
#define GEN6_GS_ENABLE 1 |
#define GEN6_CLIP_DISABLE 0 |
#define GEN6_CLIP_ENABLE 1 |
/* for GEN6_PIPE_CONTROL */ |
#define GEN6_PIPE_CONTROL GEN6_3D(3, 2, 0) |
#define GEN6_PIPE_CONTROL_CS_STALL (1 << 20) |
#define GEN6_PIPE_CONTROL_NOWRITE (0 << 14) |
#define GEN6_PIPE_CONTROL_WRITE_QWORD (1 << 14) |
#define GEN6_PIPE_CONTROL_WRITE_DEPTH (2 << 14) |
#define GEN6_PIPE_CONTROL_WRITE_TIME (3 << 14) |
#define GEN6_PIPE_CONTROL_DEPTH_STALL (1 << 13) |
#define GEN6_PIPE_CONTROL_WC_FLUSH (1 << 12) |
#define GEN6_PIPE_CONTROL_IS_FLUSH (1 << 11) |
#define GEN6_PIPE_CONTROL_TC_FLUSH (1 << 10) |
#define GEN6_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8) |
#define GEN6_PIPE_CONTROL_GLOBAL_GTT (1 << 2) |
#define GEN6_PIPE_CONTROL_LOCAL_PGTT (0 << 2) |
#define GEN6_PIPE_CONTROL_STALL_AT_SCOREBOARD (1 << 1) |
#define GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0) |
/* 3DPRIMITIVE bits */ |
#define GEN6_3DPRIMITIVE_VERTEX_SEQUENTIAL (0 << 15) |
#define GEN6_3DPRIMITIVE_VERTEX_RANDOM (1 << 15) |
/* Primitive types are in gen6_defines.h */ |
#define GEN6_3DPRIMITIVE_TOPOLOGY_SHIFT 10 |
#define GEN6_SVG_CTL 0x7400 |
#define GEN6_SVG_CTL_GS_BA (0 << 8) |
#define GEN6_SVG_CTL_SS_BA (1 << 8) |
#define GEN6_SVG_CTL_IO_BA (2 << 8) |
#define GEN6_SVG_CTL_GS_AUB (3 << 8) |
#define GEN6_SVG_CTL_IO_AUB (4 << 8) |
#define GEN6_SVG_CTL_SIP (5 << 8) |
#define GEN6_SVG_RDATA 0x7404 |
#define GEN6_SVG_WORK_CTL 0x7408 |
#define GEN6_VF_CTL 0x7500 |
#define GEN6_VF_CTL_SNAPSHOT_COMPLETE (1 << 31) |
#define GEN6_VF_CTL_SNAPSHOT_MUX_SELECT_THREADID (0 << 8) |
#define GEN6_VF_CTL_SNAPSHOT_MUX_SELECT_VF_DEBUG (1 << 8) |
#define GEN6_VF_CTL_SNAPSHOT_TYPE_VERTEX_SEQUENCE (0 << 4) |
#define GEN6_VF_CTL_SNAPSHOT_TYPE_VERTEX_INDEX (1 << 4) |
#define GEN6_VF_CTL_SKIP_INITIAL_PRIMITIVES (1 << 3) |
#define GEN6_VF_CTL_MAX_PRIMITIVES_LIMIT_ENABLE (1 << 2) |
#define GEN6_VF_CTL_VERTEX_RANGE_LIMIT_ENABLE (1 << 1) |
#define GEN6_VF_CTL_SNAPSHOT_ENABLE (1 << 0) |
#define GEN6_VF_STRG_VAL 0x7504 |
#define GEN6_VF_STR_VL_OVR 0x7508 |
#define GEN6_VF_VC_OVR 0x750c |
#define GEN6_VF_STR_PSKIP 0x7510 |
#define GEN6_VF_MAX_PRIM 0x7514 |
#define GEN6_VF_RDATA 0x7518 |
#define GEN6_VS_CTL 0x7600 |
#define GEN6_VS_CTL_SNAPSHOT_COMPLETE (1 << 31) |
#define GEN6_VS_CTL_SNAPSHOT_MUX_VERTEX_0 (0 << 8) |
#define GEN6_VS_CTL_SNAPSHOT_MUX_VERTEX_1 (1 << 8) |
#define GEN6_VS_CTL_SNAPSHOT_MUX_VALID_COUNT (2 << 8) |
#define GEN6_VS_CTL_SNAPSHOT_MUX_VS_KERNEL_POINTER (3 << 8) |
#define GEN6_VS_CTL_SNAPSHOT_ALL_THREADS (1 << 2) |
#define GEN6_VS_CTL_THREAD_SNAPSHOT_ENABLE (1 << 1) |
#define GEN6_VS_CTL_SNAPSHOT_ENABLE (1 << 0) |
#define GEN6_VS_STRG_VAL 0x7604 |
#define GEN6_VS_RDATA 0x7608 |
#define GEN6_SF_CTL 0x7b00 |
#define GEN6_SF_CTL_SNAPSHOT_COMPLETE (1 << 31) |
#define GEN6_SF_CTL_SNAPSHOT_MUX_VERTEX_0_FF_ID (0 << 8) |
#define GEN6_SF_CTL_SNAPSHOT_MUX_VERTEX_0_REL_COUNT (1 << 8) |
#define GEN6_SF_CTL_SNAPSHOT_MUX_VERTEX_1_FF_ID (2 << 8) |
#define GEN6_SF_CTL_SNAPSHOT_MUX_VERTEX_1_REL_COUNT (3 << 8) |
#define GEN6_SF_CTL_SNAPSHOT_MUX_VERTEX_2_FF_ID (4 << 8) |
#define GEN6_SF_CTL_SNAPSHOT_MUX_VERTEX_2_REL_COUNT (5 << 8) |
#define GEN6_SF_CTL_SNAPSHOT_MUX_VERTEX_COUNT (6 << 8) |
#define GEN6_SF_CTL_SNAPSHOT_MUX_SF_KERNEL_POINTER (7 << 8) |
#define GEN6_SF_CTL_MIN_MAX_PRIMITIVE_RANGE_ENABLE (1 << 4) |
#define GEN6_SF_CTL_DEBUG_CLIP_RECTANGLE_ENABLE (1 << 3) |
#define GEN6_SF_CTL_SNAPSHOT_ALL_THREADS (1 << 2) |
#define GEN6_SF_CTL_THREAD_SNAPSHOT_ENABLE (1 << 1) |
#define GEN6_SF_CTL_SNAPSHOT_ENABLE (1 << 0) |
#define GEN6_SF_STRG_VAL 0x7b04 |
#define GEN6_SF_RDATA 0x7b18 |
#define GEN6_WIZ_CTL 0x7c00 |
#define GEN6_WIZ_CTL_SNAPSHOT_COMPLETE (1 << 31) |
#define GEN6_WIZ_CTL_SUBSPAN_INSTANCE_SHIFT 16 |
#define GEN6_WIZ_CTL_SNAPSHOT_MUX_WIZ_KERNEL_POINTER (0 << 8) |
#define GEN6_WIZ_CTL_SNAPSHOT_MUX_SUBSPAN_INSTANCE (1 << 8) |
#define GEN6_WIZ_CTL_SNAPSHOT_MUX_PRIMITIVE_SEQUENCE (2 << 8) |
#define GEN6_WIZ_CTL_SINGLE_SUBSPAN_DISPATCH (1 << 6) |
#define GEN6_WIZ_CTL_IGNORE_COLOR_SCOREBOARD_STALLS (1 << 5) |
#define GEN6_WIZ_CTL_ENABLE_SUBSPAN_INSTANCE_COMPARE (1 << 4) |
#define GEN6_WIZ_CTL_USE_UPSTREAM_SNAPSHOT_FLAG (1 << 3) |
#define GEN6_WIZ_CTL_SNAPSHOT_ALL_THREADS (1 << 2) |
#define GEN6_WIZ_CTL_THREAD_SNAPSHOT_ENABLE (1 << 1) |
#define GEN6_WIZ_CTL_SNAPSHOT_ENABLE (1 << 0) |
#define GEN6_WIZ_STRG_VAL 0x7c04 |
#define GEN6_WIZ_RDATA 0x7c18 |
#define GEN6_TS_CTL 0x7e00 |
#define GEN6_TS_CTL_SNAPSHOT_COMPLETE (1 << 31) |
#define GEN6_TS_CTL_SNAPSHOT_MESSAGE_ERROR (0 << 8) |
#define GEN6_TS_CTL_SNAPSHOT_INTERFACE_DESCRIPTOR (3 << 8) |
#define GEN6_TS_CTL_SNAPSHOT_ALL_CHILD_THREADS (1 << 2) |
#define GEN6_TS_CTL_SNAPSHOT_ALL_ROOT_THREADS (1 << 1) |
#define GEN6_TS_CTL_SNAPSHOT_ENABLE (1 << 0) |
#define GEN6_TS_STRG_VAL 0x7e04 |
#define GEN6_TS_RDATA 0x7e08 |
#define GEN6_TD_CTL 0x8000 |
#define GEN6_TD_CTL_MUX_SHIFT 8 |
#define GEN6_TD_CTL_EXTERNAL_HALT_R0_DEBUG_MATCH (1 << 7) |
#define GEN6_TD_CTL_FORCE_EXTERNAL_HALT (1 << 6) |
#define GEN6_TD_CTL_EXCEPTION_MASK_OVERRIDE (1 << 5) |
#define GEN6_TD_CTL_FORCE_THREAD_BREAKPOINT_ENABLE (1 << 4) |
#define GEN6_TD_CTL_BREAKPOINT_ENABLE (1 << 2) |
#define GEN6_TD_CTL2 0x8004 |
#define GEN6_TD_CTL2_ILLEGAL_OPCODE_EXCEPTION_OVERRIDE (1 << 28) |
#define GEN6_TD_CTL2_MASKSTACK_EXCEPTION_OVERRIDE (1 << 26) |
#define GEN6_TD_CTL2_SOFTWARE_EXCEPTION_OVERRIDE (1 << 25) |
#define GEN6_TD_CTL2_ACTIVE_THREAD_LIMIT_SHIFT 16 |
#define GEN6_TD_CTL2_ACTIVE_THREAD_LIMIT_ENABLE (1 << 8) |
#define GEN6_TD_CTL2_THREAD_SPAWNER_EXECUTION_MASK_ENABLE (1 << 7) |
#define GEN6_TD_CTL2_WIZ_EXECUTION_MASK_ENABLE (1 << 6) |
#define GEN6_TD_CTL2_SF_EXECUTION_MASK_ENABLE (1 << 5) |
#define GEN6_TD_CTL2_CLIPPER_EXECUTION_MASK_ENABLE (1 << 4) |
#define GEN6_TD_CTL2_GS_EXECUTION_MASK_ENABLE (1 << 3) |
#define GEN6_TD_CTL2_VS_EXECUTION_MASK_ENABLE (1 << 0) |
#define GEN6_TD_VF_VS_EMSK 0x8008 |
#define GEN6_TD_GS_EMSK 0x800c |
#define GEN6_TD_CLIP_EMSK 0x8010 |
#define GEN6_TD_SF_EMSK 0x8014 |
#define GEN6_TD_WIZ_EMSK 0x8018 |
#define GEN6_TD_0_6_EHTRG_VAL 0x801c |
#define GEN6_TD_0_7_EHTRG_VAL 0x8020 |
#define GEN6_TD_0_6_EHTRG_MSK 0x8024 |
#define GEN6_TD_0_7_EHTRG_MSK 0x8028 |
#define GEN6_TD_RDATA 0x802c |
#define GEN6_TD_TS_EMSK 0x8030 |
#define GEN6_EU_CTL 0x8800 |
#define GEN6_EU_CTL_SELECT_SHIFT 16 |
#define GEN6_EU_CTL_DATA_MUX_SHIFT 8 |
#define GEN6_EU_ATT_0 0x8810 |
#define GEN6_EU_ATT_1 0x8814 |
#define GEN6_EU_ATT_DATA_0 0x8820 |
#define GEN6_EU_ATT_DATA_1 0x8824 |
#define GEN6_EU_ATT_CLR_0 0x8830 |
#define GEN6_EU_ATT_CLR_1 0x8834 |
#define GEN6_EU_RDATA 0x8840 |
/* 3D state: |
*/ |
#define _3DOP_3DSTATE_PIPELINED 0x0 |
#define _3DOP_3DSTATE_NONPIPELINED 0x1 |
#define _3DOP_3DCONTROL 0x2 |
#define _3DOP_3DPRIMITIVE 0x3 |
#define _3DSTATE_PIPELINED_POINTERS 0x00 |
#define _3DSTATE_BINDING_TABLE_POINTERS 0x01 |
#define _3DSTATE_VERTEX_BUFFERS 0x08 |
#define _3DSTATE_VERTEX_ELEMENTS 0x09 |
#define _3DSTATE_INDEX_BUFFER 0x0A |
#define _3DSTATE_VF_STATISTICS 0x0B |
#define _3DSTATE_DRAWING_RECTANGLE 0x00 |
#define _3DSTATE_CONSTANT_COLOR 0x01 |
#define _3DSTATE_SAMPLER_PALETTE_LOAD 0x02 |
#define _3DSTATE_CHROMA_KEY 0x04 |
#define _3DSTATE_DEPTH_BUFFER 0x05 |
#define _3DSTATE_POLY_STIPPLE_OFFSET 0x06 |
#define _3DSTATE_POLY_STIPPLE_PATTERN 0x07 |
#define _3DSTATE_LINE_STIPPLE 0x08 |
#define _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP 0x09 |
#define _3DCONTROL 0x00 |
#define _3DPRIMITIVE 0x00 |
#define _3DPRIM_POINTLIST 0x01 |
#define _3DPRIM_LINELIST 0x02 |
#define _3DPRIM_LINESTRIP 0x03 |
#define _3DPRIM_TRILIST 0x04 |
#define _3DPRIM_TRISTRIP 0x05 |
#define _3DPRIM_TRIFAN 0x06 |
#define _3DPRIM_QUADLIST 0x07 |
#define _3DPRIM_QUADSTRIP 0x08 |
#define _3DPRIM_LINELIST_ADJ 0x09 |
#define _3DPRIM_LINESTRIP_ADJ 0x0A |
#define _3DPRIM_TRILIST_ADJ 0x0B |
#define _3DPRIM_TRISTRIP_ADJ 0x0C |
#define _3DPRIM_TRISTRIP_REVERSE 0x0D |
#define _3DPRIM_POLYGON 0x0E |
#define _3DPRIM_RECTLIST 0x0F |
#define _3DPRIM_LINELOOP 0x10 |
#define _3DPRIM_POINTLIST_BF 0x11 |
#define _3DPRIM_LINESTRIP_CONT 0x12 |
#define _3DPRIM_LINESTRIP_BF 0x13 |
#define _3DPRIM_LINESTRIP_CONT_BF 0x14 |
#define _3DPRIM_TRIFAN_NOSTIPPLE 0x15 |
#define _3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL 0 |
#define _3DPRIM_VERTEXBUFFER_ACCESS_RANDOM 1 |
#define GEN6_ANISORATIO_2 0 |
#define GEN6_ANISORATIO_4 1 |
#define GEN6_ANISORATIO_6 2 |
#define GEN6_ANISORATIO_8 3 |
#define GEN6_ANISORATIO_10 4 |
#define GEN6_ANISORATIO_12 5 |
#define GEN6_ANISORATIO_14 6 |
#define GEN6_ANISORATIO_16 7 |
#define GEN6_BLENDFACTOR_ONE 0x1 |
#define GEN6_BLENDFACTOR_SRC_COLOR 0x2 |
#define GEN6_BLENDFACTOR_SRC_ALPHA 0x3 |
#define GEN6_BLENDFACTOR_DST_ALPHA 0x4 |
#define GEN6_BLENDFACTOR_DST_COLOR 0x5 |
#define GEN6_BLENDFACTOR_SRC_ALPHA_SATURATE 0x6 |
#define GEN6_BLENDFACTOR_CONST_COLOR 0x7 |
#define GEN6_BLENDFACTOR_CONST_ALPHA 0x8 |
#define GEN6_BLENDFACTOR_SRC1_COLOR 0x9 |
#define GEN6_BLENDFACTOR_SRC1_ALPHA 0x0A |
#define GEN6_BLENDFACTOR_ZERO 0x11 |
#define GEN6_BLENDFACTOR_INV_SRC_COLOR 0x12 |
#define GEN6_BLENDFACTOR_INV_SRC_ALPHA 0x13 |
#define GEN6_BLENDFACTOR_INV_DST_ALPHA 0x14 |
#define GEN6_BLENDFACTOR_INV_DST_COLOR 0x15 |
#define GEN6_BLENDFACTOR_INV_CONST_COLOR 0x17 |
#define GEN6_BLENDFACTOR_INV_CONST_ALPHA 0x18 |
#define GEN6_BLENDFACTOR_INV_SRC1_COLOR 0x19 |
#define GEN6_BLENDFACTOR_INV_SRC1_ALPHA 0x1A |
#define GEN6_BLENDFUNCTION_ADD 0 |
#define GEN6_BLENDFUNCTION_SUBTRACT 1 |
#define GEN6_BLENDFUNCTION_REVERSE_SUBTRACT 2 |
#define GEN6_BLENDFUNCTION_MIN 3 |
#define GEN6_BLENDFUNCTION_MAX 4 |
#define GEN6_ALPHATEST_FORMAT_UNORM8 0 |
#define GEN6_ALPHATEST_FORMAT_FLOAT32 1 |
#define GEN6_CHROMAKEY_KILL_ON_ANY_MATCH 0 |
#define GEN6_CHROMAKEY_REPLACE_BLACK 1 |
#define GEN6_CLIP_API_OGL 0 |
#define GEN6_CLIP_API_DX 1 |
#define GEN6_CLIPMODE_NORMAL 0 |
#define GEN6_CLIPMODE_CLIP_ALL 1 |
#define GEN6_CLIPMODE_CLIP_NON_REJECTED 2 |
#define GEN6_CLIPMODE_REJECT_ALL 3 |
#define GEN6_CLIPMODE_ACCEPT_ALL 4 |
#define GEN6_CLIP_NDCSPACE 0 |
#define GEN6_CLIP_SCREENSPACE 1 |
#define GEN6_COMPAREFUNCTION_ALWAYS 0 |
#define GEN6_COMPAREFUNCTION_NEVER 1 |
#define GEN6_COMPAREFUNCTION_LESS 2 |
#define GEN6_COMPAREFUNCTION_EQUAL 3 |
#define GEN6_COMPAREFUNCTION_LEQUAL 4 |
#define GEN6_COMPAREFUNCTION_GREATER 5 |
#define GEN6_COMPAREFUNCTION_NOTEQUAL 6 |
#define GEN6_COMPAREFUNCTION_GEQUAL 7 |
#define GEN6_COVERAGE_PIXELS_HALF 0 |
#define GEN6_COVERAGE_PIXELS_1 1 |
#define GEN6_COVERAGE_PIXELS_2 2 |
#define GEN6_COVERAGE_PIXELS_4 3 |
#define GEN6_CULLMODE_BOTH 0 |
#define GEN6_CULLMODE_NONE 1 |
#define GEN6_CULLMODE_FRONT 2 |
#define GEN6_CULLMODE_BACK 3 |
#define GEN6_DEFAULTCOLOR_R8G8B8A8_UNORM 0 |
#define GEN6_DEFAULTCOLOR_R32G32B32A32_FLOAT 1 |
#define GEN6_DEPTHFORMAT_D32_FLOAT_S8X24_UINT 0 |
#define GEN6_DEPTHFORMAT_D32_FLOAT 1 |
#define GEN6_DEPTHFORMAT_D24_UNORM_S8_UINT 2 |
#define GEN6_DEPTHFORMAT_D16_UNORM 5 |
#define GEN6_FLOATING_POINT_IEEE_754 0 |
#define GEN6_FLOATING_POINT_NON_IEEE_754 1 |
#define GEN6_FRONTWINDING_CW 0 |
#define GEN6_FRONTWINDING_CCW 1 |
#define GEN6_INDEX_BYTE 0 |
#define GEN6_INDEX_WORD 1 |
#define GEN6_INDEX_DWORD 2 |
#define GEN6_LOGICOPFUNCTION_CLEAR 0 |
#define GEN6_LOGICOPFUNCTION_NOR 1 |
#define GEN6_LOGICOPFUNCTION_AND_INVERTED 2 |
#define GEN6_LOGICOPFUNCTION_COPY_INVERTED 3 |
#define GEN6_LOGICOPFUNCTION_AND_REVERSE 4 |
#define GEN6_LOGICOPFUNCTION_INVERT 5 |
#define GEN6_LOGICOPFUNCTION_XOR 6 |
#define GEN6_LOGICOPFUNCTION_NAND 7 |
#define GEN6_LOGICOPFUNCTION_AND 8 |
#define GEN6_LOGICOPFUNCTION_EQUIV 9 |
#define GEN6_LOGICOPFUNCTION_NOOP 10 |
#define GEN6_LOGICOPFUNCTION_OR_INVERTED 11 |
#define GEN6_LOGICOPFUNCTION_COPY 12 |
#define GEN6_LOGICOPFUNCTION_OR_REVERSE 13 |
#define GEN6_LOGICOPFUNCTION_OR 14 |
#define GEN6_LOGICOPFUNCTION_SET 15 |
#define GEN6_MAPFILTER_NEAREST 0x0 |
#define GEN6_MAPFILTER_LINEAR 0x1 |
#define GEN6_MAPFILTER_ANISOTROPIC 0x2 |
#define GEN6_MIPFILTER_NONE 0 |
#define GEN6_MIPFILTER_NEAREST 1 |
#define GEN6_MIPFILTER_LINEAR 3 |
#define GEN6_POLYGON_FRONT_FACING 0 |
#define GEN6_POLYGON_BACK_FACING 1 |
#define GEN6_PREFILTER_ALWAYS 0x0 |
#define GEN6_PREFILTER_NEVER 0x1 |
#define GEN6_PREFILTER_LESS 0x2 |
#define GEN6_PREFILTER_EQUAL 0x3 |
#define GEN6_PREFILTER_LEQUAL 0x4 |
#define GEN6_PREFILTER_GREATER 0x5 |
#define GEN6_PREFILTER_NOTEQUAL 0x6 |
#define GEN6_PREFILTER_GEQUAL 0x7 |
#define GEN6_PROVOKING_VERTEX_0 0 |
#define GEN6_PROVOKING_VERTEX_1 1 |
#define GEN6_PROVOKING_VERTEX_2 2 |
#define GEN6_RASTRULE_UPPER_LEFT 0 |
#define GEN6_RASTRULE_UPPER_RIGHT 1 |
#define GEN6_RENDERTARGET_CLAMPRANGE_UNORM 0 |
#define GEN6_RENDERTARGET_CLAMPRANGE_SNORM 1 |
#define GEN6_RENDERTARGET_CLAMPRANGE_FORMAT 2 |
#define GEN6_STENCILOP_KEEP 0 |
#define GEN6_STENCILOP_ZERO 1 |
#define GEN6_STENCILOP_REPLACE 2 |
#define GEN6_STENCILOP_INCRSAT 3 |
#define GEN6_STENCILOP_DECRSAT 4 |
#define GEN6_STENCILOP_INCR 5 |
#define GEN6_STENCILOP_DECR 6 |
#define GEN6_STENCILOP_INVERT 7 |
#define GEN6_SURFACE_MIPMAPLAYOUT_BELOW 0 |
#define GEN6_SURFACE_MIPMAPLAYOUT_RIGHT 1 |
#define GEN6_SURFACEFORMAT_R32G32B32A32_FLOAT 0x000 |
#define GEN6_SURFACEFORMAT_R32G32B32A32_SINT 0x001 |
#define GEN6_SURFACEFORMAT_R32G32B32A32_UINT 0x002 |
#define GEN6_SURFACEFORMAT_R32G32B32A32_UNORM 0x003 |
#define GEN6_SURFACEFORMAT_R32G32B32A32_SNORM 0x004 |
#define GEN6_SURFACEFORMAT_R64G64_FLOAT 0x005 |
#define GEN6_SURFACEFORMAT_R32G32B32X32_FLOAT 0x006 |
#define GEN6_SURFACEFORMAT_R32G32B32A32_SSCALED 0x007 |
#define GEN6_SURFACEFORMAT_R32G32B32A32_USCALED 0x008 |
#define GEN6_SURFACEFORMAT_R32G32B32_FLOAT 0x040 |
#define GEN6_SURFACEFORMAT_R32G32B32_SINT 0x041 |
#define GEN6_SURFACEFORMAT_R32G32B32_UINT 0x042 |
#define GEN6_SURFACEFORMAT_R32G32B32_UNORM 0x043 |
#define GEN6_SURFACEFORMAT_R32G32B32_SNORM 0x044 |
#define GEN6_SURFACEFORMAT_R32G32B32_SSCALED 0x045 |
#define GEN6_SURFACEFORMAT_R32G32B32_USCALED 0x046 |
#define GEN6_SURFACEFORMAT_R16G16B16A16_UNORM 0x080 |
#define GEN6_SURFACEFORMAT_R16G16B16A16_SNORM 0x081 |
#define GEN6_SURFACEFORMAT_R16G16B16A16_SINT 0x082 |
#define GEN6_SURFACEFORMAT_R16G16B16A16_UINT 0x083 |
#define GEN6_SURFACEFORMAT_R16G16B16A16_FLOAT 0x084 |
#define GEN6_SURFACEFORMAT_R32G32_FLOAT 0x085 |
#define GEN6_SURFACEFORMAT_R32G32_SINT 0x086 |
#define GEN6_SURFACEFORMAT_R32G32_UINT 0x087 |
#define GEN6_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS 0x088 |
#define GEN6_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT 0x089 |
#define GEN6_SURFACEFORMAT_L32A32_FLOAT 0x08A |
#define GEN6_SURFACEFORMAT_R32G32_UNORM 0x08B |
#define GEN6_SURFACEFORMAT_R32G32_SNORM 0x08C |
#define GEN6_SURFACEFORMAT_R64_FLOAT 0x08D |
#define GEN6_SURFACEFORMAT_R16G16B16X16_UNORM 0x08E |
#define GEN6_SURFACEFORMAT_R16G16B16X16_FLOAT 0x08F |
#define GEN6_SURFACEFORMAT_A32X32_FLOAT 0x090 |
#define GEN6_SURFACEFORMAT_L32X32_FLOAT 0x091 |
#define GEN6_SURFACEFORMAT_I32X32_FLOAT 0x092 |
#define GEN6_SURFACEFORMAT_R16G16B16A16_SSCALED 0x093 |
#define GEN6_SURFACEFORMAT_R16G16B16A16_USCALED 0x094 |
#define GEN6_SURFACEFORMAT_R32G32_SSCALED 0x095 |
#define GEN6_SURFACEFORMAT_R32G32_USCALED 0x096 |
#define GEN6_SURFACEFORMAT_B8G8R8A8_UNORM 0x0C0 |
#define GEN6_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB 0x0C1 |
#define GEN6_SURFACEFORMAT_R10G10B10A2_UNORM 0x0C2 |
#define GEN6_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB 0x0C3 |
#define GEN6_SURFACEFORMAT_R10G10B10A2_UINT 0x0C4 |
#define GEN6_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM 0x0C5 |
#define GEN6_SURFACEFORMAT_R8G8B8A8_UNORM 0x0C7 |
#define GEN6_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB 0x0C8 |
#define GEN6_SURFACEFORMAT_R8G8B8A8_SNORM 0x0C9 |
#define GEN6_SURFACEFORMAT_R8G8B8A8_SINT 0x0CA |
#define GEN6_SURFACEFORMAT_R8G8B8A8_UINT 0x0CB |
#define GEN6_SURFACEFORMAT_R16G16_UNORM 0x0CC |
#define GEN6_SURFACEFORMAT_R16G16_SNORM 0x0CD |
#define GEN6_SURFACEFORMAT_R16G16_SINT 0x0CE |
#define GEN6_SURFACEFORMAT_R16G16_UINT 0x0CF |
#define GEN6_SURFACEFORMAT_R16G16_FLOAT 0x0D0 |
#define GEN6_SURFACEFORMAT_B10G10R10A2_UNORM 0x0D1 |
#define GEN6_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB 0x0D2 |
#define GEN6_SURFACEFORMAT_R11G11B10_FLOAT 0x0D3 |
#define GEN6_SURFACEFORMAT_R32_SINT 0x0D6 |
#define GEN6_SURFACEFORMAT_R32_UINT 0x0D7 |
#define GEN6_SURFACEFORMAT_R32_FLOAT 0x0D8 |
#define GEN6_SURFACEFORMAT_R24_UNORM_X8_TYPELESS 0x0D9 |
#define GEN6_SURFACEFORMAT_X24_TYPELESS_G8_UINT 0x0DA |
#define GEN6_SURFACEFORMAT_L16A16_UNORM 0x0DF |
#define GEN6_SURFACEFORMAT_I24X8_UNORM 0x0E0 |
#define GEN6_SURFACEFORMAT_L24X8_UNORM 0x0E1 |
#define GEN6_SURFACEFORMAT_A24X8_UNORM 0x0E2 |
#define GEN6_SURFACEFORMAT_I32_FLOAT 0x0E3 |
#define GEN6_SURFACEFORMAT_L32_FLOAT 0x0E4 |
#define GEN6_SURFACEFORMAT_A32_FLOAT 0x0E5 |
#define GEN6_SURFACEFORMAT_B8G8R8X8_UNORM 0x0E9 |
#define GEN6_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB 0x0EA |
#define GEN6_SURFACEFORMAT_R8G8B8X8_UNORM 0x0EB |
#define GEN6_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB 0x0EC |
#define GEN6_SURFACEFORMAT_R9G9B9E5_SHAREDEXP 0x0ED |
#define GEN6_SURFACEFORMAT_B10G10R10X2_UNORM 0x0EE |
#define GEN6_SURFACEFORMAT_L16A16_FLOAT 0x0F0 |
#define GEN6_SURFACEFORMAT_R32_UNORM 0x0F1 |
#define GEN6_SURFACEFORMAT_R32_SNORM 0x0F2 |
#define GEN6_SURFACEFORMAT_R10G10B10X2_USCALED 0x0F3 |
#define GEN6_SURFACEFORMAT_R8G8B8A8_SSCALED 0x0F4 |
#define GEN6_SURFACEFORMAT_R8G8B8A8_USCALED 0x0F5 |
#define GEN6_SURFACEFORMAT_R16G16_SSCALED 0x0F6 |
#define GEN6_SURFACEFORMAT_R16G16_USCALED 0x0F7 |
#define GEN6_SURFACEFORMAT_R32_SSCALED 0x0F8 |
#define GEN6_SURFACEFORMAT_R32_USCALED 0x0F9 |
#define GEN6_SURFACEFORMAT_B5G6R5_UNORM 0x100 |
#define GEN6_SURFACEFORMAT_B5G6R5_UNORM_SRGB 0x101 |
#define GEN6_SURFACEFORMAT_B5G5R5A1_UNORM 0x102 |
#define GEN6_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB 0x103 |
#define GEN6_SURFACEFORMAT_B4G4R4A4_UNORM 0x104 |
#define GEN6_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB 0x105 |
#define GEN6_SURFACEFORMAT_R8G8_UNORM 0x106 |
#define GEN6_SURFACEFORMAT_R8G8_SNORM 0x107 |
#define GEN6_SURFACEFORMAT_R8G8_SINT 0x108 |
#define GEN6_SURFACEFORMAT_R8G8_UINT 0x109 |
#define GEN6_SURFACEFORMAT_R16_UNORM 0x10A |
#define GEN6_SURFACEFORMAT_R16_SNORM 0x10B |
#define GEN6_SURFACEFORMAT_R16_SINT 0x10C |
#define GEN6_SURFACEFORMAT_R16_UINT 0x10D |
#define GEN6_SURFACEFORMAT_R16_FLOAT 0x10E |
#define GEN6_SURFACEFORMAT_I16_UNORM 0x111 |
#define GEN6_SURFACEFORMAT_L16_UNORM 0x112 |
#define GEN6_SURFACEFORMAT_A16_UNORM 0x113 |
#define GEN6_SURFACEFORMAT_L8A8_UNORM 0x114 |
#define GEN6_SURFACEFORMAT_I16_FLOAT 0x115 |
#define GEN6_SURFACEFORMAT_L16_FLOAT 0x116 |
#define GEN6_SURFACEFORMAT_A16_FLOAT 0x117 |
#define GEN6_SURFACEFORMAT_R5G5_SNORM_B6_UNORM 0x119 |
#define GEN6_SURFACEFORMAT_B5G5R5X1_UNORM 0x11A |
#define GEN6_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB 0x11B |
#define GEN6_SURFACEFORMAT_R8G8_SSCALED 0x11C |
#define GEN6_SURFACEFORMAT_R8G8_USCALED 0x11D |
#define GEN6_SURFACEFORMAT_R16_SSCALED 0x11E |
#define GEN6_SURFACEFORMAT_R16_USCALED 0x11F |
#define GEN6_SURFACEFORMAT_R8_UNORM 0x140 |
#define GEN6_SURFACEFORMAT_R8_SNORM 0x141 |
#define GEN6_SURFACEFORMAT_R8_SINT 0x142 |
#define GEN6_SURFACEFORMAT_R8_UINT 0x143 |
#define GEN6_SURFACEFORMAT_A8_UNORM 0x144 |
#define GEN6_SURFACEFORMAT_I8_UNORM 0x145 |
#define GEN6_SURFACEFORMAT_L8_UNORM 0x146 |
#define GEN6_SURFACEFORMAT_P4A4_UNORM 0x147 |
#define GEN6_SURFACEFORMAT_A4P4_UNORM 0x148 |
#define GEN6_SURFACEFORMAT_R8_SSCALED 0x149 |
#define GEN6_SURFACEFORMAT_R8_USCALED 0x14A |
#define GEN6_SURFACEFORMAT_R1_UINT 0x181 |
#define GEN6_SURFACEFORMAT_YCRCB_NORMAL 0x182 |
#define GEN6_SURFACEFORMAT_YCRCB_SWAPUVY 0x183 |
#define GEN6_SURFACEFORMAT_BC1_UNORM 0x186 |
#define GEN6_SURFACEFORMAT_BC2_UNORM 0x187 |
#define GEN6_SURFACEFORMAT_BC3_UNORM 0x188 |
#define GEN6_SURFACEFORMAT_BC4_UNORM 0x189 |
#define GEN6_SURFACEFORMAT_BC5_UNORM 0x18A |
#define GEN6_SURFACEFORMAT_BC1_UNORM_SRGB 0x18B |
#define GEN6_SURFACEFORMAT_BC2_UNORM_SRGB 0x18C |
#define GEN6_SURFACEFORMAT_BC3_UNORM_SRGB 0x18D |
#define GEN6_SURFACEFORMAT_MONO8 0x18E |
#define GEN6_SURFACEFORMAT_YCRCB_SWAPUV 0x18F |
#define GEN6_SURFACEFORMAT_YCRCB_SWAPY 0x190 |
#define GEN6_SURFACEFORMAT_DXT1_RGB 0x191 |
#define GEN6_SURFACEFORMAT_FXT1 0x192 |
#define GEN6_SURFACEFORMAT_R8G8B8_UNORM 0x193 |
#define GEN6_SURFACEFORMAT_R8G8B8_SNORM 0x194 |
#define GEN6_SURFACEFORMAT_R8G8B8_SSCALED 0x195 |
#define GEN6_SURFACEFORMAT_R8G8B8_USCALED 0x196 |
#define GEN6_SURFACEFORMAT_R64G64B64A64_FLOAT 0x197 |
#define GEN6_SURFACEFORMAT_R64G64B64_FLOAT 0x198 |
#define GEN6_SURFACEFORMAT_BC4_SNORM 0x199 |
#define GEN6_SURFACEFORMAT_BC5_SNORM 0x19A |
#define GEN6_SURFACEFORMAT_R16G16B16_UNORM 0x19C |
#define GEN6_SURFACEFORMAT_R16G16B16_SNORM 0x19D |
#define GEN6_SURFACEFORMAT_R16G16B16_SSCALED 0x19E |
#define GEN6_SURFACEFORMAT_R16G16B16_USCALED 0x19F |
#define GEN6_SURFACERETURNFORMAT_FLOAT32 0 |
#define GEN6_SURFACERETURNFORMAT_S1 1 |
#define GEN6_SURFACE_1D 0 |
#define GEN6_SURFACE_2D 1 |
#define GEN6_SURFACE_3D 2 |
#define GEN6_SURFACE_CUBE 3 |
#define GEN6_SURFACE_BUFFER 4 |
#define GEN6_SURFACE_NULL 7 |
#define GEN6_BORDER_COLOR_MODE_DEFAULT 0 |
#define GEN6_BORDER_COLOR_MODE_LEGACY 1 |
#define GEN6_TEXCOORDMODE_WRAP 0 |
#define GEN6_TEXCOORDMODE_MIRROR 1 |
#define GEN6_TEXCOORDMODE_CLAMP 2 |
#define GEN6_TEXCOORDMODE_CUBE 3 |
#define GEN6_TEXCOORDMODE_CLAMP_BORDER 4 |
#define GEN6_TEXCOORDMODE_MIRROR_ONCE 5 |
#define GEN6_THREAD_PRIORITY_NORMAL 0 |
#define GEN6_THREAD_PRIORITY_HIGH 1 |
#define GEN6_TILEWALK_XMAJOR 0 |
#define GEN6_TILEWALK_YMAJOR 1 |
#define GEN6_VERTEX_SUBPIXEL_PRECISION_8BITS 0 |
#define GEN6_VERTEX_SUBPIXEL_PRECISION_4BITS 1 |
#define GEN6_VERTEXBUFFER_ACCESS_VERTEXDATA 0 |
#define GEN6_VERTEXBUFFER_ACCESS_INSTANCEDATA 1 |
#define GEN6_VFCOMPONENT_NOSTORE 0 |
#define GEN6_VFCOMPONENT_STORE_SRC 1 |
#define GEN6_VFCOMPONENT_STORE_0 2 |
#define GEN6_VFCOMPONENT_STORE_1_FLT 3 |
#define GEN6_VFCOMPONENT_STORE_1_INT 4 |
#define GEN6_VFCOMPONENT_STORE_VID 5 |
#define GEN6_VFCOMPONENT_STORE_IID 6 |
#define GEN6_VFCOMPONENT_STORE_PID 7 |
/* Execution Unit (EU) defines |
*/ |
#define GEN6_ALIGN_1 0 |
#define GEN6_ALIGN_16 1 |
#define GEN6_ADDRESS_DIRECT 0 |
#define GEN6_ADDRESS_REGISTER_INDIRECT_REGISTER 1 |
#define GEN6_CHANNEL_X 0 |
#define GEN6_CHANNEL_Y 1 |
#define GEN6_CHANNEL_Z 2 |
#define GEN6_CHANNEL_W 3 |
#define GEN6_COMPRESSION_NONE 0 |
#define GEN6_COMPRESSION_2NDHALF 1 |
#define GEN6_COMPRESSION_COMPRESSED 2 |
#define GEN6_CONDITIONAL_NONE 0 |
#define GEN6_CONDITIONAL_Z 1 |
#define GEN6_CONDITIONAL_NZ 2 |
#define GEN6_CONDITIONAL_EQ 1 /* Z */ |
#define GEN6_CONDITIONAL_NEQ 2 /* NZ */ |
#define GEN6_CONDITIONAL_G 3 |
#define GEN6_CONDITIONAL_GE 4 |
#define GEN6_CONDITIONAL_L 5 |
#define GEN6_CONDITIONAL_LE 6 |
#define GEN6_CONDITIONAL_C 7 |
#define GEN6_CONDITIONAL_O 8 |
#define GEN6_DEBUG_NONE 0 |
#define GEN6_DEBUG_BREAKPOINT 1 |
#define GEN6_DEPENDENCY_NORMAL 0 |
#define GEN6_DEPENDENCY_NOTCLEARED 1 |
#define GEN6_DEPENDENCY_NOTCHECKED 2 |
#define GEN6_DEPENDENCY_DISABLE 3 |
#define GEN6_EXECUTE_1 0 |
#define GEN6_EXECUTE_2 1 |
#define GEN6_EXECUTE_4 2 |
#define GEN6_EXECUTE_8 3 |
#define GEN6_EXECUTE_16 4 |
#define GEN6_EXECUTE_32 5 |
#define GEN6_HORIZONTAL_STRIDE_0 0 |
#define GEN6_HORIZONTAL_STRIDE_1 1 |
#define GEN6_HORIZONTAL_STRIDE_2 2 |
#define GEN6_HORIZONTAL_STRIDE_4 3 |
#define GEN6_INSTRUCTION_NORMAL 0 |
#define GEN6_INSTRUCTION_SATURATE 1 |
#define GEN6_MASK_ENABLE 0 |
#define GEN6_MASK_DISABLE 1 |
#define GEN6_OPCODE_MOV 1 |
#define GEN6_OPCODE_SEL 2 |
#define GEN6_OPCODE_NOT 4 |
#define GEN6_OPCODE_AND 5 |
#define GEN6_OPCODE_OR 6 |
#define GEN6_OPCODE_XOR 7 |
#define GEN6_OPCODE_SHR 8 |
#define GEN6_OPCODE_SHL 9 |
#define GEN6_OPCODE_RSR 10 |
#define GEN6_OPCODE_RSL 11 |
#define GEN6_OPCODE_ASR 12 |
#define GEN6_OPCODE_CMP 16 |
#define GEN6_OPCODE_JMPI 32 |
#define GEN6_OPCODE_IF 34 |
#define GEN6_OPCODE_IFF 35 |
#define GEN6_OPCODE_ELSE 36 |
#define GEN6_OPCODE_ENDIF 37 |
#define GEN6_OPCODE_DO 38 |
#define GEN6_OPCODE_WHILE 39 |
#define GEN6_OPCODE_BREAK 40 |
#define GEN6_OPCODE_CONTINUE 41 |
#define GEN6_OPCODE_HALT 42 |
#define GEN6_OPCODE_MSAVE 44 |
#define GEN6_OPCODE_MRESTORE 45 |
#define GEN6_OPCODE_PUSH 46 |
#define GEN6_OPCODE_POP 47 |
#define GEN6_OPCODE_WAIT 48 |
#define GEN6_OPCODE_SEND 49 |
#define GEN6_OPCODE_ADD 64 |
#define GEN6_OPCODE_MUL 65 |
#define GEN6_OPCODE_AVG 66 |
#define GEN6_OPCODE_FRC 67 |
#define GEN6_OPCODE_RNDU 68 |
#define GEN6_OPCODE_RNDD 69 |
#define GEN6_OPCODE_RNDE 70 |
#define GEN6_OPCODE_RNDZ 71 |
#define GEN6_OPCODE_MAC 72 |
#define GEN6_OPCODE_MACH 73 |
#define GEN6_OPCODE_LZD 74 |
#define GEN6_OPCODE_SAD2 80 |
#define GEN6_OPCODE_SADA2 81 |
#define GEN6_OPCODE_DP4 84 |
#define GEN6_OPCODE_DPH 85 |
#define GEN6_OPCODE_DP3 86 |
#define GEN6_OPCODE_DP2 87 |
#define GEN6_OPCODE_DPA2 88 |
#define GEN6_OPCODE_LINE 89 |
#define GEN6_OPCODE_NOP 126 |
#define GEN6_PREDICATE_NONE 0 |
#define GEN6_PREDICATE_NORMAL 1 |
#define GEN6_PREDICATE_ALIGN1_ANYV 2 |
#define GEN6_PREDICATE_ALIGN1_ALLV 3 |
#define GEN6_PREDICATE_ALIGN1_ANY2H 4 |
#define GEN6_PREDICATE_ALIGN1_ALL2H 5 |
#define GEN6_PREDICATE_ALIGN1_ANY4H 6 |
#define GEN6_PREDICATE_ALIGN1_ALL4H 7 |
#define GEN6_PREDICATE_ALIGN1_ANY8H 8 |
#define GEN6_PREDICATE_ALIGN1_ALL8H 9 |
#define GEN6_PREDICATE_ALIGN1_ANY16H 10 |
#define GEN6_PREDICATE_ALIGN1_ALL16H 11 |
#define GEN6_PREDICATE_ALIGN16_REPLICATE_X 2 |
#define GEN6_PREDICATE_ALIGN16_REPLICATE_Y 3 |
#define GEN6_PREDICATE_ALIGN16_REPLICATE_Z 4 |
#define GEN6_PREDICATE_ALIGN16_REPLICATE_W 5 |
#define GEN6_PREDICATE_ALIGN16_ANY4H 6 |
#define GEN6_PREDICATE_ALIGN16_ALL4H 7 |
#define GEN6_ARCHITECTURE_REGISTER_FILE 0 |
#define GEN6_GENERAL_REGISTER_FILE 1 |
#define GEN6_MESSAGE_REGISTER_FILE 2 |
#define GEN6_IMMEDIATE_VALUE 3 |
#define GEN6_REGISTER_TYPE_UD 0 |
#define GEN6_REGISTER_TYPE_D 1 |
#define GEN6_REGISTER_TYPE_UW 2 |
#define GEN6_REGISTER_TYPE_W 3 |
#define GEN6_REGISTER_TYPE_UB 4 |
#define GEN6_REGISTER_TYPE_B 5 |
#define GEN6_REGISTER_TYPE_VF 5 /* packed float vector, immediates only? */ |
#define GEN6_REGISTER_TYPE_HF 6 |
#define GEN6_REGISTER_TYPE_V 6 /* packed int vector, immediates only, uword dest only */ |
#define GEN6_REGISTER_TYPE_F 7 |
#define GEN6_ARF_NULL 0x00 |
#define GEN6_ARF_ADDRESS 0x10 |
#define GEN6_ARF_ACCUMULATOR 0x20 |
#define GEN6_ARF_FLAG 0x30 |
#define GEN6_ARF_MASK 0x40 |
#define GEN6_ARF_MASK_STACK 0x50 |
#define GEN6_ARF_MASK_STACK_DEPTH 0x60 |
#define GEN6_ARF_STATE 0x70 |
#define GEN6_ARF_CONTROL 0x80 |
#define GEN6_ARF_NOTIFICATION_COUNT 0x90 |
#define GEN6_ARF_IP 0xA0 |
#define GEN6_AMASK 0 |
#define GEN6_IMASK 1 |
#define GEN6_LMASK 2 |
#define GEN6_CMASK 3 |
#define GEN6_THREAD_NORMAL 0 |
#define GEN6_THREAD_ATOMIC 1 |
#define GEN6_THREAD_SWITCH 2 |
#define GEN6_VERTICAL_STRIDE_0 0 |
#define GEN6_VERTICAL_STRIDE_1 1 |
#define GEN6_VERTICAL_STRIDE_2 2 |
#define GEN6_VERTICAL_STRIDE_4 3 |
#define GEN6_VERTICAL_STRIDE_8 4 |
#define GEN6_VERTICAL_STRIDE_16 5 |
#define GEN6_VERTICAL_STRIDE_32 6 |
#define GEN6_VERTICAL_STRIDE_64 7 |
#define GEN6_VERTICAL_STRIDE_128 8 |
#define GEN6_VERTICAL_STRIDE_256 9 |
#define GEN6_VERTICAL_STRIDE_ONE_DIMENSIONAL 0xF |
#define GEN6_WIDTH_1 0 |
#define GEN6_WIDTH_2 1 |
#define GEN6_WIDTH_4 2 |
#define GEN6_WIDTH_8 3 |
#define GEN6_WIDTH_16 4 |
#define GEN6_STATELESS_BUFFER_BOUNDARY_1K 0 |
#define GEN6_STATELESS_BUFFER_BOUNDARY_2K 1 |
#define GEN6_STATELESS_BUFFER_BOUNDARY_4K 2 |
#define GEN6_STATELESS_BUFFER_BOUNDARY_8K 3 |
#define GEN6_STATELESS_BUFFER_BOUNDARY_16K 4 |
#define GEN6_STATELESS_BUFFER_BOUNDARY_32K 5 |
#define GEN6_STATELESS_BUFFER_BOUNDARY_64K 6 |
#define GEN6_STATELESS_BUFFER_BOUNDARY_128K 7 |
#define GEN6_STATELESS_BUFFER_BOUNDARY_256K 8 |
#define GEN6_STATELESS_BUFFER_BOUNDARY_512K 9 |
#define GEN6_STATELESS_BUFFER_BOUNDARY_1M 10 |
#define GEN6_STATELESS_BUFFER_BOUNDARY_2M 11 |
#define GEN6_POLYGON_FACING_FRONT 0 |
#define GEN6_POLYGON_FACING_BACK 1 |
#define GEN6_MESSAGE_TARGET_NULL 0 |
#define GEN6_MESSAGE_TARGET_MATH 1 |
#define GEN6_MESSAGE_TARGET_SAMPLER 2 |
#define GEN6_MESSAGE_TARGET_GATEWAY 3 |
#define GEN6_MESSAGE_TARGET_DATAPORT_READ 4 |
#define GEN6_MESSAGE_TARGET_DATAPORT_WRITE 5 |
#define GEN6_MESSAGE_TARGET_URB 6 |
#define GEN6_MESSAGE_TARGET_THREAD_SPAWNER 7 |
#define GEN6_SAMPLER_RETURN_FORMAT_FLOAT32 0 |
#define GEN6_SAMPLER_RETURN_FORMAT_UINT32 2 |
#define GEN6_SAMPLER_RETURN_FORMAT_SINT32 3 |
#define GEN6_SAMPLER_MESSAGE_SIMD8_SAMPLE 0 |
#define GEN6_SAMPLER_MESSAGE_SIMD16_SAMPLE 0 |
#define GEN6_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0 |
#define GEN6_SAMPLER_MESSAGE_SIMD8_KILLPIX 1 |
#define GEN6_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1 |
#define GEN6_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1 |
#define GEN6_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2 |
#define GEN6_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2 |
#define GEN6_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0 |
#define GEN6_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2 |
#define GEN6_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2 |
#define GEN6_SAMPLER_MESSAGE_SIMD8_RESINFO 2 |
#define GEN6_SAMPLER_MESSAGE_SIMD16_RESINFO 2 |
#define GEN6_SAMPLER_MESSAGE_SIMD4X2_LD 3 |
#define GEN6_SAMPLER_MESSAGE_SIMD8_LD 3 |
#define GEN6_SAMPLER_MESSAGE_SIMD16_LD 3 |
#define GEN6_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0 |
#define GEN6_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1 |
#define GEN6_DATAPORT_OWORD_BLOCK_2_OWORDS 2 |
#define GEN6_DATAPORT_OWORD_BLOCK_4_OWORDS 3 |
#define GEN6_DATAPORT_OWORD_BLOCK_8_OWORDS 4 |
#define GEN6_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0 |
#define GEN6_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2 |
#define GEN6_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2 |
#define GEN6_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3 |
#define GEN6_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0 |
#define GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1 |
#define GEN6_DATAPORT_READ_MESSAGE_DWORD_BLOCK_READ 2 |
#define GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3 |
#define GEN6_DATAPORT_READ_TARGET_DATA_CACHE 0 |
#define GEN6_DATAPORT_READ_TARGET_RENDER_CACHE 1 |
#define GEN6_DATAPORT_READ_TARGET_SAMPLER_CACHE 2 |
#define GEN6_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0 |
#define GEN6_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1 |
#define GEN6_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2 |
#define GEN6_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3 |
#define GEN6_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4 |
#define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0 |
#define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1 |
#define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_BLOCK_WRITE 2 |
#define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3 |
#define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4 |
#define GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5 |
#define GEN6_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7 |
#define GEN6_MATH_FUNCTION_INV 1 |
#define GEN6_MATH_FUNCTION_LOG 2 |
#define GEN6_MATH_FUNCTION_EXP 3 |
#define GEN6_MATH_FUNCTION_SQRT 4 |
#define GEN6_MATH_FUNCTION_RSQ 5 |
#define GEN6_MATH_FUNCTION_SIN 6 /* was 7 */ |
#define GEN6_MATH_FUNCTION_COS 7 /* was 8 */ |
#define GEN6_MATH_FUNCTION_SINCOS 8 /* was 6 */ |
#define GEN6_MATH_FUNCTION_TAN 9 |
#define GEN6_MATH_FUNCTION_POW 10 |
#define GEN6_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11 |
#define GEN6_MATH_FUNCTION_INT_DIV_QUOTIENT 12 |
#define GEN6_MATH_FUNCTION_INT_DIV_REMAINDER 13 |
#define GEN6_MATH_INTEGER_UNSIGNED 0 |
#define GEN6_MATH_INTEGER_SIGNED 1 |
#define GEN6_MATH_PRECISION_FULL 0 |
#define GEN6_MATH_PRECISION_PARTIAL 1 |
#define GEN6_MATH_SATURATE_NONE 0 |
#define GEN6_MATH_SATURATE_SATURATE 1 |
#define GEN6_MATH_DATA_VECTOR 0 |
#define GEN6_MATH_DATA_SCALAR 1 |
#define GEN6_URB_OPCODE_WRITE 0 |
#define GEN6_URB_SWIZZLE_NONE 0 |
#define GEN6_URB_SWIZZLE_INTERLEAVE 1 |
#define GEN6_URB_SWIZZLE_TRANSPOSE 2 |
#define GEN6_SCRATCH_SPACE_SIZE_1K 0 |
#define GEN6_SCRATCH_SPACE_SIZE_2K 1 |
#define GEN6_SCRATCH_SPACE_SIZE_4K 2 |
#define GEN6_SCRATCH_SPACE_SIZE_8K 3 |
#define GEN6_SCRATCH_SPACE_SIZE_16K 4 |
#define GEN6_SCRATCH_SPACE_SIZE_32K 5 |
#define GEN6_SCRATCH_SPACE_SIZE_64K 6 |
#define GEN6_SCRATCH_SPACE_SIZE_128K 7 |
#define GEN6_SCRATCH_SPACE_SIZE_256K 8 |
#define GEN6_SCRATCH_SPACE_SIZE_512K 9 |
#define GEN6_SCRATCH_SPACE_SIZE_1M 10 |
#define GEN6_SCRATCH_SPACE_SIZE_2M 11 |
/* The hardware supports two different modes for border color. The |
* default (OpenGL) mode uses floating-point color channels, while the |
* legacy mode uses 4 bytes. |
* |
* More significantly, the legacy mode respects the components of the |
* border color for channels not present in the source, (whereas the |
* default mode will ignore the border color's alpha channel and use |
* alpha==1 for an RGB source, for example). |
* |
* The legacy mode matches the semantics specified by the Render |
* extension. |
*/ |
struct gen6_sampler_default_border_color { |
float color[4]; |
}; |
struct gen6_sampler_legacy_border_color { |
uint8_t color[4]; |
}; |
struct gen6_sampler_state { |
struct { |
uint32_t shadow_function:3; |
uint32_t lod_bias:11; |
uint32_t min_filter:3; |
uint32_t mag_filter:3; |
uint32_t mip_filter:2; |
uint32_t base_level:5; |
uint32_t pad:1; |
uint32_t lod_preclamp:1; |
uint32_t border_color_mode:1; |
uint32_t pad0:1; |
uint32_t disable:1; |
} ss0; |
struct { |
uint32_t r_wrap_mode:3; |
uint32_t t_wrap_mode:3; |
uint32_t s_wrap_mode:3; |
uint32_t pad:3; |
uint32_t max_lod:10; |
uint32_t min_lod:10; |
} ss1; |
struct { |
uint32_t border_color; |
} ss2; |
struct { |
uint32_t pad:19; |
uint32_t max_aniso:3; |
uint32_t chroma_key_mode:1; |
uint32_t chroma_key_index:2; |
uint32_t chroma_key_enable:1; |
uint32_t monochrome_filter_width:3; |
uint32_t monochrome_filter_height:3; |
} ss3; |
}; |
struct gen6_blend_state { |
struct { |
uint32_t dest_blend_factor:5; |
uint32_t source_blend_factor:5; |
uint32_t pad3:1; |
uint32_t blend_func:3; |
uint32_t pad2:1; |
uint32_t ia_dest_blend_factor:5; |
uint32_t ia_source_blend_factor:5; |
uint32_t pad1:1; |
uint32_t ia_blend_func:3; |
uint32_t pad0:1; |
uint32_t ia_blend_enable:1; |
uint32_t blend_enable:1; |
} blend0; |
struct { |
uint32_t post_blend_clamp_enable:1; |
uint32_t pre_blend_clamp_enable:1; |
uint32_t clamp_range:2; |
uint32_t pad0:4; |
uint32_t x_dither_offset:2; |
uint32_t y_dither_offset:2; |
uint32_t dither_enable:1; |
uint32_t alpha_test_func:3; |
uint32_t alpha_test_enable:1; |
uint32_t pad1:1; |
uint32_t logic_op_func:4; |
uint32_t logic_op_enable:1; |
uint32_t pad2:1; |
uint32_t write_disable_b:1; |
uint32_t write_disable_g:1; |
uint32_t write_disable_r:1; |
uint32_t write_disable_a:1; |
uint32_t pad3:1; |
uint32_t alpha_to_coverage_dither:1; |
uint32_t alpha_to_one:1; |
uint32_t alpha_to_coverage:1; |
} blend1; |
}; |
struct gen6_color_calc_state { |
struct { |
uint32_t alpha_test_format:1; |
uint32_t pad0:14; |
uint32_t round_disable:1; |
uint32_t bf_stencil_ref:8; |
uint32_t stencil_ref:8; |
} cc0; |
union { |
float alpha_ref_f; |
struct { |
uint32_t ui:8; |
uint32_t pad0:24; |
} alpha_ref_fi; |
} cc1; |
float constant_r; |
float constant_g; |
float constant_b; |
float constant_a; |
}; |
struct gen6_depth_stencil_state { |
struct { |
uint32_t pad0:3; |
uint32_t bf_stencil_pass_depth_pass_op:3; |
uint32_t bf_stencil_pass_depth_fail_op:3; |
uint32_t bf_stencil_fail_op:3; |
uint32_t bf_stencil_func:3; |
uint32_t bf_stencil_enable:1; |
uint32_t pad1:2; |
uint32_t stencil_write_enable:1; |
uint32_t stencil_pass_depth_pass_op:3; |
uint32_t stencil_pass_depth_fail_op:3; |
uint32_t stencil_fail_op:3; |
uint32_t stencil_func:3; |
uint32_t stencil_enable:1; |
} ds0; |
struct { |
uint32_t bf_stencil_write_mask:8; |
uint32_t bf_stencil_test_mask:8; |
uint32_t stencil_write_mask:8; |
uint32_t stencil_test_mask:8; |
} ds1; |
struct { |
uint32_t pad0:26; |
uint32_t depth_write_enable:1; |
uint32_t depth_test_func:3; |
uint32_t pad1:1; |
uint32_t depth_test_enable:1; |
} ds2; |
}; |
struct gen6_surface_state { |
struct { |
uint32_t cube_pos_z:1; |
uint32_t cube_neg_z:1; |
uint32_t cube_pos_y:1; |
uint32_t cube_neg_y:1; |
uint32_t cube_pos_x:1; |
uint32_t cube_neg_x:1; |
uint32_t pad:3; |
uint32_t render_cache_read_mode:1; |
uint32_t mipmap_layout_mode:1; |
uint32_t vert_line_stride_ofs:1; |
uint32_t vert_line_stride:1; |
uint32_t color_blend:1; |
uint32_t writedisable_blue:1; |
uint32_t writedisable_green:1; |
uint32_t writedisable_red:1; |
uint32_t writedisable_alpha:1; |
uint32_t surface_format:9; |
uint32_t data_return_format:1; |
uint32_t pad0:1; |
uint32_t surface_type:3; |
} ss0; |
struct { |
uint32_t base_addr; |
} ss1; |
struct { |
uint32_t render_target_rotation:2; |
uint32_t mip_count:4; |
uint32_t width:13; |
uint32_t height:13; |
} ss2; |
struct { |
uint32_t tile_walk:1; |
uint32_t tiled_surface:1; |
uint32_t pad:1; |
uint32_t pitch:18; |
uint32_t depth:11; |
} ss3; |
struct { |
uint32_t pad:19; |
uint32_t min_array_elt:9; |
uint32_t min_lod:4; |
} ss4; |
struct { |
uint32_t pad:20; |
uint32_t y_offset:4; |
uint32_t pad2:1; |
uint32_t x_offset:7; |
} ss5; |
}; |
/* Surface state DW0 */ |
#define GEN6_SURFACE_RC_READ_WRITE (1 << 8) |
#define GEN6_SURFACE_MIPLAYOUT_SHIFT 10 |
#define GEN6_SURFACE_MIPMAPLAYOUT_BELOW 0 |
#define GEN6_SURFACE_MIPMAPLAYOUT_RIGHT 1 |
#define GEN6_SURFACE_CUBEFACE_ENABLES 0x3f |
#define GEN6_SURFACE_BLEND_ENABLED (1 << 13) |
#define GEN6_SURFACE_WRITEDISABLE_B_SHIFT 14 |
#define GEN6_SURFACE_WRITEDISABLE_G_SHIFT 15 |
#define GEN6_SURFACE_WRITEDISABLE_R_SHIFT 16 |
#define GEN6_SURFACE_WRITEDISABLE_A_SHIFT 17 |
#define GEN6_SURFACE_FORMAT_SHIFT 18 |
#define GEN6_SURFACE_FORMAT_MASK INTEL_MASK(26, 18) |
#define GEN6_SURFACE_TYPE_SHIFT 29 |
#define GEN6_SURFACE_TYPE_MASK GEN6_MASK(31, 29) |
#define GEN6_SURFACE_1D 0 |
#define GEN6_SURFACE_2D 1 |
#define GEN6_SURFACE_3D 2 |
#define GEN6_SURFACE_CUBE 3 |
#define GEN6_SURFACE_BUFFER 4 |
#define GEN6_SURFACE_NULL 7 |
/* Surface state DW2 */ |
#define GEN6_SURFACE_HEIGHT_SHIFT 19 |
#define GEN6_SURFACE_HEIGHT_MASK GEN6_MASK(31, 19) |
#define GEN6_SURFACE_WIDTH_SHIFT 6 |
#define GEN6_SURFACE_WIDTH_MASK GEN6_MASK(18, 6) |
#define GEN6_SURFACE_LOD_SHIFT 2 |
#define GEN6_SURFACE_LOD_MASK GEN6_MASK(5, 2) |
/* Surface state DW3 */ |
#define GEN6_SURFACE_DEPTH_SHIFT 21 |
#define GEN6_SURFACE_DEPTH_MASK GEN6_MASK(31, 21) |
#define GEN6_SURFACE_PITCH_SHIFT 3 |
#define GEN6_SURFACE_PITCH_MASK GEN6_MASK(19, 3) |
#define GEN6_SURFACE_TILED (1 << 1) |
#define GEN6_SURFACE_TILED_Y (1 << 0) |
/* Surface state DW4 */ |
#define GEN6_SURFACE_MIN_LOD_SHIFT 28 |
#define GEN6_SURFACE_MIN_LOD_MASK GEN6_MASK(31, 28) |
/* Surface state DW5 */ |
#define GEN6_SURFACE_X_OFFSET_SHIFT 25 |
#define GEN6_SURFACE_X_OFFSET_MASK GEN6_MASK(31, 25) |
#define GEN6_SURFACE_Y_OFFSET_SHIFT 20 |
#define GEN6_SURFACE_Y_OFFSET_MASK GEN6_MASK(23, 20) |
struct gen6_cc_viewport { |
float min_depth; |
float max_depth; |
}; |
typedef enum { |
SAMPLER_FILTER_NEAREST = 0, |
SAMPLER_FILTER_BILINEAR, |
FILTER_COUNT |
} sampler_filter_t; |
typedef enum { |
SAMPLER_EXTEND_NONE = 0, |
SAMPLER_EXTEND_REPEAT, |
SAMPLER_EXTEND_PAD, |
SAMPLER_EXTEND_REFLECT, |
EXTEND_COUNT |
} sampler_extend_t; |
#endif |
/drivers/video/drm/i915/sna/kgem.c |
---|
0,0 → 1,1714 |
/* |
* Copyright (c) 2011 Intel Corporation |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
* copy of this software and associated documentation files (the "Software"), |
* to deal in the Software without restriction, including without limitation |
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
* and/or sell copies of the Software, and to permit persons to whom the |
* Software is furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice (including the next |
* paragraph) shall be included in all copies or substantial portions of the |
* Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
* SOFTWARE. |
* |
* Authors: |
* Chris Wilson <chris@chris-wilson.co.uk> |
* |
*/ |
#ifdef HAVE_CONFIG_H |
#include "config.h" |
#endif |
#include <drmP.h> |
#include <drm.h> |
#include "i915_drm.h" |
#include "i915_drv.h" |
#include "intel_drv.h" |
#include <linux/kernel.h> |
#include "../bitmap.h" |
#include "sna.h" |
//#include "sna_reg.h" |
//#include <time.h> |
//#include <errno.h> |
#define NO_CACHE 1 |
#define list_is_empty list_empty |
#define list_init INIT_LIST_HEAD |
extern struct drm_device *main_device; |
static struct kgem_bo * |
search_linear_cache(struct kgem *kgem, unsigned int num_pages, |
unsigned flags); |
#define INT16_MAX (32767) |
#define PAGE_ALIGN(x) ALIGN(x, PAGE_SIZE) |
#define NUM_PAGES(x) (((x) + PAGE_SIZE-1) / PAGE_SIZE) |
#define MAX_GTT_VMA_CACHE 512 |
#define MAX_CPU_VMA_CACHE INT16_MAX |
#define MAP_PRESERVE_TIME 10 |
#define CPU_MAP(ptr) ((void*)((uintptr_t)(ptr) & ~1)) |
#define MAKE_CPU_MAP(ptr) ((void*)((uintptr_t)(ptr) | 1)) |
struct kgem_partial_bo { |
struct kgem_bo base; |
void *mem; |
uint32_t used; |
uint32_t need_io : 1; |
uint32_t write : 2; |
uint32_t mmapped : 1; |
}; |
static struct kgem_bo *__kgem_freed_bo; |
static struct drm_i915_gem_exec_object2 _kgem_dummy_exec; |
static inline int bytes(struct kgem_bo *bo) |
{ |
return kgem_bo_size(bo); |
} |
#define bucket(B) (B)->size.pages.bucket |
#define num_pages(B) (B)->size.pages.count |
static void kgem_sna_reset(struct kgem *kgem) |
{ |
struct sna *sna = container_of(kgem, struct sna, kgem); |
sna->render.reset(sna); |
sna->blt_state.fill_bo = 0; |
} |
static void kgem_sna_flush(struct kgem *kgem) |
{ |
struct sna *sna = container_of(kgem, struct sna, kgem); |
sna->render.flush(sna); |
if (sna->render.solid_cache.dirty) |
sna_render_flush_solid(sna); |
} |
static int __gem_write(int fd, uint32_t handle, |
int offset, int length, |
const void *src) |
{ |
DBG(("%s(handle=%x, offset=%d, len=%d)\n", __FUNCTION__, |
handle, offset, length)); |
write_gem_object(handle, offset, length, src); |
return 0; |
} |
static int gem_write(int fd, uint32_t handle, |
int offset, int length, |
const void *src) |
{ |
u32 _offset; |
u32 _size; |
u8 *data_ptr; |
DBG(("%s(handle=%x, offset=%d, len=%d)\n", __FUNCTION__, |
handle, offset, length)); |
/* align the transfer to cachelines; fortuitously this is safe! */ |
if ((offset | length) & 63) { |
_offset = offset & ~63; |
_size = ALIGN(offset+length, 64) - _offset; |
data_ptr = (u8*)src + _offset - offset; |
} else { |
_offset = offset; |
_size = length; |
data_ptr = (u8*)src; |
} |
write_gem_object(handle, _offset, _size, data_ptr); |
return 0; |
} |
static void kgem_bo_retire(struct kgem *kgem, struct kgem_bo *bo) |
{ |
DBG(("%s: handle=%x, domain=%d\n", |
__FUNCTION__, bo->handle, bo->domain)); |
assert(!kgem_busy(kgem, bo->handle)); |
if (bo->domain == DOMAIN_GPU) |
kgem_retire(kgem); |
if (bo->exec == NULL) { |
DBG(("%s: retiring bo handle=%x (needed flush? %d), rq? %d\n", |
__FUNCTION__, bo->handle, bo->needs_flush, bo->rq != NULL)); |
bo->rq = NULL; |
list_del(&bo->request); |
bo->needs_flush = bo->flush; |
} |
} |
Bool kgem_bo_write(struct kgem *kgem, struct kgem_bo *bo, |
const void *data, int length) |
{ |
assert(bo->refcnt); |
assert(!bo->purged); |
assert(!kgem_busy(kgem, bo->handle)); |
assert(length <= bytes(bo)); |
if (gem_write(kgem->fd, bo->handle, 0, length, data)) |
return FALSE; |
DBG(("%s: flush=%d, domain=%d\n", __FUNCTION__, bo->flush, bo->domain)); |
kgem_bo_retire(kgem, bo); |
bo->domain = DOMAIN_NONE; |
return TRUE; |
} |
static uint32_t gem_create(int fd, int num_pages) |
{ |
struct drm_i915_gem_object *obj; |
int ret; |
/* Allocate the new object */ |
obj = i915_gem_alloc_object(main_device, |
PAGE_SIZE * num_pages); |
if (obj == NULL) |
goto err1; |
ret = i915_gem_object_pin(obj, 4096, true); |
if (ret) |
goto err2; |
return (uint32_t)obj; |
err2: |
drm_gem_object_unreference(&obj->base); |
err1: |
return 0; |
} |
static bool |
kgem_bo_set_purgeable(struct kgem *kgem, struct kgem_bo *bo) |
{ |
return true; |
} |
static bool |
kgem_bo_clear_purgeable(struct kgem *kgem, struct kgem_bo *bo) |
{ |
return true; |
} |
static void gem_close(int fd, uint32_t handle) |
{ |
destroy_gem_object(handle); |
} |
/* |
constant inline static unsigned long __fls(unsigned long word) |
{ |
asm("bsr %1,%0" |
: "=r" (word) |
: "rm" (word)); |
return word; |
} |
*/ |
constant inline static int cache_bucket(int num_pages) |
{ |
return __fls(num_pages); |
} |
static struct kgem_bo *__kgem_bo_init(struct kgem_bo *bo, |
int handle, int num_pages) |
{ |
assert(num_pages); |
memset(bo, 0, sizeof(*bo)); |
bo->refcnt = 1; |
bo->handle = handle; |
num_pages(bo) = num_pages; |
bucket(bo) = cache_bucket(num_pages); |
bo->reusable = true; |
bo->domain = DOMAIN_CPU; |
list_init(&bo->request); |
list_init(&bo->list); |
list_init(&bo->vma); |
return bo; |
} |
static struct kgem_bo *__kgem_bo_alloc(int handle, int num_pages) |
{ |
struct kgem_bo *bo; |
if (__kgem_freed_bo) { |
bo = __kgem_freed_bo; |
__kgem_freed_bo = *(struct kgem_bo **)bo; |
} else { |
bo = malloc(sizeof(*bo)); |
if (bo == NULL) |
return NULL; |
} |
return __kgem_bo_init(bo, handle, num_pages); |
} |
static struct kgem_request _kgem_static_request; |
static struct kgem_request *__kgem_request_alloc(void) |
{ |
struct kgem_request *rq; |
rq = malloc(sizeof(*rq)); |
if (rq == NULL) |
rq = &_kgem_static_request; |
list_init(&rq->buffers); |
return rq; |
} |
static struct list_head *inactive(struct kgem *kgem, int num_pages) |
{ |
return &kgem->inactive[cache_bucket(num_pages)]; |
} |
static struct list_head *active(struct kgem *kgem, int num_pages, int tiling) |
{ |
return &kgem->active[cache_bucket(num_pages)][tiling]; |
} |
void kgem_init(struct kgem *kgem, int gen) |
{ |
struct drm_i915_gem_get_aperture aperture; |
struct drm_i915_gem_object *obj; |
size_t totalram; |
unsigned int i, j; |
int ret; |
memset(kgem, 0, sizeof(*kgem)); |
kgem->gen = gen; |
kgem->wedged = 0; |
// kgem->wedged |= DBG_NO_HW; |
obj = i915_gem_alloc_object(main_device, 4096*4); |
if (obj == NULL) |
goto err2; |
ret = i915_gem_object_pin(obj, 4096, true); |
if (ret) |
goto err3; |
kgem->batch_ptr = drm_intel_bo_map(obj, true); |
kgem->batch = kgem->batch_ptr; |
kgem->batch_idx = 0; |
kgem->batch_obj = obj; |
kgem->max_batch_size = 1024; //ARRAY_SIZE(kgem->batch); |
kgem->half_cpu_cache_pages = (2048*1024) >> 13; |
list_init(&kgem->partial); |
list_init(&kgem->requests); |
list_init(&kgem->flushing); |
list_init(&kgem->large); |
for (i = 0; i < ARRAY_SIZE(kgem->inactive); i++) |
list_init(&kgem->inactive[i]); |
for (i = 0; i < ARRAY_SIZE(kgem->active); i++) { |
for (j = 0; j < ARRAY_SIZE(kgem->active[i]); j++) |
list_init(&kgem->active[i][j]); |
} |
for (i = 0; i < ARRAY_SIZE(kgem->vma); i++) { |
for (j = 0; j < ARRAY_SIZE(kgem->vma[i].inactive); j++) |
list_init(&kgem->vma[i].inactive[j]); |
} |
kgem->vma[MAP_GTT].count = -MAX_GTT_VMA_CACHE; |
kgem->vma[MAP_CPU].count = -MAX_CPU_VMA_CACHE; |
kgem->next_request = __kgem_request_alloc(); |
//#if defined(USE_VMAP) && defined(I915_PARAM_HAS_VMAP) |
// if (!DBG_NO_VMAP) |
// kgem->has_vmap = gem_param(kgem, I915_PARAM_HAS_VMAP) > 0; |
//#endif |
// DBG(("%s: using vmap=%d\n", __FUNCTION__, kgem->has_vmap)); |
if (gen < 40) { |
// if (!DBG_NO_RELAXED_FENCING) { |
// kgem->has_relaxed_fencing = |
// gem_param(kgem, I915_PARAM_HAS_RELAXED_FENCING) > 0; |
// } |
} else |
kgem->has_relaxed_fencing = 1; |
DBG(("%s: has relaxed fencing? %d\n", __FUNCTION__, |
kgem->has_relaxed_fencing)); |
kgem->has_llc = (gen >= 60)?true:false; |
kgem->has_cpu_bo = kgem->has_llc; |
DBG(("%s: cpu bo enabled %d: llc? %d\n", __FUNCTION__, |
kgem->has_cpu_bo, kgem->has_llc)); |
kgem->has_semaphores = false; |
// if (gen >= 60 && semaphores_enabled()) |
// kgem->has_semaphores = true; |
// DBG(("%s: semaphores enabled? %d\n", __FUNCTION__, |
// kgem->has_semaphores)); |
VG_CLEAR(aperture); |
aperture.aper_size = 64*1024*1024; |
i915_gem_get_aperture_ioctl(main_device, &aperture, NULL); |
kgem->aperture_total = aperture.aper_size; |
kgem->aperture_high = aperture.aper_size * 3/4; |
kgem->aperture_low = aperture.aper_size * 1/3; |
DBG(("%s: aperture low=%d [%d], high=%d [%d]\n", __FUNCTION__, |
kgem->aperture_low, kgem->aperture_low / (1024*1024), |
kgem->aperture_high, kgem->aperture_high / (1024*1024))); |
kgem->aperture_mappable = aperture.aper_size; |
DBG(("%s: aperture mappable=%d [%d MiB]\n", __FUNCTION__, |
kgem->aperture_mappable, kgem->aperture_mappable / (1024*1024))); |
kgem->partial_buffer_size = 64 * 1024; |
while (kgem->partial_buffer_size < kgem->aperture_mappable >> 10) |
kgem->partial_buffer_size *= 2; |
DBG(("%s: partial buffer size=%d [%d KiB]\n", __FUNCTION__, |
kgem->partial_buffer_size, kgem->partial_buffer_size / 1024)); |
kgem->min_alignment = 4; |
if (gen < 60) |
/* XXX workaround an issue where we appear to fail to |
* disable dual-stream mode */ |
kgem->min_alignment = 64; |
kgem->max_object_size = 2 * kgem->aperture_total / 3; |
kgem->max_cpu_size = kgem->max_object_size; |
kgem->max_gpu_size = kgem->max_object_size; |
if (!kgem->has_llc) |
kgem->max_gpu_size = MAX_CACHE_SIZE; |
if (gen < 40) { |
/* If we have to use fences for blitting, we have to make |
* sure we can fit them into the aperture. |
*/ |
kgem->max_gpu_size = kgem->aperture_mappable / 2; |
if (kgem->max_gpu_size > kgem->aperture_low) |
kgem->max_gpu_size = kgem->aperture_low; |
} |
if (kgem->max_gpu_size > kgem->max_cpu_size) |
kgem->max_gpu_size = kgem->max_cpu_size; |
kgem->max_upload_tile_size = kgem->aperture_mappable / 2; |
if (kgem->max_upload_tile_size > kgem->max_gpu_size / 2) |
kgem->max_upload_tile_size = kgem->max_gpu_size / 2; |
kgem->max_copy_tile_size = (MAX_CACHE_SIZE + 1)/2; |
if (kgem->max_copy_tile_size > kgem->max_gpu_size / 2) |
kgem->max_copy_tile_size = kgem->max_gpu_size / 2; |
totalram = 1024*1024; //total_ram_size(); |
if (totalram == 0) { |
DBG(("%s: total ram size unknown, assuming maximum of total aperture\n", |
__FUNCTION__)); |
totalram = kgem->aperture_total; |
} |
if (kgem->max_object_size > totalram / 2) |
kgem->max_object_size = totalram / 2; |
if (kgem->max_cpu_size > totalram / 2) |
kgem->max_cpu_size = totalram / 2; |
if (kgem->max_gpu_size > totalram / 4) |
kgem->max_gpu_size = totalram / 4; |
kgem->large_object_size = MAX_CACHE_SIZE; |
if (kgem->large_object_size > kgem->max_gpu_size) |
kgem->large_object_size = kgem->max_gpu_size; |
DBG(("%s: large object thresold=%d\n", |
__FUNCTION__, kgem->large_object_size)); |
DBG(("%s: max object size (gpu=%d, cpu=%d, tile upload=%d, copy=%d)\n", |
__FUNCTION__, |
kgem->max_gpu_size, kgem->max_cpu_size, |
kgem->max_upload_tile_size, kgem->max_copy_tile_size)); |
/* Convert the aperture thresholds to pages */ |
kgem->aperture_low /= PAGE_SIZE; |
kgem->aperture_high /= PAGE_SIZE; |
// kgem->fence_max = gem_param(kgem, I915_PARAM_NUM_FENCES_AVAIL) - 2; |
// if ((int)kgem->fence_max < 0) |
kgem->fence_max = 5; /* minimum safe value for all hw */ |
DBG(("%s: max fences=%d\n", __FUNCTION__, kgem->fence_max)); |
err3: |
err2: |
return; |
} |
static struct drm_i915_gem_exec_object2 * |
kgem_add_handle(struct kgem *kgem, struct kgem_bo *bo) |
{ |
struct drm_i915_gem_exec_object2 *exec; |
DBG(("%s: handle=%d, index=%d\n", |
__FUNCTION__, bo->handle, kgem->nexec)); |
assert(kgem->nexec < ARRAY_SIZE(kgem->exec)); |
exec = memset(&kgem->exec[kgem->nexec++], 0, sizeof(*exec)); |
exec->handle = bo->handle; |
exec->offset = bo->presumed_offset; |
kgem->aperture += num_pages(bo); |
return exec; |
} |
void _kgem_add_bo(struct kgem *kgem, struct kgem_bo *bo) |
{ |
bo->exec = kgem_add_handle(kgem, bo); |
bo->rq = kgem->next_request; |
list_move(&bo->request, &kgem->next_request->buffers); |
/* XXX is it worth working around gcc here? */ |
kgem->flush |= bo->flush; |
kgem->sync |= bo->sync; |
kgem->scanout |= bo->scanout; |
} |
static uint32_t kgem_end_batch(struct kgem *kgem) |
{ |
// kgem->context_switch(kgem, KGEM_NONE); |
kgem->batch[kgem->nbatch++] = MI_BATCH_BUFFER_END; |
if (kgem->nbatch & 1) |
kgem->batch[kgem->nbatch++] = MI_NOOP; |
return kgem->nbatch; |
} |
static void kgem_fixup_self_relocs(struct kgem *kgem, struct kgem_bo *bo) |
{ |
int n; |
for (n = 0; n < kgem->nreloc; n++) |
{ |
if (kgem->reloc[n].target_handle == 0) |
{ |
kgem->reloc[n].target_handle = bo->handle; |
kgem->reloc[n].presumed_offset = bo->presumed_offset; |
kgem->batch[kgem->reloc[n].offset/sizeof(kgem->batch[0])] = |
kgem->reloc[n].delta + bo->presumed_offset; |
dbgprintf("fixup reloc %d pos %d handle %d delta %x \n", |
n, kgem->reloc[n].offset/sizeof(kgem->batch[0]), |
bo->handle, kgem->reloc[n].delta); |
} |
} |
} |
static void kgem_bo_binding_free(struct kgem *kgem, struct kgem_bo *bo) |
{ |
struct kgem_bo_binding *b; |
b = bo->binding.next; |
while (b) { |
struct kgem_bo_binding *next = b->next; |
free (b); |
b = next; |
} |
} |
static void kgem_bo_release_map(struct kgem *kgem, struct kgem_bo *bo) |
{ |
int type = IS_CPU_MAP(bo->map); |
DBG(("%s: releasing %s vma for handle=%d, count=%d\n", |
__FUNCTION__, type ? "CPU" : "GTT", |
bo->handle, kgem->vma[type].count)); |
VG(if (type) VALGRIND_FREELIKE_BLOCK(CPU_MAP(bo->map), 0)); |
// munmap(CPU_MAP(bo->map), bytes(bo)); |
bo->map = NULL; |
if (!list_is_empty(&bo->vma)) { |
list_del(&bo->vma); |
kgem->vma[type].count--; |
} |
} |
static void kgem_bo_free(struct kgem *kgem, struct kgem_bo *bo) |
{ |
DBG(("%s: handle=%d\n", __FUNCTION__, bo->handle)); |
assert(bo->refcnt == 0); |
assert(bo->exec == NULL); |
kgem_bo_binding_free(kgem, bo); |
if (bo->map) |
kgem_bo_release_map(kgem, bo); |
assert(list_is_empty(&bo->vma)); |
list_del(&bo->list); |
list_del(&bo->request); |
gem_close(kgem->fd, bo->handle); |
if (!bo->io) { |
*(struct kgem_bo **)bo = __kgem_freed_bo; |
__kgem_freed_bo = bo; |
} else |
free(bo); |
} |
inline static void kgem_bo_move_to_inactive(struct kgem *kgem, |
struct kgem_bo *bo) |
{ |
assert(!kgem_busy(kgem, bo->handle)); |
assert(!bo->proxy); |
assert(!bo->io); |
assert(!bo->needs_flush); |
assert(bo->rq == NULL); |
assert(bo->domain != DOMAIN_GPU); |
if (bucket(bo) >= NUM_CACHE_BUCKETS) { |
kgem_bo_free(kgem, bo); |
return; |
} |
list_move(&bo->list, &kgem->inactive[bucket(bo)]); |
if (bo->map) { |
int type = IS_CPU_MAP(bo->map); |
if (bucket(bo) >= NUM_CACHE_BUCKETS || |
(!type && !kgem_bo_is_mappable(kgem, bo))) { |
list_del(&bo->vma); |
// munmap(CPU_MAP(bo->map), bytes(bo)); |
bo->map = NULL; |
} |
if (bo->map) { |
list_move(&bo->vma, &kgem->vma[type].inactive[bucket(bo)]); |
kgem->vma[type].count++; |
} |
} |
kgem->need_expire = true; |
} |
inline static void kgem_bo_remove_from_inactive(struct kgem *kgem, |
struct kgem_bo *bo) |
{ |
list_del(&bo->list); |
assert(bo->rq == NULL); |
if (bo->map) { |
assert(!list_is_empty(&bo->vma)); |
list_del(&bo->vma); |
kgem->vma[IS_CPU_MAP(bo->map)].count--; |
} |
} |
inline static void kgem_bo_remove_from_active(struct kgem *kgem, |
struct kgem_bo *bo) |
{ |
list_del(&bo->list); |
if (bo->rq == &_kgem_static_request) |
list_del(&bo->request); |
assert(list_is_empty(&bo->vma)); |
} |
static void __kgem_bo_destroy(struct kgem *kgem, struct kgem_bo *bo) |
{ |
DBG(("%s: handle=%d\n", __FUNCTION__, bo->handle)); |
assert(list_is_empty(&bo->list)); |
assert(bo->refcnt == 0); |
bo->binding.offset = 0; |
if (NO_CACHE) |
goto destroy; |
if (bo->io) { |
struct kgem_bo *base; |
base = malloc(sizeof(*base)); |
if (base) { |
DBG(("%s: transferring io handle=%d to bo\n", |
__FUNCTION__, bo->handle)); |
/* transfer the handle to a minimum bo */ |
memcpy(base, bo, sizeof (*base)); |
base->reusable = true; |
base->io = false; |
list_init(&base->list); |
list_replace(&bo->request, &base->request); |
list_replace(&bo->vma, &base->vma); |
free(bo); |
bo = base; |
} |
} |
if (!bo->reusable) { |
DBG(("%s: handle=%d, not reusable\n", |
__FUNCTION__, bo->handle)); |
goto destroy; |
} |
if (!kgem->has_llc && IS_CPU_MAP(bo->map) && bo->domain != DOMAIN_CPU) |
kgem_bo_release_map(kgem, bo); |
assert(list_is_empty(&bo->vma)); |
assert(list_is_empty(&bo->list)); |
assert(bo->vmap == false && bo->sync == false); |
assert(bo->io == false); |
bo->scanout = bo->flush = false; |
if (bo->rq) { |
struct list *cache; |
DBG(("%s: handle=%d -> active\n", __FUNCTION__, bo->handle)); |
if (bucket(bo) < NUM_CACHE_BUCKETS) |
cache = &kgem->active[bucket(bo)][bo->tiling]; |
else |
cache = &kgem->large; |
list_add(&bo->list, cache); |
return; |
} |
assert(bo->exec == NULL); |
assert(list_is_empty(&bo->request)); |
/* |
if (bo->needs_flush) { |
if ((bo->needs_flush = kgem_busy(kgem, bo->handle))) { |
struct list *cache; |
DBG(("%s: handle=%d -> flushing\n", |
__FUNCTION__, bo->handle)); |
list_add(&bo->request, &kgem->flushing); |
if (bucket(bo) < NUM_CACHE_BUCKETS) |
cache = &kgem->active[bucket(bo)][bo->tiling]; |
else |
cache = &kgem->large; |
list_add(&bo->list, cache); |
bo->rq = &_kgem_static_request; |
return; |
} |
bo->domain = DOMAIN_NONE; |
} |
*/ |
if (!IS_CPU_MAP(bo->map)) { |
if (!kgem_bo_set_purgeable(kgem, bo)) |
goto destroy; |
if (!kgem->has_llc && bo->domain == DOMAIN_CPU) |
goto destroy; |
DBG(("%s: handle=%d, purged\n", |
__FUNCTION__, bo->handle)); |
} |
DBG(("%s: handle=%d -> inactive\n", __FUNCTION__, bo->handle)); |
kgem_bo_move_to_inactive(kgem, bo); |
return; |
destroy: |
if (!bo->exec) |
kgem_bo_free(kgem, bo); |
} |
bool kgem_retire(struct kgem *kgem) |
{ |
struct kgem_bo *bo, *next; |
bool retired = false; |
DBG(("%s\n", __FUNCTION__)); |
list_for_each_entry_safe(bo, next, &kgem->flushing, request) { |
assert(bo->refcnt == 0); |
assert(bo->rq == &_kgem_static_request); |
assert(bo->exec == NULL); |
// if (kgem_busy(kgem, bo->handle)) |
// break; |
DBG(("%s: moving %d from flush to inactive\n", |
__FUNCTION__, bo->handle)); |
if (kgem_bo_set_purgeable(kgem, bo)) { |
bo->needs_flush = false; |
bo->domain = DOMAIN_NONE; |
bo->rq = NULL; |
list_del(&bo->request); |
kgem_bo_move_to_inactive(kgem, bo); |
} else |
kgem_bo_free(kgem, bo); |
retired = true; |
} |
while (!list_is_empty(&kgem->requests)) { |
struct kgem_request *rq; |
rq = list_first_entry(&kgem->requests, |
struct kgem_request, |
list); |
// if (kgem_busy(kgem, rq->bo->handle)) |
// break; |
DBG(("%s: request %d complete\n", |
__FUNCTION__, rq->bo->handle)); |
while (!list_is_empty(&rq->buffers)) { |
bo = list_first_entry(&rq->buffers, |
struct kgem_bo, |
request); |
assert(bo->rq == rq); |
assert(bo->exec == NULL); |
assert(bo->domain == DOMAIN_GPU); |
list_del(&bo->request); |
bo->rq = NULL; |
// if (bo->needs_flush) |
// bo->needs_flush = kgem_busy(kgem, bo->handle); |
if (!bo->needs_flush) |
bo->domain = DOMAIN_NONE; |
if (bo->refcnt) |
continue; |
if (!bo->reusable) { |
DBG(("%s: closing %d\n", |
__FUNCTION__, bo->handle)); |
kgem_bo_free(kgem, bo); |
continue; |
} |
if (bo->needs_flush) { |
DBG(("%s: moving %d to flushing\n", |
__FUNCTION__, bo->handle)); |
list_add(&bo->request, &kgem->flushing); |
bo->rq = &_kgem_static_request; |
} else if (kgem_bo_set_purgeable(kgem, bo)) { |
DBG(("%s: moving %d to inactive\n", |
__FUNCTION__, bo->handle)); |
kgem_bo_move_to_inactive(kgem, bo); |
retired = true; |
} else { |
DBG(("%s: closing %d\n", |
__FUNCTION__, bo->handle)); |
kgem_bo_free(kgem, bo); |
} |
} |
rq->bo->refcnt--; |
assert(rq->bo->refcnt == 0); |
assert(rq->bo->rq == NULL); |
assert(list_is_empty(&rq->bo->request)); |
if (kgem_bo_set_purgeable(kgem, rq->bo)) { |
kgem_bo_move_to_inactive(kgem, rq->bo); |
retired = true; |
} else { |
DBG(("%s: closing %d\n", |
__FUNCTION__, rq->bo->handle)); |
kgem_bo_free(kgem, rq->bo); |
} |
list_del(&rq->list); |
free(rq); |
} |
kgem->need_retire = !list_is_empty(&kgem->requests); |
DBG(("%s -- need_retire=%d\n", __FUNCTION__, kgem->need_retire)); |
kgem->retire(kgem); |
return retired; |
} |
static int kgem_batch_write(struct kgem *kgem, uint32_t handle, uint32_t size) |
{ |
int ret; |
assert(!kgem_busy(kgem, handle)); |
/* If there is no surface data, just upload the batch */ |
if (kgem->surface == kgem->max_batch_size) |
return gem_write(kgem->fd, handle, |
0, sizeof(uint32_t)*kgem->nbatch, |
kgem->batch); |
/* Are the batch pages conjoint with the surface pages? */ |
if (kgem->surface < kgem->nbatch + PAGE_SIZE/4) { |
assert(size == sizeof(kgem->batch)); |
return gem_write(kgem->fd, handle, |
0, sizeof(kgem->batch), |
kgem->batch); |
} |
/* Disjoint surface/batch, upload separately */ |
ret = gem_write(kgem->fd, handle, |
0, sizeof(uint32_t)*kgem->nbatch, |
kgem->batch); |
if (ret) |
return ret; |
assert(kgem->nbatch*sizeof(uint32_t) <= |
sizeof(uint32_t)*kgem->surface - (sizeof(kgem->batch)-size)); |
return __gem_write(kgem->fd, handle, |
sizeof(uint32_t)*kgem->surface - (sizeof(kgem->batch)-size), |
sizeof(kgem->batch) - sizeof(uint32_t)*kgem->surface, |
kgem->batch + kgem->surface); |
} |
void kgem_reset(struct kgem *kgem) |
{ |
// ENTER(); |
kgem->nfence = 0; |
kgem->nexec = 0; |
kgem->nreloc = 0; |
kgem->aperture = 0; |
kgem->aperture_fenced = 0; |
kgem->nbatch = 0; |
kgem->surface = kgem->max_batch_size; |
kgem->mode = KGEM_NONE; |
kgem->flush = 0; |
kgem->scanout = 0; |
kgem->batch = kgem->batch_ptr+1024*kgem->batch_idx; |
kgem->next_request = __kgem_request_alloc(); |
kgem_sna_reset(kgem); |
// dbgprintf("surface %x\n", kgem->surface); |
// LEAVE(); |
} |
static int compact_batch_surface(struct kgem *kgem) |
{ |
int size, shrink, n; |
/* See if we can pack the contents into one or two pages */ |
size = kgem->max_batch_size - kgem->surface + kgem->nbatch; |
if (size > 2048) |
return sizeof(kgem->batch); |
else if (size > 1024) |
size = 8192, shrink = 2*4096; |
else |
size = 4096, shrink = 3*4096; |
for (n = 0; n < kgem->nreloc; n++) { |
if (kgem->reloc[n].read_domains == I915_GEM_DOMAIN_INSTRUCTION && |
kgem->reloc[n].target_handle == 0) |
kgem->reloc[n].delta -= shrink; |
if (kgem->reloc[n].offset >= size) |
kgem->reloc[n].offset -= shrink; |
} |
return size; |
} |
void execute_buffer (struct drm_i915_gem_object *buffer, uint32_t offset, |
int size); |
void _kgem_submit(struct kgem *kgem) |
{ |
struct kgem_request *rq; |
uint32_t batch_end; |
int size; |
assert(!DBG_NO_HW); |
assert(kgem->nbatch); |
assert(kgem->nbatch <= KGEM_BATCH_SIZE(kgem)); |
assert(kgem->nbatch <= kgem->surface); |
batch_end = kgem_end_batch(kgem); |
kgem_sna_flush(kgem); |
DBG(("batch[%d/%d]: %d %d %d, nreloc=%d, nexec=%d, nfence=%d, aperture=%d\n", |
kgem->mode, kgem->ring, batch_end, kgem->nbatch, kgem->surface, |
kgem->nreloc, kgem->nexec, kgem->nfence, kgem->aperture)); |
assert(kgem->nbatch <= kgem->max_batch_size); |
assert(kgem->nbatch <= kgem->surface); |
assert(kgem->nreloc <= ARRAY_SIZE(kgem->reloc)); |
assert(kgem->nexec < ARRAY_SIZE(kgem->exec)); |
assert(kgem->nfence <= kgem->fence_max); |
// kgem_finish_partials(kgem); |
rq = kgem->next_request; |
// if (kgem->surface != kgem->max_batch_size) |
// size = compact_batch_surface(kgem); |
// else |
size = kgem->nbatch * sizeof(kgem->batch[0]); |
#if 0 |
{ |
int i; |
dbgprintf("\nDump batch\n\n"); |
for(i=0; i < kgem->nbatch; i++) |
{ |
dbgprintf("\t0x%08x,\t/* %d */\n", |
kgem->batch[i], i); |
} |
dbgprintf("\ndone\n"); |
}; |
#endif |
execute_buffer(kgem->batch_obj, kgem->batch_idx*4096, sizeof(uint32_t)*kgem->nbatch); |
// if (kgem->wedged) |
// kgem_cleanup(kgem); |
kgem->batch_idx++; |
kgem->batch_idx&= 3; |
kgem->flush_now = kgem->scanout; |
kgem_reset(kgem); |
assert(kgem->next_request != NULL); |
} |
static struct kgem_bo * |
search_linear_cache(struct kgem *kgem, unsigned int num_pages, unsigned flags) |
{ |
struct kgem_bo *bo, *first = NULL; |
bool use_active = (flags & CREATE_INACTIVE) == 0; |
struct list_head *cache; |
if (num_pages >= MAX_CACHE_SIZE / PAGE_SIZE) |
return NULL; |
if (!use_active && |
list_is_empty(inactive(kgem, num_pages)) && |
!list_is_empty(active(kgem, num_pages, I915_TILING_NONE)) && |
!kgem_retire(kgem)) |
return NULL; |
if (!use_active && flags & (CREATE_CPU_MAP | CREATE_GTT_MAP)) { |
int for_cpu = !!(flags & CREATE_CPU_MAP); |
cache = &kgem->vma[for_cpu].inactive[cache_bucket(num_pages)]; |
list_for_each_entry(bo, cache, vma) { |
assert(IS_CPU_MAP(bo->map) == for_cpu); |
assert(bucket(bo) == cache_bucket(num_pages)); |
if (num_pages > num_pages(bo)) { |
DBG(("inactive too small: %d < %d\n", |
num_pages(bo), num_pages)); |
continue; |
} |
if (bo->purged && !kgem_bo_clear_purgeable(kgem, bo)) { |
kgem_bo_free(kgem, bo); |
break; |
} |
// if (I915_TILING_NONE != bo->tiling && |
// gem_set_tiling(kgem->fd, bo->handle, |
// I915_TILING_NONE, 0) != I915_TILING_NONE) |
// continue; |
kgem_bo_remove_from_inactive(kgem, bo); |
bo->tiling = I915_TILING_NONE; |
bo->pitch = 0; |
bo->delta = 0; |
DBG((" %s: found handle=%d (num_pages=%d) in linear vma cache\n", |
__FUNCTION__, bo->handle, num_pages(bo))); |
assert(use_active || bo->domain != DOMAIN_GPU); |
assert(!bo->needs_flush); |
//assert(!kgem_busy(kgem, bo->handle)); |
return bo; |
} |
} |
cache = use_active ? active(kgem, num_pages, I915_TILING_NONE) : inactive(kgem, num_pages); |
list_for_each_entry(bo, cache, list) { |
assert(bo->refcnt == 0); |
assert(bo->reusable); |
assert(!!bo->rq == !!use_active); |
if (num_pages > num_pages(bo)) |
continue; |
if (use_active && bo->tiling != I915_TILING_NONE) |
continue; |
if (bo->purged && !kgem_bo_clear_purgeable(kgem, bo)) { |
kgem_bo_free(kgem, bo); |
break; |
} |
/* |
if (I915_TILING_NONE != bo->tiling) { |
if (use_active) |
continue; |
if (gem_set_tiling(kgem->fd, bo->handle, |
I915_TILING_NONE, 0) != I915_TILING_NONE) |
continue; |
bo->tiling = I915_TILING_NONE; |
} |
*/ |
if (bo->map) { |
if (flags & (CREATE_CPU_MAP | CREATE_GTT_MAP)) { |
int for_cpu = !!(flags & CREATE_CPU_MAP); |
if (IS_CPU_MAP(bo->map) != for_cpu) { |
if (first != NULL) |
break; |
first = bo; |
continue; |
} |
} else { |
if (first != NULL) |
break; |
first = bo; |
continue; |
} |
} else { |
if (flags & (CREATE_CPU_MAP | CREATE_GTT_MAP)) { |
if (first != NULL) |
break; |
first = bo; |
continue; |
} |
} |
if (use_active) |
kgem_bo_remove_from_active(kgem, bo); |
else |
kgem_bo_remove_from_inactive(kgem, bo); |
assert(bo->tiling == I915_TILING_NONE); |
bo->pitch = 0; |
bo->delta = 0; |
DBG((" %s: found handle=%d (num_pages=%d) in linear %s cache\n", |
__FUNCTION__, bo->handle, num_pages(bo), |
use_active ? "active" : "inactive")); |
assert(use_active || bo->domain != DOMAIN_GPU); |
assert(!bo->needs_flush || use_active); |
//assert(use_active || !kgem_busy(kgem, bo->handle)); |
return bo; |
} |
if (first) { |
assert(first->tiling == I915_TILING_NONE); |
if (use_active) |
kgem_bo_remove_from_active(kgem, first); |
else |
kgem_bo_remove_from_inactive(kgem, first); |
first->pitch = 0; |
first->delta = 0; |
DBG((" %s: found handle=%d (num_pages=%d) in linear %s cache\n", |
__FUNCTION__, first->handle, num_pages(first), |
use_active ? "active" : "inactive")); |
assert(use_active || first->domain != DOMAIN_GPU); |
assert(!first->needs_flush || use_active); |
//assert(use_active || !kgem_busy(kgem, first->handle)); |
return first; |
} |
return NULL; |
} |
struct kgem_bo *kgem_create_linear(struct kgem *kgem, int size) |
{ |
struct kgem_bo *bo; |
uint32_t handle; |
DBG(("%s(%d)\n", __FUNCTION__, size)); |
size = (size + PAGE_SIZE - 1) / PAGE_SIZE; |
bo = search_linear_cache(kgem, size, CREATE_INACTIVE); |
if (bo) |
return kgem_bo_reference(bo); |
handle = gem_create(kgem->fd, size); |
if (handle == 0) |
return NULL; |
DBG(("%s: new handle=%x\n", __FUNCTION__, handle)); |
bo = __kgem_bo_alloc(handle, size); |
if (bo == NULL) { |
gem_close(kgem->fd, handle); |
return NULL; |
} |
struct drm_i915_gem_object *obj; |
obj = (void*)handle; |
bo->gaddr = obj->gtt_offset; |
return bo; |
} |
inline int kgem_bo_fenced_size(struct kgem *kgem, struct kgem_bo *bo) |
{ |
unsigned int size; |
assert(bo->tiling); |
assert(kgem->gen < 40); |
if (kgem->gen < 30) |
size = 512 * 1024; |
else |
size = 1024 * 1024; |
while (size < bytes(bo)) |
size *= 2; |
return size; |
} |
void _kgem_bo_destroy(struct kgem *kgem, struct kgem_bo *bo) |
{ |
// if (bo->proxy) { |
// assert(bo->map == NULL); |
// if (bo->io && bo->exec == NULL) |
// _kgem_bo_delete_partial(kgem, bo); |
// kgem_bo_unref(kgem, bo->proxy); |
// kgem_bo_binding_free(kgem, bo); |
// _list_del(&bo->request); |
// free(bo); |
// return; |
// } |
// if (bo->vmap) |
// kgem_bo_sync__cpu(kgem, bo); |
__kgem_bo_destroy(kgem, bo); |
} |
void __kgem_flush(struct kgem *kgem, struct kgem_bo *bo) |
{ |
/* The kernel will emit a flush *and* update its own flushing lists. */ |
// kgem_busy(kgem, bo->handle); |
} |
bool kgem_check_bo(struct kgem *kgem, ...) |
{ |
va_list ap; |
struct kgem_bo *bo; |
int num_exec = 0; |
int num_pages = 0; |
va_start(ap, kgem); |
while ((bo = va_arg(ap, struct kgem_bo *))) { |
if (bo->exec) |
continue; |
if (bo->proxy) { |
bo = bo->proxy; |
if (bo->exec) |
continue; |
} |
num_pages += num_pages(bo); |
num_exec++; |
} |
va_end(ap); |
if (!num_pages) |
return true; |
if (kgem->aperture > kgem->aperture_low) |
return false; |
if (num_pages + kgem->aperture > kgem->aperture_high) |
return false; |
if (kgem->nexec + num_exec >= KGEM_EXEC_SIZE(kgem)) |
return false; |
return true; |
} |
/* |
bool kgem_check_bo_fenced(struct kgem *kgem, ...) |
{ |
va_list ap; |
struct kgem_bo *bo; |
int num_fence = 0; |
int num_exec = 0; |
int num_pages = 0; |
int fenced_size = 0; |
va_start(ap, kgem); |
while ((bo = va_arg(ap, struct kgem_bo *))) { |
if (bo->proxy) |
bo = bo->proxy; |
if (bo->exec) { |
if (kgem->gen >= 40 || bo->tiling == I915_TILING_NONE) |
continue; |
if ((bo->exec->flags & EXEC_OBJECT_NEEDS_FENCE) == 0) { |
fenced_size += kgem_bo_fenced_size(kgem, bo); |
num_fence++; |
} |
continue; |
} |
num_pages += num_pages(bo); |
num_exec++; |
if (kgem->gen < 40 && bo->tiling) { |
fenced_size += kgem_bo_fenced_size(kgem, bo); |
num_fence++; |
} |
} |
va_end(ap); |
if (fenced_size + kgem->aperture_fenced > kgem->aperture_mappable) |
return false; |
if (kgem->nfence + num_fence > kgem->fence_max) |
return false; |
if (!num_pages) |
return true; |
if (kgem->aperture > kgem->aperture_low) |
return false; |
if (num_pages + kgem->aperture > kgem->aperture_high) |
return false; |
if (kgem->nexec + num_exec >= KGEM_EXEC_SIZE(kgem)) |
return false; |
return true; |
} |
*/ |
#if 0 |
uint32_t kgem_add_reloc(struct kgem *kgem, |
uint32_t pos, |
struct kgem_bo *bo, |
uint32_t read_write_domain, |
uint32_t delta) |
{ |
int index; |
DBG(("%s: handle=%d, pos=%d, delta=%d, domains=%08x\n", |
__FUNCTION__, bo ? bo->handle : 0, pos, delta, read_write_domain)); |
assert((read_write_domain & 0x7fff) == 0 || bo != NULL); |
index = kgem->nreloc++; |
assert(index < ARRAY_SIZE(kgem->reloc)); |
kgem->reloc[index].offset = pos * sizeof(kgem->batch[0]); |
if (bo) { |
assert(bo->refcnt); |
assert(!bo->purged); |
delta += bo->delta; |
if (bo->proxy) { |
DBG(("%s: adding proxy for handle=%d\n", |
__FUNCTION__, bo->handle)); |
assert(bo->handle == bo->proxy->handle); |
/* need to release the cache upon batch submit */ |
list_move(&bo->request, &kgem->next_request->buffers); |
bo->exec = &_kgem_dummy_exec; |
bo = bo->proxy; |
} |
assert(!bo->purged); |
// if (bo->exec == NULL) |
// _kgem_add_bo(kgem, bo); |
// if (kgem->gen < 40 && read_write_domain & KGEM_RELOC_FENCED) { |
// if (bo->tiling && |
// (bo->exec->flags & EXEC_OBJECT_NEEDS_FENCE) == 0) { |
// assert(kgem->nfence < kgem->fence_max); |
// kgem->aperture_fenced += |
// kgem_bo_fenced_size(kgem, bo); |
// kgem->nfence++; |
// } |
// bo->exec->flags |= EXEC_OBJECT_NEEDS_FENCE; |
// } |
kgem->reloc[index].delta = delta; |
kgem->reloc[index].target_handle = bo->handle; |
kgem->reloc[index].presumed_offset = bo->presumed_offset; |
if (read_write_domain & 0x7fff) { |
DBG(("%s: marking handle=%d dirty\n", |
__FUNCTION__, bo->handle)); |
bo->needs_flush = bo->dirty = true; |
} |
delta += bo->presumed_offset; |
} else { |
kgem->reloc[index].delta = delta; |
kgem->reloc[index].target_handle = 0; |
kgem->reloc[index].presumed_offset = 0; |
} |
kgem->reloc[index].read_domains = read_write_domain >> 16; |
kgem->reloc[index].write_domain = read_write_domain & 0x7fff; |
return delta; |
} |
#endif |
void *kgem_bo_map(struct kgem *kgem, struct kgem_bo *bo) |
{ |
void *ptr; |
DBG(("%s: handle=%d, offset=%d, tiling=%d, map=%p, domain=%d\n", __FUNCTION__, |
bo->handle, bo->presumed_offset, bo->tiling, bo->map, bo->domain)); |
assert(!bo->purged); |
assert(bo->exec == NULL); |
assert(list_is_empty(&bo->list)); |
// if (bo->tiling == I915_TILING_NONE && |
// (kgem->has_llc || bo->domain == bo->presumed_offset)) { |
DBG(("%s: converting request for GTT map into CPU map\n", |
__FUNCTION__)); |
ptr = kgem_bo_map__cpu(kgem, bo); |
// kgem_bo_sync__cpu(kgem, bo); |
return ptr; |
// } |
#if 0 |
if (IS_CPU_MAP(bo->map)) |
kgem_bo_release_map(kgem, bo); |
ptr = bo->map; |
if (ptr == NULL) { |
assert(bytes(bo) <= kgem->aperture_mappable / 4); |
kgem_trim_vma_cache(kgem, MAP_GTT, bucket(bo)); |
ptr = gem_mmap(kgem->fd, bo->handle, bytes(bo), |
PROT_READ | PROT_WRITE); |
if (ptr == NULL) |
return NULL; |
/* Cache this mapping to avoid the overhead of an |
* excruciatingly slow GTT pagefault. This is more an |
* issue with compositing managers which need to frequently |
* flush CPU damage to their GPU bo. |
*/ |
bo->map = ptr; |
DBG(("%s: caching GTT vma for %d\n", __FUNCTION__, bo->handle)); |
} |
if (bo->domain != DOMAIN_GTT) { |
struct drm_i915_gem_set_domain set_domain; |
DBG(("%s: sync: needs_flush? %d, domain? %d\n", __FUNCTION__, |
bo->needs_flush, bo->domain)); |
/* XXX use PROT_READ to avoid the write flush? */ |
VG_CLEAR(set_domain); |
set_domain.handle = bo->handle; |
set_domain.read_domains = I915_GEM_DOMAIN_GTT; |
set_domain.write_domain = I915_GEM_DOMAIN_GTT; |
drmIoctl(kgem->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain); |
kgem_bo_retire(kgem, bo); |
bo->domain = DOMAIN_GTT; |
} |
#endif |
return ptr; |
} |
void *kgem_bo_map__cpu(struct kgem *kgem, struct kgem_bo *bo) |
{ |
// struct drm_i915_gem_mmap mmap_arg; |
DBG(("%s(handle=%d, size=%d)\n", __FUNCTION__, bo->handle, bytes(bo))); |
assert(!bo->purged); |
assert(list_is_empty(&bo->list)); |
if (IS_CPU_MAP(bo->map)) |
return CPU_MAP(bo->map); |
struct drm_i915_gem_object *obj = (void*)bo->handle; |
u8 *dst; |
int ret; |
if(obj->pin_count == 0) |
{ |
ret = i915_gem_object_pin(obj, 4096, true); |
if (ret) |
return NULL; |
}; |
dst = drm_intel_bo_map(obj, true); |
DBG(("%s: caching CPU vma for %d\n", __FUNCTION__, bo->handle)); |
bo->map = MAKE_CPU_MAP(dst); |
return (void *)dst; |
#if 0 |
if (bo->map) |
kgem_bo_release_map(kgem, bo); |
kgem_trim_vma_cache(kgem, MAP_CPU, bucket(bo)); |
VG_CLEAR(mmap_arg); |
mmap_arg.handle = bo->handle; |
mmap_arg.offset = 0; |
mmap_arg.size = bytes(bo); |
if (drmIoctl(kgem->fd, DRM_IOCTL_I915_GEM_MMAP, &mmap_arg)) { |
ErrorF("%s: failed to mmap %d, %d bytes, into CPU domain\n", |
__FUNCTION__, bo->handle, bytes(bo)); |
return NULL; |
} |
VG(VALGRIND_MALLOCLIKE_BLOCK(mmap_arg.addr_ptr, bytes(bo), 0, 1)); |
#endif |
} |
void kgem_clear_dirty(struct kgem *kgem) |
{ |
struct kgem_request *rq = kgem->next_request; |
struct kgem_bo *bo; |
list_for_each_entry(bo, &rq->buffers, request) |
bo->dirty = false; |
} |
struct kgem_bo *kgem_create_proxy(struct kgem_bo *target, |
int offset, int length) |
{ |
struct kgem_bo *bo; |
DBG(("%s: target handle=%d, offset=%d, length=%d, io=%d\n", |
__FUNCTION__, target->handle, offset, length, target->io)); |
bo = __kgem_bo_alloc(target->handle, length); |
if (bo == NULL) |
return NULL; |
bo->reusable = false; |
bo->size.bytes = length; |
bo->io = target->io; |
bo->dirty = target->dirty; |
bo->tiling = target->tiling; |
bo->pitch = target->pitch; |
if (target->proxy) { |
offset += target->delta; |
target = target->proxy; |
} |
bo->proxy = kgem_bo_reference(target); |
bo->delta = offset; |
bo->gaddr = offset + target->gaddr; |
return bo; |
} |
uint32_t kgem_bo_get_binding(struct kgem_bo *bo, uint32_t format) |
{ |
struct kgem_bo_binding *b; |
for (b = &bo->binding; b && b->offset; b = b->next) |
if (format == b->format) |
return b->offset; |
return 0; |
} |
void kgem_bo_set_binding(struct kgem_bo *bo, uint32_t format, uint16_t offset) |
{ |
struct kgem_bo_binding *b; |
for (b = &bo->binding; b; b = b->next) { |
if (b->offset) |
continue; |
b->offset = offset; |
b->format = format; |
if (b->next) |
b->next->offset = 0; |
return; |
} |
b = malloc(sizeof(*b)); |
if (b) { |
b->next = bo->binding.next; |
b->format = format; |
b->offset = offset; |
bo->binding.next = b; |
} |
} |
struct kgem_bo *create_bo(bitmap_t *bitmap) |
{ |
struct kgem_bo *bo; |
bo = __kgem_bo_alloc(bitmap->obj, 1024*768*4/4096); |
bo->gaddr = bitmap->gaddr; |
bo->pitch = bitmap->pitch; |
bo->tiling = 0; |
return bo; |
}; |
/drivers/video/drm/i915/sna/kgem.h |
---|
0,0 → 1,529 |
/* |
* Copyright (c) 2011 Intel Corporation |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
* copy of this software and associated documentation files (the "Software"), |
* to deal in the Software without restriction, including without limitation |
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
* and/or sell copies of the Software, and to permit persons to whom the |
* Software is furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice (including the next |
* paragraph) shall be included in all copies or substantial portions of the |
* Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
* SOFTWARE. |
* |
* Authors: |
* Chris Wilson <chris@chris-wilson.co.uk> |
* |
*/ |
#ifndef KGEM_H |
#define KGEM_H |
#include "compiler.h" |
#include <linux/list.h> |
//#include <stdarg.h> |
#include <i915_drm.h> |
#if DEBUG_KGEM |
#define DBG_HDR(x) ErrorF x |
#else |
#define DBG_HDR(x) |
#endif |
struct kgem_bo { |
struct kgem_bo *proxy; |
struct list_head list; |
struct list_head request; |
struct list_head vma; |
void *map; |
uint32_t gaddr; |
#define IS_CPU_MAP(ptr) ((uintptr_t)(ptr) & 1) |
#define IS_GTT_MAP(ptr) (ptr && ((uintptr_t)(ptr) & 1) == 0) |
struct kgem_request *rq; |
struct drm_i915_gem_exec_object2 *exec; |
struct kgem_bo_binding { |
struct kgem_bo_binding *next; |
uint32_t format; |
uint16_t offset; |
} binding; |
uint32_t unique_id; |
uint32_t refcnt; |
uint32_t handle; |
uint32_t presumed_offset; |
uint32_t delta; |
union { |
struct { |
uint32_t count:27; |
uint32_t bucket:5; |
#define NUM_CACHE_BUCKETS 16 |
#define MAX_CACHE_SIZE (1 << (NUM_CACHE_BUCKETS+12)) |
} pages; |
uint32_t bytes; |
} size; |
uint32_t pitch : 18; /* max 128k */ |
uint32_t tiling : 2; |
uint32_t reusable : 1; |
uint32_t dirty : 1; |
uint32_t domain : 2; |
uint32_t needs_flush : 1; |
uint32_t vmap : 1; |
uint32_t io : 1; |
uint32_t flush : 1; |
uint32_t scanout : 1; |
uint32_t sync : 1; |
uint32_t purged : 1; |
}; |
#define DOMAIN_NONE 0 |
#define DOMAIN_CPU 1 |
#define DOMAIN_GTT 2 |
#define DOMAIN_GPU 3 |
struct kgem_request { |
struct list_head list; |
struct kgem_bo *bo; |
struct list_head buffers; |
}; |
enum { |
MAP_GTT = 0, |
MAP_CPU, |
NUM_MAP_TYPES, |
}; |
struct kgem { |
int fd; |
int wedged; |
int gen; |
uint32_t unique_id; |
enum kgem_mode { |
/* order matches I915_EXEC_RING ordering */ |
KGEM_NONE = 0, |
KGEM_RENDER, |
KGEM_BSD, |
KGEM_BLT, |
} mode, ring; |
struct list_head flushing; |
struct list_head large; |
struct list_head active[NUM_CACHE_BUCKETS][3]; |
struct list_head inactive[NUM_CACHE_BUCKETS]; |
struct list_head partial; |
struct list_head requests; |
struct kgem_request *next_request; |
struct { |
struct list_head inactive[NUM_CACHE_BUCKETS]; |
int16_t count; |
} vma[NUM_MAP_TYPES]; |
uint16_t nbatch; |
uint16_t surface; |
uint16_t nexec; |
uint16_t nreloc; |
uint16_t nfence; |
uint16_t max_batch_size; |
uint32_t flush:1; |
uint32_t sync:1; |
uint32_t need_expire:1; |
uint32_t need_purge:1; |
uint32_t need_retire:1; |
uint32_t scanout:1; |
uint32_t flush_now:1; |
uint32_t busy:1; |
uint32_t has_vmap :1; |
uint32_t has_relaxed_fencing :1; |
uint32_t has_semaphores :1; |
uint32_t has_llc :1; |
uint32_t has_cpu_bo :1; |
uint16_t fence_max; |
uint16_t half_cpu_cache_pages; |
uint32_t aperture_total, aperture_high, aperture_low, aperture_mappable; |
uint32_t aperture, aperture_fenced; |
uint32_t min_alignment; |
uint32_t max_upload_tile_size, max_copy_tile_size; |
uint32_t max_gpu_size, max_cpu_size; |
uint32_t large_object_size, max_object_size; |
uint32_t partial_buffer_size; |
// void (*context_switch)(struct kgem *kgem, int new_mode); |
void (*retire)(struct kgem *kgem); |
uint32_t *batch; |
uint32_t *batch_ptr; |
int batch_idx; |
struct drm_i915_gem_object *batch_obj; |
struct drm_i915_gem_exec_object2 exec[256]; |
struct drm_i915_gem_relocation_entry reloc[384]; |
}; |
#define KGEM_BATCH_RESERVED 1 |
#define KGEM_RELOC_RESERVED 4 |
#define KGEM_EXEC_RESERVED 1 |
#define KGEM_BATCH_SIZE(K) ((K)->max_batch_size-KGEM_BATCH_RESERVED) |
#define KGEM_EXEC_SIZE(K) (int)(ARRAY_SIZE((K)->exec)-KGEM_EXEC_RESERVED) |
#define KGEM_RELOC_SIZE(K) (int)(ARRAY_SIZE((K)->reloc)-KGEM_RELOC_RESERVED) |
void kgem_init(struct kgem *kgem, int gen); |
void kgem_reset(struct kgem *kgem); |
struct kgem_bo *kgem_create_map(struct kgem *kgem, |
void *ptr, uint32_t size, |
bool read_only); |
struct kgem_bo *kgem_create_for_name(struct kgem *kgem, uint32_t name); |
struct kgem_bo *kgem_create_linear(struct kgem *kgem, int size); |
struct kgem_bo *kgem_create_proxy(struct kgem_bo *target, |
int offset, int length); |
//struct kgem_bo *kgem_upload_source_image(struct kgem *kgem, |
// const void *data, |
// BoxPtr box, |
// int stride, int bpp); |
int kgem_choose_tiling(struct kgem *kgem, |
int tiling, int width, int height, int bpp); |
unsigned kgem_can_create_2d(struct kgem *kgem, int width, int height, int depth); |
#define KGEM_CAN_CREATE_GPU 0x1 |
#define KGEM_CAN_CREATE_CPU 0x2 |
#define KGEM_CAN_CREATE_LARGE 0x4 |
struct kgem_bo * |
kgem_replace_bo(struct kgem *kgem, |
struct kgem_bo *src, |
uint32_t width, |
uint32_t height, |
uint32_t pitch, |
uint32_t bpp); |
enum { |
CREATE_EXACT = 0x1, |
CREATE_INACTIVE = 0x2, |
CREATE_CPU_MAP = 0x4, |
CREATE_GTT_MAP = 0x8, |
CREATE_SCANOUT = 0x10, |
}; |
struct kgem_bo *kgem_create_2d(struct kgem *kgem, |
int width, |
int height, |
int bpp, |
int tiling, |
uint32_t flags); |
uint32_t kgem_bo_get_binding(struct kgem_bo *bo, uint32_t format); |
void kgem_bo_set_binding(struct kgem_bo *bo, uint32_t format, uint16_t offset); |
bool kgem_retire(struct kgem *kgem); |
void _kgem_submit(struct kgem *kgem); |
static inline void kgem_submit(struct kgem *kgem) |
{ |
if (kgem->nbatch) |
_kgem_submit(kgem); |
} |
/* |
static inline void kgem_bo_submit(struct kgem *kgem, struct kgem_bo *bo) |
{ |
if (bo->exec) |
_kgem_submit(kgem); |
} |
void __kgem_flush(struct kgem *kgem, struct kgem_bo *bo); |
static inline void kgem_bo_flush(struct kgem *kgem, struct kgem_bo *bo) |
{ |
kgem_bo_submit(kgem, bo); |
if (!bo->needs_flush) |
return; |
__kgem_flush(kgem, bo); |
bo->needs_flush = false; |
} |
*/ |
static inline struct kgem_bo *kgem_bo_reference(struct kgem_bo *bo) |
{ |
bo->refcnt++; |
return bo; |
} |
void _kgem_bo_destroy(struct kgem *kgem, struct kgem_bo *bo); |
static inline void kgem_bo_destroy(struct kgem *kgem, struct kgem_bo *bo) |
{ |
assert(bo->refcnt); |
if (--bo->refcnt == 0) |
_kgem_bo_destroy(kgem, bo); |
} |
void kgem_clear_dirty(struct kgem *kgem); |
static inline void kgem_set_mode(struct kgem *kgem, enum kgem_mode mode) |
{ |
assert(!kgem->wedged); |
#if DEBUG_FLUSH_BATCH |
kgem_submit(kgem); |
#endif |
if (kgem->mode == mode) |
return; |
// kgem->context_switch(kgem, mode); |
kgem->mode = mode; |
} |
static inline void _kgem_set_mode(struct kgem *kgem, enum kgem_mode mode) |
{ |
assert(kgem->mode == KGEM_NONE); |
// kgem->context_switch(kgem, mode); |
kgem->mode = mode; |
} |
static inline bool kgem_check_batch(struct kgem *kgem, int num_dwords) |
{ |
return likely(kgem->nbatch + num_dwords + KGEM_BATCH_RESERVED <= kgem->surface); |
} |
static inline bool kgem_check_reloc(struct kgem *kgem, int n) |
{ |
return likely(kgem->nreloc + n <= KGEM_RELOC_SIZE(kgem)); |
} |
static inline bool kgem_check_exec(struct kgem *kgem, int n) |
{ |
return likely(kgem->nexec + n <= KGEM_EXEC_SIZE(kgem)); |
} |
static inline bool kgem_check_batch_with_surfaces(struct kgem *kgem, |
int num_dwords, |
int num_surfaces) |
{ |
return (int)(kgem->nbatch + num_dwords + KGEM_BATCH_RESERVED) <= (int)(kgem->surface - num_surfaces*8) && |
kgem_check_reloc(kgem, num_surfaces); |
} |
static inline uint32_t *kgem_get_batch(struct kgem *kgem, int num_dwords) |
{ |
if (!kgem_check_batch(kgem, num_dwords)) |
_kgem_submit(kgem); |
return kgem->batch + kgem->nbatch; |
} |
static inline void kgem_advance_batch(struct kgem *kgem, int num_dwords) |
{ |
kgem->nbatch += num_dwords; |
} |
bool kgem_check_bo(struct kgem *kgem, ...) __attribute__((sentinel(0))); |
bool kgem_check_bo_fenced(struct kgem *kgem, ...) __attribute__((sentinel(0))); |
void _kgem_add_bo(struct kgem *kgem, struct kgem_bo *bo); |
static inline void kgem_add_bo(struct kgem *kgem, struct kgem_bo *bo) |
{ |
if (bo->proxy) |
bo = bo->proxy; |
if (bo->exec == NULL) |
_kgem_add_bo(kgem, bo); |
} |
#define KGEM_RELOC_FENCED 0x8000 |
uint32_t kgem_add_reloc(struct kgem *kgem, |
uint32_t pos, |
struct kgem_bo *bo, |
uint32_t read_write_domains, |
uint32_t delta); |
void *kgem_bo_map(struct kgem *kgem, struct kgem_bo *bo); |
void *kgem_bo_map__debug(struct kgem *kgem, struct kgem_bo *bo); |
void *kgem_bo_map__cpu(struct kgem *kgem, struct kgem_bo *bo); |
void kgem_bo_sync__cpu(struct kgem *kgem, struct kgem_bo *bo); |
uint32_t kgem_bo_flink(struct kgem *kgem, struct kgem_bo *bo); |
Bool kgem_bo_write(struct kgem *kgem, struct kgem_bo *bo, |
const void *data, int length); |
int kgem_bo_fenced_size(struct kgem *kgem, struct kgem_bo *bo); |
void kgem_get_tile_size(struct kgem *kgem, int tiling, |
int *tile_width, int *tile_height, int *tile_size); |
static inline int kgem_bo_size(struct kgem_bo *bo) |
{ |
assert(!(bo->proxy && bo->io)); |
return PAGE_SIZE * bo->size.pages.count; |
} |
static inline int kgem_buffer_size(struct kgem_bo *bo) |
{ |
assert(bo->proxy && bo->io); |
return bo->size.bytes; |
} |
/* |
static inline bool kgem_bo_blt_pitch_is_ok(struct kgem *kgem, |
struct kgem_bo *bo) |
{ |
int pitch = bo->pitch; |
if (kgem->gen >= 40 && bo->tiling) |
pitch /= 4; |
if (pitch > MAXSHORT) { |
DBG(("%s: can not blt to handle=%d, adjusted pitch=%d\n", |
__FUNCTION__, pitch)); |
return false; |
} |
return true; |
} |
static inline bool kgem_bo_can_blt(struct kgem *kgem, |
struct kgem_bo *bo) |
{ |
if (bo->tiling == I915_TILING_Y) { |
DBG(("%s: can not blt to handle=%d, tiling=Y\n", |
__FUNCTION__, bo->handle)); |
return false; |
} |
return kgem_bo_blt_pitch_is_ok(kgem, bo); |
} |
*/ |
static inline bool kgem_bo_is_mappable(struct kgem *kgem, |
struct kgem_bo *bo) |
{ |
DBG_HDR(("%s: domain=%d, offset: %d size: %d\n", |
__FUNCTION__, bo->domain, bo->presumed_offset, kgem_bo_size(bo))); |
if (bo->domain == DOMAIN_GTT) |
return true; |
if (IS_GTT_MAP(bo->map)) |
return true; |
if (kgem->gen < 40 && bo->tiling && |
bo->presumed_offset & (kgem_bo_fenced_size(kgem, bo) - 1)) |
return false; |
if (!bo->presumed_offset) |
return kgem_bo_size(bo) <= kgem->aperture_mappable / 4; |
return bo->presumed_offset + kgem_bo_size(bo) <= kgem->aperture_mappable; |
} |
static inline bool kgem_bo_mapped(struct kgem_bo *bo) |
{ |
DBG_HDR(("%s: map=%p, tiling=%d\n", __FUNCTION__, bo->map, bo->tiling)); |
if (bo->map == NULL) |
return false; |
return IS_CPU_MAP(bo->map) == !bo->tiling; |
} |
static inline bool kgem_bo_is_busy(struct kgem_bo *bo) |
{ |
DBG_HDR(("%s: domain: %d exec? %d, rq? %d\n", |
__FUNCTION__, bo->domain, bo->exec != NULL, bo->rq != NULL)); |
assert(bo->proxy == NULL); |
return bo->rq; |
} |
/* |
static inline bool kgem_bo_map_will_stall(struct kgem *kgem, struct kgem_bo *bo) |
{ |
DBG(("%s? handle=%d, domain=%d, offset=%x, size=%x\n", |
__FUNCTION__, bo->handle, |
bo->domain, bo->presumed_offset, bo->size)); |
if (!kgem_bo_is_mappable(kgem, bo)) |
return true; |
if (kgem->wedged) |
return false; |
if (kgem_bo_is_busy(bo)) |
return true; |
if (bo->presumed_offset == 0) |
return !list_is_empty(&kgem->requests); |
return false; |
} |
*/ |
static inline bool kgem_bo_is_dirty(struct kgem_bo *bo) |
{ |
if (bo == NULL) |
return FALSE; |
return bo->dirty; |
} |
static inline void kgem_bo_mark_dirty(struct kgem_bo *bo) |
{ |
DBG_HDR(("%s: handle=%d\n", __FUNCTION__, bo->handle)); |
bo->dirty = true; |
} |
void kgem_sync(struct kgem *kgem); |
#define KGEM_BUFFER_WRITE 0x1 |
#define KGEM_BUFFER_INPLACE 0x2 |
#define KGEM_BUFFER_LAST 0x4 |
#define KGEM_BUFFER_WRITE_INPLACE (KGEM_BUFFER_WRITE | KGEM_BUFFER_INPLACE) |
struct kgem_bo *kgem_create_buffer(struct kgem *kgem, |
uint32_t size, uint32_t flags, |
void **ret); |
struct kgem_bo *kgem_create_buffer_2d(struct kgem *kgem, |
int width, int height, int bpp, |
uint32_t flags, |
void **ret); |
void kgem_buffer_read_sync(struct kgem *kgem, struct kgem_bo *bo); |
void kgem_throttle(struct kgem *kgem); |
#define MAX_INACTIVE_TIME 10 |
bool kgem_expire_cache(struct kgem *kgem); |
void kgem_purge_cache(struct kgem *kgem); |
void kgem_cleanup_cache(struct kgem *kgem); |
#if HAS_EXTRA_DEBUG |
void __kgem_batch_debug(struct kgem *kgem, uint32_t nbatch); |
#else |
static inline void __kgem_batch_debug(struct kgem *kgem, uint32_t nbatch) |
{ |
(void)kgem; |
(void)nbatch; |
} |
#endif |
#undef DBG_HDR |
u32 get_buffer_offset(uint32_t handle); |
#endif /* KGEM_H */ |
/drivers/video/drm/i915/sna/sna.c |
---|
0,0 → 1,323 |
#include <drmP.h> |
#include <drm.h> |
#include "i915_drm.h" |
#include "i915_drv.h" |
#include "intel_drv.h" |
#include <linux/kernel.h> |
#include <linux/module.h> |
#include <errno-base.h> |
#include <memory.h> |
#include <syscall.h> |
#include "../bitmap.h" |
#include "sna.h" |
struct kgem_bo *create_bo(bitmap_t *bitmap); |
static Bool sna_solid_cache_init(struct sna *sna); |
struct sna *sna_device; |
void no_render_init(struct sna *sna) |
{ |
struct sna_render *render = &sna->render; |
memset (render,0, sizeof (*render)); |
render->vertices = render->vertex_data; |
render->vertex_size = ARRAY_SIZE(render->vertex_data); |
// render->composite = no_render_composite; |
// render->copy_boxes = no_render_copy_boxes; |
// render->copy = no_render_copy; |
// render->fill_boxes = no_render_fill_boxes; |
// render->fill = no_render_fill; |
// render->fill_one = no_render_fill_one; |
// render->clear = no_render_clear; |
// render->reset = no_render_reset; |
// render->flush = no_render_flush; |
// render->fini = no_render_fini; |
// sna->kgem.context_switch = no_render_context_switch; |
// sna->kgem.retire = no_render_retire; |
// if (sna->kgem.gen >= 60) |
sna->kgem.ring = KGEM_RENDER; |
} |
Bool sna_accel_init(struct sna *sna) |
{ |
const char *backend; |
// list_init(&sna->deferred_free); |
// list_init(&sna->dirty_pixmaps); |
// list_init(&sna->active_pixmaps); |
// list_init(&sna->inactive_clock[0]); |
// list_init(&sna->inactive_clock[1]); |
// sna_accel_install_timers(sna); |
backend = "no"; |
sna->have_render = false; |
sna->default_tiling = 0; //I915_TILING_X; |
no_render_init(sna); |
if ((sna->have_render = gen6_render_init(sna))) |
backend = "SandyBridge"; |
/* |
if (sna->chipset.info->gen >= 80) { |
} else if (sna->chipset.info->gen >= 70) { |
if ((sna->have_render = gen7_render_init(sna))) |
backend = "IvyBridge"; |
} else if (sna->chipset.info->gen >= 60) { |
if ((sna->have_render = gen6_render_init(sna))) |
backend = "SandyBridge"; |
} else if (sna->chipset.info->gen >= 50) { |
if ((sna->have_render = gen5_render_init(sna))) |
backend = "Ironlake"; |
} else if (sna->chipset.info->gen >= 40) { |
if ((sna->have_render = gen4_render_init(sna))) |
backend = "Broadwater"; |
} else if (sna->chipset.info->gen >= 30) { |
if ((sna->have_render = gen3_render_init(sna))) |
backend = "gen3"; |
} else if (sna->chipset.info->gen >= 20) { |
if ((sna->have_render = gen2_render_init(sna))) |
backend = "gen2"; |
} |
*/ |
DBG(("%s(backend=%s, have_render=%d)\n", |
__FUNCTION__, backend, sna->have_render)); |
kgem_reset(&sna->kgem); |
if (!sna_solid_cache_init(sna)) |
return FALSE; |
sna_device = sna; |
#if 0 |
{ |
struct kgem_bo *screen_bo; |
bitmap_t screen; |
screen.pitch = 1024*4; |
screen.gaddr = 0; |
screen.width = 1024; |
screen.height = 768; |
screen.obj = (void*)-1; |
screen_bo = create_bo(&screen); |
sna->render.clear(sna, &screen, screen_bo); |
} |
#endif |
return TRUE; |
} |
int sna_init() |
{ |
struct sna *sna; |
DBG(("%s\n", __FUNCTION__)); |
sna = kzalloc(sizeof(struct sna), 0); |
if (sna == NULL) |
return FALSE; |
// sna->mode.cpp = 4; |
kgem_init(&sna->kgem, 60); |
/* |
if (!xf86ReturnOptValBool(sna->Options, |
OPTION_RELAXED_FENCING, |
sna->kgem.has_relaxed_fencing)) { |
xf86DrvMsg(scrn->scrnIndex, |
sna->kgem.has_relaxed_fencing ? X_CONFIG : X_PROBED, |
"Disabling use of relaxed fencing\n"); |
sna->kgem.has_relaxed_fencing = 0; |
} |
if (!xf86ReturnOptValBool(sna->Options, |
OPTION_VMAP, |
sna->kgem.has_vmap)) { |
xf86DrvMsg(scrn->scrnIndex, |
sna->kgem.has_vmap ? X_CONFIG : X_PROBED, |
"Disabling use of vmap\n"); |
sna->kgem.has_vmap = 0; |
} |
*/ |
/* Disable tiling by default */ |
sna->tiling = SNA_TILING_DISABLE; |
/* Default fail-safe value of 75 Hz */ |
// sna->vblank_interval = 1000 * 1000 * 1000 / 75; |
sna->flags = 0; |
sna->flags |= SNA_NO_THROTTLE; |
sna->flags |= SNA_NO_DELAYED_FLUSH; |
return sna_accel_init(sna); |
} |
static Bool sna_solid_cache_init(struct sna *sna) |
{ |
struct sna_solid_cache *cache = &sna->render.solid_cache; |
DBG(("%s\n", __FUNCTION__)); |
cache->cache_bo = |
kgem_create_linear(&sna->kgem, sizeof(cache->color)); |
if (!cache->cache_bo) |
return FALSE; |
/* |
* Initialise [0] with white since it is very common and filling the |
* zeroth slot simplifies some of the checks. |
*/ |
cache->color[0] = 0xffffffff; |
cache->bo[0] = kgem_create_proxy(cache->cache_bo, 0, sizeof(uint32_t)); |
cache->bo[0]->pitch = 4; |
cache->dirty = 1; |
cache->size = 1; |
cache->last = 0; |
return TRUE; |
} |
void |
sna_render_flush_solid(struct sna *sna) |
{ |
struct sna_solid_cache *cache = &sna->render.solid_cache; |
DBG(("sna_render_flush_solid(size=%d)\n", cache->size)); |
assert(cache->dirty); |
assert(cache->size); |
kgem_bo_write(&sna->kgem, cache->cache_bo, |
cache->color, cache->size*sizeof(uint32_t)); |
cache->dirty = 0; |
cache->last = 0; |
} |
static void |
sna_render_finish_solid(struct sna *sna, bool force) |
{ |
struct sna_solid_cache *cache = &sna->render.solid_cache; |
int i; |
DBG(("sna_render_finish_solid(force=%d, domain=%d, busy=%d, dirty=%d)\n", |
force, cache->cache_bo->domain, cache->cache_bo->rq != NULL, cache->dirty)); |
if (!force && cache->cache_bo->domain != DOMAIN_GPU) |
return; |
if (cache->dirty) |
sna_render_flush_solid(sna); |
for (i = 0; i < cache->size; i++) { |
if (cache->bo[i] == NULL) |
continue; |
kgem_bo_destroy(&sna->kgem, cache->bo[i]); |
cache->bo[i] = NULL; |
} |
kgem_bo_destroy(&sna->kgem, cache->cache_bo); |
DBG(("sna_render_finish_solid reset\n")); |
cache->cache_bo = kgem_create_linear(&sna->kgem, sizeof(cache->color)); |
cache->bo[0] = kgem_create_proxy(cache->cache_bo, 0, sizeof(uint32_t)); |
cache->bo[0]->pitch = 4; |
if (force) |
cache->size = 1; |
} |
struct kgem_bo * |
sna_render_get_solid(struct sna *sna, uint32_t color) |
{ |
struct sna_solid_cache *cache = &sna->render.solid_cache; |
int i; |
DBG(("%s: %08x\n", __FUNCTION__, color)); |
// if ((color & 0xffffff) == 0) /* alpha only */ |
// return kgem_bo_reference(sna->render.alpha_cache.bo[color>>24]); |
if (color == 0xffffffff) { |
DBG(("%s(white)\n", __FUNCTION__)); |
return kgem_bo_reference(cache->bo[0]); |
} |
if (cache->color[cache->last] == color) { |
DBG(("sna_render_get_solid(%d) = %x (last)\n", |
cache->last, color)); |
return kgem_bo_reference(cache->bo[cache->last]); |
} |
for (i = 1; i < cache->size; i++) { |
if (cache->color[i] == color) { |
if (cache->bo[i] == NULL) { |
DBG(("sna_render_get_solid(%d) = %x (recreate)\n", |
i, color)); |
goto create; |
} else { |
DBG(("sna_render_get_solid(%d) = %x (old)\n", |
i, color)); |
goto done; |
} |
} |
} |
sna_render_finish_solid(sna, i == ARRAY_SIZE(cache->color)); |
i = cache->size++; |
cache->color[i] = color; |
cache->dirty = 1; |
DBG(("sna_render_get_solid(%d) = %x (new)\n", i, color)); |
create: |
cache->bo[i] = kgem_create_proxy(cache->cache_bo, |
i*sizeof(uint32_t), sizeof(uint32_t)); |
cache->bo[i]->pitch = 4; |
done: |
cache->last = i; |
return kgem_bo_reference(cache->bo[i]); |
} |
int sna_blit_copy(bitmap_t *dst_bitmap, int dst_x, int dst_y, |
int w, int h, bitmap_t *src_bitmap, int src_x, int src_y) |
{ |
struct kgem_bo src_bo, dst_bo; |
memset(&src_bo, 0, sizeof(src_bo)); |
memset(&dst_bo, 0, sizeof(dst_bo)); |
src_bo.gaddr = src_bitmap->gaddr; |
src_bo.pitch = src_bitmap->pitch; |
src_bo.tiling = 0; |
dst_bo.gaddr = dst_bitmap->gaddr; |
dst_bo.pitch = dst_bitmap->pitch; |
dst_bo.tiling = 0; |
sna_device->render.copy(sna_device, 0, src_bitmap, &src_bo, |
dst_bitmap, &dst_bo, dst_x, dst_y, |
src_x, src_y, w, h); |
}; |
/drivers/video/drm/i915/sna/sna.h |
---|
0,0 → 1,125 |
#define FALSE 0 |
#define TRUE 1 |
#define DBG(x) |
//#define DBG(x) dbgprintf x |
#define assert(x) |
#include "compiler.h" |
#include <linux/kernel.h> |
struct pixman_box16 |
{ |
int16_t x1, y1, x2, y2; |
}; |
typedef struct pixman_box16 BoxRec; |
typedef unsigned int CARD32; |
#include "sna_render.h" |
#include "kgem.h" |
#define PictOpClear 0 |
#define PictOpSrc 1 |
#define PictOpDst 2 |
#define PictOpOver 3 |
#define PictOpOverReverse 4 |
#define PictOpIn 5 |
#define PictOpInReverse 6 |
#define PictOpOut 7 |
#define PictOpOutReverse 8 |
#define PictOpAtop 9 |
#define PictOpAtopReverse 10 |
#define PictOpXor 11 |
#define PictOpAdd 12 |
#define PictOpSaturate 13 |
#define PictOpMaximum 13 |
struct sna { |
unsigned flags; |
#define SNA_NO_THROTTLE 0x1 |
#define SNA_NO_DELAYED_FLUSH 0x2 |
// int timer[NUM_TIMERS]; |
// uint16_t timer_active; |
// uint16_t timer_ready; |
// int vblank_interval; |
// struct list deferred_free; |
// struct list dirty_pixmaps; |
// struct list active_pixmaps; |
// struct list inactive_clock[2]; |
unsigned int tiling; |
#define SNA_TILING_DISABLE 0x0 |
#define SNA_TILING_FB 0x1 |
#define SNA_TILING_2D 0x2 |
#define SNA_TILING_3D 0x4 |
#define SNA_TILING_ALL (~0) |
int Chipset; |
// EntityInfoPtr pEnt; |
// struct pci_device *PciInfo; |
// struct intel_chipset chipset; |
// PicturePtr clear; |
struct { |
uint32_t fill_bo; |
uint32_t fill_pixel; |
uint32_t fill_alu; |
} blt_state; |
union { |
// struct gen2_render_state gen2; |
// struct gen3_render_state gen3; |
// struct gen4_render_state gen4; |
// struct gen5_render_state gen5; |
struct gen6_render_state gen6; |
// struct gen7_render_state gen7; |
} render_state; |
uint32_t have_render; |
uint32_t default_tiling; |
// Bool directRenderingOpen; |
// char *deviceName; |
/* Broken-out options. */ |
// OptionInfoPtr Options; |
/* Driver phase/state information */ |
// Bool suspended; |
struct kgem kgem; |
struct sna_render render; |
}; |
static inline int vertex_space(struct sna *sna) |
{ |
return sna->render.vertex_size - sna->render.vertex_used; |
} |
static inline void vertex_emit(struct sna *sna, float v) |
{ |
assert(sna->render.vertex_used < sna->render.vertex_size); |
sna->render.vertices[sna->render.vertex_used++] = v; |
} |
static inline void vertex_emit_2s(struct sna *sna, int16_t x, int16_t y) |
{ |
int16_t *v = (int16_t *)&sna->render.vertices[sna->render.vertex_used++]; |
assert(sna->render.vertex_used <= sna->render.vertex_size); |
v[0] = x; |
v[1] = y; |
} |
static inline void batch_emit(struct sna *sna, uint32_t dword) |
{ |
assert(sna->kgem.mode != KGEM_NONE); |
assert(sna->kgem.nbatch + KGEM_BATCH_RESERVED < sna->kgem.surface); |
sna->kgem.batch[sna->kgem.nbatch++] = dword; |
} |
/drivers/video/drm/i915/sna/sna_reg.h |
---|
0,0 → 1,81 |
#ifndef SNA_REG_H |
#define SNA_REG_H |
/* Flush */ |
#define MI_FLUSH (0x04<<23) |
#define MI_FLUSH_DW (0x26<<23) |
#define MI_WRITE_DIRTY_STATE (1<<4) |
#define MI_END_SCENE (1<<3) |
#define MI_GLOBAL_SNAPSHOT_COUNT_RESET (1<<3) |
#define MI_INHIBIT_RENDER_CACHE_FLUSH (1<<2) |
#define MI_STATE_INSTRUCTION_CACHE_FLUSH (1<<1) |
#define MI_INVALIDATE_MAP_CACHE (1<<0) |
/* broadwater flush bits */ |
#define BRW_MI_GLOBAL_SNAPSHOT_RESET (1 << 3) |
#define MI_BATCH_BUFFER_END (0xA << 23) |
/* Noop */ |
#define MI_NOOP 0x00 |
#define MI_NOOP_WRITE_ID (1<<22) |
#define MI_NOOP_ID_MASK (1<<22 - 1) |
/* Wait for Events */ |
#define MI_WAIT_FOR_EVENT (0x03<<23) |
#define MI_WAIT_FOR_PIPEB_SVBLANK (1<<18) |
#define MI_WAIT_FOR_PIPEA_SVBLANK (1<<17) |
#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) |
#define MI_WAIT_FOR_PIPEB_VBLANK (1<<7) |
#define MI_WAIT_FOR_PIPEB_SCAN_LINE_WINDOW (1<<5) |
#define MI_WAIT_FOR_PIPEA_VBLANK (1<<3) |
#define MI_WAIT_FOR_PIPEA_SCAN_LINE_WINDOW (1<<1) |
/* Set the scan line for MI_WAIT_FOR_PIPE?_SCAN_LINE_WINDOW */ |
#define MI_LOAD_SCAN_LINES_INCL (0x12<<23) |
#define MI_LOAD_SCAN_LINES_DISPLAY_PIPEA (0) |
#define MI_LOAD_SCAN_LINES_DISPLAY_PIPEB (0x1<<20) |
/* BLT commands */ |
#define BLT_WRITE_ALPHA (1<<21) |
#define BLT_WRITE_RGB (1<<20) |
#define BLT_SRC_TILED (1<<15) |
#define BLT_DST_TILED (1<<11) |
#define COLOR_BLT_CMD ((2<<29)|(0x40<<22)|(0x3)) |
#define XY_COLOR_BLT ((2<<29)|(0x50<<22)|(0x4)) |
#define XY_SETUP_BLT ((2<<29)|(1<<22)|6) |
#define XY_SETUP_MONO_PATTERN_SL_BLT ((2<<29)|(0x11<<22)|7) |
#define XY_SETUP_CLIP ((2<<29)|(3<<22)|1) |
#define XY_SCANLINE_BLT ((2<<29)|(0x25<<22)|1) |
#define XY_TEXT_IMMEDIATE_BLT ((2<<29)|(0x31<<22)|(1<<16)) |
#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) |
#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|0x4) |
#define XY_PAT_BLT_IMMEDIATE ((2<<29)|(0x72<<22)) |
#define XY_MONO_PAT ((0x2<<29)|(0x52<<22)|0x7) |
#define XY_MONO_SRC_COPY ((0x2<<29)|(0x54<<22)|(0x6)) |
#define XY_MONO_SRC_COPY_IMM ((0x2<<29)|(0x71<<22)) |
#define XY_FULL_MONO_PATTERN_BLT ((0x2<<29)|(0x57<<22)|0xa) |
#define XY_FULL_MONO_PATTERN_MONO_SRC_BLT ((0x2<<29)|(0x58<<22)|0xa) |
/* FLUSH commands */ |
#define BRW_3D(Pipeline,Opcode,Subopcode) \ |
((3 << 29) | \ |
((Pipeline) << 27) | \ |
((Opcode) << 24) | \ |
((Subopcode) << 16)) |
#define PIPE_CONTROL BRW_3D(3, 2, 0) |
#define PIPE_CONTROL_NOWRITE (0 << 14) |
#define PIPE_CONTROL_WRITE_QWORD (1 << 14) |
#define PIPE_CONTROL_WRITE_DEPTH (2 << 14) |
#define PIPE_CONTROL_WRITE_TIME (3 << 14) |
#define PIPE_CONTROL_DEPTH_STALL (1 << 13) |
#define PIPE_CONTROL_WC_FLUSH (1 << 12) |
#define PIPE_CONTROL_IS_FLUSH (1 << 11) |
#define PIPE_CONTROL_TC_FLUSH (1 << 10) |
#define PIPE_CONTROL_NOTIFY_ENABLE (1 << 8) |
#define PIPE_CONTROL_GLOBAL_GTT (1 << 2) |
#define PIPE_CONTROL_LOCAL_PGTT (0 << 2) |
#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0) |
#endif |
/drivers/video/drm/i915/sna/sna_render.h |
---|
0,0 → 1,494 |
#ifndef SNA_RENDER_H |
#define SNA_RENDER_H |
typedef int Bool; |
#define GRADIENT_CACHE_SIZE 16 |
struct sna; |
struct sna_composite_rectangles { |
struct sna_coordinate { |
int16_t x, y; |
} src, mask, dst; |
int16_t width, height; |
}; |
struct sna_composite_op { |
fastcall void (*blt)(struct sna *sna, const struct sna_composite_op *op, |
const struct sna_composite_rectangles *r); |
fastcall void (*box)(struct sna *sna, |
const struct sna_composite_op *op, |
const BoxRec *box); |
void (*boxes)(struct sna *sna, const struct sna_composite_op *op, |
const BoxRec *box, int nbox); |
void (*done)(struct sna *sna, const struct sna_composite_op *op); |
struct sna_damage **damage; |
uint32_t op; |
struct { |
bitmap_t *pixmap; |
CARD32 format; |
struct kgem_bo *bo; |
int16_t x, y; |
uint16_t width, height; |
} dst; |
struct sna_composite_channel { |
struct kgem_bo *bo; |
// PictTransform *transform; |
uint16_t width; |
uint16_t height; |
uint32_t pict_format; |
uint32_t card_format; |
uint32_t filter; |
uint32_t repeat; |
uint32_t is_affine : 1; |
uint32_t is_solid : 1; |
uint32_t is_linear : 1; |
uint32_t is_opaque : 1; |
uint32_t alpha_fixup : 1; |
uint32_t rb_reversed : 1; |
int16_t offset[2]; |
float scale[2]; |
// pixman_transform_t embedded_transform; |
union { |
struct { |
uint32_t pixel; |
float linear_dx; |
float linear_dy; |
float linear_offset; |
} gen2; |
struct gen3_shader_channel { |
int type; |
uint32_t mode; |
uint32_t constants; |
} gen3; |
} u; |
} src, mask; |
uint32_t is_affine : 1; |
uint32_t has_component_alpha : 1; |
uint32_t need_magic_ca_pass : 1; |
uint32_t rb_reversed : 1; |
int16_t floats_per_vertex; |
int16_t floats_per_rect; |
fastcall void (*prim_emit)(struct sna *sna, |
const struct sna_composite_op *op, |
const struct sna_composite_rectangles *r); |
struct sna_composite_redirect { |
struct kgem_bo *real_bo; |
struct sna_damage **real_damage, *damage; |
BoxRec box; |
} redirect; |
union { |
struct sna_blt_state { |
bitmap_t *src_pixmap; |
int16_t sx, sy; |
uint32_t inplace :1; |
uint32_t overwrites:1; |
uint32_t bpp : 6; |
uint32_t cmd; |
uint32_t br13; |
uint32_t pitch[2]; |
uint32_t pixel; |
struct kgem_bo *bo[2]; |
} blt; |
struct { |
float constants[8]; |
uint32_t num_constants; |
} gen3; |
struct { |
int wm_kernel; |
int ve_id; |
} gen4; |
struct { |
int wm_kernel; |
int ve_id; |
} gen5; |
struct { |
int wm_kernel; |
int nr_surfaces; |
int nr_inputs; |
int ve_id; |
} gen6; |
struct { |
int wm_kernel; |
int nr_surfaces; |
int nr_inputs; |
int ve_id; |
} gen7; |
void *priv; |
} u; |
}; |
struct sna_render { |
int max_3d_size; |
int max_3d_pitch; |
/* |
Bool (*composite)(struct sna *sna, uint8_t op, |
PicturePtr dst, PicturePtr src, PicturePtr mask, |
int16_t src_x, int16_t src_y, |
int16_t msk_x, int16_t msk_y, |
int16_t dst_x, int16_t dst_y, |
int16_t w, int16_t h, |
struct sna_composite_op *tmp); |
Bool (*composite_spans)(struct sna *sna, uint8_t op, |
PicturePtr dst, PicturePtr src, |
int16_t src_x, int16_t src_y, |
int16_t dst_x, int16_t dst_y, |
int16_t w, int16_t h, |
unsigned flags, |
struct sna_composite_spans_op *tmp); |
#define COMPOSITE_SPANS_RECTILINEAR 0x1 |
Bool (*video)(struct sna *sna, |
struct sna_video *video, |
struct sna_video_frame *frame, |
RegionPtr dstRegion, |
short src_w, short src_h, |
short drw_w, short drw_h, |
PixmapPtr pixmap); |
Bool (*fill_boxes)(struct sna *sna, |
CARD8 op, |
PictFormat format, |
const xRenderColor *color, |
PixmapPtr dst, struct kgem_bo *dst_bo, |
const BoxRec *box, int n); |
Bool (*fill)(struct sna *sna, uint8_t alu, |
PixmapPtr dst, struct kgem_bo *dst_bo, |
uint32_t color, |
struct sna_fill_op *tmp); |
Bool (*fill_one)(struct sna *sna, PixmapPtr dst, struct kgem_bo *dst_bo, |
uint32_t color, |
int16_t x1, int16_t y1, int16_t x2, int16_t y2, |
uint8_t alu); |
*/ |
Bool (*clear)(struct sna *sna, bitmap_t *dst, struct kgem_bo *dst_bo); |
/* |
Bool (*copy_boxes)(struct sna *sna, uint8_t alu, |
PixmapPtr src, struct kgem_bo *src_bo, int16_t src_dx, int16_t src_dy, |
PixmapPtr dst, struct kgem_bo *dst_bo, int16_t dst_dx, int16_t dst_dy, |
const BoxRec *box, int n); |
*/ |
Bool (*copy)(struct sna *sna, uint8_t alu, |
bitmap_t *src, struct kgem_bo *src_bo, |
bitmap_t *dst, struct kgem_bo *dst_bo, |
int dst_x, int dst_y, int src_x, int src_y, |
int w, int h); |
void (*flush)(struct sna *sna); |
void (*reset)(struct sna *sna); |
void (*fini)(struct sna *sna); |
// struct sna_alpha_cache { |
// struct kgem_bo *cache_bo; |
// struct kgem_bo *bo[256]; |
// } alpha_cache; |
struct sna_solid_cache { |
struct kgem_bo *cache_bo; |
uint32_t color[1024]; |
struct kgem_bo *bo[1024]; |
int last; |
int size; |
int dirty; |
} solid_cache; |
// struct { |
// struct sna_gradient_cache { |
// struct kgem_bo *bo; |
// int nstops; |
// PictGradientStop *stops; |
// } cache[GRADIENT_CACHE_SIZE]; |
// int size; |
// } gradient_cache; |
// struct sna_glyph_cache{ |
// PicturePtr picture; |
// struct sna_glyph **glyphs; |
// uint16_t count; |
// uint16_t evict; |
// } glyph[2]; |
uint16_t vertex_start; |
uint16_t vertex_index; |
uint16_t vertex_used; |
uint16_t vertex_size; |
uint16_t vertex_reloc[8]; |
struct kgem_bo *vbo; |
float *vertices; |
float vertex_data[1024]; |
}; |
enum { |
GEN6_WM_KERNEL_NOMASK = 0, |
GEN6_WM_KERNEL_NOMASK_PROJECTIVE, |
GEN6_KERNEL_COUNT |
}; |
struct gen6_render_state { |
struct kgem_bo *general_bo; |
uint32_t vs_state; |
uint32_t sf_state; |
uint32_t sf_mask_state; |
uint32_t wm_state; |
uint32_t wm_kernel[GEN6_KERNEL_COUNT]; |
uint32_t cc_vp; |
uint32_t cc_blend; |
uint32_t drawrect_offset; |
uint32_t drawrect_limit; |
uint32_t blend; |
uint32_t samplers; |
uint32_t kernel; |
uint16_t num_sf_outputs; |
uint16_t vb_id; |
uint16_t ve_id; |
uint16_t vertex_offset; |
uint16_t last_primitive; |
int16_t floats_per_vertex; |
uint16_t surface_table; |
Bool needs_invariant; |
}; |
enum { |
GEN7_WM_KERNEL_NOMASK = 0, |
GEN7_WM_KERNEL_NOMASK_PROJECTIVE, |
GEN7_WM_KERNEL_MASK, |
GEN7_WM_KERNEL_MASK_PROJECTIVE, |
GEN7_WM_KERNEL_MASKCA, |
GEN7_WM_KERNEL_MASKCA_PROJECTIVE, |
GEN7_WM_KERNEL_MASKCA_SRCALPHA, |
GEN7_WM_KERNEL_MASKCA_SRCALPHA_PROJECTIVE, |
GEN7_WM_KERNEL_VIDEO_PLANAR, |
GEN7_WM_KERNEL_VIDEO_PACKED, |
GEN7_KERNEL_COUNT |
}; |
struct sna_static_stream { |
uint32_t size, used; |
uint8_t *data; |
}; |
int sna_static_stream_init(struct sna_static_stream *stream); |
uint32_t sna_static_stream_add(struct sna_static_stream *stream, |
const void *data, uint32_t len, uint32_t align); |
void *sna_static_stream_map(struct sna_static_stream *stream, |
uint32_t len, uint32_t align); |
uint32_t sna_static_stream_offsetof(struct sna_static_stream *stream, |
void *ptr); |
struct kgem_bo *sna_static_stream_fini(struct sna *sna, |
struct sna_static_stream *stream); |
/* |
struct kgem_bo * |
sna_render_get_solid(struct sna *sna, |
uint32_t color); |
void |
sna_render_flush_solid(struct sna *sna); |
struct kgem_bo * |
sna_render_get_gradient(struct sna *sna, |
PictGradient *pattern); |
uint32_t sna_rgba_for_color(uint32_t color, int depth); |
Bool sna_picture_is_solid(PicturePtr picture, uint32_t *color); |
*/ |
void no_render_init(struct sna *sna); |
Bool gen2_render_init(struct sna *sna); |
Bool gen3_render_init(struct sna *sna); |
Bool gen4_render_init(struct sna *sna); |
Bool gen5_render_init(struct sna *sna); |
Bool gen6_render_init(struct sna *sna); |
Bool gen7_render_init(struct sna *sna); |
/* |
Bool sna_tiling_composite(uint32_t op, |
PicturePtr src, |
PicturePtr mask, |
PicturePtr dst, |
int16_t src_x, int16_t src_y, |
int16_t mask_x, int16_t mask_y, |
int16_t dst_x, int16_t dst_y, |
int16_t width, int16_t height, |
struct sna_composite_op *tmp); |
Bool sna_tiling_fill_boxes(struct sna *sna, |
CARD8 op, |
PictFormat format, |
const xRenderColor *color, |
PixmapPtr dst, struct kgem_bo *dst_bo, |
const BoxRec *box, int n); |
Bool sna_tiling_copy_boxes(struct sna *sna, uint8_t alu, |
PixmapPtr src, struct kgem_bo *src_bo, int16_t src_dx, int16_t src_dy, |
PixmapPtr dst, struct kgem_bo *dst_bo, int16_t dst_dx, int16_t dst_dy, |
const BoxRec *box, int n); |
Bool sna_tiling_blt_copy_boxes(struct sna *sna, uint8_t alu, |
struct kgem_bo *src_bo, int16_t src_dx, int16_t src_dy, |
struct kgem_bo *dst_bo, int16_t dst_dx, int16_t dst_dy, |
int bpp, const BoxRec *box, int nbox); |
Bool sna_blt_composite(struct sna *sna, |
uint32_t op, |
PicturePtr src, |
PicturePtr dst, |
int16_t src_x, int16_t src_y, |
int16_t dst_x, int16_t dst_y, |
int16_t width, int16_t height, |
struct sna_composite_op *tmp); |
bool sna_blt_fill(struct sna *sna, uint8_t alu, |
struct kgem_bo *bo, |
int bpp, |
uint32_t pixel, |
struct sna_fill_op *fill); |
bool sna_blt_copy(struct sna *sna, uint8_t alu, |
struct kgem_bo *src, |
struct kgem_bo *dst, |
int bpp, |
struct sna_copy_op *copy); |
Bool sna_blt_fill_boxes(struct sna *sna, uint8_t alu, |
struct kgem_bo *bo, |
int bpp, |
uint32_t pixel, |
const BoxRec *box, int n); |
Bool sna_blt_copy_boxes(struct sna *sna, uint8_t alu, |
struct kgem_bo *src_bo, int16_t src_dx, int16_t src_dy, |
struct kgem_bo *dst_bo, int16_t dst_dx, int16_t dst_dy, |
int bpp, |
const BoxRec *box, int n); |
Bool sna_blt_copy_boxes_fallback(struct sna *sna, uint8_t alu, |
PixmapPtr src, struct kgem_bo *src_bo, int16_t src_dx, int16_t src_dy, |
PixmapPtr dst, struct kgem_bo *dst_bo, int16_t dst_dx, int16_t dst_dy, |
const BoxRec *box, int nbox); |
Bool _sna_get_pixel_from_rgba(uint32_t *pixel, |
uint16_t red, |
uint16_t green, |
uint16_t blue, |
uint16_t alpha, |
uint32_t format); |
static inline Bool |
sna_get_pixel_from_rgba(uint32_t * pixel, |
uint16_t red, |
uint16_t green, |
uint16_t blue, |
uint16_t alpha, |
uint32_t format) |
{ |
switch (format) { |
case PICT_x8r8g8b8: |
alpha = 0xffff; |
case PICT_a8r8g8b8: |
*pixel = ((alpha >> 8 << 24) | |
(red >> 8 << 16) | |
(green & 0xff00) | |
(blue >> 8)); |
return TRUE; |
case PICT_a8: |
*pixel = alpha >> 8; |
return TRUE; |
} |
return _sna_get_pixel_from_rgba(pixel, red, green, blue, alpha, format); |
} |
int |
sna_render_pixmap_bo(struct sna *sna, |
struct sna_composite_channel *channel, |
PixmapPtr pixmap, |
int16_t x, int16_t y, |
int16_t w, int16_t h, |
int16_t dst_x, int16_t dst_y); |
bool |
sna_render_pixmap_partial(struct sna *sna, |
PixmapPtr pixmap, |
struct kgem_bo *bo, |
struct sna_composite_channel *channel, |
int16_t x, int16_t y, |
int16_t w, int16_t h); |
int |
sna_render_picture_extract(struct sna *sna, |
PicturePtr picture, |
struct sna_composite_channel *channel, |
int16_t x, int16_t y, |
int16_t w, int16_t h, |
int16_t dst_x, int16_t dst_y); |
int |
sna_render_picture_fixup(struct sna *sna, |
PicturePtr picture, |
struct sna_composite_channel *channel, |
int16_t x, int16_t y, |
int16_t w, int16_t h, |
int16_t dst_x, int16_t dst_y); |
int |
sna_render_picture_convert(struct sna *sna, |
PicturePtr picture, |
struct sna_composite_channel *channel, |
PixmapPtr pixmap, |
int16_t x, int16_t y, |
int16_t w, int16_t h, |
int16_t dst_x, int16_t dst_y); |
inline static void sna_render_composite_redirect_init(struct sna_composite_op *op) |
{ |
struct sna_composite_redirect *t = &op->redirect; |
t->real_bo = NULL; |
t->damage = NULL; |
} |
Bool |
sna_render_composite_redirect(struct sna *sna, |
struct sna_composite_op *op, |
int x, int y, int width, int height); |
void |
sna_render_composite_redirect_done(struct sna *sna, |
const struct sna_composite_op *op); |
bool |
sna_composite_mask_is_opaque(PicturePtr mask); |
*/ |
#endif /* SNA_RENDER_H */ |
/drivers/video/drm/i915/sna/sna_stream.c |
---|
0,0 → 1,108 |
/* |
* Copyright © 2011 Intel Corporation |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
* copy of this software and associated documentation files (the "Software"), |
* to deal in the Software without restriction, including without limitation |
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
* and/or sell copies of the Software, and to permit persons to whom the |
* Software is furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice (including the next |
* paragraph) shall be included in all copies or substantial portions of the |
* Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
* SOFTWARE. |
* |
* Authors: |
* Chris Wilson <chris@chris-wilson.co.uk> |
* |
*/ |
#include <linux/kernel.h> |
#include "../bitmap.h" |
#include "sna.h" |
#include "sna_render.h" |
#include <memory.h> |
#if DEBUG_STREAM |
#undef DBG |
#define DBG(x) ErrorF x |
#endif |
int sna_static_stream_init(struct sna_static_stream *stream) |
{ |
stream->used = 0; |
stream->size = 64*1024; |
stream->data = malloc(stream->size); |
return stream->data != NULL; |
} |
static uint32_t sna_static_stream_alloc(struct sna_static_stream *stream, |
uint32_t len, uint32_t align) |
{ |
uint32_t offset = ALIGN(stream->used, align); |
uint32_t size = offset + len; |
if (size > stream->size) { |
/* |
do |
stream->size *= 2; |
while (stream->size < size); |
stream->data = realloc(stream->data, stream->size); |
*/ |
dbgprintf("%s: EPIC FAIL\n", __FUNCTION__); |
return 0; |
} |
stream->used = size; |
return offset; |
} |
uint32_t sna_static_stream_add(struct sna_static_stream *stream, |
const void *data, uint32_t len, uint32_t align) |
{ |
uint32_t offset = sna_static_stream_alloc(stream, len, align); |
memcpy(stream->data + offset, data, len); |
return offset; |
} |
void *sna_static_stream_map(struct sna_static_stream *stream, |
uint32_t len, uint32_t align) |
{ |
uint32_t offset = sna_static_stream_alloc(stream, len, align); |
return memset(stream->data + offset, 0, len); |
} |
uint32_t sna_static_stream_offsetof(struct sna_static_stream *stream, void *ptr) |
{ |
return (uint8_t *)ptr - stream->data; |
} |
struct kgem_bo *sna_static_stream_fini(struct sna *sna, |
struct sna_static_stream *stream) |
{ |
struct kgem_bo *bo; |
DBG(("uploaded %d bytes of static state\n", stream->used)); |
bo = kgem_create_linear(&sna->kgem, stream->used); |
if (bo && !kgem_bo_write(&sna->kgem, bo, stream->data, stream->used)) { |
// kgem_bo_destroy(&sna->kgem, bo); |
return NULL; |
} |
free(stream->data); |
LEAVE(); |
return bo; |
} |
/drivers/video/drm/i915/sna |
---|
Property changes: |
Added: bugtraq:number |
+true |
\ No newline at end of property |