/drivers/video/drm/i915/Gtt/intel-gtt.c |
---|
280,10 → 280,11 |
} |
if (stolen_size > 0) { |
dbgprintf("detected %dK %s memory\n", |
dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n", |
stolen_size / KB(1), local ? "local" : "stolen"); |
} else { |
dbgprintf("no pre-allocated video memory detected\n"); |
dev_info(&intel_private.bridge_dev->dev, |
"no pre-allocated video memory detected\n"); |
stolen_size = 0; |
} |
354,7 → 355,8 |
size = KB(1024 + 512); |
break; |
default: |
dbgprintf("unknown page table size, assuming 512KB\n"); |
dev_info(&intel_private.pcidev->dev, |
"unknown page table size, assuming 512KB\n"); |
size = KB(512); |
} |
529,7 → 531,8 |
pci_read_config_word(intel_private.bridge_dev, |
I830_GMCH_CTRL, &gmch_ctrl); |
if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) { |
dbgprintf("failed to enable the GTT: GMCH_CTRL=%x\n", |
dev_err(&intel_private.pcidev->dev, |
"failed to enable the GTT: GMCH_CTRL=%x\n", |
gmch_ctrl); |
return false; |
} |
544,7 → 547,8 |
reg = intel_private.registers+I810_PGETBL_CTL; |
writel(intel_private.PGETBL_save, reg); |
if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) { |
dbgprintf("failed to enable the GTT: PGETBL=%x [expected %x]\n", |
dev_err(&intel_private.pcidev->dev, |
"failed to enable the GTT: PGETBL=%x [expected %x]\n", |
readl(reg), intel_private.PGETBL_save); |
return false; |
} |
556,7 → 560,32 |
} |
void intel_gtt_insert_pages(unsigned int first_entry, unsigned int num_entries, |
struct page **pages, unsigned int flags) |
{ |
int i, j; |
for (i = 0, j = first_entry; i < num_entries; i++, j++) { |
dma_addr_t addr = (dma_addr_t)(pages[i]); |
intel_private.driver->write_entry(addr, |
j, flags); |
} |
readl(intel_private.gtt+j-1); |
} |
void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries) |
{ |
unsigned int i; |
for (i = first_entry; i < (first_entry + num_entries); i++) { |
intel_private.driver->write_entry(intel_private.scratch_page_dma, |
i, 0); |
} |
readl(intel_private.gtt+i-1); |
} |
static void intel_i9xx_setup_flush(void) |
{ |
/* return if already configured */ |
766,7 → 795,13 |
return &intel_private.base; |
} |
void intel_gtt_chipset_flush(void) |
{ |
if (intel_private.driver->chipset_flush) |
intel_private.driver->chipset_flush(); |
} |
phys_addr_t get_bus_addr(void) |
{ |
return intel_private.gma_bus_addr; |
/drivers/video/drm/i915/i915_dma.c |
---|
164,6 → 164,7 |
#define LFB_SIZE 0xC00000 |
static int i915_load_gem_init(struct drm_device *dev) |
{ |
181,8 → 182,6 |
/* Basic memrange allocator for stolen space */ |
drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size); |
//0xC00000 >> PAGE_SHIFT |
/* Let GEM Manage all of the aperture. |
* |
* However, leave one page at the end still bound to the scratch page. |
192,13 → 191,13 |
* at the last page of the aperture. One page should be enough to |
* keep any prefetching inside of the aperture. |
*/ |
// i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE); |
i915_gem_do_init(dev, LFB_SIZE, mappable_size, gtt_size - PAGE_SIZE - LFB_SIZE); |
// mutex_lock(&dev->struct_mutex); |
// ret = i915_gem_init_ringbuffer(dev); |
// mutex_unlock(&dev->struct_mutex); |
// if (ret) |
// return ret; |
mutex_lock(&dev->struct_mutex); |
ret = i915_gem_init_ringbuffer(dev); |
mutex_unlock(&dev->struct_mutex); |
if (ret) |
return ret; |
/* Try to set up FBC with a reasonable compressed buffer size */ |
// if (I915_HAS_FBC(dev) && i915_powersave) { |
240,13 → 239,11 |
if (ret) |
goto cleanup_vga_switcheroo; |
#if 0 |
intel_modeset_gem_init(dev); |
ret = drm_irq_install(dev); |
if (ret) |
goto cleanup_gem; |
// ret = drm_irq_install(dev); |
// if (ret) |
// goto cleanup_gem; |
/* Always safe in the mode setting case. */ |
/* FIXME: do pre/post-mode set stuff in core KMS code */ |
256,13 → 253,11 |
if (ret) |
goto cleanup_irq; |
drm_kms_helper_poll_init(dev); |
// drm_kms_helper_poll_init(dev); |
/* We're off and running w/KMS */ |
dev_priv->mm.suspended = 0; |
#endif |
return 0; |
cleanup_irq: |
/drivers/video/drm/i915/i915_drv.c |
---|
49,7 → 49,7 |
int i915_panel_ignore_lid __read_mostly = 0; |
unsigned int i915_powersave __read_mostly = 1; |
unsigned int i915_powersave __read_mostly = 0; |
unsigned int i915_enable_rc6 __read_mostly = 0; |
/drivers/video/drm/i915/i915_drv.h |
---|
35,7 → 35,7 |
#include "intel_ringbuffer.h" |
//#include <linux/io-mapping.h> |
#include <linux/i2c.h> |
//#include <drm/intel-gtt.h> |
#include <drm/intel-gtt.h> |
//#include <linux/backlight.h> |
#include <linux/spinlock.h> |
293,8 → 293,8 |
drm_dma_handle_t *status_page_dmah; |
// uint32_t counter; |
// drm_local_map_t hws_map; |
// struct drm_i915_gem_object *pwrctx; |
// struct drm_i915_gem_object *renderctx; |
struct drm_i915_gem_object *pwrctx; |
struct drm_i915_gem_object *renderctx; |
// struct resource mch_res; |
552,7 → 552,7 |
/** Memory allocator for GTT stolen memory */ |
struct drm_mm stolen; |
/** Memory allocator for GTT */ |
// struct drm_mm gtt_space; |
struct drm_mm gtt_space; |
/** List of all objects in gtt_space. Used to restore gtt |
* mappings on resume */ |
struct list_head gtt_list; |
722,7 → 722,7 |
unsigned long last_gpu_reset; |
/* list of fbdev register on this device */ |
// struct intel_fbdev *fbdev; |
struct intel_fbdev *fbdev; |
// struct backlight_device *backlight; |
1154,14 → 1154,14 |
// return (int32_t)(seq1 - seq2) >= 0; |
//} |
//static inline u32 |
//i915_gem_next_request_seqno(struct intel_ring_buffer *ring) |
//{ |
// drm_i915_private_t *dev_priv = ring->dev->dev_private; |
// return ring->outstanding_lazy_request = dev_priv->next_seqno; |
//} |
static inline u32 |
i915_gem_next_request_seqno(struct intel_ring_buffer *ring) |
{ |
drm_i915_private_t *dev_priv = ring->dev->dev_private; |
return ring->outstanding_lazy_request = dev_priv->next_seqno; |
} |
/* |
void i915_gem_retire_requests(struct drm_device *dev); |
void i915_gem_reset(struct drm_device *dev); |
void i915_gem_clflush_object(struct drm_i915_gem_object *obj); |
1206,8 → 1206,8 |
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
enum i915_cache_level cache_level); |
*/ |
/* i915_gem_gtt.c */ |
void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj); |
/drivers/video/drm/i915/i915_gem.c |
---|
36,13 → 36,985 |
//#include <linux/swap.h> |
#include <linux/pci.h> |
#define MAX_ERRNO 4095 |
#define IS_ERR_VALUE(x) unlikely((x) >= (unsigned long)-MAX_ERRNO) |
static inline long IS_ERR(const void *ptr) |
{ |
return IS_ERR_VALUE((unsigned long)ptr); |
} |
static inline void *ERR_PTR(long error) |
{ |
return (void *) error; |
} |
static inline long PTR_ERR(const void *ptr) |
{ |
return (long) ptr; |
} |
/** |
* Initialize an already allocated GEM object of the specified size with |
* shmfs backing store. |
*/ |
int drm_gem_object_init(struct drm_device *dev, |
struct drm_gem_object *obj, size_t size) |
{ |
BUG_ON((size & (PAGE_SIZE - 1)) != 0); |
obj->dev = dev; |
atomic_set(&obj->handle_count, 0); |
obj->size = size; |
return 0; |
} |
#define I915_EXEC_CONSTANTS_MASK (3<<6) |
#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ |
#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) |
#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ |
static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj); |
static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
static __must_check int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, |
bool write); |
static __must_check int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, |
uint64_t offset, |
uint64_t size); |
static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj); |
static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
unsigned alignment, |
bool map_and_fenceable); |
static void i915_gem_clear_fence_reg(struct drm_device *dev, |
struct drm_i915_fence_reg *reg); |
static int i915_gem_phys_pwrite(struct drm_device *dev, |
struct drm_i915_gem_object *obj, |
struct drm_i915_gem_pwrite *args, |
struct drm_file *file); |
static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj); |
static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
struct shrink_control *sc); |
/* some bookkeeping */ |
static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
size_t size) |
{ |
dev_priv->mm.object_count++; |
dev_priv->mm.object_memory += size; |
} |
static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
size_t size) |
{ |
dev_priv->mm.object_count--; |
dev_priv->mm.object_memory -= size; |
} |
#if 0 |
static int |
i915_gem_wait_for_error(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct completion *x = &dev_priv->error_completion; |
unsigned long flags; |
int ret; |
if (!atomic_read(&dev_priv->mm.wedged)) |
return 0; |
ret = wait_for_completion_interruptible(x); |
if (ret) |
return ret; |
if (atomic_read(&dev_priv->mm.wedged)) { |
/* GPU is hung, bump the completion count to account for |
* the token we just consumed so that we never hit zero and |
* end up waiting upon a subsequent completion event that |
* will never happen. |
*/ |
spin_lock_irqsave(&x->wait.lock, flags); |
x->done++; |
spin_unlock_irqrestore(&x->wait.lock, flags); |
} |
return 0; |
} |
int i915_mutex_lock_interruptible(struct drm_device *dev) |
{ |
int ret; |
ret = i915_gem_wait_for_error(dev); |
if (ret) |
return ret; |
ret = mutex_lock_interruptible(&dev->struct_mutex); |
if (ret) |
return ret; |
WARN_ON(i915_verify_lists(dev)); |
return 0; |
} |
static inline bool |
i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
{ |
return obj->gtt_space && !obj->active && obj->pin_count == 0; |
} |
#endif |
void i915_gem_do_init(struct drm_device *dev, |
unsigned long start, |
unsigned long mappable_end, |
unsigned long end) |
{ |
drm_i915_private_t *dev_priv = dev->dev_private; |
drm_mm_init(&dev_priv->mm.gtt_space, start, end - start); |
dev_priv->mm.gtt_start = start; |
dev_priv->mm.gtt_mappable_end = mappable_end; |
dev_priv->mm.gtt_end = end; |
dev_priv->mm.gtt_total = end - start; |
dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start; |
/* Take over this portion of the GTT */ |
intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE); |
} |
#if 0 |
int |
i915_gem_init_ioctl(struct drm_device *dev, void *data, |
struct drm_file *file) |
{ |
struct drm_i915_gem_init *args = data; |
if (args->gtt_start >= args->gtt_end || |
(args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) |
return -EINVAL; |
mutex_lock(&dev->struct_mutex); |
i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end); |
mutex_unlock(&dev->struct_mutex); |
return 0; |
} |
int |
i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
struct drm_file *file) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct drm_i915_gem_get_aperture *args = data; |
struct drm_i915_gem_object *obj; |
size_t pinned; |
if (!(dev->driver->driver_features & DRIVER_GEM)) |
return -ENODEV; |
pinned = 0; |
mutex_lock(&dev->struct_mutex); |
list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) |
pinned += obj->gtt_space->size; |
mutex_unlock(&dev->struct_mutex); |
args->aper_size = dev_priv->mm.gtt_total; |
args->aper_available_size = args->aper_size -pinned; |
return 0; |
} |
static int |
i915_gem_create(struct drm_file *file, |
struct drm_device *dev, |
uint64_t size, |
uint32_t *handle_p) |
{ |
struct drm_i915_gem_object *obj; |
int ret; |
u32 handle; |
size = roundup(size, PAGE_SIZE); |
/* Allocate the new object */ |
obj = i915_gem_alloc_object(dev, size); |
if (obj == NULL) |
return -ENOMEM; |
ret = drm_gem_handle_create(file, &obj->base, &handle); |
if (ret) { |
drm_gem_object_release(&obj->base); |
i915_gem_info_remove_obj(dev->dev_private, obj->base.size); |
kfree(obj); |
return ret; |
} |
/* drop reference from allocate - handle holds it now */ |
drm_gem_object_unreference(&obj->base); |
// trace_i915_gem_object_create(obj); |
*handle_p = handle; |
return 0; |
} |
int |
i915_gem_dumb_create(struct drm_file *file, |
struct drm_device *dev, |
struct drm_mode_create_dumb *args) |
{ |
/* have to work out size/pitch and return them */ |
args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
args->size = args->pitch * args->height; |
return i915_gem_create(file, dev, |
args->size, &args->handle); |
} |
int i915_gem_dumb_destroy(struct drm_file *file, |
struct drm_device *dev, |
uint32_t handle) |
{ |
return drm_gem_handle_delete(file, handle); |
} |
/** |
* Creates a new mm object and returns a handle to it. |
*/ |
int |
i915_gem_create_ioctl(struct drm_device *dev, void *data, |
struct drm_file *file) |
{ |
struct drm_i915_gem_create *args = data; |
return i915_gem_create(file, dev, |
args->size, &args->handle); |
} |
static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
{ |
drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
obj->tiling_mode != I915_TILING_NONE; |
} |
static inline void |
slow_shmem_copy(struct page *dst_page, |
int dst_offset, |
struct page *src_page, |
int src_offset, |
int length) |
{ |
char *dst_vaddr, *src_vaddr; |
dst_vaddr = kmap(dst_page); |
src_vaddr = kmap(src_page); |
memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); |
kunmap(src_page); |
kunmap(dst_page); |
} |
static inline void |
slow_shmem_bit17_copy(struct page *gpu_page, |
int gpu_offset, |
struct page *cpu_page, |
int cpu_offset, |
int length, |
int is_read) |
{ |
char *gpu_vaddr, *cpu_vaddr; |
/* Use the unswizzled path if this page isn't affected. */ |
if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { |
if (is_read) |
return slow_shmem_copy(cpu_page, cpu_offset, |
gpu_page, gpu_offset, length); |
else |
return slow_shmem_copy(gpu_page, gpu_offset, |
cpu_page, cpu_offset, length); |
} |
gpu_vaddr = kmap(gpu_page); |
cpu_vaddr = kmap(cpu_page); |
/* Copy the data, XORing A6 with A17 (1). The user already knows he's |
* XORing with the other bits (A9 for Y, A9 and A10 for X) |
*/ |
while (length > 0) { |
int cacheline_end = ALIGN(gpu_offset + 1, 64); |
int this_length = min(cacheline_end - gpu_offset, length); |
int swizzled_gpu_offset = gpu_offset ^ 64; |
if (is_read) { |
memcpy(cpu_vaddr + cpu_offset, |
gpu_vaddr + swizzled_gpu_offset, |
this_length); |
} else { |
memcpy(gpu_vaddr + swizzled_gpu_offset, |
cpu_vaddr + cpu_offset, |
this_length); |
} |
cpu_offset += this_length; |
gpu_offset += this_length; |
length -= this_length; |
} |
kunmap(cpu_page); |
kunmap(gpu_page); |
} |
/** |
* This is the fast shmem pread path, which attempts to copy_from_user directly |
* from the backing pages of the object to the user's address space. On a |
* fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). |
*/ |
static int |
i915_gem_shmem_pread_fast(struct drm_device *dev, |
struct drm_i915_gem_object *obj, |
struct drm_i915_gem_pread *args, |
struct drm_file *file) |
{ |
struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
ssize_t remain; |
loff_t offset; |
char __user *user_data; |
int page_offset, page_length; |
user_data = (char __user *) (uintptr_t) args->data_ptr; |
remain = args->size; |
offset = args->offset; |
while (remain > 0) { |
struct page *page; |
char *vaddr; |
int ret; |
/* Operation in this page |
* |
* page_offset = offset within page |
* page_length = bytes to copy for this page |
*/ |
page_offset = offset_in_page(offset); |
page_length = remain; |
if ((page_offset + remain) > PAGE_SIZE) |
page_length = PAGE_SIZE - page_offset; |
page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
if (IS_ERR(page)) |
return PTR_ERR(page); |
vaddr = kmap_atomic(page); |
ret = __copy_to_user_inatomic(user_data, |
vaddr + page_offset, |
page_length); |
kunmap_atomic(vaddr); |
mark_page_accessed(page); |
page_cache_release(page); |
if (ret) |
return -EFAULT; |
remain -= page_length; |
user_data += page_length; |
offset += page_length; |
} |
return 0; |
} |
/** |
* This is the fallback shmem pread path, which allocates temporary storage |
* in kernel space to copy_to_user into outside of the struct_mutex, so we |
* can copy out of the object's backing pages while holding the struct mutex |
* and not take page faults. |
*/ |
static int |
i915_gem_shmem_pread_slow(struct drm_device *dev, |
struct drm_i915_gem_object *obj, |
struct drm_i915_gem_pread *args, |
struct drm_file *file) |
{ |
struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
struct mm_struct *mm = current->mm; |
struct page **user_pages; |
ssize_t remain; |
loff_t offset, pinned_pages, i; |
loff_t first_data_page, last_data_page, num_pages; |
int shmem_page_offset; |
int data_page_index, data_page_offset; |
int page_length; |
int ret; |
uint64_t data_ptr = args->data_ptr; |
int do_bit17_swizzling; |
remain = args->size; |
/* Pin the user pages containing the data. We can't fault while |
* holding the struct mutex, yet we want to hold it while |
* dereferencing the user data. |
*/ |
first_data_page = data_ptr / PAGE_SIZE; |
last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
num_pages = last_data_page - first_data_page + 1; |
user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
if (user_pages == NULL) |
return -ENOMEM; |
mutex_unlock(&dev->struct_mutex); |
down_read(&mm->mmap_sem); |
pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
num_pages, 1, 0, user_pages, NULL); |
up_read(&mm->mmap_sem); |
mutex_lock(&dev->struct_mutex); |
if (pinned_pages < num_pages) { |
ret = -EFAULT; |
goto out; |
} |
ret = i915_gem_object_set_cpu_read_domain_range(obj, |
args->offset, |
args->size); |
if (ret) |
goto out; |
do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
offset = args->offset; |
while (remain > 0) { |
struct page *page; |
/* Operation in this page |
* |
* shmem_page_offset = offset within page in shmem file |
* data_page_index = page number in get_user_pages return |
* data_page_offset = offset with data_page_index page. |
* page_length = bytes to copy for this page |
*/ |
shmem_page_offset = offset_in_page(offset); |
data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
data_page_offset = offset_in_page(data_ptr); |
page_length = remain; |
if ((shmem_page_offset + page_length) > PAGE_SIZE) |
page_length = PAGE_SIZE - shmem_page_offset; |
if ((data_page_offset + page_length) > PAGE_SIZE) |
page_length = PAGE_SIZE - data_page_offset; |
page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
if (IS_ERR(page)) { |
ret = PTR_ERR(page); |
goto out; |
} |
if (do_bit17_swizzling) { |
slow_shmem_bit17_copy(page, |
shmem_page_offset, |
user_pages[data_page_index], |
data_page_offset, |
page_length, |
1); |
} else { |
slow_shmem_copy(user_pages[data_page_index], |
data_page_offset, |
page, |
shmem_page_offset, |
page_length); |
} |
mark_page_accessed(page); |
page_cache_release(page); |
remain -= page_length; |
data_ptr += page_length; |
offset += page_length; |
} |
out: |
for (i = 0; i < pinned_pages; i++) { |
SetPageDirty(user_pages[i]); |
mark_page_accessed(user_pages[i]); |
page_cache_release(user_pages[i]); |
} |
drm_free_large(user_pages); |
return ret; |
} |
#endif |
static uint32_t |
i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
{ |
uint32_t gtt_size; |
if (INTEL_INFO(dev)->gen >= 4 || |
tiling_mode == I915_TILING_NONE) |
return size; |
/* Previous chips need a power-of-two fence region when tiling */ |
if (INTEL_INFO(dev)->gen == 3) |
gtt_size = 1024*1024; |
else |
gtt_size = 512*1024; |
while (gtt_size < size) |
gtt_size <<= 1; |
return gtt_size; |
} |
/** |
* i915_gem_get_gtt_alignment - return required GTT alignment for an object |
* @obj: object to check |
* |
* Return the required GTT alignment for an object, taking into account |
* potential fence register mapping. |
*/ |
static uint32_t |
i915_gem_get_gtt_alignment(struct drm_device *dev, |
uint32_t size, |
int tiling_mode) |
{ |
/* |
* Minimum alignment is 4k (GTT page size), but might be greater |
* if a fence register is needed for the object. |
*/ |
if (INTEL_INFO(dev)->gen >= 4 || |
tiling_mode == I915_TILING_NONE) |
return 4096; |
/* |
* Previous chips need to be aligned to the size of the smallest |
* fence register that can contain the object. |
*/ |
return i915_gem_get_gtt_size(dev, size, tiling_mode); |
} |
/** |
* i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an |
* unfenced object |
* @dev: the device |
* @size: size of the object |
* @tiling_mode: tiling mode of the object |
* |
* Return the required GTT alignment for an object, only taking into account |
* unfenced tiled surface requirements. |
*/ |
uint32_t |
i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
uint32_t size, |
int tiling_mode) |
{ |
/* |
* Minimum alignment is 4k (GTT page size) for sane hw. |
*/ |
if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || |
tiling_mode == I915_TILING_NONE) |
return 4096; |
/* Previous hardware however needs to be aligned to a power-of-two |
* tile height. The simplest method for determining this is to reuse |
* the power-of-tile object size. |
*/ |
return i915_gem_get_gtt_size(dev, size, tiling_mode); |
} |
static int |
i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
gfp_t gfpmask) |
{ |
int page_count, i; |
struct page *page; |
ENTER(); |
/* Get the list of pages out of our struct file. They'll be pinned |
* at this point until we release them. |
*/ |
page_count = obj->base.size / PAGE_SIZE; |
BUG_ON(obj->pages != NULL); |
obj->pages = malloc(page_count * sizeof(struct page *)); |
if (obj->pages == NULL) |
return -ENOMEM; |
for (i = 0; i < page_count; i++) { |
page = (struct page*)AllocPage(); // oh-oh |
if (IS_ERR(page)) |
goto err_pages; |
obj->pages[i] = page; |
} |
// if (obj->tiling_mode != I915_TILING_NONE) |
// i915_gem_object_do_bit_17_swizzle(obj); |
LEAVE(); |
return 0; |
err_pages: |
// while (i--) |
// page_cache_release(obj->pages[i]); |
free(obj->pages); |
obj->pages = NULL; |
return PTR_ERR(page); |
} |
static void |
i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
{ |
int page_count = obj->base.size / PAGE_SIZE; |
int i; |
BUG_ON(obj->madv == __I915_MADV_PURGED); |
// if (obj->tiling_mode != I915_TILING_NONE) |
// i915_gem_object_save_bit_17_swizzle(obj); |
if (obj->madv == I915_MADV_DONTNEED) |
obj->dirty = 0; |
/* It's a swap!!! |
for (i = 0; i < page_count; i++) { |
if (obj->dirty) |
set_page_dirty(obj->pages[i]); |
if (obj->madv == I915_MADV_WILLNEED) |
mark_page_accessed(obj->pages[i]); |
//page_cache_release(obj->pages[i]); |
} |
obj->dirty = 0; |
*/ |
free(obj->pages); |
obj->pages = NULL; |
} |
void |
i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
struct intel_ring_buffer *ring, |
u32 seqno) |
{ |
struct drm_device *dev = obj->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
BUG_ON(ring == NULL); |
obj->ring = ring; |
/* Add a reference if we're newly entering the active list. */ |
if (!obj->active) { |
// drm_gem_object_reference(&obj->base); |
obj->active = 1; |
} |
/* Move from whatever list we were on to the tail of execution. */ |
list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
list_move_tail(&obj->ring_list, &ring->active_list); |
obj->last_rendering_seqno = seqno; |
if (obj->fenced_gpu_access) { |
struct drm_i915_fence_reg *reg; |
BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE); |
obj->last_fenced_seqno = seqno; |
obj->last_fenced_ring = ring; |
reg = &dev_priv->fence_regs[obj->fence_reg]; |
list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
} |
} |
static void |
i915_gem_process_flushing_list(struct intel_ring_buffer *ring, |
uint32_t flush_domains) |
{ |
struct drm_i915_gem_object *obj, *next; |
list_for_each_entry_safe(obj, next, |
&ring->gpu_write_list, |
gpu_write_list) { |
if (obj->base.write_domain & flush_domains) { |
uint32_t old_write_domain = obj->base.write_domain; |
obj->base.write_domain = 0; |
list_del_init(&obj->gpu_write_list); |
i915_gem_object_move_to_active(obj, ring, |
i915_gem_next_request_seqno(ring)); |
// trace_i915_gem_object_change_domain(obj, |
// obj->base.read_domains, |
// old_write_domain); |
} |
} |
} |
/** |
* Ensures that all rendering to the object has completed and the object is |
* safe to unbind from the GTT or access from the CPU. |
*/ |
int |
i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj) |
{ |
int ret; |
/* This function only exists to support waiting for existing rendering, |
* not for emitting required flushes. |
*/ |
BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0); |
/* If there is rendering queued on the buffer being evicted, wait for |
* it. |
*/ |
// if (obj->active) { |
// ret = i915_wait_request(obj->ring, obj->last_rendering_seqno); |
// if (ret) |
// return ret; |
// } |
return 0; |
} |
int |
i915_gem_flush_ring(struct intel_ring_buffer *ring, |
uint32_t invalidate_domains, |
uint32_t flush_domains) |
{ |
int ret; |
if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0) |
return 0; |
// trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains); |
ret = ring->flush(ring, invalidate_domains, flush_domains); |
if (ret) |
return ret; |
if (flush_domains & I915_GEM_GPU_DOMAINS) |
i915_gem_process_flushing_list(ring, flush_domains); |
return 0; |
} |
/** |
* i915_gem_clear_fence_reg - clear out fence register info |
* @obj: object to clear |
* |
81,8 → 1053,619 |
reg->setup_seqno = 0; |
} |
/** |
* Finds free space in the GTT aperture and binds the object there. |
*/ |
static int |
i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
unsigned alignment, |
bool map_and_fenceable) |
{ |
struct drm_device *dev = obj->base.dev; |
drm_i915_private_t *dev_priv = dev->dev_private; |
struct drm_mm_node *free_space; |
gfp_t gfpmask = 0; //__GFP_NORETRY | __GFP_NOWARN; |
u32 size, fence_size, fence_alignment, unfenced_alignment; |
bool mappable, fenceable; |
int ret; |
ENTER(); |
if (obj->madv != I915_MADV_WILLNEED) { |
DRM_ERROR("Attempting to bind a purgeable object\n"); |
return -EINVAL; |
} |
fence_size = i915_gem_get_gtt_size(dev, |
obj->base.size, |
obj->tiling_mode); |
fence_alignment = i915_gem_get_gtt_alignment(dev, |
obj->base.size, |
obj->tiling_mode); |
unfenced_alignment = |
i915_gem_get_unfenced_gtt_alignment(dev, |
obj->base.size, |
obj->tiling_mode); |
if (alignment == 0) |
alignment = map_and_fenceable ? fence_alignment : |
unfenced_alignment; |
if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
return -EINVAL; |
} |
size = map_and_fenceable ? fence_size : obj->base.size; |
/* If the object is bigger than the entire aperture, reject it early |
* before evicting everything in a vain attempt to find space. |
*/ |
if (obj->base.size > |
(map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
return -E2BIG; |
} |
search_free: |
if (map_and_fenceable) |
free_space = |
drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, |
size, alignment, 0, |
dev_priv->mm.gtt_mappable_end, |
0); |
else |
free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, |
size, alignment, 0); |
if (free_space != NULL) { |
if (map_and_fenceable) |
obj->gtt_space = |
drm_mm_get_block_range_generic(free_space, |
size, alignment, 0, |
dev_priv->mm.gtt_mappable_end, |
0); |
else |
obj->gtt_space = |
drm_mm_get_block(free_space, size, alignment); |
} |
if (obj->gtt_space == NULL) { |
/* If the gtt is empty and we're still having trouble |
* fitting our object in, we're out of memory. |
*/ |
ret = 1; //i915_gem_evict_something(dev, size, alignment, |
// map_and_fenceable); |
if (ret) |
return ret; |
goto search_free; |
} |
ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
if (ret) { |
drm_mm_put_block(obj->gtt_space); |
obj->gtt_space = NULL; |
#if 0 |
if (ret == -ENOMEM) { |
/* first try to reclaim some memory by clearing the GTT */ |
ret = i915_gem_evict_everything(dev, false); |
if (ret) { |
/* now try to shrink everyone else */ |
if (gfpmask) { |
gfpmask = 0; |
goto search_free; |
} |
return -ENOMEM; |
} |
goto search_free; |
} |
#endif |
return ret; |
} |
ret = i915_gem_gtt_bind_object(obj); |
if (ret) { |
// i915_gem_object_put_pages_gtt(obj); |
drm_mm_put_block(obj->gtt_space); |
obj->gtt_space = NULL; |
// if (i915_gem_evict_everything(dev, false)) |
return ret; |
// goto search_free; |
} |
list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list); |
list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
/* Assert that the object is not currently in any GPU domain. As it |
* wasn't in the GTT, there shouldn't be any way it could have been in |
* a GPU cache |
*/ |
BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); |
obj->gtt_offset = obj->gtt_space->start; |
fenceable = |
obj->gtt_space->size == fence_size && |
(obj->gtt_space->start & (fence_alignment -1)) == 0; |
mappable = |
obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
obj->map_and_fenceable = mappable && fenceable; |
LEAVE(); |
// trace_i915_gem_object_bind(obj, map_and_fenceable); |
return 0; |
} |
void |
i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
{ |
/* If we don't have a page list set up, then we're not pinned |
* to GPU, and we can ignore the cache flush because it'll happen |
* again at bind time. |
*/ |
if (obj->pages == NULL) |
return; |
/* If the GPU is snooping the contents of the CPU cache, |
* we do not need to manually clear the CPU cache lines. However, |
* the caches are only snooped when the render cache is |
* flushed/invalidated. As we always have to emit invalidations |
* and flushes when moving into and out of the RENDER domain, correct |
* snooping behaviour occurs naturally as the result of our domain |
* tracking. |
*/ |
if (obj->cache_level != I915_CACHE_NONE) |
return; |
// trace_i915_gem_object_clflush(obj); |
// drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
mb(); |
__asm__ ("wbinvd"); // this is really ugly |
mb(); |
} |
/** Flushes any GPU write domain for the object if it's dirty. */ |
static int |
i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj) |
{ |
if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) |
return 0; |
/* Queue the GPU write cache flushing we need. */ |
return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
} |
/** Flushes the CPU write domain for the object if it's dirty. */ |
static void |
i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
{ |
uint32_t old_write_domain; |
if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
return; |
i915_gem_clflush_object(obj); |
intel_gtt_chipset_flush(); |
old_write_domain = obj->base.write_domain; |
obj->base.write_domain = 0; |
// trace_i915_gem_object_change_domain(obj, |
// obj->base.read_domains, |
// old_write_domain); |
} |
/** |
* Moves a single object to the GTT read, and possibly write domain. |
* |
* This function returns when the move is complete, including waiting on |
* flushes to occur. |
*/ |
int |
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
{ |
uint32_t old_write_domain, old_read_domains; |
int ret; |
/* Not valid to be called on unbound objects. */ |
if (obj->gtt_space == NULL) |
return -EINVAL; |
if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
return 0; |
ret = i915_gem_object_flush_gpu_write_domain(obj); |
if (ret) |
return ret; |
if (obj->pending_gpu_write || write) { |
ret = i915_gem_object_wait_rendering(obj); |
if (ret) |
return ret; |
} |
i915_gem_object_flush_cpu_write_domain(obj); |
old_write_domain = obj->base.write_domain; |
old_read_domains = obj->base.read_domains; |
/* It should now be out of any other write domains, and we can update |
* the domain values for our changes. |
*/ |
BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
if (write) { |
obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
obj->base.write_domain = I915_GEM_DOMAIN_GTT; |
obj->dirty = 1; |
} |
return 0; |
} |
int |
i915_gem_object_pin(struct drm_i915_gem_object *obj, |
uint32_t alignment, |
bool map_and_fenceable) |
{ |
struct drm_device *dev = obj->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
int ret; |
ENTER(); |
BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
// WARN_ON(i915_verify_lists(dev)); |
#if 0 |
if (obj->gtt_space != NULL) { |
if ((alignment && obj->gtt_offset & (alignment - 1)) || |
(map_and_fenceable && !obj->map_and_fenceable)) { |
WARN(obj->pin_count, |
"bo is already pinned with incorrect alignment:" |
" offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
" obj->map_and_fenceable=%d\n", |
obj->gtt_offset, alignment, |
map_and_fenceable, |
obj->map_and_fenceable); |
ret = i915_gem_object_unbind(obj); |
if (ret) |
return ret; |
} |
} |
#endif |
if (obj->gtt_space == NULL) { |
ret = i915_gem_object_bind_to_gtt(obj, alignment, |
map_and_fenceable); |
if (ret) |
return ret; |
} |
if (obj->pin_count++ == 0) { |
if (!obj->active) |
list_move_tail(&obj->mm_list, |
&dev_priv->mm.pinned_list); |
} |
obj->pin_mappable |= map_and_fenceable; |
LEAVE(); |
// WARN_ON(i915_verify_lists(dev)); |
return 0; |
} |
struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
size_t size) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct drm_i915_gem_object *obj; |
ENTER(); |
obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
if (obj == NULL) |
return NULL; |
if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
kfree(obj); |
return NULL; |
} |
i915_gem_info_add_obj(dev_priv, size); |
obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
if (IS_GEN6(dev)) { |
/* On Gen6, we can have the GPU use the LLC (the CPU |
* cache) for about a 10% performance improvement |
* compared to uncached. Graphics requests other than |
* display scanout are coherent with the CPU in |
* accessing this cache. This means in this mode we |
* don't need to clflush on the CPU side, and on the |
* GPU side we only need to flush internal caches to |
* get data visible to the CPU. |
* |
* However, we maintain the display planes as UC, and so |
* need to rebind when first used as such. |
*/ |
obj->cache_level = I915_CACHE_LLC; |
} else |
obj->cache_level = I915_CACHE_NONE; |
obj->base.driver_private = NULL; |
obj->fence_reg = I915_FENCE_REG_NONE; |
INIT_LIST_HEAD(&obj->mm_list); |
INIT_LIST_HEAD(&obj->gtt_list); |
INIT_LIST_HEAD(&obj->ring_list); |
INIT_LIST_HEAD(&obj->exec_list); |
INIT_LIST_HEAD(&obj->gpu_write_list); |
obj->madv = I915_MADV_WILLNEED; |
/* Avoid an unnecessary call to unbind on the first bind. */ |
obj->map_and_fenceable = true; |
LEAVE(); |
return obj; |
} |
int |
i915_gem_init_ringbuffer(struct drm_device *dev) |
{ |
drm_i915_private_t *dev_priv = dev->dev_private; |
int ret; |
ENTER(); |
ret = intel_init_render_ring_buffer(dev); |
if (ret) |
return ret; |
if (HAS_BSD(dev)) { |
ret = intel_init_bsd_ring_buffer(dev); |
if (ret) |
goto cleanup_render_ring; |
} |
if (HAS_BLT(dev)) { |
ret = intel_init_blt_ring_buffer(dev); |
if (ret) |
goto cleanup_bsd_ring; |
} |
dev_priv->next_seqno = 1; |
LEAVE(); |
return 0; |
cleanup_bsd_ring: |
intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
cleanup_render_ring: |
intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
return ret; |
} |
#if 0 |
void |
i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
{ |
drm_i915_private_t *dev_priv = dev->dev_private; |
int i; |
for (i = 0; i < I915_NUM_RINGS; i++) |
intel_cleanup_ring_buffer(&dev_priv->ring[i]); |
} |
int |
i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
struct drm_file *file_priv) |
{ |
drm_i915_private_t *dev_priv = dev->dev_private; |
int ret, i; |
if (drm_core_check_feature(dev, DRIVER_MODESET)) |
return 0; |
if (atomic_read(&dev_priv->mm.wedged)) { |
DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
atomic_set(&dev_priv->mm.wedged, 0); |
} |
mutex_lock(&dev->struct_mutex); |
dev_priv->mm.suspended = 0; |
ret = i915_gem_init_ringbuffer(dev); |
if (ret != 0) { |
mutex_unlock(&dev->struct_mutex); |
return ret; |
} |
BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); |
for (i = 0; i < I915_NUM_RINGS; i++) { |
BUG_ON(!list_empty(&dev_priv->ring[i].active_list)); |
BUG_ON(!list_empty(&dev_priv->ring[i].request_list)); |
} |
mutex_unlock(&dev->struct_mutex); |
ret = drm_irq_install(dev); |
if (ret) |
goto cleanup_ringbuffer; |
return 0; |
cleanup_ringbuffer: |
mutex_lock(&dev->struct_mutex); |
i915_gem_cleanup_ringbuffer(dev); |
dev_priv->mm.suspended = 1; |
mutex_unlock(&dev->struct_mutex); |
return ret; |
} |
int |
i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
struct drm_file *file_priv) |
{ |
if (drm_core_check_feature(dev, DRIVER_MODESET)) |
return 0; |
drm_irq_uninstall(dev); |
return i915_gem_idle(dev); |
} |
void |
i915_gem_lastclose(struct drm_device *dev) |
{ |
int ret; |
if (drm_core_check_feature(dev, DRIVER_MODESET)) |
return; |
ret = i915_gem_idle(dev); |
if (ret) |
DRM_ERROR("failed to idle hardware: %d\n", ret); |
} |
#endif |
static void |
init_ring_lists(struct intel_ring_buffer *ring) |
{ |
INIT_LIST_HEAD(&ring->active_list); |
90,7 → 1673,6 |
INIT_LIST_HEAD(&ring->gpu_write_list); |
} |
void |
i915_gem_load(struct drm_device *dev) |
{ |
/drivers/video/drm/i915/i915_gem_gtt.c |
---|
0,0 → 1,138 |
/* |
* Copyright © 2010 Daniel Vetter |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
* copy of this software and associated documentation files (the "Software"), |
* to deal in the Software without restriction, including without limitation |
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
* and/or sell copies of the Software, and to permit persons to whom the |
* Software is furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice (including the next |
* paragraph) shall be included in all copies or substantial portions of the |
* Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
* IN THE SOFTWARE. |
* |
*/ |
#include "drmP.h" |
#include "drm.h" |
#include "i915_drm.h" |
#include "i915_drv.h" |
//#include "i915_trace.h" |
#include "intel_drv.h" |
#define AGP_USER_TYPES (1 << 16) |
#define AGP_USER_MEMORY (AGP_USER_TYPES) |
#define AGP_USER_CACHED_MEMORY (AGP_USER_TYPES + 1) |
/* XXX kill agp_type! */ |
static unsigned int cache_level_to_agp_type(struct drm_device *dev, |
enum i915_cache_level cache_level) |
{ |
switch (cache_level) { |
case I915_CACHE_LLC_MLC: |
if (INTEL_INFO(dev)->gen >= 6) |
return AGP_USER_CACHED_MEMORY_LLC_MLC; |
/* Older chipsets do not have this extra level of CPU |
* cacheing, so fallthrough and request the PTE simply |
* as cached. |
*/ |
case I915_CACHE_LLC: |
return AGP_USER_CACHED_MEMORY; |
default: |
case I915_CACHE_NONE: |
return AGP_USER_MEMORY; |
} |
} |
#if 0 |
void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct drm_i915_gem_object *obj; |
/* First fill our portion of the GTT with scratch pages */ |
intel_gtt_clear_range(dev_priv->mm.gtt_start / PAGE_SIZE, |
(dev_priv->mm.gtt_end - dev_priv->mm.gtt_start) / PAGE_SIZE); |
list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { |
i915_gem_clflush_object(obj); |
i915_gem_gtt_rebind_object(obj, obj->cache_level); |
} |
intel_gtt_chipset_flush(); |
} |
#endif |
int i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj) |
{ |
struct drm_device *dev = obj->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
unsigned int agp_type = cache_level_to_agp_type(dev, obj->cache_level); |
int ret; |
ENTER(); |
// if (dev_priv->mm.gtt->needs_dmar) { |
// ret = intel_gtt_map_memory(obj->pages, |
// obj->base.size >> PAGE_SHIFT, |
// &obj->sg_list, |
// &obj->num_sg); |
// if (ret != 0) |
// return ret; |
// intel_gtt_insert_sg_entries(obj->sg_list, |
// obj->num_sg, |
// obj->gtt_space->start >> PAGE_SHIFT, |
// agp_type); |
// } else |
intel_gtt_insert_pages(obj->gtt_space->start >> PAGE_SHIFT, |
obj->base.size >> PAGE_SHIFT, |
obj->pages, |
agp_type); |
LEAVE(); |
return 0; |
} |
#if 0 |
void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj, |
enum i915_cache_level cache_level) |
{ |
struct drm_device *dev = obj->base.dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
unsigned int agp_type = cache_level_to_agp_type(dev, cache_level); |
if (dev_priv->mm.gtt->needs_dmar) { |
BUG_ON(!obj->sg_list); |
intel_gtt_insert_sg_entries(obj->sg_list, |
obj->num_sg, |
obj->gtt_space->start >> PAGE_SHIFT, |
agp_type); |
} else |
intel_gtt_insert_pages(obj->gtt_space->start >> PAGE_SHIFT, |
obj->base.size >> PAGE_SHIFT, |
obj->pages, |
agp_type); |
} |
void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj) |
{ |
intel_gtt_clear_range(obj->gtt_space->start >> PAGE_SHIFT, |
obj->base.size >> PAGE_SHIFT); |
if (obj->sg_list) { |
intel_gtt_unmap_memory(obj->sg_list, obj->num_sg); |
obj->sg_list = NULL; |
} |
} |
#endif |
/drivers/video/drm/i915/intel_display.c |
---|
5668,9 → 5668,26 |
/** Sets the color ramps on behalf of RandR */ |
void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
u16 blue, int regno) |
{ |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
intel_crtc->lut_r[regno] = red >> 8; |
intel_crtc->lut_g[regno] = green >> 8; |
intel_crtc->lut_b[regno] = blue >> 8; |
} |
void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
u16 *blue, int regno) |
{ |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
*red = intel_crtc->lut_r[regno] << 8; |
*green = intel_crtc->lut_g[regno] << 8; |
*blue = intel_crtc->lut_b[regno] << 8; |
} |
static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
u16 *blue, uint32_t start, uint32_t size) |
7103,10 → 7120,109 |
I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS); |
} |
static void ironlake_teardown_rc6(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
if (dev_priv->renderctx) { |
// i915_gem_object_unpin(dev_priv->renderctx); |
// drm_gem_object_unreference(&dev_priv->renderctx->base); |
dev_priv->renderctx = NULL; |
} |
if (dev_priv->pwrctx) { |
// i915_gem_object_unpin(dev_priv->pwrctx); |
// drm_gem_object_unreference(&dev_priv->pwrctx->base); |
dev_priv->pwrctx = NULL; |
} |
} |
static int ironlake_setup_rc6(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
if (dev_priv->renderctx == NULL) |
// dev_priv->renderctx = intel_alloc_context_page(dev); |
if (!dev_priv->renderctx) |
return -ENOMEM; |
if (dev_priv->pwrctx == NULL) |
// dev_priv->pwrctx = intel_alloc_context_page(dev); |
if (!dev_priv->pwrctx) { |
ironlake_teardown_rc6(dev); |
return -ENOMEM; |
} |
return 0; |
} |
void ironlake_enable_rc6(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
int ret; |
/* rc6 disabled by default due to repeated reports of hanging during |
* boot and resume. |
*/ |
if (!i915_enable_rc6) |
return; |
mutex_lock(&dev->struct_mutex); |
ret = ironlake_setup_rc6(dev); |
if (ret) { |
mutex_unlock(&dev->struct_mutex); |
return; |
} |
/* |
* GPU can automatically power down the render unit if given a page |
* to save state. |
*/ |
#if 0 |
ret = BEGIN_LP_RING(6); |
if (ret) { |
ironlake_teardown_rc6(dev); |
mutex_unlock(&dev->struct_mutex); |
return; |
} |
OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); |
OUT_RING(MI_SET_CONTEXT); |
OUT_RING(dev_priv->renderctx->gtt_offset | |
MI_MM_SPACE_GTT | |
MI_SAVE_EXT_STATE_EN | |
MI_RESTORE_EXT_STATE_EN | |
MI_RESTORE_INHIBIT); |
OUT_RING(MI_SUSPEND_FLUSH); |
OUT_RING(MI_NOOP); |
OUT_RING(MI_FLUSH); |
ADVANCE_LP_RING(); |
/* |
* Wait for the command parser to advance past MI_SET_CONTEXT. The HW |
* does an implicit flush, combined with MI_FLUSH above, it should be |
* safe to assume that renderctx is valid |
*/ |
ret = intel_wait_ring_idle(LP_RING(dev_priv)); |
if (ret) { |
DRM_ERROR("failed to enable ironlake power power savings\n"); |
ironlake_teardown_rc6(dev); |
mutex_unlock(&dev->struct_mutex); |
return; |
} |
#endif |
I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN); |
I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
mutex_unlock(&dev->struct_mutex); |
} |
void intel_init_clock_gating(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
7438,9 → 7554,20 |
gen6_update_ring_freq(dev_priv); |
} |
// INIT_WORK(&dev_priv->idle_work, intel_idle_update); |
// setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, |
// (unsigned long)dev); |
} |
void intel_modeset_gem_init(struct drm_device *dev) |
{ |
if (IS_IRONLAKE_M(dev)) |
ironlake_enable_rc6(dev); |
// intel_setup_overlay(dev); |
} |
/* |
* Return which encoder is currently attached for connector. |
*/ |
/drivers/video/drm/i915/intel_fb.c |
---|
0,0 → 1,85 |
/* |
* Copyright © 2007 David Airlie |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
* copy of this software and associated documentation files (the "Software"), |
* to deal in the Software without restriction, including without limitation |
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
* and/or sell copies of the Software, and to permit persons to whom the |
* Software is furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice (including the next |
* paragraph) shall be included in all copies or substantial portions of the |
* Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
* DEALINGS IN THE SOFTWARE. |
* |
* Authors: |
* David Airlie |
*/ |
#include <linux/module.h> |
#include <linux/kernel.h> |
#include <linux/errno.h> |
#include <linux/string.h> |
//#include <linux/mm.h> |
//#include <linux/tty.h> |
#include <linux/sysrq.h> |
//#include <linux/delay.h> |
#include <linux/fb.h> |
//#include <linux/init.h> |
//#include <linux/vga_switcheroo.h> |
#include "drmP.h" |
#include "drm.h" |
#include "drm_crtc.h" |
#include "drm_fb_helper.h" |
#include "intel_drv.h" |
#include "i915_drm.h" |
#include "i915_drv.h" |
static struct drm_fb_helper_funcs intel_fb_helper_funcs = { |
.gamma_set = intel_crtc_fb_gamma_set, |
.gamma_get = intel_crtc_fb_gamma_get, |
// .fb_probe = intel_fb_find_or_create_single, |
}; |
int intel_fbdev_init(struct drm_device *dev) |
{ |
struct intel_fbdev *ifbdev; |
drm_i915_private_t *dev_priv = dev->dev_private; |
int ret; |
ENTER(); |
ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL); |
if (!ifbdev) |
return -ENOMEM; |
dev_priv->fbdev = ifbdev; |
ifbdev->helper.funcs = &intel_fb_helper_funcs; |
ret = drm_fb_helper_init(dev, &ifbdev->helper, |
dev_priv->num_pipe, |
INTELFB_CONN_LIMIT); |
if (ret) { |
kfree(ifbdev); |
return ret; |
} |
drm_fb_helper_single_add_all_connectors(&ifbdev->helper); |
drm_fb_helper_initial_config(&ifbdev->helper, 32); |
LEAVE(); |
return 0; |
} |
/drivers/video/drm/i915/intel_ringbuffer.c |
---|
0,0 → 1,1375 |
/* |
* Copyright © 2008-2010 Intel Corporation |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
* copy of this software and associated documentation files (the "Software"), |
* to deal in the Software without restriction, including without limitation |
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
* and/or sell copies of the Software, and to permit persons to whom the |
* Software is furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice (including the next |
* paragraph) shall be included in all copies or substantial portions of the |
* Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
* IN THE SOFTWARE. |
* |
* Authors: |
* Eric Anholt <eric@anholt.net> |
* Zou Nan hai <nanhai.zou@intel.com> |
* Xiang Hai hao<haihao.xiang@intel.com> |
* |
*/ |
#define iowrite32(v, addr) writel((v), (addr)) |
#define ioread32(addr) readl(addr) |
#include "drmP.h" |
#include "drm.h" |
#include "i915_drv.h" |
#include "i915_drm.h" |
//#include "i915_trace.h" |
#include "intel_drv.h" |
static inline int ring_space(struct intel_ring_buffer *ring) |
{ |
int space = (ring->head & HEAD_ADDR) - (ring->tail + 8); |
if (space < 0) |
space += ring->size; |
return space; |
} |
static u32 i915_gem_get_seqno(struct drm_device *dev) |
{ |
drm_i915_private_t *dev_priv = dev->dev_private; |
u32 seqno; |
seqno = dev_priv->next_seqno; |
/* reserve 0 for non-seqno */ |
if (++dev_priv->next_seqno == 0) |
dev_priv->next_seqno = 1; |
return seqno; |
} |
static int |
render_ring_flush(struct intel_ring_buffer *ring, |
u32 invalidate_domains, |
u32 flush_domains) |
{ |
struct drm_device *dev = ring->dev; |
u32 cmd; |
int ret; |
/* |
* read/write caches: |
* |
* I915_GEM_DOMAIN_RENDER is always invalidated, but is |
* only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is |
* also flushed at 2d versus 3d pipeline switches. |
* |
* read-only caches: |
* |
* I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if |
* MI_READ_FLUSH is set, and is always flushed on 965. |
* |
* I915_GEM_DOMAIN_COMMAND may not exist? |
* |
* I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is |
* invalidated when MI_EXE_FLUSH is set. |
* |
* I915_GEM_DOMAIN_VERTEX, which exists on 965, is |
* invalidated with every MI_FLUSH. |
* |
* TLBs: |
* |
* On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND |
* and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and |
* I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER |
* are flushed at any MI_FLUSH. |
*/ |
cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; |
if ((invalidate_domains|flush_domains) & |
I915_GEM_DOMAIN_RENDER) |
cmd &= ~MI_NO_WRITE_FLUSH; |
if (INTEL_INFO(dev)->gen < 4) { |
/* |
* On the 965, the sampler cache always gets flushed |
* and this bit is reserved. |
*/ |
if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) |
cmd |= MI_READ_FLUSH; |
} |
if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
cmd |= MI_EXE_FLUSH; |
if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
(IS_G4X(dev) || IS_GEN5(dev))) |
cmd |= MI_INVALIDATE_ISP; |
ret = intel_ring_begin(ring, 2); |
if (ret) |
return ret; |
intel_ring_emit(ring, cmd); |
intel_ring_emit(ring, MI_NOOP); |
intel_ring_advance(ring); |
return 0; |
} |
static void ring_write_tail(struct intel_ring_buffer *ring, |
u32 value) |
{ |
drm_i915_private_t *dev_priv = ring->dev->dev_private; |
I915_WRITE_TAIL(ring, value); |
} |
u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
{ |
drm_i915_private_t *dev_priv = ring->dev->dev_private; |
u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? |
RING_ACTHD(ring->mmio_base) : ACTHD; |
return I915_READ(acthd_reg); |
} |
static int init_ring_common(struct intel_ring_buffer *ring) |
{ |
drm_i915_private_t *dev_priv = ring->dev->dev_private; |
struct drm_i915_gem_object *obj = ring->obj; |
u32 head; |
ENTER(); |
/* Stop the ring if it's running. */ |
I915_WRITE_CTL(ring, 0); |
I915_WRITE_HEAD(ring, 0); |
ring->write_tail(ring, 0); |
/* Initialize the ring. */ |
I915_WRITE_START(ring, obj->gtt_offset); |
head = I915_READ_HEAD(ring) & HEAD_ADDR; |
/* G45 ring initialization fails to reset head to zero */ |
if (head != 0) { |
DRM_DEBUG_KMS("%s head not reset to zero " |
"ctl %08x head %08x tail %08x start %08x\n", |
ring->name, |
I915_READ_CTL(ring), |
I915_READ_HEAD(ring), |
I915_READ_TAIL(ring), |
I915_READ_START(ring)); |
I915_WRITE_HEAD(ring, 0); |
if (I915_READ_HEAD(ring) & HEAD_ADDR) { |
DRM_ERROR("failed to set %s head to zero " |
"ctl %08x head %08x tail %08x start %08x\n", |
ring->name, |
I915_READ_CTL(ring), |
I915_READ_HEAD(ring), |
I915_READ_TAIL(ring), |
I915_READ_START(ring)); |
} |
} |
I915_WRITE_CTL(ring, |
((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
| RING_REPORT_64K | RING_VALID); |
/* If the head is still not zero, the ring is dead */ |
if ((I915_READ_CTL(ring) & RING_VALID) == 0 || |
I915_READ_START(ring) != obj->gtt_offset || |
(I915_READ_HEAD(ring) & HEAD_ADDR) != 0) { |
DRM_ERROR("%s initialization failed " |
"ctl %08x head %08x tail %08x start %08x\n", |
ring->name, |
I915_READ_CTL(ring), |
I915_READ_HEAD(ring), |
I915_READ_TAIL(ring), |
I915_READ_START(ring)); |
return -EIO; |
} |
ring->head = I915_READ_HEAD(ring); |
ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
ring->space = ring_space(ring); |
LEAVE(); |
return 0; |
} |
#if 0 |
/* |
* 965+ support PIPE_CONTROL commands, which provide finer grained control |
* over cache flushing. |
*/ |
struct pipe_control { |
struct drm_i915_gem_object *obj; |
volatile u32 *cpu_page; |
u32 gtt_offset; |
}; |
static int |
init_pipe_control(struct intel_ring_buffer *ring) |
{ |
struct pipe_control *pc; |
struct drm_i915_gem_object *obj; |
int ret; |
if (ring->private) |
return 0; |
pc = kmalloc(sizeof(*pc), GFP_KERNEL); |
if (!pc) |
return -ENOMEM; |
obj = i915_gem_alloc_object(ring->dev, 4096); |
if (obj == NULL) { |
DRM_ERROR("Failed to allocate seqno page\n"); |
ret = -ENOMEM; |
goto err; |
} |
i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
ret = i915_gem_object_pin(obj, 4096, true); |
if (ret) |
goto err_unref; |
pc->gtt_offset = obj->gtt_offset; |
pc->cpu_page = kmap(obj->pages[0]); |
if (pc->cpu_page == NULL) |
goto err_unpin; |
pc->obj = obj; |
ring->private = pc; |
return 0; |
err_unpin: |
i915_gem_object_unpin(obj); |
err_unref: |
drm_gem_object_unreference(&obj->base); |
err: |
kfree(pc); |
return ret; |
} |
static void |
cleanup_pipe_control(struct intel_ring_buffer *ring) |
{ |
struct pipe_control *pc = ring->private; |
struct drm_i915_gem_object *obj; |
if (!ring->private) |
return; |
obj = pc->obj; |
kunmap(obj->pages[0]); |
i915_gem_object_unpin(obj); |
drm_gem_object_unreference(&obj->base); |
kfree(pc); |
ring->private = NULL; |
} |
#endif |
static int init_render_ring(struct intel_ring_buffer *ring) |
{ |
struct drm_device *dev = ring->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
ENTER(); |
int ret = init_ring_common(ring); |
if (INTEL_INFO(dev)->gen > 3) { |
int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH; |
if (IS_GEN6(dev) || IS_GEN7(dev)) |
mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE; |
I915_WRITE(MI_MODE, mode); |
if (IS_GEN7(dev)) |
I915_WRITE(GFX_MODE_GEN7, |
GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | |
GFX_MODE_ENABLE(GFX_REPLAY_MODE)); |
} |
if (INTEL_INFO(dev)->gen >= 6) { |
} else if (IS_GEN5(dev)) { |
// ret = init_pipe_control(ring); |
if (ret) |
return ret; |
} |
LEAVE(); |
return ret; |
} |
#if 0 |
static void render_ring_cleanup(struct intel_ring_buffer *ring) |
{ |
if (!ring->private) |
return; |
cleanup_pipe_control(ring); |
} |
static void |
update_semaphore(struct intel_ring_buffer *ring, int i, u32 seqno) |
{ |
struct drm_device *dev = ring->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
int id; |
/* |
* cs -> 1 = vcs, 0 = bcs |
* vcs -> 1 = bcs, 0 = cs, |
* bcs -> 1 = cs, 0 = vcs. |
*/ |
id = ring - dev_priv->ring; |
id += 2 - i; |
id %= 3; |
intel_ring_emit(ring, |
MI_SEMAPHORE_MBOX | |
MI_SEMAPHORE_REGISTER | |
MI_SEMAPHORE_UPDATE); |
intel_ring_emit(ring, seqno); |
intel_ring_emit(ring, |
RING_SYNC_0(dev_priv->ring[id].mmio_base) + 4*i); |
} |
static int |
gen6_add_request(struct intel_ring_buffer *ring, |
u32 *result) |
{ |
u32 seqno; |
int ret; |
ret = intel_ring_begin(ring, 10); |
if (ret) |
return ret; |
seqno = i915_gem_get_seqno(ring->dev); |
update_semaphore(ring, 0, seqno); |
update_semaphore(ring, 1, seqno); |
intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
intel_ring_emit(ring, seqno); |
intel_ring_emit(ring, MI_USER_INTERRUPT); |
intel_ring_advance(ring); |
*result = seqno; |
return 0; |
} |
int |
intel_ring_sync(struct intel_ring_buffer *ring, |
struct intel_ring_buffer *to, |
u32 seqno) |
{ |
int ret; |
ret = intel_ring_begin(ring, 4); |
if (ret) |
return ret; |
intel_ring_emit(ring, |
MI_SEMAPHORE_MBOX | |
MI_SEMAPHORE_REGISTER | |
intel_ring_sync_index(ring, to) << 17 | |
MI_SEMAPHORE_COMPARE); |
intel_ring_emit(ring, seqno); |
intel_ring_emit(ring, 0); |
intel_ring_emit(ring, MI_NOOP); |
intel_ring_advance(ring); |
return 0; |
} |
#define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
do { \ |
intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \ |
PIPE_CONTROL_DEPTH_STALL | 2); \ |
intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
intel_ring_emit(ring__, 0); \ |
intel_ring_emit(ring__, 0); \ |
} while (0) |
static int |
pc_render_add_request(struct intel_ring_buffer *ring, |
u32 *result) |
{ |
struct drm_device *dev = ring->dev; |
u32 seqno = i915_gem_get_seqno(dev); |
struct pipe_control *pc = ring->private; |
u32 scratch_addr = pc->gtt_offset + 128; |
int ret; |
/* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently |
* incoherent with writes to memory, i.e. completely fubar, |
* so we need to use PIPE_NOTIFY instead. |
* |
* However, we also need to workaround the qword write |
* incoherence by flushing the 6 PIPE_NOTIFY buffers out to |
* memory before requesting an interrupt. |
*/ |
ret = intel_ring_begin(ring, 32); |
if (ret) |
return ret; |
intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | |
PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH); |
intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
intel_ring_emit(ring, seqno); |
intel_ring_emit(ring, 0); |
PIPE_CONTROL_FLUSH(ring, scratch_addr); |
scratch_addr += 128; /* write to separate cachelines */ |
PIPE_CONTROL_FLUSH(ring, scratch_addr); |
scratch_addr += 128; |
PIPE_CONTROL_FLUSH(ring, scratch_addr); |
scratch_addr += 128; |
PIPE_CONTROL_FLUSH(ring, scratch_addr); |
scratch_addr += 128; |
PIPE_CONTROL_FLUSH(ring, scratch_addr); |
scratch_addr += 128; |
PIPE_CONTROL_FLUSH(ring, scratch_addr); |
intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | |
PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH | |
PIPE_CONTROL_NOTIFY); |
intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
intel_ring_emit(ring, seqno); |
intel_ring_emit(ring, 0); |
intel_ring_advance(ring); |
*result = seqno; |
return 0; |
} |
static int |
render_ring_add_request(struct intel_ring_buffer *ring, |
u32 *result) |
{ |
struct drm_device *dev = ring->dev; |
u32 seqno = i915_gem_get_seqno(dev); |
int ret; |
ret = intel_ring_begin(ring, 4); |
if (ret) |
return ret; |
intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
intel_ring_emit(ring, seqno); |
intel_ring_emit(ring, MI_USER_INTERRUPT); |
intel_ring_advance(ring); |
*result = seqno; |
return 0; |
} |
static u32 |
ring_get_seqno(struct intel_ring_buffer *ring) |
{ |
return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
} |
static u32 |
pc_render_get_seqno(struct intel_ring_buffer *ring) |
{ |
struct pipe_control *pc = ring->private; |
return pc->cpu_page[0]; |
} |
static void |
ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
{ |
dev_priv->gt_irq_mask &= ~mask; |
I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
POSTING_READ(GTIMR); |
} |
static void |
ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask) |
{ |
dev_priv->gt_irq_mask |= mask; |
I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
POSTING_READ(GTIMR); |
} |
static void |
i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
{ |
dev_priv->irq_mask &= ~mask; |
I915_WRITE(IMR, dev_priv->irq_mask); |
POSTING_READ(IMR); |
} |
static void |
i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) |
{ |
dev_priv->irq_mask |= mask; |
I915_WRITE(IMR, dev_priv->irq_mask); |
POSTING_READ(IMR); |
} |
static bool |
render_ring_get_irq(struct intel_ring_buffer *ring) |
{ |
struct drm_device *dev = ring->dev; |
drm_i915_private_t *dev_priv = dev->dev_private; |
if (!dev->irq_enabled) |
return false; |
spin_lock(&ring->irq_lock); |
if (ring->irq_refcount++ == 0) { |
if (HAS_PCH_SPLIT(dev)) |
ironlake_enable_irq(dev_priv, |
GT_PIPE_NOTIFY | GT_USER_INTERRUPT); |
else |
i915_enable_irq(dev_priv, I915_USER_INTERRUPT); |
} |
spin_unlock(&ring->irq_lock); |
return true; |
} |
static void |
render_ring_put_irq(struct intel_ring_buffer *ring) |
{ |
struct drm_device *dev = ring->dev; |
drm_i915_private_t *dev_priv = dev->dev_private; |
spin_lock(&ring->irq_lock); |
if (--ring->irq_refcount == 0) { |
if (HAS_PCH_SPLIT(dev)) |
ironlake_disable_irq(dev_priv, |
GT_USER_INTERRUPT | |
GT_PIPE_NOTIFY); |
else |
i915_disable_irq(dev_priv, I915_USER_INTERRUPT); |
} |
spin_unlock(&ring->irq_lock); |
} |
void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
{ |
struct drm_device *dev = ring->dev; |
drm_i915_private_t *dev_priv = ring->dev->dev_private; |
u32 mmio = 0; |
/* The ring status page addresses are no longer next to the rest of |
* the ring registers as of gen7. |
*/ |
if (IS_GEN7(dev)) { |
switch (ring->id) { |
case RING_RENDER: |
mmio = RENDER_HWS_PGA_GEN7; |
break; |
case RING_BLT: |
mmio = BLT_HWS_PGA_GEN7; |
break; |
case RING_BSD: |
mmio = BSD_HWS_PGA_GEN7; |
break; |
} |
} else if (IS_GEN6(ring->dev)) { |
mmio = RING_HWS_PGA_GEN6(ring->mmio_base); |
} else { |
mmio = RING_HWS_PGA(ring->mmio_base); |
} |
I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
POSTING_READ(mmio); |
} |
#endif |
static int |
bsd_ring_flush(struct intel_ring_buffer *ring, |
u32 invalidate_domains, |
u32 flush_domains) |
{ |
int ret; |
ret = intel_ring_begin(ring, 2); |
if (ret) |
return ret; |
intel_ring_emit(ring, MI_FLUSH); |
intel_ring_emit(ring, MI_NOOP); |
intel_ring_advance(ring); |
return 0; |
} |
#if 0 |
static int |
ring_add_request(struct intel_ring_buffer *ring, |
u32 *result) |
{ |
u32 seqno; |
int ret; |
ret = intel_ring_begin(ring, 4); |
if (ret) |
return ret; |
seqno = i915_gem_get_seqno(ring->dev); |
intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
intel_ring_emit(ring, seqno); |
intel_ring_emit(ring, MI_USER_INTERRUPT); |
intel_ring_advance(ring); |
*result = seqno; |
return 0; |
} |
static bool |
gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag) |
{ |
struct drm_device *dev = ring->dev; |
drm_i915_private_t *dev_priv = dev->dev_private; |
if (!dev->irq_enabled) |
return false; |
spin_lock(&ring->irq_lock); |
if (ring->irq_refcount++ == 0) { |
ring->irq_mask &= ~rflag; |
I915_WRITE_IMR(ring, ring->irq_mask); |
ironlake_enable_irq(dev_priv, gflag); |
} |
spin_unlock(&ring->irq_lock); |
return true; |
} |
static void |
gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag) |
{ |
struct drm_device *dev = ring->dev; |
drm_i915_private_t *dev_priv = dev->dev_private; |
spin_lock(&ring->irq_lock); |
if (--ring->irq_refcount == 0) { |
ring->irq_mask |= rflag; |
I915_WRITE_IMR(ring, ring->irq_mask); |
ironlake_disable_irq(dev_priv, gflag); |
} |
spin_unlock(&ring->irq_lock); |
} |
static bool |
bsd_ring_get_irq(struct intel_ring_buffer *ring) |
{ |
struct drm_device *dev = ring->dev; |
drm_i915_private_t *dev_priv = dev->dev_private; |
if (!dev->irq_enabled) |
return false; |
spin_lock(&ring->irq_lock); |
if (ring->irq_refcount++ == 0) { |
if (IS_G4X(dev)) |
i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT); |
else |
ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT); |
} |
spin_unlock(&ring->irq_lock); |
return true; |
} |
static void |
bsd_ring_put_irq(struct intel_ring_buffer *ring) |
{ |
struct drm_device *dev = ring->dev; |
drm_i915_private_t *dev_priv = dev->dev_private; |
spin_lock(&ring->irq_lock); |
if (--ring->irq_refcount == 0) { |
if (IS_G4X(dev)) |
i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT); |
else |
ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT); |
} |
spin_unlock(&ring->irq_lock); |
} |
static int |
ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length) |
{ |
int ret; |
ret = intel_ring_begin(ring, 2); |
if (ret) |
return ret; |
intel_ring_emit(ring, |
MI_BATCH_BUFFER_START | (2 << 6) | |
MI_BATCH_NON_SECURE_I965); |
intel_ring_emit(ring, offset); |
intel_ring_advance(ring); |
return 0; |
} |
static int |
render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
u32 offset, u32 len) |
{ |
struct drm_device *dev = ring->dev; |
int ret; |
if (IS_I830(dev) || IS_845G(dev)) { |
ret = intel_ring_begin(ring, 4); |
if (ret) |
return ret; |
intel_ring_emit(ring, MI_BATCH_BUFFER); |
intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); |
intel_ring_emit(ring, offset + len - 8); |
intel_ring_emit(ring, 0); |
} else { |
ret = intel_ring_begin(ring, 2); |
if (ret) |
return ret; |
if (INTEL_INFO(dev)->gen >= 4) { |
intel_ring_emit(ring, |
MI_BATCH_BUFFER_START | (2 << 6) | |
MI_BATCH_NON_SECURE_I965); |
intel_ring_emit(ring, offset); |
} else { |
intel_ring_emit(ring, |
MI_BATCH_BUFFER_START | (2 << 6)); |
intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); |
} |
} |
intel_ring_advance(ring); |
return 0; |
} |
static void cleanup_status_page(struct intel_ring_buffer *ring) |
{ |
drm_i915_private_t *dev_priv = ring->dev->dev_private; |
struct drm_i915_gem_object *obj; |
obj = ring->status_page.obj; |
if (obj == NULL) |
return; |
kunmap(obj->pages[0]); |
i915_gem_object_unpin(obj); |
drm_gem_object_unreference(&obj->base); |
ring->status_page.obj = NULL; |
memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
} |
static int init_status_page(struct intel_ring_buffer *ring) |
{ |
struct drm_device *dev = ring->dev; |
drm_i915_private_t *dev_priv = dev->dev_private; |
struct drm_i915_gem_object *obj; |
int ret; |
obj = i915_gem_alloc_object(dev, 4096); |
if (obj == NULL) { |
DRM_ERROR("Failed to allocate status page\n"); |
ret = -ENOMEM; |
goto err; |
} |
i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
ret = i915_gem_object_pin(obj, 4096, true); |
if (ret != 0) { |
goto err_unref; |
} |
ring->status_page.gfx_addr = obj->gtt_offset; |
ring->status_page.page_addr = kmap(obj->pages[0]); |
if (ring->status_page.page_addr == NULL) { |
memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
goto err_unpin; |
} |
ring->status_page.obj = obj; |
memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
intel_ring_setup_status_page(ring); |
DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
ring->name, ring->status_page.gfx_addr); |
return 0; |
err_unpin: |
i915_gem_object_unpin(obj); |
err_unref: |
drm_gem_object_unreference(&obj->base); |
err: |
return ret; |
} |
#endif |
int intel_init_ring_buffer(struct drm_device *dev, |
struct intel_ring_buffer *ring) |
{ |
struct drm_i915_gem_object *obj=NULL; |
int ret; |
ENTER(); |
ring->dev = dev; |
INIT_LIST_HEAD(&ring->active_list); |
INIT_LIST_HEAD(&ring->request_list); |
INIT_LIST_HEAD(&ring->gpu_write_list); |
// init_waitqueue_head(&ring->irq_queue); |
// spin_lock_init(&ring->irq_lock); |
ring->irq_mask = ~0; |
if (I915_NEED_GFX_HWS(dev)) { |
// ret = init_status_page(ring); |
// if (ret) |
// return ret; |
} |
obj = i915_gem_alloc_object(dev, ring->size); |
if (obj == NULL) { |
DRM_ERROR("Failed to allocate ringbuffer\n"); |
ret = -ENOMEM; |
goto err_hws; |
} |
ring->obj = obj; |
ret = i915_gem_object_pin(obj, PAGE_SIZE, true); |
if (ret) |
goto err_unref; |
ring->map.size = ring->size; |
ring->map.offset = get_bus_addr() + obj->gtt_offset; |
ring->map.type = 0; |
ring->map.flags = 0; |
ring->map.mtrr = 0; |
// drm_core_ioremap_wc(&ring->map, dev); |
ring->map.handle = ioremap(ring->map.offset, ring->map.size); |
if (ring->map.handle == NULL) { |
DRM_ERROR("Failed to map ringbuffer.\n"); |
ret = -EINVAL; |
goto err_unpin; |
} |
ring->virtual_start = ring->map.handle; |
ret = ring->init(ring); |
if (ret) |
goto err_unmap; |
/* Workaround an erratum on the i830 which causes a hang if |
* the TAIL pointer points to within the last 2 cachelines |
* of the buffer. |
*/ |
ring->effective_size = ring->size; |
if (IS_I830(ring->dev)) |
ring->effective_size -= 128; |
LEAVE(); |
return 0; |
err_unmap: |
// drm_core_ioremapfree(&ring->map, dev); |
FreeKernelSpace(ring->virtual_start); |
err_unpin: |
// i915_gem_object_unpin(obj); |
err_unref: |
// drm_gem_object_unreference(&obj->base); |
ring->obj = NULL; |
err_hws: |
// cleanup_status_page(ring); |
return ret; |
} |
void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
{ |
struct drm_i915_private *dev_priv; |
int ret; |
if (ring->obj == NULL) |
return; |
/* Disable the ring buffer. The ring must be idle at this point */ |
dev_priv = ring->dev->dev_private; |
ret = intel_wait_ring_idle(ring); |
if (ret) |
DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
ring->name, ret); |
I915_WRITE_CTL(ring, 0); |
// drm_core_ioremapfree(&ring->map, ring->dev); |
// i915_gem_object_unpin(ring->obj); |
// drm_gem_object_unreference(&ring->obj->base); |
ring->obj = NULL; |
if (ring->cleanup) |
ring->cleanup(ring); |
// cleanup_status_page(ring); |
} |
static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
{ |
unsigned int *virt; |
int rem = ring->size - ring->tail; |
if (ring->space < rem) { |
int ret = intel_wait_ring_buffer(ring, rem); |
if (ret) |
return ret; |
} |
virt = (unsigned int *)(ring->virtual_start + ring->tail); |
rem /= 8; |
while (rem--) { |
*virt++ = MI_NOOP; |
*virt++ = MI_NOOP; |
} |
ring->tail = 0; |
ring->space = ring_space(ring); |
return 0; |
} |
int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n) |
{ |
struct drm_device *dev = ring->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
unsigned long end; |
u32 head; |
/* If the reported head position has wrapped or hasn't advanced, |
* fallback to the slow and accurate path. |
*/ |
head = intel_read_status_page(ring, 4); |
if (head > ring->head) { |
ring->head = head; |
ring->space = ring_space(ring); |
if (ring->space >= n) |
return 0; |
} |
// trace_i915_ring_wait_begin(ring); |
end = jiffies + 3 * HZ; |
do { |
ring->head = I915_READ_HEAD(ring); |
ring->space = ring_space(ring); |
if (ring->space >= n) { |
// trace_i915_ring_wait_end(ring); |
return 0; |
} |
if (dev->primary->master) { |
struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
if (master_priv->sarea_priv) |
master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; |
} |
msleep(1); |
if (atomic_read(&dev_priv->mm.wedged)) |
return -EAGAIN; |
} while (!time_after(jiffies, end)); |
// trace_i915_ring_wait_end(ring); |
return -EBUSY; |
} |
int intel_ring_begin(struct intel_ring_buffer *ring, |
int num_dwords) |
{ |
struct drm_i915_private *dev_priv = ring->dev->dev_private; |
int n = 4*num_dwords; |
int ret; |
if (unlikely(atomic_read(&dev_priv->mm.wedged))) |
return -EIO; |
if (unlikely(ring->tail + n > ring->effective_size)) { |
ret = intel_wrap_ring_buffer(ring); |
if (unlikely(ret)) |
return ret; |
} |
if (unlikely(ring->space < n)) { |
ret = intel_wait_ring_buffer(ring, n); |
if (unlikely(ret)) |
return ret; |
} |
ring->space -= n; |
return 0; |
} |
void intel_ring_advance(struct intel_ring_buffer *ring) |
{ |
ring->tail &= ring->size - 1; |
ring->write_tail(ring, ring->tail); |
} |
static const struct intel_ring_buffer render_ring = { |
.name = "render ring", |
.id = RING_RENDER, |
.mmio_base = RENDER_RING_BASE, |
.size = 32 * PAGE_SIZE, |
.init = init_render_ring, |
.write_tail = ring_write_tail, |
.flush = render_ring_flush, |
// .add_request = render_ring_add_request, |
// .get_seqno = ring_get_seqno, |
// .irq_get = render_ring_get_irq, |
// .irq_put = render_ring_put_irq, |
// .dispatch_execbuffer = render_ring_dispatch_execbuffer, |
// .cleanup = render_ring_cleanup, |
}; |
/* ring buffer for bit-stream decoder */ |
static const struct intel_ring_buffer bsd_ring = { |
.name = "bsd ring", |
.id = RING_BSD, |
.mmio_base = BSD_RING_BASE, |
.size = 32 * PAGE_SIZE, |
.init = init_ring_common, |
.write_tail = ring_write_tail, |
.flush = bsd_ring_flush, |
// .add_request = ring_add_request, |
// .get_seqno = ring_get_seqno, |
// .irq_get = bsd_ring_get_irq, |
// .irq_put = bsd_ring_put_irq, |
// .dispatch_execbuffer = ring_dispatch_execbuffer, |
}; |
static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
u32 value) |
{ |
drm_i915_private_t *dev_priv = ring->dev->dev_private; |
/* Every tail move must follow the sequence below */ |
I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | |
GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE); |
I915_WRITE(GEN6_BSD_RNCID, 0x0); |
if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0, |
50)) |
DRM_ERROR("timed out waiting for IDLE Indicator\n"); |
I915_WRITE_TAIL(ring, value); |
I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | |
GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE); |
} |
static int gen6_ring_flush(struct intel_ring_buffer *ring, |
u32 invalidate, u32 flush) |
{ |
uint32_t cmd; |
int ret; |
ret = intel_ring_begin(ring, 4); |
if (ret) |
return ret; |
cmd = MI_FLUSH_DW; |
if (invalidate & I915_GEM_GPU_DOMAINS) |
cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
intel_ring_emit(ring, cmd); |
intel_ring_emit(ring, 0); |
intel_ring_emit(ring, 0); |
intel_ring_emit(ring, MI_NOOP); |
intel_ring_advance(ring); |
return 0; |
} |
#if 0 |
static int |
gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
u32 offset, u32 len) |
{ |
int ret; |
ret = intel_ring_begin(ring, 2); |
if (ret) |
return ret; |
intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965); |
/* bit0-7 is the length on GEN6+ */ |
intel_ring_emit(ring, offset); |
intel_ring_advance(ring); |
return 0; |
} |
static bool |
gen6_render_ring_get_irq(struct intel_ring_buffer *ring) |
{ |
return gen6_ring_get_irq(ring, |
GT_USER_INTERRUPT, |
GEN6_RENDER_USER_INTERRUPT); |
} |
static void |
gen6_render_ring_put_irq(struct intel_ring_buffer *ring) |
{ |
return gen6_ring_put_irq(ring, |
GT_USER_INTERRUPT, |
GEN6_RENDER_USER_INTERRUPT); |
} |
static bool |
gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring) |
{ |
return gen6_ring_get_irq(ring, |
GT_GEN6_BSD_USER_INTERRUPT, |
GEN6_BSD_USER_INTERRUPT); |
} |
static void |
gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring) |
{ |
return gen6_ring_put_irq(ring, |
GT_GEN6_BSD_USER_INTERRUPT, |
GEN6_BSD_USER_INTERRUPT); |
} |
#endif |
/* ring buffer for Video Codec for Gen6+ */ |
static const struct intel_ring_buffer gen6_bsd_ring = { |
.name = "gen6 bsd ring", |
.id = RING_BSD, |
.mmio_base = GEN6_BSD_RING_BASE, |
.size = 32 * PAGE_SIZE, |
.init = init_ring_common, |
.write_tail = gen6_bsd_ring_write_tail, |
.flush = gen6_ring_flush, |
// .add_request = gen6_add_request, |
// .get_seqno = ring_get_seqno, |
// .irq_get = gen6_bsd_ring_get_irq, |
// .irq_put = gen6_bsd_ring_put_irq, |
// .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, |
}; |
#if 0 |
/* Blitter support (SandyBridge+) */ |
static bool |
blt_ring_get_irq(struct intel_ring_buffer *ring) |
{ |
return gen6_ring_get_irq(ring, |
GT_BLT_USER_INTERRUPT, |
GEN6_BLITTER_USER_INTERRUPT); |
} |
static void |
blt_ring_put_irq(struct intel_ring_buffer *ring) |
{ |
gen6_ring_put_irq(ring, |
GT_BLT_USER_INTERRUPT, |
GEN6_BLITTER_USER_INTERRUPT); |
} |
#endif |
/* Workaround for some stepping of SNB, |
* each time when BLT engine ring tail moved, |
* the first command in the ring to be parsed |
* should be MI_BATCH_BUFFER_START |
*/ |
#define NEED_BLT_WORKAROUND(dev) \ |
(IS_GEN6(dev) && (dev->pdev->revision < 8)) |
static inline struct drm_i915_gem_object * |
to_blt_workaround(struct intel_ring_buffer *ring) |
{ |
return ring->private; |
} |
static int blt_ring_init(struct intel_ring_buffer *ring) |
{ |
if (NEED_BLT_WORKAROUND(ring->dev)) { |
struct drm_i915_gem_object *obj; |
u32 *ptr; |
int ret; |
obj = i915_gem_alloc_object(ring->dev, 4096); |
if (obj == NULL) |
return -ENOMEM; |
ret = i915_gem_object_pin(obj, 4096, true); |
if (ret) { |
// drm_gem_object_unreference(&obj->base); |
return ret; |
} |
ptr = ioremap(obj->pages[0], 4096); |
*ptr++ = MI_BATCH_BUFFER_END; |
*ptr++ = MI_NOOP; |
iounmap(obj->pages[0]); |
ret = i915_gem_object_set_to_gtt_domain(obj, false); |
if (ret) { |
// i915_gem_object_unpin(obj); |
// drm_gem_object_unreference(&obj->base); |
return ret; |
} |
ring->private = obj; |
} |
return init_ring_common(ring); |
} |
static int blt_ring_begin(struct intel_ring_buffer *ring, |
int num_dwords) |
{ |
if (ring->private) { |
int ret = intel_ring_begin(ring, num_dwords+2); |
if (ret) |
return ret; |
intel_ring_emit(ring, MI_BATCH_BUFFER_START); |
intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset); |
return 0; |
} else |
return intel_ring_begin(ring, 4); |
} |
static int blt_ring_flush(struct intel_ring_buffer *ring, |
u32 invalidate, u32 flush) |
{ |
uint32_t cmd; |
int ret; |
ret = blt_ring_begin(ring, 4); |
if (ret) |
return ret; |
cmd = MI_FLUSH_DW; |
if (invalidate & I915_GEM_DOMAIN_RENDER) |
cmd |= MI_INVALIDATE_TLB; |
intel_ring_emit(ring, cmd); |
intel_ring_emit(ring, 0); |
intel_ring_emit(ring, 0); |
intel_ring_emit(ring, MI_NOOP); |
intel_ring_advance(ring); |
return 0; |
} |
static void blt_ring_cleanup(struct intel_ring_buffer *ring) |
{ |
if (!ring->private) |
return; |
i915_gem_object_unpin(ring->private); |
drm_gem_object_unreference(ring->private); |
ring->private = NULL; |
} |
static const struct intel_ring_buffer gen6_blt_ring = { |
.name = "blt ring", |
.id = RING_BLT, |
.mmio_base = BLT_RING_BASE, |
.size = 32 * PAGE_SIZE, |
.init = blt_ring_init, |
.write_tail = ring_write_tail, |
.flush = blt_ring_flush, |
// .add_request = gen6_add_request, |
// .get_seqno = ring_get_seqno, |
// .irq_get = blt_ring_get_irq, |
// .irq_put = blt_ring_put_irq, |
// .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, |
// .cleanup = blt_ring_cleanup, |
}; |
int intel_init_render_ring_buffer(struct drm_device *dev) |
{ |
drm_i915_private_t *dev_priv = dev->dev_private; |
struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
ENTER(); |
*ring = render_ring; |
if (INTEL_INFO(dev)->gen >= 6) { |
// ring->add_request = gen6_add_request; |
// ring->irq_get = gen6_render_ring_get_irq; |
// ring->irq_put = gen6_render_ring_put_irq; |
} else if (IS_GEN5(dev)) { |
// ring->add_request = pc_render_add_request; |
// ring->get_seqno = pc_render_get_seqno; |
} |
if (!I915_NEED_GFX_HWS(dev)) { |
ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
} |
LEAVE(); |
return intel_init_ring_buffer(dev, ring); |
} |
int intel_init_bsd_ring_buffer(struct drm_device *dev) |
{ |
drm_i915_private_t *dev_priv = dev->dev_private; |
struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
if (IS_GEN6(dev) || IS_GEN7(dev)) |
*ring = gen6_bsd_ring; |
else |
*ring = bsd_ring; |
return intel_init_ring_buffer(dev, ring); |
} |
int intel_init_blt_ring_buffer(struct drm_device *dev) |
{ |
drm_i915_private_t *dev_priv = dev->dev_private; |
struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
*ring = gen6_blt_ring; |
return intel_init_ring_buffer(dev, ring); |
} |