| 31,6 → 31,10 |
|---|
| #include "radeon_asic.h" |
| #include "cikd.h" |
| |
| #define VCE_V2_0_FW_SIZE (256 * 1024) |
| #define VCE_V2_0_STACK_SIZE (64 * 1024) |
| #define VCE_V2_0_DATA_SIZE (23552 * RADEON_MAX_VCE_HANDLES) |
| |
| static void vce_v2_0_set_sw_cg(struct radeon_device *rdev, bool gated) |
| { |
| u32 tmp; |
| 140,6 → 144,12 |
|---|
| WREG32(VCE_CLOCK_GATING_B, tmp); |
| } |
| |
| unsigned vce_v2_0_bo_size(struct radeon_device *rdev) |
| { |
| WARN_ON(rdev->vce_fw->size > VCE_V2_0_FW_SIZE); |
| return VCE_V2_0_FW_SIZE + VCE_V2_0_STACK_SIZE + VCE_V2_0_DATA_SIZE; |
| } |
| |
| int vce_v2_0_resume(struct radeon_device *rdev) |
| { |
| uint64_t addr = rdev->vce.gpu_addr; |
| 156,17 → 166,20 |
|---|
| WREG32(VCE_LMI_SWAP_CNTL1, 0); |
| WREG32(VCE_LMI_VM_CTRL, 0); |
| |
| size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size); |
| WREG32(VCE_LMI_VCPU_CACHE_40BIT_BAR, addr >> 8); |
| |
| addr &= 0xff; |
| size = VCE_V2_0_FW_SIZE; |
| WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff); |
| WREG32(VCE_VCPU_CACHE_SIZE0, size); |
| |
| addr += size; |
| size = RADEON_VCE_STACK_SIZE; |
| size = VCE_V2_0_STACK_SIZE; |
| WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff); |
| WREG32(VCE_VCPU_CACHE_SIZE1, size); |
| |
| addr += size; |
| size = RADEON_VCE_HEAP_SIZE; |
| size = VCE_V2_0_DATA_SIZE; |
| WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff); |
| WREG32(VCE_VCPU_CACHE_SIZE2, size); |
| |