| 1001,6 → 1001,28 |
|---|
| ps->sclk_high, ps->max_voltage); |
| } |
| |
| /* get the current sclk in 10 khz units */ |
| u32 rs780_dpm_get_current_sclk(struct radeon_device *rdev) |
| { |
| u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK; |
| u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL); |
| u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1; |
| u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 + |
| ((func_cntl & SPLL_SW_LOLEN_MASK) >> SPLL_SW_LOLEN_SHIFT) + 1; |
| u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / |
| (post_div * ref_div); |
| |
| return sclk; |
| } |
| |
| /* get the current mclk in 10 khz units */ |
| u32 rs780_dpm_get_current_mclk(struct radeon_device *rdev) |
| { |
| struct igp_power_info *pi = rs780_get_pi(rdev); |
| |
| return pi->bootup_uma_clk; |
| } |
| |
| int rs780_dpm_force_performance_level(struct radeon_device *rdev, |
| enum radeon_dpm_forced_level level) |
| { |