42,16 → 42,21 |
* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 |
*/ |
int r100_init(struct radeon_device *rdev); |
int r200_init(struct radeon_device *rdev); |
uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg); |
void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
void r100_errata(struct radeon_device *rdev); |
void r100_vram_info(struct radeon_device *rdev); |
void r100_vga_set_state(struct radeon_device *rdev, bool state); |
int r100_gpu_reset(struct radeon_device *rdev); |
int r100_mc_init(struct radeon_device *rdev); |
void r100_mc_fini(struct radeon_device *rdev); |
u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); |
int r100_wb_init(struct radeon_device *rdev); |
void r100_wb_fini(struct radeon_device *rdev); |
int r100_gart_enable(struct radeon_device *rdev); |
int r100_pci_gart_init(struct radeon_device *rdev); |
void r100_pci_gart_fini(struct radeon_device *rdev); |
int r100_pci_gart_enable(struct radeon_device *rdev); |
void r100_pci_gart_disable(struct radeon_device *rdev); |
void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
58,6 → 63,7 |
int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); |
void r100_cp_fini(struct radeon_device *rdev); |
void r100_cp_disable(struct radeon_device *rdev); |
void r100_cp_commit(struct radeon_device *rdev); |
void r100_ring_start(struct radeon_device *rdev); |
int r100_irq_set(struct radeon_device *rdev); |
int r100_irq_process(struct radeon_device *rdev); |
71,8 → 77,15 |
uint64_t dst_offset, |
unsigned num_pages, |
struct radeon_fence *fence); |
int r100_set_surface_reg(struct radeon_device *rdev, int reg, |
uint32_t tiling_flags, uint32_t pitch, |
uint32_t offset, uint32_t obj_size); |
int r100_clear_surface_reg(struct radeon_device *rdev, int reg); |
void r100_bandwidth_update(struct radeon_device *rdev); |
void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
int r100_ib_test(struct radeon_device *rdev); |
int r100_ring_test(struct radeon_device *rdev); |
|
|
static struct radeon_asic r100_asic = { |
.init = &r100_init, |
.errata = &r100_errata, |
82,7 → 95,7 |
.mc_fini = &r100_mc_fini, |
// .wb_init = &r100_wb_init, |
// .wb_fini = &r100_wb_fini, |
.gart_enable = &r100_gart_enable, |
.gart_enable = &r100_pci_gart_enable, |
.gart_disable = &r100_pci_gart_disable, |
.gart_tlb_flush = &r100_pci_gart_tlb_flush, |
.gart_set_page = &r100_pci_gart_set_page, |
101,6 → 114,9 |
// .set_memory_clock = NULL, |
// .set_pcie_lanes = NULL, |
// .set_clock_gating = &radeon_legacy_set_clock_gating, |
.set_surface_reg = r100_set_surface_reg, |
.clear_surface_reg = r100_clear_surface_reg, |
.bandwidth_update = &r100_bandwidth_update, |
}; |
|
|
117,7 → 133,9 |
void r300_fence_ring_emit(struct radeon_device *rdev, |
struct radeon_fence *fence); |
int r300_cs_parse(struct radeon_cs_parser *p); |
int r300_gart_enable(struct radeon_device *rdev); |
int rv370_pcie_gart_init(struct radeon_device *rdev); |
void rv370_pcie_gart_fini(struct radeon_device *rdev); |
int rv370_pcie_gart_enable(struct radeon_device *rdev); |
void rv370_pcie_gart_disable(struct radeon_device *rdev); |
void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); |
int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
130,17 → 148,17 |
unsigned num_pages, |
struct radeon_fence *fence); |
|
|
static struct radeon_asic r300_asic = { |
.init = &r300_init, |
.errata = &r300_errata, |
.vram_info = &r300_vram_info, |
.vga_set_state = &r100_vga_set_state, |
.gpu_reset = &r300_gpu_reset, |
.mc_init = &r300_mc_init, |
.mc_fini = &r300_mc_fini, |
// .wb_init = &r100_wb_init, |
// .wb_fini = &r100_wb_fini, |
.gart_enable = &r300_gart_enable, |
.gart_enable = &r100_pci_gart_enable, |
.gart_disable = &r100_pci_gart_disable, |
.gart_tlb_flush = &r100_pci_gart_tlb_flush, |
.gart_set_page = &r100_pci_gart_set_page, |
159,32 → 177,38 |
// .set_memory_clock = NULL, |
// .set_pcie_lanes = &rv370_set_pcie_lanes, |
// .set_clock_gating = &radeon_legacy_set_clock_gating, |
.set_surface_reg = r100_set_surface_reg, |
.clear_surface_reg = r100_clear_surface_reg, |
.bandwidth_update = &r100_bandwidth_update, |
}; |
|
|
/* |
* r420,r423,rv410 |
*/ |
void r420_errata(struct radeon_device *rdev); |
void r420_vram_info(struct radeon_device *rdev); |
int r420_mc_init(struct radeon_device *rdev); |
void r420_mc_fini(struct radeon_device *rdev); |
extern int r420_init(struct radeon_device *rdev); |
extern void r420_fini(struct radeon_device *rdev); |
extern int r420_suspend(struct radeon_device *rdev); |
extern int r420_resume(struct radeon_device *rdev); |
static struct radeon_asic r420_asic = { |
.init = &r300_init, |
.errata = &r420_errata, |
.vram_info = &r420_vram_info, |
.init = &r420_init, |
.fini = &r420_fini, |
.suspend = &r420_suspend, |
.resume = &r420_resume, |
.errata = NULL, |
.vram_info = NULL, |
.vga_set_state = &r100_vga_set_state, |
.gpu_reset = &r300_gpu_reset, |
.mc_init = &r420_mc_init, |
.mc_fini = &r420_mc_fini, |
// .wb_init = &r100_wb_init, |
// .wb_fini = &r100_wb_fini, |
.gart_enable = &r300_gart_enable, |
.gart_disable = &rv370_pcie_gart_disable, |
.mc_init = NULL, |
.mc_fini = NULL, |
.wb_init = NULL, |
.wb_fini = NULL, |
.gart_enable = NULL, |
.gart_disable = NULL, |
.gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
.gart_set_page = &rv370_pcie_gart_set_page, |
.cp_init = &r100_cp_init, |
// .cp_fini = &r100_cp_fini, |
// .cp_disable = &r100_cp_disable, |
.cp_init = NULL, |
.cp_fini = NULL, |
.cp_disable = NULL, |
.ring_start = &r300_ring_start, |
// .irq_set = &r100_irq_set, |
// .irq_process = &r100_irq_process, |
197,6 → 221,9 |
// .set_memory_clock = &radeon_atom_set_memory_clock, |
// .set_pcie_lanes = &rv370_set_pcie_lanes, |
// .set_clock_gating = &radeon_atom_set_clock_gating, |
.set_surface_reg = r100_set_surface_reg, |
.clear_surface_reg = r100_clear_surface_reg, |
.bandwidth_update = &r100_bandwidth_update, |
}; |
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|
207,6 → 234,8 |
void rs400_vram_info(struct radeon_device *rdev); |
int rs400_mc_init(struct radeon_device *rdev); |
void rs400_mc_fini(struct radeon_device *rdev); |
int rs400_gart_init(struct radeon_device *rdev); |
void rs400_gart_fini(struct radeon_device *rdev); |
int rs400_gart_enable(struct radeon_device *rdev); |
void rs400_gart_disable(struct radeon_device *rdev); |
void rs400_gart_tlb_flush(struct radeon_device *rdev); |
217,11 → 246,14 |
.init = &r300_init, |
.errata = &rs400_errata, |
.vram_info = &rs400_vram_info, |
.vga_set_state = &r100_vga_set_state, |
.gpu_reset = &r300_gpu_reset, |
.mc_init = &rs400_mc_init, |
.mc_fini = &rs400_mc_fini, |
// .wb_init = &r100_wb_init, |
// .wb_fini = &r100_wb_fini, |
.gart_init = &rs400_gart_init, |
.gart_fini = &rs400_gart_fini, |
.gart_enable = &rs400_gart_enable, |
.gart_disable = &rs400_gart_disable, |
.gart_tlb_flush = &rs400_gart_tlb_flush, |
229,6 → 261,7 |
.cp_init = &r100_cp_init, |
// .cp_fini = &r100_cp_fini, |
// .cp_disable = &r100_cp_disable, |
.cp_commit = &r100_cp_commit, |
.ring_start = &r300_ring_start, |
// .irq_set = &r100_irq_set, |
// .irq_process = &r100_irq_process, |
241,6 → 274,9 |
// .set_memory_clock = NULL, |
// .set_pcie_lanes = NULL, |
// .set_clock_gating = &radeon_legacy_set_clock_gating, |
.set_surface_reg = r100_set_surface_reg, |
.clear_surface_reg = r100_clear_surface_reg, |
.bandwidth_update = &r100_bandwidth_update, |
}; |
|
|
247,11 → 283,16 |
/* |
* rs600. |
*/ |
int rs600_init(struct radeon_device *rdev); |
void rs600_errata(struct radeon_device *rdev); |
void rs600_vram_info(struct radeon_device *rdev); |
int rs600_mc_init(struct radeon_device *rdev); |
void rs600_mc_fini(struct radeon_device *rdev); |
int rs600_irq_set(struct radeon_device *rdev); |
int rs600_irq_process(struct radeon_device *rdev); |
u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); |
int rs600_gart_init(struct radeon_device *rdev); |
void rs600_gart_fini(struct radeon_device *rdev); |
int rs600_gart_enable(struct radeon_device *rdev); |
void rs600_gart_disable(struct radeon_device *rdev); |
void rs600_gart_tlb_flush(struct radeon_device *rdev); |
258,16 → 299,19 |
int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
|
void rs600_bandwidth_update(struct radeon_device *rdev); |
static struct radeon_asic rs600_asic = { |
.init = &r300_init, |
.init = &rs600_init, |
.errata = &rs600_errata, |
.vram_info = &rs600_vram_info, |
.vga_set_state = &r100_vga_set_state, |
.gpu_reset = &r300_gpu_reset, |
.mc_init = &rs600_mc_init, |
.mc_fini = &rs600_mc_fini, |
// .wb_init = &r100_wb_init, |
// .wb_fini = &r100_wb_fini, |
.gart_init = &rs600_gart_init, |
.gart_fini = &rs600_gart_fini, |
.gart_enable = &rs600_gart_enable, |
.gart_disable = &rs600_gart_disable, |
.gart_tlb_flush = &rs600_gart_tlb_flush, |
275,6 → 319,7 |
.cp_init = &r100_cp_init, |
// .cp_fini = &r100_cp_fini, |
// .cp_disable = &r100_cp_disable, |
.cp_commit = &r100_cp_commit, |
.ring_start = &r300_ring_start, |
// .irq_set = &rs600_irq_set, |
// .irq_process = &r100_irq_process, |
287,6 → 332,7 |
// .set_memory_clock = &radeon_atom_set_memory_clock, |
// .set_pcie_lanes = NULL, |
// .set_clock_gating = &radeon_atom_set_clock_gating, |
.bandwidth_update = &rs600_bandwidth_update, |
}; |
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|
299,15 → 345,19 |
void rs690_mc_fini(struct radeon_device *rdev); |
uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
void rs690_bandwidth_update(struct radeon_device *rdev); |
static struct radeon_asic rs690_asic = { |
.init = &r300_init, |
.init = &rs600_init, |
.errata = &rs690_errata, |
.vram_info = &rs690_vram_info, |
.vga_set_state = &r100_vga_set_state, |
.gpu_reset = &r300_gpu_reset, |
.mc_init = &rs690_mc_init, |
.mc_fini = &rs690_mc_fini, |
// .wb_init = &r100_wb_init, |
// .wb_fini = &r100_wb_fini, |
.gart_init = &rs400_gart_init, |
.gart_fini = &rs400_gart_fini, |
.gart_enable = &rs400_gart_enable, |
.gart_disable = &rs400_gart_disable, |
.gart_tlb_flush = &rs400_gart_tlb_flush, |
315,6 → 365,7 |
.cp_init = &r100_cp_init, |
// .cp_fini = &r100_cp_fini, |
// .cp_disable = &r100_cp_disable, |
.cp_commit = &r100_cp_commit, |
.ring_start = &r300_ring_start, |
// .irq_set = &rs600_irq_set, |
// .irq_process = &r100_irq_process, |
327,8 → 378,12 |
// .set_memory_clock = &radeon_atom_set_memory_clock, |
// .set_pcie_lanes = NULL, |
// .set_clock_gating = &radeon_atom_set_clock_gating, |
.set_surface_reg = r100_set_surface_reg, |
.clear_surface_reg = r100_clear_surface_reg, |
.bandwidth_update = &rs690_bandwidth_update, |
}; |
|
|
/* |
* rv515 |
*/ |
343,18 → 398,20 |
void rv515_ring_start(struct radeon_device *rdev); |
uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg); |
void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
|
|
void rv515_bandwidth_update(struct radeon_device *rdev); |
static struct radeon_asic rv515_asic = { |
.init = &rv515_init, |
.errata = &rv515_errata, |
.vram_info = &rv515_vram_info, |
.vga_set_state = &r100_vga_set_state, |
.gpu_reset = &rv515_gpu_reset, |
.mc_init = &rv515_mc_init, |
.mc_fini = &rv515_mc_fini, |
// .wb_init = &r100_wb_init, |
// .wb_fini = &r100_wb_fini, |
.gart_enable = &r300_gart_enable, |
.gart_init = &rv370_pcie_gart_init, |
.gart_fini = &rv370_pcie_gart_fini, |
.gart_enable = &rv370_pcie_gart_enable, |
.gart_disable = &rv370_pcie_gart_disable, |
.gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
.gart_set_page = &rv370_pcie_gart_set_page, |
361,6 → 418,7 |
.cp_init = &r100_cp_init, |
// .cp_fini = &r100_cp_fini, |
// .cp_disable = &r100_cp_disable, |
.cp_commit = &r100_cp_commit, |
.ring_start = &rv515_ring_start, |
// .irq_set = &r100_irq_set, |
// .irq_process = &r100_irq_process, |
373,6 → 431,9 |
// .set_memory_clock = &radeon_atom_set_memory_clock, |
// .set_pcie_lanes = &rv370_set_pcie_lanes, |
// .set_clock_gating = &radeon_atom_set_clock_gating, |
.set_surface_reg = r100_set_surface_reg, |
.clear_surface_reg = r100_clear_surface_reg, |
.bandwidth_update = &rv515_bandwidth_update, |
}; |
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|
383,17 → 444,20 |
void r520_vram_info(struct radeon_device *rdev); |
int r520_mc_init(struct radeon_device *rdev); |
void r520_mc_fini(struct radeon_device *rdev); |
|
void r520_bandwidth_update(struct radeon_device *rdev); |
static struct radeon_asic r520_asic = { |
.init = &rv515_init, |
.errata = &r520_errata, |
.vram_info = &r520_vram_info, |
.vga_set_state = &r100_vga_set_state, |
.gpu_reset = &rv515_gpu_reset, |
.mc_init = &r520_mc_init, |
.mc_fini = &r520_mc_fini, |
// .wb_init = &r100_wb_init, |
// .wb_fini = &r100_wb_fini, |
.gart_enable = &r300_gart_enable, |
.gart_init = &rv370_pcie_gart_init, |
.gart_fini = &rv370_pcie_gart_fini, |
.gart_enable = &rv370_pcie_gart_enable, |
.gart_disable = &rv370_pcie_gart_disable, |
.gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
.gart_set_page = &rv370_pcie_gart_set_page, |
400,6 → 464,7 |
.cp_init = &r100_cp_init, |
// .cp_fini = &r100_cp_fini, |
// .cp_disable = &r100_cp_disable, |
.cp_commit = &r100_cp_commit, |
.ring_start = &rv515_ring_start, |
// .irq_set = &r100_irq_set, |
// .irq_process = &r100_irq_process, |
412,11 → 477,23 |
// .set_memory_clock = &radeon_atom_set_memory_clock, |
// .set_pcie_lanes = &rv370_set_pcie_lanes, |
// .set_clock_gating = &radeon_atom_set_clock_gating, |
.set_surface_reg = r100_set_surface_reg, |
.clear_surface_reg = r100_clear_surface_reg, |
.bandwidth_update = &r520_bandwidth_update, |
}; |
|
/* |
* r600,rv610,rv630,rv620,rv635,rv670,rs780,rv770,rv730,rv710 |
*/ |
int r600_init(struct radeon_device *rdev); |
void r600_fini(struct radeon_device *rdev); |
int r600_suspend(struct radeon_device *rdev); |
int r600_resume(struct radeon_device *rdev); |
void r600_vga_set_state(struct radeon_device *rdev, bool state); |
int r600_wb_init(struct radeon_device *rdev); |
void r600_wb_fini(struct radeon_device *rdev); |
void r600_cp_commit(struct radeon_device *rdev); |
void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); |
void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
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