122,6 → 122,10 |
rdev->mc_rreg = &rs600_mc_rreg; |
rdev->mc_wreg = &rs600_mc_wreg; |
} |
if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { |
rdev->mc_rreg = &rs780_mc_rreg; |
rdev->mc_wreg = &rs780_mc_wreg; |
} |
if (rdev->family >= CHIP_R600) { |
rdev->pciep_rreg = &r600_pciep_rreg; |
rdev->pciep_wreg = &r600_pciep_wreg; |
934,6 → 938,8 |
// .ioctl_wait_idle = r600_ioctl_wait_idle, |
.gui_idle = &r600_gui_idle, |
.mc_wait_for_idle = &r600_mc_wait_for_idle, |
.get_xclk = &r600_get_xclk, |
.get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
.gart = { |
.tlb_flush = &r600_pcie_gart_tlb_flush, |
.set_page = &rs600_gart_set_page, |
946,7 → 952,7 |
// .cs_parse = &r600_cs_parse, |
.ring_test = &r600_ring_test, |
.ib_test = &r600_ib_test, |
.is_lockup = &r600_gpu_is_lockup, |
.is_lockup = &r600_gfx_is_lockup, |
}, |
[R600_RING_TYPE_DMA_INDEX] = { |
.ib_execute = &r600_dma_ring_ib_execute, |
1018,6 → 1024,8 |
// .ioctl_wait_idle = r600_ioctl_wait_idle, |
.gui_idle = &r600_gui_idle, |
.mc_wait_for_idle = &r600_mc_wait_for_idle, |
.get_xclk = &r600_get_xclk, |
.get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
.gart = { |
.tlb_flush = &r600_pcie_gart_tlb_flush, |
.set_page = &rs600_gart_set_page, |
1030,7 → 1038,7 |
// .cs_parse = &r600_cs_parse, |
.ring_test = &r600_ring_test, |
.ib_test = &r600_ib_test, |
.is_lockup = &r600_gpu_is_lockup, |
.is_lockup = &r600_gfx_is_lockup, |
}, |
[R600_RING_TYPE_DMA_INDEX] = { |
.ib_execute = &r600_dma_ring_ib_execute, |
1102,6 → 1110,8 |
// .ioctl_wait_idle = r600_ioctl_wait_idle, |
.gui_idle = &r600_gui_idle, |
.mc_wait_for_idle = &r600_mc_wait_for_idle, |
.get_xclk = &rv770_get_xclk, |
.get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
.gart = { |
.tlb_flush = &r600_pcie_gart_tlb_flush, |
.set_page = &rs600_gart_set_page, |
1114,7 → 1124,7 |
// .cs_parse = &r600_cs_parse, |
.ring_test = &r600_ring_test, |
.ib_test = &r600_ib_test, |
.is_lockup = &r600_gpu_is_lockup, |
.is_lockup = &r600_gfx_is_lockup, |
}, |
[R600_RING_TYPE_DMA_INDEX] = { |
.ib_execute = &r600_dma_ring_ib_execute, |
1124,6 → 1134,15 |
.ring_test = &r600_dma_ring_test, |
.ib_test = &r600_dma_ib_test, |
.is_lockup = &r600_dma_is_lockup, |
}, |
[R600_RING_TYPE_UVD_INDEX] = { |
// .ib_execute = &r600_uvd_ib_execute, |
// .emit_fence = &r600_uvd_fence_emit, |
// .emit_semaphore = &r600_uvd_semaphore_emit, |
// .cs_parse = &radeon_uvd_cs_parse, |
// .ring_test = &r600_uvd_ring_test, |
// .ib_test = &r600_uvd_ib_test, |
// .is_lockup = &radeon_ring_test_lockup, |
} |
}, |
.irq = { |
1140,9 → 1159,9 |
.copy = { |
.blit = &r600_copy_blit, |
.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
.dma = &r600_copy_dma, |
.dma = &rv770_copy_dma, |
.dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
.copy = &r600_copy_dma, |
.copy = &rv770_copy_dma, |
.copy_ring_index = R600_RING_TYPE_DMA_INDEX, |
}, |
.surface = { |
1168,6 → 1187,7 |
// .get_pcie_lanes = &r600_get_pcie_lanes, |
// .set_pcie_lanes = &r600_set_pcie_lanes, |
// .set_clock_gating = &radeon_atom_set_clock_gating, |
.set_uvd_clocks = &rv770_set_uvd_clocks, |
}, |
.pflip = { |
// .pre_page_flip = &rs600_pre_page_flip, |
1186,6 → 1206,8 |
// .ioctl_wait_idle = r600_ioctl_wait_idle, |
.gui_idle = &r600_gui_idle, |
.mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
.get_xclk = &rv770_get_xclk, |
.get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
.gart = { |
.tlb_flush = &evergreen_pcie_gart_tlb_flush, |
.set_page = &rs600_gart_set_page, |
1198,7 → 1220,7 |
// .cs_parse = &evergreen_cs_parse, |
.ring_test = &r600_ring_test, |
.ib_test = &r600_ib_test, |
.is_lockup = &evergreen_gpu_is_lockup, |
.is_lockup = &evergreen_gfx_is_lockup, |
}, |
[R600_RING_TYPE_DMA_INDEX] = { |
.ib_execute = &evergreen_dma_ring_ib_execute, |
1207,7 → 1229,16 |
// .cs_parse = &evergreen_dma_cs_parse, |
.ring_test = &r600_dma_ring_test, |
.ib_test = &r600_dma_ib_test, |
.is_lockup = &r600_dma_is_lockup, |
.is_lockup = &evergreen_dma_is_lockup, |
}, |
[R600_RING_TYPE_UVD_INDEX] = { |
// .ib_execute = &r600_uvd_ib_execute, |
// .emit_fence = &r600_uvd_fence_emit, |
// .emit_semaphore = &r600_uvd_semaphore_emit, |
// .cs_parse = &radeon_uvd_cs_parse, |
// .ring_test = &r600_uvd_ring_test, |
// .ib_test = &r600_uvd_ib_test, |
// .is_lockup = &radeon_ring_test_lockup, |
} |
}, |
.irq = { |
1252,6 → 1283,7 |
// .get_pcie_lanes = &r600_get_pcie_lanes, |
// .set_pcie_lanes = &r600_set_pcie_lanes, |
// .set_clock_gating = NULL, |
.set_uvd_clocks = &evergreen_set_uvd_clocks, |
}, |
.pflip = { |
// .pre_page_flip = &evergreen_pre_page_flip, |
1270,6 → 1302,8 |
// .ioctl_wait_idle = r600_ioctl_wait_idle, |
.gui_idle = &r600_gui_idle, |
.mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
.get_xclk = &r600_get_xclk, |
.get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
.gart = { |
.tlb_flush = &evergreen_pcie_gart_tlb_flush, |
.set_page = &rs600_gart_set_page, |
1282,7 → 1316,7 |
// .cs_parse = &evergreen_cs_parse, |
.ring_test = &r600_ring_test, |
.ib_test = &r600_ib_test, |
.is_lockup = &evergreen_gpu_is_lockup, |
.is_lockup = &evergreen_gfx_is_lockup, |
}, |
[R600_RING_TYPE_DMA_INDEX] = { |
.ib_execute = &evergreen_dma_ring_ib_execute, |
1291,7 → 1325,16 |
// .cs_parse = &evergreen_dma_cs_parse, |
.ring_test = &r600_dma_ring_test, |
.ib_test = &r600_dma_ib_test, |
.is_lockup = &r600_dma_is_lockup, |
.is_lockup = &evergreen_dma_is_lockup, |
}, |
[R600_RING_TYPE_UVD_INDEX] = { |
// .ib_execute = &r600_uvd_ib_execute, |
// .emit_fence = &r600_uvd_fence_emit, |
// .emit_semaphore = &r600_uvd_semaphore_emit, |
// .cs_parse = &radeon_uvd_cs_parse, |
// .ring_test = &r600_uvd_ring_test, |
// .ib_test = &r600_uvd_ib_test, |
// .is_lockup = &radeon_ring_test_lockup, |
} |
}, |
.irq = { |
1336,6 → 1379,7 |
.get_pcie_lanes = NULL, |
.set_pcie_lanes = NULL, |
.set_clock_gating = NULL, |
.set_uvd_clocks = &sumo_set_uvd_clocks, |
}, |
.pflip = { |
// .pre_page_flip = &evergreen_pre_page_flip, |
1354,6 → 1398,8 |
// .ioctl_wait_idle = r600_ioctl_wait_idle, |
.gui_idle = &r600_gui_idle, |
.mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
.get_xclk = &rv770_get_xclk, |
.get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
.gart = { |
.tlb_flush = &evergreen_pcie_gart_tlb_flush, |
.set_page = &rs600_gart_set_page, |
1366,7 → 1412,7 |
// .cs_parse = &evergreen_cs_parse, |
.ring_test = &r600_ring_test, |
.ib_test = &r600_ib_test, |
.is_lockup = &evergreen_gpu_is_lockup, |
.is_lockup = &evergreen_gfx_is_lockup, |
}, |
[R600_RING_TYPE_DMA_INDEX] = { |
.ib_execute = &evergreen_dma_ring_ib_execute, |
1375,7 → 1421,16 |
// .cs_parse = &evergreen_dma_cs_parse, |
.ring_test = &r600_dma_ring_test, |
.ib_test = &r600_dma_ib_test, |
.is_lockup = &r600_dma_is_lockup, |
.is_lockup = &evergreen_dma_is_lockup, |
}, |
[R600_RING_TYPE_UVD_INDEX] = { |
// .ib_execute = &r600_uvd_ib_execute, |
// .emit_fence = &r600_uvd_fence_emit, |
// .emit_semaphore = &r600_uvd_semaphore_emit, |
// .cs_parse = &radeon_uvd_cs_parse, |
// .ring_test = &r600_uvd_ring_test, |
// .ib_test = &r600_uvd_ib_test, |
// .is_lockup = &radeon_ring_test_lockup, |
} |
}, |
.irq = { |
1420,6 → 1475,7 |
.get_pcie_lanes = NULL, |
.set_pcie_lanes = NULL, |
.set_clock_gating = NULL, |
.set_uvd_clocks = &evergreen_set_uvd_clocks, |
}, |
.pflip = { |
// .pre_page_flip = &evergreen_pre_page_flip, |
1438,6 → 1494,8 |
// .ioctl_wait_idle = r600_ioctl_wait_idle, |
.gui_idle = &r600_gui_idle, |
.mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
.get_xclk = &rv770_get_xclk, |
.get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
.gart = { |
.tlb_flush = &cayman_pcie_gart_tlb_flush, |
.set_page = &rs600_gart_set_page, |
1457,7 → 1515,7 |
// .cs_parse = &evergreen_cs_parse, |
.ring_test = &r600_ring_test, |
.ib_test = &r600_ib_test, |
.is_lockup = &evergreen_gpu_is_lockup, |
.is_lockup = &cayman_gfx_is_lockup, |
.vm_flush = &cayman_vm_flush, |
}, |
[CAYMAN_RING_TYPE_CP1_INDEX] = { |
1468,7 → 1526,7 |
// .cs_parse = &evergreen_cs_parse, |
.ring_test = &r600_ring_test, |
.ib_test = &r600_ib_test, |
.is_lockup = &evergreen_gpu_is_lockup, |
.is_lockup = &cayman_gfx_is_lockup, |
.vm_flush = &cayman_vm_flush, |
}, |
[CAYMAN_RING_TYPE_CP2_INDEX] = { |
1479,7 → 1537,7 |
// .cs_parse = &evergreen_cs_parse, |
.ring_test = &r600_ring_test, |
.ib_test = &r600_ib_test, |
.is_lockup = &evergreen_gpu_is_lockup, |
.is_lockup = &cayman_gfx_is_lockup, |
.vm_flush = &cayman_vm_flush, |
}, |
[R600_RING_TYPE_DMA_INDEX] = { |
1503,6 → 1561,15 |
.ib_test = &r600_dma_ib_test, |
.is_lockup = &cayman_dma_is_lockup, |
.vm_flush = &cayman_dma_vm_flush, |
}, |
[R600_RING_TYPE_UVD_INDEX] = { |
// .ib_execute = &r600_uvd_ib_execute, |
// .emit_fence = &r600_uvd_fence_emit, |
// .emit_semaphore = &cayman_uvd_semaphore_emit, |
// .cs_parse = &radeon_uvd_cs_parse, |
// .ring_test = &r600_uvd_ring_test, |
// .ib_test = &r600_uvd_ib_test, |
// .is_lockup = &radeon_ring_test_lockup, |
} |
}, |
.irq = { |
1547,6 → 1614,7 |
.get_pcie_lanes = NULL, |
.set_pcie_lanes = NULL, |
.set_clock_gating = NULL, |
.set_uvd_clocks = &evergreen_set_uvd_clocks, |
}, |
.pflip = { |
// .pre_page_flip = &evergreen_pre_page_flip, |
1565,6 → 1633,8 |
// .ioctl_wait_idle = r600_ioctl_wait_idle, |
.gui_idle = &r600_gui_idle, |
.mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
.get_xclk = &r600_get_xclk, |
.get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
.gart = { |
.tlb_flush = &cayman_pcie_gart_tlb_flush, |
.set_page = &rs600_gart_set_page, |
1584,7 → 1654,7 |
// .cs_parse = &evergreen_cs_parse, |
.ring_test = &r600_ring_test, |
.ib_test = &r600_ib_test, |
.is_lockup = &evergreen_gpu_is_lockup, |
.is_lockup = &cayman_gfx_is_lockup, |
.vm_flush = &cayman_vm_flush, |
}, |
[CAYMAN_RING_TYPE_CP1_INDEX] = { |
1595,7 → 1665,7 |
// .cs_parse = &evergreen_cs_parse, |
.ring_test = &r600_ring_test, |
.ib_test = &r600_ib_test, |
.is_lockup = &evergreen_gpu_is_lockup, |
.is_lockup = &cayman_gfx_is_lockup, |
.vm_flush = &cayman_vm_flush, |
}, |
[CAYMAN_RING_TYPE_CP2_INDEX] = { |
1606,7 → 1676,7 |
// .cs_parse = &evergreen_cs_parse, |
.ring_test = &r600_ring_test, |
.ib_test = &r600_ib_test, |
.is_lockup = &evergreen_gpu_is_lockup, |
.is_lockup = &cayman_gfx_is_lockup, |
.vm_flush = &cayman_vm_flush, |
}, |
[R600_RING_TYPE_DMA_INDEX] = { |
1630,6 → 1700,15 |
.ib_test = &r600_dma_ib_test, |
.is_lockup = &cayman_dma_is_lockup, |
.vm_flush = &cayman_dma_vm_flush, |
}, |
[R600_RING_TYPE_UVD_INDEX] = { |
// .ib_execute = &r600_uvd_ib_execute, |
// .emit_fence = &r600_uvd_fence_emit, |
// .emit_semaphore = &cayman_uvd_semaphore_emit, |
// .cs_parse = &radeon_uvd_cs_parse, |
// .ring_test = &r600_uvd_ring_test, |
// .ib_test = &r600_uvd_ib_test, |
// .is_lockup = &radeon_ring_test_lockup, |
} |
}, |
.irq = { |
1674,6 → 1753,7 |
.get_pcie_lanes = NULL, |
.set_pcie_lanes = NULL, |
.set_clock_gating = NULL, |
.set_uvd_clocks = &sumo_set_uvd_clocks, |
}, |
.pflip = { |
// .pre_page_flip = &evergreen_pre_page_flip, |
1692,6 → 1772,8 |
// .ioctl_wait_idle = r600_ioctl_wait_idle, |
.gui_idle = &r600_gui_idle, |
.mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
.get_xclk = &si_get_xclk, |
.get_gpu_clock_counter = &si_get_gpu_clock_counter, |
.gart = { |
.tlb_flush = &si_pcie_gart_tlb_flush, |
.set_page = &rs600_gart_set_page, |
1711,7 → 1793,7 |
.cs_parse = NULL, |
.ring_test = &r600_ring_test, |
.ib_test = &r600_ib_test, |
.is_lockup = &si_gpu_is_lockup, |
.is_lockup = &si_gfx_is_lockup, |
.vm_flush = &si_vm_flush, |
}, |
[CAYMAN_RING_TYPE_CP1_INDEX] = { |
1722,7 → 1804,7 |
.cs_parse = NULL, |
.ring_test = &r600_ring_test, |
.ib_test = &r600_ib_test, |
.is_lockup = &si_gpu_is_lockup, |
.is_lockup = &si_gfx_is_lockup, |
.vm_flush = &si_vm_flush, |
}, |
[CAYMAN_RING_TYPE_CP2_INDEX] = { |
1733,7 → 1815,7 |
.cs_parse = NULL, |
.ring_test = &r600_ring_test, |
.ib_test = &r600_ib_test, |
.is_lockup = &si_gpu_is_lockup, |
.is_lockup = &si_gfx_is_lockup, |
.vm_flush = &si_vm_flush, |
}, |
[R600_RING_TYPE_DMA_INDEX] = { |
1744,7 → 1826,7 |
.cs_parse = NULL, |
.ring_test = &r600_dma_ring_test, |
.ib_test = &r600_dma_ib_test, |
.is_lockup = &cayman_dma_is_lockup, |
.is_lockup = &si_dma_is_lockup, |
.vm_flush = &si_dma_vm_flush, |
}, |
[CAYMAN_RING_TYPE_DMA1_INDEX] = { |
1755,8 → 1837,17 |
.cs_parse = NULL, |
.ring_test = &r600_dma_ring_test, |
.ib_test = &r600_dma_ib_test, |
.is_lockup = &cayman_dma_is_lockup, |
.is_lockup = &si_dma_is_lockup, |
.vm_flush = &si_dma_vm_flush, |
}, |
[R600_RING_TYPE_UVD_INDEX] = { |
// .ib_execute = &r600_uvd_ib_execute, |
// .emit_fence = &r600_uvd_fence_emit, |
// .emit_semaphore = &cayman_uvd_semaphore_emit, |
// .cs_parse = &radeon_uvd_cs_parse, |
// .ring_test = &r600_uvd_ring_test, |
// .ib_test = &r600_uvd_ib_test, |
// .is_lockup = &radeon_ring_test_lockup, |
} |
}, |
.irq = { |
1801,6 → 1892,7 |
.get_pcie_lanes = NULL, |
.set_pcie_lanes = NULL, |
.set_clock_gating = NULL, |
// .set_uvd_clocks = &si_set_uvd_clocks, |
}, |
.pflip = { |
// .pre_page_flip = &evergreen_pre_page_flip, |
1829,6 → 1921,8 |
else |
rdev->num_crtc = 2; |
|
rdev->has_uvd = false; |
|
switch (rdev->family) { |
case CHIP_R100: |
case CHIP_RV100: |
1893,10 → 1987,15 |
case CHIP_RV635: |
case CHIP_RV670: |
rdev->asic = &r600_asic; |
if (rdev->family == CHIP_R600) |
rdev->has_uvd = false; |
else |
rdev->has_uvd = true; |
break; |
case CHIP_RS780: |
case CHIP_RS880: |
rdev->asic = &rs780_asic; |
rdev->has_uvd = true; |
break; |
case CHIP_RV770: |
case CHIP_RV730: |
1903,6 → 2002,7 |
case CHIP_RV710: |
case CHIP_RV740: |
rdev->asic = &rv770_asic; |
rdev->has_uvd = true; |
break; |
case CHIP_CEDAR: |
case CHIP_REDWOOD: |
1915,11 → 2015,13 |
else |
rdev->num_crtc = 6; |
rdev->asic = &evergreen_asic; |
rdev->has_uvd = true; |
break; |
case CHIP_PALM: |
case CHIP_SUMO: |
case CHIP_SUMO2: |
rdev->asic = &sumo_asic; |
rdev->has_uvd = true; |
break; |
case CHIP_BARTS: |
case CHIP_TURKS: |
1930,23 → 2032,37 |
else |
rdev->num_crtc = 6; |
rdev->asic = &btc_asic; |
rdev->has_uvd = true; |
break; |
case CHIP_CAYMAN: |
rdev->asic = &cayman_asic; |
/* set num crtcs */ |
rdev->num_crtc = 6; |
rdev->has_uvd = true; |
break; |
case CHIP_ARUBA: |
rdev->asic = &trinity_asic; |
/* set num crtcs */ |
rdev->num_crtc = 4; |
rdev->has_uvd = true; |
break; |
case CHIP_TAHITI: |
case CHIP_PITCAIRN: |
case CHIP_VERDE: |
case CHIP_OLAND: |
case CHIP_HAINAN: |
rdev->asic = &si_asic; |
/* set num crtcs */ |
if (rdev->family == CHIP_HAINAN) |
rdev->num_crtc = 0; |
else if (rdev->family == CHIP_OLAND) |
rdev->num_crtc = 2; |
else |
rdev->num_crtc = 6; |
if (rdev->family == CHIP_HAINAN) |
rdev->has_uvd = false; |
else |
rdev->has_uvd = true; |
break; |
default: |
/* FIXME: not supported yet */ |