| 26,6 → 26,7 |
|---|
| #include "drmP.h" |
| #include "radeon_drm.h" |
| #include "radeon.h" |
| #include "radeon_asic.h" |
| #include "atom.h" |
| |
| /* |
| 290,17 → 291,15 |
|---|
| if (!offset) |
| return; |
| |
| if (r600_hdmi_is_audio_buffer_filled(encoder)) { |
| /* disable audio workaround and start delivering of audio frames */ |
| if (!radeon_encoder->hdmi_audio_workaround || |
| r600_hdmi_is_audio_buffer_filled(encoder)) { |
| |
| /* disable audio workaround */ |
| WREG32_P(offset+R600_HDMI_CNTL, 0x00000001, ~0x00001001); |
| |
| } else if (radeon_encoder->hdmi_audio_workaround) { |
| /* enable audio workaround and start delivering of audio frames */ |
| } else { |
| /* enable audio workaround */ |
| WREG32_P(offset+R600_HDMI_CNTL, 0x00001001, ~0x00001001); |
| |
| } else { |
| /* disable audio workaround and stop delivering of audio frames */ |
| WREG32_P(offset+R600_HDMI_CNTL, 0x00000000, ~0x00001001); |
| } |
| } |
| |
| 314,6 → 313,9 |
|---|
| struct radeon_device *rdev = dev->dev_private; |
| uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; |
| |
| if (ASIC_IS_DCE4(rdev)) |
| return; |
| |
| if (!offset) |
| return; |
| |
| 332,7 → 334,7 |
|---|
| r600_hdmi_videoinfoframe(encoder, RGB, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); |
| |
| /* it's unknown what these bits do excatly, but it's indeed quite usefull for debugging */ |
| /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ |
| WREG32(offset+R600_HDMI_AUDIO_DEBUG_0, 0x00FFFFFF); |
| WREG32(offset+R600_HDMI_AUDIO_DEBUG_1, 0x007FFFFF); |
| WREG32(offset+R600_HDMI_AUDIO_DEBUG_2, 0x00000001); |
| 342,25 → 344,23 |
|---|
| |
| /* audio packets per line, does anyone know how to calc this ? */ |
| WREG32_P(offset+R600_HDMI_CNTL, 0x00040000, ~0x001F0000); |
| |
| /* update? reset? don't realy know */ |
| WREG32_P(offset+R600_HDMI_CNTL, 0x14000000, ~0x14000000); |
| } |
| |
| /* |
| * update settings with current parameters from audio engine |
| */ |
| void r600_hdmi_update_audio_settings(struct drm_encoder *encoder, |
| int channels, |
| int rate, |
| int bps, |
| uint8_t status_bits, |
| uint8_t category_code) |
| void r600_hdmi_update_audio_settings(struct drm_encoder *encoder) |
| { |
| struct drm_device *dev = encoder->dev; |
| struct radeon_device *rdev = dev->dev_private; |
| uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; |
| |
| int channels = r600_audio_channels(rdev); |
| int rate = r600_audio_rate(rdev); |
| int bps = r600_audio_bits_per_sample(rdev); |
| uint8_t status_bits = r600_audio_status_bits(rdev); |
| uint8_t category_code = r600_audio_category_code(rdev); |
| |
| uint32_t iec; |
| |
| if (!offset) |
| 412,95 → 412,168 |
|---|
| r600_hdmi_audioinfoframe(encoder, channels-1, 0, 0, 0, 0, 0, 0, 0); |
| |
| r600_hdmi_audio_workaround(encoder); |
| } |
| |
| /* update? reset? don't realy know */ |
| WREG32_P(offset+R600_HDMI_CNTL, 0x04000000, ~0x04000000); |
| static int r600_hdmi_find_free_block(struct drm_device *dev) |
| { |
| struct radeon_device *rdev = dev->dev_private; |
| struct drm_encoder *encoder; |
| struct radeon_encoder *radeon_encoder; |
| bool free_blocks[3] = { true, true, true }; |
| |
| list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| radeon_encoder = to_radeon_encoder(encoder); |
| switch (radeon_encoder->hdmi_offset) { |
| case R600_HDMI_BLOCK1: |
| free_blocks[0] = false; |
| break; |
| case R600_HDMI_BLOCK2: |
| free_blocks[1] = false; |
| break; |
| case R600_HDMI_BLOCK3: |
| free_blocks[2] = false; |
| break; |
| } |
| } |
| |
| if (rdev->family == CHIP_RS600 || rdev->family == CHIP_RS690 || |
| rdev->family == CHIP_RS740) { |
| return free_blocks[0] ? R600_HDMI_BLOCK1 : 0; |
| } else if (rdev->family >= CHIP_R600) { |
| if (free_blocks[0]) |
| return R600_HDMI_BLOCK1; |
| else if (free_blocks[1]) |
| return R600_HDMI_BLOCK2; |
| } |
| return 0; |
| } |
| |
| static void r600_hdmi_assign_block(struct drm_encoder *encoder) |
| { |
| struct drm_device *dev = encoder->dev; |
| struct radeon_device *rdev = dev->dev_private; |
| struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| |
| if (!dig) { |
| dev_err(rdev->dev, "Enabling HDMI on non-dig encoder\n"); |
| return; |
| } |
| |
| if (ASIC_IS_DCE4(rdev)) { |
| /* TODO */ |
| } else if (ASIC_IS_DCE3(rdev)) { |
| radeon_encoder->hdmi_offset = dig->dig_encoder ? |
| R600_HDMI_BLOCK3 : R600_HDMI_BLOCK1; |
| if (ASIC_IS_DCE32(rdev)) |
| radeon_encoder->hdmi_config_offset = dig->dig_encoder ? |
| R600_HDMI_CONFIG2 : R600_HDMI_CONFIG1; |
| } else if (rdev->family >= CHIP_R600 || rdev->family == CHIP_RS600 || |
| rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { |
| radeon_encoder->hdmi_offset = r600_hdmi_find_free_block(dev); |
| } |
| } |
| |
| /* |
| * enable/disable the HDMI engine |
| * enable the HDMI engine |
| */ |
| void r600_hdmi_enable(struct drm_encoder *encoder, int enable) |
| void r600_hdmi_enable(struct drm_encoder *encoder) |
| { |
| struct drm_device *dev = encoder->dev; |
| struct radeon_device *rdev = dev->dev_private; |
| struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; |
| uint32_t offset; |
| |
| if (!offset) |
| if (ASIC_IS_DCE4(rdev)) |
| return; |
| |
| DRM_DEBUG("%s HDMI interface @ 0x%04X\n", enable ? "Enabling" : "Disabling", offset); |
| if (!radeon_encoder->hdmi_offset) { |
| r600_hdmi_assign_block(encoder); |
| if (!radeon_encoder->hdmi_offset) { |
| dev_warn(rdev->dev, "Could not find HDMI block for " |
| "0x%x encoder\n", radeon_encoder->encoder_id); |
| return; |
| } |
| } |
| |
| /* some version of atombios ignore the enable HDMI flag |
| * so enabling/disabling HDMI was moved here for TMDS1+2 */ |
| offset = radeon_encoder->hdmi_offset; |
| if (ASIC_IS_DCE32(rdev) && !ASIC_IS_DCE4(rdev)) { |
| WREG32_P(radeon_encoder->hdmi_config_offset + 0x4, 0x1, ~0x1); |
| } else if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) { |
| switch (radeon_encoder->encoder_id) { |
| case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
| WREG32_P(AVIVO_TMDSA_CNTL, enable ? 0x4 : 0x0, ~0x4); |
| WREG32(offset+R600_HDMI_ENABLE, enable ? 0x101 : 0x0); |
| WREG32_P(AVIVO_TMDSA_CNTL, 0x4, ~0x4); |
| WREG32(offset + R600_HDMI_ENABLE, 0x101); |
| break; |
| |
| case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
| WREG32_P(AVIVO_LVTMA_CNTL, enable ? 0x4 : 0x0, ~0x4); |
| WREG32(offset+R600_HDMI_ENABLE, enable ? 0x105 : 0x0); |
| WREG32_P(AVIVO_LVTMA_CNTL, 0x4, ~0x4); |
| WREG32(offset + R600_HDMI_ENABLE, 0x105); |
| break; |
| |
| case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
| case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
| case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
| /* This part is doubtfull in my opinion */ |
| WREG32(offset+R600_HDMI_ENABLE, enable ? 0x110 : 0x0); |
| break; |
| |
| default: |
| DRM_ERROR("unknown HDMI output type\n"); |
| dev_err(rdev->dev, "Unknown HDMI output type\n"); |
| break; |
| } |
| } |
| #if 0 |
| if (rdev->irq.installed |
| && rdev->family != CHIP_RS600 |
| && rdev->family != CHIP_RS690 |
| && rdev->family != CHIP_RS740) { |
| |
| /* if irq is available use it */ |
| rdev->irq.hdmi[offset == R600_HDMI_BLOCK1 ? 0 : 1] = true; |
| radeon_irq_set(rdev); |
| |
| r600_audio_disable_polling(encoder); |
| } else { |
| /* if not fallback to polling */ |
| r600_audio_enable_polling(encoder); |
| } |
| #endif |
| DRM_DEBUG("Enabling HDMI interface @ 0x%04X for encoder 0x%x\n", |
| radeon_encoder->hdmi_offset, radeon_encoder->encoder_id); |
| } |
| |
| /* |
| * determin at which register offset the HDMI encoder is |
| * disable the HDMI engine |
| */ |
| void r600_hdmi_init(struct drm_encoder *encoder) |
| void r600_hdmi_disable(struct drm_encoder *encoder) |
| { |
| struct drm_device *dev = encoder->dev; |
| struct radeon_device *rdev = dev->dev_private; |
| struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| uint32_t offset; |
| |
| if (ASIC_IS_DCE4(rdev)) |
| return; |
| |
| offset = radeon_encoder->hdmi_offset; |
| if (!offset) { |
| dev_err(rdev->dev, "Disabling not enabled HDMI\n"); |
| return; |
| } |
| |
| DRM_DEBUG("Disabling HDMI interface @ 0x%04X for encoder 0x%x\n", |
| offset, radeon_encoder->encoder_id); |
| |
| if (ASIC_IS_DCE32(rdev) && !ASIC_IS_DCE4(rdev)) { |
| WREG32_P(radeon_encoder->hdmi_config_offset + 0x4, 0, ~0x1); |
| } else if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) { |
| switch (radeon_encoder->encoder_id) { |
| case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
| case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
| radeon_encoder->hdmi_offset = R600_HDMI_TMDS1; |
| WREG32_P(AVIVO_TMDSA_CNTL, 0, ~0x4); |
| WREG32(offset + R600_HDMI_ENABLE, 0); |
| break; |
| |
| case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
| switch (r600_audio_tmds_index(encoder)) { |
| case 0: |
| radeon_encoder->hdmi_offset = R600_HDMI_TMDS1; |
| WREG32_P(AVIVO_LVTMA_CNTL, 0, ~0x4); |
| WREG32(offset + R600_HDMI_ENABLE, 0); |
| break; |
| case 1: |
| radeon_encoder->hdmi_offset = R600_HDMI_TMDS2; |
| break; |
| default: |
| radeon_encoder->hdmi_offset = 0; |
| dev_err(rdev->dev, "Unknown HDMI output type\n"); |
| break; |
| } |
| case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
| radeon_encoder->hdmi_offset = R600_HDMI_TMDS2; |
| break; |
| } |
| |
| case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
| radeon_encoder->hdmi_offset = R600_HDMI_DIG; |
| break; |
| |
| default: |
| radeon_encoder->hdmi_offset = 0; |
| break; |
| radeon_encoder->hdmi_config_offset = 0; |
| } |
| |
| DRM_DEBUG("using HDMI engine at offset 0x%04X for encoder 0x%x\n", |
| radeon_encoder->hdmi_offset, radeon_encoder->encoder_id); |
| |
| /* TODO: make this configureable */ |
| radeon_encoder->hdmi_audio_workaround = 0; |
| } |