| 869,13 → 869,14 |
|---|
| return false; |
| } |
| |
| int r100_copy_blit(struct radeon_device *rdev, |
| struct radeon_fence *r100_copy_blit(struct radeon_device *rdev, |
| uint64_t src_offset, |
| uint64_t dst_offset, |
| unsigned num_gpu_pages, |
| struct radeon_fence **fence) |
| struct reservation_object *resv) |
| { |
| struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
| struct radeon_fence *fence; |
| uint32_t cur_pages; |
| uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE; |
| uint32_t pitch; |
| 896,7 → 897,7 |
|---|
| r = radeon_ring_lock(rdev, ring, ndw); |
| if (r) { |
| DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); |
| return -EINVAL; |
| return ERR_PTR(-EINVAL); |
| } |
| while (num_gpu_pages > 0) { |
| cur_pages = num_gpu_pages; |
| 936,11 → 937,13 |
|---|
| RADEON_WAIT_2D_IDLECLEAN | |
| RADEON_WAIT_HOST_IDLECLEAN | |
| RADEON_WAIT_DMA_GUI_IDLE); |
| if (fence) { |
| r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX); |
| r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX); |
| if (r) { |
| radeon_ring_unlock_undo(rdev, ring); |
| return ERR_PTR(r); |
| } |
| radeon_ring_unlock_commit(rdev, ring, false); |
| return r; |
| return fence; |
| } |
| |
| static int r100_cp_wait_for_idle(struct radeon_device *rdev) |
| 1247,7 → 1250,7 |
|---|
| int r; |
| u32 tile_flags = 0; |
| u32 tmp; |
| struct radeon_cs_reloc *reloc; |
| struct radeon_bo_list *reloc; |
| u32 value; |
| |
| r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
| 1286,7 → 1289,7 |
|---|
| int idx) |
| { |
| unsigned c, i; |
| struct radeon_cs_reloc *reloc; |
| struct radeon_bo_list *reloc; |
| struct r100_cs_track *track; |
| int r = 0; |
| volatile uint32_t *ib; |
| 1535,7 → 1538,7 |
|---|
| struct radeon_cs_packet *pkt, |
| unsigned idx, unsigned reg) |
| { |
| struct radeon_cs_reloc *reloc; |
| struct radeon_bo_list *reloc; |
| struct r100_cs_track *track; |
| volatile uint32_t *ib; |
| uint32_t tmp; |
| 1894,7 → 1897,7 |
|---|
| static int r100_packet3_check(struct radeon_cs_parser *p, |
| struct radeon_cs_packet *pkt) |
| { |
| struct radeon_cs_reloc *reloc; |
| struct radeon_bo_list *reloc; |
| struct r100_cs_track *track; |
| unsigned idx; |
| volatile uint32_t *ib; |
| 2054,7 → 2057,7 |
|---|
| } |
| if (r) |
| return r; |
| } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); |
| } while (p->idx < p->chunk_ib->length_dw); |
| return 0; |
| } |
| |
| 3200,6 → 3203,9 |
|---|
| uint32_t pixel_bytes1 = 0; |
| uint32_t pixel_bytes2 = 0; |
| |
| if (!rdev->mode_info.mode_config_initialized) |
| return; |
| |
| radeon_update_display_priority(rdev); |
| |
| if (rdev->mode_info.crtcs[0]->base.enabled) { |