63,6 → 63,95 |
* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 |
*/ |
|
/* hpd for digital panel detect/disconnect */ |
bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
{ |
bool connected = false; |
|
switch (hpd) { |
case RADEON_HPD_1: |
if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) |
connected = true; |
break; |
case RADEON_HPD_2: |
if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) |
connected = true; |
break; |
default: |
break; |
} |
return connected; |
} |
|
void r100_hpd_set_polarity(struct radeon_device *rdev, |
enum radeon_hpd_id hpd) |
{ |
u32 tmp; |
bool connected = r100_hpd_sense(rdev, hpd); |
|
switch (hpd) { |
case RADEON_HPD_1: |
tmp = RREG32(RADEON_FP_GEN_CNTL); |
if (connected) |
tmp &= ~RADEON_FP_DETECT_INT_POL; |
else |
tmp |= RADEON_FP_DETECT_INT_POL; |
WREG32(RADEON_FP_GEN_CNTL, tmp); |
break; |
case RADEON_HPD_2: |
tmp = RREG32(RADEON_FP2_GEN_CNTL); |
if (connected) |
tmp &= ~RADEON_FP2_DETECT_INT_POL; |
else |
tmp |= RADEON_FP2_DETECT_INT_POL; |
WREG32(RADEON_FP2_GEN_CNTL, tmp); |
break; |
default: |
break; |
} |
} |
|
void r100_hpd_init(struct radeon_device *rdev) |
{ |
struct drm_device *dev = rdev->ddev; |
struct drm_connector *connector; |
|
list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
switch (radeon_connector->hpd.hpd) { |
case RADEON_HPD_1: |
rdev->irq.hpd[0] = true; |
break; |
case RADEON_HPD_2: |
rdev->irq.hpd[1] = true; |
break; |
default: |
break; |
} |
} |
r100_irq_set(rdev); |
} |
|
void r100_hpd_fini(struct radeon_device *rdev) |
{ |
struct drm_device *dev = rdev->ddev; |
struct drm_connector *connector; |
|
list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
switch (radeon_connector->hpd.hpd) { |
case RADEON_HPD_1: |
rdev->irq.hpd[0] = false; |
break; |
case RADEON_HPD_2: |
rdev->irq.hpd[1] = false; |
break; |
default: |
break; |
} |
} |
} |
|
/* |
* PCI GART |
*/ |
92,6 → 181,15 |
return radeon_gart_table_ram_alloc(rdev); |
} |
|
/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ |
void r100_enable_bm(struct radeon_device *rdev) |
{ |
uint32_t tmp; |
/* Enable bus mastering */ |
tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; |
WREG32(RADEON_BUS_CNTL, tmp); |
} |
|
int r100_pci_gart_enable(struct radeon_device *rdev) |
{ |
uint32_t tmp; |
103,9 → 201,6 |
WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location); |
tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
WREG32(RADEON_AIC_HI_ADDR, tmp); |
/* Enable bus mastering */ |
tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; |
WREG32(RADEON_BUS_CNTL, tmp); |
/* set PCI GART page-table base address */ |
WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); |
tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; |
157,8 → 252,9 |
static inline uint32_t r100_irq_ack(struct radeon_device *rdev) |
{ |
uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); |
uint32_t irq_mask = RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT | |
RADEON_CRTC2_VBLANK_STAT; |
uint32_t irq_mask = RADEON_SW_INT_TEST | |
RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT | |
RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT; |
|
if (irqs) { |
WREG32(RADEON_GEN_INT_STATUS, irqs); |
192,24 → 288,27 |
int r; |
|
if (rdev->wb.wb_obj == NULL) { |
r = radeon_object_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, |
true, |
r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true, |
RADEON_GEM_DOMAIN_GTT, |
false, &rdev->wb.wb_obj); |
&rdev->wb.wb_obj); |
if (r) { |
DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r); |
dev_err(rdev->dev, "(%d) create WB buffer failed\n", r); |
return r; |
} |
r = radeon_object_pin(rdev->wb.wb_obj, |
RADEON_GEM_DOMAIN_GTT, |
r = radeon_bo_reserve(rdev->wb.wb_obj, false); |
if (unlikely(r != 0)) |
return r; |
r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, |
&rdev->wb.gpu_addr); |
if (r) { |
DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r); |
dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r); |
radeon_bo_unreserve(rdev->wb.wb_obj); |
return r; |
} |
r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); |
r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); |
radeon_bo_unreserve(rdev->wb.wb_obj); |
if (r) { |
DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r); |
dev_err(rdev->dev, "(%d) map WB buffer failed\n", r); |
return r; |
} |
} |
227,6 → 326,8 |
|
void r100_wb_fini(struct radeon_device *rdev) |
{ |
int r; |
|
r100_wb_disable(rdev); |
if (rdev->wb.wb_obj) { |
// radeon_object_kunmap(rdev->wb.wb_obj); |
1245,17 → 1346,17 |
|
int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
struct radeon_cs_packet *pkt, |
struct radeon_object *robj) |
struct radeon_bo *robj) |
{ |
unsigned idx; |
u32 value; |
idx = pkt->idx + 1; |
value = radeon_get_ib_value(p, idx + 2); |
if ((value + 1) > radeon_object_size(robj)) { |
if ((value + 1) > radeon_bo_size(robj)) { |
DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " |
"(need %u have %lu) !\n", |
value + 1, |
radeon_object_size(robj)); |
radeon_bo_size(robj)); |
return -EINVAL; |
} |
return 0; |
1541,6 → 1642,14 |
r100_hdp_reset(rdev); |
} |
|
void r100_hdp_flush(struct radeon_device *rdev) |
{ |
u32 tmp; |
tmp = RREG32(RADEON_HOST_PATH_CNTL); |
tmp |= RADEON_HDP_READ_BUFFER_INVALIDATE; |
WREG32(RADEON_HOST_PATH_CNTL, tmp); |
} |
|
void r100_hdp_reset(struct radeon_device *rdev) |
{ |
uint32_t tmp; |
1612,6 → 1721,17 |
return 0; |
} |
|
void r100_set_common_regs(struct radeon_device *rdev) |
{ |
/* set these so they don't interfere with anything */ |
WREG32(RADEON_OV0_SCALE_CNTL, 0); |
WREG32(RADEON_SUBPIC_CNTL, 0); |
WREG32(RADEON_VIPH_CONTROL, 0); |
WREG32(RADEON_I2C_CNTL_1, 0); |
WREG32(RADEON_DVI_I2C_CNTL_1, 0); |
WREG32(RADEON_CAP0_TRIG_CNTL, 0); |
WREG32(RADEON_CAP1_TRIG_CNTL, 0); |
} |
|
/* |
* VRAM info |
2677,6 → 2797,9 |
{ |
int r; |
|
/* set common regs */ |
r100_set_common_regs(rdev); |
/* program mc */ |
r100_mc_program(rdev); |
/* Resume clock */ |
r100_clock_startup(rdev); |
2684,6 → 2807,7 |
r100_gpu_init(rdev); |
/* Initialize GART (initialize after TTM so we can allocate |
* memory through TTM but finalize after TTM) */ |
r100_enable_bm(rdev); |
if (rdev->flags & RADEON_IS_PCI) { |
r = r100_pci_gart_enable(rdev); |
if (r) |
2690,7 → 2814,6 |
return r; |
} |
/* Enable IRQ */ |
// rdev->irq.sw_int = true; |
// r100_irq_set(rdev); |
/* 1M ring buffer */ |
// r = r100_cp_init(rdev, 1024 * 1024); |
2772,10 → 2895,8 |
RREG32(R_0007C0_CP_STAT)); |
} |
/* check if cards are posted or not */ |
if (!radeon_card_posted(rdev) && rdev->bios) { |
DRM_INFO("GPU not posted. posting now...\n"); |
radeon_combios_asic_init(rdev->ddev); |
} |
if (radeon_boot_test_post_card(rdev) == false) |
return -EINVAL; |
/* Set asic errata */ |
r100_errata(rdev); |
/* Initialize clocks */ |
2795,7 → 2916,7 |
// if (r) |
// return r; |
/* Memory manager */ |
r = radeon_object_init(rdev); |
r = radeon_bo_init(rdev); |
if (r) |
return r; |
if (rdev->flags & RADEON_IS_PCI) { |