| 45,6 → 45,8 |
|---|
| #define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002 |
| #define CEDAR_GB_ADDR_CONFIG_GOLDEN 0x02010001 |
| #define CAICOS_GB_ADDR_CONFIG_GOLDEN 0x02010001 |
| #define SUMO_GB_ADDR_CONFIG_GOLDEN 0x02010002 |
| #define SUMO2_GB_ADDR_CONFIG_GOLDEN 0x02010002 |
| |
| /* Registers */ |
| |
| 355,6 → 357,54 |
|---|
| # define AFMT_MPEG_INFO_UPDATE (1 << 10) |
| #define AFMT_GENERIC0_7 0x7138 |
| |
| /* DCE4/5 ELD audio interface */ |
| #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x5f84 /* LPCM */ |
| #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x5f88 /* AC3 */ |
| #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x5f8c /* MPEG1 */ |
| #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x5f90 /* MP3 */ |
| #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x5f94 /* MPEG2 */ |
| #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x5f98 /* AAC */ |
| #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x5f9c /* DTS */ |
| #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x5fa0 /* ATRAC */ |
| #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x5fa4 /* one bit audio - leave at 0 (default) */ |
| #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x5fa8 /* Dolby Digital */ |
| #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x5fac /* DTS-HD */ |
| #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x5fb0 /* MAT-MLP */ |
| #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x5fb4 /* DTS */ |
| #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x5fb8 /* WMA Pro */ |
| # define MAX_CHANNELS(x) (((x) & 0x7) << 0) |
| /* max channels minus one. 7 = 8 channels */ |
| # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8) |
| # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16) |
| # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */ |
| /* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO |
| * bit0 = 32 kHz |
| * bit1 = 44.1 kHz |
| * bit2 = 48 kHz |
| * bit3 = 88.2 kHz |
| * bit4 = 96 kHz |
| * bit5 = 176.4 kHz |
| * bit6 = 192 kHz |
| */ |
| |
| #define AZ_HOT_PLUG_CONTROL 0x5e78 |
| # define AZ_FORCE_CODEC_WAKE (1 << 0) |
| # define PIN0_JACK_DETECTION_ENABLE (1 << 4) |
| # define PIN1_JACK_DETECTION_ENABLE (1 << 5) |
| # define PIN2_JACK_DETECTION_ENABLE (1 << 6) |
| # define PIN3_JACK_DETECTION_ENABLE (1 << 7) |
| # define PIN0_UNSOLICITED_RESPONSE_ENABLE (1 << 8) |
| # define PIN1_UNSOLICITED_RESPONSE_ENABLE (1 << 9) |
| # define PIN2_UNSOLICITED_RESPONSE_ENABLE (1 << 10) |
| # define PIN3_UNSOLICITED_RESPONSE_ENABLE (1 << 11) |
| # define CODEC_HOT_PLUG_ENABLE (1 << 12) |
| # define PIN0_AUDIO_ENABLED (1 << 24) |
| # define PIN1_AUDIO_ENABLED (1 << 25) |
| # define PIN2_AUDIO_ENABLED (1 << 26) |
| # define PIN3_AUDIO_ENABLED (1 << 27) |
| # define AUDIO_ENABLED (1 << 31) |
| |
| |
| #define GC_USER_SHADER_PIPE_CONFIG 0x8954 |
| #define INACTIVE_QD_PIPES(x) ((x) << 8) |
| #define INACTIVE_QD_PIPES_MASK 0x0000FF00 |
| 651,6 → 701,7 |
|---|
| #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) |
| #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) |
| #define VM_CONTEXT1_CNTL 0x1414 |
| #define VM_CONTEXT1_CNTL2 0x1434 |
| #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C |
| #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C |
| #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C |
| 672,6 → 723,8 |
|---|
| #define CACHE_UPDATE_MODE(x) ((x) << 6) |
| #define VM_L2_STATUS 0x140C |
| #define L2_BUSY (1 << 0) |
| #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC |
| #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC |
| |
| #define WAIT_UNTIL 0x8040 |
| |
| 689,6 → 742,7 |
|---|
| #define SOFT_RESET_ROM (1 << 14) |
| #define SOFT_RESET_SEM (1 << 15) |
| #define SOFT_RESET_VMC (1 << 17) |
| #define SOFT_RESET_DMA (1 << 20) |
| #define SOFT_RESET_TST (1 << 21) |
| #define SOFT_RESET_REGBB (1 << 22) |
| #define SOFT_RESET_ORB (1 << 23) |
| 854,6 → 908,37 |
|---|
| # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) |
| # define DC_HPDx_EN (1 << 28) |
| |
| /* ASYNC DMA */ |
| #define DMA_RB_RPTR 0xd008 |
| #define DMA_RB_WPTR 0xd00c |
| |
| #define DMA_CNTL 0xd02c |
| # define TRAP_ENABLE (1 << 0) |
| # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) |
| # define SEM_WAIT_INT_ENABLE (1 << 2) |
| # define DATA_SWAP_ENABLE (1 << 3) |
| # define FENCE_SWAP_ENABLE (1 << 4) |
| # define CTXEMPTY_INT_ENABLE (1 << 28) |
| #define DMA_TILING_CONFIG 0xD0B8 |
| |
| #define CAYMAN_DMA1_CNTL 0xd82c |
| |
| /* async DMA packets */ |
| #define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ |
| (((t) & 0x1) << 23) | \ |
| (((s) & 0x1) << 22) | \ |
| (((n) & 0xFFFFF) << 0)) |
| /* async DMA Packet types */ |
| #define DMA_PACKET_WRITE 0x2 |
| #define DMA_PACKET_COPY 0x3 |
| #define DMA_PACKET_INDIRECT_BUFFER 0x4 |
| #define DMA_PACKET_SEMAPHORE 0x5 |
| #define DMA_PACKET_FENCE 0x6 |
| #define DMA_PACKET_TRAP 0x7 |
| #define DMA_PACKET_SRBM_WRITE 0x9 |
| #define DMA_PACKET_CONSTANT_FILL 0xd |
| #define DMA_PACKET_NOP 0xf |
| |
| /* PCIE link stuff */ |
| #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ |
| #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ |
| 951,6 → 1036,53 |
|---|
| #define PACKET3_WAIT_REG_MEM 0x3C |
| #define PACKET3_MEM_WRITE 0x3D |
| #define PACKET3_INDIRECT_BUFFER 0x32 |
| #define PACKET3_CP_DMA 0x41 |
| /* 1. header |
| * 2. SRC_ADDR_LO or DATA [31:0] |
| * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | |
| * SRC_ADDR_HI [7:0] |
| * 4. DST_ADDR_LO [31:0] |
| * 5. DST_ADDR_HI [7:0] |
| * 6. COMMAND [29:22] | BYTE_COUNT [20:0] |
| */ |
| # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) |
| /* 0 - SRC_ADDR |
| * 1 - GDS |
| */ |
| # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) |
| /* 0 - ME |
| * 1 - PFP |
| */ |
| # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) |
| /* 0 - SRC_ADDR |
| * 1 - GDS |
| * 2 - DATA |
| */ |
| # define PACKET3_CP_DMA_CP_SYNC (1 << 31) |
| /* COMMAND */ |
| # define PACKET3_CP_DMA_DIS_WC (1 << 21) |
| # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) |
| /* 0 - none |
| * 1 - 8 in 16 |
| * 2 - 8 in 32 |
| * 3 - 8 in 64 |
| */ |
| # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) |
| /* 0 - none |
| * 1 - 8 in 16 |
| * 2 - 8 in 32 |
| * 3 - 8 in 64 |
| */ |
| # define PACKET3_CP_DMA_CMD_SAS (1 << 26) |
| /* 0 - memory |
| * 1 - register |
| */ |
| # define PACKET3_CP_DMA_CMD_DAS (1 << 27) |
| /* 0 - memory |
| * 1 - register |
| */ |
| # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) |
| # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) |
| #define PACKET3_SURFACE_SYNC 0x43 |
| # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) |
| # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) |
| 1896,4 → 2028,15 |
|---|
| /* cayman packet3 addition */ |
| #define CAYMAN_PACKET3_DEALLOC_STATE 0x14 |
| |
| /* DMA regs common on r6xx/r7xx/evergreen/ni */ |
| #define DMA_RB_CNTL 0xd000 |
| # define DMA_RB_ENABLE (1 << 0) |
| # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ |
| # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ |
| # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) |
| # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ |
| # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ |
| #define DMA_STATUS_REG 0xd034 |
| # define DMA_IDLE (1 << 0) |
| |
| #endif |