43,9 → 43,19 |
|
static inline bool fbc_supported(struct drm_i915_private *dev_priv) |
{ |
return dev_priv->fbc.enable_fbc != NULL; |
return dev_priv->fbc.activate != NULL; |
} |
|
static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv) |
{ |
return IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8; |
} |
|
static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv) |
{ |
return INTEL_INFO(dev_priv)->gen < 4; |
} |
|
/* |
* In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the |
* frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's |
59,11 → 69,51 |
return crtc->base.y - crtc->adjusted_y; |
} |
|
static void i8xx_fbc_disable(struct drm_i915_private *dev_priv) |
/* |
* For SKL+, the plane source size used by the hardware is based on the value we |
* write to the PLANE_SIZE register. For BDW-, the hardware looks at the value |
* we wrote to PIPESRC. |
*/ |
static void intel_fbc_get_plane_source_size(struct intel_crtc *crtc, |
int *width, int *height) |
{ |
struct intel_plane_state *plane_state = |
to_intel_plane_state(crtc->base.primary->state); |
int w, h; |
|
if (intel_rotation_90_or_270(plane_state->base.rotation)) { |
w = drm_rect_height(&plane_state->src) >> 16; |
h = drm_rect_width(&plane_state->src) >> 16; |
} else { |
w = drm_rect_width(&plane_state->src) >> 16; |
h = drm_rect_height(&plane_state->src) >> 16; |
} |
|
if (width) |
*width = w; |
if (height) |
*height = h; |
} |
|
static int intel_fbc_calculate_cfb_size(struct intel_crtc *crtc, |
struct drm_framebuffer *fb) |
{ |
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
int lines; |
|
intel_fbc_get_plane_source_size(crtc, NULL, &lines); |
if (INTEL_INFO(dev_priv)->gen >= 7) |
lines = min(lines, 2048); |
|
/* Hardware needs the full buffer stride, not just the active area. */ |
return lines * fb->pitches[0]; |
} |
|
static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv) |
{ |
u32 fbc_ctl; |
|
dev_priv->fbc.enabled = false; |
dev_priv->fbc.active = false; |
|
/* Disable compression */ |
fbc_ctl = I915_READ(FBC_CONTROL); |
78,11 → 128,9 |
DRM_DEBUG_KMS("FBC idle timed out\n"); |
return; |
} |
|
DRM_DEBUG_KMS("disabled FBC\n"); |
} |
|
static void i8xx_fbc_enable(struct intel_crtc *crtc) |
static void i8xx_fbc_activate(struct intel_crtc *crtc) |
{ |
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
struct drm_framebuffer *fb = crtc->base.primary->fb; |
91,10 → 139,10 |
int i; |
u32 fbc_ctl; |
|
dev_priv->fbc.enabled = true; |
dev_priv->fbc.active = true; |
|
/* Note: fbc.threshold == 1 for i8xx */ |
cfb_pitch = dev_priv->fbc.uncompressed_size / FBC_LL_SIZE; |
cfb_pitch = intel_fbc_calculate_cfb_size(crtc, fb) / FBC_LL_SIZE; |
if (fb->pitches[0] < cfb_pitch) |
cfb_pitch = fb->pitches[0]; |
|
127,17 → 175,14 |
fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
fbc_ctl |= obj->fence_reg; |
I915_WRITE(FBC_CONTROL, fbc_ctl); |
|
DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n", |
cfb_pitch, crtc->base.y, plane_name(crtc->plane)); |
} |
|
static bool i8xx_fbc_enabled(struct drm_i915_private *dev_priv) |
static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv) |
{ |
return I915_READ(FBC_CONTROL) & FBC_CTL_EN; |
} |
|
static void g4x_fbc_enable(struct intel_crtc *crtc) |
static void g4x_fbc_activate(struct intel_crtc *crtc) |
{ |
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
struct drm_framebuffer *fb = crtc->base.primary->fb; |
144,7 → 189,7 |
struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
u32 dpfc_ctl; |
|
dev_priv->fbc.enabled = true; |
dev_priv->fbc.active = true; |
|
dpfc_ctl = DPFC_CTL_PLANE(crtc->plane) | DPFC_SR_EN; |
if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
157,15 → 202,13 |
|
/* enable it... */ |
I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
|
DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane)); |
} |
|
static void g4x_fbc_disable(struct drm_i915_private *dev_priv) |
static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv) |
{ |
u32 dpfc_ctl; |
|
dev_priv->fbc.enabled = false; |
dev_priv->fbc.active = false; |
|
/* Disable compression */ |
dpfc_ctl = I915_READ(DPFC_CONTROL); |
172,23 → 215,22 |
if (dpfc_ctl & DPFC_CTL_EN) { |
dpfc_ctl &= ~DPFC_CTL_EN; |
I915_WRITE(DPFC_CONTROL, dpfc_ctl); |
|
DRM_DEBUG_KMS("disabled FBC\n"); |
} |
} |
|
static bool g4x_fbc_enabled(struct drm_i915_private *dev_priv) |
static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv) |
{ |
return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; |
} |
|
static void intel_fbc_nuke(struct drm_i915_private *dev_priv) |
/* This function forces a CFB recompression through the nuke operation. */ |
static void intel_fbc_recompress(struct drm_i915_private *dev_priv) |
{ |
I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE); |
POSTING_READ(MSG_FBC_REND_STATE); |
} |
|
static void ilk_fbc_enable(struct intel_crtc *crtc) |
static void ilk_fbc_activate(struct intel_crtc *crtc) |
{ |
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
struct drm_framebuffer *fb = crtc->base.primary->fb; |
197,7 → 239,7 |
int threshold = dev_priv->fbc.threshold; |
unsigned int y_offset; |
|
dev_priv->fbc.enabled = true; |
dev_priv->fbc.active = true; |
|
dpfc_ctl = DPFC_CTL_PLANE(crtc->plane); |
if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
231,16 → 273,14 |
I915_WRITE(DPFC_CPU_FENCE_OFFSET, y_offset); |
} |
|
intel_fbc_nuke(dev_priv); |
|
DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane)); |
intel_fbc_recompress(dev_priv); |
} |
|
static void ilk_fbc_disable(struct drm_i915_private *dev_priv) |
static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv) |
{ |
u32 dpfc_ctl; |
|
dev_priv->fbc.enabled = false; |
dev_priv->fbc.active = false; |
|
/* Disable compression */ |
dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
247,17 → 287,15 |
if (dpfc_ctl & DPFC_CTL_EN) { |
dpfc_ctl &= ~DPFC_CTL_EN; |
I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); |
|
DRM_DEBUG_KMS("disabled FBC\n"); |
} |
} |
|
static bool ilk_fbc_enabled(struct drm_i915_private *dev_priv) |
static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv) |
{ |
return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; |
} |
|
static void gen7_fbc_enable(struct intel_crtc *crtc) |
static void gen7_fbc_activate(struct intel_crtc *crtc) |
{ |
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
struct drm_framebuffer *fb = crtc->base.primary->fb; |
265,7 → 303,7 |
u32 dpfc_ctl; |
int threshold = dev_priv->fbc.threshold; |
|
dev_priv->fbc.enabled = true; |
dev_priv->fbc.active = true; |
|
dpfc_ctl = 0; |
if (IS_IVYBRIDGE(dev_priv)) |
310,13 → 348,11 |
SNB_CPU_FENCE_ENABLE | obj->fence_reg); |
I915_WRITE(DPFC_CPU_FENCE_OFFSET, get_crtc_fence_y_offset(crtc)); |
|
intel_fbc_nuke(dev_priv); |
|
DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane)); |
intel_fbc_recompress(dev_priv); |
} |
|
/** |
* intel_fbc_enabled - Is FBC enabled? |
* intel_fbc_is_active - Is FBC active? |
* @dev_priv: i915 device instance |
* |
* This function is used to verify the current state of FBC. |
323,19 → 359,18 |
* FIXME: This should be tracked in the plane config eventually |
* instead of queried at runtime for most callers. |
*/ |
bool intel_fbc_enabled(struct drm_i915_private *dev_priv) |
bool intel_fbc_is_active(struct drm_i915_private *dev_priv) |
{ |
return dev_priv->fbc.enabled; |
return dev_priv->fbc.active; |
} |
|
static void intel_fbc_enable(struct intel_crtc *crtc, |
const struct drm_framebuffer *fb) |
static void intel_fbc_activate(const struct drm_framebuffer *fb) |
{ |
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
struct drm_i915_private *dev_priv = fb->dev->dev_private; |
struct intel_crtc *crtc = dev_priv->fbc.crtc; |
|
dev_priv->fbc.enable_fbc(crtc); |
dev_priv->fbc.activate(crtc); |
|
dev_priv->fbc.crtc = crtc; |
dev_priv->fbc.fb_id = fb->base.id; |
dev_priv->fbc.y = crtc->base.y; |
} |
342,123 → 377,91 |
|
static void intel_fbc_work_fn(struct work_struct *__work) |
{ |
struct intel_fbc_work *work = |
container_of(to_delayed_work(__work), |
struct intel_fbc_work, work); |
struct drm_i915_private *dev_priv = work->crtc->base.dev->dev_private; |
struct drm_framebuffer *crtc_fb = work->crtc->base.primary->fb; |
struct drm_i915_private *dev_priv = |
container_of(__work, struct drm_i915_private, fbc.work.work); |
struct intel_fbc_work *work = &dev_priv->fbc.work; |
struct intel_crtc *crtc = dev_priv->fbc.crtc; |
int delay_ms = 50; |
|
mutex_lock(&dev_priv->fbc.lock); |
if (work == dev_priv->fbc.fbc_work) { |
/* Double check that we haven't switched fb without cancelling |
* the prior work. |
retry: |
/* Delay the actual enabling to let pageflipping cease and the |
* display to settle before starting the compression. Note that |
* this delay also serves a second purpose: it allows for a |
* vblank to pass after disabling the FBC before we attempt |
* to modify the control registers. |
* |
* A more complicated solution would involve tracking vblanks |
* following the termination of the page-flipping sequence |
* and indeed performing the enable as a co-routine and not |
* waiting synchronously upon the vblank. |
* |
* WaFbcWaitForVBlankBeforeEnable:ilk,snb |
*/ |
if (crtc_fb == work->fb) |
intel_fbc_enable(work->crtc, work->fb); |
wait_remaining_ms_from_jiffies(work->enable_jiffies, delay_ms); |
|
dev_priv->fbc.fbc_work = NULL; |
mutex_lock(&dev_priv->fbc.lock); |
|
/* Were we cancelled? */ |
if (!work->scheduled) |
goto out; |
|
/* Were we delayed again while this function was sleeping? */ |
if (time_after(work->enable_jiffies + msecs_to_jiffies(delay_ms), |
jiffies)) { |
mutex_unlock(&dev_priv->fbc.lock); |
goto retry; |
} |
|
if (crtc->base.primary->fb == work->fb) |
intel_fbc_activate(work->fb); |
|
work->scheduled = false; |
|
out: |
mutex_unlock(&dev_priv->fbc.lock); |
|
kfree(work); |
} |
|
static void intel_fbc_cancel_work(struct drm_i915_private *dev_priv) |
{ |
WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
|
if (dev_priv->fbc.fbc_work == NULL) |
return; |
|
DRM_DEBUG_KMS("cancelling pending FBC enable\n"); |
|
/* Synchronisation is provided by struct_mutex and checking of |
* dev_priv->fbc.fbc_work, so we can perform the cancellation |
* entirely asynchronously. |
*/ |
if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work)) |
/* tasklet was killed before being run, clean up */ |
kfree(dev_priv->fbc.fbc_work); |
|
/* Mark the work as no longer wanted so that if it does |
* wake-up (because the work was already running and waiting |
* for our mutex), it will discover that is no longer |
* necessary to run. |
*/ |
dev_priv->fbc.fbc_work = NULL; |
dev_priv->fbc.work.scheduled = false; |
} |
|
static void intel_fbc_schedule_enable(struct intel_crtc *crtc) |
static void intel_fbc_schedule_activation(struct intel_crtc *crtc) |
{ |
struct intel_fbc_work *work; |
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
struct intel_fbc_work *work = &dev_priv->fbc.work; |
|
WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
|
intel_fbc_cancel_work(dev_priv); |
|
work = kzalloc(sizeof(*work), GFP_KERNEL); |
if (work == NULL) { |
DRM_ERROR("Failed to allocate FBC work structure\n"); |
intel_fbc_enable(crtc, crtc->base.primary->fb); |
return; |
} |
|
work->crtc = crtc; |
/* It is useless to call intel_fbc_cancel_work() in this function since |
* we're not releasing fbc.lock, so it won't have an opportunity to grab |
* it to discover that it was cancelled. So we just update the expected |
* jiffy count. */ |
work->fb = crtc->base.primary->fb; |
INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); |
work->scheduled = true; |
work->enable_jiffies = jiffies; |
|
dev_priv->fbc.fbc_work = work; |
|
/* Delay the actual enabling to let pageflipping cease and the |
* display to settle before starting the compression. Note that |
* this delay also serves a second purpose: it allows for a |
* vblank to pass after disabling the FBC before we attempt |
* to modify the control registers. |
* |
* A more complicated solution would involve tracking vblanks |
* following the termination of the page-flipping sequence |
* and indeed performing the enable as a co-routine and not |
* waiting synchronously upon the vblank. |
* |
* WaFbcWaitForVBlankBeforeEnable:ilk,snb |
*/ |
schedule_delayed_work(&work->work, msecs_to_jiffies(50)); |
schedule_work(&work->work); |
} |
|
static void __intel_fbc_disable(struct drm_i915_private *dev_priv) |
static void __intel_fbc_deactivate(struct drm_i915_private *dev_priv) |
{ |
WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
|
intel_fbc_cancel_work(dev_priv); |
|
dev_priv->fbc.disable_fbc(dev_priv); |
dev_priv->fbc.crtc = NULL; |
if (dev_priv->fbc.active) |
dev_priv->fbc.deactivate(dev_priv); |
} |
|
/** |
* intel_fbc_disable - disable FBC |
* @dev_priv: i915 device instance |
* |
* This function disables FBC. |
*/ |
void intel_fbc_disable(struct drm_i915_private *dev_priv) |
{ |
if (!fbc_supported(dev_priv)) |
return; |
|
mutex_lock(&dev_priv->fbc.lock); |
__intel_fbc_disable(dev_priv); |
mutex_unlock(&dev_priv->fbc.lock); |
} |
|
/* |
* intel_fbc_disable_crtc - disable FBC if it's associated with crtc |
* intel_fbc_deactivate - deactivate FBC if it's associated with crtc |
* @crtc: the CRTC |
* |
* This function disables FBC if it's associated with the provided CRTC. |
* This function deactivates FBC if it's associated with the provided CRTC. |
*/ |
void intel_fbc_disable_crtc(struct intel_crtc *crtc) |
void intel_fbc_deactivate(struct intel_crtc *crtc) |
{ |
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
|
467,85 → 470,42 |
|
mutex_lock(&dev_priv->fbc.lock); |
if (dev_priv->fbc.crtc == crtc) |
__intel_fbc_disable(dev_priv); |
__intel_fbc_deactivate(dev_priv); |
mutex_unlock(&dev_priv->fbc.lock); |
} |
|
const char *intel_no_fbc_reason_str(enum no_fbc_reason reason) |
{ |
switch (reason) { |
case FBC_OK: |
return "FBC enabled but currently disabled in hardware"; |
case FBC_UNSUPPORTED: |
return "unsupported by this chipset"; |
case FBC_NO_OUTPUT: |
return "no output"; |
case FBC_STOLEN_TOO_SMALL: |
return "not enough stolen memory"; |
case FBC_UNSUPPORTED_MODE: |
return "mode incompatible with compression"; |
case FBC_MODE_TOO_LARGE: |
return "mode too large for compression"; |
case FBC_BAD_PLANE: |
return "FBC unsupported on plane"; |
case FBC_NOT_TILED: |
return "framebuffer not tiled or fenced"; |
case FBC_MULTIPLE_PIPES: |
return "more than one pipe active"; |
case FBC_MODULE_PARAM: |
return "disabled per module param"; |
case FBC_CHIP_DEFAULT: |
return "disabled per chip default"; |
case FBC_ROTATION: |
return "rotation unsupported"; |
case FBC_IN_DBG_MASTER: |
return "Kernel debugger is active"; |
case FBC_BAD_STRIDE: |
return "framebuffer stride not supported"; |
case FBC_PIXEL_RATE: |
return "pixel rate is too big"; |
case FBC_PIXEL_FORMAT: |
return "pixel format is invalid"; |
default: |
MISSING_CASE(reason); |
return "unknown reason"; |
} |
} |
|
static void set_no_fbc_reason(struct drm_i915_private *dev_priv, |
enum no_fbc_reason reason) |
const char *reason) |
{ |
if (dev_priv->fbc.no_fbc_reason == reason) |
return; |
|
dev_priv->fbc.no_fbc_reason = reason; |
DRM_DEBUG_KMS("Disabling FBC: %s\n", intel_no_fbc_reason_str(reason)); |
DRM_DEBUG_KMS("Disabling FBC: %s\n", reason); |
} |
|
static struct drm_crtc *intel_fbc_find_crtc(struct drm_i915_private *dev_priv) |
static bool crtc_can_fbc(struct intel_crtc *crtc) |
{ |
struct drm_crtc *crtc = NULL, *tmp_crtc; |
enum pipe pipe; |
bool pipe_a_only = false; |
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
|
if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) |
pipe_a_only = true; |
if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A) |
return false; |
|
for_each_pipe(dev_priv, pipe) { |
tmp_crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A) |
return false; |
|
if (intel_crtc_active(tmp_crtc) && |
to_intel_plane_state(tmp_crtc->primary->state)->visible) |
crtc = tmp_crtc; |
|
if (pipe_a_only) |
break; |
return true; |
} |
|
if (!crtc || crtc->primary->fb == NULL) |
return NULL; |
static bool crtc_is_valid(struct intel_crtc *crtc) |
{ |
if (!intel_crtc_active(&crtc->base)) |
return false; |
|
return crtc; |
if (!to_intel_plane_state(crtc->base.primary->state)->visible) |
return false; |
|
return true; |
} |
|
static bool multiple_pipes_ok(struct drm_i915_private *dev_priv) |
581,7 → 541,8 |
* reserved range size, so it always assumes the maximum (8mb) is used. |
* If we enable FBC using a CFB on that memory range we'll get FIFO |
* underruns, even if that range is not reserved by the BIOS. */ |
if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv)) |
if (IS_BROADWELL(dev_priv) || |
IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
end = dev_priv->gtt.stolen_size - 8 * 1024 * 1024; |
else |
end = dev_priv->gtt.stolen_usable_size; |
617,12 → 578,18 |
} |
} |
|
static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv, int size, |
int fb_cpp) |
static int intel_fbc_alloc_cfb(struct intel_crtc *crtc) |
{ |
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
struct drm_framebuffer *fb = crtc->base.primary->state->fb; |
struct drm_mm_node *uninitialized_var(compressed_llb); |
int ret; |
int size, fb_cpp, ret; |
|
WARN_ON(drm_mm_node_allocated(&dev_priv->fbc.compressed_fb)); |
|
size = intel_fbc_calculate_cfb_size(crtc, fb); |
fb_cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
|
ret = find_compression_threshold(dev_priv, &dev_priv->fbc.compressed_fb, |
size, fb_cpp); |
if (!ret) |
656,8 → 623,6 |
dev_priv->mm.stolen_base + compressed_llb->start); |
} |
|
dev_priv->fbc.uncompressed_size = size; |
|
DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n", |
dev_priv->fbc.compressed_fb.size, |
dev_priv->fbc.threshold); |
674,18 → 639,15 |
|
static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) |
{ |
if (dev_priv->fbc.uncompressed_size == 0) |
return; |
if (drm_mm_node_allocated(&dev_priv->fbc.compressed_fb)) |
i915_gem_stolen_remove_node(dev_priv, |
&dev_priv->fbc.compressed_fb); |
|
i915_gem_stolen_remove_node(dev_priv, &dev_priv->fbc.compressed_fb); |
|
if (dev_priv->fbc.compressed_llb) { |
i915_gem_stolen_remove_node(dev_priv, |
dev_priv->fbc.compressed_llb); |
kfree(dev_priv->fbc.compressed_llb); |
} |
|
dev_priv->fbc.uncompressed_size = 0; |
} |
|
void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) |
698,63 → 660,6 |
mutex_unlock(&dev_priv->fbc.lock); |
} |
|
/* |
* For SKL+, the plane source size used by the hardware is based on the value we |
* write to the PLANE_SIZE register. For BDW-, the hardware looks at the value |
* we wrote to PIPESRC. |
*/ |
static void intel_fbc_get_plane_source_size(struct intel_crtc *crtc, |
int *width, int *height) |
{ |
struct intel_plane_state *plane_state = |
to_intel_plane_state(crtc->base.primary->state); |
int w, h; |
|
if (intel_rotation_90_or_270(plane_state->base.rotation)) { |
w = drm_rect_height(&plane_state->src) >> 16; |
h = drm_rect_width(&plane_state->src) >> 16; |
} else { |
w = drm_rect_width(&plane_state->src) >> 16; |
h = drm_rect_height(&plane_state->src) >> 16; |
} |
|
if (width) |
*width = w; |
if (height) |
*height = h; |
} |
|
static int intel_fbc_calculate_cfb_size(struct intel_crtc *crtc) |
{ |
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
struct drm_framebuffer *fb = crtc->base.primary->fb; |
int lines; |
|
intel_fbc_get_plane_source_size(crtc, NULL, &lines); |
if (INTEL_INFO(dev_priv)->gen >= 7) |
lines = min(lines, 2048); |
|
return lines * fb->pitches[0]; |
} |
|
static int intel_fbc_setup_cfb(struct intel_crtc *crtc) |
{ |
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
struct drm_framebuffer *fb = crtc->base.primary->fb; |
int size, cpp; |
|
size = intel_fbc_calculate_cfb_size(crtc); |
cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
|
if (size <= dev_priv->fbc.uncompressed_size) |
return 0; |
|
/* Release any current block */ |
__intel_fbc_cleanup_cfb(dev_priv); |
|
return intel_fbc_alloc_cfb(dev_priv, size, cpp); |
} |
|
static bool stride_is_valid(struct drm_i915_private *dev_priv, |
unsigned int stride) |
{ |
829,28 → 734,15 |
} |
|
/** |
* __intel_fbc_update - enable/disable FBC as needed, unlocked |
* @dev_priv: i915 device instance |
* __intel_fbc_update - activate/deactivate FBC as needed, unlocked |
* @crtc: the CRTC that triggered the update |
* |
* Set up the framebuffer compression hardware at mode set time. We |
* enable it if possible: |
* - plane A only (on pre-965) |
* - no pixel mulitply/line duplication |
* - no alpha buffer discard |
* - no dual wide |
* - framebuffer <= max_hdisplay in width, max_vdisplay in height |
* |
* We can't assume that any compression will take place (worst case), |
* so the compressed buffer has to be the same size as the uncompressed |
* one. It also must reside (along with the line length buffer) in |
* stolen memory. |
* |
* We need to enable/disable FBC on a global basis. |
* This function completely reevaluates the status of FBC, then activates, |
* deactivates or maintains it on the same state. |
*/ |
static void __intel_fbc_update(struct drm_i915_private *dev_priv) |
static void __intel_fbc_update(struct intel_crtc *crtc) |
{ |
struct drm_crtc *crtc = NULL; |
struct intel_crtc *intel_crtc; |
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
struct drm_framebuffer *fb; |
struct drm_i915_gem_object *obj; |
const struct drm_display_mode *adjusted_mode; |
857,102 → 749,79 |
|
WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
|
/* disable framebuffer compression in vGPU */ |
if (intel_vgpu_active(dev_priv->dev)) |
i915.enable_fbc = 0; |
|
if (i915.enable_fbc < 0) { |
set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT); |
if (!multiple_pipes_ok(dev_priv)) { |
set_no_fbc_reason(dev_priv, "more than one pipe active"); |
goto out_disable; |
} |
|
if (!i915.enable_fbc) { |
set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM); |
goto out_disable; |
} |
if (!dev_priv->fbc.enabled || dev_priv->fbc.crtc != crtc) |
return; |
|
/* |
* If FBC is already on, we just have to verify that we can |
* keep it that way... |
* Need to disable if: |
* - more than one pipe is active |
* - changing FBC params (stride, fence, mode) |
* - new fb is too large to fit in compressed buffer |
* - going to an unsupported config (interlace, pixel multiply, etc.) |
*/ |
crtc = intel_fbc_find_crtc(dev_priv); |
if (!crtc) { |
set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT); |
if (!crtc_is_valid(crtc)) { |
set_no_fbc_reason(dev_priv, "no output"); |
goto out_disable; |
} |
|
if (!multiple_pipes_ok(dev_priv)) { |
set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES); |
goto out_disable; |
} |
|
intel_crtc = to_intel_crtc(crtc); |
fb = crtc->primary->fb; |
fb = crtc->base.primary->fb; |
obj = intel_fb_obj(fb); |
adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
adjusted_mode = &crtc->config->base.adjusted_mode; |
|
if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) || |
(adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) { |
set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE); |
set_no_fbc_reason(dev_priv, "incompatible mode"); |
goto out_disable; |
} |
|
if (!intel_fbc_hw_tracking_covers_screen(intel_crtc)) { |
set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE); |
if (!intel_fbc_hw_tracking_covers_screen(crtc)) { |
set_no_fbc_reason(dev_priv, "mode too large for compression"); |
goto out_disable; |
} |
|
if ((INTEL_INFO(dev_priv)->gen < 4 || HAS_DDI(dev_priv)) && |
intel_crtc->plane != PLANE_A) { |
set_no_fbc_reason(dev_priv, FBC_BAD_PLANE); |
goto out_disable; |
} |
|
/* The use of a CPU fence is mandatory in order to detect writes |
* by the CPU to the scanout and trigger updates to the FBC. |
*/ |
if (obj->tiling_mode != I915_TILING_X || |
obj->fence_reg == I915_FENCE_REG_NONE) { |
set_no_fbc_reason(dev_priv, FBC_NOT_TILED); |
set_no_fbc_reason(dev_priv, "framebuffer not tiled or fenced"); |
goto out_disable; |
} |
if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) && |
crtc->primary->state->rotation != BIT(DRM_ROTATE_0)) { |
set_no_fbc_reason(dev_priv, FBC_ROTATION); |
crtc->base.primary->state->rotation != BIT(DRM_ROTATE_0)) { |
set_no_fbc_reason(dev_priv, "rotation unsupported"); |
goto out_disable; |
} |
|
if (!stride_is_valid(dev_priv, fb->pitches[0])) { |
set_no_fbc_reason(dev_priv, FBC_BAD_STRIDE); |
set_no_fbc_reason(dev_priv, "framebuffer stride not supported"); |
goto out_disable; |
} |
|
if (!pixel_format_is_valid(fb)) { |
set_no_fbc_reason(dev_priv, FBC_PIXEL_FORMAT); |
set_no_fbc_reason(dev_priv, "pixel format is invalid"); |
goto out_disable; |
} |
|
/* If the kernel debugger is active, always disable compression */ |
if (in_dbg_master()) { |
set_no_fbc_reason(dev_priv, FBC_IN_DBG_MASTER); |
goto out_disable; |
} |
|
/* WaFbcExceedCdClockThreshold:hsw,bdw */ |
if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) && |
ilk_pipe_pixel_rate(intel_crtc->config) >= |
ilk_pipe_pixel_rate(crtc->config) >= |
dev_priv->cdclk_freq * 95 / 100) { |
set_no_fbc_reason(dev_priv, FBC_PIXEL_RATE); |
set_no_fbc_reason(dev_priv, "pixel rate is too big"); |
goto out_disable; |
} |
|
if (intel_fbc_setup_cfb(intel_crtc)) { |
set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL); |
/* It is possible for the required CFB size change without a |
* crtc->disable + crtc->enable since it is possible to change the |
* stride without triggering a full modeset. Since we try to |
* over-allocate the CFB, there's a chance we may keep FBC enabled even |
* if this happens, but if we exceed the current CFB size we'll have to |
* disable FBC. Notice that it would be possible to disable FBC, wait |
* for a frame, free the stolen node, then try to reenable FBC in case |
* we didn't get any invalidate/deactivate calls, but this would require |
* a lot of tracking just for a specific case. If we conclude it's an |
* important case, we can implement it later. */ |
if (intel_fbc_calculate_cfb_size(crtc, fb) > |
dev_priv->fbc.compressed_fb.size * dev_priv->fbc.threshold) { |
set_no_fbc_reason(dev_priv, "CFB requirements changed"); |
goto out_disable; |
} |
|
961,12 → 830,13 |
* cannot be unpinned (and have its GTT offset and fence revoked) |
* without first being decoupled from the scanout and FBC disabled. |
*/ |
if (dev_priv->fbc.crtc == intel_crtc && |
if (dev_priv->fbc.crtc == crtc && |
dev_priv->fbc.fb_id == fb->base.id && |
dev_priv->fbc.y == crtc->y) |
dev_priv->fbc.y == crtc->base.y && |
dev_priv->fbc.active) |
return; |
|
if (intel_fbc_enabled(dev_priv)) { |
if (intel_fbc_is_active(dev_priv)) { |
/* We update FBC along two paths, after changing fb/crtc |
* configuration (modeswitching) and after page-flipping |
* finishes. For the latter, we know that not only did |
990,36 → 860,37 |
* disabling paths we do need to wait for a vblank at |
* some point. And we wait before enabling FBC anyway. |
*/ |
DRM_DEBUG_KMS("disabling active FBC for update\n"); |
__intel_fbc_disable(dev_priv); |
DRM_DEBUG_KMS("deactivating FBC for update\n"); |
__intel_fbc_deactivate(dev_priv); |
} |
|
intel_fbc_schedule_enable(intel_crtc); |
dev_priv->fbc.no_fbc_reason = FBC_OK; |
intel_fbc_schedule_activation(crtc); |
dev_priv->fbc.no_fbc_reason = "FBC enabled (not necessarily active)"; |
return; |
|
out_disable: |
/* Multiple disables should be harmless */ |
if (intel_fbc_enabled(dev_priv)) { |
DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); |
__intel_fbc_disable(dev_priv); |
if (intel_fbc_is_active(dev_priv)) { |
DRM_DEBUG_KMS("unsupported config, deactivating FBC\n"); |
__intel_fbc_deactivate(dev_priv); |
} |
__intel_fbc_cleanup_cfb(dev_priv); |
} |
|
/* |
* intel_fbc_update - enable/disable FBC as needed |
* @dev_priv: i915 device instance |
* intel_fbc_update - activate/deactivate FBC as needed |
* @crtc: the CRTC that triggered the update |
* |
* This function reevaluates the overall state and enables or disables FBC. |
* This function reevaluates the overall state and activates or deactivates FBC. |
*/ |
void intel_fbc_update(struct drm_i915_private *dev_priv) |
void intel_fbc_update(struct intel_crtc *crtc) |
{ |
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
|
if (!fbc_supported(dev_priv)) |
return; |
|
mutex_lock(&dev_priv->fbc.lock); |
__intel_fbc_update(dev_priv); |
__intel_fbc_update(crtc); |
mutex_unlock(&dev_priv->fbc.lock); |
} |
|
1039,9 → 910,6 |
|
if (dev_priv->fbc.enabled) |
fbc_bits = INTEL_FRONTBUFFER_PRIMARY(dev_priv->fbc.crtc->pipe); |
else if (dev_priv->fbc.fbc_work) |
fbc_bits = INTEL_FRONTBUFFER_PRIMARY( |
dev_priv->fbc.fbc_work->crtc->pipe); |
else |
fbc_bits = dev_priv->fbc.possible_framebuffer_bits; |
|
1048,7 → 916,7 |
dev_priv->fbc.busy_bits |= (fbc_bits & frontbuffer_bits); |
|
if (dev_priv->fbc.busy_bits) |
__intel_fbc_disable(dev_priv); |
__intel_fbc_deactivate(dev_priv); |
|
mutex_unlock(&dev_priv->fbc.lock); |
} |
1066,11 → 934,136 |
|
dev_priv->fbc.busy_bits &= ~frontbuffer_bits; |
|
if (!dev_priv->fbc.busy_bits) { |
if (!dev_priv->fbc.busy_bits && dev_priv->fbc.enabled) { |
if (origin != ORIGIN_FLIP && dev_priv->fbc.active) { |
intel_fbc_recompress(dev_priv); |
} else { |
__intel_fbc_deactivate(dev_priv); |
__intel_fbc_update(dev_priv->fbc.crtc); |
} |
} |
|
mutex_unlock(&dev_priv->fbc.lock); |
} |
|
/** |
* intel_fbc_enable: tries to enable FBC on the CRTC |
* @crtc: the CRTC |
* |
* This function checks if it's possible to enable FBC on the following CRTC, |
* then enables it. Notice that it doesn't activate FBC. |
*/ |
void intel_fbc_enable(struct intel_crtc *crtc) |
{ |
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
|
if (!fbc_supported(dev_priv)) |
return; |
|
mutex_lock(&dev_priv->fbc.lock); |
|
if (dev_priv->fbc.enabled) { |
WARN_ON(dev_priv->fbc.crtc == crtc); |
goto out; |
} |
|
WARN_ON(dev_priv->fbc.active); |
WARN_ON(dev_priv->fbc.crtc != NULL); |
|
if (intel_vgpu_active(dev_priv->dev)) { |
set_no_fbc_reason(dev_priv, "VGPU is active"); |
goto out; |
} |
|
if (i915.enable_fbc < 0) { |
set_no_fbc_reason(dev_priv, "disabled per chip default"); |
goto out; |
} |
|
if (!i915.enable_fbc) { |
set_no_fbc_reason(dev_priv, "disabled per module param"); |
goto out; |
} |
|
if (!crtc_can_fbc(crtc)) { |
set_no_fbc_reason(dev_priv, "no enabled pipes can have FBC"); |
goto out; |
} |
|
if (intel_fbc_alloc_cfb(crtc)) { |
set_no_fbc_reason(dev_priv, "not enough stolen memory"); |
goto out; |
} |
|
DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe)); |
dev_priv->fbc.no_fbc_reason = "FBC enabled but not active yet\n"; |
|
dev_priv->fbc.enabled = true; |
dev_priv->fbc.crtc = crtc; |
out: |
mutex_unlock(&dev_priv->fbc.lock); |
} |
|
/** |
* __intel_fbc_disable - disable FBC |
* @dev_priv: i915 device instance |
* |
* This is the low level function that actually disables FBC. Callers should |
* grab the FBC lock. |
*/ |
static void __intel_fbc_disable(struct drm_i915_private *dev_priv) |
{ |
struct intel_crtc *crtc = dev_priv->fbc.crtc; |
|
WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
WARN_ON(!dev_priv->fbc.enabled); |
WARN_ON(dev_priv->fbc.active); |
assert_pipe_disabled(dev_priv, crtc->pipe); |
|
DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe)); |
|
__intel_fbc_cleanup_cfb(dev_priv); |
|
dev_priv->fbc.enabled = false; |
dev_priv->fbc.crtc = NULL; |
} |
|
/** |
* intel_fbc_disable_crtc - disable FBC if it's associated with crtc |
* @crtc: the CRTC |
* |
* This function disables FBC if it's associated with the provided CRTC. |
*/ |
void intel_fbc_disable_crtc(struct intel_crtc *crtc) |
{ |
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
|
if (!fbc_supported(dev_priv)) |
return; |
|
mutex_lock(&dev_priv->fbc.lock); |
if (dev_priv->fbc.crtc == crtc) { |
WARN_ON(!dev_priv->fbc.enabled); |
WARN_ON(dev_priv->fbc.active); |
__intel_fbc_disable(dev_priv); |
__intel_fbc_update(dev_priv); |
} |
mutex_unlock(&dev_priv->fbc.lock); |
} |
|
/** |
* intel_fbc_disable - globally disable FBC |
* @dev_priv: i915 device instance |
* |
* This function disables FBC regardless of which CRTC is associated with it. |
*/ |
void intel_fbc_disable(struct drm_i915_private *dev_priv) |
{ |
if (!fbc_supported(dev_priv)) |
return; |
|
mutex_lock(&dev_priv->fbc.lock); |
if (dev_priv->fbc.enabled) |
__intel_fbc_disable(dev_priv); |
mutex_unlock(&dev_priv->fbc.lock); |
} |
|
1084,11 → 1077,14 |
{ |
enum pipe pipe; |
|
INIT_WORK(&dev_priv->fbc.work.work, intel_fbc_work_fn); |
mutex_init(&dev_priv->fbc.lock); |
dev_priv->fbc.enabled = false; |
dev_priv->fbc.active = false; |
dev_priv->fbc.work.scheduled = false; |
|
if (!HAS_FBC(dev_priv)) { |
dev_priv->fbc.enabled = false; |
dev_priv->fbc.no_fbc_reason = FBC_UNSUPPORTED; |
dev_priv->fbc.no_fbc_reason = "unsupported by this chipset"; |
return; |
} |
|
1096,30 → 1092,34 |
dev_priv->fbc.possible_framebuffer_bits |= |
INTEL_FRONTBUFFER_PRIMARY(pipe); |
|
if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) |
if (fbc_on_pipe_a_only(dev_priv)) |
break; |
} |
|
if (INTEL_INFO(dev_priv)->gen >= 7) { |
dev_priv->fbc.fbc_enabled = ilk_fbc_enabled; |
dev_priv->fbc.enable_fbc = gen7_fbc_enable; |
dev_priv->fbc.disable_fbc = ilk_fbc_disable; |
dev_priv->fbc.is_active = ilk_fbc_is_active; |
dev_priv->fbc.activate = gen7_fbc_activate; |
dev_priv->fbc.deactivate = ilk_fbc_deactivate; |
} else if (INTEL_INFO(dev_priv)->gen >= 5) { |
dev_priv->fbc.fbc_enabled = ilk_fbc_enabled; |
dev_priv->fbc.enable_fbc = ilk_fbc_enable; |
dev_priv->fbc.disable_fbc = ilk_fbc_disable; |
dev_priv->fbc.is_active = ilk_fbc_is_active; |
dev_priv->fbc.activate = ilk_fbc_activate; |
dev_priv->fbc.deactivate = ilk_fbc_deactivate; |
} else if (IS_GM45(dev_priv)) { |
dev_priv->fbc.fbc_enabled = g4x_fbc_enabled; |
dev_priv->fbc.enable_fbc = g4x_fbc_enable; |
dev_priv->fbc.disable_fbc = g4x_fbc_disable; |
dev_priv->fbc.is_active = g4x_fbc_is_active; |
dev_priv->fbc.activate = g4x_fbc_activate; |
dev_priv->fbc.deactivate = g4x_fbc_deactivate; |
} else { |
dev_priv->fbc.fbc_enabled = i8xx_fbc_enabled; |
dev_priv->fbc.enable_fbc = i8xx_fbc_enable; |
dev_priv->fbc.disable_fbc = i8xx_fbc_disable; |
dev_priv->fbc.is_active = i8xx_fbc_is_active; |
dev_priv->fbc.activate = i8xx_fbc_activate; |
dev_priv->fbc.deactivate = i8xx_fbc_deactivate; |
|
/* This value was pulled out of someone's hat */ |
I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); |
} |
|
dev_priv->fbc.enabled = dev_priv->fbc.fbc_enabled(dev_priv); |
/* We still don't have any sort of hardware state readout for FBC, so |
* deactivate it in case the BIOS activated it to make sure software |
* matches the hardware state. */ |
if (dev_priv->fbc.is_active(dev_priv)) |
dev_priv->fbc.deactivate(dev_priv); |
} |