189,8 → 189,15 |
* shouldn't touch the cache level, especially as that |
* would make the object snooped which might have a |
* negative performance impact. |
* |
* Snooping is required on non-llc platforms in execlist |
* mode, but since all GGTT accesses use PAT entry 0 we |
* get snooping anyway regardless of cache_level. |
* |
* This is only applicable for Ivy Bridge devices since |
* later platforms don't have L3 control bits in the PTE. |
*/ |
if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) { |
if (IS_IVYBRIDGE(dev)) { |
ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC); |
/* Failure shouldn't ever happen this early */ |
if (WARN_ON(ret)) { |
558,7 → 565,7 |
if (signaller == ring) |
continue; |
|
intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base)); |
intel_ring_emit_reg(ring, RING_PSMI_CTL(signaller->mmio_base)); |
intel_ring_emit(ring, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); |
} |
} |
583,7 → 590,7 |
if (signaller == ring) |
continue; |
|
intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base)); |
intel_ring_emit_reg(ring, RING_PSMI_CTL(signaller->mmio_base)); |
intel_ring_emit(ring, _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); |
} |
} |
927,6 → 934,14 |
case I915_CONTEXT_PARAM_NO_ZEROMAP: |
args->value = ctx->flags & CONTEXT_NO_ZEROMAP; |
break; |
case I915_CONTEXT_PARAM_GTT_SIZE: |
if (ctx->ppgtt) |
args->value = ctx->ppgtt->base.total; |
else if (to_i915(dev)->mm.aliasing_ppgtt) |
args->value = to_i915(dev)->mm.aliasing_ppgtt->base.total; |
else |
args->value = to_i915(dev)->gtt.base.total; |
break; |
default: |
ret = -EINVAL; |
break; |
958,7 → 973,8 |
case I915_CONTEXT_PARAM_BAN_PERIOD: |
if (args->size) |
ret = -EINVAL; |
else if (args->value < ctx->hang_stats.ban_period_seconds) |
else if (args->value < ctx->hang_stats.ban_period_seconds && |
!capable(CAP_SYS_ADMIN)) |
ret = -EPERM; |
else |
ctx->hang_stats.ban_period_seconds = args->value; |