/drivers/include/uapi/drm/drm.h |
---|
630,6 → 630,7 |
*/ |
#define DRM_CAP_CURSOR_WIDTH 0x8 |
#define DRM_CAP_CURSOR_HEIGHT 0x9 |
#define DRM_CAP_ADDFB2_MODIFIERS 0x10 |
/** DRM_IOCTL_GET_CAP ioctl argument type */ |
struct drm_get_cap { |
654,6 → 655,13 |
*/ |
#define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2 |
/** |
* DRM_CLIENT_CAP_ATOMIC |
* |
* If set to 1, the DRM core will expose atomic properties to userspace |
*/ |
#define DRM_CLIENT_CAP_ATOMIC 3 |
/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */ |
struct drm_set_client_cap { |
__u64 capability; |
777,6 → 785,9 |
#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties) |
#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property) |
#define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2) |
#define DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic) |
#define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct drm_mode_create_blob) |
#define DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct drm_mode_destroy_blob) |
/** |
* Device specific ioctls should only be in their respective headers |
/drivers/include/uapi/drm/drm_fourcc.h |
---|
34,6 → 34,13 |
/* color index */ |
#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ |
/* 8 bpp Red */ |
#define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ |
/* 16 bpp RG */ |
#define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */ |
#define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */ |
/* 8 bpp RGB */ |
#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ |
#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ |
109,9 → 116,6 |
#define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ |
#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ |
/* special NV12 tiled format */ |
#define DRM_FORMAT_NV12MT fourcc_code('T', 'M', '1', '2') /* 2x2 subsampled Cr:Cb plane 64x32 macroblocks */ |
/* |
* 3 plane YCbCr |
* index 0: Y plane, [7:0] Y |
132,4 → 136,97 |
#define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ |
#define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ |
/* |
* Format Modifiers: |
* |
* Format modifiers describe, typically, a re-ordering or modification |
* of the data in a plane of an FB. This can be used to express tiled/ |
* swizzled formats, or compression, or a combination of the two. |
* |
* The upper 8 bits of the format modifier are a vendor-id as assigned |
* below. The lower 56 bits are assigned as vendor sees fit. |
*/ |
/* Vendor Ids: */ |
#define DRM_FORMAT_MOD_NONE 0 |
#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 |
#define DRM_FORMAT_MOD_VENDOR_AMD 0x02 |
#define DRM_FORMAT_MOD_VENDOR_NV 0x03 |
#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 |
#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 |
/* add more to the end as needed */ |
#define fourcc_mod_code(vendor, val) \ |
((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffULL)) |
/* |
* Format Modifier tokens: |
* |
* When adding a new token please document the layout with a code comment, |
* similar to the fourcc codes above. drm_fourcc.h is considered the |
* authoritative source for all of these. |
*/ |
/* Intel framebuffer modifiers */ |
/* |
* Intel X-tiling layout |
* |
* This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) |
* in row-major layout. Within the tile bytes are laid out row-major, with |
* a platform-dependent stride. On top of that the memory can apply |
* platform-depending swizzling of some higher address bits into bit6. |
* |
* This format is highly platforms specific and not useful for cross-driver |
* sharing. It exists since on a given platform it does uniquely identify the |
* layout in a simple way for i915-specific userspace. |
*/ |
#define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) |
/* |
* Intel Y-tiling layout |
* |
* This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb) |
* in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes) |
* chunks column-major, with a platform-dependent height. On top of that the |
* memory can apply platform-depending swizzling of some higher address bits |
* into bit6. |
* |
* This format is highly platforms specific and not useful for cross-driver |
* sharing. It exists since on a given platform it does uniquely identify the |
* layout in a simple way for i915-specific userspace. |
*/ |
#define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) |
/* |
* Intel Yf-tiling layout |
* |
* This is a tiled layout using 4Kb tiles in row-major layout. |
* Within the tile pixels are laid out in 16 256 byte units / sub-tiles which |
* are arranged in four groups (two wide, two high) with column-major layout. |
* Each group therefore consits out of four 256 byte units, which are also laid |
* out as 2x2 column-major. |
* 256 byte units are made out of four 64 byte blocks of pixels, producing |
* either a square block or a 2:1 unit. |
* 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width |
* in pixel depends on the pixel depth. |
*/ |
#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) |
/* |
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks |
* |
* Macroblocks are laid in a Z-shape, and each pixel data is following the |
* standard NV12 style. |
* As for NV12, an image is the result of two frame buffers: one for Y, |
* one for the interleaved Cb/Cr components (1/2 the height of the Y buffer). |
* Alignment requirements are (for each buffer): |
* - multiple of 128 pixels for the width |
* - multiple of 32 pixels for the height |
* |
* For more information: see http://linuxtv.org/downloads/v4l-dvb-apis/re32.html |
*/ |
#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) |
#endif /* DRM_FOURCC_H */ |
/drivers/include/uapi/drm/drm_mode.h |
---|
105,8 → 105,16 |
struct drm_mode_modeinfo { |
__u32 clock; |
__u16 hdisplay, hsync_start, hsync_end, htotal, hskew; |
__u16 vdisplay, vsync_start, vsync_end, vtotal, vscan; |
__u16 hdisplay; |
__u16 hsync_start; |
__u16 hsync_end; |
__u16 htotal; |
__u16 hskew; |
__u16 vdisplay; |
__u16 vsync_start; |
__u16 vsync_end; |
__u16 vtotal; |
__u16 vscan; |
__u32 vrefresh; |
124,8 → 132,10 |
__u32 count_crtcs; |
__u32 count_connectors; |
__u32 count_encoders; |
__u32 min_width, max_width; |
__u32 min_height, max_height; |
__u32 min_width; |
__u32 max_width; |
__u32 min_height; |
__u32 max_height; |
}; |
struct drm_mode_crtc { |
135,7 → 145,8 |
__u32 crtc_id; /**< Id */ |
__u32 fb_id; /**< Id of framebuffer */ |
__u32 x, y; /**< Position on the frameuffer */ |
__u32 x; /**< x Position on the framebuffer */ |
__u32 y; /**< y Position on the framebuffer */ |
__u32 gamma_size; |
__u32 mode_valid; |
153,12 → 164,16 |
__u32 flags; /* see above flags */ |
/* Signed dest location allows it to be partially off screen */ |
__s32 crtc_x, crtc_y; |
__u32 crtc_w, crtc_h; |
__s32 crtc_x; |
__s32 crtc_y; |
__u32 crtc_w; |
__u32 crtc_h; |
/* Source values are 16.16 fixed point */ |
__u32 src_x, src_y; |
__u32 src_h, src_w; |
__u32 src_x; |
__u32 src_y; |
__u32 src_h; |
__u32 src_w; |
}; |
struct drm_mode_get_plane { |
244,7 → 259,8 |
__u32 connector_type_id; |
__u32 connection; |
__u32 mm_width, mm_height; /**< HxW in millimeters */ |
__u32 mm_width; /**< width in millimeters */ |
__u32 mm_height; /**< height in millimeters */ |
__u32 subpixel; |
__u32 pad; |
272,6 → 288,13 |
#define DRM_MODE_PROP_OBJECT DRM_MODE_PROP_TYPE(1) |
#define DRM_MODE_PROP_SIGNED_RANGE DRM_MODE_PROP_TYPE(2) |
/* the PROP_ATOMIC flag is used to hide properties from userspace that |
* is not aware of atomic properties. This is mostly to work around |
* older userspace (DDX drivers) that read/write each prop they find, |
* witout being aware that this could be triggering a lengthy modeset. |
*/ |
#define DRM_MODE_PROP_ATOMIC 0x80000000 |
struct drm_mode_property_enum { |
__u64 value; |
char name[DRM_PROP_NAME_LEN]; |
320,7 → 343,8 |
struct drm_mode_fb_cmd { |
__u32 fb_id; |
__u32 width, height; |
__u32 width; |
__u32 height; |
__u32 pitch; |
__u32 bpp; |
__u32 depth; |
329,16 → 353,18 |
}; |
#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */ |
#define DRM_MODE_FB_MODIFIERS (1<<1) /* enables ->modifer[] */ |
struct drm_mode_fb_cmd2 { |
__u32 fb_id; |
__u32 width, height; |
__u32 width; |
__u32 height; |
__u32 pixel_format; /* fourcc code from drm_fourcc.h */ |
__u32 flags; /* see above flags */ |
/* |
* In case of planar formats, this ioctl allows up to 4 |
* buffer objects with offets and pitches per plane. |
* buffer objects with offsets and pitches per plane. |
* The pitch and offset order is dictated by the fourcc, |
* e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as: |
* |
346,13 → 372,21 |
* followed by an interleaved U/V plane containing |
* 8 bit 2x2 subsampled colour difference samples. |
* |
* So it would consist of Y as offset[0] and UV as |
* offeset[1]. Note that offset[0] will generally |
* be 0. |
* So it would consist of Y as offsets[0] and UV as |
* offsets[1]. Note that offsets[0] will generally |
* be 0 (but this is not required). |
* |
* To accommodate tiled, compressed, etc formats, a per-plane |
* modifier can be specified. The default value of zero |
* indicates "native" format as specified by the fourcc. |
* Vendor specific modifier token. This allows, for example, |
* different tiling/swizzling pattern on different planes. |
* See discussion above of DRM_FORMAT_MOD_xxx. |
*/ |
__u32 handles[4]; |
__u32 pitches[4]; /* pitch for each plane */ |
__u32 offsets[4]; /* offset of each plane */ |
__u64 modifier[4]; /* ie, tiling, compressed (per plane) */ |
}; |
#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01 |
519,4 → 553,47 |
uint32_t handle; |
}; |
/* page-flip flags are valid, plus: */ |
#define DRM_MODE_ATOMIC_TEST_ONLY 0x0100 |
#define DRM_MODE_ATOMIC_NONBLOCK 0x0200 |
#define DRM_MODE_ATOMIC_ALLOW_MODESET 0x0400 |
#define DRM_MODE_ATOMIC_FLAGS (\ |
DRM_MODE_PAGE_FLIP_EVENT |\ |
DRM_MODE_PAGE_FLIP_ASYNC |\ |
DRM_MODE_ATOMIC_TEST_ONLY |\ |
DRM_MODE_ATOMIC_NONBLOCK |\ |
DRM_MODE_ATOMIC_ALLOW_MODESET) |
struct drm_mode_atomic { |
__u32 flags; |
__u32 count_objs; |
__u64 objs_ptr; |
__u64 count_props_ptr; |
__u64 props_ptr; |
__u64 prop_values_ptr; |
__u64 reserved; |
__u64 user_data; |
}; |
/** |
* Create a new 'blob' data property, copying length bytes from data pointer, |
* and returning new blob ID. |
*/ |
struct drm_mode_create_blob { |
/** Pointer to data to copy. */ |
__u64 data; |
/** Length of data to copy. */ |
__u32 length; |
/** Return: new property ID. */ |
__u32 blob_id; |
}; |
/** |
* Destroy a user-created blob property. |
*/ |
struct drm_mode_destroy_blob { |
__u32 blob_id; |
}; |
#endif |
/drivers/include/uapi/drm/i915_drm.h |
---|
171,8 → 171,12 |
#define I915_BOX_TEXTURE_LOAD 0x8 |
#define I915_BOX_LOST_CONTEXT 0x10 |
/* I915 specific ioctls |
* The device specific ioctl range is 0x40 to 0x79. |
/* |
* i915 specific ioctls. |
* |
* The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie |
* [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset |
* against DRM_COMMAND_BASE and should be between [0x0, 0x60). |
*/ |
#define DRM_I915_INIT 0x00 |
#define DRM_I915_FLUSH 0x01 |
224,6 → 228,8 |
#define DRM_I915_REG_READ 0x31 |
#define DRM_I915_GET_RESET_STATS 0x32 |
#define DRM_I915_GEM_USERPTR 0x33 |
#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 |
#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 |
#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) |
#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) |
268,7 → 274,7 |
#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) |
#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) |
#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) |
#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) |
#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) |
#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) |
#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) |
#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) |
275,6 → 281,8 |
#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) |
#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) |
#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) |
#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) |
#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) |
/* Allow drivers to submit batchbuffers directly to hardware, relying |
* on the security mechanisms provided by hardware. |
341,9 → 349,20 |
#define I915_PARAM_HAS_WT 27 |
#define I915_PARAM_CMD_PARSER_VERSION 28 |
#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 |
#define I915_PARAM_MMAP_VERSION 30 |
#define I915_PARAM_HAS_BSD2 31 |
#define I915_PARAM_REVISION 32 |
#define I915_PARAM_SUBSLICE_TOTAL 33 |
#define I915_PARAM_EU_TOTAL 34 |
#define I915_PARAM_HAS_GPU_RESET 35 |
#define I915_PARAM_HAS_RESOURCE_STREAMER 36 |
typedef struct drm_i915_getparam { |
int param; |
__s32 param; |
/* |
* WARNING: Using pointers instead of fixed-size u64 means we need to write |
* compat32 code. Don't repeat this mistake. |
*/ |
int __user *value; |
} drm_i915_getparam_t; |
488,6 → 507,14 |
* This is a fixed-size type for 32/64 compatibility. |
*/ |
__u64 addr_ptr; |
/** |
* Flags for extended behaviour. |
* |
* Added in version 2. |
*/ |
__u64 flags; |
#define I915_MMAP_WC 0x1 |
}; |
struct drm_i915_gem_mmap_gtt { |
663,7 → 690,8 |
#define EXEC_OBJECT_NEEDS_FENCE (1<<0) |
#define EXEC_OBJECT_NEEDS_GTT (1<<1) |
#define EXEC_OBJECT_WRITE (1<<2) |
#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1) |
#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3) |
#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_SUPPORTS_48B_ADDRESS<<1) |
__u64 flags; |
__u64 rsvd1; |
737,8 → 765,19 |
*/ |
#define I915_EXEC_HANDLE_LUT (1<<12) |
#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1) |
/** Used for switching BSD rings on the platforms with two BSD rings */ |
#define I915_EXEC_BSD_MASK (3<<13) |
#define I915_EXEC_BSD_DEFAULT (0<<13) /* default ping-pong mode */ |
#define I915_EXEC_BSD_RING1 (1<<13) |
#define I915_EXEC_BSD_RING2 (2<<13) |
/** Tell the kernel that the batchbuffer is processed by |
* the resource streamer. |
*/ |
#define I915_EXEC_RESOURCE_STREAMER (1<<15) |
#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_RESOURCE_STREAMER<<1) |
#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) |
#define i915_execbuffer2_set_context_id(eb2, context) \ |
(eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK |
973,6 → 1012,7 |
/* flags */ |
#define I915_OVERLAY_UPDATE_ATTRS (1<<0) |
#define I915_OVERLAY_UPDATE_GAMMA (1<<1) |
#define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2) |
struct drm_intel_overlay_attrs { |
__u32 flags; |
__u32 color_key; |
1042,6 → 1082,14 |
__u64 offset; |
__u64 val; /* Return value */ |
}; |
/* Known registers: |
* |
* Render engine timestamp - 0x2358 + 64bit - gen7+ |
* - Note this register returns an invalid value if using the default |
* single instruction 8byte read, in order to workaround that use |
* offset (0x2538 | 1) instead. |
* |
*/ |
struct drm_i915_reset_stats { |
__u32 ctx_id; |
1073,6 → 1121,16 |
__u32 handle; |
}; |
struct drm_i915_gem_context_param { |
__u32 ctx_id; |
__u32 size; |
__u64 param; |
#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 |
#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 |
__u64 value; |
}; |
struct drm_i915_mask { |
__u32 handle; |
__u32 width; |
1100,6 → 1158,7 |
__u32 height; |
__u32 bo_pitch; |
__u32 bo_map; |
__u32 forced; |
}; |
/drivers/include/uapi/drm/radeon_drm.h |
---|
33,7 → 33,7 |
#ifndef __RADEON_DRM_H__ |
#define __RADEON_DRM_H__ |
#include <drm/drm.h> |
#include "drm.h" |
/* WARNING: If you change any of these defines, make sure to change the |
* defines in the X server file (radeon_sarea.h) |
1034,6 → 1034,12 |
#define RADEON_INFO_VRAM_USAGE 0x1e |
#define RADEON_INFO_GTT_USAGE 0x1f |
#define RADEON_INFO_ACTIVE_CU_COUNT 0x20 |
#define RADEON_INFO_CURRENT_GPU_TEMP 0x21 |
#define RADEON_INFO_CURRENT_GPU_SCLK 0x22 |
#define RADEON_INFO_CURRENT_GPU_MCLK 0x23 |
#define RADEON_INFO_READ_REG 0x24 |
#define RADEON_INFO_VA_UNMAP_WORKING 0x25 |
#define RADEON_INFO_GPU_RESET_COUNTER 0x26 |
struct drm_radeon_info { |
uint32_t request; |
/drivers/include/uapi/drm/vmwgfx_drm.h |
---|
1,6 → 1,6 |
/************************************************************************** |
* |
* Copyright © 2009 VMware, Inc., Palo Alto, CA., USA |
* Copyright © 2009-2015 VMware, Inc., Palo Alto, CA., USA |
* All Rights Reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
64,6 → 64,7 |
#define DRM_VMW_GB_SURFACE_CREATE 23 |
#define DRM_VMW_GB_SURFACE_REF 24 |
#define DRM_VMW_SYNCCPU 25 |
#define DRM_VMW_CREATE_EXTENDED_CONTEXT 26 |
/*************************************************************************/ |
/** |
88,6 → 89,8 |
#define DRM_VMW_PARAM_3D_CAPS_SIZE 8 |
#define DRM_VMW_PARAM_MAX_MOB_MEMORY 9 |
#define DRM_VMW_PARAM_MAX_MOB_SIZE 10 |
#define DRM_VMW_PARAM_SCREEN_TARGET 11 |
#define DRM_VMW_PARAM_DX 12 |
/** |
* enum drm_vmw_handle_type - handle type for ref ioctls |
296,7 → 299,7 |
* Argument to the DRM_VMW_EXECBUF Ioctl. |
*/ |
#define DRM_VMW_EXECBUF_VERSION 1 |
#define DRM_VMW_EXECBUF_VERSION 2 |
struct drm_vmw_execbuf_arg { |
uint64_t commands; |
305,6 → 308,8 |
uint64_t fence_rep; |
uint32_t version; |
uint32_t flags; |
uint32_t context_handle; |
uint32_t pad64; |
}; |
/** |
825,7 → 830,6 |
enum drm_vmw_shader_type { |
drm_vmw_shader_type_vs = 0, |
drm_vmw_shader_type_ps, |
drm_vmw_shader_type_gs |
}; |
907,6 → 911,8 |
* @buffer_handle Buffer handle of backup buffer. SVGA3D_INVALID_ID |
* if none. |
* @base_size Size of the base mip level for all faces. |
* @array_size Must be zero for non-DX hardware, and if non-zero |
* svga3d_flags must have proper bind flags setup. |
* |
* Input argument to the DRM_VMW_GB_SURFACE_CREATE Ioctl. |
* Part of output argument for the DRM_VMW_GB_SURFACE_REF Ioctl. |
919,7 → 925,7 |
uint32_t multisample_count; |
uint32_t autogen_filter; |
uint32_t buffer_handle; |
uint32_t pad64; |
uint32_t array_size; |
struct drm_vmw_size base_size; |
}; |
1059,4 → 1065,28 |
uint32_t pad64; |
}; |
/*************************************************************************/ |
/** |
* DRM_VMW_CREATE_EXTENDED_CONTEXT - Create a host context. |
* |
* Allocates a device unique context id, and queues a create context command |
* for the host. Does not wait for host completion. |
*/ |
enum drm_vmw_extended_context { |
drm_vmw_context_legacy, |
drm_vmw_context_dx |
}; |
/** |
* union drm_vmw_extended_context_arg |
* |
* @req: Context type. |
* @rep: Context identifier. |
* |
* Argument to the DRM_VMW_CREATE_EXTENDED_CONTEXT Ioctl. |
*/ |
union drm_vmw_extended_context_arg { |
enum drm_vmw_extended_context req; |
struct drm_vmw_context_arg rep; |
}; |
#endif |