| 171,8 → 171,12 |
|---|
| #define I915_BOX_TEXTURE_LOAD 0x8 |
| #define I915_BOX_LOST_CONTEXT 0x10 |
| |
| /* I915 specific ioctls |
| * The device specific ioctl range is 0x40 to 0x79. |
| /* |
| * i915 specific ioctls. |
| * |
| * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie |
| * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset |
| * against DRM_COMMAND_BASE and should be between [0x0, 0x60). |
| */ |
| #define DRM_I915_INIT 0x00 |
| #define DRM_I915_FLUSH 0x01 |
| 243,7 → 247,7 |
|---|
| #define DRM_IOCTL_I915_VBLANK_SWAP |
| #define DRM_IOCTL_I915_HWS_ADDR |
| #define DRM_IOCTL_I915_GEM_INIT |
| #define DRM_IOCTL_I915_GEM_EXECBUFFER |
| #define DRM_IOCTL_I915_GEM_EXECBUFFER SRV_I915_GEM_EXECBUFFER |
| #define DRM_IOCTL_I915_GEM_EXECBUFFER2 SRV_I915_GEM_EXECBUFFER2 |
| #define DRM_IOCTL_I915_GEM_PIN SRV_I915_GEM_PIN |
| #define DRM_IOCTL_I915_GEM_UNPIN SRV_I915_GEM_UNPIN |
| 254,7 → 258,7 |
|---|
| #define DRM_IOCTL_I915_GEM_ENTERVT |
| #define DRM_IOCTL_I915_GEM_LEAVEVT |
| #define DRM_IOCTL_I915_GEM_CREATE SRV_I915_GEM_CREATE |
| #define DRM_IOCTL_I915_GEM_PREAD |
| #define DRM_IOCTL_I915_GEM_PREAD SRV_I915_GEM_PREAD |
| #define DRM_IOCTL_I915_GEM_PWRITE SRV_I915_GEM_PWRITE |
| #define DRM_IOCTL_I915_GEM_MMAP SRV_I915_GEM_MMAP |
| #define DRM_IOCTL_I915_GEM_MMAP_GTT SRV_I915_GEM_MMAP_GTT |
| 340,9 → 344,21 |
|---|
| #define I915_PARAM_HAS_WT 27 |
| #define I915_PARAM_CMD_PARSER_VERSION 28 |
| #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 |
| #define I915_PARAM_MMAP_VERSION 30 |
| #define I915_PARAM_HAS_BSD2 31 |
| #define I915_PARAM_REVISION 32 |
| #define I915_PARAM_SUBSLICE_TOTAL 33 |
| #define I915_PARAM_EU_TOTAL 34 |
| #define I915_PARAM_HAS_GPU_RESET 35 |
| #define I915_PARAM_HAS_RESOURCE_STREAMER 36 |
| #define I915_PARAM_HAS_EXEC_SOFTPIN 37 |
| |
| typedef struct drm_i915_getparam { |
| int param; |
| /* |
| * WARNING: Using pointers instead of fixed-size u64 means we need to write |
| * compat32 code. Don't repeat this mistake. |
| */ |
| int *value; |
| } drm_i915_getparam_t; |
| |
| 487,6 → 503,14 |
|---|
| * This is a fixed-size type for 32/64 compatibility. |
| */ |
| __u64 addr_ptr; |
| |
| /** |
| * Flags for extended behaviour. |
| * |
| * Added in version 2. |
| */ |
| __u64 flags; |
| #define I915_MMAP_WC 0x1 |
| }; |
| |
| struct drm_i915_gem_mmap_gtt { |
| 654,8 → 678,12 |
|---|
| __u64 alignment; |
| |
| /** |
| * Returned value of the updated offset of the object, for future |
| * presumed_offset writes. |
| * When the EXEC_OBJECT_PINNED flag is specified this is populated by |
| * the user with the GTT offset at which this object will be pinned. |
| * When the I915_EXEC_NO_RELOC flag is specified this must contain the |
| * presumed_offset of the object. |
| * During execbuffer2 the kernel populates it with the value of the |
| * current GTT offset of the object, for future presumed_offset writes. |
| */ |
| __u64 offset; |
| |
| 662,7 → 690,9 |
|---|
| #define EXEC_OBJECT_NEEDS_FENCE (1<<0) |
| #define EXEC_OBJECT_NEEDS_GTT (1<<1) |
| #define EXEC_OBJECT_WRITE (1<<2) |
| #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1) |
| #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3) |
| #define EXEC_OBJECT_PINNED (1<<4) |
| #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_PINNED<<1) |
| __u64 flags; |
| |
| __u64 rsvd1; |
| 736,8 → 766,19 |
|---|
| */ |
| #define I915_EXEC_HANDLE_LUT (1<<12) |
| |
| #define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1) |
| /** Used for switching BSD rings on the platforms with two BSD rings */ |
| #define I915_EXEC_BSD_MASK (3<<13) |
| #define I915_EXEC_BSD_DEFAULT (0<<13) /* default ping-pong mode */ |
| #define I915_EXEC_BSD_RING1 (1<<13) |
| #define I915_EXEC_BSD_RING2 (2<<13) |
| |
| /** Tell the kernel that the batchbuffer is processed by |
| * the resource streamer. |
| */ |
| #define I915_EXEC_RESOURCE_STREAMER (1<<15) |
| |
| #define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_RESOURCE_STREAMER<<1) |
| |
| #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) |
| #define i915_execbuffer2_set_context_id(eb2, context) \ |
| (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK |
| 972,6 → 1013,7 |
|---|
| /* flags */ |
| #define I915_OVERLAY_UPDATE_ATTRS (1<<0) |
| #define I915_OVERLAY_UPDATE_GAMMA (1<<1) |
| #define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2) |
| struct drm_intel_overlay_attrs { |
| __u32 flags; |
| __u32 color_key; |
| 1038,9 → 1080,23 |
|---|
| }; |
| |
| struct drm_i915_reg_read { |
| /* |
| * Register offset. |
| * For 64bit wide registers where the upper 32bits don't immediately |
| * follow the lower 32bits, the offset of the lower 32bits must |
| * be specified |
| */ |
| __u64 offset; |
| __u64 val; /* Return value */ |
| }; |
| /* Known registers: |
| * |
| * Render engine timestamp - 0x2358 + 64bit - gen7+ |
| * - Note this register returns an invalid value if using the default |
| * single instruction 8byte read, in order to workaround that use |
| * offset (0x2538 | 1) instead. |
| * |
| */ |
| |
| struct drm_i915_reset_stats { |
| __u32 ctx_id; |
| 1072,6 → 1128,16 |
|---|
| __u32 handle; |
| }; |
| |
| struct drm_i915_gem_context_param { |
| __u32 ctx_id; |
| __u32 size; |
| __u64 param; |
| #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 |
| #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 |
| #define I915_CONTEXT_PARAM_GTT_SIZE 0x3 |
| __u64 value; |
| }; |
| |
| struct drm_i915_mask { |
| __u32 handle; |
| __u32 width; |