WebSVN – Kolibri OS – Path Comparison – / – /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/ Rev 4357 and /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/ Rev 4358

Regard whitespace Rev 4357 → Rev 4358

 /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/Android.mk
 ,0 → 1,38
+# Mesa 3-D graphics library
+#
+# Copyright (C) 2010-2011 Chia-I Wu <olvaffe@gmail.com>
+# Copyright (C) 2010-2011 LunarG Inc.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included
+# in all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+LOCAL_PATH := $(call my-dir)
+# get C_SOURCES
+include $(LOCAL_PATH)/Makefile.sources
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES := $(C_SOURCES)
+LOCAL_C_INCLUDES :=
+LOCAL_MODULE := libmesa_pipe_radeonsi
+include $(GALLIUM_COMMON_MK)
+include $(BUILD_STATIC_LIBRARY)

 /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/Makefile.am
 ,0 → 1,38
+# Copyright © 2012 Intel Corporation
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice (including the next
+# paragraph) shall be included in all copies or substantial portions of the
+# Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+# NONINFRINGEMENT.  IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+# HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+include Makefile.sources
+include $(top_srcdir)/src/gallium/Automake.inc
+noinst_LTLIBRARIES = libradeonsi.la
+AM_CPPFLAGS = \
+        -I$(top_srcdir)/src/gallium/drivers/radeon \
+        -I$(top_srcdir)/src/gallium/drivers \
+        -I$(top_srcdir)/include \
+        $(GALLIUM_CFLAGS)
+AM_CFLAGS = $(LLVM_CFLAGS)
+libradeonsi_la_SOURCES = $(C_SOURCES)
+libradeonsi_la_LIBADD = \
+        ../radeon/libradeon.la \
+        ../radeon/libllvmradeon.la

 /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/Makefile.in
 ,0 → 1,824
+# Makefile.in generated by automake 1.14 from Makefile.am.
+# @configure_input@
+# Copyright (C) 1994-2013 Free Software Foundation, Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+@SET_MAKE@
+# Copyright © 2012 Intel Corporation
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice (including the next
+# paragraph) shall be included in all copies or substantial portions of the
+# Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+# NONINFRINGEMENT.  IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+# HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+VPATH = @srcdir@
+am__is_gnu_make = test -n '$(MAKEFILE_LIST)' && test -n '$(MAKELEVEL)'
+am__make_running_with_option = \
+  case $${target_option-} in \
+      ?) ;; \
+      *) echo "am__make_running_with_option: internal error: invalid" \
+              "target option '$${target_option-}' specified" >&2; \
+         exit 1;; \
+  esac; \
+  has_opt=no; \
+  sane_makeflags=$$MAKEFLAGS; \
+  if $(am__is_gnu_make); then \
+    sane_makeflags=$$MFLAGS; \
+  else \
+    case $$MAKEFLAGS in \
+      *\\[\ \   ]*) \
+        bs=\\; \
+        sane_makeflags=`printf '%s\n' "$$MAKEFLAGS" \
+          | sed "s/$$bs$$bs[$$bs $$bs   ]*//g"`;; \
+    esac; \
+  fi; \
+  skip_next=no; \
+  strip_trailopt () \
+  { \
+    flg=`printf '%s\n' "$$flg" | sed "s/$$1.*$$//"`; \
+  }; \
+  for flg in $$sane_makeflags; do \
+    test $$skip_next = yes && { skip_next=no; continue; }; \
+    case $$flg in \
+      *=*|--*) continue;; \
+        -*I) strip_trailopt 'I'; skip_next=yes;; \
+      -*I?*) strip_trailopt 'I';; \
+        -*O) strip_trailopt 'O'; skip_next=yes;; \
+      -*O?*) strip_trailopt 'O';; \
+        -*l) strip_trailopt 'l'; skip_next=yes;; \
+      -*l?*) strip_trailopt 'l';; \
+      -[dEDm]) skip_next=yes;; \
+      -[JT]) skip_next=yes;; \
+    esac; \
+    case $$flg in \
+      *$$target_option*) has_opt=yes; break;; \
+    esac; \
+  done; \
+  test $$has_opt = yes
+am__make_dryrun = (target_option=n; $(am__make_running_with_option))
+am__make_keepgoing = (target_option=k; $(am__make_running_with_option))
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+target_triplet = @target@
+DIST_COMMON = $(srcdir)/Makefile.sources \
+        $(top_srcdir)/src/gallium/Automake.inc $(srcdir)/Makefile.in \
+        $(srcdir)/Makefile.am $(top_srcdir)/bin/depcomp
+subdir = src/gallium/drivers/radeonsi
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/m4/ax_prog_bison.m4 \
+        $(top_srcdir)/m4/ax_prog_cc_for_build.m4 \
+        $(top_srcdir)/m4/ax_prog_cxx_for_build.m4 \
+        $(top_srcdir)/m4/ax_prog_flex.m4 \
+        $(top_srcdir)/m4/ax_pthread.m4 \
+        $(top_srcdir)/m4/ax_python_module.m4 \
+        $(top_srcdir)/m4/libtool.m4 $(top_srcdir)/m4/ltoptions.m4 \
+        $(top_srcdir)/m4/ltsugar.m4 $(top_srcdir)/m4/ltversion.m4 \
+        $(top_srcdir)/m4/lt~obsolete.m4 $(top_srcdir)/configure.ac
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+        $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+LTLIBRARIES = $(noinst_LTLIBRARIES)
+libradeonsi_la_DEPENDENCIES = ../radeon/libradeon.la \
+        ../radeon/libllvmradeon.la
+am__objects_1 = r600_blit.lo r600_buffer.lo r600_hw_context.lo \
+        radeonsi_pipe.lo r600_query.lo r600_resource.lo \
+        radeonsi_shader.lo r600_texture.lo r600_translate.lo \
+        radeonsi_pm4.lo radeonsi_compute.lo si_state.lo \
+        si_state_streamout.lo si_state_draw.lo si_commands.lo \
+        radeonsi_uvd.lo
+am_libradeonsi_la_OBJECTS = $(am__objects_1)
+libradeonsi_la_OBJECTS = $(am_libradeonsi_la_OBJECTS)
+AM_V_lt = $(am__v_lt_@AM_V@)
+am__v_lt_ = $(am__v_lt_@AM_DEFAULT_V@)
+am__v_lt_0 = --silent
+am__v_lt_1 =
+AM_V_P = $(am__v_P_@AM_V@)
+am__v_P_ = $(am__v_P_@AM_DEFAULT_V@)
+am__v_P_0 = false
+am__v_P_1 = :
+AM_V_GEN = $(am__v_GEN_@AM_V@)
+am__v_GEN_ = $(am__v_GEN_@AM_DEFAULT_V@)
+am__v_GEN_0 = @echo "  GEN     " $@;
+am__v_GEN_1 =
+AM_V_at = $(am__v_at_@AM_V@)
+am__v_at_ = $(am__v_at_@AM_DEFAULT_V@)
+am__v_at_0 = @
+am__v_at_1 =
+DEFAULT_INCLUDES = -I.@am__isrc@
+depcomp = $(SHELL) $(top_srcdir)/bin/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+        $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+LTCOMPILE = $(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) \
+        $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) \
+        $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) \
+        $(AM_CFLAGS) $(CFLAGS)
+AM_V_CC = $(am__v_CC_@AM_V@)
+am__v_CC_ = $(am__v_CC_@AM_DEFAULT_V@)
+am__v_CC_0 = @echo "  CC      " $@;
+am__v_CC_1 =
+CCLD = $(CC)
+LINK = $(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) \
+        $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \
+        $(AM_LDFLAGS) $(LDFLAGS) -o $@
+AM_V_CCLD = $(am__v_CCLD_@AM_V@)
+am__v_CCLD_ = $(am__v_CCLD_@AM_DEFAULT_V@)
+am__v_CCLD_0 = @echo "  CCLD    " $@;
+am__v_CCLD_1 =
+SOURCES = $(libradeonsi_la_SOURCES)
+DIST_SOURCES = $(libradeonsi_la_SOURCES)
+am__can_run_installinfo = \
+  case $$AM_UPDATE_INFO_DIR in \
+    n|no|NO) false;; \
+    *) (install-info --version) >/dev/null 2>&1;; \
+  esac
+am__tagged_files = $(HEADERS) $(SOURCES) $(TAGS_FILES) $(LISP)
+# Read a list of newline-separated strings from the standard input,
+# and print each of them once, without duplicates.  Input order is
+# *not* preserved.
+am__uniquify_input = $(AWK) '\
+  BEGIN { nonempty = 0; } \
+  { items[$$0] = 1; nonempty = 1; } \
+  END { if (nonempty) { for (i in items) print i; }; } \
+'
+# Make sure the list of sources is unique.  This is necessary because,
+# e.g., the same source file might be shared among _SOURCES variables
+# for different programs/libraries.
+am__define_uniq_tagged_files = \
+  list='$(am__tagged_files)'; \
+  unique=`for i in $$list; do \
+    if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+  done | $(am__uniquify_input)`
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AM_DEFAULT_VERBOSITY = @AM_DEFAULT_VERBOSITY@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BUILD_EXEEXT = @BUILD_EXEEXT@
+BUILD_OBJEXT = @BUILD_OBJEXT@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CC_FOR_BUILD = @CC_FOR_BUILD@
+CFLAGS = @CFLAGS@
+CFLAGS_FOR_BUILD = @CFLAGS_FOR_BUILD@
+CLANG_RESOURCE_DIR = @CLANG_RESOURCE_DIR@
+CLOCK_LIB = @CLOCK_LIB@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CPPFLAGS_FOR_BUILD = @CPPFLAGS_FOR_BUILD@
+CPP_FOR_BUILD = @CPP_FOR_BUILD@
+CXX = @CXX@
+CXXCPP = @CXXCPP@
+CXXCPPFLAGS_FOR_BUILD = @CXXCPPFLAGS_FOR_BUILD@
+CXXCPP_FOR_BUILD = @CXXCPP_FOR_BUILD@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CXXFLAGS_FOR_BUILD = @CXXFLAGS_FOR_BUILD@
+CXX_FOR_BUILD = @CXX_FOR_BUILD@
+CYGPATH_W = @CYGPATH_W@
+DEFINES = @DEFINES@
+DEFINES_FOR_BUILD = @DEFINES_FOR_BUILD@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DLLTOOL = @DLLTOOL@
+DLOPEN_LIBS = @DLOPEN_LIBS@
+DRI2PROTO_CFLAGS = @DRI2PROTO_CFLAGS@
+DRI2PROTO_LIBS = @DRI2PROTO_LIBS@
+DRIGL_CFLAGS = @DRIGL_CFLAGS@
+DRIGL_LIBS = @DRIGL_LIBS@
+DRI_DRIVER_INSTALL_DIR = @DRI_DRIVER_INSTALL_DIR@
+DRI_DRIVER_SEARCH_DIR = @DRI_DRIVER_SEARCH_DIR@
+DRI_LIB_DEPS = @DRI_LIB_DEPS@
+DRI_PC_REQ_PRIV = @DRI_PC_REQ_PRIV@
+DSYMUTIL = @DSYMUTIL@
+DUMPBIN = @DUMPBIN@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGL_CFLAGS = @EGL_CFLAGS@
+EGL_CLIENT_APIS = @EGL_CLIENT_APIS@
+EGL_DRIVER_INSTALL_DIR = @EGL_DRIVER_INSTALL_DIR@
+EGL_LIB_DEPS = @EGL_LIB_DEPS@
+EGL_LIB_GLOB = @EGL_LIB_GLOB@
+EGL_LIB_NAME = @EGL_LIB_NAME@
+EGL_NATIVE_PLATFORM = @EGL_NATIVE_PLATFORM@
+EGL_PLATFORMS = @EGL_PLATFORMS@
+EGREP = @EGREP@
+ELF_LIB = @ELF_LIB@
+EXEEXT = @EXEEXT@
+EXPAT_INCLUDES = @EXPAT_INCLUDES@
+FGREP = @FGREP@
+FREEDRENO_CFLAGS = @FREEDRENO_CFLAGS@
+FREEDRENO_LIBS = @FREEDRENO_LIBS@
+GALLIUM_DRI_LIB_DEPS = @GALLIUM_DRI_LIB_DEPS@
+GALLIUM_PIPE_LOADER_DEFINES = @GALLIUM_PIPE_LOADER_DEFINES@
+GALLIUM_PIPE_LOADER_LIBS = @GALLIUM_PIPE_LOADER_LIBS@
+GALLIUM_PIPE_LOADER_XCB_CFLAGS = @GALLIUM_PIPE_LOADER_XCB_CFLAGS@
+GALLIUM_PIPE_LOADER_XCB_LIBS = @GALLIUM_PIPE_LOADER_XCB_LIBS@
+GBM_PC_LIB_PRIV = @GBM_PC_LIB_PRIV@
+GBM_PC_REQ_PRIV = @GBM_PC_REQ_PRIV@
+GLAPI_LIB_GLOB = @GLAPI_LIB_GLOB@
+GLAPI_LIB_NAME = @GLAPI_LIB_NAME@
+GLESv1_CM_LIB_DEPS = @GLESv1_CM_LIB_DEPS@
+GLESv1_CM_LIB_GLOB = @GLESv1_CM_LIB_GLOB@
+GLESv1_CM_LIB_NAME = @GLESv1_CM_LIB_NAME@
+GLESv1_CM_PC_LIB_PRIV = @GLESv1_CM_PC_LIB_PRIV@
+GLESv2_LIB_DEPS = @GLESv2_LIB_DEPS@
+GLESv2_LIB_GLOB = @GLESv2_LIB_GLOB@
+GLESv2_LIB_NAME = @GLESv2_LIB_NAME@
+GLESv2_PC_LIB_PRIV = @GLESv2_PC_LIB_PRIV@
+GLPROTO_CFLAGS = @GLPROTO_CFLAGS@
+GLPROTO_LIBS = @GLPROTO_LIBS@
+GLX_TLS = @GLX_TLS@
+GL_LIB = @GL_LIB@
+GL_LIB_DEPS = @GL_LIB_DEPS@
+GL_LIB_GLOB = @GL_LIB_GLOB@
+GL_LIB_NAME = @GL_LIB_NAME@
+GL_PC_CFLAGS = @GL_PC_CFLAGS@
+GL_PC_LIB_PRIV = @GL_PC_LIB_PRIV@
+GL_PC_REQ_PRIV = @GL_PC_REQ_PRIV@
+GREP = @GREP@
+HAVE_XF86VIDMODE = @HAVE_XF86VIDMODE@
+INDENT = @INDENT@
+INDENT_FLAGS = @INDENT_FLAGS@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+INTEL_CFLAGS = @INTEL_CFLAGS@
+INTEL_LIBS = @INTEL_LIBS@
+LD = @LD@
+LDFLAGS = @LDFLAGS@
+LDFLAGS_FOR_BUILD = @LDFLAGS_FOR_BUILD@
+LEX = @LEX@
+LEXLIB = @LEXLIB@
+LEX_OUTPUT_ROOT = @LEX_OUTPUT_ROOT@
+LIBCLC_INCLUDEDIR = @LIBCLC_INCLUDEDIR@
+LIBCLC_LIBEXECDIR = @LIBCLC_LIBEXECDIR@
+LIBDRM_CFLAGS = @LIBDRM_CFLAGS@
+LIBDRM_LIBS = @LIBDRM_LIBS@
+LIBDRM_XORG_CFLAGS = @LIBDRM_XORG_CFLAGS@
+LIBDRM_XORG_LIBS = @LIBDRM_XORG_LIBS@
+LIBKMS_XORG_CFLAGS = @LIBKMS_XORG_CFLAGS@
+LIBKMS_XORG_LIBS = @LIBKMS_XORG_LIBS@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LIBTOOL = @LIBTOOL@
+LIBUDEV_CFLAGS = @LIBUDEV_CFLAGS@
+LIBUDEV_LIBS = @LIBUDEV_LIBS@
+LIB_DIR = @LIB_DIR@
+LIPO = @LIPO@
+LLVM_BINDIR = @LLVM_BINDIR@
+LLVM_CFLAGS = @LLVM_CFLAGS@
+LLVM_CONFIG = @LLVM_CONFIG@
+LLVM_CPPFLAGS = @LLVM_CPPFLAGS@
+LLVM_CXXFLAGS = @LLVM_CXXFLAGS@
+LLVM_INCLUDEDIR = @LLVM_INCLUDEDIR@
+LLVM_LDFLAGS = @LLVM_LDFLAGS@
+LLVM_LIBDIR = @LLVM_LIBDIR@
+LLVM_LIBS = @LLVM_LIBS@
+LLVM_VERSION = @LLVM_VERSION@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAKE = @MAKE@
+MAKEINFO = @MAKEINFO@
+MANIFEST_TOOL = @MANIFEST_TOOL@
+MESA_LLVM = @MESA_LLVM@
+MKDIR_P = @MKDIR_P@
+NM = @NM@
+NMEDIT = @NMEDIT@
+NOUVEAU_CFLAGS = @NOUVEAU_CFLAGS@
+NOUVEAU_LIBS = @NOUVEAU_LIBS@
+OBJDUMP = @OBJDUMP@
+OBJEXT = @OBJEXT@
+OPENCL_LIB_INSTALL_DIR = @OPENCL_LIB_INSTALL_DIR@
+OSMESA_LIB = @OSMESA_LIB@
+OSMESA_LIB_DEPS = @OSMESA_LIB_DEPS@
+OSMESA_LIB_NAME = @OSMESA_LIB_NAME@
+OSMESA_MESA_DEPS = @OSMESA_MESA_DEPS@
+OSMESA_PC_LIB_PRIV = @OSMESA_PC_LIB_PRIV@
+OSMESA_PC_REQ = @OSMESA_PC_REQ@
+OSMESA_VERSION = @OSMESA_VERSION@
+OTOOL = @OTOOL@
+OTOOL64 = @OTOOL64@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PKG_CONFIG = @PKG_CONFIG@
+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@
+POSIX_SHELL = @POSIX_SHELL@
+PTHREAD_CC = @PTHREAD_CC@
+PTHREAD_CFLAGS = @PTHREAD_CFLAGS@
+PTHREAD_LIBS = @PTHREAD_LIBS@
+PYTHON2 = @PYTHON2@
+RADEON_CFLAGS = @RADEON_CFLAGS@
+RADEON_LIBS = @RADEON_LIBS@
+RANLIB = @RANLIB@
+SED = @SED@
+SELINUX_LIBS = @SELINUX_LIBS@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VDPAU_CFLAGS = @VDPAU_CFLAGS@
+VDPAU_LIBS = @VDPAU_LIBS@
+VDPAU_LIB_INSTALL_DIR = @VDPAU_LIB_INSTALL_DIR@
+VDPAU_MAJOR = @VDPAU_MAJOR@
+VDPAU_MINOR = @VDPAU_MINOR@
+VERSION = @VERSION@
+VG_LIB_DEPS = @VG_LIB_DEPS@
+VG_LIB_GLOB = @VG_LIB_GLOB@
+VG_LIB_NAME = @VG_LIB_NAME@
+VG_PC_LIB_PRIV = @VG_PC_LIB_PRIV@
+VISIBILITY_CFLAGS = @VISIBILITY_CFLAGS@
+VISIBILITY_CXXFLAGS = @VISIBILITY_CXXFLAGS@
+WAYLAND_CFLAGS = @WAYLAND_CFLAGS@
+WAYLAND_LIBS = @WAYLAND_LIBS@
+WAYLAND_SCANNER = @WAYLAND_SCANNER@
+X11_INCLUDES = @X11_INCLUDES@
+XA_MAJOR = @XA_MAJOR@
+XA_MINOR = @XA_MINOR@
+XA_TINY = @XA_TINY@
+XA_VERSION = @XA_VERSION@
+XCB_DRI2_CFLAGS = @XCB_DRI2_CFLAGS@
+XCB_DRI2_LIBS = @XCB_DRI2_LIBS@
+XEXT_CFLAGS = @XEXT_CFLAGS@
+XEXT_LIBS = @XEXT_LIBS@
+XF86VIDMODE_CFLAGS = @XF86VIDMODE_CFLAGS@
+XF86VIDMODE_LIBS = @XF86VIDMODE_LIBS@
+XLIBGL_CFLAGS = @XLIBGL_CFLAGS@
+XLIBGL_LIBS = @XLIBGL_LIBS@
+XORG_CFLAGS = @XORG_CFLAGS@
+XORG_DRIVER_INSTALL_DIR = @XORG_DRIVER_INSTALL_DIR@
+XORG_LIBS = @XORG_LIBS@
+XVMC_CFLAGS = @XVMC_CFLAGS@
+XVMC_LIBS = @XVMC_LIBS@
+XVMC_LIB_INSTALL_DIR = @XVMC_LIB_INSTALL_DIR@
+XVMC_MAJOR = @XVMC_MAJOR@
+XVMC_MINOR = @XVMC_MINOR@
+YACC = @YACC@
+YFLAGS = @YFLAGS@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_AR = @ac_ct_AR@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CC_FOR_BUILD = @ac_ct_CC_FOR_BUILD@
+ac_ct_CXX = @ac_ct_CXX@
+ac_ct_CXX_FOR_BUILD = @ac_ct_CXX_FOR_BUILD@
+ac_ct_DUMPBIN = @ac_ct_DUMPBIN@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+ax_pthread_config = @ax_pthread_config@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target = @target@
+target_alias = @target_alias@
+target_cpu = @target_cpu@
+target_os = @target_os@
+target_vendor = @target_vendor@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+C_SOURCES := \
+        r600_blit.c \
+        r600_buffer.c \
+        r600_hw_context.c \
+        radeonsi_pipe.c \
+        r600_query.c \
+        r600_resource.c \
+        radeonsi_shader.c \
+        r600_texture.c \
+        r600_translate.c \
+        radeonsi_pm4.c \
+        radeonsi_compute.c \
+        si_state.c \
+        si_state_streamout.c \
+        si_state_draw.c \
+        si_commands.c \
+        radeonsi_uvd.c
+GALLIUM_CFLAGS = \
+        -I$(top_srcdir)/include \
+        -I$(top_srcdir)/src/gallium/include \
+        -I$(top_srcdir)/src/gallium/auxiliary \
+        $(DEFINES)
+noinst_LTLIBRARIES = libradeonsi.la
+AM_CPPFLAGS = \
+        -I$(top_srcdir)/src/gallium/drivers/radeon \
+        -I$(top_srcdir)/src/gallium/drivers \
+        -I$(top_srcdir)/include \
+        $(GALLIUM_CFLAGS)
+AM_CFLAGS = $(LLVM_CFLAGS)
+libradeonsi_la_SOURCES = $(C_SOURCES)
+libradeonsi_la_LIBADD = \
+        ../radeon/libradeon.la \
+        ../radeon/libllvmradeon.la
+all: all-am
+.SUFFIXES:
+.SUFFIXES: .c .lo .o .obj
+$(srcdir)/Makefile.in:  $(srcdir)/Makefile.am $(srcdir)/Makefile.sources $(top_srcdir)/src/gallium/Automake.inc $(am__configure_deps)
+        @for dep in $?; do \
+          case '$(am__configure_deps)' in \
+            *$$dep*) \
+              ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+                && { if test -f $@; then exit 0; else break; fi; }; \
+              exit 1;; \
+          esac; \
+        done; \
+        echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign src/gallium/drivers/radeonsi/Makefile'; \
+        $(am__cd) $(top_srcdir) && \
+          $(AUTOMAKE) --foreign src/gallium/drivers/radeonsi/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+        @case '$?' in \
+          *config.status*) \
+            cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+          *) \
+            echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+            cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+        esac;
+$(srcdir)/Makefile.sources $(top_srcdir)/src/gallium/Automake.inc:
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+        cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(top_srcdir)/configure:  $(am__configure_deps)
+        cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4):  $(am__aclocal_m4_deps)
+        cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+clean-noinstLTLIBRARIES:
+        -test -z "$(noinst_LTLIBRARIES)" || rm -f $(noinst_LTLIBRARIES)
+        @list='$(noinst_LTLIBRARIES)'; \
+        locs=`for p in $$list; do echo $$p; done | \
+              sed 's|^[^/]*$$|.|; s|/[^/]*$$||; s|$$|/so_locations|' | \
+              sort -u`; \
+        test -z "$$locs" || { \
+          echo rm -f $${locs}; \
+          rm -f $${locs}; \
+        }
+libradeonsi.la: $(libradeonsi_la_OBJECTS) $(libradeonsi_la_DEPENDENCIES) $(EXTRA_libradeonsi_la_DEPENDENCIES)
+        $(AM_V_CCLD)$(LINK)  $(libradeonsi_la_OBJECTS) $(libradeonsi_la_LIBADD) $(LIBS)
+mostlyclean-compile:
+        -rm -f *.$(OBJEXT)
+distclean-compile:
+        -rm -f *.tab.c
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/r600_blit.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/r600_buffer.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/r600_hw_context.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/r600_query.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/r600_resource.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/r600_texture.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/r600_translate.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeonsi_compute.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeonsi_pipe.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeonsi_pm4.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeonsi_shader.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/radeonsi_uvd.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/si_commands.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/si_state.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/si_state_draw.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/si_state_streamout.Plo@am__quote@
+.c.o:
+@am__fastdepCC_TRUE@    $(AM_V_CC)$(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@    $(AM_V_at)$(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@       $(AM_V_CC)source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@       DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@   $(AM_V_CC@am__nodep@)$(COMPILE) -c -o $@ $<
+.c.obj:
+@am__fastdepCC_TRUE@    $(AM_V_CC)$(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@    $(AM_V_at)$(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@       $(AM_V_CC)source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@       DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@   $(AM_V_CC@am__nodep@)$(COMPILE) -c -o $@ `$(CYGPATH_W) '$<'`
+.c.lo:
+@am__fastdepCC_TRUE@    $(AM_V_CC)$(LTCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@    $(AM_V_at)$(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Plo
+@AMDEP_TRUE@@am__fastdepCC_FALSE@       $(AM_V_CC)source='$<' object='$@' libtool=yes @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@       DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@   $(AM_V_CC@am__nodep@)$(LTCOMPILE) -c -o $@ $<
+mostlyclean-libtool:
+        -rm -f *.lo
+clean-libtool:
+        -rm -rf .libs _libs
+ID: $(am__tagged_files)
+        $(am__define_uniq_tagged_files); mkid -fID $$unique
+tags: tags-am
+TAGS: tags
+tags-am: $(TAGS_DEPENDENCIES) $(am__tagged_files)
+        set x; \
+        here=`pwd`; \
+        $(am__define_uniq_tagged_files); \
+        shift; \
+        if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+          test -n "$$unique" || unique=$$empty_fix; \
+          if test $$# -gt 0; then \
+            $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+              "$$@" $$unique; \
+          else \
+            $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+              $$unique; \
+          fi; \
+        fi
+ctags: ctags-am
+CTAGS: ctags
+ctags-am: $(TAGS_DEPENDENCIES) $(am__tagged_files)
+        $(am__define_uniq_tagged_files); \
+        test -z "$(CTAGS_ARGS)$$unique" \
+          || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+             $$unique
+GTAGS:
+        here=`$(am__cd) $(top_builddir) && pwd` \
+          && $(am__cd) $(top_srcdir) \
+          && gtags -i $(GTAGS_ARGS) "$$here"
+cscopelist: cscopelist-am
+cscopelist-am: $(am__tagged_files)
+        list='$(am__tagged_files)'; \
+        case "$(srcdir)" in \
+          [\\/]* | ?:[\\/]*) sdir="$(srcdir)" ;; \
+          *) sdir=$(subdir)/$(srcdir) ;; \
+        esac; \
+        for i in $$list; do \
+          if test -f "$$i"; then \
+            echo "$(subdir)/$$i"; \
+          else \
+            echo "$$sdir/$$i"; \
+          fi; \
+        done >> $(top_builddir)/cscope.files
+distclean-tags:
+        -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+distdir: $(DISTFILES)
+        @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+        topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+        list='$(DISTFILES)'; \
+          dist_files=`for file in $$list; do echo $$file; done | \
+          sed -e "s|^$$srcdirstrip/||;t" \
+              -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+        case $$dist_files in \
+          */*) $(MKDIR_P) `echo "$$dist_files" | \
+                           sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+                           sort -u` ;; \
+        esac; \
+        for file in $$dist_files; do \
+          if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+          if test -d $$d/$$file; then \
+            dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+            if test -d "$(distdir)/$$file"; then \
+              find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+            fi; \
+            if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+              cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+              find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+            fi; \
+            cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+          else \
+            test -f "$(distdir)/$$file" \
+            || cp -p $$d/$$file "$(distdir)/$$file" \
+            || exit 1; \
+          fi; \
+        done
+check-am: all-am
+check: check-am
+all-am: Makefile $(LTLIBRARIES)
+installdirs:
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+install-am: all-am
+        @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+installcheck: installcheck-am
+install-strip:
+        if test -z '$(STRIP)'; then \
+          $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+            install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+              install; \
+        else \
+          $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+            install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+            "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'" install; \
+        fi
+mostlyclean-generic:
+clean-generic:
+distclean-generic:
+        -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+        -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+maintainer-clean-generic:
+        @echo "This command is intended for maintainers to use"
+        @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+clean-am: clean-generic clean-libtool clean-noinstLTLIBRARIES \
+        mostlyclean-am
+distclean: distclean-am
+        -rm -rf ./$(DEPDIR)
+        -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+        distclean-tags
+dvi: dvi-am
+dvi-am:
+html: html-am
+html-am:
+info: info-am
+info-am:
+install-data-am:
+install-dvi: install-dvi-am
+install-dvi-am:
+install-exec-am:
+install-html: install-html-am
+install-html-am:
+install-info: install-info-am
+install-info-am:
+install-man:
+install-pdf: install-pdf-am
+install-pdf-am:
+install-ps: install-ps-am
+install-ps-am:
+installcheck-am:
+maintainer-clean: maintainer-clean-am
+        -rm -rf ./$(DEPDIR)
+        -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+mostlyclean: mostlyclean-am
+mostlyclean-am: mostlyclean-compile mostlyclean-generic \
+        mostlyclean-libtool
+pdf: pdf-am
+pdf-am:
+ps: ps-am
+ps-am:
+uninstall-am:
+.MAKE: install-am install-strip
+.PHONY: CTAGS GTAGS TAGS all all-am check check-am clean clean-generic \
+        clean-libtool clean-noinstLTLIBRARIES cscopelist-am ctags \
+        ctags-am distclean distclean-compile distclean-generic \
+        distclean-libtool distclean-tags distdir dvi dvi-am html \
+        html-am info info-am install install-am install-data \
+        install-data-am install-dvi install-dvi-am install-exec \
+        install-exec-am install-html install-html-am install-info \
+        install-info-am install-man install-pdf install-pdf-am \
+        install-ps install-ps-am install-strip installcheck \
+        installcheck-am installdirs maintainer-clean \
+        maintainer-clean-generic mostlyclean mostlyclean-compile \
+        mostlyclean-generic mostlyclean-libtool pdf pdf-am ps ps-am \
+        tags tags-am uninstall uninstall-am
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:

 /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/Makefile.sources
 ,0 → 1,17
+C_SOURCES := \
+        r600_blit.c \
+        r600_buffer.c \
+        r600_hw_context.c \
+        radeonsi_pipe.c \
+        r600_query.c \
+        r600_resource.c \
+        radeonsi_shader.c \
+        r600_texture.c \
+        r600_translate.c \
+        radeonsi_pm4.c \
+        radeonsi_compute.c \
+        si_state.c \
+        si_state_streamout.c \
+        si_state_draw.c \
+        si_commands.c \
+        radeonsi_uvd.c

 /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/r600.h
 ,0 → 1,109
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#ifndef R600_H
+#define R600_H
+#include "../../winsys/radeon/drm/radeon_winsys.h"
+#include "util/u_double_list.h"
+#include "util/u_transfer.h"
+#include "radeonsi_resource.h"
+#define R600_ERR(fmt, args...) \
+        fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
+struct winsys_handle;
+struct r600_tiling_info {
+        unsigned num_channels;
+        unsigned num_banks;
+        unsigned group_bytes;
+};
+/* R600/R700 STATES */
+struct r600_query {
+        union {
+                uint64_t                        u64;
+                boolean                         b;
+                struct pipe_query_data_so_statistics so;
+        } result;
+        /* The kind of query */
+        unsigned                                type;
+        /* Offset of the first result for current query */
+        unsigned                                results_start;
+        /* Offset of the next free result after current query data */
+        unsigned                                results_end;
+        /* Size of the result in memory for both begin_query and end_query,
+         * this can be one or two numbers, or it could even be a size of a structure. */
+        unsigned                                result_size;
+        /* The buffer where query results are stored. It's used as a ring,
+         * data blocks for current query are stored sequentially from
+         * results_start to results_end, with wrapping on the buffer end */
+        struct si_resource                      *buffer;
+        /* The number of dwords for begin_query or end_query. */
+        unsigned                                num_cs_dw;
+        /* linked list of queries */
+        struct list_head                        list;
+};
+struct r600_so_target {
+        struct pipe_stream_output_target b;
+        /* The buffer where BUFFER_FILLED_SIZE is stored. */
+        struct si_resource      *filled_size;
+        unsigned                stride;
+        unsigned                so_index;
+};
+#define R600_CONTEXT_DST_CACHES_DIRTY   (1 << 1)
+#define R600_CONTEXT_CHECK_EVENT_FLUSH  (1 << 2)
+struct r600_context;
+struct r600_screen;
+void si_get_backend_mask(struct r600_context *ctx);
+void si_context_flush(struct r600_context *ctx, unsigned flags);
+struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type);
+void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query);
+boolean r600_context_query_result(struct r600_context *ctx,
+                                struct r600_query *query,
+                                boolean wait, void *vresult);
+void r600_query_begin(struct r600_context *ctx, struct r600_query *query);
+void r600_query_end(struct r600_context *ctx, struct r600_query *query);
+void r600_context_queries_suspend(struct r600_context *ctx);
+void r600_context_queries_resume(struct r600_context *ctx);
+void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation,
+                            int flag_wait);
+void si_context_emit_fence(struct r600_context *ctx, struct si_resource *fence,
+                           unsigned offset, unsigned value);
+void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_target *t);
+void si_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
+int si_context_init(struct r600_context *ctx);
+#endif

 /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/r600_blit.c
 ,0 → 1,501
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include "util/u_surface.h"
+#include "util/u_blitter.h"
+#include "util/u_format.h"
+#include "radeonsi_pipe.h"
+#include "si_state.h"
+enum r600_blitter_op /* bitmask */
+{
+        R600_SAVE_TEXTURES      = 1,
+        R600_SAVE_FRAMEBUFFER   = 2,
+        R600_DISABLE_RENDER_COND = 4,
+        R600_CLEAR         = 0,
+        R600_CLEAR_SURFACE = R600_SAVE_FRAMEBUFFER,
+        R600_COPY          = R600_SAVE_FRAMEBUFFER | R600_SAVE_TEXTURES |
+                             R600_DISABLE_RENDER_COND,
+        R600_BLIT          = R600_SAVE_FRAMEBUFFER | R600_SAVE_TEXTURES |
+                             R600_DISABLE_RENDER_COND,
+        R600_DECOMPRESS    = R600_SAVE_FRAMEBUFFER | R600_DISABLE_RENDER_COND,
+};
+static void r600_blitter_begin(struct pipe_context *ctx, enum r600_blitter_op op)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        r600_context_queries_suspend(rctx);
+        util_blitter_save_blend(rctx->blitter, rctx->queued.named.blend);
+        util_blitter_save_depth_stencil_alpha(rctx->blitter, rctx->queued.named.dsa);
+        util_blitter_save_stencil_ref(rctx->blitter, &rctx->stencil_ref);
+        util_blitter_save_rasterizer(rctx->blitter, rctx->queued.named.rasterizer);
+        util_blitter_save_fragment_shader(rctx->blitter, rctx->ps_shader);
+        util_blitter_save_vertex_shader(rctx->blitter, rctx->vs_shader);
+        util_blitter_save_vertex_elements(rctx->blitter, rctx->vertex_elements);
+        if (rctx->queued.named.viewport) {
+                util_blitter_save_viewport(rctx->blitter, &rctx->queued.named.viewport->viewport);
+        }
+        util_blitter_save_vertex_buffer_slot(rctx->blitter, rctx->vertex_buffer);
+        util_blitter_save_so_targets(rctx->blitter, rctx->num_so_targets,
+                                     (struct pipe_stream_output_target**)rctx->so_targets);
+        if (op & R600_SAVE_FRAMEBUFFER)
+                util_blitter_save_framebuffer(rctx->blitter, &rctx->framebuffer);
+        if (op & R600_SAVE_TEXTURES) {
+                util_blitter_save_fragment_sampler_states(
+                        rctx->blitter, rctx->ps_samplers.n_samplers,
+                        (void**)rctx->ps_samplers.samplers);
+                util_blitter_save_fragment_sampler_views(
+                        rctx->blitter, rctx->ps_samplers.n_views,
+                        (struct pipe_sampler_view**)rctx->ps_samplers.views);
+        }
+        if ((op & R600_DISABLE_RENDER_COND) && rctx->current_render_cond) {
+                rctx->saved_render_cond = rctx->current_render_cond;
+                rctx->saved_render_cond_cond = rctx->current_render_cond_cond;
+                rctx->saved_render_cond_mode = rctx->current_render_cond_mode;
+                rctx->context.render_condition(&rctx->context, NULL, FALSE, 0);
+        }
+}
+static void r600_blitter_end(struct pipe_context *ctx)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        if (rctx->saved_render_cond) {
+                rctx->context.render_condition(&rctx->context,
+                                               rctx->saved_render_cond,
+                                               rctx->saved_render_cond_cond,
+                                               rctx->saved_render_cond_mode);
+                rctx->saved_render_cond = NULL;
+        }
+        r600_context_queries_resume(rctx);
+}
+void si_blit_uncompress_depth(struct pipe_context *ctx,
+                struct r600_resource_texture *texture,
+                struct r600_resource_texture *staging,
+                unsigned first_level, unsigned last_level,
+                unsigned first_layer, unsigned last_layer)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        unsigned layer, level, checked_last_layer, max_layer;
+        float depth = 1.0f;
+        const struct util_format_description *desc;
+        void *custom_dsa;
+        struct r600_resource_texture *flushed_depth_texture = staging ?
+                        staging : texture->flushed_depth_texture;
+        if (!staging && !texture->dirty_db_mask)
+                return;
+        desc = util_format_description(flushed_depth_texture->resource.b.b.format);
+        switch (util_format_has_depth(desc) | util_format_has_stencil(desc) << 1) {
+        default:
+                assert(!"No depth or stencil to uncompress");
+        case 3:
+                custom_dsa = rctx->custom_dsa_flush_depth_stencil;
+                break;
+        case 2:
+                custom_dsa = rctx->custom_dsa_flush_stencil;
+                break;
+        case 1:
+                custom_dsa = rctx->custom_dsa_flush_depth;
+                break;
+        }
+        for (level = first_level; level <= last_level; level++) {
+                if (!staging && !(texture->dirty_db_mask & (1 << level)))
+                        continue;
+                /* The smaller the mipmap level, the less layers there are
+                 * as far as 3D textures are concerned. */
+                max_layer = util_max_layer(&texture->resource.b.b, level);
+                checked_last_layer = last_layer < max_layer ? last_layer : max_layer;
+                for (layer = first_layer; layer <= checked_last_layer; layer++) {
+                        struct pipe_surface *zsurf, *cbsurf, surf_tmpl;
+                        surf_tmpl.format = texture->real_format;
+                        surf_tmpl.u.tex.level = level;
+                        surf_tmpl.u.tex.first_layer = layer;
+                        surf_tmpl.u.tex.last_layer = layer;
+                        zsurf = ctx->create_surface(ctx, &texture->resource.b.b, &surf_tmpl);
+                        surf_tmpl.format = flushed_depth_texture->real_format;
+                        cbsurf = ctx->create_surface(ctx,
+                                        (struct pipe_resource*)flushed_depth_texture, &surf_tmpl);
+                        r600_blitter_begin(ctx, R600_DECOMPRESS);
+                        util_blitter_custom_depth_stencil(rctx->blitter, zsurf, cbsurf, ~0, custom_dsa, depth);
+                        r600_blitter_end(ctx);
+                        pipe_surface_reference(&zsurf, NULL);
+                        pipe_surface_reference(&cbsurf, NULL);
+                }
+                /* The texture will always be dirty if some layers aren't flushed.
+                 * I don't think this case can occur though. */
+                if (!staging && first_layer == 0 && last_layer == max_layer) {
+                        texture->dirty_db_mask &= ~(1 << level);
+                }
+        }
+}
+static void si_blit_decompress_depth_in_place(struct r600_context *rctx,
+                                              struct r600_resource_texture *texture,
+                                              unsigned first_level, unsigned last_level,
+                                              unsigned first_layer, unsigned last_layer)
+{
+        struct pipe_surface *zsurf, surf_tmpl = {{0}};
+        unsigned layer, max_layer, checked_last_layer, level;
+        surf_tmpl.format = texture->resource.b.b.format;
+        for (level = first_level; level <= last_level; level++) {
+                if (!(texture->dirty_db_mask & (1 << level)))
+                        continue;
+                surf_tmpl.u.tex.level = level;
+                /* The smaller the mipmap level, the less layers there are
+                 * as far as 3D textures are concerned. */
+                max_layer = util_max_layer(&texture->resource.b.b, level);
+                checked_last_layer = last_layer < max_layer ? last_layer : max_layer;
+                for (layer = first_layer; layer <= checked_last_layer; layer++) {
+                        surf_tmpl.u.tex.first_layer = layer;
+                        surf_tmpl.u.tex.last_layer = layer;
+                        zsurf = rctx->context.create_surface(&rctx->context, &texture->resource.b.b, &surf_tmpl);
+                        r600_blitter_begin(&rctx->context, R600_DECOMPRESS);
+                        util_blitter_custom_depth_stencil(rctx->blitter, zsurf, NULL, ~0,
+                                                          rctx->custom_dsa_flush_inplace,
+.0f);
+                        r600_blitter_end(&rctx->context);
+                        pipe_surface_reference(&zsurf, NULL);
+                }
+                /* The texture will always be dirty if some layers aren't flushed.
+                 * I don't think this case occurs often though. */
+                if (first_layer == 0 && last_layer == max_layer) {
+                        texture->dirty_db_mask &= ~(1 << level);
+                }
+        }
+}
+void si_flush_depth_textures(struct r600_context *rctx,
+                             struct r600_textures_info *textures)
+{
+        unsigned i;
+        for (i = 0; i < textures->n_views; ++i) {
+                struct pipe_sampler_view *view;
+                struct r600_resource_texture *tex;
+                view = &textures->views[i]->base;
+                if (!view) continue;
+                tex = (struct r600_resource_texture *)view->texture;
+                if (!tex->is_depth || tex->is_flushing_texture)
+                        continue;
+                si_blit_decompress_depth_in_place(rctx, tex,
+                                                  view->u.tex.first_level, view->u.tex.last_level,
+, util_max_layer(&tex->resource.b.b, view->u.tex.first_level));
+        }
+}
+static void r600_clear(struct pipe_context *ctx, unsigned buffers,
+                       const union pipe_color_union *color,
+                       double depth, unsigned stencil)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct pipe_framebuffer_state *fb = &rctx->framebuffer;
+        r600_blitter_begin(ctx, R600_CLEAR);
+        util_blitter_clear(rctx->blitter, fb->width, fb->height,
+                           buffers, color, depth, stencil);
+        r600_blitter_end(ctx);
+}
+static void r600_clear_render_target(struct pipe_context *ctx,
+                                     struct pipe_surface *dst,
+                                     const union pipe_color_union *color,
+                                     unsigned dstx, unsigned dsty,
+                                     unsigned width, unsigned height)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        r600_blitter_begin(ctx, R600_CLEAR_SURFACE);
+        util_blitter_clear_render_target(rctx->blitter, dst, color,
+                                         dstx, dsty, width, height);
+        r600_blitter_end(ctx);
+}
+static void r600_clear_depth_stencil(struct pipe_context *ctx,
+                                     struct pipe_surface *dst,
+                                     unsigned clear_flags,
+                                     double depth,
+                                     unsigned stencil,
+                                     unsigned dstx, unsigned dsty,
+                                     unsigned width, unsigned height)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        r600_blitter_begin(ctx, R600_CLEAR_SURFACE);
+        util_blitter_clear_depth_stencil(rctx->blitter, dst, clear_flags, depth, stencil,
+                                         dstx, dsty, width, height);
+        r600_blitter_end(ctx);
+}
+struct texture_orig_info {
+        unsigned format;
+        unsigned width0;
+        unsigned height0;
+        unsigned npix_x;
+        unsigned npix_y;
+        unsigned npix0_x;
+        unsigned npix0_y;
+};
+static void r600_compressed_to_blittable(struct pipe_resource *tex,
+                                   unsigned level,
+                                   struct texture_orig_info *orig)
+{
+        struct r600_resource_texture *rtex = (struct r600_resource_texture*)tex;
+        unsigned pixsize = util_format_get_blocksize(rtex->real_format);
+        int new_format;
+        int new_height, new_width;
+        orig->format = tex->format;
+        orig->width0 = tex->width0;
+        orig->height0 = tex->height0;
+        orig->npix0_x = rtex->surface.level[0].npix_x;
+        orig->npix0_y = rtex->surface.level[0].npix_y;
+        orig->npix_x = rtex->surface.level[level].npix_x;
+        orig->npix_y = rtex->surface.level[level].npix_y;
+        if (pixsize == 8)
+                new_format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
+        else
+                new_format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
+        new_width = util_format_get_nblocksx(tex->format, orig->width0);
+        new_height = util_format_get_nblocksy(tex->format, orig->height0);
+        tex->width0 = new_width;
+        tex->height0 = new_height;
+        tex->format = new_format;
+        rtex->surface.level[0].npix_x = util_format_get_nblocksx(orig->format, orig->npix0_x);
+        rtex->surface.level[0].npix_y = util_format_get_nblocksy(orig->format, orig->npix0_y);
+        rtex->surface.level[level].npix_x = util_format_get_nblocksx(orig->format, orig->npix_x);
+        rtex->surface.level[level].npix_y = util_format_get_nblocksy(orig->format, orig->npix_y);
+}
+static void r600_change_format(struct pipe_resource *tex,
+                               unsigned level,
+                               struct texture_orig_info *orig,
+                               enum pipe_format format)
+{
+        struct r600_resource_texture *rtex = (struct r600_resource_texture*)tex;
+        orig->format = tex->format;
+        orig->width0 = tex->width0;
+        orig->height0 = tex->height0;
+        orig->npix0_x = rtex->surface.level[0].npix_x;
+        orig->npix0_y = rtex->surface.level[0].npix_y;
+        orig->npix_x = rtex->surface.level[level].npix_x;
+        orig->npix_y = rtex->surface.level[level].npix_y;
+        tex->format = format;
+}
+static void r600_reset_blittable_to_orig(struct pipe_resource *tex,
+                                         unsigned level,
+                                         struct texture_orig_info *orig)
+{
+        struct r600_resource_texture *rtex = (struct r600_resource_texture*)tex;
+        tex->format = orig->format;
+        tex->width0 = orig->width0;
+        tex->height0 = orig->height0;
+        rtex->surface.level[0].npix_x = orig->npix0_x;
+        rtex->surface.level[0].npix_y = orig->npix0_y;
+        rtex->surface.level[level].npix_x = orig->npix_x;
+        rtex->surface.level[level].npix_y = orig->npix_y;
+}
+static void r600_resource_copy_region(struct pipe_context *ctx,
+                                      struct pipe_resource *dst,
+                                      unsigned dst_level,
+                                      unsigned dstx, unsigned dsty, unsigned dstz,
+                                      struct pipe_resource *src,
+                                      unsigned src_level,
+                                      const struct pipe_box *src_box)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct r600_resource_texture *rsrc = (struct r600_resource_texture*)src;
+        struct texture_orig_info orig_info[2];
+        struct pipe_box sbox;
+        const struct pipe_box *psbox = src_box;
+        boolean restore_orig[2];
+        memset(orig_info, 0, sizeof(orig_info));
+        /* Fallback for buffers. */
+        if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
+                util_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
+                                          src, src_level, src_box);
+                return;
+        }
+        /* This must be done before entering u_blitter to avoid recursion. */
+        if (rsrc->is_depth && !rsrc->is_flushing_texture) {
+                si_blit_decompress_depth_in_place(rctx, rsrc,
+                                                  src_level, src_level,
+                                                  src_box->z, src_box->z + src_box->depth - 1);
+        }
+        restore_orig[0] = restore_orig[1] = FALSE;
+        if (util_format_is_compressed(src->format) &&
+            util_format_is_compressed(dst->format)) {
+                r600_compressed_to_blittable(src, src_level, &orig_info[0]);
+                restore_orig[0] = TRUE;
+                sbox.x = util_format_get_nblocksx(orig_info[0].format, src_box->x);
+                sbox.y = util_format_get_nblocksy(orig_info[0].format, src_box->y);
+                sbox.z = src_box->z;
+                sbox.width = util_format_get_nblocksx(orig_info[0].format, src_box->width);
+                sbox.height = util_format_get_nblocksy(orig_info[0].format, src_box->height);
+                sbox.depth = src_box->depth;
+                psbox=&sbox;
+                r600_compressed_to_blittable(dst, dst_level, &orig_info[1]);
+                restore_orig[1] = TRUE;
+                /* translate the dst box as well */
+                dstx = util_format_get_nblocksx(orig_info[1].format, dstx);
+                dsty = util_format_get_nblocksy(orig_info[1].format, dsty);
+        } else if (!util_blitter_is_copy_supported(rctx->blitter, dst, src,
+                                                   PIPE_MASK_RGBAZS)) {
+                unsigned blocksize = util_format_get_blocksize(src->format);
+                switch (blocksize) {
+                case 1:
+                        r600_change_format(src, src_level, &orig_info[0],
+                                           PIPE_FORMAT_R8_UNORM);
+                        r600_change_format(dst, dst_level, &orig_info[1],
+                                           PIPE_FORMAT_R8_UNORM);
+                        break;
+                case 2:
+                        r600_change_format(src, src_level, &orig_info[0],
+                                           PIPE_FORMAT_R8G8_UNORM);
+                        r600_change_format(dst, dst_level, &orig_info[1],
+                                           PIPE_FORMAT_R8G8_UNORM);
+                        break;
+                case 4:
+                        r600_change_format(src, src_level, &orig_info[0],
+                                           PIPE_FORMAT_R8G8B8A8_UNORM);
+                        r600_change_format(dst, dst_level, &orig_info[1],
+                                           PIPE_FORMAT_R8G8B8A8_UNORM);
+                        break;
+                case 8:
+                        r600_change_format(src, src_level, &orig_info[0],
+                                           PIPE_FORMAT_R16G16B16A16_UINT);
+                        r600_change_format(dst, dst_level, &orig_info[1],
+                                           PIPE_FORMAT_R16G16B16A16_UINT);
+                        break;
+                case 16:
+                        r600_change_format(src, src_level, &orig_info[0],
+                                           PIPE_FORMAT_R32G32B32A32_UINT);
+                        r600_change_format(dst, dst_level, &orig_info[1],
+                                           PIPE_FORMAT_R32G32B32A32_UINT);
+                        break;
+                default:
+                        fprintf(stderr, "Unhandled format %s with blocksize %u\n",
+                                util_format_short_name(src->format), blocksize);
+                        assert(0);
+                }
+                restore_orig[0] = TRUE;
+                restore_orig[1] = TRUE;
+        }
+        r600_blitter_begin(ctx, R600_COPY);
+        util_blitter_copy_texture(rctx->blitter, dst, dst_level, dstx, dsty, dstz,
+                                  src, src_level, psbox, PIPE_MASK_RGBAZS, TRUE);
+        r600_blitter_end(ctx);
+        if (restore_orig[0])
+                r600_reset_blittable_to_orig(src, src_level, &orig_info[0]);
+        if (restore_orig[1])
+                r600_reset_blittable_to_orig(dst, dst_level, &orig_info[1]);
+}
+static void si_blit(struct pipe_context *ctx,
+                      const struct pipe_blit_info *info)
+{
+        struct r600_context *rctx = (struct r600_context*)ctx;
+        struct r600_resource_texture *rsrc = (struct r600_resource_texture*)info->src.resource;
+        assert(util_blitter_is_blit_supported(rctx->blitter, info));
+        if (info->src.resource->nr_samples > 1 &&
+            info->dst.resource->nr_samples <= 1 &&
+            !util_format_is_depth_or_stencil(info->src.resource->format) &&
+            !util_format_is_pure_integer(info->src.resource->format)) {
+                debug_printf("radeonsi: color resolve is unimplemented\n");
+                return;
+        }
+        if (rsrc->is_depth && !rsrc->is_flushing_texture) {
+                si_blit_decompress_depth_in_place(rctx, rsrc,
+                                                  info->src.level, info->src.level,
+                                                  info->src.box.z,
+                                                  info->src.box.z + info->src.box.depth - 1);
+        }
+        r600_blitter_begin(ctx, R600_BLIT);
+        util_blitter_blit(rctx->blitter, info);
+        r600_blitter_end(ctx);
+}
+void si_init_blit_functions(struct r600_context *rctx)
+{
+        rctx->context.clear = r600_clear;
+        rctx->context.clear_render_target = r600_clear_render_target;
+        rctx->context.clear_depth_stencil = r600_clear_depth_stencil;
+        rctx->context.resource_copy_region = r600_resource_copy_region;
+        rctx->context.blit = si_blit;
+}

 /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/r600_buffer.c
 ,0 → 1,197
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ *      Corbin Simpson <MostAwesomeDude@gmail.com>
+ */
+#include "pipe/p_screen.h"
+#include "util/u_format.h"
+#include "util/u_math.h"
+#include "util/u_inlines.h"
+#include "util/u_memory.h"
+#include "util/u_upload_mgr.h"
+#include "r600.h"
+#include "radeonsi_pipe.h"
+static void r600_buffer_destroy(struct pipe_screen *screen,
+                                struct pipe_resource *buf)
+{
+        struct si_resource *rbuffer = si_resource(buf);
+        pb_reference(&rbuffer->buf, NULL);
+        FREE(rbuffer);
+}
+static void *r600_buffer_transfer_map(struct pipe_context *ctx,
+                                      struct pipe_resource *resource,
+                                      unsigned level,
+                                      unsigned usage,
+                                      const struct pipe_box *box,
+                                      struct pipe_transfer **ptransfer)
+{
+        struct r600_context *rctx = (struct r600_context*)ctx;
+        struct pipe_transfer *transfer;
+        struct si_resource *rbuffer = si_resource(resource);
+        uint8_t *data;
+        data = rctx->ws->buffer_map(rbuffer->cs_buf, rctx->cs, usage);
+        if (!data) {
+                return NULL;
+        }
+        transfer = util_slab_alloc(&rctx->pool_transfers);
+        transfer->resource = resource;
+        transfer->level = level;
+        transfer->usage = usage;
+        transfer->box = *box;
+        transfer->stride = 0;
+        transfer->layer_stride = 0;
+        *ptransfer = transfer;
+        return (uint8_t*)data + transfer->box.x;
+}
+static void r600_buffer_transfer_unmap(struct pipe_context *ctx,
+                                        struct pipe_transfer *transfer)
+{
+        struct r600_context *rctx = (struct r600_context*)ctx;
+        util_slab_free(&rctx->pool_transfers, transfer);
+}
+static void r600_buffer_transfer_flush_region(struct pipe_context *pipe,
+                                                struct pipe_transfer *transfer,
+                                                const struct pipe_box *box)
+{
+}
+static const struct u_resource_vtbl r600_buffer_vtbl =
+{
+        u_default_resource_get_handle,          /* get_handle */
+        r600_buffer_destroy,                    /* resource_destroy */
+        r600_buffer_transfer_map,               /* transfer_map */
+        r600_buffer_transfer_flush_region,      /* transfer_flush_region */
+        r600_buffer_transfer_unmap,             /* transfer_unmap */
+        NULL    /* transfer_inline_write */
+};
+bool si_init_resource(struct r600_screen *rscreen,
+                        struct si_resource *res,
+                        unsigned size, unsigned alignment,
+                        boolean use_reusable_pool, unsigned usage)
+{
+        uint32_t initial_domain, domains;
+        /* Staging resources particpate in transfers and blits only
+         * and are used for uploads and downloads from regular
+         * resources.  We generate them internally for some transfers.
+         */
+        if (usage == PIPE_USAGE_STAGING) {
+                domains = RADEON_DOMAIN_GTT;
+                initial_domain = RADEON_DOMAIN_GTT;
+        } else {
+                domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
+                switch(usage) {
+                case PIPE_USAGE_DYNAMIC:
+                case PIPE_USAGE_STREAM:
+                case PIPE_USAGE_STAGING:
+                        initial_domain = RADEON_DOMAIN_GTT;
+                        break;
+                case PIPE_USAGE_DEFAULT:
+                case PIPE_USAGE_STATIC:
+                case PIPE_USAGE_IMMUTABLE:
+                default:
+                        initial_domain = RADEON_DOMAIN_VRAM;
+                        break;
+                }
+        }
+        res->buf = rscreen->ws->buffer_create(rscreen->ws, size, alignment,
+                                              use_reusable_pool,
+                                              initial_domain);
+        if (!res->buf) {
+                return false;
+        }
+        res->cs_buf = rscreen->ws->buffer_get_cs_handle(res->buf);
+        res->domains = domains;
+        return true;
+}
+struct pipe_resource *si_buffer_create(struct pipe_screen *screen,
+                                       const struct pipe_resource *templ)
+{
+        struct r600_screen *rscreen = (struct r600_screen*)screen;
+        struct si_resource *rbuffer;
+        /* XXX We probably want a different alignment for buffers and textures. */
+        unsigned alignment = 4096;
+        rbuffer = MALLOC_STRUCT(si_resource);
+        rbuffer->b.b = *templ;
+        pipe_reference_init(&rbuffer->b.b.reference, 1);
+        rbuffer->b.b.screen = screen;
+        rbuffer->b.vtbl = &r600_buffer_vtbl;
+        if (!si_init_resource(rscreen, rbuffer, templ->width0, alignment, TRUE, templ->usage)) {
+                FREE(rbuffer);
+                return NULL;
+        }
+        return &rbuffer->b.b;
+}
+void r600_upload_index_buffer(struct r600_context *rctx,
+                              struct pipe_index_buffer *ib, unsigned count)
+{
+        u_upload_data(rctx->uploader, 0, count * ib->index_size,
+                      ib->user_buffer, &ib->offset, &ib->buffer);
+}
+void r600_upload_const_buffer(struct r600_context *rctx, struct si_resource **rbuffer,
+                        const uint8_t *ptr, unsigned size,
+                        uint32_t *const_offset)
+{
+        if (R600_BIG_ENDIAN) {
+                uint32_t *tmpPtr;
+                unsigned i;
+                if (!(tmpPtr = malloc(size))) {
+                        R600_ERR("Failed to allocate BE swap buffer.\n");
+                        return;
+                }
+                for (i = 0; i < size / 4; ++i) {
+                        tmpPtr[i] = util_bswap32(((uint32_t *)ptr)[i]);
+                }
+                u_upload_data(rctx->uploader, 0, size, tmpPtr, const_offset,
+                                (struct pipe_resource**)rbuffer);
+                free(tmpPtr);
+        } else {
+                u_upload_data(rctx->uploader, 0, size, ptr, const_offset,
+                                        (struct pipe_resource**)rbuffer);
+        }
+}

 /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/r600_hw_context.c
 ,0 → 1,729
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#include "r600_hw_context_priv.h"
+#include "radeonsi_pm4.h"
+#include "radeonsi_pipe.h"
+#include "sid.h"
+#include "util/u_memory.h"
+#include <errno.h>
+#define GROUP_FORCE_NEW_BLOCK   0
+/* Get backends mask */
+void si_get_backend_mask(struct r600_context *ctx)
+{
+        struct radeon_winsys_cs *cs = ctx->cs;
+        struct si_resource *buffer;
+        uint32_t *results;
+        unsigned num_backends = ctx->screen->info.r600_num_backends;
+        unsigned i, mask = 0;
+        /* if backend_map query is supported by the kernel */
+        if (ctx->screen->info.r600_backend_map_valid) {
+                unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes;
+                unsigned backend_map = ctx->screen->info.r600_backend_map;
+                unsigned item_width = 4, item_mask = 0x7;
+                while(num_tile_pipes--) {
+                        i = backend_map & item_mask;
+                        mask |= (1<<i);
+                        backend_map >>= item_width;
+                }
+                if (mask != 0) {
+                        ctx->backend_mask = mask;
+                        return;
+                }
+        }
+        /* otherwise backup path for older kernels */
+        /* create buffer for event data */
+        buffer = si_resource_create_custom(&ctx->screen->screen,
+                                           PIPE_USAGE_STAGING,
+                                           ctx->max_db*16);
+        if (!buffer)
+                goto err;
+        /* initialize buffer with zeroes */
+        results = ctx->ws->buffer_map(buffer->cs_buf, ctx->cs, PIPE_TRANSFER_WRITE);
+        if (results) {
+                uint64_t va = 0;
+                memset(results, 0, ctx->max_db * 4 * 4);
+                ctx->ws->buffer_unmap(buffer->cs_buf);
+                /* emit EVENT_WRITE for ZPASS_DONE */
+                va = r600_resource_va(&ctx->screen->screen, (void *)buffer);
+                cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
+                cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
+                cs->buf[cs->cdw++] = va;
+                cs->buf[cs->cdw++] = va >> 32;
+                cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
+                cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, buffer, RADEON_USAGE_WRITE);
+                /* analyze results */
+                results = ctx->ws->buffer_map(buffer->cs_buf, ctx->cs, PIPE_TRANSFER_READ);
+                if (results) {
+                        for(i = 0; i < ctx->max_db; i++) {
+                                /* at least highest bit will be set if backend is used */
+                                if (results[i*4 + 1])
+                                        mask |= (1<<i);
+                        }
+                        ctx->ws->buffer_unmap(buffer->cs_buf);
+                }
+        }
+        si_resource_reference(&buffer, NULL);
+        if (mask != 0) {
+                ctx->backend_mask = mask;
+                return;
+        }
+err:
+        /* fallback to old method - set num_backends lower bits to 1 */
+        ctx->backend_mask = (~((uint32_t)0))>>(32-num_backends);
+        return;
+}
+/* initialize */
+void si_need_cs_space(struct r600_context *ctx, unsigned num_dw,
+                        boolean count_draw_in)
+{
+        /* The number of dwords we already used in the CS so far. */
+        num_dw += ctx->cs->cdw;
+        if (count_draw_in) {
+                /* The number of dwords all the dirty states would take. */
+                num_dw += ctx->pm4_dirty_cdwords;
+                /* The upper-bound of how much a draw command would take. */
+                num_dw += SI_MAX_DRAW_CS_DWORDS;
+        }
+        /* Count in queries_suspend. */
+        num_dw += ctx->num_cs_dw_queries_suspend;
+        /* Count in streamout_end at the end of CS. */
+        num_dw += ctx->num_cs_dw_streamout_end;
+        /* Count in render_condition(NULL) at the end of CS. */
+        if (ctx->predicate_drawing) {
+                num_dw += 3;
+        }
+        /* Count in framebuffer cache flushes at the end of CS. */
+        num_dw += 7; /* one SURFACE_SYNC and CACHE_FLUSH_AND_INV (r6xx-only) */
+        /* Save 16 dwords for the fence mechanism. */
+        num_dw += 16;
+#if R600_TRACE_CS
+        if (ctx->screen->trace_bo) {
+                num_dw += R600_TRACE_CS_DWORDS;
+        }
+#endif
+        /* Flush if there's not enough space. */
+        if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
+                radeonsi_flush(&ctx->context, NULL, RADEON_FLUSH_ASYNC);
+        }
+}
+static void r600_flush_framebuffer(struct r600_context *ctx)
+{
+        struct si_pm4_state *pm4;
+        if (!(ctx->flags & R600_CONTEXT_DST_CACHES_DIRTY))
+                return;
+        pm4 = si_pm4_alloc_state(ctx);
+        if (pm4 == NULL)
+                return;
+        si_cmd_surface_sync(pm4, S_0085F0_CB0_DEST_BASE_ENA(1) |
+                                S_0085F0_CB1_DEST_BASE_ENA(1) |
+                                S_0085F0_CB2_DEST_BASE_ENA(1) |
+                                S_0085F0_CB3_DEST_BASE_ENA(1) |
+                                S_0085F0_CB4_DEST_BASE_ENA(1) |
+                                S_0085F0_CB5_DEST_BASE_ENA(1) |
+                                S_0085F0_CB6_DEST_BASE_ENA(1) |
+                                S_0085F0_CB7_DEST_BASE_ENA(1) |
+                                S_0085F0_DB_ACTION_ENA(1) |
+                                S_0085F0_DB_DEST_BASE_ENA(1));
+        si_pm4_emit(ctx, pm4);
+        si_pm4_free_state(ctx, pm4, ~0);
+        ctx->flags &= ~R600_CONTEXT_DST_CACHES_DIRTY;
+}
+void si_context_flush(struct r600_context *ctx, unsigned flags)
+{
+        struct radeon_winsys_cs *cs = ctx->cs;
+        bool queries_suspended = false;
+#if 0
+        bool streamout_suspended = false;
+#endif
+        if (!cs->cdw)
+                return;
+        /* suspend queries */
+        if (ctx->num_cs_dw_queries_suspend) {
+                r600_context_queries_suspend(ctx);
+                queries_suspended = true;
+        }
+#if 0
+        if (ctx->num_cs_dw_streamout_end) {
+                r600_context_streamout_end(ctx);
+                streamout_suspended = true;
+        }
+#endif
+        r600_flush_framebuffer(ctx);
+        /* partial flush is needed to avoid lockups on some chips with user fences */
+        cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
+        cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
+        /* force to keep tiling flags */
+        flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
+#if R600_TRACE_CS
+        if (ctx->screen->trace_bo) {
+                struct r600_screen *rscreen = ctx->screen;
+                unsigned i;
+                for (i = 0; i < cs->cdw; i++) {
+                        fprintf(stderr, "[%4d] [%5d] 0x%08x\n", rscreen->cs_count, i, cs->buf[i]);
+                }
+                rscreen->cs_count++;
+        }
+#endif
+        /* Flush the CS. */
+        ctx->ws->cs_flush(ctx->cs, flags, 0);
+#if R600_TRACE_CS
+        if (ctx->screen->trace_bo) {
+                struct r600_screen *rscreen = ctx->screen;
+                unsigned i;
+                for (i = 0; i < 10; i++) {
+                        usleep(5);
+                        if (!ctx->ws->buffer_is_busy(rscreen->trace_bo->buf, RADEON_USAGE_READWRITE)) {
+                                break;
+                        }
+                }
+                if (i == 10) {
+                        fprintf(stderr, "timeout on cs lockup likely happen at cs %d dw %d\n",
+                                rscreen->trace_ptr[1], rscreen->trace_ptr[0]);
+                } else {
+                        fprintf(stderr, "cs %d executed in %dms\n", rscreen->trace_ptr[1], i * 5);
+                }
+        }
+#endif
+        ctx->pm4_dirty_cdwords = 0;
+        ctx->flags = 0;
+#if 0
+        if (streamout_suspended) {
+                ctx->streamout_start = TRUE;
+                ctx->streamout_append_bitmask = ~0;
+        }
+#endif
+        /* resume queries */
+        if (queries_suspended) {
+                r600_context_queries_resume(ctx);
+        }
+        /* set all valid group as dirty so they get reemited on
+         * next draw command
+         */
+        si_pm4_reset_emitted(ctx);
+}
+void si_context_emit_fence(struct r600_context *ctx, struct si_resource *fence_bo, unsigned offset, unsigned value)
+{
+        struct radeon_winsys_cs *cs = ctx->cs;
+        uint64_t va;
+        si_need_cs_space(ctx, 10, FALSE);
+        va = r600_resource_va(&ctx->screen->screen, (void*)fence_bo);
+        va = va + (offset << 2);
+        cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
+        cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
+        cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
+        cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
+        cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL;       /* ADDRESS_LO */
+        /* DATA_SEL | INT_EN | ADDRESS_HI */
+        cs->buf[cs->cdw++] = (1 << 29) | (0 << 24) | ((va >> 32UL) & 0xFF);
+        cs->buf[cs->cdw++] = value;                   /* DATA_LO */
+        cs->buf[cs->cdw++] = 0;                       /* DATA_HI */
+        cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
+        cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, fence_bo, RADEON_USAGE_WRITE);
+}
+static unsigned r600_query_read_result(char *map, unsigned start_index, unsigned end_index,
+                                       bool test_status_bit)
+{
+        uint32_t *current_result = (uint32_t*)map;
+        uint64_t start, end;
+        start = (uint64_t)current_result[start_index] |
+                (uint64_t)current_result[start_index+1] << 32;
+        end = (uint64_t)current_result[end_index] |
+              (uint64_t)current_result[end_index+1] << 32;
+        if (!test_status_bit ||
+            ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))) {
+                return end - start;
+        }
+        return 0;
+}
+static boolean r600_query_result(struct r600_context *ctx, struct r600_query *query, boolean wait)
+{
+        unsigned results_base = query->results_start;
+        char *map;
+        map = ctx->ws->buffer_map(query->buffer->cs_buf, ctx->cs,
+                                  PIPE_TRANSFER_READ |
+                                  (wait ? 0 : PIPE_TRANSFER_DONTBLOCK));
+        if (!map)
+                return FALSE;
+        /* count all results across all data blocks */
+        switch (query->type) {
+        case PIPE_QUERY_OCCLUSION_COUNTER:
+                while (results_base != query->results_end) {
+                        query->result.u64 +=
+                                r600_query_read_result(map + results_base, 0, 2, true);
+                        results_base = (results_base + 16) % query->buffer->b.b.width0;
+                }
+                break;
+        case PIPE_QUERY_OCCLUSION_PREDICATE:
+                while (results_base != query->results_end) {
+                        query->result.b = query->result.b ||
+                                r600_query_read_result(map + results_base, 0, 2, true) != 0;
+                        results_base = (results_base + 16) % query->buffer->b.b.width0;
+                }
+                break;
+        case PIPE_QUERY_TIME_ELAPSED:
+                while (results_base != query->results_end) {
+                        query->result.u64 +=
+                                r600_query_read_result(map + results_base, 0, 2, false);
+                        results_base = (results_base + query->result_size) % query->buffer->b.b.width0;
+                }
+                break;
+        case PIPE_QUERY_PRIMITIVES_EMITTED:
+                /* SAMPLE_STREAMOUTSTATS stores this structure:
+                 * {
+                 *    u64 NumPrimitivesWritten;
+                 *    u64 PrimitiveStorageNeeded;
+                 * }
+                 * We only need NumPrimitivesWritten here. */
+                while (results_base != query->results_end) {
+                        query->result.u64 +=
+                                r600_query_read_result(map + results_base, 2, 6, true);
+                        results_base = (results_base + query->result_size) % query->buffer->b.b.width0;
+                }
+                break;
+        case PIPE_QUERY_PRIMITIVES_GENERATED:
+                /* Here we read PrimitiveStorageNeeded. */
+                while (results_base != query->results_end) {
+                        query->result.u64 +=
+                                r600_query_read_result(map + results_base, 0, 4, true);
+                        results_base = (results_base + query->result_size) % query->buffer->b.b.width0;
+                }
+                break;
+        case PIPE_QUERY_SO_STATISTICS:
+                while (results_base != query->results_end) {
+                        query->result.so.num_primitives_written +=
+                                r600_query_read_result(map + results_base, 2, 6, true);
+                        query->result.so.primitives_storage_needed +=
+                                r600_query_read_result(map + results_base, 0, 4, true);
+                        results_base = (results_base + query->result_size) % query->buffer->b.b.width0;
+                }
+                break;
+        case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
+                while (results_base != query->results_end) {
+                        query->result.b = query->result.b ||
+                                r600_query_read_result(map + results_base, 2, 6, true) !=
+                                r600_query_read_result(map + results_base, 0, 4, true);
+                        results_base = (results_base + query->result_size) % query->buffer->b.b.width0;
+                }
+                break;
+        default:
+                assert(0);
+        }
+        query->results_start = query->results_end;
+        ctx->ws->buffer_unmap(query->buffer->cs_buf);
+        return TRUE;
+}
+void r600_query_begin(struct r600_context *ctx, struct r600_query *query)
+{
+        struct radeon_winsys_cs *cs = ctx->cs;
+        unsigned new_results_end, i;
+        uint32_t *results;
+        uint64_t va;
+        si_need_cs_space(ctx, query->num_cs_dw * 2, TRUE);
+        new_results_end = (query->results_end + query->result_size) % query->buffer->b.b.width0;
+        /* collect current results if query buffer is full */
+        if (new_results_end == query->results_start) {
+                r600_query_result(ctx, query, TRUE);
+        }
+        switch (query->type) {
+        case PIPE_QUERY_OCCLUSION_COUNTER:
+        case PIPE_QUERY_OCCLUSION_PREDICATE:
+                results = ctx->ws->buffer_map(query->buffer->cs_buf, ctx->cs, PIPE_TRANSFER_WRITE);
+                if (results) {
+                        results = (uint32_t*)((char*)results + query->results_end);
+                        memset(results, 0, query->result_size);
+                        /* Set top bits for unused backends */
+                        for (i = 0; i < ctx->max_db; i++) {
+                                if (!(ctx->backend_mask & (1<<i))) {
+                                        results[(i * 4)+1] = 0x80000000;
+                                        results[(i * 4)+3] = 0x80000000;
+                                }
+                        }
+                        ctx->ws->buffer_unmap(query->buffer->cs_buf);
+                }
+                break;
+        case PIPE_QUERY_TIME_ELAPSED:
+                break;
+        case PIPE_QUERY_PRIMITIVES_EMITTED:
+        case PIPE_QUERY_PRIMITIVES_GENERATED:
+        case PIPE_QUERY_SO_STATISTICS:
+        case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
+                results = ctx->ws->buffer_map(query->buffer->cs_buf, ctx->cs, PIPE_TRANSFER_WRITE);
+                results = (uint32_t*)((char*)results + query->results_end);
+                memset(results, 0, query->result_size);
+                ctx->ws->buffer_unmap(query->buffer->cs_buf);
+                break;
+        default:
+                assert(0);
+        }
+        /* emit begin query */
+        va = r600_resource_va(&ctx->screen->screen, (void*)query->buffer);
+        va += query->results_end;
+        switch (query->type) {
+        case PIPE_QUERY_OCCLUSION_COUNTER:
+        case PIPE_QUERY_OCCLUSION_PREDICATE:
+                cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
+                cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
+                cs->buf[cs->cdw++] = va;
+                cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
+                break;
+        case PIPE_QUERY_PRIMITIVES_EMITTED:
+        case PIPE_QUERY_PRIMITIVES_GENERATED:
+        case PIPE_QUERY_SO_STATISTICS:
+        case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
+                cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
+                cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SAMPLE_STREAMOUTSTATS) | EVENT_INDEX(3);
+                cs->buf[cs->cdw++] = query->results_end;
+                cs->buf[cs->cdw++] = 0;
+                break;
+        case PIPE_QUERY_TIME_ELAPSED:
+                cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
+                cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
+                cs->buf[cs->cdw++] = va;
+                cs->buf[cs->cdw++] = (3 << 29) | ((va >> 32UL) & 0xFF);
+                cs->buf[cs->cdw++] = 0;
+                cs->buf[cs->cdw++] = 0;
+                break;
+        default:
+                assert(0);
+        }
+        cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
+        cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, query->buffer, RADEON_USAGE_WRITE);
+        ctx->num_cs_dw_queries_suspend += query->num_cs_dw;
+}
+void r600_query_end(struct r600_context *ctx, struct r600_query *query)
+{
+        struct radeon_winsys_cs *cs = ctx->cs;
+        uint64_t va;
+        va = r600_resource_va(&ctx->screen->screen, (void*)query->buffer);
+        /* emit end query */
+        switch (query->type) {
+        case PIPE_QUERY_OCCLUSION_COUNTER:
+        case PIPE_QUERY_OCCLUSION_PREDICATE:
+                va += query->results_end + 8;
+                cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
+                cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
+                cs->buf[cs->cdw++] = va;
+                cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
+                break;
+        case PIPE_QUERY_PRIMITIVES_EMITTED:
+        case PIPE_QUERY_PRIMITIVES_GENERATED:
+        case PIPE_QUERY_SO_STATISTICS:
+        case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
+                cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
+                cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SAMPLE_STREAMOUTSTATS) | EVENT_INDEX(3);
+                cs->buf[cs->cdw++] = query->results_end + query->result_size/2;
+                cs->buf[cs->cdw++] = 0;
+                break;
+        case PIPE_QUERY_TIME_ELAPSED:
+                va += query->results_end + query->result_size/2;
+                cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
+                cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
+                cs->buf[cs->cdw++] = va;
+                cs->buf[cs->cdw++] = (3 << 29) | ((va >> 32UL) & 0xFF);
+                cs->buf[cs->cdw++] = 0;
+                cs->buf[cs->cdw++] = 0;
+                break;
+        default:
+                assert(0);
+        }
+        cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
+        cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, query->buffer, RADEON_USAGE_WRITE);
+        query->results_end = (query->results_end + query->result_size) % query->buffer->b.b.width0;
+        ctx->num_cs_dw_queries_suspend -= query->num_cs_dw;
+}
+void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation,
+                            int flag_wait)
+{
+        struct radeon_winsys_cs *cs = ctx->cs;
+        uint64_t va;
+        if (operation == PREDICATION_OP_CLEAR) {
+                si_need_cs_space(ctx, 3, FALSE);
+                cs->buf[cs->cdw++] = PKT3(PKT3_SET_PREDICATION, 1, 0);
+                cs->buf[cs->cdw++] = 0;
+                cs->buf[cs->cdw++] = PRED_OP(PREDICATION_OP_CLEAR);
+        } else {
+                unsigned results_base = query->results_start;
+                unsigned count;
+                uint32_t op;
+                /* find count of the query data blocks */
+                count = (query->buffer->b.b.width0 + query->results_end - query->results_start) % query->buffer->b.b.width0;
+                count /= query->result_size;
+                si_need_cs_space(ctx, 5 * count, TRUE);
+                op = PRED_OP(operation) | PREDICATION_DRAW_VISIBLE |
+                                (flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW);
+                va = r600_resource_va(&ctx->screen->screen, (void*)query->buffer);
+                /* emit predicate packets for all data blocks */
+                while (results_base != query->results_end) {
+                        cs->buf[cs->cdw++] = PKT3(PKT3_SET_PREDICATION, 1, 0);
+                        cs->buf[cs->cdw++] = (va + results_base) & 0xFFFFFFFFUL;
+                        cs->buf[cs->cdw++] = op | (((va + results_base) >> 32UL) & 0xFF);
+                        cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
+                        cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, query->buffer,
+                                                                             RADEON_USAGE_READ);
+                        results_base = (results_base + query->result_size) % query->buffer->b.b.width0;
+                        /* set CONTINUE bit for all packets except the first */
+                        op |= PREDICATION_CONTINUE;
+                }
+        }
+}
+struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type)
+{
+        struct r600_query *query;
+        unsigned buffer_size = 4096;
+        query = CALLOC_STRUCT(r600_query);
+        if (query == NULL)
+                return NULL;
+        query->type = query_type;
+        switch (query_type) {
+        case PIPE_QUERY_OCCLUSION_COUNTER:
+        case PIPE_QUERY_OCCLUSION_PREDICATE:
+                query->result_size = 16 * ctx->max_db;
+                query->num_cs_dw = 6;
+                break;
+        case PIPE_QUERY_TIME_ELAPSED:
+                query->result_size = 16;
+                query->num_cs_dw = 8;
+                break;
+        case PIPE_QUERY_PRIMITIVES_EMITTED:
+        case PIPE_QUERY_PRIMITIVES_GENERATED:
+        case PIPE_QUERY_SO_STATISTICS:
+        case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
+                /* NumPrimitivesWritten, PrimitiveStorageNeeded. */
+                query->result_size = 32;
+                query->num_cs_dw = 6;
+                break;
+        default:
+                assert(0);
+                FREE(query);
+                return NULL;
+        }
+        /* adjust buffer size to simplify offsets wrapping math */
+        buffer_size -= buffer_size % query->result_size;
+        /* Queries are normally read by the CPU after
+         * being written by the gpu, hence staging is probably a good
+         * usage pattern.
+         */
+        query->buffer = si_resource_create_custom(&ctx->screen->screen,
+                                                  PIPE_USAGE_STAGING,
+                                                  buffer_size);
+        if (!query->buffer) {
+                FREE(query);
+                return NULL;
+        }
+        return query;
+}
+void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query)
+{
+        si_resource_reference(&query->buffer, NULL);
+        free(query);
+}
+boolean r600_context_query_result(struct r600_context *ctx,
+                                struct r600_query *query,
+                                boolean wait, void *vresult)
+{
+        boolean *result_b = (boolean*)vresult;
+        uint64_t *result_u64 = (uint64_t*)vresult;
+        struct pipe_query_data_so_statistics *result_so =
+                (struct pipe_query_data_so_statistics*)vresult;
+        if (!r600_query_result(ctx, query, wait))
+                return FALSE;
+        switch (query->type) {
+        case PIPE_QUERY_OCCLUSION_COUNTER:
+        case PIPE_QUERY_PRIMITIVES_EMITTED:
+        case PIPE_QUERY_PRIMITIVES_GENERATED:
+                *result_u64 = query->result.u64;
+                break;
+        case PIPE_QUERY_OCCLUSION_PREDICATE:
+        case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
+                *result_b = query->result.b;
+                break;
+        case PIPE_QUERY_TIME_ELAPSED:
+                *result_u64 = (1000000 * query->result.u64) / ctx->screen->info.r600_clock_crystal_freq;
+                break;
+        case PIPE_QUERY_SO_STATISTICS:
+                *result_so = query->result.so;
+                break;
+        default:
+                assert(0);
+        }
+        return TRUE;
+}
+void r600_context_queries_suspend(struct r600_context *ctx)
+{
+        struct r600_query *query;
+        LIST_FOR_EACH_ENTRY(query, &ctx->active_query_list, list) {
+                r600_query_end(ctx, query);
+        }
+        assert(ctx->num_cs_dw_queries_suspend == 0);
+}
+void r600_context_queries_resume(struct r600_context *ctx)
+{
+        struct r600_query *query;
+        assert(ctx->num_cs_dw_queries_suspend == 0);
+        LIST_FOR_EACH_ENTRY(query, &ctx->active_query_list, list) {
+                r600_query_begin(ctx, query);
+        }
+}
+void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_target *t)
+{
+        struct radeon_winsys_cs *cs = ctx->cs;
+        si_need_cs_space(ctx, 14 + 21, TRUE);
+        cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
+        cs->buf[cs->cdw++] = (R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET - SI_CONTEXT_REG_OFFSET) >> 2;
+        cs->buf[cs->cdw++] = 0;
+        cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
+        cs->buf[cs->cdw++] = (R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE - SI_CONTEXT_REG_OFFSET) >> 2;
+        cs->buf[cs->cdw++] = t->stride >> 2;
+#if 0
+        cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
+        cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
+        cs->buf[cs->cdw++] = 0; /* src address lo */
+        cs->buf[cs->cdw++] = 0; /* src address hi */
+        cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
+        cs->buf[cs->cdw++] = 0; /* unused */
+#endif
+        cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
+        cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, t->filled_size, RADEON_USAGE_READ);
+}
+#if R600_TRACE_CS
+void r600_trace_emit(struct r600_context *rctx)
+{
+        struct r600_screen *rscreen = rctx->screen;
+        struct radeon_winsys_cs *cs = rctx->cs;
+        uint64_t va;
+        va = r600_resource_va(&rscreen->screen, (void*)rscreen->trace_bo);
+        r600_context_bo_reloc(rctx, rscreen->trace_bo, RADEON_USAGE_READWRITE);
+        cs->buf[cs->cdw++] = PKT3(PKT3_WRITE_DATA, 4, 0);
+        cs->buf[cs->cdw++] = PKT3_WRITE_DATA_DST_SEL(PKT3_WRITE_DATA_DST_SEL_MEM_SYNC) |
+                                PKT3_WRITE_DATA_WR_CONFIRM |
+                                PKT3_WRITE_DATA_ENGINE_SEL(PKT3_WRITE_DATA_ENGINE_SEL_ME);
+        cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL;
+        cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFFFFFFFUL;
+        cs->buf[cs->cdw++] = cs->cdw;
+        cs->buf[cs->cdw++] = rscreen->cs_count;
+}
+#endif

 /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/r600_hw_context_priv.h
 ,0 → 1,45
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#ifndef R600_PRIV_H
+#define R600_PRIV_H
+#include "radeonsi_pipe.h"
+#include "util/u_hash_table.h"
+#include "os/os_thread.h"
+#define SI_MAX_DRAW_CS_DWORDS 18
+#define PKT_COUNT_C                     0xC000FFFF
+#define PKT_COUNT_S(x)                  (((x) & 0x3FFF) << 16)
+static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct si_resource *rbo,
+                                             enum radeon_bo_usage usage)
+{
+        assert(usage);
+        return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4;
+}
+#endif

 /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/r600_query.c
 ,0 → 1,132
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include "radeonsi_pipe.h"
+#include "sid.h"
+static struct pipe_query *r600_create_query(struct pipe_context *ctx, unsigned query_type)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        return (struct pipe_query*)r600_context_query_create(rctx, query_type);
+}
+static void r600_destroy_query(struct pipe_context *ctx, struct pipe_query *query)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        r600_context_query_destroy(rctx, (struct r600_query *)query);
+}
+static void r600_begin_query(struct pipe_context *ctx, struct pipe_query *query)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct r600_query *rquery = (struct r600_query *)query;
+        memset(&rquery->result, 0, sizeof(rquery->result));
+        rquery->results_start = rquery->results_end;
+        r600_query_begin(rctx, (struct r600_query *)query);
+        LIST_ADDTAIL(&rquery->list, &rctx->active_query_list);
+}
+static void r600_end_query(struct pipe_context *ctx, struct pipe_query *query)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct r600_query *rquery = (struct r600_query *)query;
+        r600_query_end(rctx, rquery);
+        LIST_DELINIT(&rquery->list);
+}
+static boolean r600_get_query_result(struct pipe_context *ctx,
+                                        struct pipe_query *query,
+                                        boolean wait, union pipe_query_result *vresult)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct r600_query *rquery = (struct r600_query *)query;
+        return r600_context_query_result(rctx, rquery, wait, vresult);
+}
+static void r600_render_condition(struct pipe_context *ctx,
+                                  struct pipe_query *query,
+                                  boolean condition,
+                                  uint mode)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct r600_query *rquery = (struct r600_query *)query;
+        int wait_flag = 0;
+        /* If we already have nonzero result, render unconditionally */
+        if (query != NULL && rquery->result.u64 != 0) {
+                if (rctx->current_render_cond) {
+                        r600_render_condition(ctx, NULL, FALSE, 0);
+                }
+                return;
+        }
+        rctx->current_render_cond = query;
+        rctx->current_render_cond_cond = condition;
+        rctx->current_render_cond_mode = mode;
+        if (query == NULL) {
+                if (rctx->predicate_drawing) {
+                        rctx->predicate_drawing = false;
+                        r600_query_predication(rctx, NULL, PREDICATION_OP_CLEAR, 1);
+                }
+                return;
+        }
+        if (mode == PIPE_RENDER_COND_WAIT ||
+            mode == PIPE_RENDER_COND_BY_REGION_WAIT) {
+                wait_flag = 1;
+        }
+        rctx->predicate_drawing = true;
+        switch (rquery->type) {
+        case PIPE_QUERY_OCCLUSION_COUNTER:
+        case PIPE_QUERY_OCCLUSION_PREDICATE:
+                r600_query_predication(rctx, rquery, PREDICATION_OP_ZPASS, wait_flag);
+                break;
+        case PIPE_QUERY_PRIMITIVES_EMITTED:
+        case PIPE_QUERY_PRIMITIVES_GENERATED:
+        case PIPE_QUERY_SO_STATISTICS:
+        case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
+                r600_query_predication(rctx, rquery, PREDICATION_OP_PRIMCOUNT, wait_flag);
+                break;
+        default:
+                assert(0);
+        }
+}
+void r600_init_query_functions(struct r600_context *rctx)
+{
+        rctx->context.create_query = r600_create_query;
+        rctx->context.destroy_query = r600_destroy_query;
+        rctx->context.begin_query = r600_begin_query;
+        rctx->context.end_query = r600_end_query;
+        rctx->context.get_query_result = r600_get_query_result;
+        if (rctx->screen->info.r600_num_backends > 0)
+            rctx->context.render_condition = r600_render_condition;
+}

 /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/r600_resource.c
 ,0 → 1,61
+/*
+ * Copyright 2010 Marek Olšák <maraeo@gmail.com
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include "radeonsi_pipe.h"
+static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
+                                                const struct pipe_resource *templ)
+{
+        if (templ->target == PIPE_BUFFER) {
+                return si_buffer_create(screen, templ);
+        } else {
+                return si_texture_create(screen, templ);
+        }
+}
+static struct pipe_resource *r600_resource_from_handle(struct pipe_screen * screen,
+                                                        const struct pipe_resource *templ,
+                                                        struct winsys_handle *whandle)
+{
+        if (templ->target == PIPE_BUFFER) {
+                return NULL;
+        } else {
+                return si_texture_from_handle(screen, templ, whandle);
+        }
+}
+void r600_init_screen_resource_functions(struct pipe_screen *screen)
+{
+        screen->resource_create = r600_resource_create;
+        screen->resource_from_handle = r600_resource_from_handle;
+        screen->resource_get_handle = u_resource_get_handle_vtbl;
+        screen->resource_destroy = u_resource_destroy_vtbl;
+}
+void r600_init_context_resource_functions(struct r600_context *r600)
+{
+        r600->context.transfer_map = u_transfer_map_vtbl;
+        r600->context.transfer_flush_region = u_transfer_flush_region_vtbl;
+        r600->context.transfer_unmap = u_transfer_unmap_vtbl;
+        r600->context.transfer_inline_write = u_default_transfer_inline_write;
+}

 /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/r600_resource.h
 ,0 → 1,82
+/*
+ * Copyright 2010 Marek Olšák <maraeo@gmail.com
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef R600_RESOURCE_H
+#define R600_RESOURCE_H
+#include "util/u_transfer.h"
+/* flag to indicate a resource is to be used as a transfer so should not be tiled */
+#define R600_RESOURCE_FLAG_TRANSFER             PIPE_RESOURCE_FLAG_DRV_PRIV
+#define R600_RESOURCE_FLAG_FLUSHED_DEPTH        (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
+/* Texture transfer. */
+struct r600_transfer {
+        /* Base class. */
+        struct pipe_transfer            transfer;
+        /* Buffer transfer. */
+        struct pipe_transfer            *buffer_transfer;
+        unsigned                        offset;
+        struct pipe_resource            *staging;
+};
+struct r600_resource_texture {
+        struct si_resource              resource;
+        /* If this resource is a depth-stencil buffer on evergreen, this contains
+         * the depth part of the format. There is a separate stencil resource
+         * for the stencil buffer below. */
+        enum pipe_format                real_format;
+        unsigned                        pitch_override;
+        unsigned                        is_depth;
+        unsigned                        dirty_db_mask; /* each bit says if that miplevel is dirty */
+        struct r600_resource_texture    *flushed_depth_texture;
+        boolean                         is_flushing_texture;
+        struct radeon_surface           surface;
+};
+struct r600_surface {
+        struct pipe_surface             base;
+};
+void r600_init_screen_resource_functions(struct pipe_screen *screen);
+/* r600_texture */
+struct pipe_resource *si_texture_create(struct pipe_screen *screen,
+                                        const struct pipe_resource *templ);
+struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen,
+                                             const struct pipe_resource *base,
+                                             struct winsys_handle *whandle);
+bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
+                                     struct pipe_resource *texture,
+                                     struct r600_resource_texture **staging);
+struct r600_context;
+void r600_upload_const_buffer(struct r600_context *rctx, struct si_resource **rbuffer,
+                              const uint8_t *ptr, unsigned size,
+                              uint32_t *const_offset);
+#endif

 /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/r600_texture.c
 ,0 → 1,678
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ *      Corbin Simpson
+ */
+#include <errno.h>
+#include "pipe/p_screen.h"
+#include "util/u_format.h"
+#include "util/u_format_s3tc.h"
+#include "util/u_math.h"
+#include "util/u_inlines.h"
+#include "util/u_memory.h"
+#include "pipebuffer/pb_buffer.h"
+#include "radeonsi_pipe.h"
+#include "r600_resource.h"
+#include "sid.h"
+/* Copy from a full GPU texture to a transfer's staging one. */
+static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
+{
+        struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
+        struct pipe_resource *texture = transfer->resource;
+        ctx->resource_copy_region(ctx, rtransfer->staging,
+, 0, 0, 0, texture, transfer->level,
+                                &transfer->box);
+}
+/* Copy from a transfer's staging texture to a full GPU one. */
+static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
+{
+        struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
+        struct pipe_resource *texture = transfer->resource;
+        struct pipe_box sbox;
+        u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
+        ctx->resource_copy_region(ctx, texture, transfer->level,
+                                  transfer->box.x, transfer->box.y, transfer->box.z,
+                                  rtransfer->staging,
+, &sbox);
+}
+static unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
+                                        unsigned level, unsigned layer)
+{
+        return rtex->surface.level[level].offset +
+               layer * rtex->surface.level[level].slice_size;
+}
+static int r600_init_surface(struct r600_screen *rscreen,
+                             struct radeon_surface *surface,
+                             const struct pipe_resource *ptex,
+                             unsigned array_mode,
+                             bool is_flushed_depth)
+{
+        const struct util_format_description *desc =
+                util_format_description(ptex->format);
+        bool is_depth, is_stencil;
+        is_depth = util_format_has_depth(desc);
+        is_stencil = util_format_has_stencil(desc);
+        surface->npix_x = ptex->width0;
+        surface->npix_y = ptex->height0;
+        surface->npix_z = ptex->depth0;
+        surface->blk_w = util_format_get_blockwidth(ptex->format);
+        surface->blk_h = util_format_get_blockheight(ptex->format);
+        surface->blk_d = 1;
+        surface->array_size = 1;
+        surface->last_level = ptex->last_level;
+        if (!is_flushed_depth &&
+            ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
+                surface->bpe = 4; /* stencil is allocated separately on evergreen */
+        } else {
+                surface->bpe = util_format_get_blocksize(ptex->format);
+                /* align byte per element on dword */
+                if (surface->bpe == 3) {
+                        surface->bpe = 4;
+                }
+        }
+        surface->nsamples = 1;
+        surface->flags = 0;
+        switch (array_mode) {
+        case V_009910_ARRAY_1D_TILED_THIN1:
+                surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
+                break;
+        case V_009910_ARRAY_2D_TILED_THIN1:
+                surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
+                break;
+        case V_009910_ARRAY_LINEAR_ALIGNED:
+                surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
+                break;
+        case V_009910_ARRAY_LINEAR_GENERAL:
+        default:
+                surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
+                break;
+        }
+        switch (ptex->target) {
+        case PIPE_TEXTURE_1D:
+                surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
+                break;
+        case PIPE_TEXTURE_RECT:
+        case PIPE_TEXTURE_2D:
+                surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
+                break;
+        case PIPE_TEXTURE_3D:
+                surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
+                break;
+        case PIPE_TEXTURE_1D_ARRAY:
+                surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
+                surface->array_size = ptex->array_size;
+                break;
+        case PIPE_TEXTURE_2D_ARRAY:
+                surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
+                surface->array_size = ptex->array_size;
+                break;
+        case PIPE_TEXTURE_CUBE:
+                surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
+                break;
+        case PIPE_BUFFER:
+        default:
+                return -EINVAL;
+        }
+        if (ptex->bind & PIPE_BIND_SCANOUT) {
+                surface->flags |= RADEON_SURF_SCANOUT;
+        }
+        if (!is_flushed_depth && is_depth) {
+                surface->flags |= RADEON_SURF_ZBUFFER;
+                if (is_stencil) {
+                        surface->flags |= RADEON_SURF_SBUFFER |
+                                RADEON_SURF_HAS_SBUFFER_MIPTREE;
+                }
+        }
+        surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
+        return 0;
+}
+static int r600_setup_surface(struct pipe_screen *screen,
+                              struct r600_resource_texture *rtex,
+                              unsigned array_mode,
+                              unsigned pitch_in_bytes_override)
+{
+        struct r600_screen *rscreen = (struct r600_screen*)screen;
+        int r;
+        r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
+        if (r) {
+                return r;
+        }
+        if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
+                /* old ddx on evergreen over estimate alignment for 1d, only 1 level
+                 * for those
+                 */
+                rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
+                rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
+                rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
+                if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
+                        rtex->surface.stencil_offset =
+                        rtex->surface.stencil_level[0].offset = rtex->surface.level[0].slice_size;
+                }
+        }
+        return 0;
+}
+static boolean r600_texture_get_handle(struct pipe_screen* screen,
+                                        struct pipe_resource *ptex,
+                                        struct winsys_handle *whandle)
+{
+        struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
+        struct si_resource *resource = &rtex->resource;
+        struct radeon_surface *surface = &rtex->surface;
+        struct r600_screen *rscreen = (struct r600_screen*)screen;
+        rscreen->ws->buffer_set_tiling(resource->buf,
+                                       NULL,
+                                       surface->level[0].mode >= RADEON_SURF_MODE_1D ?
+                                       RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
+                                       surface->level[0].mode >= RADEON_SURF_MODE_2D ?
+                                       RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
+                                       surface->bankw, surface->bankh,
+                                       surface->tile_split,
+                                       surface->stencil_tile_split,
+                                       surface->mtilea,
+                                       surface->level[0].pitch_bytes);
+        return rscreen->ws->buffer_get_handle(resource->buf,
+                                              surface->level[0].pitch_bytes, whandle);
+}
+static void r600_texture_destroy(struct pipe_screen *screen,
+                                 struct pipe_resource *ptex)
+{
+        struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
+        struct si_resource *resource = &rtex->resource;
+        if (rtex->flushed_depth_texture)
+                si_resource_reference((struct si_resource **)&rtex->flushed_depth_texture, NULL);
+        pb_reference(&resource->buf, NULL);
+        FREE(rtex);
+}
+static void *si_texture_transfer_map(struct pipe_context *ctx,
+                                     struct pipe_resource *texture,
+                                     unsigned level,
+                                     unsigned usage,
+                                     const struct pipe_box *box,
+                                     struct pipe_transfer **ptransfer)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
+        struct r600_transfer *trans;
+        boolean use_staging_texture = FALSE;
+        struct radeon_winsys_cs_handle *buf;
+        enum pipe_format format = texture->format;
+        unsigned offset = 0;
+        char *map;
+        /* We cannot map a tiled texture directly because the data is
+         * in a different order, therefore we do detiling using a blit.
+         *
+         * Also, use a temporary in GTT memory for read transfers, as
+         * the CPU is much happier reading out of cached system memory
+         * than uncached VRAM.
+         */
+        if (rtex->surface.level[level].mode != RADEON_SURF_MODE_LINEAR_ALIGNED &&
+            rtex->surface.level[level].mode != RADEON_SURF_MODE_LINEAR)
+                use_staging_texture = TRUE;
+        /* XXX: Use a staging texture for uploads if the underlying BO
+         * is busy.  No interface for checking that currently? so do
+         * it eagerly whenever the transfer doesn't require a readback
+         * and might block.
+         */
+        if ((usage & PIPE_TRANSFER_WRITE) &&
+                        !(usage & (PIPE_TRANSFER_READ |
+                                        PIPE_TRANSFER_DONTBLOCK |
+                                        PIPE_TRANSFER_UNSYNCHRONIZED)))
+                use_staging_texture = TRUE;
+        if (texture->flags & R600_RESOURCE_FLAG_TRANSFER)
+                use_staging_texture = FALSE;
+        if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY))
+                return NULL;
+        trans = CALLOC_STRUCT(r600_transfer);
+        if (trans == NULL)
+                return NULL;
+        pipe_resource_reference(&trans->transfer.resource, texture);
+        trans->transfer.level = level;
+        trans->transfer.usage = usage;
+        trans->transfer.box = *box;
+        if (rtex->is_depth) {
+                /* XXX: only readback the rectangle which is being mapped?
+                */
+                /* XXX: when discard is true, no need to read back from depth texture
+                */
+                struct r600_resource_texture *staging_depth;
+                if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
+                        R600_ERR("failed to create temporary texture to hold untiled copy\n");
+                        pipe_resource_reference(&trans->transfer.resource, NULL);
+                        FREE(trans);
+                        return NULL;
+                }
+                si_blit_uncompress_depth(ctx, rtex, staging_depth,
+                                         level, level,
+                                         box->z, box->z + box->depth - 1);
+                trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
+                trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
+                trans->offset = r600_texture_get_offset(staging_depth, level, box->z);
+                trans->staging = &staging_depth->resource.b.b;
+        } else if (use_staging_texture) {
+                struct pipe_resource resource;
+                struct r600_resource_texture *staging;
+                memset(&resource, 0, sizeof(resource));
+                resource.format = texture->format;
+                resource.width0 = box->width;
+                resource.height0 = box->height;
+                resource.depth0 = 1;
+                resource.array_size = 1;
+                resource.usage = PIPE_USAGE_STAGING;
+                resource.flags = R600_RESOURCE_FLAG_TRANSFER;
+                /* We must set the correct texture target and dimensions if needed for a 3D transfer. */
+                if (box->depth > 1 && util_max_layer(texture, level) > 0)
+                        resource.target = texture->target;
+                else
+                        resource.target = PIPE_TEXTURE_2D;
+                switch (resource.target) {
+                case PIPE_TEXTURE_1D_ARRAY:
+                case PIPE_TEXTURE_2D_ARRAY:
+                case PIPE_TEXTURE_CUBE_ARRAY:
+                        resource.array_size = box->depth;
+                        break;
+                case PIPE_TEXTURE_3D:
+                        resource.depth0 = box->depth;
+                        break;
+                default:;
+                }
+                /* Create the temporary texture. */
+                staging = (struct r600_resource_texture*)ctx->screen->resource_create(ctx->screen, &resource);
+                if (staging == NULL) {
+                        R600_ERR("failed to create temporary texture to hold untiled copy\n");
+                        pipe_resource_reference(&trans->transfer.resource, NULL);
+                        FREE(trans);
+                        return NULL;
+                }
+                trans->staging = &staging->resource.b.b;
+                trans->transfer.stride = staging->surface.level[0].pitch_bytes;
+                trans->transfer.layer_stride = staging->surface.level[0].slice_size;
+                if (usage & PIPE_TRANSFER_READ) {
+                        r600_copy_to_staging_texture(ctx, trans);
+                        /* Always referenced in the blit. */
+                        radeonsi_flush(ctx, NULL, 0);
+                }
+        } else {
+                trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
+                trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
+                trans->offset = r600_texture_get_offset(rtex, level, box->z);
+        }
+        if (trans->staging) {
+                buf = si_resource(trans->staging)->cs_buf;
+        } else {
+                buf = rtex->resource.cs_buf;
+        }
+        if (rtex->is_depth || !trans->staging)
+                offset = trans->offset +
+                        box->y / util_format_get_blockheight(format) * trans->transfer.stride +
+                        box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
+        if (!(map = rctx->ws->buffer_map(buf, rctx->cs, usage))) {
+                pipe_resource_reference(&trans->staging, NULL);
+                pipe_resource_reference(&trans->transfer.resource, NULL);
+                FREE(trans);
+                return NULL;
+        }
+        *ptransfer = &trans->transfer;
+        return map + offset;
+}
+static void si_texture_transfer_unmap(struct pipe_context *ctx,
+                                      struct pipe_transfer* transfer)
+{
+        struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
+        struct r600_context *rctx = (struct r600_context*)ctx;
+        struct radeon_winsys_cs_handle *buf;
+        struct pipe_resource *texture = transfer->resource;
+        struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
+        if (rtransfer->staging) {
+                buf = si_resource(rtransfer->staging)->cs_buf;
+        } else {
+                buf = si_resource(transfer->resource)->cs_buf;
+        }
+        rctx->ws->buffer_unmap(buf);
+        if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
+                if (rtex->is_depth) {
+                        ctx->resource_copy_region(ctx, texture, transfer->level,
+                                                  transfer->box.x, transfer->box.y, transfer->box.z,
+                                                  &si_resource(rtransfer->staging)->b.b, transfer->level,
+                                                  &transfer->box);
+                } else {
+                        r600_copy_from_staging_texture(ctx, rtransfer);
+                }
+        }
+        if (rtransfer->staging)
+                pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL);
+        pipe_resource_reference(&transfer->resource, NULL);
+        FREE(transfer);
+}
+static const struct u_resource_vtbl r600_texture_vtbl =
+{
+        r600_texture_get_handle,        /* get_handle */
+        r600_texture_destroy,           /* resource_destroy */
+        si_texture_transfer_map,        /* transfer_map */
+        u_default_transfer_flush_region,/* transfer_flush_region */
+        si_texture_transfer_unmap,      /* transfer_unmap */
+        NULL    /* transfer_inline_write */
+};
+DEBUG_GET_ONCE_BOOL_OPTION(print_texdepth, "RADEON_PRINT_TEXDEPTH", FALSE);
+static struct r600_resource_texture *
+r600_texture_create_object(struct pipe_screen *screen,
+                           const struct pipe_resource *base,
+                           unsigned array_mode,
+                           unsigned pitch_in_bytes_override,
+                           unsigned max_buffer_size,
+                           struct pb_buffer *buf,
+                           boolean alloc_bo,
+                           struct radeon_surface *surface)
+{
+        struct r600_resource_texture *rtex;
+        struct si_resource *resource;
+        struct r600_screen *rscreen = (struct r600_screen*)screen;
+        int r;
+        rtex = CALLOC_STRUCT(r600_resource_texture);
+        if (rtex == NULL)
+                return NULL;
+        resource = &rtex->resource;
+        resource->b.b = *base;
+        resource->b.vtbl = &r600_texture_vtbl;
+        pipe_reference_init(&resource->b.b.reference, 1);
+        resource->b.b.screen = screen;
+        rtex->pitch_override = pitch_in_bytes_override;
+        rtex->real_format = base->format;
+        /* don't include stencil-only formats which we don't support for rendering */
+        rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
+        rtex->surface = *surface;
+        r = r600_setup_surface(screen, rtex, array_mode, pitch_in_bytes_override);
+        if (r) {
+                FREE(rtex);
+                return NULL;
+        }
+        /* Now create the backing buffer. */
+        if (!buf && alloc_bo) {
+                unsigned base_align = rtex->surface.bo_alignment;
+                unsigned size = rtex->surface.bo_size;
+                base_align = rtex->surface.bo_alignment;
+                if (!si_init_resource(rscreen, resource, size, base_align, FALSE, base->usage)) {
+                        FREE(rtex);
+                        return NULL;
+                }
+        } else if (buf) {
+                resource->buf = buf;
+                resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
+                resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
+        }
+        if (debug_get_option_print_texdepth() && rtex->is_depth) {
+                printf("Texture: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
+                       "blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
+                       "bpe=%u, nsamples=%u, flags=%u\n",
+                       rtex->surface.npix_x, rtex->surface.npix_y,
+                       rtex->surface.npix_z, rtex->surface.blk_w,
+                       rtex->surface.blk_h, rtex->surface.blk_d,
+                       rtex->surface.array_size, rtex->surface.last_level,
+                       rtex->surface.bpe, rtex->surface.nsamples,
+                       rtex->surface.flags);
+                if (rtex->surface.flags & RADEON_SURF_ZBUFFER) {
+                        for (int i = 0; i <= rtex->surface.last_level; i++) {
+                                printf("  Z %i: offset=%llu, slice_size=%llu, npix_x=%u, "
+                                       "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
+                                       "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
+                                       i, rtex->surface.level[i].offset,
+                                       rtex->surface.level[i].slice_size,
+                                       rtex->surface.level[i].npix_x,
+                                       rtex->surface.level[i].npix_y,
+                                       rtex->surface.level[i].npix_z,
+                                       rtex->surface.level[i].nblk_x,
+                                       rtex->surface.level[i].nblk_y,
+                                       rtex->surface.level[i].nblk_z,
+                                       rtex->surface.level[i].pitch_bytes,
+                                       rtex->surface.level[i].mode);
+                        }
+                }
+                if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
+                        for (int i = 0; i <= rtex->surface.last_level; i++) {
+                                printf("  S %i: offset=%llu, slice_size=%llu, npix_x=%u, "
+                                       "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
+                                       "nblk_z=%u, pitch_bytes=%u, mode=%u\n",
+                                       i, rtex->surface.stencil_level[i].offset,
+                                       rtex->surface.stencil_level[i].slice_size,
+                                       rtex->surface.stencil_level[i].npix_x,
+                                       rtex->surface.stencil_level[i].npix_y,
+                                       rtex->surface.stencil_level[i].npix_z,
+                                       rtex->surface.stencil_level[i].nblk_x,
+                                       rtex->surface.stencil_level[i].nblk_y,
+                                       rtex->surface.stencil_level[i].nblk_z,
+                                       rtex->surface.stencil_level[i].pitch_bytes,
+                                       rtex->surface.stencil_level[i].mode);
+                        }
+                }
+        }
+        return rtex;
+}
+struct pipe_resource *si_texture_create(struct pipe_screen *screen,
+                                        const struct pipe_resource *templ)
+{
+        struct r600_screen *rscreen = (struct r600_screen*)screen;
+        struct radeon_surface surface;
+        unsigned array_mode = V_009910_ARRAY_LINEAR_ALIGNED;
+        int r;
+        if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
+            !(templ->bind & PIPE_BIND_SCANOUT)) {
+                if (util_format_is_compressed(templ->format)) {
+                        array_mode = V_009910_ARRAY_1D_TILED_THIN1;
+                } else {
+                        if (rscreen->chip_class >= CIK)
+                                array_mode = V_009910_ARRAY_1D_TILED_THIN1; /* XXX fix me */
+                        else
+                                array_mode = V_009910_ARRAY_2D_TILED_THIN1;
+                }
+        }
+        r = r600_init_surface(rscreen, &surface, templ, array_mode,
+                              templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
+        if (r) {
+                return NULL;
+        }
+        r = rscreen->ws->surface_best(rscreen->ws, &surface);
+        if (r) {
+                return NULL;
+        }
+        return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
+, 0, NULL, TRUE, &surface);
+}
+static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
+                                                struct pipe_resource *texture,
+                                                const struct pipe_surface *surf_tmpl)
+{
+        struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
+        struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
+        unsigned level = surf_tmpl->u.tex.level;
+        assert(surf_tmpl->u.tex.first_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));
+        assert(surf_tmpl->u.tex.last_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));
+        assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
+        if (surface == NULL)
+                return NULL;
+        /* XXX no offset */
+/*      offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
+        pipe_reference_init(&surface->base.reference, 1);
+        pipe_resource_reference(&surface->base.texture, texture);
+        surface->base.context = pipe;
+        surface->base.format = surf_tmpl->format;
+        surface->base.width = rtex->surface.level[level].npix_x;
+        surface->base.height = rtex->surface.level[level].npix_y;
+        surface->base.texture = texture;
+        surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
+        surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
+        surface->base.u.tex.level = level;
+        return &surface->base;
+}
+static void r600_surface_destroy(struct pipe_context *pipe,
+                                 struct pipe_surface *surface)
+{
+        pipe_resource_reference(&surface->texture, NULL);
+        FREE(surface);
+}
+struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen,
+                                             const struct pipe_resource *templ,
+                                             struct winsys_handle *whandle)
+{
+        struct r600_screen *rscreen = (struct r600_screen*)screen;
+        struct pb_buffer *buf = NULL;
+        unsigned stride = 0;
+        unsigned array_mode = V_009910_ARRAY_LINEAR_ALIGNED;
+        enum radeon_bo_layout micro, macro;
+        struct radeon_surface surface;
+        int r;
+        /* Support only 2D textures without mipmaps */
+        if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
+              templ->depth0 != 1 || templ->last_level != 0)
+                return NULL;
+        buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
+        if (!buf)
+                return NULL;
+        rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
+                                       &surface.bankw, &surface.bankh,
+                                       &surface.tile_split,
+                                       &surface.stencil_tile_split,
+                                       &surface.mtilea);
+        if (macro == RADEON_LAYOUT_TILED)
+                array_mode = V_009910_ARRAY_2D_TILED_THIN1;
+        else if (micro == RADEON_LAYOUT_TILED)
+                array_mode = V_009910_ARRAY_1D_TILED_THIN1;
+        else
+                array_mode = V_009910_ARRAY_LINEAR_ALIGNED;
+        r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
+        if (r) {
+                return NULL;
+        }
+        /* always set the scanout flags */
+        surface.flags |= RADEON_SURF_SCANOUT;
+        return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
+                                                                  stride, 0, buf, FALSE, &surface);
+}
+bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
+                                     struct pipe_resource *texture,
+                                     struct r600_resource_texture **staging)
+{
+        struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
+        struct pipe_resource resource;
+        struct r600_resource_texture **flushed_depth_texture = staging ?
+                        staging : &rtex->flushed_depth_texture;
+        if (!staging && rtex->flushed_depth_texture)
+                return true; /* it's ready */
+        resource.target = texture->target;
+        resource.format = texture->format;
+        resource.width0 = texture->width0;
+        resource.height0 = texture->height0;
+        resource.depth0 = texture->depth0;
+        resource.array_size = texture->array_size;
+        resource.last_level = texture->last_level;
+        resource.nr_samples = texture->nr_samples;
+        resource.usage = staging ? PIPE_USAGE_DYNAMIC : PIPE_USAGE_DEFAULT;
+        resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
+        resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
+        if (staging)
+                resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
+        else
+                rtex->dirty_db_mask = (1 << (resource.last_level+1)) - 1;
+        *flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
+        if (*flushed_depth_texture == NULL) {
+                R600_ERR("failed to create temporary texture to hold flushed depth\n");
+                return false;
+        }
+        (*flushed_depth_texture)->is_flushing_texture = TRUE;
+        return true;
+}
+void si_init_surface_functions(struct r600_context *r600)
+{
+        r600->context.create_surface = r600_create_surface;
+        r600->context.surface_destroy = r600_surface_destroy;
+}

 /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/r600_translate.c
 ,0 → 1,53
+/*
+ * Copyright 2010 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie <airlied@redhat.com>
+ */
+#include "util/u_index_modify.h"
+#include "util/u_upload_mgr.h"
+#include "radeonsi_pipe.h"
+void r600_translate_index_buffer(struct r600_context *r600,
+                                 struct pipe_index_buffer *ib,
+                                 unsigned count)
+{
+        struct pipe_resource *out_buffer = NULL;
+        unsigned out_offset;
+        void *ptr;
+        switch (ib->index_size) {
+        case 1:
+                u_upload_alloc(r600->uploader, 0, count * 2,
+                               &out_offset, &out_buffer, &ptr);
+                util_shorten_ubyte_elts_to_userptr(
+                                &r600->context, ib, 0, ib->offset, count, ptr);
+                pipe_resource_reference(&ib->buffer, NULL);
+                ib->buffer = out_buffer;
+                ib->offset = out_offset;
+                ib->index_size = 2;
+                break;
+        }
+}

 /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/radeonsi_compute.c
 ,0 → 1,265
+#include "util/u_memory.h"
+#include "radeonsi_pipe.h"
+#include "radeonsi_shader.h"
+#include "radeon_llvm_util.h"
+#define MAX_GLOBAL_BUFFERS 20
+struct si_pipe_compute {
+        struct r600_context *ctx;
+        unsigned local_size;
+        unsigned private_size;
+        unsigned input_size;
+        unsigned num_kernels;
+        struct si_pipe_shader *kernels;
+        unsigned num_user_sgprs;
+        struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS];
+};
+static void *radeonsi_create_compute_state(
+        struct pipe_context *ctx,
+        const struct pipe_compute_state *cso)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct si_pipe_compute *program =
+                                        CALLOC_STRUCT(si_pipe_compute);
+        const struct pipe_llvm_program_header *header;
+        const unsigned char *code;
+        unsigned i;
+        header = cso->prog;
+        code = cso->prog + sizeof(struct pipe_llvm_program_header);
+        program->ctx = rctx;
+        program->local_size = cso->req_local_mem;
+        program->private_size = cso->req_private_mem;
+        program->input_size = cso->req_input_mem;
+        program->num_kernels = radeon_llvm_get_num_kernels(code,
+                                                        header->num_bytes);
+        program->kernels = CALLOC(sizeof(struct si_pipe_shader),
+                                                        program->num_kernels);
+        for (i = 0; i < program->num_kernels; i++) {
+                LLVMModuleRef mod = radeon_llvm_get_kernel_module(i, code,
+                                                        header->num_bytes);
+                si_compile_llvm(rctx, &program->kernels[i], mod);
+        }
+        return program;
+}
+static void radeonsi_bind_compute_state(struct pipe_context *ctx, void *state)
+{
+        struct r600_context *rctx = (struct r600_context*)ctx;
+        rctx->cs_shader_state.program = (struct si_pipe_compute*)state;
+}
+static void radeonsi_set_global_binding(
+        struct pipe_context *ctx, unsigned first, unsigned n,
+        struct pipe_resource **resources,
+        uint32_t **handles)
+{
+        unsigned i;
+        struct r600_context *rctx = (struct r600_context*)ctx;
+        struct si_pipe_compute *program = rctx->cs_shader_state.program;
+        if (!resources) {
+                for (i = first; i < first + n; i++) {
+                        program->global_buffers[i] = NULL;
+                }
+                return;
+        }
+        for (i = first; i < first + n; i++) {
+                uint64_t va;
+                program->global_buffers[i] = resources[i];
+                va = r600_resource_va(ctx->screen, resources[i]);
+                memcpy(handles[i], &va, sizeof(va));
+        }
+}
+static void radeonsi_launch_grid(
+                struct pipe_context *ctx,
+                const uint *block_layout, const uint *grid_layout,
+                uint32_t pc, const void *input)
+{
+        struct r600_context *rctx = (struct r600_context*)ctx;
+        struct si_pipe_compute *program = rctx->cs_shader_state.program;
+        struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+        struct si_resource *kernel_args_buffer = NULL;
+        unsigned kernel_args_size;
+        unsigned num_work_size_bytes = 36;
+        uint32_t kernel_args_offset = 0;
+        uint32_t *kernel_args;
+        uint64_t kernel_args_va;
+        uint64_t shader_va;
+        unsigned arg_user_sgpr_count = 2;
+        unsigned i;
+        struct si_pipe_shader *shader = &program->kernels[pc];
+        pm4->compute_pkt = true;
+        si_cmd_context_control(pm4);
+        si_pm4_cmd_begin(pm4, PKT3_EVENT_WRITE);
+        si_pm4_cmd_add(pm4, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH) |
+                            EVENT_INDEX(0x7) |
+                            EVENT_WRITE_INV_L2);
+        si_pm4_cmd_end(pm4, false);
+        si_pm4_inval_texture_cache(pm4);
+        si_pm4_inval_shader_cache(pm4);
+        si_cmd_surface_sync(pm4, pm4->cp_coher_cntl);
+        /* Upload the kernel arguments */
+        /* The extra num_work_size_bytes are for work group / work item size information */
+        kernel_args_size = program->input_size + num_work_size_bytes;
+        kernel_args = MALLOC(kernel_args_size);
+        for (i = 0; i < 3; i++) {
+                kernel_args[i] = grid_layout[i];
+                kernel_args[i + 3] = grid_layout[i] * block_layout[i];
+                kernel_args[i + 6] = block_layout[i];
+        }
+        memcpy(kernel_args + (num_work_size_bytes / 4), input, program->input_size);
+        r600_upload_const_buffer(rctx, &kernel_args_buffer, (uint8_t*)kernel_args,
+                                        kernel_args_size, &kernel_args_offset);
+        kernel_args_va = r600_resource_va(ctx->screen,
+                                (struct pipe_resource*)kernel_args_buffer);
+        kernel_args_va += kernel_args_offset;
+        si_pm4_add_bo(pm4, kernel_args_buffer, RADEON_USAGE_READ);
+        si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0, kernel_args_va);
+        si_pm4_set_reg(pm4, R_00B900_COMPUTE_USER_DATA_0 + 4, S_008F04_BASE_ADDRESS_HI (kernel_args_va >> 32) | S_008F04_STRIDE(0));
+        si_pm4_set_reg(pm4, R_00B810_COMPUTE_START_X, 0);
+        si_pm4_set_reg(pm4, R_00B814_COMPUTE_START_Y, 0);
+        si_pm4_set_reg(pm4, R_00B818_COMPUTE_START_Z, 0);
+        si_pm4_set_reg(pm4, R_00B81C_COMPUTE_NUM_THREAD_X,
+                                S_00B81C_NUM_THREAD_FULL(block_layout[0]));
+        si_pm4_set_reg(pm4, R_00B820_COMPUTE_NUM_THREAD_Y,
+                                S_00B820_NUM_THREAD_FULL(block_layout[1]));
+        si_pm4_set_reg(pm4, R_00B824_COMPUTE_NUM_THREAD_Z,
+                                S_00B824_NUM_THREAD_FULL(block_layout[2]));
+        /* Global buffers */
+        for (i = 0; i < MAX_GLOBAL_BUFFERS; i++) {
+                struct si_resource *buffer =
+                                (struct si_resource*)program->global_buffers[i];
+                if (!buffer) {
+                        continue;
+                }
+                si_pm4_add_bo(pm4, buffer, RADEON_USAGE_READWRITE);
+        }
+        /* XXX: This should be:
+         * (number of compute units) * 4 * (waves per simd) - 1 */
+        si_pm4_set_reg(pm4, R_00B82C_COMPUTE_MAX_WAVE_ID, 0x190 /* Default value */);
+        shader_va = r600_resource_va(ctx->screen, (void *)shader->bo);
+        si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
+        si_pm4_set_reg(pm4, R_00B830_COMPUTE_PGM_LO, (shader_va >> 8) & 0xffffffff);
+        si_pm4_set_reg(pm4, R_00B834_COMPUTE_PGM_HI, shader_va >> 40);
+        si_pm4_set_reg(pm4, R_00B848_COMPUTE_PGM_RSRC1,
+                /* We always use at least 3 VGPRS, these come from
+                 * TIDIG_COMP_CNT.
+                 * XXX: The compiler should account for this.
+                 */
+                S_00B848_VGPRS((MAX2(3, shader->num_vgprs) - 1) / 4)
+                /* We always use at least 4 + arg_user_sgpr_count.  The 4 extra
+                 * sgprs are from TGID_X_EN, TGID_Y_EN, TGID_Z_EN, TG_SIZE_EN
+                 * XXX: The compiler should account for this.
+                 */
+                |  S_00B848_SGPRS(((MAX2(4 + arg_user_sgpr_count,
+                                        shader->num_sgprs)) - 1) / 8))
+                ;
+        si_pm4_set_reg(pm4, R_00B84C_COMPUTE_PGM_RSRC2,
+                S_00B84C_SCRATCH_EN(0)
+                | S_00B84C_USER_SGPR(arg_user_sgpr_count)
+                | S_00B84C_TGID_X_EN(1)
+                | S_00B84C_TGID_Y_EN(1)
+                | S_00B84C_TGID_Z_EN(1)
+                | S_00B84C_TG_SIZE_EN(1)
+                | S_00B84C_TIDIG_COMP_CNT(2)
+                | S_00B84C_LDS_SIZE(shader->lds_size)
+                | S_00B84C_EXCP_EN(0))
+                ;
+        si_pm4_set_reg(pm4, R_00B854_COMPUTE_RESOURCE_LIMITS, 0);
+        si_pm4_set_reg(pm4, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0,
+                S_00B858_SH0_CU_EN(0xffff /* Default value */)
+                | S_00B858_SH1_CU_EN(0xffff /* Default value */))
+                ;
+        si_pm4_set_reg(pm4, R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1,
+                S_00B85C_SH0_CU_EN(0xffff /* Default value */)
+                | S_00B85C_SH1_CU_EN(0xffff /* Default value */))
+                ;
+        si_pm4_cmd_begin(pm4, PKT3_DISPATCH_DIRECT);
+        si_pm4_cmd_add(pm4, grid_layout[0]); /* Thread groups DIM_X */
+        si_pm4_cmd_add(pm4, grid_layout[1]); /* Thread groups DIM_Y */
+        si_pm4_cmd_add(pm4, grid_layout[2]); /* Thread gropus DIM_Z */
+        si_pm4_cmd_add(pm4, 1); /* DISPATCH_INITIATOR */
+        si_pm4_cmd_end(pm4, false);
+        si_pm4_cmd_begin(pm4, PKT3_EVENT_WRITE);
+        si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(0x4)));
+        si_pm4_cmd_end(pm4, false);
+        si_pm4_inval_texture_cache(pm4);
+        si_pm4_inval_shader_cache(pm4);
+        si_cmd_surface_sync(pm4, pm4->cp_coher_cntl);
+        si_pm4_emit(rctx, pm4);
+#if 0
+        fprintf(stderr, "cdw: %i\n", rctx->cs->cdw);
+        for (i = 0; i < rctx->cs->cdw; i++) {
+                fprintf(stderr, "%4i : 0x%08X\n", i, rctx->cs->buf[i]);
+        }
+#endif
+        rctx->ws->cs_flush(rctx->cs, RADEON_FLUSH_COMPUTE, 0);
+        rctx->ws->buffer_wait(shader->bo->buf, 0);
+        FREE(pm4);
+        FREE(kernel_args);
+}
+static void si_delete_compute_state(struct pipe_context *ctx, void* state){}
+static void si_set_compute_resources(struct pipe_context * ctx_,
+                unsigned start, unsigned count,
+                struct pipe_surface ** surfaces) { }
+static void si_set_cs_sampler_view(struct pipe_context *ctx_,
+                unsigned start_slot, unsigned count,
+                struct pipe_sampler_view **views) { }
+static void si_bind_compute_sampler_states(
+        struct pipe_context *ctx_,
+        unsigned start_slot,
+        unsigned num_samplers,
+        void **samplers_) { }
+void si_init_compute_functions(struct r600_context *rctx)
+{
+        rctx->context.create_compute_state = radeonsi_create_compute_state;
+        rctx->context.delete_compute_state = si_delete_compute_state;
+        rctx->context.bind_compute_state = radeonsi_bind_compute_state;
+/*       ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; */
+        rctx->context.set_compute_resources = si_set_compute_resources;
+        rctx->context.set_compute_sampler_views = si_set_cs_sampler_view;
+        rctx->context.bind_compute_sampler_states = si_bind_compute_sampler_states;
+        rctx->context.set_global_binding = radeonsi_set_global_binding;
+        rctx->context.launch_grid = radeonsi_launch_grid;
+}

 /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/radeonsi_pipe.c
 ,0 → 1,876
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <stdio.h>
+#include <errno.h>
+#include "pipe/p_defines.h"
+#include "pipe/p_state.h"
+#include "pipe/p_context.h"
+#include "tgsi/tgsi_scan.h"
+#include "tgsi/tgsi_parse.h"
+#include "tgsi/tgsi_util.h"
+#include "util/u_blitter.h"
+#include "util/u_double_list.h"
+#include "util/u_format.h"
+#include "util/u_format_s3tc.h"
+#include "util/u_transfer.h"
+#include "util/u_surface.h"
+#include "util/u_pack_color.h"
+#include "util/u_memory.h"
+#include "util/u_inlines.h"
+#include "util/u_simple_shaders.h"
+#include "util/u_upload_mgr.h"
+#include "vl/vl_decoder.h"
+#include "vl/vl_video_buffer.h"
+#include "os/os_time.h"
+#include "pipebuffer/pb_buffer.h"
+#include "radeonsi_pipe.h"
+#include "radeon/radeon_uvd.h"
+#include "r600.h"
+#include "sid.h"
+#include "r600_resource.h"
+#include "radeonsi_pipe.h"
+#include "r600_hw_context_priv.h"
+#include "si_state.h"
+/*
+ * pipe_context
+ */
+static struct r600_fence *r600_create_fence(struct r600_context *rctx)
+{
+        struct r600_screen *rscreen = rctx->screen;
+        struct r600_fence *fence = NULL;
+        pipe_mutex_lock(rscreen->fences.mutex);
+        if (!rscreen->fences.bo) {
+                /* Create the shared buffer object */
+                rscreen->fences.bo = si_resource_create_custom(&rscreen->screen,
+                                                               PIPE_USAGE_STAGING,
+);
+                if (!rscreen->fences.bo) {
+                        R600_ERR("r600: failed to create bo for fence objects\n");
+                        goto out;
+                }
+                rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->cs_buf,
+                                                           rctx->cs,
+                                                           PIPE_TRANSFER_READ_WRITE);
+        }
+        if (!LIST_IS_EMPTY(&rscreen->fences.pool)) {
+                struct r600_fence *entry;
+                /* Try to find a freed fence that has been signalled */
+                LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) {
+                        if (rscreen->fences.data[entry->index] != 0) {
+                                LIST_DELINIT(&entry->head);
+                                fence = entry;
+                                break;
+                        }
+                }
+        }
+        if (!fence) {
+                /* Allocate a new fence */
+                struct r600_fence_block *block;
+                unsigned index;
+                if ((rscreen->fences.next_index + 1) >= 1024) {
+                        R600_ERR("r600: too many concurrent fences\n");
+                        goto out;
+                }
+                index = rscreen->fences.next_index++;
+                if (!(index % FENCE_BLOCK_SIZE)) {
+                        /* Allocate a new block */
+                        block = CALLOC_STRUCT(r600_fence_block);
+                        if (block == NULL)
+                                goto out;
+                        LIST_ADD(&block->head, &rscreen->fences.blocks);
+                } else {
+                        block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head);
+                }
+                fence = &block->fences[index % FENCE_BLOCK_SIZE];
+                fence->index = index;
+        }
+        pipe_reference_init(&fence->reference, 1);
+        rscreen->fences.data[fence->index] = 0;
+        si_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
+        /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
+        fence->sleep_bo = si_resource_create_custom(&rctx->screen->screen, PIPE_USAGE_STAGING, 1);
+        /* Add the fence as a dummy relocation. */
+        r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE);
+out:
+        pipe_mutex_unlock(rscreen->fences.mutex);
+        return fence;
+}
+void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
+                    unsigned flags)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct r600_fence **rfence = (struct r600_fence**)fence;
+        struct pipe_query *render_cond = NULL;
+        boolean render_cond_cond = FALSE;
+        unsigned render_cond_mode = 0;
+        if (rfence)
+                *rfence = r600_create_fence(rctx);
+        /* Disable render condition. */
+        if (rctx->current_render_cond) {
+                render_cond = rctx->current_render_cond;
+                render_cond_cond = rctx->current_render_cond_cond;
+                render_cond_mode = rctx->current_render_cond_mode;
+                ctx->render_condition(ctx, NULL, FALSE, 0);
+        }
+        si_context_flush(rctx, flags);
+        /* Re-enable render condition. */
+        if (render_cond) {
+                ctx->render_condition(ctx, render_cond, render_cond_cond, render_cond_mode);
+        }
+}
+static void r600_flush_from_st(struct pipe_context *ctx,
+                               struct pipe_fence_handle **fence,
+                               unsigned flags)
+{
+        radeonsi_flush(ctx, fence,
+                       flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
+}
+static void r600_flush_from_winsys(void *ctx, unsigned flags)
+{
+        radeonsi_flush((struct pipe_context*)ctx, NULL, flags);
+}
+static void r600_destroy_context(struct pipe_context *context)
+{
+        struct r600_context *rctx = (struct r600_context *)context;
+        si_resource_reference(&rctx->border_color_table, NULL);
+        if (rctx->dummy_pixel_shader) {
+                rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader);
+        }
+        rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_depth_stencil);
+        rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_depth);
+        rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_stencil);
+        rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush_inplace);
+        util_unreference_framebuffer_state(&rctx->framebuffer);
+        util_blitter_destroy(rctx->blitter);
+        if (rctx->uploader) {
+                u_upload_destroy(rctx->uploader);
+        }
+        util_slab_destroy(&rctx->pool_transfers);
+        FREE(rctx);
+}
+static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
+{
+        struct r600_context *rctx = CALLOC_STRUCT(r600_context);
+        struct r600_screen* rscreen = (struct r600_screen *)screen;
+        if (rctx == NULL)
+                return NULL;
+        rctx->context.screen = screen;
+        rctx->context.priv = priv;
+        rctx->context.destroy = r600_destroy_context;
+        rctx->context.flush = r600_flush_from_st;
+        /* Easy accessing of screen/winsys. */
+        rctx->screen = rscreen;
+        rctx->ws = rscreen->ws;
+        rctx->family = rscreen->family;
+        rctx->chip_class = rscreen->chip_class;
+        si_init_blit_functions(rctx);
+        r600_init_query_functions(rctx);
+        r600_init_context_resource_functions(rctx);
+        si_init_surface_functions(rctx);
+        si_init_compute_functions(rctx);
+        if (rscreen->info.has_uvd) {
+                rctx->context.create_video_decoder = radeonsi_uvd_create_decoder;
+                rctx->context.create_video_buffer = radeonsi_video_buffer_create;
+        } else {
+                rctx->context.create_video_decoder = vl_create_decoder;
+                rctx->context.create_video_buffer = vl_video_buffer_create;
+        }
+        switch (rctx->chip_class) {
+        case SI:
+                si_init_state_functions(rctx);
+                LIST_INITHEAD(&rctx->active_query_list);
+                rctx->cs = rctx->ws->cs_create(rctx->ws, RING_GFX, NULL);
+                rctx->max_db = 8;
+                si_init_config(rctx);
+                break;
+        case CIK:
+                si_init_state_functions(rctx);
+                LIST_INITHEAD(&rctx->active_query_list);
+                rctx->cs = rctx->ws->cs_create(rctx->ws, RING_GFX, NULL);
+                rctx->max_db = 8;
+                si_init_config(rctx);
+                break;
+        default:
+                R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
+                r600_destroy_context(&rctx->context);
+                return NULL;
+        }
+        rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx);
+        util_slab_create(&rctx->pool_transfers,
+                         sizeof(struct pipe_transfer), 64,
+                         UTIL_SLAB_SINGLETHREADED);
+        rctx->uploader = u_upload_create(&rctx->context, 1024 * 1024, 256,
+                                         PIPE_BIND_INDEX_BUFFER |
+                                         PIPE_BIND_CONSTANT_BUFFER);
+        if (!rctx->uploader) {
+                r600_destroy_context(&rctx->context);
+                return NULL;
+        }
+        rctx->blitter = util_blitter_create(&rctx->context);
+        if (rctx->blitter == NULL) {
+                r600_destroy_context(&rctx->context);
+                return NULL;
+        }
+        si_get_backend_mask(rctx); /* this emits commands and must be last */
+        rctx->dummy_pixel_shader =
+                util_make_fragment_cloneinput_shader(&rctx->context, 0,
+                                                     TGSI_SEMANTIC_GENERIC,
+                                                     TGSI_INTERPOLATE_CONSTANT);
+        rctx->context.bind_fs_state(&rctx->context, rctx->dummy_pixel_shader);
+        return &rctx->context;
+}
+/*
+ * pipe_screen
+ */
+static const char* r600_get_vendor(struct pipe_screen* pscreen)
+{
+        return "X.Org";
+}
+const char *r600_get_llvm_processor_name(enum radeon_family family)
+{
+        switch (family) {
+                case CHIP_TAHITI: return "tahiti";
+                case CHIP_PITCAIRN: return "pitcairn";
+                case CHIP_VERDE: return "verde";
+                case CHIP_OLAND: return "oland";
+#if HAVE_LLVM <= 0x0303
+                default: return "SI";
+#else
+                case CHIP_HAINAN: return "hainan";
+                case CHIP_BONAIRE: return "bonaire";
+                case CHIP_KABINI: return "kabini";
+                case CHIP_KAVERI: return "kaveri";
+                default: return "";
+#endif
+        }
+}
+static const char *r600_get_family_name(enum radeon_family family)
+{
+        switch(family) {
+        case CHIP_TAHITI: return "AMD TAHITI";
+        case CHIP_PITCAIRN: return "AMD PITCAIRN";
+        case CHIP_VERDE: return "AMD CAPE VERDE";
+        case CHIP_OLAND: return "AMD OLAND";
+        case CHIP_HAINAN: return "AMD HAINAN";
+        case CHIP_BONAIRE: return "AMD BONAIRE";
+        case CHIP_KAVERI: return "AMD KAVERI";
+        case CHIP_KABINI: return "AMD KABINI";
+        default: return "AMD unknown";
+        }
+}
+static const char* r600_get_name(struct pipe_screen* pscreen)
+{
+        struct r600_screen *rscreen = (struct r600_screen *)pscreen;
+        return r600_get_family_name(rscreen->family);
+}
+static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
+{
+        struct r600_screen *rscreen = (struct r600_screen *)pscreen;
+        switch (param) {
+        /* Supported features (boolean caps). */
+        case PIPE_CAP_TWO_SIDED_STENCIL:
+        case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
+        case PIPE_CAP_ANISOTROPIC_FILTER:
+        case PIPE_CAP_POINT_SPRITE:
+        case PIPE_CAP_OCCLUSION_QUERY:
+        case PIPE_CAP_TEXTURE_SHADOW_MAP:
+        case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
+        case PIPE_CAP_BLEND_EQUATION_SEPARATE:
+        case PIPE_CAP_TEXTURE_SWIZZLE:
+        case PIPE_CAP_DEPTH_CLIP_DISABLE:
+        case PIPE_CAP_SHADER_STENCIL_EXPORT:
+        case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
+        case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
+        case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
+        case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
+        case PIPE_CAP_SM3:
+        case PIPE_CAP_SEAMLESS_CUBE_MAP:
+        case PIPE_CAP_PRIMITIVE_RESTART:
+        case PIPE_CAP_CONDITIONAL_RENDER:
+        case PIPE_CAP_TEXTURE_BARRIER:
+        case PIPE_CAP_INDEP_BLEND_ENABLE:
+        case PIPE_CAP_INDEP_BLEND_FUNC:
+        case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
+        case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
+        case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
+        case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
+        case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
+        case PIPE_CAP_USER_INDEX_BUFFERS:
+        case PIPE_CAP_USER_CONSTANT_BUFFERS:
+        case PIPE_CAP_START_INSTANCE:
+        case PIPE_CAP_NPOT_TEXTURES:
+        case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
+        case PIPE_CAP_TGSI_INSTANCEID:
+        case PIPE_CAP_COMPUTE:
+                return 1;
+        case PIPE_CAP_TGSI_TEXCOORD:
+                return 0;
+        case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
+                return 64;
+        case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
+                return 256;
+        case PIPE_CAP_GLSL_FEATURE_LEVEL:
+                return 130;
+        /* Unsupported features. */
+        case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
+        case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
+        case PIPE_CAP_SCALED_RESOLVE:
+        case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
+        case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
+        case PIPE_CAP_VERTEX_COLOR_CLAMPED:
+        case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
+        case PIPE_CAP_USER_VERTEX_BUFFERS:
+        case PIPE_CAP_TEXTURE_MULTISAMPLE:
+        case PIPE_CAP_QUERY_TIMESTAMP:
+        case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
+        case PIPE_CAP_CUBE_MAP_ARRAY:
+        case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
+        case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
+        case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
+        case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
+                return 0;
+        /* Stream output. */
+#if 0
+        case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
+                return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 4 : 0;
+        case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
+                return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 1 : 0;
+        case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
+        case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
+                return 16*4;
+#endif
+        case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
+        case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
+        case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
+        case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
+                return 0;
+        /* Texturing. */
+        case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
+        case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
+        case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
+                        return 15;
+        case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
+                return 16384;
+        case PIPE_CAP_MAX_COMBINED_SAMPLERS:
+                return 32;
+        /* Render targets. */
+        case PIPE_CAP_MAX_RENDER_TARGETS:
+                /* FIXME some r6xx are buggy and can only do 4 */
+                return 8;
+        /* Timer queries, present when the clock frequency is non zero. */
+        case PIPE_CAP_QUERY_TIME_ELAPSED:
+                return rscreen->info.r600_clock_crystal_freq != 0;
+        case PIPE_CAP_MIN_TEXEL_OFFSET:
+                return -8;
+        case PIPE_CAP_MAX_TEXEL_OFFSET:
+                return 7;
+        case PIPE_CAP_ENDIANNESS:
+                return PIPE_ENDIAN_LITTLE;
+        }
+        return 0;
+}
+static float r600_get_paramf(struct pipe_screen* pscreen,
+                             enum pipe_capf param)
+{
+        switch (param) {
+        case PIPE_CAPF_MAX_LINE_WIDTH:
+        case PIPE_CAPF_MAX_LINE_WIDTH_AA:
+        case PIPE_CAPF_MAX_POINT_WIDTH:
+        case PIPE_CAPF_MAX_POINT_WIDTH_AA:
+                return 16384.0f;
+        case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
+                return 16.0f;
+        case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
+                return 16.0f;
+        case PIPE_CAPF_GUARD_BAND_LEFT:
+        case PIPE_CAPF_GUARD_BAND_TOP:
+        case PIPE_CAPF_GUARD_BAND_RIGHT:
+        case PIPE_CAPF_GUARD_BAND_BOTTOM:
+                return 0.0f;
+        }
+        return 0.0f;
+}
+static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
+{
+        switch(shader)
+        {
+        case PIPE_SHADER_FRAGMENT:
+        case PIPE_SHADER_VERTEX:
+                break;
+        case PIPE_SHADER_GEOMETRY:
+                /* TODO: support and enable geometry programs */
+                return 0;
+        case PIPE_SHADER_COMPUTE:
+                switch (param) {
+                case PIPE_SHADER_CAP_PREFERRED_IR:
+                        return PIPE_SHADER_IR_LLVM;
+                default:
+                        return 0;
+                }
+        default:
+                /* TODO: support tessellation */
+                return 0;
+        }
+        switch (param) {
+        case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
+        case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
+        case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
+        case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
+                return 16384;
+        case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
+                return 32;
+        case PIPE_SHADER_CAP_MAX_INPUTS:
+                return 32;
+        case PIPE_SHADER_CAP_MAX_TEMPS:
+                return 256; /* Max native temporaries. */
+        case PIPE_SHADER_CAP_MAX_ADDRS:
+                /* FIXME Isn't this equal to TEMPS? */
+                return 1; /* Max native address registers */
+        case PIPE_SHADER_CAP_MAX_CONSTS:
+                return 4096; /* actually only memory limits this */
+        case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
+                return 1;
+        case PIPE_SHADER_CAP_MAX_PREDS:
+                return 0; /* FIXME */
+        case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
+                return 1;
+        case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
+                return 0;
+        case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
+        case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
+        case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
+        case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
+                return 1;
+        case PIPE_SHADER_CAP_INTEGERS:
+                return 1;
+        case PIPE_SHADER_CAP_SUBROUTINES:
+                return 0;
+        case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
+                return 16;
+        case PIPE_SHADER_CAP_PREFERRED_IR:
+                return PIPE_SHADER_IR_TGSI;
+        }
+        return 0;
+}
+static int r600_get_video_param(struct pipe_screen *screen,
+                                enum pipe_video_profile profile,
+                                enum pipe_video_cap param)
+{
+        switch (param) {
+        case PIPE_VIDEO_CAP_SUPPORTED:
+                return vl_profile_supported(screen, profile);
+        case PIPE_VIDEO_CAP_NPOT_TEXTURES:
+                return 1;
+        case PIPE_VIDEO_CAP_MAX_WIDTH:
+        case PIPE_VIDEO_CAP_MAX_HEIGHT:
+                return vl_video_buffer_max_size(screen);
+        case PIPE_VIDEO_CAP_PREFERED_FORMAT:
+                return PIPE_FORMAT_NV12;
+        default:
+                return 0;
+        }
+}
+static int r600_get_compute_param(struct pipe_screen *screen,
+        enum pipe_compute_cap param,
+        void *ret)
+{
+        struct r600_screen *rscreen = (struct r600_screen *)screen;
+        //TODO: select these params by asic
+        switch (param) {
+        case PIPE_COMPUTE_CAP_IR_TARGET: {
+                const char *gpu = r600_get_llvm_processor_name(rscreen->family);
+                if (ret) {
+                        sprintf(ret, "%s-r600--", gpu);
+                }
+                return (8 + strlen(gpu)) * sizeof(char);
+        }
+        case PIPE_COMPUTE_CAP_GRID_DIMENSION:
+                if (ret) {
+                        uint64_t * grid_dimension = ret;
+                        grid_dimension[0] = 3;
+                }
+                return 1 * sizeof(uint64_t);
+        case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
+                if (ret) {
+                        uint64_t * grid_size = ret;
+                        grid_size[0] = 65535;
+                        grid_size[1] = 65535;
+                        grid_size[2] = 1;
+                }
+                return 3 * sizeof(uint64_t) ;
+        case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
+                if (ret) {
+                        uint64_t * block_size = ret;
+                        block_size[0] = 256;
+                        block_size[1] = 256;
+                        block_size[2] = 256;
+                }
+                return 3 * sizeof(uint64_t);
+        case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
+                if (ret) {
+                        uint64_t * max_threads_per_block = ret;
+                        *max_threads_per_block = 256;
+                }
+                return sizeof(uint64_t);
+        case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
+                if (ret) {
+                        uint64_t *max_global_size = ret;
+                        /* XXX: Not sure what to put here. */
+                        *max_global_size = 2000000000;
+                }
+                return sizeof(uint64_t);
+        case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
+                if (ret) {
+                        uint64_t max_global_size;
+                        uint64_t *max_mem_alloc_size = ret;
+                        r600_get_compute_param(screen, PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE, &max_global_size);
+                        *max_mem_alloc_size = max_global_size / 4;
+                }
+                return sizeof(uint64_t);
+        default:
+                fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
+                return 0;
+        }
+}
+static void r600_destroy_screen(struct pipe_screen* pscreen)
+{
+        struct r600_screen *rscreen = (struct r600_screen *)pscreen;
+        if (rscreen == NULL)
+                return;
+        if (rscreen->fences.bo) {
+                struct r600_fence_block *entry, *tmp;
+                LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) {
+                        LIST_DEL(&entry->head);
+                        FREE(entry);
+                }
+                rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf);
+                si_resource_reference(&rscreen->fences.bo, NULL);
+        }
+#if R600_TRACE_CS
+        if (rscreen->trace_bo) {
+                rscreen->ws->buffer_unmap(rscreen->trace_bo->cs_buf);
+                pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
+        }
+#endif
+        pipe_mutex_destroy(rscreen->fences.mutex);
+        rscreen->ws->destroy(rscreen->ws);
+        FREE(rscreen);
+}
+static void r600_fence_reference(struct pipe_screen *pscreen,
+                                 struct pipe_fence_handle **ptr,
+                                 struct pipe_fence_handle *fence)
+{
+        struct r600_fence **oldf = (struct r600_fence**)ptr;
+        struct r600_fence *newf = (struct r600_fence*)fence;
+        if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
+                struct r600_screen *rscreen = (struct r600_screen *)pscreen;
+                pipe_mutex_lock(rscreen->fences.mutex);
+                si_resource_reference(&(*oldf)->sleep_bo, NULL);
+                LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
+                pipe_mutex_unlock(rscreen->fences.mutex);
+        }
+        *ptr = fence;
+}
+static boolean r600_fence_signalled(struct pipe_screen *pscreen,
+                                    struct pipe_fence_handle *fence)
+{
+        struct r600_screen *rscreen = (struct r600_screen *)pscreen;
+        struct r600_fence *rfence = (struct r600_fence*)fence;
+        return rscreen->fences.data[rfence->index] != 0;
+}
+static boolean r600_fence_finish(struct pipe_screen *pscreen,
+                                 struct pipe_fence_handle *fence,
+                                 uint64_t timeout)
+{
+        struct r600_screen *rscreen = (struct r600_screen *)pscreen;
+        struct r600_fence *rfence = (struct r600_fence*)fence;
+        int64_t start_time = 0;
+        unsigned spins = 0;
+        if (timeout != PIPE_TIMEOUT_INFINITE) {
+                start_time = os_time_get();
+                /* Convert to microseconds. */
+                timeout /= 1000;
+        }
+        while (rscreen->fences.data[rfence->index] == 0) {
+                /* Special-case infinite timeout - wait for the dummy BO to become idle */
+                if (timeout == PIPE_TIMEOUT_INFINITE) {
+                        rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE);
+                        break;
+                }
+                /* The dummy BO will be busy until the CS including the fence has completed, or
+                 * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
+                if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE))
+                        break;
+                if (++spins % 256)
+                        continue;
+#ifdef PIPE_OS_UNIX
+                sched_yield();
+#else
+                os_time_sleep(10);
+#endif
+                if (timeout != PIPE_TIMEOUT_INFINITE &&
+                    os_time_get() - start_time >= timeout) {
+                        break;
+                }
+        }
+        return rscreen->fences.data[rfence->index] != 0;
+}
+static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
+{
+        switch (tiling_config & 0xf) {
+        case 0:
+                rscreen->tiling_info.num_channels = 1;
+                break;
+        case 1:
+                rscreen->tiling_info.num_channels = 2;
+                break;
+        case 2:
+                rscreen->tiling_info.num_channels = 4;
+                break;
+        case 3:
+                rscreen->tiling_info.num_channels = 8;
+                break;
+        default:
+                return -EINVAL;
+        }
+        switch ((tiling_config & 0xf0) >> 4) {
+        case 0:
+                rscreen->tiling_info.num_banks = 4;
+                break;
+        case 1:
+                rscreen->tiling_info.num_banks = 8;
+                break;
+        case 2:
+                rscreen->tiling_info.num_banks = 16;
+                break;
+        default:
+                return -EINVAL;
+        }
+        switch ((tiling_config & 0xf00) >> 8) {
+        case 0:
+                rscreen->tiling_info.group_bytes = 256;
+                break;
+        case 1:
+                rscreen->tiling_info.group_bytes = 512;
+                break;
+        default:
+                return -EINVAL;
+        }
+        return 0;
+}
+static int r600_init_tiling(struct r600_screen *rscreen)
+{
+        uint32_t tiling_config = rscreen->info.r600_tiling_config;
+        /* set default group bytes, overridden by tiling info ioctl */
+        rscreen->tiling_info.group_bytes = 512;
+        if (!tiling_config)
+                return 0;
+        return evergreen_interpret_tiling(rscreen, tiling_config);
+}
+static unsigned radeon_family_from_device(unsigned device)
+{
+        switch (device) {
+#define CHIPSET(pciid, name, family) case pciid: return CHIP_##family;
+#include "pci_ids/radeonsi_pci_ids.h"
+#undef CHIPSET
+        default:
+                return CHIP_UNKNOWN;
+        }
+}
+struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
+{
+        struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
+        if (rscreen == NULL) {
+                return NULL;
+        }
+        rscreen->ws = ws;
+        ws->query_info(ws, &rscreen->info);
+        rscreen->family = radeon_family_from_device(rscreen->info.pci_id);
+        if (rscreen->family == CHIP_UNKNOWN) {
+                fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
+                FREE(rscreen);
+                return NULL;
+        }
+        /* setup class */
+        if (rscreen->family >= CHIP_BONAIRE) {
+                rscreen->chip_class = CIK;
+        } else if (rscreen->family >= CHIP_TAHITI) {
+                rscreen->chip_class = SI;
+        } else {
+                fprintf(stderr, "r600: Unsupported family %d\n", rscreen->family);
+                FREE(rscreen);
+                return NULL;
+        }
+        if (r600_init_tiling(rscreen)) {
+                FREE(rscreen);
+                return NULL;
+        }
+        rscreen->screen.destroy = r600_destroy_screen;
+        rscreen->screen.get_name = r600_get_name;
+        rscreen->screen.get_vendor = r600_get_vendor;
+        rscreen->screen.get_param = r600_get_param;
+        rscreen->screen.get_shader_param = r600_get_shader_param;
+        rscreen->screen.get_paramf = r600_get_paramf;
+        rscreen->screen.get_compute_param = r600_get_compute_param;
+        rscreen->screen.is_format_supported = si_is_format_supported;
+        rscreen->screen.context_create = r600_create_context;
+        rscreen->screen.fence_reference = r600_fence_reference;
+        rscreen->screen.fence_signalled = r600_fence_signalled;
+        rscreen->screen.fence_finish = r600_fence_finish;
+        r600_init_screen_resource_functions(&rscreen->screen);
+        if (rscreen->info.has_uvd) {
+                rscreen->screen.get_video_param = ruvd_get_video_param;
+                rscreen->screen.is_video_format_supported = ruvd_is_format_supported;
+        } else {
+                rscreen->screen.get_video_param = r600_get_video_param;
+                rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
+        }
+        util_format_s3tc_init();
+        rscreen->fences.bo = NULL;
+        rscreen->fences.data = NULL;
+        rscreen->fences.next_index = 0;
+        LIST_INITHEAD(&rscreen->fences.pool);
+        LIST_INITHEAD(&rscreen->fences.blocks);
+        pipe_mutex_init(rscreen->fences.mutex);
+#if R600_TRACE_CS
+        rscreen->cs_count = 0;
+        if (rscreen->info.drm_minor >= 28) {
+                rscreen->trace_bo = (struct si_resource*)pipe_buffer_create(&rscreen->screen,
+                                                                                PIPE_BIND_CUSTOM,
+                                                                                PIPE_USAGE_STAGING,
+);
+                if (rscreen->trace_bo) {
+                        rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
+                                                                        PIPE_TRANSFER_UNSYNCHRONIZED);
+                }
+        }
+#endif
+        return &rscreen->screen;
+}

 /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/radeonsi_pipe.h
 ,0 → 1,322
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#ifndef RADEONSI_PIPE_H
+#define RADEONSI_PIPE_H
+#include "../../winsys/radeon/drm/radeon_winsys.h"
+#include "pipe/p_state.h"
+#include "pipe/p_screen.h"
+#include "pipe/p_context.h"
+#include "util/u_format.h"
+#include "util/u_math.h"
+#include "util/u_slab.h"
+#include "r600.h"
+#include "radeonsi_public.h"
+#include "radeonsi_pm4.h"
+#include "si_state.h"
+#include "r600_resource.h"
+#include "sid.h"
+#ifdef PIPE_ARCH_BIG_ENDIAN
+#define R600_BIG_ENDIAN 1
+#else
+#define R600_BIG_ENDIAN 0
+#endif
+#define R600_TRACE_CS 0
+#define R600_TRACE_CS_DWORDS            6
+struct si_pipe_compute;
+struct r600_pipe_fences {
+        struct si_resource              *bo;
+        unsigned                        *data;
+        unsigned                        next_index;
+        /* linked list of preallocated blocks */
+        struct list_head                blocks;
+        /* linked list of freed fences */
+        struct list_head                pool;
+        pipe_mutex                      mutex;
+};
+struct r600_screen {
+        struct pipe_screen              screen;
+        struct radeon_winsys            *ws;
+        unsigned                        family;
+        enum chip_class                 chip_class;
+        struct radeon_info              info;
+        struct r600_tiling_info         tiling_info;
+        struct util_slab_mempool        pool_buffers;
+        struct r600_pipe_fences         fences;
+#if R600_TRACE_CS
+        struct si_resource              *trace_bo;
+        uint32_t                        *trace_ptr;
+        unsigned                        cs_count;
+#endif
+};
+struct si_pipe_sampler_view {
+        struct pipe_sampler_view        base;
+        struct si_resource              *resource;
+        uint32_t                        state[8];
+};
+struct si_pipe_sampler_state {
+        uint32_t                        val[4];
+        uint32_t                        border_color[4];
+};
+struct si_cs_shader_state {
+        struct si_pipe_compute          *program;
+};
+/* needed for blitter save */
+#define NUM_TEX_UNITS 16
+struct r600_textures_info {
+        struct si_pipe_sampler_view     *views[NUM_TEX_UNITS];
+        struct si_pipe_sampler_state    *samplers[NUM_TEX_UNITS];
+        unsigned                        n_views;
+        uint32_t                        depth_texture_mask; /* which textures are depth */
+        unsigned                        n_samplers;
+        bool                            samplers_dirty;
+        bool                            is_array_sampler[NUM_TEX_UNITS];
+};
+struct r600_fence {
+        struct pipe_reference           reference;
+        unsigned                        index; /* in the shared bo */
+        struct si_resource            *sleep_bo;
+        struct list_head                head;
+};
+#define FENCE_BLOCK_SIZE 16
+struct r600_fence_block {
+        struct r600_fence               fences[FENCE_BLOCK_SIZE];
+        struct list_head                head;
+};
+#define R600_CONSTANT_ARRAY_SIZE 256
+#define R600_RESOURCE_ARRAY_SIZE 160
+struct r600_constbuf_state
+{
+        struct pipe_constant_buffer     cb[2];
+        uint32_t                        enabled_mask;
+        uint32_t                        dirty_mask;
+};
+struct r600_context {
+        struct pipe_context             context;
+        struct blitter_context          *blitter;
+        enum radeon_family              family;
+        enum chip_class                 chip_class;
+        void                            *custom_dsa_flush_depth_stencil;
+        void                            *custom_dsa_flush_depth;
+        void                            *custom_dsa_flush_stencil;
+        void                            *custom_dsa_flush_inplace;
+        struct r600_screen              *screen;
+        struct radeon_winsys            *ws;
+        struct si_vertex_element        *vertex_elements;
+        struct pipe_framebuffer_state   framebuffer;
+        unsigned                        pa_sc_line_stipple;
+        unsigned                        pa_su_sc_mode_cntl;
+        /* for saving when using blitter */
+        struct pipe_stencil_ref         stencil_ref;
+        struct si_pipe_shader_selector  *ps_shader;
+        struct si_pipe_shader_selector  *vs_shader;
+        struct si_cs_shader_state       cs_shader_state;
+        struct pipe_query               *current_render_cond;
+        unsigned                        current_render_cond_mode;
+        boolean                         current_render_cond_cond;
+        struct pipe_query               *saved_render_cond;
+        unsigned                        saved_render_cond_mode;
+        boolean                         saved_render_cond_cond;
+        /* shader information */
+        unsigned                        sprite_coord_enable;
+        unsigned                        export_16bpc;
+        struct r600_constbuf_state      constbuf_state[PIPE_SHADER_TYPES];
+        struct r600_textures_info       vs_samplers;
+        struct r600_textures_info       ps_samplers;
+        struct si_resource              *border_color_table;
+        unsigned                        border_color_offset;
+        struct u_upload_mgr             *uploader;
+        struct util_slab_mempool        pool_transfers;
+        unsigned default_ps_gprs, default_vs_gprs;
+        /* Below are variables from the old r600_context.
+         */
+        struct radeon_winsys_cs *cs;
+        unsigned                pm4_dirty_cdwords;
+        /* The list of active queries. Only one query of each type can be active. */
+        struct list_head        active_query_list;
+        unsigned                num_cs_dw_queries_suspend;
+        unsigned                num_cs_dw_streamout_end;
+        unsigned                backend_mask;
+        unsigned                max_db; /* for OQ */
+        unsigned                flags;
+        boolean                 predicate_drawing;
+        unsigned                num_so_targets;
+        struct r600_so_target   *so_targets[PIPE_MAX_SO_BUFFERS];
+        boolean                 streamout_start;
+        unsigned                streamout_append_bitmask;
+        unsigned                *vs_so_stride_in_dw;
+        unsigned                *vs_shader_so_strides;
+        /* Vertex and index buffers. */
+        bool                    vertex_buffers_dirty;
+        struct pipe_index_buffer index_buffer;
+        struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
+        unsigned                nr_vertex_buffers;
+        /* With rasterizer discard, there doesn't have to be a pixel shader.
+         * In that case, we bind this one: */
+        struct si_pipe_shader   *dummy_pixel_shader;
+        /* SI state handling */
+        union si_state  queued;
+        union si_state  emitted;
+};
+/* r600_blit.c */
+void si_init_blit_functions(struct r600_context *rctx);
+void si_blit_uncompress_depth(struct pipe_context *ctx,
+                struct r600_resource_texture *texture,
+                struct r600_resource_texture *staging,
+                unsigned first_level, unsigned last_level,
+                unsigned first_layer, unsigned last_layer);
+void si_flush_depth_textures(struct r600_context *rctx,
+                             struct r600_textures_info *textures);
+/* r600_buffer.c */
+bool si_init_resource(struct r600_screen *rscreen,
+                      struct si_resource *res,
+                      unsigned size, unsigned alignment,
+                      boolean use_reusable_pool, unsigned usage);
+struct pipe_resource *si_buffer_create(struct pipe_screen *screen,
+                                       const struct pipe_resource *templ);
+void r600_upload_index_buffer(struct r600_context *rctx,
+                              struct pipe_index_buffer *ib, unsigned count);
+/* r600_pipe.c */
+void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
+                    unsigned flags);
+const char *r600_get_llvm_processor_name(enum radeon_family family);
+/* r600_query.c */
+void r600_init_query_functions(struct r600_context *rctx);
+/* r600_resource.c */
+void r600_init_context_resource_functions(struct r600_context *r600);
+/* r600_texture.c */
+void r600_init_screen_texture_functions(struct pipe_screen *screen);
+void si_init_surface_functions(struct r600_context *r600);
+/* r600_translate.c */
+void r600_translate_index_buffer(struct r600_context *r600,
+                                 struct pipe_index_buffer *ib,
+                                 unsigned count);
+#if R600_TRACE_CS
+void r600_trace_emit(struct r600_context *rctx);
+#endif
+/* radeonsi_compute.c */
+void si_init_compute_functions(struct r600_context *rctx);
+/* radeonsi_uvd.c */
+struct pipe_video_decoder *radeonsi_uvd_create_decoder(struct pipe_context *context,
+                                                       enum pipe_video_profile profile,
+                                                       enum pipe_video_entrypoint entrypoint,
+                                                       enum pipe_video_chroma_format chroma_format,
+                                                       unsigned width, unsigned height,
+                                                       unsigned max_references, bool expect_chunked_decode);
+struct pipe_video_buffer *radeonsi_video_buffer_create(struct pipe_context *pipe,
+                                                       const struct pipe_video_buffer *tmpl);
+/*
+ * common helpers
+ */
+static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
+{
+        return value * (1 << frac_bits);
+}
+#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
+static INLINE unsigned si_map_swizzle(unsigned swizzle)
+{
+        switch (swizzle) {
+        case UTIL_FORMAT_SWIZZLE_Y:
+                return V_008F0C_SQ_SEL_Y;
+        case UTIL_FORMAT_SWIZZLE_Z:
+                return V_008F0C_SQ_SEL_Z;
+        case UTIL_FORMAT_SWIZZLE_W:
+                return V_008F0C_SQ_SEL_W;
+        case UTIL_FORMAT_SWIZZLE_0:
+                return V_008F0C_SQ_SEL_0;
+        case UTIL_FORMAT_SWIZZLE_1:
+                return V_008F0C_SQ_SEL_1;
+        default: /* UTIL_FORMAT_SWIZZLE_X */
+                return V_008F0C_SQ_SEL_X;
+        }
+}
+static inline unsigned r600_tex_aniso_filter(unsigned filter)
+{
+        if (filter <= 1)   return 0;
+        if (filter <= 2)   return 1;
+        if (filter <= 4)   return 2;
+        if (filter <= 8)   return 3;
+         /* else */        return 4;
+}
+/* 12.4 fixed-point */
+static INLINE unsigned r600_pack_float_12p4(float x)
+{
+        return x <= 0    ? 0 :
+               x >= 4096 ? 0xffff : x * 16;
+}
+static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
+{
+        struct r600_screen *rscreen = (struct r600_screen*)screen;
+        struct si_resource *rresource = (struct si_resource*)resource;
+        return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
+}
+#endif

 /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/radeonsi_pm4.c
 ,0 → 1,264
+/*
+ * Copyright 2012 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Christian König <christian.koenig@amd.com>
+ */
+#include "util/u_memory.h"
+#include "radeonsi_pipe.h"
+#include "radeonsi_pm4.h"
+#include "sid.h"
+#include "r600_hw_context_priv.h"
+#define NUMBER_OF_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *))
+void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode)
+{
+        state->last_opcode = opcode;
+        state->last_pm4 = state->ndw++;
+}
+void si_pm4_cmd_add(struct si_pm4_state *state, uint32_t dw)
+{
+        state->pm4[state->ndw++] = dw;
+}
+void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate)
+{
+        unsigned count;
+        count = state->ndw - state->last_pm4 - 2;
+        state->pm4[state->last_pm4] =
+                PKT3(state->last_opcode, count, predicate)
+                   | PKT3_SHADER_TYPE_S(state->compute_pkt);
+        assert(state->ndw <= SI_PM4_MAX_DW);
+}
+void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val)
+{
+        unsigned opcode;
+        if (reg >= SI_CONFIG_REG_OFFSET && reg < SI_CONFIG_REG_END) {
+                opcode = PKT3_SET_CONFIG_REG;
+                reg -= SI_CONFIG_REG_OFFSET;
+        } else if (reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END) {
+                opcode = PKT3_SET_SH_REG;
+                reg -= SI_SH_REG_OFFSET;
+        } else if (reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END) {
+                opcode = PKT3_SET_CONTEXT_REG;
+                reg -= SI_CONTEXT_REG_OFFSET;
+        } else if (reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END) {
+                opcode = PKT3_SET_UCONFIG_REG;
+                reg -= CIK_UCONFIG_REG_OFFSET;
+        } else {
+                R600_ERR("Invalid register offset %08x!\n", reg);
+                return;
+        }
+        reg >>= 2;
+        if (opcode != state->last_opcode || reg != (state->last_reg + 1)) {
+                si_pm4_cmd_begin(state, opcode);
+                si_pm4_cmd_add(state, reg);
+        }
+        state->last_reg = reg;
+        si_pm4_cmd_add(state, val);
+        si_pm4_cmd_end(state, false);
+}
+void si_pm4_add_bo(struct si_pm4_state *state,
+                   struct si_resource *bo,
+                   enum radeon_bo_usage usage)
+{
+        unsigned idx = state->nbo++;
+        assert(idx < SI_PM4_MAX_BO);
+        si_resource_reference(&state->bo[idx], bo);
+        state->bo_usage[idx] = usage;
+}
+void si_pm4_sh_data_begin(struct si_pm4_state *state)
+{
+        si_pm4_cmd_begin(state, PKT3_NOP);
+}
+void si_pm4_sh_data_add(struct si_pm4_state *state, uint32_t dw)
+{
+        si_pm4_cmd_add(state, dw);
+}
+void si_pm4_sh_data_end(struct si_pm4_state *state, unsigned base, unsigned idx)
+{
+        unsigned offs = state->last_pm4 + 1;
+        unsigned reg = base + idx * 4;
+        /* Bail if no data was added */
+        if (state->ndw == offs) {
+                state->ndw--;
+                return;
+        }
+        si_pm4_cmd_end(state, false);
+        si_pm4_cmd_begin(state, PKT3_SET_SH_REG_OFFSET);
+        si_pm4_cmd_add(state, (reg - SI_SH_REG_OFFSET) >> 2);
+        state->relocs[state->nrelocs++] = state->ndw;
+        si_pm4_cmd_add(state, offs << 2);
+        si_pm4_cmd_add(state, 0);
+        si_pm4_cmd_end(state, false);
+}
+void si_pm4_inval_shader_cache(struct si_pm4_state *state)
+{
+        state->cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
+        state->cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
+}
+void si_pm4_inval_texture_cache(struct si_pm4_state *state)
+{
+        state->cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1);
+        state->cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1);
+}
+void si_pm4_inval_fb_cache(struct si_pm4_state *state, unsigned nr_cbufs)
+{
+        state->cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1);
+        state->cp_coher_cntl |= ((1 << nr_cbufs) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT;
+}
+void si_pm4_inval_zsbuf_cache(struct si_pm4_state *state)
+{
+        state->cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) | S_0085F0_DB_DEST_BASE_ENA(1);
+}
+void si_pm4_free_state(struct r600_context *rctx,
+                       struct si_pm4_state *state,
+                       unsigned idx)
+{
+        if (state == NULL)
+                return;
+        if (idx != ~0 && rctx->emitted.array[idx] == state) {
+                rctx->emitted.array[idx] = NULL;
+        }
+        for (int i = 0; i < state->nbo; ++i) {
+                si_resource_reference(&state->bo[i], NULL);
+        }
+        FREE(state);
+}
+struct si_pm4_state * si_pm4_alloc_state(struct r600_context *rctx)
+{
+        struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+        if (pm4 == NULL)
+                return NULL;
+        pm4->chip_class = rctx->chip_class;
+        return pm4;
+}
+uint32_t si_pm4_sync_flags(struct r600_context *rctx)
+{
+        uint32_t cp_coher_cntl = 0;
+        for (int i = 0; i < NUMBER_OF_STATES; ++i) {
+                struct si_pm4_state *state = rctx->queued.array[i];
+                if (!state || rctx->emitted.array[i] == state)
+                        continue;
+                cp_coher_cntl |= state->cp_coher_cntl;
+        }
+        return cp_coher_cntl;
+}
+unsigned si_pm4_dirty_dw(struct r600_context *rctx)
+{
+        unsigned count = 0;
+        for (int i = 0; i < NUMBER_OF_STATES; ++i) {
+                struct si_pm4_state *state = rctx->queued.array[i];
+                if (!state || rctx->emitted.array[i] == state)
+                        continue;
+                count += state->ndw;
+#if R600_TRACE_CS
+                /* for tracing each states */
+                if (rctx->screen->trace_bo) {
+                        count += R600_TRACE_CS_DWORDS;
+                }
+#endif
+        }
+        return count;
+}
+void si_pm4_emit(struct r600_context *rctx, struct si_pm4_state *state)
+{
+        struct radeon_winsys_cs *cs = rctx->cs;
+        for (int i = 0; i < state->nbo; ++i) {
+                r600_context_bo_reloc(rctx, state->bo[i],
+                                      state->bo_usage[i]);
+        }
+        memcpy(&cs->buf[cs->cdw], state->pm4, state->ndw * 4);
+        for (int i = 0; i < state->nrelocs; ++i) {
+                cs->buf[cs->cdw + state->relocs[i]] += cs->cdw << 2;
+        }
+        cs->cdw += state->ndw;
+#if R600_TRACE_CS
+        if (rctx->screen->trace_bo) {
+                r600_trace_emit(rctx);
+        }
+#endif
+}
+void si_pm4_emit_dirty(struct r600_context *rctx)
+{
+        for (int i = 0; i < NUMBER_OF_STATES; ++i) {
+                struct si_pm4_state *state = rctx->queued.array[i];
+                if (!state || rctx->emitted.array[i] == state)
+                        continue;
+                si_pm4_emit(rctx, state);
+                rctx->emitted.array[i] = state;
+        }
+}
+void si_pm4_reset_emitted(struct r600_context *rctx)
+{
+        memset(&rctx->emitted, 0, sizeof(rctx->emitted));
+}

 /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/radeonsi_pm4.h
 ,0 → 1,97
+/*
+ * Copyright 2012 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Christian König <christian.koenig@amd.com>
+ */
+#ifndef RADEONSI_PM4_H
+#define RADEONSI_PM4_H
+#include "../../winsys/radeon/drm/radeon_winsys.h"
+#define SI_PM4_MAX_DW           256
+#define SI_PM4_MAX_BO           32
+#define SI_PM4_MAX_RELOCS       4
+// forward defines
+struct r600_context;
+enum chip_class;
+struct si_pm4_state
+{
+        /* family specific handling */
+        enum chip_class chip_class;
+        /* PKT3_SET_*_REG handling */
+        unsigned        last_opcode;
+        unsigned        last_reg;
+        unsigned        last_pm4;
+        /* flush flags for SURFACE_SYNC */
+        uint32_t        cp_coher_cntl;
+        /* commands for the DE */
+        unsigned        ndw;
+        uint32_t        pm4[SI_PM4_MAX_DW];
+        /* BO's referenced by this state */
+        unsigned                nbo;
+        struct si_resource      *bo[SI_PM4_MAX_BO];
+        enum radeon_bo_usage    bo_usage[SI_PM4_MAX_BO];
+        /* relocs for shader data */
+        unsigned        nrelocs;
+        unsigned        relocs[SI_PM4_MAX_RELOCS];
+        bool compute_pkt;
+};
+void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode);
+void si_pm4_cmd_add(struct si_pm4_state *state, uint32_t dw);
+void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate);
+void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val);
+void si_pm4_add_bo(struct si_pm4_state *state,
+                   struct si_resource *bo,
+                   enum radeon_bo_usage usage);
+void si_pm4_sh_data_begin(struct si_pm4_state *state);
+void si_pm4_sh_data_add(struct si_pm4_state *state, uint32_t dw);
+void si_pm4_sh_data_end(struct si_pm4_state *state, unsigned base, unsigned idx);
+void si_pm4_inval_shader_cache(struct si_pm4_state *state);
+void si_pm4_inval_texture_cache(struct si_pm4_state *state);
+void si_pm4_inval_fb_cache(struct si_pm4_state *state, unsigned nr_cbufs);
+void si_pm4_inval_zsbuf_cache(struct si_pm4_state *state);
+void si_pm4_free_state(struct r600_context *rctx,
+                       struct si_pm4_state *state,
+                       unsigned idx);
+struct si_pm4_state * si_pm4_alloc_state(struct r600_context *rctx);
+uint32_t si_pm4_sync_flags(struct r600_context *rctx);
+unsigned si_pm4_dirty_dw(struct r600_context *rctx);
+void si_pm4_emit(struct r600_context *rctx, struct si_pm4_state *state);
+void si_pm4_emit_dirty(struct r600_context *rctx);
+void si_pm4_reset_emitted(struct r600_context *rctx);
+#endif

 /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/radeonsi_public.h
 ,0 → 1,30
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef RADEONSI_PUBLIC_H
+#define RADEONSI_PUBLIC_H
+struct radeon_winsys;
+struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws);
+#endif

 /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/radeonsi_resource.h
 ,0 → 1,67
+/*
+ * Copyright 2012 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Christian König <christian.koenig@amd.com>
+ */
+#ifndef RADEONSI_RESOURCE_H
+#define RADEONSI_RESOURCE_H
+#include "../../winsys/radeon/drm/radeon_winsys.h"
+#include "util/u_transfer.h"
+#include "util/u_inlines.h"
+struct si_resource {
+        struct u_resource               b;
+        /* Winsys objects. */
+        struct pb_buffer                *buf;
+        struct radeon_winsys_cs_handle  *cs_buf;
+        /* Resource state. */
+        unsigned                        domains;
+};
+static INLINE void
+si_resource_reference(struct si_resource **ptr, struct si_resource *res)
+{
+        pipe_resource_reference((struct pipe_resource **)ptr,
+                                (struct pipe_resource *)res);
+}
+static INLINE struct si_resource *
+si_resource(struct pipe_resource *r)
+{
+        return (struct si_resource*)r;
+}
+static INLINE struct si_resource *
+si_resource_create_custom(struct pipe_screen *screen,
+                          unsigned usage, unsigned size)
+{
+        assert(size);
+        return si_resource(pipe_buffer_create(screen,
+                PIPE_BIND_CUSTOM, usage, size));
+}
+#endif

 /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/radeonsi_shader.c
 ,0 → 1,1541
+/*
+ * Copyright 2012 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Tom Stellard <thomas.stellard@amd.com>
+ *      Michel Dänzer <michel.daenzer@amd.com>
+ *      Christian König <christian.koenig@amd.com>
+ */
+#include "gallivm/lp_bld_tgsi_action.h"
+#include "gallivm/lp_bld_const.h"
+#include "gallivm/lp_bld_gather.h"
+#include "gallivm/lp_bld_intr.h"
+#include "gallivm/lp_bld_logic.h"
+#include "gallivm/lp_bld_tgsi.h"
+#include "gallivm/lp_bld_arit.h"
+#include "radeon_llvm.h"
+#include "radeon_llvm_emit.h"
+#include "util/u_memory.h"
+#include "tgsi/tgsi_info.h"
+#include "tgsi/tgsi_parse.h"
+#include "tgsi/tgsi_scan.h"
+#include "tgsi/tgsi_util.h"
+#include "tgsi/tgsi_dump.h"
+#include "radeonsi_pipe.h"
+#include "radeonsi_shader.h"
+#include "si_state.h"
+#include "sid.h"
+#include <assert.h>
+#include <errno.h>
+#include <stdio.h>
+struct si_shader_context
+{
+        struct radeon_llvm_context radeon_bld;
+        struct tgsi_parse_context parse;
+        struct tgsi_token * tokens;
+        struct si_pipe_shader *shader;
+        unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
+        LLVMValueRef const_md;
+        LLVMValueRef const_resource;
+#if HAVE_LLVM >= 0x0304
+        LLVMValueRef ddxy_lds;
+#endif
+        LLVMValueRef *constants;
+        LLVMValueRef *resources;
+        LLVMValueRef *samplers;
+};
+static struct si_shader_context * si_shader_context(
+        struct lp_build_tgsi_context * bld_base)
+{
+        return (struct si_shader_context *)bld_base;
+}
+#define PERSPECTIVE_BASE 0
+#define LINEAR_BASE 9
+#define SAMPLE_OFFSET 0
+#define CENTER_OFFSET 2
+#define CENTROID_OFSET 4
+#define USE_SGPR_MAX_SUFFIX_LEN 5
+#define CONST_ADDR_SPACE 2
+#define LOCAL_ADDR_SPACE 3
+#define USER_SGPR_ADDR_SPACE 8
+/**
+ * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad
+ *
+ * @param offset The offset parameter specifies the number of
+ * elements to offset, not the number of bytes or dwords.  An element is the
+ * the type pointed to by the base_ptr parameter (e.g. int is the element of
+ * an int* pointer)
+ *
+ * When LLVM lowers the load instruction, it will convert the element offset
+ * into a dword offset automatically.
+ *
+ */
+static LLVMValueRef build_indexed_load(
+        struct si_shader_context * si_shader_ctx,
+        LLVMValueRef base_ptr,
+        LLVMValueRef offset)
+{
+        struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
+        LLVMValueRef computed_ptr = LLVMBuildGEP(
+                base->gallivm->builder, base_ptr, &offset, 1, "");
+        LLVMValueRef result = LLVMBuildLoad(base->gallivm->builder, computed_ptr, "");
+        LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
+        return result;
+}
+static LLVMValueRef get_instance_index(
+        struct radeon_llvm_context * radeon_bld,
+        unsigned divisor)
+{
+        struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
+        LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_INSTANCE_ID);
+        result = LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
+                        radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
+        if (divisor > 1)
+                result = LLVMBuildUDiv(gallivm->builder, result,
+                                lp_build_const_int32(gallivm, divisor), "");
+        return result;
+}
+static void declare_input_vs(
+        struct si_shader_context * si_shader_ctx,
+        unsigned input_index,
+        const struct tgsi_full_declaration *decl)
+{
+        struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
+        unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
+        unsigned chan;
+        LLVMValueRef t_list_ptr;
+        LLVMValueRef t_offset;
+        LLVMValueRef t_list;
+        LLVMValueRef attribute_offset;
+        LLVMValueRef buffer_index;
+        LLVMValueRef args[3];
+        LLVMTypeRef vec4_type;
+        LLVMValueRef input;
+        /* Load the T list */
+        t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
+        t_offset = lp_build_const_int32(base->gallivm, input_index);
+        t_list = build_indexed_load(si_shader_ctx, t_list_ptr, t_offset);
+        /* Build the attribute offset */
+        attribute_offset = lp_build_const_int32(base->gallivm, 0);
+        if (divisor) {
+                /* Build index from instance ID, start instance and divisor */
+                si_shader_ctx->shader->shader.uses_instanceid = true;
+                buffer_index = get_instance_index(&si_shader_ctx->radeon_bld, divisor);
+        } else {
+                /* Load the buffer index, which is always stored in VGPR0
+                 * for Vertex Shaders */
+                buffer_index = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_ID);
+        }
+        vec4_type = LLVMVectorType(base->elem_type, 4);
+        args[0] = t_list;
+        args[1] = attribute_offset;
+        args[2] = buffer_index;
+        input = build_intrinsic(base->gallivm->builder,
+                "llvm.SI.vs.load.input", vec4_type, args, 3,
+                LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
+        /* Break up the vec4 into individual components */
+        for (chan = 0; chan < 4; chan++) {
+                LLVMValueRef llvm_chan = lp_build_const_int32(base->gallivm, chan);
+                /* XXX: Use a helper function for this.  There is one in
+                 * tgsi_llvm.c. */
+                si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
+                                LLVMBuildExtractElement(base->gallivm->builder,
+                                input, llvm_chan, "");
+        }
+}
+static void declare_input_fs(
+        struct si_shader_context * si_shader_ctx,
+        unsigned input_index,
+        const struct tgsi_full_declaration *decl)
+{
+        struct si_shader *shader = &si_shader_ctx->shader->shader;
+        struct lp_build_context * base =
+                                &si_shader_ctx->radeon_bld.soa.bld_base.base;
+        struct lp_build_context *uint =
+                                &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
+        struct gallivm_state * gallivm = base->gallivm;
+        LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
+        LLVMValueRef main_fn = si_shader_ctx->radeon_bld.main_fn;
+        LLVMValueRef interp_param;
+        const char * intr_name;
+        /* This value is:
+         * [15:0] NewPrimMask (Bit mask for each quad.  It is set it the
+         *                     quad begins a new primitive.  Bit 0 always needs
+         *                     to be unset)
+         * [32:16] ParamOffset
+         *
+         */
+        LLVMValueRef params = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
+        LLVMValueRef attr_number;
+        unsigned chan;
+        if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
+                for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
+                        unsigned soa_index =
+                                radeon_llvm_reg_index_soa(input_index, chan);
+                        si_shader_ctx->radeon_bld.inputs[soa_index] =
+                                LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
+                        if (chan == 3)
+                                /* RCP for fragcoord.w */
+                                si_shader_ctx->radeon_bld.inputs[soa_index] =
+                                        LLVMBuildFDiv(gallivm->builder,
+                                                      lp_build_const_float(gallivm, 1.0f),
+                                                      si_shader_ctx->radeon_bld.inputs[soa_index],
+                                                      "");
+                }
+                return;
+        }
+        if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
+                LLVMValueRef face, is_face_positive;
+                face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
+                is_face_positive = LLVMBuildFCmp(gallivm->builder,
+                                                 LLVMRealUGT, face,
+                                                 lp_build_const_float(gallivm, 0.0f),
+                                                 "");
+                si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
+                        LLVMBuildSelect(gallivm->builder,
+                                        is_face_positive,
+                                        lp_build_const_float(gallivm, 1.0f),
+                                        lp_build_const_float(gallivm, 0.0f),
+                                        "");
+                si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
+                si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
+                        lp_build_const_float(gallivm, 0.0f);
+                si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
+                        lp_build_const_float(gallivm, 1.0f);
+                return;
+        }
+        shader->input[input_index].param_offset = shader->ninterp++;
+        attr_number = lp_build_const_int32(gallivm,
+                                           shader->input[input_index].param_offset);
+        /* XXX: Handle all possible interpolation modes */
+        switch (decl->Interp.Interpolate) {
+        case TGSI_INTERPOLATE_COLOR:
+                if (si_shader_ctx->shader->key.ps.flatshade) {
+                        interp_param = 0;
+                } else {
+                        if (decl->Interp.Centroid)
+                                interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
+                        else
+                                interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
+                }
+                break;
+        case TGSI_INTERPOLATE_CONSTANT:
+                interp_param = 0;
+                break;
+        case TGSI_INTERPOLATE_LINEAR:
+                if (decl->Interp.Centroid)
+                        interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTROID);
+                else
+                        interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTER);
+                break;
+        case TGSI_INTERPOLATE_PERSPECTIVE:
+                if (decl->Interp.Centroid)
+                        interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
+                else
+                        interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
+                break;
+        default:
+                fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
+                return;
+        }
+        intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
+        /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
+        if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
+            si_shader_ctx->shader->key.ps.color_two_side) {
+                LLVMValueRef args[4];
+                LLVMValueRef face, is_face_positive;
+                LLVMValueRef back_attr_number =
+                        lp_build_const_int32(gallivm,
+                                             shader->input[input_index].param_offset + 1);
+                face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
+                is_face_positive = LLVMBuildFCmp(gallivm->builder,
+                                                 LLVMRealUGT, face,
+                                                 lp_build_const_float(gallivm, 0.0f),
+                                                 "");
+                args[2] = params;
+                args[3] = interp_param;
+                for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
+                        LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
+                        unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
+                        LLVMValueRef front, back;
+                        args[0] = llvm_chan;
+                        args[1] = attr_number;
+                        front = build_intrinsic(base->gallivm->builder, intr_name,
+                                                input_type, args, args[3] ? 4 : 3,
+                                                LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
+                        args[1] = back_attr_number;
+                        back = build_intrinsic(base->gallivm->builder, intr_name,
+                                               input_type, args, args[3] ? 4 : 3,
+                                               LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
+                        si_shader_ctx->radeon_bld.inputs[soa_index] =
+                                LLVMBuildSelect(gallivm->builder,
+                                                is_face_positive,
+                                                front,
+                                                back,
+                                                "");
+                }
+                shader->ninterp++;
+        } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
+                LLVMValueRef args[4];
+                args[0] = uint->zero;
+                args[1] = attr_number;
+                args[2] = params;
+                args[3] = interp_param;
+                si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
+                        build_intrinsic(base->gallivm->builder, intr_name,
+                                                input_type, args, args[3] ? 4 : 3,
+                                                LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
+                si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
+                si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
+                        lp_build_const_float(gallivm, 0.0f);
+                si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
+                        lp_build_const_float(gallivm, 1.0f);
+        } else {
+                for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
+                        LLVMValueRef args[4];
+                        LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
+                        unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
+                        args[0] = llvm_chan;
+                        args[1] = attr_number;
+                        args[2] = params;
+                        args[3] = interp_param;
+                        si_shader_ctx->radeon_bld.inputs[soa_index] =
+                                build_intrinsic(base->gallivm->builder, intr_name,
+                                                input_type, args, args[3] ? 4 : 3,
+                                                LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
+                }
+        }
+}
+static void declare_input(
+        struct radeon_llvm_context * radeon_bld,
+        unsigned input_index,
+        const struct tgsi_full_declaration *decl)
+{
+        struct si_shader_context * si_shader_ctx =
+                                si_shader_context(&radeon_bld->soa.bld_base);
+        if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
+                declare_input_vs(si_shader_ctx, input_index, decl);
+        } else if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
+                declare_input_fs(si_shader_ctx, input_index, decl);
+        } else {
+                fprintf(stderr, "Warning: Unsupported shader type,\n");
+        }
+}
+static void declare_system_value(
+        struct radeon_llvm_context * radeon_bld,
+        unsigned index,
+        const struct tgsi_full_declaration *decl)
+{
+        LLVMValueRef value = 0;
+        switch (decl->Semantic.Name) {
+        case TGSI_SEMANTIC_INSTANCEID:
+                value = get_instance_index(radeon_bld, 1);
+                break;
+        case TGSI_SEMANTIC_VERTEXID:
+                value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_VERTEX_ID);
+                break;
+        default:
+                assert(!"unknown system value");
+                return;
+        }
+        radeon_bld->system_values[index] = value;
+}
+static LLVMValueRef fetch_constant(
+        struct lp_build_tgsi_context * bld_base,
+        const struct tgsi_full_src_register *reg,
+        enum tgsi_opcode_type type,
+        unsigned swizzle)
+{
+        struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
+        struct lp_build_context * base = &bld_base->base;
+        const struct tgsi_ind_register *ireg = &reg->Indirect;
+        unsigned idx;
+        LLVMValueRef args[2];
+        LLVMValueRef addr;
+        LLVMValueRef result;
+        if (swizzle == LP_CHAN_ALL) {
+                unsigned chan;
+                LLVMValueRef values[4];
+                for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
+                        values[chan] = fetch_constant(bld_base, reg, type, chan);
+                return lp_build_gather_values(bld_base->base.gallivm, values, 4);
+        }
+        idx = reg->Register.Index * 4 + swizzle;
+        if (!reg->Register.Indirect)
+                return bitcast(bld_base, type, si_shader_ctx->constants[idx]);
+        args[0] = si_shader_ctx->const_resource;
+        args[1] = lp_build_const_int32(base->gallivm, idx * 4);
+        addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
+        addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
+        addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
+        args[1] = lp_build_add(&bld_base->uint_bld, addr, args[1]);
+        result = build_intrinsic(base->gallivm->builder, "llvm.SI.load.const", base->elem_type,
+                                 args, 2, LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
+        return bitcast(bld_base, type, result);
+}
+/* Initialize arguments for the shader export intrinsic */
+static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
+                                     struct tgsi_full_declaration *d,
+                                     unsigned index,
+                                     unsigned target,
+                                     LLVMValueRef *args)
+{
+        struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
+        struct lp_build_context *uint =
+                                &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
+        struct lp_build_context *base = &bld_base->base;
+        unsigned compressed = 0;
+        unsigned chan;
+        if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
+                int cbuf = target - V_008DFC_SQ_EXP_MRT;
+                if (cbuf >= 0 && cbuf < 8) {
+                        compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
+                        if (compressed)
+                                si_shader_ctx->shader->spi_shader_col_format |=
+                                        V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
+                        else
+                                si_shader_ctx->shader->spi_shader_col_format |=
+                                        V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
+                        si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
+                }
+        }
+        if (compressed) {
+                /* Pixel shader needs to pack output values before export */
+                for (chan = 0; chan < 2; chan++ ) {
+                        LLVMValueRef *out_ptr =
+                                si_shader_ctx->radeon_bld.soa.outputs[index];
+                        args[0] = LLVMBuildLoad(base->gallivm->builder,
+                                                out_ptr[2 * chan], "");
+                        args[1] = LLVMBuildLoad(base->gallivm->builder,
+                                                out_ptr[2 * chan + 1], "");
+                        args[chan + 5] =
+                                build_intrinsic(base->gallivm->builder,
+                                                "llvm.SI.packf16",
+                                                LLVMInt32TypeInContext(base->gallivm->context),
+                                                args, 2,
+                                                LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
+                        args[chan + 7] = args[chan + 5] =
+                                LLVMBuildBitCast(base->gallivm->builder,
+                                                 args[chan + 5],
+                                                 LLVMFloatTypeInContext(base->gallivm->context),
+                                                 "");
+                }
+                /* Set COMPR flag */
+                args[4] = uint->one;
+        } else {
+                for (chan = 0; chan < 4; chan++ ) {
+                        LLVMValueRef out_ptr =
+                                si_shader_ctx->radeon_bld.soa.outputs[index][chan];
+                        /* +5 because the first output value will be
+                         * the 6th argument to the intrinsic. */
+                        args[chan + 5] = LLVMBuildLoad(base->gallivm->builder,
+                                                       out_ptr, "");
+                }
+                /* Clear COMPR flag */
+                args[4] = uint->zero;
+        }
+        /* XXX: This controls which components of the output
+         * registers actually get exported. (e.g bit 0 means export
+         * X component, bit 1 means export Y component, etc.)  I'm
+         * hard coding this to 0xf for now.  In the future, we might
+         * want to do something else. */
+        args[0] = lp_build_const_int32(base->gallivm, 0xf);
+        /* Specify whether the EXEC mask represents the valid mask */
+        args[1] = uint->zero;
+        /* Specify whether this is the last export */
+        args[2] = uint->zero;
+        /* Specify the target we are exporting */
+        args[3] = lp_build_const_int32(base->gallivm, target);
+        /* XXX: We probably need to keep track of the output
+         * values, so we know what we are passing to the next
+         * stage. */
+}
+static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
+                          unsigned index)
+{
+        struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
+        struct gallivm_state *gallivm = bld_base->base.gallivm;
+        if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
+                LLVMValueRef out_ptr = si_shader_ctx->radeon_bld.soa.outputs[index][3];
+                LLVMValueRef alpha_pass =
+                        lp_build_cmp(&bld_base->base,
+                                     si_shader_ctx->shader->key.ps.alpha_func,
+                                     LLVMBuildLoad(gallivm->builder, out_ptr, ""),
+                                     lp_build_const_float(gallivm, si_shader_ctx->shader->key.ps.alpha_ref));
+                LLVMValueRef arg =
+                        lp_build_select(&bld_base->base,
+                                        alpha_pass,
+                                        lp_build_const_float(gallivm, 1.0f),
+                                        lp_build_const_float(gallivm, -1.0f));
+                build_intrinsic(gallivm->builder,
+                                "llvm.AMDGPU.kill",
+                                LLVMVoidTypeInContext(gallivm->context),
+                                &arg, 1, 0);
+        } else {
+                build_intrinsic(gallivm->builder,
+                                "llvm.AMDGPU.kilp",
+                                LLVMVoidTypeInContext(gallivm->context),
+                                NULL, 0, 0);
+        }
+}
+static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
+                                    LLVMValueRef (*pos)[9], unsigned index)
+{
+        struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
+        struct lp_build_context *base = &bld_base->base;
+        struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
+        unsigned reg_index;
+        unsigned chan;
+        unsigned const_chan;
+        LLVMValueRef out_elts[4];
+        LLVMValueRef base_elt;
+        LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
+        LLVMValueRef const_resource = build_indexed_load(si_shader_ctx, ptr, uint->one);
+        for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
+                LLVMValueRef out_ptr = si_shader_ctx->radeon_bld.soa.outputs[index][chan];
+                out_elts[chan] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
+        }
+        for (reg_index = 0; reg_index < 2; reg_index ++) {
+                LLVMValueRef *args = pos[2 + reg_index];
+                args[5] =
+                args[6] =
+                args[7] =
+                args[8] = lp_build_const_float(base->gallivm, 0.0f);
+                /* Compute dot products of position and user clip plane vectors */
+                for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
+                        for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
+                                args[0] = const_resource;
+                                args[1] = lp_build_const_int32(base->gallivm,
+                                                               ((reg_index * 4 + chan) * 4 +
+                                                                const_chan) * 4);
+                                base_elt = build_intrinsic(base->gallivm->builder,
+                                                           "llvm.SI.load.const",
+                                                           base->elem_type,
+                                                           args, 2,
+                                                           LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
+                                args[5 + chan] =
+                                        lp_build_add(base, args[5 + chan],
+                                                     lp_build_mul(base, base_elt,
+                                                                  out_elts[const_chan]));
+                        }
+                }
+                args[0] = lp_build_const_int32(base->gallivm, 0xf);
+                args[1] = uint->zero;
+                args[2] = uint->zero;
+                args[3] = lp_build_const_int32(base->gallivm,
+                                               V_008DFC_SQ_EXP_POS + 2 + reg_index);
+                args[4] = uint->zero;
+        }
+}
+/* XXX: This is partially implemented for VS only at this point.  It is not complete */
+static void si_llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
+{
+        struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
+        struct si_shader * shader = &si_shader_ctx->shader->shader;
+        struct lp_build_context * base = &bld_base->base;
+        struct lp_build_context * uint =
+                                &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
+        struct tgsi_parse_context *parse = &si_shader_ctx->parse;
+        LLVMValueRef args[9];
+        LLVMValueRef last_args[9] = { 0 };
+        LLVMValueRef pos_args[4][9] = { { 0 } };
+        unsigned semantic_name;
+        unsigned color_count = 0;
+        unsigned param_count = 0;
+        int depth_index = -1, stencil_index = -1;
+        int i;
+        while (!tgsi_parse_end_of_tokens(parse)) {
+                struct tgsi_full_declaration *d =
+                                        &parse->FullToken.FullDeclaration;
+                unsigned target;
+                unsigned index;
+                tgsi_parse_token(parse);
+                if (parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_PROPERTY &&
+                    parse->FullToken.FullProperty.Property.PropertyName ==
+                    TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS)
+                        shader->fs_write_all = TRUE;
+                if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
+                        continue;
+                switch (d->Declaration.File) {
+                case TGSI_FILE_INPUT:
+                        i = shader->ninput++;
+                        assert(i < Elements(shader->input));
+                        shader->input[i].name = d->Semantic.Name;
+                        shader->input[i].sid = d->Semantic.Index;
+                        shader->input[i].interpolate = d->Interp.Interpolate;
+                        shader->input[i].centroid = d->Interp.Centroid;
+                        continue;
+                case TGSI_FILE_OUTPUT:
+                        i = shader->noutput++;
+                        assert(i < Elements(shader->output));
+                        shader->output[i].name = d->Semantic.Name;
+                        shader->output[i].sid = d->Semantic.Index;
+                        shader->output[i].interpolate = d->Interp.Interpolate;
+                        break;
+                default:
+                        continue;
+                }
+                semantic_name = d->Semantic.Name;
+handle_semantic:
+                for (index = d->Range.First; index <= d->Range.Last; index++) {
+                        /* Select the correct target */
+                        switch(semantic_name) {
+                        case TGSI_SEMANTIC_PSIZE:
+                                shader->vs_out_misc_write = 1;
+                                shader->vs_out_point_size = 1;
+                                target = V_008DFC_SQ_EXP_POS + 1;
+                                break;
+                        case TGSI_SEMANTIC_POSITION:
+                                if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
+                                        target = V_008DFC_SQ_EXP_POS;
+                                        break;
+                                } else {
+                                        depth_index = index;
+                                        continue;
+                                }
+                        case TGSI_SEMANTIC_STENCIL:
+                                stencil_index = index;
+                                continue;
+                        case TGSI_SEMANTIC_COLOR:
+                                if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
+                        case TGSI_SEMANTIC_BCOLOR:
+                                        target = V_008DFC_SQ_EXP_PARAM + param_count;
+                                        shader->output[i].param_offset = param_count;
+                                        param_count++;
+                                } else {
+                                        target = V_008DFC_SQ_EXP_MRT + color_count;
+                                        if (color_count == 0 &&
+                                            si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
+                                                si_alpha_test(bld_base, index);
+                                        color_count++;
+                                }
+                                break;
+                        case TGSI_SEMANTIC_CLIPDIST:
+                                shader->clip_dist_write |=
+                                        d->Declaration.UsageMask << (d->Semantic.Index << 2);
+                                target = V_008DFC_SQ_EXP_POS + 2 + d->Semantic.Index;
+                                break;
+                        case TGSI_SEMANTIC_CLIPVERTEX:
+                                si_llvm_emit_clipvertex(bld_base, pos_args, index);
+                                shader->clip_dist_write = 0xFF;
+                                continue;
+                        case TGSI_SEMANTIC_FOG:
+                        case TGSI_SEMANTIC_GENERIC:
+                                target = V_008DFC_SQ_EXP_PARAM + param_count;
+                                shader->output[i].param_offset = param_count;
+                                param_count++;
+                                break;
+                        default:
+                                target = 0;
+                                fprintf(stderr,
+                                        "Warning: SI unhandled output type:%d\n",
+                                        semantic_name);
+                        }
+                        si_llvm_init_export_args(bld_base, d, index, target, args);
+                        if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
+                            target >= V_008DFC_SQ_EXP_POS &&
+                            target <= (V_008DFC_SQ_EXP_POS + 3)) {
+                                memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
+                                       args, sizeof(args));
+                        } else if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT &&
+                                   semantic_name == TGSI_SEMANTIC_COLOR) {
+                                if (last_args[0]) {
+                                        lp_build_intrinsic(base->gallivm->builder,
+                                                           "llvm.SI.export",
+                                                           LLVMVoidTypeInContext(base->gallivm->context),
+                                                           last_args, 9);
+                                }
+                                memcpy(last_args, args, sizeof(args));
+                        } else {
+                                lp_build_intrinsic(base->gallivm->builder,
+                                                   "llvm.SI.export",
+                                                   LLVMVoidTypeInContext(base->gallivm->context),
+                                                   args, 9);
+                        }
+                }
+                if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
+                        semantic_name = TGSI_SEMANTIC_GENERIC;
+                        goto handle_semantic;
+                }
+        }
+        if (depth_index >= 0 || stencil_index >= 0) {
+                LLVMValueRef out_ptr;
+                unsigned mask = 0;
+                /* Specify the target we are exporting */
+                args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
+                if (depth_index >= 0) {
+                        out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
+                        args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
+                        mask |= 0x1;
+                        if (stencil_index < 0) {
+                                args[6] =
+                                args[7] =
+                                args[8] = args[5];
+                        }
+                }
+                if (stencil_index >= 0) {
+                        out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
+                        args[7] =
+                        args[8] =
+                        args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
+                        /* Only setting the stencil component bit (0x2) here
+                         * breaks some stencil piglit tests
+                         */
+                        mask |= 0x3;
+                        if (depth_index < 0)
+                                args[5] = args[6];
+                }
+                /* Specify which components to enable */
+                args[0] = lp_build_const_int32(base->gallivm, mask);
+                args[1] =
+                args[2] =
+                args[4] = uint->zero;
+                if (last_args[0])
+                        lp_build_intrinsic(base->gallivm->builder,
+                                           "llvm.SI.export",
+                                           LLVMVoidTypeInContext(base->gallivm->context),
+                                           args, 9);
+                else
+                        memcpy(last_args, args, sizeof(args));
+        }
+        if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
+                unsigned pos_idx = 0;
+                for (i = 0; i < 4; i++)
+                        if (pos_args[i][0])
+                                shader->nr_pos_exports++;
+                for (i = 0; i < 4; i++) {
+                        if (!pos_args[i][0])
+                                continue;
+                        /* Specify the target we are exporting */
+                        pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
+                        if (pos_idx == shader->nr_pos_exports)
+                                /* Specify that this is the last export */
+                                pos_args[i][2] = uint->one;
+                        lp_build_intrinsic(base->gallivm->builder,
+                                           "llvm.SI.export",
+                                           LLVMVoidTypeInContext(base->gallivm->context),
+                                           pos_args[i], 9);
+                }
+        } else {
+                if (!last_args[0]) {
+                        /* Specify which components to enable */
+                        last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
+                        /* Specify the target we are exporting */
+                        last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
+                        /* Set COMPR flag to zero to export data as 32-bit */
+                        last_args[4] = uint->zero;
+                        /* dummy bits */
+                        last_args[5]= uint->zero;
+                        last_args[6]= uint->zero;
+                        last_args[7]= uint->zero;
+                        last_args[8]= uint->zero;
+                        si_shader_ctx->shader->spi_shader_col_format |=
+                                V_028714_SPI_SHADER_32_ABGR;
+                        si_shader_ctx->shader->cb_shader_mask |= S_02823C_OUTPUT0_ENABLE(0xf);
+                }
+                /* Specify whether the EXEC mask represents the valid mask */
+                last_args[1] = uint->one;
+                if (shader->fs_write_all && shader->nr_cbufs > 1) {
+                        int i;
+                        /* Specify that this is not yet the last export */
+                        last_args[2] = lp_build_const_int32(base->gallivm, 0);
+                        for (i = 1; i < shader->nr_cbufs; i++) {
+                                /* Specify the target we are exporting */
+                                last_args[3] = lp_build_const_int32(base->gallivm,
+                                                                    V_008DFC_SQ_EXP_MRT + i);
+                                lp_build_intrinsic(base->gallivm->builder,
+                                                   "llvm.SI.export",
+                                                   LLVMVoidTypeInContext(base->gallivm->context),
+                                                   last_args, 9);
+                                si_shader_ctx->shader->spi_shader_col_format |=
+                                        si_shader_ctx->shader->spi_shader_col_format << 4;
+                                si_shader_ctx->shader->cb_shader_mask |=
+                                        si_shader_ctx->shader->cb_shader_mask << 4;
+                        }
+                        last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
+                }
+                /* Specify that this is the last export */
+                last_args[2] = lp_build_const_int32(base->gallivm, 1);
+                lp_build_intrinsic(base->gallivm->builder,
+                                   "llvm.SI.export",
+                                   LLVMVoidTypeInContext(base->gallivm->context),
+                                   last_args, 9);
+        }
+/* XXX: Look up what this function does */
+/*              ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);*/
+}
+static void tex_fetch_args(
+        struct lp_build_tgsi_context * bld_base,
+        struct lp_build_emit_data * emit_data)
+{
+        struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
+        struct gallivm_state *gallivm = bld_base->base.gallivm;
+        const struct tgsi_full_instruction * inst = emit_data->inst;
+        unsigned opcode = inst->Instruction.Opcode;
+        unsigned target = inst->Texture.Texture;
+        unsigned sampler_src;
+        LLVMValueRef coords[4];
+        LLVMValueRef address[16];
+        int ref_pos;
+        unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
+        unsigned count = 0;
+        unsigned chan;
+        /* Fetch and project texture coordinates */
+        coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
+        for (chan = 0; chan < 3; chan++ ) {
+                coords[chan] = lp_build_emit_fetch(bld_base,
+                                                   emit_data->inst, 0,
+                                                   chan);
+                if (opcode == TGSI_OPCODE_TXP)
+                        coords[chan] = lp_build_emit_llvm_binary(bld_base,
+                                                                 TGSI_OPCODE_DIV,
+                                                                 coords[chan],
+                                                                 coords[3]);
+        }
+        if (opcode == TGSI_OPCODE_TXP)
+                coords[3] = bld_base->base.one;
+        /* Pack LOD bias value */
+        if (opcode == TGSI_OPCODE_TXB)
+                address[count++] = coords[3];
+        if (target == TGSI_TEXTURE_CUBE || target == TGSI_TEXTURE_SHADOWCUBE)
+                radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
+        /* Pack depth comparison value */
+        switch (target) {
+        case TGSI_TEXTURE_SHADOW1D:
+        case TGSI_TEXTURE_SHADOW1D_ARRAY:
+        case TGSI_TEXTURE_SHADOW2D:
+        case TGSI_TEXTURE_SHADOWRECT:
+        case TGSI_TEXTURE_SHADOWCUBE:
+        case TGSI_TEXTURE_SHADOW2D_ARRAY:
+                assert(ref_pos >= 0);
+                address[count++] = coords[ref_pos];
+                break;
+        case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
+                address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
+        }
+        /* Pack user derivatives */
+        if (opcode == TGSI_OPCODE_TXD) {
+                for (chan = 0; chan < 2; chan++) {
+                        address[count++] = lp_build_emit_fetch(bld_base, inst, 1, chan);
+                        if (num_coords > 1)
+                                address[count++] = lp_build_emit_fetch(bld_base, inst, 2, chan);
+                }
+        }
+        /* Pack texture coordinates */
+        address[count++] = coords[0];
+        if (num_coords > 1)
+                address[count++] = coords[1];
+        if (num_coords > 2)
+                address[count++] = coords[2];
+        /* Pack array slice */
+        switch (target) {
+        case TGSI_TEXTURE_1D_ARRAY:
+                address[count++] = coords[1];
+        }
+        switch (target) {
+        case TGSI_TEXTURE_2D_ARRAY:
+        case TGSI_TEXTURE_2D_ARRAY_MSAA:
+        case TGSI_TEXTURE_SHADOW2D_ARRAY:
+                address[count++] = coords[2];
+        }
+        switch (target) {
+        case TGSI_TEXTURE_CUBE_ARRAY:
+        case TGSI_TEXTURE_SHADOW1D_ARRAY:
+        case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
+                address[count++] = coords[3];
+        }
+        /* Pack LOD */
+        if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
+                address[count++] = coords[3];
+        if (count > 16) {
+                assert(!"Cannot handle more than 16 texture address parameters");
+                count = 16;
+        }
+        for (chan = 0; chan < count; chan++ ) {
+                address[chan] = LLVMBuildBitCast(gallivm->builder,
+                                                 address[chan],
+                                                 LLVMInt32TypeInContext(gallivm->context),
+                                                 "");
+        }
+        sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
+        /* Resource */
+        emit_data->args[1] = si_shader_ctx->resources[emit_data->inst->Src[sampler_src].Register.Index];
+        if (opcode == TGSI_OPCODE_TXF) {
+                /* add tex offsets */
+                if (inst->Texture.NumOffsets) {
+                        struct lp_build_context *uint_bld = &bld_base->uint_bld;
+                        struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
+                        const struct tgsi_texture_offset * off = inst->TexOffsets;
+                        assert(inst->Texture.NumOffsets == 1);
+                        address[0] =
+                                lp_build_add(uint_bld, address[0],
+                                             bld->immediates[off->Index][off->SwizzleX]);
+                        if (num_coords > 1)
+                                address[1] =
+                                        lp_build_add(uint_bld, address[1],
+                                                     bld->immediates[off->Index][off->SwizzleY]);
+                        if (num_coords > 2)
+                                address[2] =
+                                        lp_build_add(uint_bld, address[2],
+                                                     bld->immediates[off->Index][off->SwizzleZ]);
+                }
+                emit_data->dst_type = LLVMVectorType(
+                        LLVMInt32TypeInContext(bld_base->base.gallivm->context),
+);
+                emit_data->arg_count = 3;
+        } else {
+                /* Sampler */
+                emit_data->args[2] = si_shader_ctx->samplers[emit_data->inst->Src[sampler_src].Register.Index];
+                emit_data->dst_type = LLVMVectorType(
+                        LLVMFloatTypeInContext(bld_base->base.gallivm->context),
+);
+                emit_data->arg_count = 4;
+        }
+        /* Dimensions */
+        emit_data->args[emit_data->arg_count - 1] =
+                lp_build_const_int32(bld_base->base.gallivm, target);
+        /* Pad to power of two vector */
+        while (count < util_next_power_of_two(count))
+                address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
+        emit_data->args[0] = lp_build_gather_values(gallivm, address, count);
+}
+static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
+                                struct lp_build_tgsi_context * bld_base,
+                                struct lp_build_emit_data * emit_data)
+{
+        struct lp_build_context * base = &bld_base->base;
+        char intr_name[23];
+        sprintf(intr_name, "%sv%ui32", action->intr_name,
+                LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
+        emit_data->output[emit_data->chan] = build_intrinsic(
+                base->gallivm->builder, intr_name, emit_data->dst_type,
+                emit_data->args, emit_data->arg_count,
+                LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
+}
+static void txq_fetch_args(
+        struct lp_build_tgsi_context * bld_base,
+        struct lp_build_emit_data * emit_data)
+{
+        struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
+        const struct tgsi_full_instruction *inst = emit_data->inst;
+        /* Mip level */
+        emit_data->args[0] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
+        /* Resource */
+        emit_data->args[1] = si_shader_ctx->resources[inst->Src[1].Register.Index];
+        /* Dimensions */
+        emit_data->args[2] = lp_build_const_int32(bld_base->base.gallivm,
+                                                  inst->Texture.Texture);
+        emit_data->arg_count = 3;
+        emit_data->dst_type = LLVMVectorType(
+                LLVMInt32TypeInContext(bld_base->base.gallivm->context),
+);
+}
+#if HAVE_LLVM >= 0x0304
+static void si_llvm_emit_ddxy(
+        const struct lp_build_tgsi_action * action,
+        struct lp_build_tgsi_context * bld_base,
+        struct lp_build_emit_data * emit_data)
+{
+        struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
+        struct gallivm_state *gallivm = bld_base->base.gallivm;
+        struct lp_build_context * base = &bld_base->base;
+        const struct tgsi_full_instruction *inst = emit_data->inst;
+        unsigned opcode = inst->Instruction.Opcode;
+        LLVMValueRef indices[2];
+        LLVMValueRef store_ptr, load_ptr0, load_ptr1;
+        LLVMValueRef tl, trbl, result[4];
+        LLVMTypeRef i32;
+        unsigned swizzle[4];
+        unsigned c;
+        i32 = LLVMInt32TypeInContext(gallivm->context);
+        indices[0] = bld_base->uint_bld.zero;
+        indices[1] = build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
+                                     NULL, 0, LLVMReadNoneAttribute);
+        store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
+                                 indices, 2, "");
+        indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
+                                  lp_build_const_int32(gallivm, 0xfffffffc), "");
+        load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
+                                 indices, 2, "");
+        indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
+                                  lp_build_const_int32(gallivm,
+                                                       opcode == TGSI_OPCODE_DDX ? 1 : 2),
+                                  "");
+        load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
+                                 indices, 2, "");
+        for (c = 0; c < 4; ++c) {
+                unsigned i;
+                swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
+                for (i = 0; i < c; ++i) {
+                        if (swizzle[i] == swizzle[c]) {
+                                result[c] = result[i];
+                                break;
+                        }
+                }
+                if (i != c)
+                        continue;
+                LLVMBuildStore(gallivm->builder,
+                               LLVMBuildBitCast(gallivm->builder,
+                                                lp_build_emit_fetch(bld_base, inst, 0, c),
+                                                i32, ""),
+                               store_ptr);
+                tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
+                tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
+                trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
+                trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
+                result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
+        }
+        emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
+}
+#endif /* HAVE_LLVM >= 0x0304 */
+static const struct lp_build_tgsi_action tex_action = {
+        .fetch_args = tex_fetch_args,
+        .emit = build_tex_intrinsic,
+        .intr_name = "llvm.SI.sample."
+};
+static const struct lp_build_tgsi_action txb_action = {
+        .fetch_args = tex_fetch_args,
+        .emit = build_tex_intrinsic,
+        .intr_name = "llvm.SI.sampleb."
+};
+#if HAVE_LLVM >= 0x0304
+static const struct lp_build_tgsi_action txd_action = {
+        .fetch_args = tex_fetch_args,
+        .emit = build_tex_intrinsic,
+        .intr_name = "llvm.SI.sampled."
+};
+#endif
+static const struct lp_build_tgsi_action txf_action = {
+        .fetch_args = tex_fetch_args,
+        .emit = build_tex_intrinsic,
+        .intr_name = "llvm.SI.imageload."
+};
+static const struct lp_build_tgsi_action txl_action = {
+        .fetch_args = tex_fetch_args,
+        .emit = build_tex_intrinsic,
+        .intr_name = "llvm.SI.samplel."
+};
+static const struct lp_build_tgsi_action txq_action = {
+        .fetch_args = txq_fetch_args,
+        .emit = build_tgsi_intrinsic_nomem,
+        .intr_name = "llvm.SI.resinfo"
+};
+static void create_meta_data(struct si_shader_context *si_shader_ctx)
+{
+        struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
+        LLVMValueRef args[3];
+        args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
+        args[1] = 0;
+        args[2] = lp_build_const_int32(gallivm, 1);
+        si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
+}
+static void create_function(struct si_shader_context *si_shader_ctx)
+{
+        struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
+        struct gallivm_state *gallivm = bld_base->base.gallivm;
+        LLVMTypeRef params[20], f32, i8, i32, v2i32, v3i32;
+        unsigned i;
+        i8 = LLVMInt8TypeInContext(gallivm->context);
+        i32 = LLVMInt32TypeInContext(gallivm->context);
+        f32 = LLVMFloatTypeInContext(gallivm->context);
+        v2i32 = LLVMVectorType(i32, 2);
+        v3i32 = LLVMVectorType(i32, 3);
+        params[SI_PARAM_CONST] = LLVMPointerType(LLVMVectorType(i8, 16), CONST_ADDR_SPACE);
+        params[SI_PARAM_SAMPLER] = params[SI_PARAM_CONST];
+        params[SI_PARAM_RESOURCE] = LLVMPointerType(LLVMVectorType(i8, 32), CONST_ADDR_SPACE);
+        if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
+                params[SI_PARAM_VERTEX_BUFFER] = params[SI_PARAM_SAMPLER];
+                params[SI_PARAM_START_INSTANCE] = i32;
+                params[SI_PARAM_VERTEX_ID] = i32;
+                params[SI_PARAM_DUMMY_0] = i32;
+                params[SI_PARAM_DUMMY_1] = i32;
+                params[SI_PARAM_INSTANCE_ID] = i32;
+                radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, 9);
+        } else {
+                params[SI_PARAM_PRIM_MASK] = i32;
+                params[SI_PARAM_PERSP_SAMPLE] = v2i32;
+                params[SI_PARAM_PERSP_CENTER] = v2i32;
+                params[SI_PARAM_PERSP_CENTROID] = v2i32;
+                params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
+                params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
+                params[SI_PARAM_LINEAR_CENTER] = v2i32;
+                params[SI_PARAM_LINEAR_CENTROID] = v2i32;
+                params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
+                params[SI_PARAM_POS_X_FLOAT] = f32;
+                params[SI_PARAM_POS_Y_FLOAT] = f32;
+                params[SI_PARAM_POS_Z_FLOAT] = f32;
+                params[SI_PARAM_POS_W_FLOAT] = f32;
+                params[SI_PARAM_FRONT_FACE] = f32;
+                params[SI_PARAM_ANCILLARY] = f32;
+                params[SI_PARAM_SAMPLE_COVERAGE] = f32;
+                params[SI_PARAM_POS_FIXED_PT] = f32;
+                radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, 20);
+        }
+        radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
+        for (i = SI_PARAM_CONST; i <= SI_PARAM_VERTEX_BUFFER; ++i) {
+                LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
+                LLVMAddAttribute(P, LLVMInRegAttribute);
+        }
+        if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
+                LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
+                                              SI_PARAM_START_INSTANCE);
+                LLVMAddAttribute(P, LLVMInRegAttribute);
+        }
+#if HAVE_LLVM >= 0x0304
+        if (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
+            bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0)
+                si_shader_ctx->ddxy_lds =
+                        LLVMAddGlobalInAddressSpace(gallivm->module,
+                                                    LLVMArrayType(i32, 64),
+                                                    "ddxy_lds",
+                                                    LOCAL_ADDR_SPACE);
+#endif
+}
+static void preload_constants(struct si_shader_context *si_shader_ctx)
+{
+        struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
+        struct gallivm_state * gallivm = bld_base->base.gallivm;
+        const struct tgsi_shader_info * info = bld_base->info;
+        unsigned i, num_const = info->file_max[TGSI_FILE_CONSTANT] + 1;
+        LLVMValueRef ptr;
+        if (num_const == 0)
+                return;
+        /* Allocate space for the constant values */
+        si_shader_ctx->constants = CALLOC(num_const * 4, sizeof(LLVMValueRef));
+        /* Load the resource descriptor */
+        ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
+        si_shader_ctx->const_resource = build_indexed_load(si_shader_ctx, ptr, bld_base->uint_bld.zero);
+        /* Load the constants, we rely on the code sinking to do the rest */
+        for (i = 0; i < num_const * 4; ++i) {
+                LLVMValueRef args[2] = {
+                        si_shader_ctx->const_resource,
+                        lp_build_const_int32(gallivm, i * 4)
+                };
+                si_shader_ctx->constants[i] = build_intrinsic(gallivm->builder, "llvm.SI.load.const",
+                        bld_base->base.elem_type, args, 2, LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
+        }
+}
+static void preload_samplers(struct si_shader_context *si_shader_ctx)
+{
+        struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
+        struct gallivm_state * gallivm = bld_base->base.gallivm;
+        const struct tgsi_shader_info * info = bld_base->info;
+        unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
+        LLVMValueRef res_ptr, samp_ptr;
+        LLVMValueRef offset;
+        if (num_samplers == 0)
+                return;
+        /* Allocate space for the values */
+        si_shader_ctx->resources = CALLOC(num_samplers, sizeof(LLVMValueRef));
+        si_shader_ctx->samplers = CALLOC(num_samplers, sizeof(LLVMValueRef));
+        res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
+        samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
+        /* Load the resources and samplers, we rely on the code sinking to do the rest */
+        for (i = 0; i < num_samplers; ++i) {
+                /* Resource */
+                offset = lp_build_const_int32(gallivm, i);
+                si_shader_ctx->resources[i] = build_indexed_load(si_shader_ctx, res_ptr, offset);
+                /* Sampler */
+                offset = lp_build_const_int32(gallivm, i);
+                si_shader_ctx->samplers[i] = build_indexed_load(si_shader_ctx, samp_ptr, offset);
+        }
+}
+int si_compile_llvm(struct r600_context *rctx, struct si_pipe_shader *shader,
+                                                        LLVMModuleRef mod)
+{
+        unsigned i;
+        uint32_t *ptr;
+        bool dump;
+        struct radeon_llvm_binary binary;
+        dump = debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE);
+        memset(&binary, 0, sizeof(binary));
+        radeon_llvm_compile(mod, &binary,
+                r600_get_llvm_processor_name(rctx->screen->family), dump);
+        if (dump) {
+                fprintf(stderr, "SI CODE:\n");
+                for (i = 0; i < binary.code_size; i+=4 ) {
+                        fprintf(stderr, "%02x%02x%02x%02x\n", binary.code[i + 3],
+                                binary.code[i + 2], binary.code[i + 1],
+                                binary.code[i]);
+                }
+        }
+        /* XXX: We may be able to emit some of these values directly rather than
+         * extracting fields to be emitted later.
+         */
+        for (i = 0; i < binary.config_size; i+= 8) {
+                unsigned reg = util_le32_to_cpu(*(uint32_t*)(binary.config + i));
+                unsigned value = util_le32_to_cpu(*(uint32_t*)(binary.config + i + 4));
+                switch (reg) {
+                case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
+                case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
+                case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
+                case R_00B848_COMPUTE_PGM_RSRC1:
+                        shader->num_sgprs = (G_00B028_SGPRS(value) + 1) * 8;
+                        shader->num_vgprs = (G_00B028_VGPRS(value) + 1) * 4;
+                        break;
+                case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
+                        shader->lds_size = G_00B02C_EXTRA_LDS_SIZE(value);
+                        break;
+                case R_00B84C_COMPUTE_PGM_RSRC2:
+                        shader->lds_size = G_00B84C_LDS_SIZE(value);
+                        break;
+                case R_0286CC_SPI_PS_INPUT_ENA:
+                        shader->spi_ps_input_ena = value;
+                        break;
+                default:
+                        fprintf(stderr, "Warning: Compiler emitted unknown "
+                                "config register: 0x%x\n", reg);
+                        break;
+                }
+        }
+        /* copy new shader */
+        si_resource_reference(&shader->bo, NULL);
+        shader->bo = si_resource_create_custom(rctx->context.screen, PIPE_USAGE_IMMUTABLE,
+                                               binary.code_size);
+        if (shader->bo == NULL) {
+                return -ENOMEM;
+        }
+        ptr = (uint32_t*)rctx->ws->buffer_map(shader->bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
+        if (0 /*R600_BIG_ENDIAN*/) {
+                for (i = 0; i < binary.code_size / 4; ++i) {
+                        ptr[i] = util_bswap32(*(uint32_t*)(binary.code + i*4));
+                }
+        } else {
+                memcpy(ptr, binary.code, binary.code_size);
+        }
+        rctx->ws->buffer_unmap(shader->bo->cs_buf);
+        free(binary.code);
+        free(binary.config);
+        return 0;
+}
+int si_pipe_shader_create(
+        struct pipe_context *ctx,
+        struct si_pipe_shader *shader)
+{
+        struct r600_context *rctx = (struct r600_context*)ctx;
+        struct si_pipe_shader_selector *sel = shader->selector;
+        struct si_shader_context si_shader_ctx;
+        struct tgsi_shader_info shader_info;
+        struct lp_build_tgsi_context * bld_base;
+        LLVMModuleRef mod;
+        bool dump;
+        int r = 0;
+        dump = debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE);
+        assert(shader->shader.noutput == 0);
+        assert(shader->shader.ninterp == 0);
+        assert(shader->shader.ninput == 0);
+        memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
+        radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
+        bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
+        tgsi_scan_shader(sel->tokens, &shader_info);
+        shader->shader.uses_kill = shader_info.uses_kill;
+        shader->shader.uses_instanceid = shader_info.uses_instanceid;
+        bld_base->info = &shader_info;
+        bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
+        bld_base->emit_epilogue = si_llvm_emit_epilogue;
+        bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
+        bld_base->op_actions[TGSI_OPCODE_TXB] = txb_action;
+#if HAVE_LLVM >= 0x0304
+        bld_base->op_actions[TGSI_OPCODE_TXD] = txd_action;
+#endif
+        bld_base->op_actions[TGSI_OPCODE_TXF] = txf_action;
+        bld_base->op_actions[TGSI_OPCODE_TXL] = txl_action;
+        bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
+        bld_base->op_actions[TGSI_OPCODE_TXQ] = txq_action;
+#if HAVE_LLVM >= 0x0304
+        bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
+        bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
+#endif
+        si_shader_ctx.radeon_bld.load_input = declare_input;
+        si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
+        si_shader_ctx.tokens = sel->tokens;
+        tgsi_parse_init(&si_shader_ctx.parse, si_shader_ctx.tokens);
+        si_shader_ctx.shader = shader;
+        si_shader_ctx.type = si_shader_ctx.parse.FullHeader.Processor.Processor;
+        create_meta_data(&si_shader_ctx);
+        create_function(&si_shader_ctx);
+        preload_constants(&si_shader_ctx);
+        preload_samplers(&si_shader_ctx);
+        shader->shader.nr_cbufs = rctx->framebuffer.nr_cbufs;
+        /* Dump TGSI code before doing TGSI->LLVM conversion in case the
+         * conversion fails. */
+        if (dump) {
+                tgsi_dump(sel->tokens, 0);
+        }
+        if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
+                fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
+                FREE(si_shader_ctx.constants);
+                FREE(si_shader_ctx.resources);
+                FREE(si_shader_ctx.samplers);
+                return -EINVAL;
+        }
+        radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
+        mod = bld_base->base.gallivm->module;
+        r = si_compile_llvm(rctx, shader, mod);
+        radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
+        tgsi_parse_free(&si_shader_ctx.parse);
+        FREE(si_shader_ctx.constants);
+        FREE(si_shader_ctx.resources);
+        FREE(si_shader_ctx.samplers);
+        return r;
+}
+void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader)
+{
+        si_resource_reference(&shader->bo, NULL);
+}

 /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/radeonsi_shader.h
 ,0 → 1,158
+/*
+ * Copyright 2012 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Tom Stellard <thomas.stellard@amd.com>
+ *      Michel Dänzer <michel.daenzer@amd.com>
+ *      Christian König <christian.koenig@amd.com>
+ */
+#ifndef RADEONSI_SHADER_H
+#define RADEONSI_SHADER_H
+#include <llvm-c/Core.h> /* LLVMModuleRef */
+#define SI_SGPR_CONST           0
+#define SI_SGPR_SAMPLER         2
+#define SI_SGPR_RESOURCE        4
+#define SI_SGPR_VERTEX_BUFFER   6
+#define SI_SGPR_START_INSTANCE  8
+#define SI_VS_NUM_USER_SGPR     9
+#define SI_PS_NUM_USER_SGPR     6
+/* LLVM function parameter indices */
+#define SI_PARAM_CONST          0
+#define SI_PARAM_SAMPLER        1
+#define SI_PARAM_RESOURCE       2
+/* VS only parameters */
+#define SI_PARAM_VERTEX_BUFFER  3
+#define SI_PARAM_START_INSTANCE 4
+#define SI_PARAM_VERTEX_ID      5
+#define SI_PARAM_DUMMY_0        6
+#define SI_PARAM_DUMMY_1        7
+#define SI_PARAM_INSTANCE_ID    8
+/* PS only parameters */
+#define SI_PARAM_PRIM_MASK              3
+#define SI_PARAM_PERSP_SAMPLE           4
+#define SI_PARAM_PERSP_CENTER           5
+#define SI_PARAM_PERSP_CENTROID         6
+#define SI_PARAM_PERSP_PULL_MODEL       7
+#define SI_PARAM_LINEAR_SAMPLE          8
+#define SI_PARAM_LINEAR_CENTER          9
+#define SI_PARAM_LINEAR_CENTROID        10
+#define SI_PARAM_LINE_STIPPLE_TEX       11
+#define SI_PARAM_POS_X_FLOAT            12
+#define SI_PARAM_POS_Y_FLOAT            13
+#define SI_PARAM_POS_Z_FLOAT            14
+#define SI_PARAM_POS_W_FLOAT            15
+#define SI_PARAM_FRONT_FACE             16
+#define SI_PARAM_ANCILLARY              17
+#define SI_PARAM_SAMPLE_COVERAGE        18
+#define SI_PARAM_POS_FIXED_PT           19
+struct si_shader_io {
+        unsigned                name;
+        int                     sid;
+        unsigned                param_offset;
+        unsigned                interpolate;
+        bool                    centroid;
+};
+struct si_pipe_shader;
+struct si_pipe_shader_selector {
+        struct si_pipe_shader *current;
+        struct tgsi_token       *tokens;
+        struct pipe_stream_output_info  so;
+        unsigned        num_shaders;
+        /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
+        unsigned        type;
+        /* 1 when the shader contains
+         * TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS, otherwise it's 0.
+         * Used to determine whether we need to include nr_cbufs in the key */
+        unsigned        fs_write_all;
+};
+struct si_shader {
+        unsigned                ninput;
+        struct si_shader_io     input[40];
+        unsigned                noutput;
+        struct si_shader_io     output[40];
+        unsigned                ninterp;
+        bool                    uses_kill;
+        bool                    uses_instanceid;
+        bool                    fs_write_all;
+        bool                    vs_out_misc_write;
+        bool                    vs_out_point_size;
+        unsigned                nr_cbufs;
+        unsigned                nr_pos_exports;
+        unsigned                clip_dist_write;
+};
+union si_shader_key {
+        struct {
+                unsigned        export_16bpc:8;
+                unsigned        nr_cbufs:4;
+                unsigned        color_two_side:1;
+                unsigned        alpha_func:3;
+                unsigned        flatshade:1;
+                float           alpha_ref;
+        } ps;
+        struct {
+                unsigned        instance_divisors[PIPE_MAX_ATTRIBS];
+        } vs;
+};
+struct si_pipe_shader {
+        struct si_pipe_shader_selector  *selector;
+        struct si_pipe_shader           *next_variant;
+        struct si_shader                shader;
+        struct si_pm4_state             *pm4;
+        struct si_resource              *bo;
+        unsigned                        num_sgprs;
+        unsigned                        num_vgprs;
+        unsigned                        lds_size;
+        unsigned                        spi_ps_input_ena;
+        unsigned                        spi_shader_col_format;
+        unsigned                        cb_shader_mask;
+        unsigned                        sprite_coord_enable;
+        unsigned                        so_strides[4];
+        union si_shader_key             key;
+};
+/* radeonsi_shader.c */
+int si_pipe_shader_create(struct pipe_context *ctx, struct si_pipe_shader *shader);
+int si_pipe_shader_create(struct pipe_context *ctx, struct si_pipe_shader *shader);
+int si_compile_llvm(struct r600_context *rctx, struct si_pipe_shader *shader,
+                                                        LLVMModuleRef mod);
+void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader);
+#endif

 /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/radeonsi_uvd.c
 ,0 → 1,161
+/**************************************************************************
+ *
+ * Copyright 2011 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **************************************************************************/
+/*
+ * Authors:
+ *      Christian König <christian.koenig@amd.com>
+ *
+ */
+#include <sys/types.h>
+#include <assert.h>
+#include <errno.h>
+#include <unistd.h>
+#include "pipe/p_video_decoder.h"
+#include "util/u_memory.h"
+#include "util/u_video.h"
+#include "vl/vl_defines.h"
+#include "vl/vl_mpeg12_decoder.h"
+#include "radeonsi_pipe.h"
+#include "radeon/radeon_uvd.h"
+#include "sid.h"
+/**
+ * creates an video buffer with an UVD compatible memory layout
+ */
+struct pipe_video_buffer *radeonsi_video_buffer_create(struct pipe_context *pipe,
+                                                       const struct pipe_video_buffer *tmpl)
+{
+        struct r600_context *ctx = (struct r600_context *)pipe;
+        struct r600_resource_texture *resources[VL_NUM_COMPONENTS] = {};
+        struct radeon_surface *surfaces[VL_NUM_COMPONENTS] = {};
+        struct pb_buffer **pbs[VL_NUM_COMPONENTS] = {};
+        const enum pipe_format *resource_formats;
+        struct pipe_video_buffer template;
+        struct pipe_resource templ;
+        unsigned i, array_size;
+        assert(pipe);
+        /* first create the needed resources as "normal" textures */
+        resource_formats = vl_video_buffer_formats(pipe->screen, tmpl->buffer_format);
+        if (!resource_formats)
+                return NULL;
+        array_size = tmpl->interlaced ? 2 : 1;
+        template = *tmpl;
+        template.width = align(tmpl->width, VL_MACROBLOCK_WIDTH);
+        template.height = align(tmpl->height / array_size, VL_MACROBLOCK_HEIGHT);
+        vl_video_buffer_template(&templ, &template, resource_formats[0], 1, array_size, PIPE_USAGE_STATIC, 0);
+        /* TODO: Setting the transfer flag is only a workaround till we get tiling working */
+        templ.flags = R600_RESOURCE_FLAG_TRANSFER;
+        resources[0] = (struct r600_resource_texture *)
+                pipe->screen->resource_create(pipe->screen, &templ);
+        if (!resources[0])
+                goto error;
+        if (resource_formats[1] != PIPE_FORMAT_NONE) {
+                vl_video_buffer_template(&templ, &template, resource_formats[1], 1, array_size, PIPE_USAGE_STATIC, 1);
+                templ.flags = R600_RESOURCE_FLAG_TRANSFER;
+                resources[1] = (struct r600_resource_texture *)
+                        pipe->screen->resource_create(pipe->screen, &templ);
+                if (!resources[1])
+                        goto error;
+        }
+        if (resource_formats[2] != PIPE_FORMAT_NONE) {
+                vl_video_buffer_template(&templ, &template, resource_formats[2], 1, array_size, PIPE_USAGE_STATIC, 2);
+                templ.flags = R600_RESOURCE_FLAG_TRANSFER;
+                resources[2] = (struct r600_resource_texture *)
+                        pipe->screen->resource_create(pipe->screen, &templ);
+                if (!resources[2])
+                        goto error;
+        }
+        for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
+                if (!resources[i])
+                        continue;
+                surfaces[i] = & resources[i]->surface;
+                pbs[i] = &resources[i]->resource.buf;
+        }
+        ruvd_join_surfaces(ctx->ws, templ.bind, pbs, surfaces);
+        for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
+                if (!resources[i])
+                        continue;
+                /* recreate the CS handle */
+                resources[i]->resource.cs_buf = ctx->ws->buffer_get_cs_handle(
+                        resources[i]->resource.buf);
+        }
+        template.height *= array_size;
+        return vl_video_buffer_create_ex2(pipe, &template, (struct pipe_resource **)resources);
+error:
+        for (i = 0; i < VL_NUM_COMPONENTS; ++i)
+                pipe_resource_reference((struct pipe_resource **)&resources[i], NULL);
+        return NULL;
+}
+/* set the decoding target buffer offsets */
+static struct radeon_winsys_cs_handle* radeonsi_uvd_set_dtb(struct ruvd_msg *msg, struct vl_video_buffer *buf)
+{
+        struct r600_resource_texture *luma = (struct r600_resource_texture *)buf->resources[0];
+        struct r600_resource_texture *chroma = (struct r600_resource_texture *)buf->resources[1];
+        msg->body.decode.dt_field_mode = buf->base.interlaced;
+        ruvd_set_dt_surfaces(msg, &luma->surface, &chroma->surface);
+        return luma->resource.cs_buf;
+}
+/**
+ * creates an UVD compatible decoder
+ */
+struct pipe_video_decoder *radeonsi_uvd_create_decoder(struct pipe_context *context,
+                                                       enum pipe_video_profile profile,
+                                                       enum pipe_video_entrypoint entrypoint,
+                                                       enum pipe_video_chroma_format chroma_format,
+                                                       unsigned width, unsigned height,
+                                                       unsigned max_references, bool expect_chunked_decode)
+{
+        struct r600_context *ctx = (struct r600_context *)context;
+        return ruvd_create_decoder(context, profile, entrypoint, chroma_format,
+                                   width, height, max_references, expect_chunked_decode,
+                                   ctx->ws, radeonsi_uvd_set_dtb);
+}

 /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/si_commands.c
 ,0 → 1,80
+/*
+ * Copyright 2012 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Christian König <christian.koenig@amd.com>
+ */
+#include "radeonsi_pipe.h"
+#include "radeonsi_pm4.h"
+#include "sid.h"
+void si_cmd_context_control(struct si_pm4_state *pm4)
+{
+        si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
+        si_pm4_cmd_add(pm4, 0x80000000);
+        si_pm4_cmd_add(pm4, 0x80000000);
+        si_pm4_cmd_end(pm4, false);
+}
+void si_cmd_draw_index_2(struct si_pm4_state *pm4, uint32_t max_size,
+                         uint64_t index_base, uint32_t index_count,
+                         uint32_t initiator, bool predicate)
+{
+        si_pm4_cmd_begin(pm4, PKT3_DRAW_INDEX_2);
+        si_pm4_cmd_add(pm4, max_size);
+        si_pm4_cmd_add(pm4, index_base);
+        si_pm4_cmd_add(pm4, (index_base >> 32UL) & 0xFF);
+        si_pm4_cmd_add(pm4, index_count);
+        si_pm4_cmd_add(pm4, initiator);
+        si_pm4_cmd_end(pm4, predicate);
+}
+void si_cmd_draw_index_auto(struct si_pm4_state *pm4, uint32_t count,
+                            uint32_t initiator, bool predicate)
+{
+        si_pm4_cmd_begin(pm4, PKT3_DRAW_INDEX_AUTO);
+        si_pm4_cmd_add(pm4, count);
+        si_pm4_cmd_add(pm4, initiator);
+        si_pm4_cmd_end(pm4, predicate);
+}
+void si_cmd_surface_sync(struct si_pm4_state *pm4, uint32_t cp_coher_cntl)
+{
+        if (pm4->chip_class >= CIK) {
+                si_pm4_cmd_begin(pm4, PKT3_ACQUIRE_MEM);
+                si_pm4_cmd_add(pm4, cp_coher_cntl);     /* CP_COHER_CNTL */
+                si_pm4_cmd_add(pm4, 0xffffffff);        /* CP_COHER_SIZE */
+                si_pm4_cmd_add(pm4, 0xff);              /* CP_COHER_SIZE_HI */
+                si_pm4_cmd_add(pm4, 0);                 /* CP_COHER_BASE */
+                si_pm4_cmd_add(pm4, 0);                 /* CP_COHER_BASE_HI */
+                si_pm4_cmd_add(pm4, 0x0000000A);        /* POLL_INTERVAL */
+                si_pm4_cmd_end(pm4, false);
+        } else {
+                si_pm4_cmd_begin(pm4, PKT3_SURFACE_SYNC);
+                si_pm4_cmd_add(pm4, cp_coher_cntl);     /* CP_COHER_CNTL */
+                si_pm4_cmd_add(pm4, 0xffffffff);        /* CP_COHER_SIZE */
+                si_pm4_cmd_add(pm4, 0);                 /* CP_COHER_BASE */
+                si_pm4_cmd_add(pm4, 0x0000000A);        /* POLL_INTERVAL */
+                si_pm4_cmd_end(pm4, false);
+        }
+}

 /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/si_state.c
 ,0 → 1,2977
+/*
+ * Copyright 2012 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Christian König <christian.koenig@amd.com>
+ */
+#include "util/u_memory.h"
+#include "util/u_framebuffer.h"
+#include "util/u_blitter.h"
+#include "util/u_helpers.h"
+#include "util/u_math.h"
+#include "util/u_pack_color.h"
+#include "util/u_upload_mgr.h"
+#include "util/u_format_s3tc.h"
+#include "tgsi/tgsi_parse.h"
+#include "radeonsi_pipe.h"
+#include "radeonsi_shader.h"
+#include "si_state.h"
+#include "sid.h"
+static uint32_t cik_num_banks(uint32_t nbanks)
+{
+        switch (nbanks) {
+        case 2:
+                return V_02803C_ADDR_SURF_2_BANK;
+        case 4:
+                return V_02803C_ADDR_SURF_4_BANK;
+        case 8:
+        default:
+                return V_02803C_ADDR_SURF_8_BANK;
+        case 16:
+                return V_02803C_ADDR_SURF_16_BANK;
+        }
+}
+static unsigned cik_tile_split(unsigned tile_split)
+{
+        switch (tile_split) {
+        case 64:
+                tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
+                break;
+        case 128:
+                tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
+                break;
+        case 256:
+                tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
+                break;
+        case 512:
+                tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
+                break;
+        default:
+        case 1024:
+                tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
+                break;
+        case 2048:
+                tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
+                break;
+        case 4096:
+                tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
+                break;
+        }
+        return tile_split;
+}
+static unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
+{
+        switch (macro_tile_aspect) {
+        default:
+        case 1:
+                macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
+                break;
+        case 2:
+                macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
+                break;
+        case 4:
+                macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
+                break;
+        case 8:
+                macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
+                break;
+        }
+        return macro_tile_aspect;
+}
+static unsigned cik_bank_wh(unsigned bankwh)
+{
+        switch (bankwh) {
+        default:
+        case 1:
+                bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
+                break;
+        case 2:
+                bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
+                break;
+        case 4:
+                bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
+                break;
+        case 8:
+                bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
+                break;
+        }
+        return bankwh;
+}
+static unsigned cik_db_pipe_config(unsigned tile_pipes,
+                                   unsigned num_rbs)
+{
+        unsigned pipe_config;
+        switch (tile_pipes) {
+        case 8:
+                pipe_config = V_02803C_X_ADDR_SURF_P8_32X32_16X16;
+                break;
+        case 4:
+        default:
+                if (num_rbs == 4)
+                        pipe_config = V_02803C_X_ADDR_SURF_P4_16X16;
+                else
+                        pipe_config = V_02803C_X_ADDR_SURF_P4_8X16;
+                break;
+        case 2:
+                        pipe_config = V_02803C_ADDR_SURF_P2;
+                break;
+        }
+        return pipe_config;
+}
+/*
+ * inferred framebuffer and blender state
+ */
+static void si_update_fb_blend_state(struct r600_context *rctx)
+{
+        struct si_pm4_state *pm4;
+        struct si_state_blend *blend = rctx->queued.named.blend;
+        uint32_t mask;
+        if (blend == NULL)
+                return;
+        pm4 = si_pm4_alloc_state(rctx);
+        if (pm4 == NULL)
+                return;
+        mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
+        mask &= blend->cb_target_mask;
+        si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
+        si_pm4_set_state(rctx, fb_blend, pm4);
+}
+/*
+ * Blender functions
+ */
+static uint32_t si_translate_blend_function(int blend_func)
+{
+        switch (blend_func) {
+        case PIPE_BLEND_ADD:
+                return V_028780_COMB_DST_PLUS_SRC;
+        case PIPE_BLEND_SUBTRACT:
+                return V_028780_COMB_SRC_MINUS_DST;
+        case PIPE_BLEND_REVERSE_SUBTRACT:
+                return V_028780_COMB_DST_MINUS_SRC;
+        case PIPE_BLEND_MIN:
+                return V_028780_COMB_MIN_DST_SRC;
+        case PIPE_BLEND_MAX:
+                return V_028780_COMB_MAX_DST_SRC;
+        default:
+                R600_ERR("Unknown blend function %d\n", blend_func);
+                assert(0);
+                break;
+        }
+        return 0;
+}
+static uint32_t si_translate_blend_factor(int blend_fact)
+{
+        switch (blend_fact) {
+        case PIPE_BLENDFACTOR_ONE:
+                return V_028780_BLEND_ONE;
+        case PIPE_BLENDFACTOR_SRC_COLOR:
+                return V_028780_BLEND_SRC_COLOR;
+        case PIPE_BLENDFACTOR_SRC_ALPHA:
+                return V_028780_BLEND_SRC_ALPHA;
+        case PIPE_BLENDFACTOR_DST_ALPHA:
+                return V_028780_BLEND_DST_ALPHA;
+        case PIPE_BLENDFACTOR_DST_COLOR:
+                return V_028780_BLEND_DST_COLOR;
+        case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
+                return V_028780_BLEND_SRC_ALPHA_SATURATE;
+        case PIPE_BLENDFACTOR_CONST_COLOR:
+                return V_028780_BLEND_CONSTANT_COLOR;
+        case PIPE_BLENDFACTOR_CONST_ALPHA:
+                return V_028780_BLEND_CONSTANT_ALPHA;
+        case PIPE_BLENDFACTOR_ZERO:
+                return V_028780_BLEND_ZERO;
+        case PIPE_BLENDFACTOR_INV_SRC_COLOR:
+                return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
+        case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
+                return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
+        case PIPE_BLENDFACTOR_INV_DST_ALPHA:
+                return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
+        case PIPE_BLENDFACTOR_INV_DST_COLOR:
+                return V_028780_BLEND_ONE_MINUS_DST_COLOR;
+        case PIPE_BLENDFACTOR_INV_CONST_COLOR:
+                return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
+        case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
+                return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
+        case PIPE_BLENDFACTOR_SRC1_COLOR:
+                return V_028780_BLEND_SRC1_COLOR;
+        case PIPE_BLENDFACTOR_SRC1_ALPHA:
+                return V_028780_BLEND_SRC1_ALPHA;
+        case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
+                return V_028780_BLEND_INV_SRC1_COLOR;
+        case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
+                return V_028780_BLEND_INV_SRC1_ALPHA;
+        default:
+                R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
+                assert(0);
+                break;
+        }
+        return 0;
+}
+static void *si_create_blend_state(struct pipe_context *ctx,
+                                   const struct pipe_blend_state *state)
+{
+        struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
+        struct si_pm4_state *pm4 = &blend->pm4;
+        uint32_t color_control;
+        if (blend == NULL)
+                return NULL;
+        color_control = S_028808_MODE(V_028808_CB_NORMAL);
+        if (state->logicop_enable) {
+                color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
+        } else {
+                color_control |= S_028808_ROP3(0xcc);
+        }
+        si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
+        si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, ~0);
+        si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, ~0);
+        blend->cb_target_mask = 0;
+        for (int i = 0; i < 8; i++) {
+                /* state->rt entries > 0 only written if independent blending */
+                const int j = state->independent_blend_enable ? i : 0;
+                unsigned eqRGB = state->rt[j].rgb_func;
+                unsigned srcRGB = state->rt[j].rgb_src_factor;
+                unsigned dstRGB = state->rt[j].rgb_dst_factor;
+                unsigned eqA = state->rt[j].alpha_func;
+                unsigned srcA = state->rt[j].alpha_src_factor;
+                unsigned dstA = state->rt[j].alpha_dst_factor;
+                unsigned blend_cntl = 0;
+                /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
+                blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
+                if (!state->rt[j].blend_enable) {
+                        si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
+                        continue;
+                }
+                blend_cntl |= S_028780_ENABLE(1);
+                blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
+                blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
+                blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
+                if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
+                        blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
+                        blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
+                        blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
+                        blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
+                }
+                si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
+        }
+        return blend;
+}
+static void si_bind_blend_state(struct pipe_context *ctx, void *state)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state);
+        si_update_fb_blend_state(rctx);
+}
+static void si_delete_blend_state(struct pipe_context *ctx, void *state)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state);
+}
+static void si_set_blend_color(struct pipe_context *ctx,
+                               const struct pipe_blend_color *state)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
+        if (pm4 == NULL)
+                return;
+        si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
+        si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
+        si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
+        si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
+        si_pm4_set_state(rctx, blend_color, pm4);
+}
+/*
+ * Clipping, scissors and viewport
+ */
+static void si_set_clip_state(struct pipe_context *ctx,
+                              const struct pipe_clip_state *state)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
+        struct pipe_constant_buffer cb;
+        if (pm4 == NULL)
+                return;
+        for (int i = 0; i < 6; i++) {
+                si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
+                               fui(state->ucp[i][0]));
+                si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
+                               fui(state->ucp[i][1]));
+                si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
+                               fui(state->ucp[i][2]));
+                si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
+                               fui(state->ucp[i][3]));
+        }
+        cb.buffer = NULL;
+        cb.user_buffer = state->ucp;
+        cb.buffer_offset = 0;
+        cb.buffer_size = 4*4*8;
+        ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
+        pipe_resource_reference(&cb.buffer, NULL);
+        si_pm4_set_state(rctx, clip, pm4);
+}
+static void si_set_scissor_states(struct pipe_context *ctx,
+                                  unsigned start_slot,
+                                  unsigned num_scissors,
+                                  const struct pipe_scissor_state *state)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
+        uint32_t tl, br;
+        if (pm4 == NULL)
+                return;
+        tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
+        br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
+        si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl);
+        si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br);
+        si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl);
+        si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br);
+        si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl);
+        si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br);
+        si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl);
+        si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br);
+        si_pm4_set_state(rctx, scissor, pm4);
+}
+static void si_set_viewport_states(struct pipe_context *ctx,
+                                   unsigned start_slot,
+                                   unsigned num_viewports,
+                                   const struct pipe_viewport_state *state)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
+        struct si_pm4_state *pm4 = &viewport->pm4;
+        if (viewport == NULL)
+                return;
+        viewport->viewport = *state;
+        si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
+        si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
+        si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
+        si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
+        si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
+        si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
+        si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
+        si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
+        si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
+        si_pm4_set_state(rctx, viewport, viewport);
+}
+/*
+ * inferred state between framebuffer and rasterizer
+ */
+static void si_update_fb_rs_state(struct r600_context *rctx)
+{
+        struct si_state_rasterizer *rs = rctx->queued.named.rasterizer;
+        struct si_pm4_state *pm4;
+        unsigned offset_db_fmt_cntl = 0, depth;
+        float offset_units;
+        if (!rs || !rctx->framebuffer.zsbuf)
+                return;
+        offset_units = rctx->queued.named.rasterizer->offset_units;
+        switch (rctx->framebuffer.zsbuf->texture->format) {
+        case PIPE_FORMAT_S8_UINT_Z24_UNORM:
+        case PIPE_FORMAT_X8Z24_UNORM:
+        case PIPE_FORMAT_Z24X8_UNORM:
+        case PIPE_FORMAT_Z24_UNORM_S8_UINT:
+                depth = -24;
+                offset_units *= 2.0f;
+                break;
+        case PIPE_FORMAT_Z32_FLOAT:
+        case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
+                depth = -23;
+                offset_units *= 1.0f;
+                offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
+                break;
+        case PIPE_FORMAT_Z16_UNORM:
+                depth = -16;
+                offset_units *= 4.0f;
+                break;
+        default:
+                return;
+        }
+        pm4 = si_pm4_alloc_state(rctx);
+        if (pm4 == NULL)
+                return;
+        /* FIXME some of those reg can be computed with cso */
+        offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
+        si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
+                       fui(rctx->queued.named.rasterizer->offset_scale));
+        si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
+        si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
+                       fui(rctx->queued.named.rasterizer->offset_scale));
+        si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
+        si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl);
+        si_pm4_set_state(rctx, fb_rs, pm4);
+}
+/*
+ * Rasterizer
+ */
+static uint32_t si_translate_fill(uint32_t func)
+{
+        switch(func) {
+        case PIPE_POLYGON_MODE_FILL:
+                return V_028814_X_DRAW_TRIANGLES;
+        case PIPE_POLYGON_MODE_LINE:
+                return V_028814_X_DRAW_LINES;
+        case PIPE_POLYGON_MODE_POINT:
+                return V_028814_X_DRAW_POINTS;
+        default:
+                assert(0);
+                return V_028814_X_DRAW_POINTS;
+        }
+}
+static void *si_create_rs_state(struct pipe_context *ctx,
+                                const struct pipe_rasterizer_state *state)
+{
+        struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
+        struct si_pm4_state *pm4 = &rs->pm4;
+        unsigned tmp;
+        unsigned prov_vtx = 1, polygon_dual_mode;
+        unsigned clip_rule;
+        float psize_min, psize_max;
+        if (rs == NULL) {
+                return NULL;
+        }
+        rs->two_side = state->light_twoside;
+        rs->clip_plane_enable = state->clip_plane_enable;
+        polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
+                                state->fill_back != PIPE_POLYGON_MODE_FILL);
+        if (state->flatshade_first)
+                prov_vtx = 0;
+        rs->flatshade = state->flatshade;
+        rs->sprite_coord_enable = state->sprite_coord_enable;
+        rs->pa_sc_line_stipple = state->line_stipple_enable ?
+                                S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
+                                S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
+        rs->pa_su_sc_mode_cntl =
+                S_028814_PROVOKING_VTX_LAST(prov_vtx) |
+                S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
+                S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
+                S_028814_FACE(!state->front_ccw) |
+                S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
+                S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
+                S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
+                S_028814_POLY_MODE(polygon_dual_mode) |
+                S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
+                S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
+        rs->pa_cl_clip_cntl =
+                S_028810_PS_UCP_MODE(3) |
+                S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
+                S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
+                S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
+        clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
+        /* offset */
+        rs->offset_units = state->offset_units;
+        rs->offset_scale = state->offset_scale * 12.0f;
+        tmp = S_0286D4_FLAT_SHADE_ENA(1);
+        if (state->sprite_coord_enable) {
+                tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
+                        S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
+                        S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
+                        S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
+                        S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
+                if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
+                        tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
+                }
+        }
+        si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
+        si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
+        /* point size 12.4 fixed point */
+        tmp = (unsigned)(state->point_size * 8.0);
+        si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
+        if (state->point_size_per_vertex) {
+                psize_min = util_get_min_point_size(state);
+                psize_max = 8192;
+        } else {
+                /* Force the point size to be as if the vertex output was disabled. */
+                psize_min = state->point_size;
+                psize_max = state->point_size;
+        }
+        /* Divide by two, because 0.5 = 1 pixel. */
+        si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
+                        S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
+                        S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
+        tmp = (unsigned)state->line_width * 8;
+        si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
+        si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
+                        S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
+        si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, 0x00000400);
+        si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
+                        S_028BE4_PIX_CENTER(state->half_pixel_center));
+        si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
+        si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
+        si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
+        si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
+        si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
+        si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule);
+        return rs;
+}
+static void si_bind_rs_state(struct pipe_context *ctx, void *state)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
+        if (state == NULL)
+                return;
+        // TODO
+        rctx->sprite_coord_enable = rs->sprite_coord_enable;
+        rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
+        rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
+        si_pm4_bind_state(rctx, rasterizer, rs);
+        si_update_fb_rs_state(rctx);
+}
+static void si_delete_rs_state(struct pipe_context *ctx, void *state)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state);
+}
+/*
+ * infeered state between dsa and stencil ref
+ */
+static void si_update_dsa_stencil_ref(struct r600_context *rctx)
+{
+        struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
+        struct pipe_stencil_ref *ref = &rctx->stencil_ref;
+        struct si_state_dsa *dsa = rctx->queued.named.dsa;
+        if (pm4 == NULL)
+                return;
+        si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
+                       S_028430_STENCILTESTVAL(ref->ref_value[0]) |
+                       S_028430_STENCILMASK(dsa->valuemask[0]) |
+                       S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
+                       S_028430_STENCILOPVAL(1));
+        si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
+                       S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
+                       S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
+                       S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
+                       S_028434_STENCILOPVAL_BF(1));
+        si_pm4_set_state(rctx, dsa_stencil_ref, pm4);
+}
+static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
+                                    const struct pipe_stencil_ref *state)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        rctx->stencil_ref = *state;
+        si_update_dsa_stencil_ref(rctx);
+}
+/*
+ * DSA
+ */
+static uint32_t si_translate_stencil_op(int s_op)
+{
+        switch (s_op) {
+        case PIPE_STENCIL_OP_KEEP:
+                return V_02842C_STENCIL_KEEP;
+        case PIPE_STENCIL_OP_ZERO:
+                return V_02842C_STENCIL_ZERO;
+        case PIPE_STENCIL_OP_REPLACE:
+                return V_02842C_STENCIL_REPLACE_TEST;
+        case PIPE_STENCIL_OP_INCR:
+                return V_02842C_STENCIL_ADD_CLAMP;
+        case PIPE_STENCIL_OP_DECR:
+                return V_02842C_STENCIL_SUB_CLAMP;
+        case PIPE_STENCIL_OP_INCR_WRAP:
+                return V_02842C_STENCIL_ADD_WRAP;
+        case PIPE_STENCIL_OP_DECR_WRAP:
+                return V_02842C_STENCIL_SUB_WRAP;
+        case PIPE_STENCIL_OP_INVERT:
+                return V_02842C_STENCIL_INVERT;
+        default:
+                R600_ERR("Unknown stencil op %d", s_op);
+                assert(0);
+                break;
+        }
+        return 0;
+}
+static void *si_create_dsa_state(struct pipe_context *ctx,
+                                 const struct pipe_depth_stencil_alpha_state *state)
+{
+        struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
+        struct si_pm4_state *pm4 = &dsa->pm4;
+        unsigned db_depth_control;
+        unsigned db_render_override, db_render_control;
+        uint32_t db_stencil_control = 0;
+        if (dsa == NULL) {
+                return NULL;
+        }
+        dsa->valuemask[0] = state->stencil[0].valuemask;
+        dsa->valuemask[1] = state->stencil[1].valuemask;
+        dsa->writemask[0] = state->stencil[0].writemask;
+        dsa->writemask[1] = state->stencil[1].writemask;
+        db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
+                S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
+                S_028800_ZFUNC(state->depth.func);
+        /* stencil */
+        if (state->stencil[0].enabled) {
+                db_depth_control |= S_028800_STENCIL_ENABLE(1);
+                db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
+                db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
+                db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
+                db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
+                if (state->stencil[1].enabled) {
+                        db_depth_control |= S_028800_BACKFACE_ENABLE(1);
+                        db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
+                        db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
+                        db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
+                        db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
+                }
+        }
+        /* alpha */
+        if (state->alpha.enabled) {
+                dsa->alpha_func = state->alpha.func;
+                dsa->alpha_ref = state->alpha.ref_value;
+        } else {
+                dsa->alpha_func = PIPE_FUNC_ALWAYS;
+        }
+        /* misc */
+        db_render_control = 0;
+        db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
+                S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
+                S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
+        /* TODO db_render_override depends on query */
+        si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
+        si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
+        si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
+        si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
+        //si_pm4_set_reg(pm4, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control);
+        si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
+        si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
+        si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
+        si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
+        si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
+        si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
+        si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
+        si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
+        dsa->db_render_override = db_render_override;
+        return dsa;
+}
+static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct si_state_dsa *dsa = state;
+        if (state == NULL)
+                return;
+        si_pm4_bind_state(rctx, dsa, dsa);
+        si_update_dsa_stencil_ref(rctx);
+}
+static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state);
+}
+static void *si_create_db_flush_dsa(struct r600_context *rctx, bool copy_depth,
+                                    bool copy_stencil)
+{
+        struct pipe_depth_stencil_alpha_state dsa;
+        struct si_state_dsa *state;
+        memset(&dsa, 0, sizeof(dsa));
+        state = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
+        if (copy_depth || copy_stencil) {
+                si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
+                               S_028000_DEPTH_COPY(copy_depth) |
+                               S_028000_STENCIL_COPY(copy_stencil) |
+                               S_028000_COPY_CENTROID(1));
+        } else {
+                si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
+                               S_028000_DEPTH_COMPRESS_DISABLE(1) |
+                               S_028000_STENCIL_COMPRESS_DISABLE(1));
+                si_pm4_set_reg(&state->pm4, R_02800C_DB_RENDER_OVERRIDE,
+                               S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
+                               S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
+                               S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
+                               S_02800C_DISABLE_TILE_RATE_TILES(1));
+        }
+        return state;
+}
+/*
+ * format translation
+ */
+static uint32_t si_translate_colorformat(enum pipe_format format)
+{
+        switch (format) {
+        /* 8-bit buffers. */
+        case PIPE_FORMAT_A8_UNORM:
+        case PIPE_FORMAT_A8_SNORM:
+        case PIPE_FORMAT_A8_UINT:
+        case PIPE_FORMAT_A8_SINT:
+        case PIPE_FORMAT_I8_UNORM:
+        case PIPE_FORMAT_I8_SNORM:
+        case PIPE_FORMAT_I8_UINT:
+        case PIPE_FORMAT_I8_SINT:
+        case PIPE_FORMAT_L8_UNORM:
+        case PIPE_FORMAT_L8_SNORM:
+        case PIPE_FORMAT_L8_UINT:
+        case PIPE_FORMAT_L8_SINT:
+        case PIPE_FORMAT_L8_SRGB:
+        case PIPE_FORMAT_R8_UNORM:
+        case PIPE_FORMAT_R8_SNORM:
+        case PIPE_FORMAT_R8_UINT:
+        case PIPE_FORMAT_R8_SINT:
+                return V_028C70_COLOR_8;
+        /* 16-bit buffers. */
+        case PIPE_FORMAT_B5G6R5_UNORM:
+                return V_028C70_COLOR_5_6_5;
+        case PIPE_FORMAT_B5G5R5A1_UNORM:
+        case PIPE_FORMAT_B5G5R5X1_UNORM:
+                return V_028C70_COLOR_1_5_5_5;
+        case PIPE_FORMAT_B4G4R4A4_UNORM:
+        case PIPE_FORMAT_B4G4R4X4_UNORM:
+                return V_028C70_COLOR_4_4_4_4;
+        case PIPE_FORMAT_L8A8_UNORM:
+        case PIPE_FORMAT_L8A8_SNORM:
+        case PIPE_FORMAT_L8A8_UINT:
+        case PIPE_FORMAT_L8A8_SINT:
+        case PIPE_FORMAT_R8G8_SNORM:
+        case PIPE_FORMAT_R8G8_UNORM:
+        case PIPE_FORMAT_R8G8_UINT:
+        case PIPE_FORMAT_R8G8_SINT:
+                return V_028C70_COLOR_8_8;
+        case PIPE_FORMAT_Z16_UNORM:
+        case PIPE_FORMAT_R16_UNORM:
+        case PIPE_FORMAT_R16_SNORM:
+        case PIPE_FORMAT_R16_UINT:
+        case PIPE_FORMAT_R16_SINT:
+        case PIPE_FORMAT_R16_FLOAT:
+        case PIPE_FORMAT_L16_UNORM:
+        case PIPE_FORMAT_L16_SNORM:
+        case PIPE_FORMAT_L16_FLOAT:
+        case PIPE_FORMAT_I16_UNORM:
+        case PIPE_FORMAT_I16_SNORM:
+        case PIPE_FORMAT_I16_FLOAT:
+        case PIPE_FORMAT_A16_UNORM:
+        case PIPE_FORMAT_A16_SNORM:
+        case PIPE_FORMAT_A16_FLOAT:
+                return V_028C70_COLOR_16;
+        /* 32-bit buffers. */
+        case PIPE_FORMAT_A8B8G8R8_SRGB:
+        case PIPE_FORMAT_A8B8G8R8_UNORM:
+        case PIPE_FORMAT_A8R8G8B8_UNORM:
+        case PIPE_FORMAT_B8G8R8A8_SRGB:
+        case PIPE_FORMAT_B8G8R8A8_UNORM:
+        case PIPE_FORMAT_B8G8R8X8_UNORM:
+        case PIPE_FORMAT_R8G8B8A8_SNORM:
+        case PIPE_FORMAT_R8G8B8A8_UNORM:
+        case PIPE_FORMAT_R8G8B8X8_UNORM:
+        case PIPE_FORMAT_R8G8B8X8_SNORM:
+        case PIPE_FORMAT_R8G8B8X8_SRGB:
+        case PIPE_FORMAT_R8G8B8X8_UINT:
+        case PIPE_FORMAT_R8G8B8X8_SINT:
+        case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
+        case PIPE_FORMAT_X8B8G8R8_UNORM:
+        case PIPE_FORMAT_X8R8G8B8_UNORM:
+        case PIPE_FORMAT_R8G8B8A8_SSCALED:
+        case PIPE_FORMAT_R8G8B8A8_USCALED:
+        case PIPE_FORMAT_R8G8B8A8_SINT:
+        case PIPE_FORMAT_R8G8B8A8_UINT:
+                return V_028C70_COLOR_8_8_8_8;
+        case PIPE_FORMAT_R10G10B10A2_UNORM:
+        case PIPE_FORMAT_R10G10B10X2_SNORM:
+        case PIPE_FORMAT_B10G10R10A2_UNORM:
+        case PIPE_FORMAT_B10G10R10A2_UINT:
+        case PIPE_FORMAT_B10G10R10X2_UNORM:
+        case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
+                return V_028C70_COLOR_2_10_10_10;
+        case PIPE_FORMAT_Z24X8_UNORM:
+        case PIPE_FORMAT_Z24_UNORM_S8_UINT:
+                return V_028C70_COLOR_8_24;
+        case PIPE_FORMAT_S8X24_UINT:
+        case PIPE_FORMAT_X8Z24_UNORM:
+        case PIPE_FORMAT_S8_UINT_Z24_UNORM:
+                return V_028C70_COLOR_24_8;
+        case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
+                return V_028C70_COLOR_X24_8_32_FLOAT;
+        case PIPE_FORMAT_I32_FLOAT:
+        case PIPE_FORMAT_L32_FLOAT:
+        case PIPE_FORMAT_R32_FLOAT:
+        case PIPE_FORMAT_A32_FLOAT:
+        case PIPE_FORMAT_Z32_FLOAT:
+                return V_028C70_COLOR_32;
+        case PIPE_FORMAT_L16A16_UNORM:
+        case PIPE_FORMAT_L16A16_SNORM:
+        case PIPE_FORMAT_L16A16_FLOAT:
+        case PIPE_FORMAT_R16G16_SSCALED:
+        case PIPE_FORMAT_R16G16_UNORM:
+        case PIPE_FORMAT_R16G16_SNORM:
+        case PIPE_FORMAT_R16G16_UINT:
+        case PIPE_FORMAT_R16G16_SINT:
+        case PIPE_FORMAT_R16G16_FLOAT:
+                return V_028C70_COLOR_16_16;
+        case PIPE_FORMAT_R11G11B10_FLOAT:
+                return V_028C70_COLOR_10_11_11;
+        /* 64-bit buffers. */
+        case PIPE_FORMAT_R16G16B16A16_UINT:
+        case PIPE_FORMAT_R16G16B16A16_SINT:
+        case PIPE_FORMAT_R16G16B16A16_USCALED:
+        case PIPE_FORMAT_R16G16B16A16_SSCALED:
+        case PIPE_FORMAT_R16G16B16A16_UNORM:
+        case PIPE_FORMAT_R16G16B16A16_SNORM:
+        case PIPE_FORMAT_R16G16B16A16_FLOAT:
+        case PIPE_FORMAT_R16G16B16X16_UNORM:
+        case PIPE_FORMAT_R16G16B16X16_SNORM:
+        case PIPE_FORMAT_R16G16B16X16_FLOAT:
+        case PIPE_FORMAT_R16G16B16X16_UINT:
+        case PIPE_FORMAT_R16G16B16X16_SINT:
+                return V_028C70_COLOR_16_16_16_16;
+        case PIPE_FORMAT_L32A32_FLOAT:
+        case PIPE_FORMAT_L32A32_UINT:
+        case PIPE_FORMAT_L32A32_SINT:
+        case PIPE_FORMAT_R32G32_FLOAT:
+        case PIPE_FORMAT_R32G32_USCALED:
+        case PIPE_FORMAT_R32G32_SSCALED:
+        case PIPE_FORMAT_R32G32_SINT:
+        case PIPE_FORMAT_R32G32_UINT:
+                return V_028C70_COLOR_32_32;
+        /* 128-bit buffers. */
+        case PIPE_FORMAT_R32G32B32A32_SNORM:
+        case PIPE_FORMAT_R32G32B32A32_UNORM:
+        case PIPE_FORMAT_R32G32B32A32_SSCALED:
+        case PIPE_FORMAT_R32G32B32A32_USCALED:
+        case PIPE_FORMAT_R32G32B32A32_SINT:
+        case PIPE_FORMAT_R32G32B32A32_UINT:
+        case PIPE_FORMAT_R32G32B32A32_FLOAT:
+        case PIPE_FORMAT_R32G32B32X32_FLOAT:
+        case PIPE_FORMAT_R32G32B32X32_UINT:
+        case PIPE_FORMAT_R32G32B32X32_SINT:
+                return V_028C70_COLOR_32_32_32_32;
+        /* YUV buffers. */
+        case PIPE_FORMAT_UYVY:
+        case PIPE_FORMAT_YUYV:
+        /* 96-bit buffers. */
+        case PIPE_FORMAT_R32G32B32_FLOAT:
+        /* 8-bit buffers. */
+        case PIPE_FORMAT_L4A4_UNORM:
+        case PIPE_FORMAT_R4A4_UNORM:
+        case PIPE_FORMAT_A4R4_UNORM:
+        default:
+                return V_028C70_COLOR_INVALID; /* Unsupported. */
+        }
+}
+static uint32_t si_translate_colorswap(enum pipe_format format)
+{
+        switch (format) {
+        /* 8-bit buffers. */
+        case PIPE_FORMAT_L4A4_UNORM:
+        case PIPE_FORMAT_A4R4_UNORM:
+                return V_028C70_SWAP_ALT;
+        case PIPE_FORMAT_A8_UNORM:
+        case PIPE_FORMAT_A8_SNORM:
+        case PIPE_FORMAT_A8_UINT:
+        case PIPE_FORMAT_A8_SINT:
+        case PIPE_FORMAT_R4A4_UNORM:
+                return V_028C70_SWAP_ALT_REV;
+        case PIPE_FORMAT_I8_UNORM:
+        case PIPE_FORMAT_I8_SNORM:
+        case PIPE_FORMAT_L8_UNORM:
+        case PIPE_FORMAT_L8_SNORM:
+        case PIPE_FORMAT_I8_UINT:
+        case PIPE_FORMAT_I8_SINT:
+        case PIPE_FORMAT_L8_UINT:
+        case PIPE_FORMAT_L8_SINT:
+        case PIPE_FORMAT_L8_SRGB:
+        case PIPE_FORMAT_R8_UNORM:
+        case PIPE_FORMAT_R8_SNORM:
+        case PIPE_FORMAT_R8_UINT:
+        case PIPE_FORMAT_R8_SINT:
+                return V_028C70_SWAP_STD;
+        /* 16-bit buffers. */
+        case PIPE_FORMAT_B5G6R5_UNORM:
+                return V_028C70_SWAP_STD_REV;
+        case PIPE_FORMAT_B5G5R5A1_UNORM:
+        case PIPE_FORMAT_B5G5R5X1_UNORM:
+                return V_028C70_SWAP_ALT;
+        case PIPE_FORMAT_B4G4R4A4_UNORM:
+        case PIPE_FORMAT_B4G4R4X4_UNORM:
+                return V_028C70_SWAP_ALT;
+        case PIPE_FORMAT_Z16_UNORM:
+                return V_028C70_SWAP_STD;
+        case PIPE_FORMAT_L8A8_UNORM:
+        case PIPE_FORMAT_L8A8_SNORM:
+        case PIPE_FORMAT_L8A8_UINT:
+        case PIPE_FORMAT_L8A8_SINT:
+                return V_028C70_SWAP_ALT;
+        case PIPE_FORMAT_R8G8_SNORM:
+        case PIPE_FORMAT_R8G8_UNORM:
+        case PIPE_FORMAT_R8G8_UINT:
+        case PIPE_FORMAT_R8G8_SINT:
+                return V_028C70_SWAP_STD;
+        case PIPE_FORMAT_I16_UNORM:
+        case PIPE_FORMAT_I16_SNORM:
+        case PIPE_FORMAT_I16_FLOAT:
+        case PIPE_FORMAT_L16_UNORM:
+        case PIPE_FORMAT_L16_SNORM:
+        case PIPE_FORMAT_L16_FLOAT:
+        case PIPE_FORMAT_R16_UNORM:
+        case PIPE_FORMAT_R16_SNORM:
+        case PIPE_FORMAT_R16_UINT:
+        case PIPE_FORMAT_R16_SINT:
+        case PIPE_FORMAT_R16_FLOAT:
+                return V_028C70_SWAP_STD;
+        case PIPE_FORMAT_A16_UNORM:
+        case PIPE_FORMAT_A16_SNORM:
+        case PIPE_FORMAT_A16_FLOAT:
+                return V_028C70_SWAP_ALT_REV;
+        /* 32-bit buffers. */
+        case PIPE_FORMAT_A8B8G8R8_SRGB:
+                return V_028C70_SWAP_STD_REV;
+        case PIPE_FORMAT_B8G8R8A8_SRGB:
+                return V_028C70_SWAP_ALT;
+        case PIPE_FORMAT_B8G8R8A8_UNORM:
+        case PIPE_FORMAT_B8G8R8X8_UNORM:
+                return V_028C70_SWAP_ALT;
+        case PIPE_FORMAT_A8R8G8B8_UNORM:
+        case PIPE_FORMAT_X8R8G8B8_UNORM:
+                return V_028C70_SWAP_ALT_REV;
+        case PIPE_FORMAT_R8G8B8A8_SNORM:
+        case PIPE_FORMAT_R8G8B8A8_UNORM:
+        case PIPE_FORMAT_R8G8B8A8_SSCALED:
+        case PIPE_FORMAT_R8G8B8A8_USCALED:
+        case PIPE_FORMAT_R8G8B8A8_SINT:
+        case PIPE_FORMAT_R8G8B8A8_UINT:
+        case PIPE_FORMAT_R8G8B8X8_UNORM:
+        case PIPE_FORMAT_R8G8B8X8_SNORM:
+        case PIPE_FORMAT_R8G8B8X8_SRGB:
+        case PIPE_FORMAT_R8G8B8X8_UINT:
+        case PIPE_FORMAT_R8G8B8X8_SINT:
+                return V_028C70_SWAP_STD;
+        case PIPE_FORMAT_A8B8G8R8_UNORM:
+        case PIPE_FORMAT_X8B8G8R8_UNORM:
+        /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
+                return V_028C70_SWAP_STD_REV;
+        case PIPE_FORMAT_Z24X8_UNORM:
+        case PIPE_FORMAT_Z24_UNORM_S8_UINT:
+                return V_028C70_SWAP_STD;
+        case PIPE_FORMAT_S8X24_UINT:
+        case PIPE_FORMAT_X8Z24_UNORM:
+        case PIPE_FORMAT_S8_UINT_Z24_UNORM:
+                return V_028C70_SWAP_STD_REV;
+        case PIPE_FORMAT_R10G10B10A2_UNORM:
+        case PIPE_FORMAT_R10G10B10X2_SNORM:
+        case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
+                return V_028C70_SWAP_STD;
+        case PIPE_FORMAT_B10G10R10A2_UNORM:
+        case PIPE_FORMAT_B10G10R10A2_UINT:
+        case PIPE_FORMAT_B10G10R10X2_UNORM:
+                return V_028C70_SWAP_ALT;
+        case PIPE_FORMAT_R11G11B10_FLOAT:
+        case PIPE_FORMAT_I32_FLOAT:
+        case PIPE_FORMAT_L32_FLOAT:
+        case PIPE_FORMAT_R32_FLOAT:
+        case PIPE_FORMAT_R32_UINT:
+        case PIPE_FORMAT_R32_SINT:
+        case PIPE_FORMAT_Z32_FLOAT:
+        case PIPE_FORMAT_R16G16_FLOAT:
+        case PIPE_FORMAT_R16G16_UNORM:
+        case PIPE_FORMAT_R16G16_SNORM:
+        case PIPE_FORMAT_R16G16_UINT:
+        case PIPE_FORMAT_R16G16_SINT:
+                return V_028C70_SWAP_STD;
+        case PIPE_FORMAT_L16A16_UNORM:
+        case PIPE_FORMAT_L16A16_SNORM:
+        case PIPE_FORMAT_L16A16_FLOAT:
+                return V_028C70_SWAP_ALT;
+        case PIPE_FORMAT_A32_FLOAT:
+                return V_028C70_SWAP_ALT_REV;
+        /* 64-bit buffers. */
+        case PIPE_FORMAT_R32G32_FLOAT:
+        case PIPE_FORMAT_R32G32_UINT:
+        case PIPE_FORMAT_R32G32_SINT:
+        case PIPE_FORMAT_R16G16B16A16_UNORM:
+        case PIPE_FORMAT_R16G16B16A16_SNORM:
+        case PIPE_FORMAT_R16G16B16A16_USCALED:
+        case PIPE_FORMAT_R16G16B16A16_SSCALED:
+        case PIPE_FORMAT_R16G16B16A16_UINT:
+        case PIPE_FORMAT_R16G16B16A16_SINT:
+        case PIPE_FORMAT_R16G16B16A16_FLOAT:
+        case PIPE_FORMAT_R16G16B16X16_UNORM:
+        case PIPE_FORMAT_R16G16B16X16_SNORM:
+        case PIPE_FORMAT_R16G16B16X16_FLOAT:
+        case PIPE_FORMAT_R16G16B16X16_UINT:
+        case PIPE_FORMAT_R16G16B16X16_SINT:
+        case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
+                return V_028C70_SWAP_STD;
+        case PIPE_FORMAT_L32A32_FLOAT:
+        case PIPE_FORMAT_L32A32_UINT:
+        case PIPE_FORMAT_L32A32_SINT:
+                return V_028C70_SWAP_ALT;
+        /* 128-bit buffers. */
+        case PIPE_FORMAT_R32G32B32A32_FLOAT:
+        case PIPE_FORMAT_R32G32B32A32_SNORM:
+        case PIPE_FORMAT_R32G32B32A32_UNORM:
+        case PIPE_FORMAT_R32G32B32A32_SSCALED:
+        case PIPE_FORMAT_R32G32B32A32_USCALED:
+        case PIPE_FORMAT_R32G32B32A32_SINT:
+        case PIPE_FORMAT_R32G32B32A32_UINT:
+        case PIPE_FORMAT_R32G32B32X32_FLOAT:
+        case PIPE_FORMAT_R32G32B32X32_UINT:
+        case PIPE_FORMAT_R32G32B32X32_SINT:
+                return V_028C70_SWAP_STD;
+        default:
+                R600_ERR("unsupported colorswap format %d\n", format);
+                return ~0U;
+        }
+        return ~0U;
+}
+static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
+{
+        if (R600_BIG_ENDIAN) {
+                switch(colorformat) {
+                /* 8-bit buffers. */
+                case V_028C70_COLOR_8:
+                        return V_028C70_ENDIAN_NONE;
+                /* 16-bit buffers. */
+                case V_028C70_COLOR_5_6_5:
+                case V_028C70_COLOR_1_5_5_5:
+                case V_028C70_COLOR_4_4_4_4:
+                case V_028C70_COLOR_16:
+                case V_028C70_COLOR_8_8:
+                        return V_028C70_ENDIAN_8IN16;
+                /* 32-bit buffers. */
+                case V_028C70_COLOR_8_8_8_8:
+                case V_028C70_COLOR_2_10_10_10:
+                case V_028C70_COLOR_8_24:
+                case V_028C70_COLOR_24_8:
+                case V_028C70_COLOR_16_16:
+                        return V_028C70_ENDIAN_8IN32;
+                /* 64-bit buffers. */
+                case V_028C70_COLOR_16_16_16_16:
+                        return V_028C70_ENDIAN_8IN16;
+                case V_028C70_COLOR_32_32:
+                        return V_028C70_ENDIAN_8IN32;
+                /* 128-bit buffers. */
+                case V_028C70_COLOR_32_32_32_32:
+                        return V_028C70_ENDIAN_8IN32;
+                default:
+                        return V_028C70_ENDIAN_NONE; /* Unsupported. */
+                }
+        } else {
+                return V_028C70_ENDIAN_NONE;
+        }
+}
+/* Returns the size in bits of the widest component of a CB format */
+static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
+{
+        switch(colorformat) {
+        case V_028C70_COLOR_4_4_4_4:
+                return 4;
+        case V_028C70_COLOR_1_5_5_5:
+        case V_028C70_COLOR_5_5_5_1:
+                return 5;
+        case V_028C70_COLOR_5_6_5:
+                return 6;
+        case V_028C70_COLOR_8:
+        case V_028C70_COLOR_8_8:
+        case V_028C70_COLOR_8_8_8_8:
+                return 8;
+        case V_028C70_COLOR_10_10_10_2:
+        case V_028C70_COLOR_2_10_10_10:
+                return 10;
+        case V_028C70_COLOR_10_11_11:
+        case V_028C70_COLOR_11_11_10:
+                return 11;
+        case V_028C70_COLOR_16:
+        case V_028C70_COLOR_16_16:
+        case V_028C70_COLOR_16_16_16_16:
+                return 16;
+        case V_028C70_COLOR_8_24:
+        case V_028C70_COLOR_24_8:
+                return 24;
+        case V_028C70_COLOR_32:
+        case V_028C70_COLOR_32_32:
+        case V_028C70_COLOR_32_32_32_32:
+        case V_028C70_COLOR_X24_8_32_FLOAT:
+                return 32;
+        }
+        assert(!"Unknown maximum component size");
+        return 0;
+}
+static uint32_t si_translate_dbformat(enum pipe_format format)
+{
+        switch (format) {
+        case PIPE_FORMAT_Z16_UNORM:
+                return V_028040_Z_16;
+        case PIPE_FORMAT_S8_UINT_Z24_UNORM:
+        case PIPE_FORMAT_X8Z24_UNORM:
+        case PIPE_FORMAT_Z24X8_UNORM:
+        case PIPE_FORMAT_Z24_UNORM_S8_UINT:
+                return V_028040_Z_24; /* deprecated on SI */
+        case PIPE_FORMAT_Z32_FLOAT:
+        case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
+                return V_028040_Z_32_FLOAT;
+        default:
+                return V_028040_Z_INVALID;
+        }
+}
+/*
+ * Texture translation
+ */
+static uint32_t si_translate_texformat(struct pipe_screen *screen,
+                                       enum pipe_format format,
+                                       const struct util_format_description *desc,
+                                       int first_non_void)
+{
+        struct r600_screen *rscreen = (struct r600_screen*)screen;
+        bool enable_s3tc = rscreen->info.drm_minor >= 31;
+        boolean uniform = TRUE;
+        int i;
+        /* Colorspace (return non-RGB formats directly). */
+        switch (desc->colorspace) {
+        /* Depth stencil formats */
+        case UTIL_FORMAT_COLORSPACE_ZS:
+                switch (format) {
+                case PIPE_FORMAT_Z16_UNORM:
+                        return V_008F14_IMG_DATA_FORMAT_16;
+                case PIPE_FORMAT_X24S8_UINT:
+                case PIPE_FORMAT_Z24X8_UNORM:
+                case PIPE_FORMAT_Z24_UNORM_S8_UINT:
+                        return V_008F14_IMG_DATA_FORMAT_8_24;
+                case PIPE_FORMAT_X8Z24_UNORM:
+                case PIPE_FORMAT_S8X24_UINT:
+                case PIPE_FORMAT_S8_UINT_Z24_UNORM:
+                        return V_008F14_IMG_DATA_FORMAT_24_8;
+                case PIPE_FORMAT_S8_UINT:
+                        return V_008F14_IMG_DATA_FORMAT_8;
+                case PIPE_FORMAT_Z32_FLOAT:
+                        return V_008F14_IMG_DATA_FORMAT_32;
+                case PIPE_FORMAT_X32_S8X24_UINT:
+                case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
+                        return V_008F14_IMG_DATA_FORMAT_X24_8_32;
+                default:
+                        goto out_unknown;
+                }
+        case UTIL_FORMAT_COLORSPACE_YUV:
+                goto out_unknown; /* TODO */
+        case UTIL_FORMAT_COLORSPACE_SRGB:
+                if (desc->nr_channels != 4 && desc->nr_channels != 1)
+                        goto out_unknown;
+                break;
+        default:
+                break;
+        }
+        if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
+                if (!enable_s3tc)
+                        goto out_unknown;
+                switch (format) {
+                case PIPE_FORMAT_RGTC1_SNORM:
+                case PIPE_FORMAT_LATC1_SNORM:
+                case PIPE_FORMAT_RGTC1_UNORM:
+                case PIPE_FORMAT_LATC1_UNORM:
+                        return V_008F14_IMG_DATA_FORMAT_BC4;
+                case PIPE_FORMAT_RGTC2_SNORM:
+                case PIPE_FORMAT_LATC2_SNORM:
+                case PIPE_FORMAT_RGTC2_UNORM:
+                case PIPE_FORMAT_LATC2_UNORM:
+                        return V_008F14_IMG_DATA_FORMAT_BC5;
+                default:
+                        goto out_unknown;
+                }
+        }
+        if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
+                if (!enable_s3tc)
+                        goto out_unknown;
+                if (!util_format_s3tc_enabled) {
+                        goto out_unknown;
+                }
+                switch (format) {
+                case PIPE_FORMAT_DXT1_RGB:
+                case PIPE_FORMAT_DXT1_RGBA:
+                case PIPE_FORMAT_DXT1_SRGB:
+                case PIPE_FORMAT_DXT1_SRGBA:
+                        return V_008F14_IMG_DATA_FORMAT_BC1;
+                case PIPE_FORMAT_DXT3_RGBA:
+                case PIPE_FORMAT_DXT3_SRGBA:
+                        return V_008F14_IMG_DATA_FORMAT_BC2;
+                case PIPE_FORMAT_DXT5_RGBA:
+                case PIPE_FORMAT_DXT5_SRGBA:
+                        return V_008F14_IMG_DATA_FORMAT_BC3;
+                default:
+                        goto out_unknown;
+                }
+        }
+        if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
+                return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
+        } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
+                return V_008F14_IMG_DATA_FORMAT_10_11_11;
+        }
+        /* R8G8Bx_SNORM - TODO CxV8U8 */
+        /* See whether the components are of the same size. */
+        for (i = 1; i < desc->nr_channels; i++) {
+                uniform = uniform && desc->channel[0].size == desc->channel[i].size;
+        }
+        /* Non-uniform formats. */
+        if (!uniform) {
+                switch(desc->nr_channels) {
+                case 3:
+                        if (desc->channel[0].size == 5 &&
+                            desc->channel[1].size == 6 &&
+                            desc->channel[2].size == 5) {
+                                return V_008F14_IMG_DATA_FORMAT_5_6_5;
+                        }
+                        goto out_unknown;
+                case 4:
+                        if (desc->channel[0].size == 5 &&
+                            desc->channel[1].size == 5 &&
+                            desc->channel[2].size == 5 &&
+                            desc->channel[3].size == 1) {
+                                return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
+                        }
+                        if (desc->channel[0].size == 10 &&
+                            desc->channel[1].size == 10 &&
+                            desc->channel[2].size == 10 &&
+                            desc->channel[3].size == 2) {
+                                return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
+                        }
+                        goto out_unknown;
+                }
+                goto out_unknown;
+        }
+        if (first_non_void < 0 || first_non_void > 3)
+                goto out_unknown;
+        /* uniform formats */
+        switch (desc->channel[first_non_void].size) {
+        case 4:
+                switch (desc->nr_channels) {
+#if 0 /* Not supported for render targets */
+                case 2:
+                        return V_008F14_IMG_DATA_FORMAT_4_4;
+#endif
+                case 4:
+                        return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
+                }
+                break;
+        case 8:
+                switch (desc->nr_channels) {
+                case 1:
+                        return V_008F14_IMG_DATA_FORMAT_8;
+                case 2:
+                        return V_008F14_IMG_DATA_FORMAT_8_8;
+                case 4:
+                        return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
+                }
+                break;
+        case 16:
+                switch (desc->nr_channels) {
+                case 1:
+                        return V_008F14_IMG_DATA_FORMAT_16;
+                case 2:
+                        return V_008F14_IMG_DATA_FORMAT_16_16;
+                case 4:
+                        return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
+                }
+                break;
+        case 32:
+                switch (desc->nr_channels) {
+                case 1:
+                        return V_008F14_IMG_DATA_FORMAT_32;
+                case 2:
+                        return V_008F14_IMG_DATA_FORMAT_32_32;
+#if 0 /* Not supported for render targets */
+                case 3:
+                        return V_008F14_IMG_DATA_FORMAT_32_32_32;
+#endif
+                case 4:
+                        return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
+                }
+        }
+out_unknown:
+        /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
+        return ~0;
+}
+static unsigned si_tex_wrap(unsigned wrap)
+{
+        switch (wrap) {
+        default:
+        case PIPE_TEX_WRAP_REPEAT:
+                return V_008F30_SQ_TEX_WRAP;
+        case PIPE_TEX_WRAP_CLAMP:
+                return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
+        case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
+                return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
+        case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
+                return V_008F30_SQ_TEX_CLAMP_BORDER;
+        case PIPE_TEX_WRAP_MIRROR_REPEAT:
+                return V_008F30_SQ_TEX_MIRROR;
+        case PIPE_TEX_WRAP_MIRROR_CLAMP:
+                return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
+        case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
+                return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
+        case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
+                return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
+        }
+}
+static unsigned si_tex_filter(unsigned filter)
+{
+        switch (filter) {
+        default:
+        case PIPE_TEX_FILTER_NEAREST:
+                return V_008F38_SQ_TEX_XY_FILTER_POINT;
+        case PIPE_TEX_FILTER_LINEAR:
+                return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
+        }
+}
+static unsigned si_tex_mipfilter(unsigned filter)
+{
+        switch (filter) {
+        case PIPE_TEX_MIPFILTER_NEAREST:
+                return V_008F38_SQ_TEX_Z_FILTER_POINT;
+        case PIPE_TEX_MIPFILTER_LINEAR:
+                return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
+        default:
+        case PIPE_TEX_MIPFILTER_NONE:
+                return V_008F38_SQ_TEX_Z_FILTER_NONE;
+        }
+}
+static unsigned si_tex_compare(unsigned compare)
+{
+        switch (compare) {
+        default:
+        case PIPE_FUNC_NEVER:
+                return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
+        case PIPE_FUNC_LESS:
+                return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
+        case PIPE_FUNC_EQUAL:
+                return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
+        case PIPE_FUNC_LEQUAL:
+                return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
+        case PIPE_FUNC_GREATER:
+                return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
+        case PIPE_FUNC_NOTEQUAL:
+                return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
+        case PIPE_FUNC_GEQUAL:
+                return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
+        case PIPE_FUNC_ALWAYS:
+                return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
+        }
+}
+static unsigned si_tex_dim(unsigned dim)
+{
+        switch (dim) {
+        default:
+        case PIPE_TEXTURE_1D:
+                return V_008F1C_SQ_RSRC_IMG_1D;
+        case PIPE_TEXTURE_1D_ARRAY:
+                return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
+        case PIPE_TEXTURE_2D:
+        case PIPE_TEXTURE_RECT:
+                return V_008F1C_SQ_RSRC_IMG_2D;
+        case PIPE_TEXTURE_2D_ARRAY:
+                return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
+        case PIPE_TEXTURE_3D:
+                return V_008F1C_SQ_RSRC_IMG_3D;
+        case PIPE_TEXTURE_CUBE:
+                return V_008F1C_SQ_RSRC_IMG_CUBE;
+        }
+}
+/*
+ * Format support testing
+ */
+static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
+{
+        return si_translate_texformat(screen, format, util_format_description(format),
+                                      util_format_get_first_non_void_channel(format)) != ~0U;
+}
+static uint32_t si_translate_vertexformat(struct pipe_screen *screen,
+                                          enum pipe_format format,
+                                          const struct util_format_description *desc,
+                                          int first_non_void)
+{
+        unsigned type = desc->channel[first_non_void].type;
+        int i;
+        if (type == UTIL_FORMAT_TYPE_FIXED)
+                return V_008F0C_BUF_DATA_FORMAT_INVALID;
+        /* See whether the components are of the same size. */
+        for (i = 0; i < desc->nr_channels; i++) {
+                if (desc->channel[first_non_void].size != desc->channel[i].size)
+                        return V_008F0C_BUF_DATA_FORMAT_INVALID;
+        }
+        switch (desc->channel[first_non_void].size) {
+        case 8:
+                switch (desc->nr_channels) {
+                case 1:
+                        return V_008F0C_BUF_DATA_FORMAT_8;
+                case 2:
+                        return V_008F0C_BUF_DATA_FORMAT_8_8;
+                case 3:
+                case 4:
+                        return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
+                }
+                break;
+        case 16:
+                switch (desc->nr_channels) {
+                case 1:
+                        return V_008F0C_BUF_DATA_FORMAT_16;
+                case 2:
+                        return V_008F0C_BUF_DATA_FORMAT_16_16;
+                case 3:
+                case 4:
+                        return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
+                }
+                break;
+        case 32:
+                if (type != UTIL_FORMAT_TYPE_FLOAT)
+                        return V_008F0C_BUF_DATA_FORMAT_INVALID;
+                switch (desc->nr_channels) {
+                case 1:
+                        return V_008F0C_BUF_DATA_FORMAT_32;
+                case 2:
+                        return V_008F0C_BUF_DATA_FORMAT_32_32;
+                case 3:
+                        return V_008F0C_BUF_DATA_FORMAT_32_32_32;
+                case 4:
+                        return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
+                }
+                break;
+        }
+        return V_008F0C_BUF_DATA_FORMAT_INVALID;
+}
+static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
+{
+        const struct util_format_description *desc;
+        int first_non_void;
+        unsigned data_format;
+        desc = util_format_description(format);
+        first_non_void = util_format_get_first_non_void_channel(format);
+        data_format = si_translate_vertexformat(screen, format, desc, first_non_void);
+        return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
+}
+static bool si_is_colorbuffer_format_supported(enum pipe_format format)
+{
+        return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
+                si_translate_colorswap(format) != ~0U;
+}
+static bool si_is_zs_format_supported(enum pipe_format format)
+{
+        return si_translate_dbformat(format) != V_028040_Z_INVALID;
+}
+boolean si_is_format_supported(struct pipe_screen *screen,
+                               enum pipe_format format,
+                               enum pipe_texture_target target,
+                               unsigned sample_count,
+                               unsigned usage)
+{
+        unsigned retval = 0;
+        if (target >= PIPE_MAX_TEXTURE_TYPES) {
+                R600_ERR("r600: unsupported texture type %d\n", target);
+                return FALSE;
+        }
+        if (!util_format_is_supported(format, usage))
+                return FALSE;
+        /* Multisample */
+        if (sample_count > 1)
+                return FALSE;
+        if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
+            si_is_sampler_format_supported(screen, format)) {
+                retval |= PIPE_BIND_SAMPLER_VIEW;
+        }
+        if ((usage & (PIPE_BIND_RENDER_TARGET |
+                      PIPE_BIND_DISPLAY_TARGET |
+                      PIPE_BIND_SCANOUT |
+                      PIPE_BIND_SHARED)) &&
+            si_is_colorbuffer_format_supported(format)) {
+                retval |= usage &
+                          (PIPE_BIND_RENDER_TARGET |
+                           PIPE_BIND_DISPLAY_TARGET |
+                           PIPE_BIND_SCANOUT |
+                           PIPE_BIND_SHARED);
+        }
+        if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
+            si_is_zs_format_supported(format)) {
+                retval |= PIPE_BIND_DEPTH_STENCIL;
+        }
+        if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
+            si_is_vertex_format_supported(screen, format)) {
+                retval |= PIPE_BIND_VERTEX_BUFFER;
+        }
+        if (usage & PIPE_BIND_TRANSFER_READ)
+                retval |= PIPE_BIND_TRANSFER_READ;
+        if (usage & PIPE_BIND_TRANSFER_WRITE)
+                retval |= PIPE_BIND_TRANSFER_WRITE;
+        return retval == usage;
+}
+static unsigned si_tile_mode_index(struct r600_resource_texture *rtex, unsigned level, bool stencil)
+{
+        unsigned tile_mode_index = 0;
+        if (stencil) {
+                tile_mode_index = rtex->surface.stencil_tiling_index[level];
+        } else {
+                tile_mode_index = rtex->surface.tiling_index[level];
+        }
+        return tile_mode_index;
+}
+/*
+ * framebuffer handling
+ */
+static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
+                  const struct pipe_framebuffer_state *state, int cb)
+{
+        struct r600_resource_texture *rtex;
+        struct r600_surface *surf;
+        unsigned level = state->cbufs[cb]->u.tex.level;
+        unsigned pitch, slice;
+        unsigned color_info, color_attrib;
+        unsigned tile_mode_index;
+        unsigned format, swap, ntype, endian;
+        uint64_t offset;
+        const struct util_format_description *desc;
+        int i;
+        unsigned blend_clamp = 0, blend_bypass = 0;
+        unsigned max_comp_size;
+        surf = (struct r600_surface *)state->cbufs[cb];
+        rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
+        offset = rtex->surface.level[level].offset;
+        if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
+                offset += rtex->surface.level[level].slice_size *
+                          state->cbufs[cb]->u.tex.first_layer;
+        }
+        pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
+        slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
+        if (slice) {
+                slice = slice - 1;
+        }
+        tile_mode_index = si_tile_mode_index(rtex, level, false);
+        desc = util_format_description(surf->base.format);
+        for (i = 0; i < 4; i++) {
+                if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
+                        break;
+                }
+        }
+        if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
+                ntype = V_028C70_NUMBER_FLOAT;
+        } else {
+                ntype = V_028C70_NUMBER_UNORM;
+                if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
+                        ntype = V_028C70_NUMBER_SRGB;
+                else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
+                        if (desc->channel[i].pure_integer) {
+                                ntype = V_028C70_NUMBER_SINT;
+                        } else {
+                                assert(desc->channel[i].normalized);
+                                ntype = V_028C70_NUMBER_SNORM;
+                        }
+                } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
+                        if (desc->channel[i].pure_integer) {
+                                ntype = V_028C70_NUMBER_UINT;
+                        } else {
+                                assert(desc->channel[i].normalized);
+                                ntype = V_028C70_NUMBER_UNORM;
+                        }
+                }
+        }
+        format = si_translate_colorformat(surf->base.format);
+        if (format == V_028C70_COLOR_INVALID) {
+                R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
+        }
+        assert(format != V_028C70_COLOR_INVALID);
+        swap = si_translate_colorswap(surf->base.format);
+        if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
+                endian = V_028C70_ENDIAN_NONE;
+        } else {
+                endian = si_colorformat_endian_swap(format);
+        }
+        /* blend clamp should be set for all NORM/SRGB types */
+        if (ntype == V_028C70_NUMBER_UNORM ||
+            ntype == V_028C70_NUMBER_SNORM ||
+            ntype == V_028C70_NUMBER_SRGB)
+                blend_clamp = 1;
+        /* set blend bypass according to docs if SINT/UINT or
+/24 COLOR variants */
+        if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
+            format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
+            format == V_028C70_COLOR_X24_8_32_FLOAT) {
+                blend_clamp = 0;
+                blend_bypass = 1;
+        }
+        color_info = S_028C70_FORMAT(format) |
+                S_028C70_COMP_SWAP(swap) |
+                S_028C70_BLEND_CLAMP(blend_clamp) |
+                S_028C70_BLEND_BYPASS(blend_bypass) |
+                S_028C70_NUMBER_TYPE(ntype) |
+                S_028C70_ENDIAN(endian);
+        color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
+                S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
+        offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
+        offset >>= 8;
+        /* FIXME handle enabling of CB beyond BASE8 which has different offset */
+        si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
+        si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset);
+        si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, S_028C64_TILE_MAX(pitch));
+        si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice));
+        if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
+                si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 0x00000000);
+        } else {
+                si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
+                               S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
+                               S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
+        }
+        si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
+        si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib);
+        /* set CB_COLOR1_INFO for possible dual-src blending */
+        if (state->nr_cbufs == 1) {
+                assert(cb == 0);
+                si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, color_info);
+        }
+        /* Determine pixel shader export format */
+        max_comp_size = si_colorformat_max_comp_size(format);
+        if (ntype == V_028C70_NUMBER_SRGB ||
+            ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
+             max_comp_size <= 10) ||
+            (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
+                rctx->export_16bpc |= 1 << cb;
+                /* set SPI_SHADER_COL_FORMAT for possible dual-src blending */
+                if (state->nr_cbufs == 1)
+                        rctx->export_16bpc |= 1 << 1;
+        }
+}
+static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
+                  const struct pipe_framebuffer_state *state)
+{
+        struct r600_screen *rscreen = rctx->screen;
+        struct r600_resource_texture *rtex;
+        struct r600_surface *surf;
+        unsigned level, pitch, slice, format, tile_mode_index, array_mode;
+        unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
+        uint32_t z_info, s_info, db_depth_info;
+        uint64_t z_offs, s_offs;
+        if (state->zsbuf == NULL) {
+                si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID));
+                si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
+                return;
+        }
+        surf = (struct r600_surface *)state->zsbuf;
+        level = surf->base.u.tex.level;
+        rtex = (struct r600_resource_texture*)surf->base.texture;
+        format = si_translate_dbformat(rtex->real_format);
+        if (format == V_028040_Z_INVALID) {
+                R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->real_format);
+        }
+        assert(format != V_028040_Z_INVALID);
+        s_offs = z_offs = r600_resource_va(rctx->context.screen, surf->base.texture);
+        z_offs += rtex->surface.level[level].offset;
+        s_offs += rtex->surface.stencil_level[level].offset;
+        z_offs >>= 8;
+        s_offs >>= 8;
+        pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
+        slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
+        if (slice) {
+                slice = slice - 1;
+        }
+        db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
+        z_info = S_028040_FORMAT(format);
+        if (rtex->surface.flags & RADEON_SURF_SBUFFER)
+                s_info = S_028044_FORMAT(V_028044_STENCIL_8);
+        else
+                s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
+        if (rctx->chip_class >= CIK) {
+                switch (rtex->surface.level[level].mode) {
+                case RADEON_SURF_MODE_2D:
+                        array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
+                        break;
+                case RADEON_SURF_MODE_1D:
+                case RADEON_SURF_MODE_LINEAR_ALIGNED:
+                case RADEON_SURF_MODE_LINEAR:
+                default:
+                        array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
+                        break;
+                }
+                tile_split = rtex->surface.tile_split;
+                stile_split = rtex->surface.stencil_tile_split;
+                macro_aspect = rtex->surface.mtilea;
+                bankw = rtex->surface.bankw;
+                bankh = rtex->surface.bankh;
+                tile_split = cik_tile_split(tile_split);
+                stile_split = cik_tile_split(stile_split);
+                macro_aspect = cik_macro_tile_aspect(macro_aspect);
+                bankw = cik_bank_wh(bankw);
+                bankh = cik_bank_wh(bankh);
+                nbanks = cik_num_banks(rscreen->tiling_info.num_banks);
+                pipe_config = cik_db_pipe_config(rscreen->info.r600_num_tile_pipes,
+                                                 rscreen->info.r600_num_backends);
+                db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
+                        S_02803C_PIPE_CONFIG(pipe_config) |
+                        S_02803C_BANK_WIDTH(bankw) |
+                        S_02803C_BANK_HEIGHT(bankh) |
+                        S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
+                        S_02803C_NUM_BANKS(nbanks);
+                z_info |= S_028040_TILE_SPLIT(tile_split);
+                s_info |= S_028044_TILE_SPLIT(stile_split);
+        } else {
+                tile_mode_index = si_tile_mode_index(rtex, level, false);
+                z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
+                tile_mode_index = si_tile_mode_index(rtex, level, true);
+                s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
+        }
+        si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
+                       S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
+                       S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
+        si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, db_depth_info);
+        si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
+        si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
+        si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
+        si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
+        si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs);
+        si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs);
+        si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs);
+        si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
+        si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
+}
+static void si_set_framebuffer_state(struct pipe_context *ctx,
+                                     const struct pipe_framebuffer_state *state)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
+        uint32_t tl, br;
+        int tl_x, tl_y, br_x, br_y;
+        if (pm4 == NULL)
+                return;
+        si_pm4_inval_fb_cache(pm4, state->nr_cbufs);
+        if (state->zsbuf)
+                si_pm4_inval_zsbuf_cache(pm4);
+        util_copy_framebuffer_state(&rctx->framebuffer, state);
+        /* build states */
+        rctx->export_16bpc = 0;
+        for (int i = 0; i < state->nr_cbufs; i++) {
+                si_cb(rctx, pm4, state, i);
+        }
+        assert(!(rctx->export_16bpc & ~0xff));
+        si_db(rctx, pm4, state);
+        tl_x = 0;
+        tl_y = 0;
+        br_x = state->width;
+        br_y = state->height;
+        tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
+        br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
+        si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl);
+        si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br);
+        si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
+        si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
+        si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl);
+        si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br);
+        si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
+        si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
+        si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000);
+        si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
+        si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0x00000000);
+        si_pm4_set_state(rctx, framebuffer, pm4);
+        si_update_fb_rs_state(rctx);
+        si_update_fb_blend_state(rctx);
+}
+/*
+ * shaders
+ */
+/* Compute the key for the hw shader variant */
+static INLINE void si_shader_selector_key(struct pipe_context *ctx,
+                                          struct si_pipe_shader_selector *sel,
+                                          union si_shader_key *key)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        memset(key, 0, sizeof(*key));
+        if (sel->type == PIPE_SHADER_VERTEX) {
+                unsigned i;
+                if (!rctx->vertex_elements)
+                        return;
+                for (i = 0; i < rctx->vertex_elements->count; ++i)
+                        key->vs.instance_divisors[i] = rctx->vertex_elements->elements[i].instance_divisor;
+        } else if (sel->type == PIPE_SHADER_FRAGMENT) {
+                if (sel->fs_write_all)
+                        key->ps.nr_cbufs = rctx->framebuffer.nr_cbufs;
+                key->ps.export_16bpc = rctx->export_16bpc;
+                if (rctx->queued.named.rasterizer) {
+                        key->ps.color_two_side = rctx->queued.named.rasterizer->two_side;
+                        key->ps.flatshade = rctx->queued.named.rasterizer->flatshade;
+                }
+                if (rctx->queued.named.dsa) {
+                        key->ps.alpha_func = rctx->queued.named.dsa->alpha_func;
+                        key->ps.alpha_ref = rctx->queued.named.dsa->alpha_ref;
+                } else {
+                        key->ps.alpha_func = PIPE_FUNC_ALWAYS;
+                }
+        }
+}
+/* Select the hw shader variant depending on the current state.
+ * (*dirty) is set to 1 if current variant was changed */
+int si_shader_select(struct pipe_context *ctx,
+                     struct si_pipe_shader_selector *sel,
+                     unsigned *dirty)
+{
+        union si_shader_key key;
+        struct si_pipe_shader * shader = NULL;
+        int r;
+        si_shader_selector_key(ctx, sel, &key);
+        /* Check if we don't need to change anything.
+         * This path is also used for most shaders that don't need multiple
+         * variants, it will cost just a computation of the key and this
+         * test. */
+        if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
+                return 0;
+        }
+        /* lookup if we have other variants in the list */
+        if (sel->num_shaders > 1) {
+                struct si_pipe_shader *p = sel->current, *c = p->next_variant;
+                while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
+                        p = c;
+                        c = c->next_variant;
+                }
+                if (c) {
+                        p->next_variant = c->next_variant;
+                        shader = c;
+                }
+        }
+        if (unlikely(!shader)) {
+                shader = CALLOC(1, sizeof(struct si_pipe_shader));
+                shader->selector = sel;
+                shader->key = key;
+                r = si_pipe_shader_create(ctx, shader);
+                if (unlikely(r)) {
+                        R600_ERR("Failed to build shader variant (type=%u) %d\n",
+                                 sel->type, r);
+                        sel->current = NULL;
+                        FREE(shader);
+                        return r;
+                }
+                /* We don't know the value of fs_write_all property until we built
+                 * at least one variant, so we may need to recompute the key (include
+                 * rctx->framebuffer.nr_cbufs) after building first variant. */
+                if (sel->type == PIPE_SHADER_FRAGMENT &&
+                    sel->num_shaders == 0 &&
+                    shader->shader.fs_write_all) {
+                        sel->fs_write_all = 1;
+                        si_shader_selector_key(ctx, sel, &shader->key);
+                }
+                sel->num_shaders++;
+        }
+        if (dirty)
+                *dirty = 1;
+        shader->next_variant = sel->current;
+        sel->current = shader;
+        return 0;
+}
+static void *si_create_shader_state(struct pipe_context *ctx,
+                                    const struct pipe_shader_state *state,
+                                    unsigned pipe_shader_type)
+{
+        struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
+        int r;
+        sel->type = pipe_shader_type;
+        sel->tokens = tgsi_dup_tokens(state->tokens);
+        sel->so = state->stream_output;
+        r = si_shader_select(ctx, sel, NULL);
+        if (r) {
+            free(sel);
+            return NULL;
+        }
+        return sel;
+}
+static void *si_create_fs_state(struct pipe_context *ctx,
+                                const struct pipe_shader_state *state)
+{
+        return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
+}
+static void *si_create_vs_state(struct pipe_context *ctx,
+                                const struct pipe_shader_state *state)
+{
+        return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
+}
+static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct si_pipe_shader_selector *sel = state;
+        if (rctx->vs_shader == sel)
+                return;
+        rctx->vs_shader = sel;
+        if (sel && sel->current)
+                si_pm4_bind_state(rctx, vs, sel->current->pm4);
+        else
+                si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
+}
+static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct si_pipe_shader_selector *sel = state;
+        if (rctx->ps_shader == sel)
+                return;
+        rctx->ps_shader = sel;
+        if (sel && sel->current)
+                si_pm4_bind_state(rctx, ps, sel->current->pm4);
+        else
+                si_pm4_bind_state(rctx, ps, rctx->dummy_pixel_shader->pm4);
+}
+static void si_delete_shader_selector(struct pipe_context *ctx,
+                                      struct si_pipe_shader_selector *sel)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct si_pipe_shader *p = sel->current, *c;
+        while (p) {
+                c = p->next_variant;
+                si_pm4_delete_state(rctx, vs, p->pm4);
+                si_pipe_shader_destroy(ctx, p);
+                free(p);
+                p = c;
+        }
+        free(sel->tokens);
+        free(sel);
+ }
+static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
+        if (rctx->vs_shader == sel) {
+                rctx->vs_shader = NULL;
+        }
+        si_delete_shader_selector(ctx, sel);
+}
+static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
+        if (rctx->ps_shader == sel) {
+                rctx->ps_shader = NULL;
+        }
+        si_delete_shader_selector(ctx, sel);
+}
+/*
+ * Samplers
+ */
+static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
+                                                        struct pipe_resource *texture,
+                                                        const struct pipe_sampler_view *state)
+{
+        struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
+        struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
+        const struct util_format_description *desc;
+        unsigned format, num_format;
+        uint32_t pitch = 0;
+        unsigned char state_swizzle[4], swizzle[4];
+        unsigned height, depth, width;
+        enum pipe_format pipe_format = state->format;
+        struct radeon_surface_level *surflevel;
+        int first_non_void;
+        uint64_t va;
+        if (view == NULL)
+                return NULL;
+        /* initialize base object */
+        view->base = *state;
+        view->base.texture = NULL;
+        pipe_reference(NULL, &texture->reference);
+        view->base.texture = texture;
+        view->base.reference.count = 1;
+        view->base.context = ctx;
+        state_swizzle[0] = state->swizzle_r;
+        state_swizzle[1] = state->swizzle_g;
+        state_swizzle[2] = state->swizzle_b;
+        state_swizzle[3] = state->swizzle_a;
+        surflevel = tmp->surface.level;
+        /* Texturing with separate depth and stencil. */
+        if (tmp->is_depth && !tmp->is_flushing_texture) {
+                switch (pipe_format) {
+                case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
+                        pipe_format = PIPE_FORMAT_Z32_FLOAT;
+                        break;
+                case PIPE_FORMAT_X8Z24_UNORM:
+                case PIPE_FORMAT_S8_UINT_Z24_UNORM:
+                        /* Z24 is always stored like this. */
+                        pipe_format = PIPE_FORMAT_Z24X8_UNORM;
+                        break;
+                case PIPE_FORMAT_X24S8_UINT:
+                case PIPE_FORMAT_S8X24_UINT:
+                case PIPE_FORMAT_X32_S8X24_UINT:
+                        pipe_format = PIPE_FORMAT_S8_UINT;
+                        surflevel = tmp->surface.stencil_level;
+                        break;
+                default:;
+                }
+        }
+        desc = util_format_description(pipe_format);
+        if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
+                const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
+                const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
+                switch (pipe_format) {
+                case PIPE_FORMAT_S8_UINT_Z24_UNORM:
+                case PIPE_FORMAT_X24S8_UINT:
+                case PIPE_FORMAT_X32_S8X24_UINT:
+                case PIPE_FORMAT_X8Z24_UNORM:
+                        util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
+                        break;
+                default:
+                        util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
+                }
+        } else {
+                util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
+        }
+        first_non_void = util_format_get_first_non_void_channel(pipe_format);
+        switch (pipe_format) {
+        case PIPE_FORMAT_S8_UINT_Z24_UNORM:
+                num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
+                break;
+        default:
+                if (first_non_void < 0) {
+                        if (util_format_is_compressed(pipe_format)) {
+                                switch (pipe_format) {
+                                case PIPE_FORMAT_DXT1_SRGB:
+                                case PIPE_FORMAT_DXT1_SRGBA:
+                                case PIPE_FORMAT_DXT3_SRGBA:
+                                case PIPE_FORMAT_DXT5_SRGBA:
+                                        num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
+                                        break;
+                                case PIPE_FORMAT_RGTC1_SNORM:
+                                case PIPE_FORMAT_LATC1_SNORM:
+                                case PIPE_FORMAT_RGTC2_SNORM:
+                                case PIPE_FORMAT_LATC2_SNORM:
+                                        num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
+                                        break;
+                                default:
+                                        num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
+                                        break;
+                                }
+                        } else {
+                                num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
+                        }
+                } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
+                        num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
+                } else {
+                        num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
+                        switch (desc->channel[first_non_void].type) {
+                        case UTIL_FORMAT_TYPE_FLOAT:
+                                num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
+                                break;
+                        case UTIL_FORMAT_TYPE_SIGNED:
+                                if (desc->channel[first_non_void].normalized)
+                                        num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
+                                else if (desc->channel[first_non_void].pure_integer)
+                                        num_format = V_008F14_IMG_NUM_FORMAT_SINT;
+                                else
+                                        num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
+                                break;
+                        case UTIL_FORMAT_TYPE_UNSIGNED:
+                                if (desc->channel[first_non_void].normalized)
+                                        num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
+                                else if (desc->channel[first_non_void].pure_integer)
+                                        num_format = V_008F14_IMG_NUM_FORMAT_UINT;
+                                else
+                                        num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
+                        }
+                }
+        }
+        format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
+        if (format == ~0) {
+                format = 0;
+        }
+        view->resource = &tmp->resource;
+        /* not supported any more */
+        //endian = si_colorformat_endian_swap(format);
+        width = surflevel[0].npix_x;
+        height = surflevel[0].npix_y;
+        depth = surflevel[0].npix_z;
+        pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
+        if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
+                height = 1;
+                depth = texture->array_size;
+        } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
+                depth = texture->array_size;
+        }
+        va = r600_resource_va(ctx->screen, texture);
+        va += surflevel[0].offset;
+        view->state[0] = va >> 8;
+        view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
+                          S_008F14_DATA_FORMAT(format) |
+                          S_008F14_NUM_FORMAT(num_format));
+        view->state[2] = (S_008F18_WIDTH(width - 1) |
+                          S_008F18_HEIGHT(height - 1));
+        view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
+                          S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
+                          S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
+                          S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
+                          S_008F1C_BASE_LEVEL(state->u.tex.first_level) |
+                          S_008F1C_LAST_LEVEL(state->u.tex.last_level) |
+                          S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
+                          S_008F1C_POW2_PAD(texture->last_level > 0) |
+                          S_008F1C_TYPE(si_tex_dim(texture->target)));
+        view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
+        view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
+                          S_008F24_LAST_ARRAY(state->u.tex.last_layer));
+        view->state[6] = 0;
+        view->state[7] = 0;
+        return &view->base;
+}
+static void si_sampler_view_destroy(struct pipe_context *ctx,
+                                    struct pipe_sampler_view *state)
+{
+        struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
+        pipe_resource_reference(&state->texture, NULL);
+        FREE(resource);
+}
+static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
+{
+        return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
+               wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
+               (linear_filter &&
+                (wrap == PIPE_TEX_WRAP_CLAMP ||
+                 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
+}
+static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
+{
+        bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
+                             state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
+        return (state->border_color.ui[0] || state->border_color.ui[1] ||
+                state->border_color.ui[2] || state->border_color.ui[3]) &&
+               (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
+                wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
+                wrap_mode_uses_border_color(state->wrap_r, linear_filter));
+}
+static void *si_create_sampler_state(struct pipe_context *ctx,
+                                     const struct pipe_sampler_state *state)
+{
+        struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
+        unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
+        unsigned border_color_type;
+        if (rstate == NULL) {
+                return NULL;
+        }
+        if (sampler_state_needs_border_color(state))
+                border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
+        else
+                border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
+        rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
+                          S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
+                          S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
+                          (state->max_anisotropy & 0x7) << 9 | /* XXX */
+                          S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
+                          S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
+                          aniso_flag_offset << 16 | /* XXX */
+                          S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
+        rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
+                          S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
+        rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
+                          S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
+                          S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
+                          S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
+        rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
+        if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
+                memcpy(rstate->border_color, state->border_color.ui,
+                       sizeof(rstate->border_color));
+        }
+        return rstate;
+}
+static struct si_pm4_state *si_set_sampler_view(struct r600_context *rctx,
+                                                unsigned count,
+                                                struct pipe_sampler_view **views,
+                                                struct r600_textures_info *samplers,
+                                                unsigned user_data_reg)
+{
+        struct si_pipe_sampler_view **resource = (struct si_pipe_sampler_view **)views;
+        struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
+        int i, j;
+        if (!count)
+                goto out;
+        si_pm4_inval_texture_cache(pm4);
+        si_pm4_sh_data_begin(pm4);
+        for (i = 0; i < count; i++) {
+                pipe_sampler_view_reference(
+                        (struct pipe_sampler_view **)&samplers->views[i],
+                        views[i]);
+                if (views[i]) {
+                        struct r600_resource_texture *rtex =
+                                (struct r600_resource_texture*)views[i]->texture;
+                        if (rtex->is_depth && !rtex->is_flushing_texture) {
+                                samplers->depth_texture_mask |= 1 << i;
+                        } else {
+                                samplers->depth_texture_mask &= ~(1 << i);
+                        }
+                        si_pm4_add_bo(pm4, resource[i]->resource, RADEON_USAGE_READ);
+                } else {
+                        samplers->depth_texture_mask &= ~(1 << i);
+                }
+                for (j = 0; j < Elements(resource[i]->state); ++j) {
+                        si_pm4_sh_data_add(pm4, resource[i] ? resource[i]->state[j] : 0);
+                }
+        }
+        for (i = count; i < NUM_TEX_UNITS; i++) {
+                if (samplers->views[i])
+                        pipe_sampler_view_reference((struct pipe_sampler_view **)&samplers->views[i], NULL);
+        }
+        si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_RESOURCE);
+out:
+        rctx->ps_samplers.n_views = count;
+        return pm4;
+}
+static void si_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
+                                   struct pipe_sampler_view **views)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct si_pm4_state *pm4;
+        pm4 = si_set_sampler_view(rctx, count, views, &rctx->vs_samplers,
+                            R_00B130_SPI_SHADER_USER_DATA_VS_0);
+        si_pm4_set_state(rctx, vs_sampler_views, pm4);
+}
+static void si_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
+                                   struct pipe_sampler_view **views)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct si_pm4_state *pm4;
+        pm4 = si_set_sampler_view(rctx, count, views, &rctx->ps_samplers,
+                                  R_00B030_SPI_SHADER_USER_DATA_PS_0);
+        si_pm4_set_state(rctx, ps_sampler_views, pm4);
+}
+static struct si_pm4_state *si_bind_sampler(struct r600_context *rctx, unsigned count,
+                                            void **states,
+                                            struct r600_textures_info *samplers,
+                                            unsigned user_data_reg)
+{
+        struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
+        struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
+        uint32_t *border_color_table = NULL;
+        int i, j;
+        if (!count)
+                goto out;
+        si_pm4_inval_texture_cache(pm4);
+        si_pm4_sh_data_begin(pm4);
+        for (i = 0; i < count; i++) {
+                if (rstates[i] &&
+                    G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
+                    V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
+                        if (!rctx->border_color_table ||
+                            ((rctx->border_color_offset + count - i) &
+                             C_008F3C_BORDER_COLOR_PTR)) {
+                                si_resource_reference(&rctx->border_color_table, NULL);
+                                rctx->border_color_offset = 0;
+                                rctx->border_color_table =
+                                        si_resource_create_custom(&rctx->screen->screen,
+                                                                  PIPE_USAGE_STAGING,
+* 4 * 4);
+                        }
+                        if (!border_color_table) {
+                                border_color_table =
+                                        rctx->ws->buffer_map(rctx->border_color_table->cs_buf,
+                                                             rctx->cs,
+                                                             PIPE_TRANSFER_WRITE |
+                                                             PIPE_TRANSFER_UNSYNCHRONIZED);
+                        }
+                        for (j = 0; j < 4; j++) {
+                                border_color_table[4 * rctx->border_color_offset + j] =
+                                        util_le32_to_cpu(rstates[i]->border_color[j]);
+                        }
+                        rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
+                        rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(rctx->border_color_offset++);
+                }
+                for (j = 0; j < Elements(rstates[i]->val); ++j) {
+                        si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0);
+                }
+        }
+        si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER);
+        if (border_color_table) {
+                uint64_t va_offset =
+                        r600_resource_va(&rctx->screen->screen,
+                                         (void*)rctx->border_color_table);
+                si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
+                if (rctx->chip_class >= CIK)
+                        si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
+                rctx->ws->buffer_unmap(rctx->border_color_table->cs_buf);
+                si_pm4_add_bo(pm4, rctx->border_color_table, RADEON_USAGE_READ);
+        }
+        memcpy(samplers->samplers, states, sizeof(void*) * count);
+out:
+        samplers->n_samplers = count;
+        return pm4;
+}
+static void si_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct si_pm4_state *pm4;
+        pm4 = si_bind_sampler(rctx, count, states, &rctx->vs_samplers,
+                              R_00B130_SPI_SHADER_USER_DATA_VS_0);
+        si_pm4_set_state(rctx, vs_sampler, pm4);
+}
+static void si_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct si_pm4_state *pm4;
+        pm4 = si_bind_sampler(rctx, count, states, &rctx->ps_samplers,
+                              R_00B030_SPI_SHADER_USER_DATA_PS_0);
+        si_pm4_set_state(rctx, ps_sampler, pm4);
+}
+static void si_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
+{
+}
+static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
+{
+        free(state);
+}
+/*
+ * Constants
+ */
+static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
+                                   struct pipe_constant_buffer *input)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
+        struct pipe_constant_buffer *cb;
+        const uint8_t *ptr;
+        /* Note that the state tracker can unbind constant buffers by
+         * passing NULL here.
+         */
+        if (unlikely(!input || (!input->buffer && !input->user_buffer))) {
+                state->enabled_mask &= ~(1 << index);
+                state->dirty_mask &= ~(1 << index);
+                pipe_resource_reference(&state->cb[index].buffer, NULL);
+                return;
+        }
+        cb = &state->cb[index];
+        cb->buffer_size = input->buffer_size;
+        ptr = input->user_buffer;
+        if (ptr) {
+                r600_upload_const_buffer(rctx,
+                                (struct si_resource**)&cb->buffer, ptr,
+                                cb->buffer_size, &cb->buffer_offset);
+        } else {
+                /* Setup the hw buffer. */
+                cb->buffer_offset = input->buffer_offset;
+                pipe_resource_reference(&cb->buffer, input->buffer);
+        }
+        state->enabled_mask |= 1 << index;
+        state->dirty_mask |= 1 << index;
+}
+/*
+ * Vertex elements & buffers
+ */
+static void *si_create_vertex_elements(struct pipe_context *ctx,
+                                       unsigned count,
+                                       const struct pipe_vertex_element *elements)
+{
+        struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
+        int i;
+        assert(count < PIPE_MAX_ATTRIBS);
+        if (!v)
+                return NULL;
+        v->count = count;
+        for (i = 0; i < count; ++i) {
+                const struct util_format_description *desc;
+                unsigned data_format, num_format;
+                int first_non_void;
+                desc = util_format_description(elements[i].src_format);
+                first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
+                data_format = si_translate_vertexformat(ctx->screen, elements[i].src_format,
+                                                        desc, first_non_void);
+                switch (desc->channel[first_non_void].type) {
+                case UTIL_FORMAT_TYPE_FIXED:
+                        num_format = V_008F0C_BUF_NUM_FORMAT_USCALED; /* XXX */
+                        break;
+                case UTIL_FORMAT_TYPE_SIGNED:
+                        if (desc->channel[first_non_void].normalized)
+                                num_format = V_008F0C_BUF_NUM_FORMAT_SNORM;
+                        else if (desc->channel[first_non_void].pure_integer)
+                                num_format = V_008F0C_BUF_NUM_FORMAT_SINT;
+                        else
+                                num_format = V_008F0C_BUF_NUM_FORMAT_SSCALED;
+                        break;
+                case UTIL_FORMAT_TYPE_UNSIGNED:
+                        if (desc->channel[first_non_void].normalized)
+                                num_format = V_008F0C_BUF_NUM_FORMAT_UNORM;
+                        else if (desc->channel[first_non_void].pure_integer)
+                                num_format = V_008F0C_BUF_NUM_FORMAT_UINT;
+                        else
+                                num_format = V_008F0C_BUF_NUM_FORMAT_USCALED;
+                        break;
+                case UTIL_FORMAT_TYPE_FLOAT:
+                default:
+                        num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
+                }
+                v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
+                                   S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
+                                   S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
+                                   S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
+                                   S_008F0C_NUM_FORMAT(num_format) |
+                                   S_008F0C_DATA_FORMAT(data_format);
+        }
+        memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
+        return v;
+}
+static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct si_vertex_element *v = (struct si_vertex_element*)state;
+        rctx->vertex_elements = v;
+}
+static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        if (rctx->vertex_elements == state)
+                rctx->vertex_elements = NULL;
+        FREE(state);
+}
+static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count,
+                                  const struct pipe_vertex_buffer *buffers)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        util_set_vertex_buffers_count(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, start_slot, count);
+}
+static void si_set_index_buffer(struct pipe_context *ctx,
+                                const struct pipe_index_buffer *ib)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        if (ib) {
+                pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
+                memcpy(&rctx->index_buffer, ib, sizeof(*ib));
+        } else {
+                pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
+        }
+}
+/*
+ * Misc
+ */
+static void si_set_polygon_stipple(struct pipe_context *ctx,
+                                   const struct pipe_poly_stipple *state)
+{
+}
+static void si_texture_barrier(struct pipe_context *ctx)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
+        if (pm4 == NULL)
+                return;
+        si_pm4_inval_texture_cache(pm4);
+        si_pm4_inval_fb_cache(pm4, rctx->framebuffer.nr_cbufs);
+        si_pm4_set_state(rctx, texture_barrier, pm4);
+}
+void si_init_state_functions(struct r600_context *rctx)
+{
+        rctx->context.create_blend_state = si_create_blend_state;
+        rctx->context.bind_blend_state = si_bind_blend_state;
+        rctx->context.delete_blend_state = si_delete_blend_state;
+        rctx->context.set_blend_color = si_set_blend_color;
+        rctx->context.create_rasterizer_state = si_create_rs_state;
+        rctx->context.bind_rasterizer_state = si_bind_rs_state;
+        rctx->context.delete_rasterizer_state = si_delete_rs_state;
+        rctx->context.create_depth_stencil_alpha_state = si_create_dsa_state;
+        rctx->context.bind_depth_stencil_alpha_state = si_bind_dsa_state;
+        rctx->context.delete_depth_stencil_alpha_state = si_delete_dsa_state;
+        rctx->custom_dsa_flush_depth_stencil = si_create_db_flush_dsa(rctx, true, true);
+        rctx->custom_dsa_flush_depth = si_create_db_flush_dsa(rctx, true, false);
+        rctx->custom_dsa_flush_stencil = si_create_db_flush_dsa(rctx, false, true);
+        rctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(rctx, false, false);
+        rctx->context.set_clip_state = si_set_clip_state;
+        rctx->context.set_scissor_states = si_set_scissor_states;
+        rctx->context.set_viewport_states = si_set_viewport_states;
+        rctx->context.set_stencil_ref = si_set_pipe_stencil_ref;
+        rctx->context.set_framebuffer_state = si_set_framebuffer_state;
+        rctx->context.create_vs_state = si_create_vs_state;
+        rctx->context.create_fs_state = si_create_fs_state;
+        rctx->context.bind_vs_state = si_bind_vs_shader;
+        rctx->context.bind_fs_state = si_bind_ps_shader;
+        rctx->context.delete_vs_state = si_delete_vs_shader;
+        rctx->context.delete_fs_state = si_delete_ps_shader;
+        rctx->context.create_sampler_state = si_create_sampler_state;
+        rctx->context.bind_vertex_sampler_states = si_bind_vs_sampler;
+        rctx->context.bind_fragment_sampler_states = si_bind_ps_sampler;
+        rctx->context.delete_sampler_state = si_delete_sampler_state;
+        rctx->context.create_sampler_view = si_create_sampler_view;
+        rctx->context.set_vertex_sampler_views = si_set_vs_sampler_view;
+        rctx->context.set_fragment_sampler_views = si_set_ps_sampler_view;
+        rctx->context.sampler_view_destroy = si_sampler_view_destroy;
+        rctx->context.set_sample_mask = si_set_sample_mask;
+        rctx->context.set_constant_buffer = si_set_constant_buffer;
+        rctx->context.create_vertex_elements_state = si_create_vertex_elements;
+        rctx->context.bind_vertex_elements_state = si_bind_vertex_elements;
+        rctx->context.delete_vertex_elements_state = si_delete_vertex_element;
+        rctx->context.set_vertex_buffers = si_set_vertex_buffers;
+        rctx->context.set_index_buffer = si_set_index_buffer;
+        rctx->context.create_stream_output_target = si_create_so_target;
+        rctx->context.stream_output_target_destroy = si_so_target_destroy;
+        rctx->context.set_stream_output_targets = si_set_so_targets;
+        rctx->context.texture_barrier = si_texture_barrier;
+        rctx->context.set_polygon_stipple = si_set_polygon_stipple;
+        rctx->context.draw_vbo = si_draw_vbo;
+}
+void si_init_config(struct r600_context *rctx)
+{
+        struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
+        if (pm4 == NULL)
+                return;
+        si_cmd_context_control(pm4);
+        si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
+        si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
+        si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
+        si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
+        si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
+        si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
+        si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
+        si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
+        si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
+        si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
+        si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
+        si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
+        si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
+        si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0);
+        si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
+        si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
+        si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
+        si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
+        si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
+                       S_028AA8_SWITCH_ON_EOP(1) |
+                       S_028AA8_PARTIAL_VS_WAVE_ON(1) |
+                       S_028AA8_PRIMGROUP_SIZE(63));
+        si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
+        si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
+        if (rctx->chip_class < CIK)
+                si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
+                               S_008A14_CLIP_VTX_REORDER_ENA(1));
+        si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0);
+        si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
+        si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
+        si_pm4_set_reg(pm4, R_028804_DB_EQAA, 0x110000);
+        si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
+        if (rctx->chip_class >= CIK) {
+                switch (rctx->screen->family) {
+                case CHIP_BONAIRE:
+                        si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
+                        si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
+                        break;
+                case CHIP_KAVERI:
+                        /* XXX todo */
+                case CHIP_KABINI:
+                        /* XXX todo */
+                default:
+                        si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
+                        si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
+                        break;
+                }
+        } else {
+                switch (rctx->screen->family) {
+                case CHIP_TAHITI:
+                case CHIP_PITCAIRN:
+                        si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
+                        break;
+                case CHIP_VERDE:
+                        si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
+                        break;
+                case CHIP_OLAND:
+                        si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
+                        break;
+                case CHIP_HAINAN:
+                        si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
+                        break;
+                default:
+                        si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
+                        break;
+                }
+        }
+        si_pm4_set_state(rctx, init, pm4);
+}

 /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/si_state.h
 ,0 → 1,175
+/*
+ * Copyright 2012 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Christian König <christian.koenig@amd.com>
+ */
+#ifndef SI_STATE_H
+#define SI_STATE_H
+#include "radeonsi_pm4.h"
+struct si_state_blend {
+        struct si_pm4_state     pm4;
+        uint32_t                cb_target_mask;
+        uint32_t                cb_color_control;
+};
+struct si_state_viewport {
+        struct si_pm4_state             pm4;
+        struct pipe_viewport_state      viewport;
+};
+struct si_state_rasterizer {
+        struct si_pm4_state     pm4;
+        bool                    flatshade;
+        bool                    two_side;
+        unsigned                sprite_coord_enable;
+        unsigned                pa_sc_line_stipple;
+        unsigned                pa_su_sc_mode_cntl;
+        unsigned                pa_cl_clip_cntl;
+        unsigned                pa_cl_vs_out_cntl;
+        unsigned                clip_plane_enable;
+        float                   offset_units;
+        float                   offset_scale;
+};
+struct si_state_dsa {
+        struct si_pm4_state     pm4;
+        float                   alpha_ref;
+        unsigned                alpha_func;
+        unsigned                db_render_override;
+        unsigned                db_render_control;
+        uint8_t                 valuemask[2];
+        uint8_t                 writemask[2];
+};
+struct si_vertex_element
+{
+        unsigned                        count;
+        uint32_t                        rsrc_word3[PIPE_MAX_ATTRIBS];
+        struct pipe_vertex_element      elements[PIPE_MAX_ATTRIBS];
+};
+union si_state {
+        struct {
+                struct si_pm4_state             *sync;
+                struct si_pm4_state             *init;
+                struct si_state_blend           *blend;
+                struct si_pm4_state             *blend_color;
+                struct si_pm4_state             *clip;
+                struct si_pm4_state             *scissor;
+                struct si_state_viewport        *viewport;
+                struct si_pm4_state             *framebuffer;
+                struct si_state_rasterizer      *rasterizer;
+                struct si_state_dsa             *dsa;
+                struct si_pm4_state             *fb_rs;
+                struct si_pm4_state             *fb_blend;
+                struct si_pm4_state             *dsa_stencil_ref;
+                struct si_pm4_state             *vs;
+                struct si_pm4_state             *vs_sampler_views;
+                struct si_pm4_state             *vs_sampler;
+                struct si_pm4_state             *vs_const;
+                struct si_pm4_state             *ps;
+                struct si_pm4_state             *ps_sampler_views;
+                struct si_pm4_state             *ps_sampler;
+                struct si_pm4_state             *ps_const;
+                struct si_pm4_state             *spi;
+                struct si_pm4_state             *vertex_buffers;
+                struct si_pm4_state             *texture_barrier;
+                struct si_pm4_state             *draw_info;
+                struct si_pm4_state             *draw;
+        } named;
+        struct si_pm4_state     *array[0];
+};
+#define si_pm4_block_idx(member) \
+        (offsetof(union si_state, named.member) / sizeof(struct si_pm4_state *))
+#define si_pm4_state_changed(rctx, member) \
+        ((rctx)->queued.named.member != (rctx)->emitted.named.member)
+#define si_pm4_bind_state(rctx, member, value) \
+        do { \
+                (rctx)->queued.named.member = (value); \
+        } while(0)
+#define si_pm4_delete_state(rctx, member, value) \
+        do { \
+                if ((rctx)->queued.named.member == (value)) { \
+                        (rctx)->queued.named.member = NULL; \
+                } \
+                si_pm4_free_state(rctx, (struct si_pm4_state *)(value), \
+                                  si_pm4_block_idx(member)); \
+        } while(0)
+#define si_pm4_set_state(rctx, member, value) \
+        do { \
+                if ((rctx)->queued.named.member != (value)) { \
+                        si_pm4_free_state(rctx, \
+                                (struct si_pm4_state *)(rctx)->queued.named.member, \
+                                si_pm4_block_idx(member)); \
+                        (rctx)->queued.named.member = (value); \
+                } \
+        } while(0)
+/* si_state.c */
+struct si_pipe_shader_selector;
+boolean si_is_format_supported(struct pipe_screen *screen,
+                               enum pipe_format format,
+                               enum pipe_texture_target target,
+                               unsigned sample_count,
+                               unsigned usage);
+int si_shader_select(struct pipe_context *ctx,
+                     struct si_pipe_shader_selector *sel,
+                     unsigned *dirty);
+void si_init_state_functions(struct r600_context *rctx);
+void si_init_config(struct r600_context *rctx);
+/* si_state_streamout.c */
+struct pipe_stream_output_target *
+si_create_so_target(struct pipe_context *ctx,
+                    struct pipe_resource *buffer,
+                    unsigned buffer_offset,
+                    unsigned buffer_size);
+void si_so_target_destroy(struct pipe_context *ctx,
+                          struct pipe_stream_output_target *target);
+void si_set_so_targets(struct pipe_context *ctx,
+                       unsigned num_targets,
+                       struct pipe_stream_output_target **targets,
+                       unsigned append_bitmask);
+/* si_state_draw.c */
+void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
+/* si_commands.c */
+void si_cmd_context_control(struct si_pm4_state *pm4);
+void si_cmd_draw_index_2(struct si_pm4_state *pm4, uint32_t max_size,
+                         uint64_t index_base, uint32_t index_count,
+                         uint32_t initiator, bool predicate);
+void si_cmd_draw_index_auto(struct si_pm4_state *pm4, uint32_t count,
+                            uint32_t initiator, bool predicate);
+void si_cmd_surface_sync(struct si_pm4_state *pm4, uint32_t cp_coher_cntl);
+#endif

 /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/si_state_draw.c
 ,0 → 1,734
+/*
+ * Copyright 2012 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Christian König <christian.koenig@amd.com>
+ */
+#include "util/u_memory.h"
+#include "util/u_framebuffer.h"
+#include "util/u_blitter.h"
+#include "tgsi/tgsi_parse.h"
+#include "radeonsi_pipe.h"
+#include "radeonsi_shader.h"
+#include "si_state.h"
+#include "sid.h"
+/*
+ * Shaders
+ */
+static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct si_pm4_state *pm4;
+        unsigned num_sgprs, num_user_sgprs;
+        unsigned nparams, i, vgpr_comp_cnt;
+        uint64_t va;
+        si_pm4_delete_state(rctx, vs, shader->pm4);
+        pm4 = shader->pm4 = si_pm4_alloc_state(rctx);
+        if (pm4 == NULL)
+                return;
+        si_pm4_inval_shader_cache(pm4);
+        /* Certain attributes (position, psize, etc.) don't count as params.
+         * VS is required to export at least one param and r600_shader_from_tgsi()
+         * takes care of adding a dummy export.
+         */
+        for (nparams = 0, i = 0 ; i < shader->shader.noutput; i++) {
+                switch (shader->shader.output[i].name) {
+                case TGSI_SEMANTIC_POSITION:
+                case TGSI_SEMANTIC_PSIZE:
+                        break;
+                default:
+                        nparams++;
+                }
+        }
+        if (nparams < 1)
+                nparams = 1;
+        si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
+                       S_0286C4_VS_EXPORT_COUNT(nparams - 1));
+        si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
+                       S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
+                       S_02870C_POS1_EXPORT_FORMAT(shader->shader.nr_pos_exports > 1 ?
+                                                   V_02870C_SPI_SHADER_4COMP :
+                                                   V_02870C_SPI_SHADER_NONE) |
+                       S_02870C_POS2_EXPORT_FORMAT(shader->shader.nr_pos_exports > 2 ?
+                                                   V_02870C_SPI_SHADER_4COMP :
+                                                   V_02870C_SPI_SHADER_NONE) |
+                       S_02870C_POS3_EXPORT_FORMAT(shader->shader.nr_pos_exports > 3 ?
+                                                   V_02870C_SPI_SHADER_4COMP :
+                                                   V_02870C_SPI_SHADER_NONE));
+        va = r600_resource_va(ctx->screen, (void *)shader->bo);
+        si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
+        si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
+        si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
+        num_user_sgprs = SI_VS_NUM_USER_SGPR;
+        num_sgprs = shader->num_sgprs;
+        if (num_user_sgprs > num_sgprs) {
+                /* Last 2 reserved SGPRs are used for VCC */
+                num_sgprs = num_user_sgprs + 2;
+        }
+        assert(num_sgprs <= 104);
+        vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
+        si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
+                       S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
+                       S_00B128_SGPRS((num_sgprs - 1) / 8) |
+                       S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt));
+        si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
+                       S_00B12C_USER_SGPR(num_user_sgprs));
+        if (rctx->chip_class >= CIK) {
+                si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
+                               S_00B118_CU_EN(0xffff));
+                si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
+                               S_00B11C_LIMIT(0));
+        }
+        si_pm4_bind_state(rctx, vs, shader->pm4);
+}
+static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct si_pm4_state *pm4;
+        unsigned i, exports_ps, num_cout, spi_ps_in_control, db_shader_control;
+        unsigned num_sgprs, num_user_sgprs;
+        boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
+        unsigned fragcoord_interp_mode = 0;
+        unsigned spi_baryc_cntl, spi_ps_input_ena, spi_shader_z_format;
+        uint64_t va;
+        si_pm4_delete_state(rctx, ps, shader->pm4);
+        pm4 = shader->pm4 = si_pm4_alloc_state(rctx);
+        if (pm4 == NULL)
+                return;
+        si_pm4_inval_shader_cache(pm4);
+        db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
+        for (i = 0; i < shader->shader.ninput; i++) {
+                switch (shader->shader.input[i].name) {
+                case TGSI_SEMANTIC_POSITION:
+                        if (shader->shader.input[i].centroid) {
+                                /* fragcoord_interp_mode will be written to
+                                 * SPI_BARYC_CNTL.POS_FLOAT_LOCATION
+                                 * Possible vaules:
+                                 * 0 -> Position = pixel center (default)
+                                 * 1 -> Position = pixel centroid
+                                 * 2 -> Position = iterated sample number XXX:
+                                 *                        What does this mean?
+                                 */
+                                fragcoord_interp_mode = 1;
+                        }
+                        /* Fall through */
+                case TGSI_SEMANTIC_FACE:
+                        continue;
+                }
+                if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
+                        have_linear = TRUE;
+                if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
+                        have_perspective = TRUE;
+                if (shader->shader.input[i].centroid)
+                        have_centroid = TRUE;
+        }
+        for (i = 0; i < shader->shader.noutput; i++) {
+                if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION)
+                        db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
+                if (shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
+                        db_shader_control |= S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
+        }
+        if (shader->shader.uses_kill || shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
+                db_shader_control |= S_02880C_KILL_ENABLE(1);
+        exports_ps = 0;
+        num_cout = 0;
+        for (i = 0; i < shader->shader.noutput; i++) {
+                if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION ||
+                    shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
+                        exports_ps |= 1;
+                else if (shader->shader.output[i].name == TGSI_SEMANTIC_COLOR) {
+                        if (shader->shader.fs_write_all)
+                                num_cout = shader->shader.nr_cbufs;
+                        else
+                                num_cout++;
+                }
+        }
+        if (!exports_ps) {
+                /* always at least export 1 component per pixel */
+                exports_ps = 2;
+        }
+        spi_ps_in_control = S_0286D8_NUM_INTERP(shader->shader.ninterp) |
+                S_0286D8_BC_OPTIMIZE_DISABLE(1);
+        spi_baryc_cntl = 0;
+        if (have_perspective)
+                spi_baryc_cntl |= have_centroid ?
+                        S_0286E0_PERSP_CENTROID_CNTL(1) : S_0286E0_PERSP_CENTER_CNTL(1);
+        if (have_linear)
+                spi_baryc_cntl |= have_centroid ?
+                        S_0286E0_LINEAR_CENTROID_CNTL(1) : S_0286E0_LINEAR_CENTER_CNTL(1);
+        spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(fragcoord_interp_mode);
+        si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
+        spi_ps_input_ena = shader->spi_ps_input_ena;
+        /* we need to enable at least one of them, otherwise we hang the GPU */
+        assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
+            G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
+            G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
+            G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
+            G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
+            G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
+            G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
+            G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
+        si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
+        si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
+        si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
+        if (G_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(db_shader_control))
+                spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
+        else if (G_02880C_Z_EXPORT_ENABLE(db_shader_control))
+                spi_shader_z_format = V_028710_SPI_SHADER_32_R;
+        else
+                spi_shader_z_format = 0;
+        si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, spi_shader_z_format);
+        si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
+                       shader->spi_shader_col_format);
+        si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
+        va = r600_resource_va(ctx->screen, (void *)shader->bo);
+        si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
+        si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
+        si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
+        num_user_sgprs = SI_PS_NUM_USER_SGPR;
+        num_sgprs = shader->num_sgprs;
+        if (num_user_sgprs > num_sgprs) {
+                /* Last 2 reserved SGPRs are used for VCC */
+                num_sgprs = num_user_sgprs + 2;
+        }
+        assert(num_sgprs <= 104);
+        si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
+                       S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
+                       S_00B028_SGPRS((num_sgprs - 1) / 8));
+        si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
+                       S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
+                       S_00B02C_USER_SGPR(num_user_sgprs));
+        if (rctx->chip_class >= CIK) {
+                si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
+                               S_00B01C_CU_EN(0xffff));
+        }
+        si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
+        shader->sprite_coord_enable = rctx->sprite_coord_enable;
+        si_pm4_bind_state(rctx, ps, shader->pm4);
+}
+/*
+ * Drawing
+ */
+static unsigned si_conv_pipe_prim(unsigned pprim)
+{
+        static const unsigned prim_conv[] = {
+                [PIPE_PRIM_POINTS]                      = V_008958_DI_PT_POINTLIST,
+                [PIPE_PRIM_LINES]                       = V_008958_DI_PT_LINELIST,
+                [PIPE_PRIM_LINE_LOOP]                   = V_008958_DI_PT_LINELOOP,
+                [PIPE_PRIM_LINE_STRIP]                  = V_008958_DI_PT_LINESTRIP,
+                [PIPE_PRIM_TRIANGLES]                   = V_008958_DI_PT_TRILIST,
+                [PIPE_PRIM_TRIANGLE_STRIP]              = V_008958_DI_PT_TRISTRIP,
+                [PIPE_PRIM_TRIANGLE_FAN]                = V_008958_DI_PT_TRIFAN,
+                [PIPE_PRIM_QUADS]                       = V_008958_DI_PT_QUADLIST,
+                [PIPE_PRIM_QUAD_STRIP]                  = V_008958_DI_PT_QUADSTRIP,
+                [PIPE_PRIM_POLYGON]                     = V_008958_DI_PT_POLYGON,
+                [PIPE_PRIM_LINES_ADJACENCY]             = ~0,
+                [PIPE_PRIM_LINE_STRIP_ADJACENCY]        = ~0,
+                [PIPE_PRIM_TRIANGLES_ADJACENCY]         = ~0,
+                [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY]    = ~0
+        };
+        unsigned result = prim_conv[pprim];
+        if (result == ~0) {
+                R600_ERR("unsupported primitive type %d\n", pprim);
+        }
+        return result;
+}
+static bool si_update_draw_info_state(struct r600_context *rctx,
+                               const struct pipe_draw_info *info)
+{
+        struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
+        struct si_shader *vs = &rctx->vs_shader->current->shader;
+        unsigned prim = si_conv_pipe_prim(info->mode);
+        unsigned ls_mask = 0;
+        if (pm4 == NULL)
+                return false;
+        if (prim == ~0) {
+                FREE(pm4);
+                return false;
+        }
+        if (rctx->chip_class >= CIK)
+                si_pm4_set_reg(pm4, R_030908_VGT_PRIMITIVE_TYPE, prim);
+        else
+                si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
+        si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
+        si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
+        si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET,
+                       info->indexed ? info->index_bias : info->start);
+        si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
+        si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
+        si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 + SI_SGPR_START_INSTANCE * 4,
+                       info->start_instance);
+        if (prim == V_008958_DI_PT_LINELIST)
+                ls_mask = 1;
+        else if (prim == V_008958_DI_PT_LINESTRIP)
+                ls_mask = 2;
+        si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE,
+                       S_028A0C_AUTO_RESET_CNTL(ls_mask) |
+                       rctx->pa_sc_line_stipple);
+        if (info->mode == PIPE_PRIM_QUADS || info->mode == PIPE_PRIM_QUAD_STRIP || info->mode == PIPE_PRIM_POLYGON) {
+                si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
+                               S_028814_PROVOKING_VTX_LAST(1) | rctx->pa_su_sc_mode_cntl);
+        } else {
+                si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, rctx->pa_su_sc_mode_cntl);
+        }
+        si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
+                       S_02881C_USE_VTX_POINT_SIZE(vs->vs_out_point_size) |
+                       S_02881C_VS_OUT_CCDIST0_VEC_ENA((vs->clip_dist_write & 0x0F) != 0) |
+                       S_02881C_VS_OUT_CCDIST1_VEC_ENA((vs->clip_dist_write & 0xF0) != 0) |
+                       S_02881C_VS_OUT_MISC_VEC_ENA(vs->vs_out_misc_write) |
+                       (rctx->queued.named.rasterizer->clip_plane_enable &
+                        vs->clip_dist_write));
+        si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL,
+                       rctx->queued.named.rasterizer->pa_cl_clip_cntl |
+                       (vs->clip_dist_write ? 0 :
+                        rctx->queued.named.rasterizer->clip_plane_enable & 0x3F));
+        si_pm4_set_state(rctx, draw_info, pm4);
+        return true;
+}
+static void si_update_spi_map(struct r600_context *rctx)
+{
+        struct si_shader *ps = &rctx->ps_shader->current->shader;
+        struct si_shader *vs = &rctx->vs_shader->current->shader;
+        struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
+        unsigned i, j, tmp;
+        for (i = 0; i < ps->ninput; i++) {
+                unsigned name = ps->input[i].name;
+                unsigned param_offset = ps->input[i].param_offset;
+                if (name == TGSI_SEMANTIC_POSITION)
+                        /* Read from preloaded VGPRs, not parameters */
+                        continue;
+bcolor:
+                tmp = 0;
+                if (ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
+                    (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
+                     rctx->ps_shader->current->key.ps.flatshade)) {
+                        tmp |= S_028644_FLAT_SHADE(1);
+                }
+                if (name == TGSI_SEMANTIC_GENERIC &&
+                    rctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
+                        tmp |= S_028644_PT_SPRITE_TEX(1);
+                }
+                for (j = 0; j < vs->noutput; j++) {
+                        if (name == vs->output[j].name &&
+                            ps->input[i].sid == vs->output[j].sid) {
+                                tmp |= S_028644_OFFSET(vs->output[j].param_offset);
+                                break;
+                        }
+                }
+                if (j == vs->noutput) {
+                        /* No corresponding output found, load defaults into input */
+                        tmp |= S_028644_OFFSET(0x20);
+                }
+                si_pm4_set_reg(pm4,
+                               R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
+                               tmp);
+                if (name == TGSI_SEMANTIC_COLOR &&
+                    rctx->ps_shader->current->key.ps.color_two_side) {
+                        name = TGSI_SEMANTIC_BCOLOR;
+                        param_offset++;
+                        goto bcolor;
+                }
+        }
+        si_pm4_set_state(rctx, spi, pm4);
+}
+static void si_update_derived_state(struct r600_context *rctx)
+{
+        struct pipe_context * ctx = (struct pipe_context*)rctx;
+        unsigned vs_dirty = 0, ps_dirty = 0;
+        if (!rctx->blitter->running) {
+                /* Flush depth textures which need to be flushed. */
+                if (rctx->vs_samplers.depth_texture_mask) {
+                        si_flush_depth_textures(rctx, &rctx->vs_samplers);
+                }
+                if (rctx->ps_samplers.depth_texture_mask) {
+                        si_flush_depth_textures(rctx, &rctx->ps_samplers);
+                }
+        }
+        si_shader_select(ctx, rctx->vs_shader, &vs_dirty);
+        if (!rctx->vs_shader->current->pm4) {
+                si_pipe_shader_vs(ctx, rctx->vs_shader->current);
+                vs_dirty = 0;
+        }
+        if (vs_dirty) {
+                si_pm4_bind_state(rctx, vs, rctx->vs_shader->current->pm4);
+        }
+        si_shader_select(ctx, rctx->ps_shader, &ps_dirty);
+        if (!rctx->ps_shader->current->pm4) {
+                si_pipe_shader_ps(ctx, rctx->ps_shader->current);
+                ps_dirty = 0;
+        }
+        if (!rctx->ps_shader->current->bo) {
+                if (!rctx->dummy_pixel_shader->pm4)
+                        si_pipe_shader_ps(ctx, rctx->dummy_pixel_shader);
+                else
+                        si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
+                ps_dirty = 0;
+        }
+        if (ps_dirty) {
+                si_pm4_bind_state(rctx, ps, rctx->ps_shader->current->pm4);
+        }
+        if (si_pm4_state_changed(rctx, ps) || si_pm4_state_changed(rctx, vs)) {
+                /* XXX: Emitting the PS state even when only the VS changed
+                 * fixes random failures with piglit glsl-max-varyings.
+                 * Not sure why...
+                 */
+                rctx->emitted.named.ps = NULL;
+                si_update_spi_map(rctx);
+        }
+}
+static void si_constant_buffer_update(struct r600_context *rctx)
+{
+        struct pipe_context *ctx = &rctx->context;
+        struct si_pm4_state *pm4;
+        unsigned shader, i;
+        uint64_t va;
+        if (!rctx->constbuf_state[PIPE_SHADER_VERTEX].dirty_mask &&
+            !rctx->constbuf_state[PIPE_SHADER_FRAGMENT].dirty_mask)
+                return;
+        for (shader = PIPE_SHADER_VERTEX ; shader <= PIPE_SHADER_FRAGMENT; shader++) {
+                struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
+                pm4 = CALLOC_STRUCT(si_pm4_state);
+                if (!pm4)
+                        continue;
+                si_pm4_inval_shader_cache(pm4);
+                si_pm4_sh_data_begin(pm4);
+                for (i = 0; i < 2; i++) {
+                        if (state->enabled_mask & (1 << i)) {
+                                struct pipe_constant_buffer *cb = &state->cb[i];
+                                struct si_resource *rbuffer = si_resource(cb->buffer);
+                                va = r600_resource_va(ctx->screen, (void*)rbuffer);
+                                va += cb->buffer_offset;
+                                si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
+                                /* Fill in a T# buffer resource description */
+                                si_pm4_sh_data_add(pm4, va);
+                                si_pm4_sh_data_add(pm4, (S_008F04_BASE_ADDRESS_HI(va >> 32) |
+                                                         S_008F04_STRIDE(0)));
+                                si_pm4_sh_data_add(pm4, cb->buffer_size);
+                                si_pm4_sh_data_add(pm4, S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
+                                                   S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
+                                                   S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
+                                                   S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
+                                                   S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
+                                                   S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32));
+                        } else {
+                                /* Fill in an empty T# buffer resource description */
+                                si_pm4_sh_data_add(pm4, 0);
+                                si_pm4_sh_data_add(pm4, 0);
+                                si_pm4_sh_data_add(pm4, 0);
+                                si_pm4_sh_data_add(pm4, 0);
+                        }
+                }
+                switch (shader) {
+                case PIPE_SHADER_VERTEX:
+                        si_pm4_sh_data_end(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, SI_SGPR_CONST);
+                        si_pm4_set_state(rctx, vs_const, pm4);
+                        break;
+                case PIPE_SHADER_FRAGMENT:
+                        si_pm4_sh_data_end(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0, SI_SGPR_CONST);
+                        si_pm4_set_state(rctx, ps_const, pm4);
+                        break;
+                default:
+                        R600_ERR("unsupported %d\n", shader);
+                        FREE(pm4);
+                        return;
+                }
+                state->dirty_mask = 0;
+        }
+}
+static void si_vertex_buffer_update(struct r600_context *rctx)
+{
+        struct pipe_context *ctx = &rctx->context;
+        struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
+        bool bound[PIPE_MAX_ATTRIBS] = {};
+        unsigned i, count;
+        uint64_t va;
+        si_pm4_inval_texture_cache(pm4);
+        /* bind vertex buffer once */
+        count = rctx->vertex_elements->count;
+        assert(count <= 256 / 4);
+        si_pm4_sh_data_begin(pm4);
+        for (i = 0 ; i < count; i++) {
+                struct pipe_vertex_element *ve = &rctx->vertex_elements->elements[i];
+                struct pipe_vertex_buffer *vb;
+                struct si_resource *rbuffer;
+                unsigned offset;
+                if (ve->vertex_buffer_index >= rctx->nr_vertex_buffers)
+                        continue;
+                vb = &rctx->vertex_buffer[ve->vertex_buffer_index];
+                rbuffer = (struct si_resource*)vb->buffer;
+                if (rbuffer == NULL)
+                        continue;
+                offset = 0;
+                offset += vb->buffer_offset;
+                offset += ve->src_offset;
+                va = r600_resource_va(ctx->screen, (void*)rbuffer);
+                va += offset;
+                /* Fill in T# buffer resource description */
+                si_pm4_sh_data_add(pm4, va & 0xFFFFFFFF);
+                si_pm4_sh_data_add(pm4, (S_008F04_BASE_ADDRESS_HI(va >> 32) |
+                                         S_008F04_STRIDE(vb->stride)));
+                if (vb->stride)
+                        /* Round up by rounding down and adding 1 */
+                        si_pm4_sh_data_add(pm4,
+                                           (vb->buffer->width0 - offset -
+                                            util_format_get_blocksize(ve->src_format)) /
+                                           vb->stride + 1);
+                else
+                        si_pm4_sh_data_add(pm4, vb->buffer->width0 - offset);
+                si_pm4_sh_data_add(pm4, rctx->vertex_elements->rsrc_word3[i]);
+                if (!bound[ve->vertex_buffer_index]) {
+                        si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
+                        bound[ve->vertex_buffer_index] = true;
+                }
+        }
+        si_pm4_sh_data_end(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, SI_SGPR_VERTEX_BUFFER);
+        si_pm4_set_state(rctx, vertex_buffers, pm4);
+}
+static void si_state_draw(struct r600_context *rctx,
+                          const struct pipe_draw_info *info,
+                          const struct pipe_index_buffer *ib)
+{
+        struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
+        if (pm4 == NULL)
+                return;
+        /* queries need some special values
+         * (this is non-zero if any query is active) */
+        if (rctx->num_cs_dw_queries_suspend) {
+                struct si_state_dsa *dsa = rctx->queued.named.dsa;
+                si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
+                               S_028004_PERFECT_ZPASS_COUNTS(1));
+                si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
+                               dsa->db_render_override |
+                               S_02800C_NOOP_CULL_DISABLE(1));
+        }
+        /* draw packet */
+        si_pm4_cmd_begin(pm4, PKT3_INDEX_TYPE);
+        if (ib->index_size == 4) {
+                si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_32 | (R600_BIG_ENDIAN ?
+                                V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
+        } else {
+                si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (R600_BIG_ENDIAN ?
+                                V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
+        }
+        si_pm4_cmd_end(pm4, rctx->predicate_drawing);
+        si_pm4_cmd_begin(pm4, PKT3_NUM_INSTANCES);
+        si_pm4_cmd_add(pm4, info->instance_count);
+        si_pm4_cmd_end(pm4, rctx->predicate_drawing);
+        if (info->indexed) {
+                uint32_t max_size = (ib->buffer->width0 - ib->offset) /
+                                 rctx->index_buffer.index_size;
+                uint64_t va;
+                va = r600_resource_va(&rctx->screen->screen, ib->buffer);
+                va += ib->offset;
+                si_pm4_add_bo(pm4, (struct si_resource *)ib->buffer, RADEON_USAGE_READ);
+                si_cmd_draw_index_2(pm4, max_size, va, info->count,
+                                    V_0287F0_DI_SRC_SEL_DMA,
+                                    rctx->predicate_drawing);
+        } else {
+                uint32_t initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
+                initiator |= S_0287F0_USE_OPAQUE(!!info->count_from_stream_output);
+                si_cmd_draw_index_auto(pm4, info->count, initiator, rctx->predicate_drawing);
+        }
+        si_pm4_set_state(rctx, draw, pm4);
+}
+void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
+{
+        struct r600_context *rctx = (struct r600_context *)ctx;
+        struct pipe_index_buffer ib = {};
+        uint32_t cp_coher_cntl;
+        if (!info->count && (info->indexed || !info->count_from_stream_output))
+                return;
+        if (!rctx->ps_shader || !rctx->vs_shader)
+                return;
+        si_update_derived_state(rctx);
+        si_constant_buffer_update(rctx);
+        si_vertex_buffer_update(rctx);
+        if (info->indexed) {
+                /* Initialize the index buffer struct. */
+                pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
+                ib.user_buffer = rctx->index_buffer.user_buffer;
+                ib.index_size = rctx->index_buffer.index_size;
+                ib.offset = rctx->index_buffer.offset + info->start * ib.index_size;
+                /* Translate or upload, if needed. */
+                r600_translate_index_buffer(rctx, &ib, info->count);
+                if (ib.user_buffer && !ib.buffer) {
+                        r600_upload_index_buffer(rctx, &ib, info->count);
+                }
+        } else if (info->count_from_stream_output) {
+                r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info->count_from_stream_output);
+        }
+        rctx->vs_shader_so_strides = rctx->vs_shader->current->so_strides;
+        if (!si_update_draw_info_state(rctx, info))
+                return;
+        si_state_draw(rctx, info, &ib);
+        cp_coher_cntl = si_pm4_sync_flags(rctx);
+        if (cp_coher_cntl) {
+                struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
+                if (pm4 == NULL)
+                        return;
+                si_cmd_surface_sync(pm4, cp_coher_cntl);
+                si_pm4_set_state(rctx, sync, pm4);
+        }
+        /* Emit states. */
+        rctx->pm4_dirty_cdwords += si_pm4_dirty_dw(rctx);
+        si_need_cs_space(rctx, 0, TRUE);
+        si_pm4_emit_dirty(rctx);
+        rctx->pm4_dirty_cdwords = 0;
+#if R600_TRACE_CS
+        if (rctx->screen->trace_bo) {
+                r600_trace_emit(rctx);
+        }
+#endif
+#if 0
+        /* Enable stream out if needed. */
+        if (rctx->streamout_start) {
+                r600_context_streamout_begin(rctx);
+                rctx->streamout_start = FALSE;
+        }
+#endif
+        rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY;
+        /* Set the depth buffer as dirty. */
+        if (rctx->framebuffer.zsbuf) {
+                struct pipe_surface *surf = rctx->framebuffer.zsbuf;
+                struct r600_resource_texture *rtex = (struct r600_resource_texture *)surf->texture;
+                rtex->dirty_db_mask |= 1 << surf->u.tex.level;
+        }
+        pipe_resource_reference(&ib.buffer, NULL);
+}

 /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/si_state_streamout.c
 ,0 → 1,269
+/*
+ * Copyright 2012 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Christian König <christian.koenig@amd.com>
+ */
+#include "radeonsi_pipe.h"
+#include "si_state.h"
+/*
+ * Stream out
+ */
+#if 0
+void si_context_streamout_begin(struct r600_context *ctx)
+{
+        struct radeon_winsys_cs *cs = ctx->cs;
+        struct si_so_target **t = ctx->so_targets;
+        unsigned *strides = ctx->vs_shader_so_strides;
+        unsigned buffer_en, i;
+        buffer_en = (ctx->num_so_targets >= 1 && t[0] ? 1 : 0) |
+                    (ctx->num_so_targets >= 2 && t[1] ? 2 : 0) |
+                    (ctx->num_so_targets >= 3 && t[2] ? 4 : 0) |
+                    (ctx->num_so_targets >= 4 && t[3] ? 8 : 0);
+        ctx->num_cs_dw_streamout_end =
++ /* flush_vgt_streamout */
+                util_bitcount(buffer_en) * 8 +
+;
+        si_need_cs_space(ctx,
++ /* flush_vgt_streamout */
++ /* enables */
+                           util_bitcount(buffer_en & ctx->streamout_append_bitmask) * 8 +
+                           util_bitcount(buffer_en & ~ctx->streamout_append_bitmask) * 6 +
+                           ctx->num_cs_dw_streamout_end, TRUE);
+        evergreen_flush_vgt_streamout(ctx);
+        evergreen_set_streamout_enable(ctx, buffer_en);
+        for (i = 0; i < ctx->num_so_targets; i++) {
+#if 0
+                if (t[i]) {
+                        t[i]->stride = strides[i];
+                        t[i]->so_index = i;
+                        cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 3, 0);
+                        cs->buf[cs->cdw++] = (R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 +
+*i - SI_CONTEXT_REG_OFFSET) >> 2;
+                        cs->buf[cs->cdw++] = (t[i]->b.buffer_offset +
+                                                        t[i]->b.buffer_size) >> 2; /* BUFFER_SIZE (in DW) */
+                        cs->buf[cs->cdw++] = strides[i] >> 2;              /* VTX_STRIDE (in DW) */
+                        cs->buf[cs->cdw++] = 0;                    /* BUFFER_BASE */
+                        cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
+                        cs->buf[cs->cdw++] =
+                                si_context_bo_reloc(ctx, si_resource(t[i]->b.buffer),
+                                                      RADEON_USAGE_WRITE);
+                        if (ctx->streamout_append_bitmask & (1 << i)) {
+                                /* Append. */
+                                cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
+                                cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
+                                                               STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM); /* control */
+                                cs->buf[cs->cdw++] = 0; /* unused */
+                                cs->buf[cs->cdw++] = 0; /* unused */
+                                cs->buf[cs->cdw++] = 0; /* src address lo */
+                                cs->buf[cs->cdw++] = 0; /* src address hi */
+                                cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
+                                cs->buf[cs->cdw++] =
+                                        si_context_bo_reloc(ctx,  t[i]->filled_size,
+                                                              RADEON_USAGE_READ);
+                        } else {
+                                /* Start from the beginning. */
+                                cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
+                                cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
+                                                               STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET); /* control */
+                                cs->buf[cs->cdw++] = 0; /* unused */
+                                cs->buf[cs->cdw++] = 0; /* unused */
+                                cs->buf[cs->cdw++] = t[i]->b.buffer_offset >> 2; /* buffer offset in DW */
+                                cs->buf[cs->cdw++] = 0; /* unused */
+                        }
+                }
+#endif
+        }
+}
+void si_context_streamout_end(struct r600_context *ctx)
+{
+        struct radeon_winsys_cs *cs = ctx->cs;
+        struct si_so_target **t = ctx->so_targets;
+        unsigned i, flush_flags = 0;
+        evergreen_flush_vgt_streamout(ctx);
+        for (i = 0; i < ctx->num_so_targets; i++) {
+#if 0
+                if (t[i]) {
+                        cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0);
+                        cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) |
+                                                       STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
+                                                       STRMOUT_STORE_BUFFER_FILLED_SIZE; /* control */
+                        cs->buf[cs->cdw++] = 0; /* dst address lo */
+                        cs->buf[cs->cdw++] = 0; /* dst address hi */
+                        cs->buf[cs->cdw++] = 0; /* unused */
+                        cs->buf[cs->cdw++] = 0; /* unused */
+                        cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
+                        cs->buf[cs->cdw++] =
+                                si_context_bo_reloc(ctx,  t[i]->filled_size,
+                                                      RADEON_USAGE_WRITE);
+                        flush_flags |= S_0085F0_SO0_DEST_BASE_ENA(1) << i;
+                }
+#endif
+        }
+        evergreen_set_streamout_enable(ctx, 0);
+        ctx->atom_surface_sync.flush_flags |= flush_flags;
+        si_atom_dirty(ctx, &ctx->atom_surface_sync.atom);
+        ctx->num_cs_dw_streamout_end = 0;
+        /* XXX print some debug info */
+        for (i = 0; i < ctx->num_so_targets; i++) {
+                if (!t[i])
+                        continue;
+                uint32_t *ptr = ctx->ws->buffer_map(t[i]->filled_size->cs_buf, ctx->cs, RADEON_USAGE_READ);
+                printf("FILLED_SIZE%i: %u\n", i, *ptr);
+                ctx->ws->buffer_unmap(t[i]->filled_size->cs_buf);
+        }
+}
+void evergreen_flush_vgt_streamout(struct si_context *ctx)
+{
+        struct radeon_winsys_cs *cs = ctx->cs;
+        cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, 1, 0);
+        cs->buf[cs->cdw++] = (R_0084FC_CP_STRMOUT_CNTL - SI_CONFIG_REG_OFFSET) >> 2;
+        cs->buf[cs->cdw++] = 0;
+        cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
+        cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0);
+        cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0);
+        cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */
+        cs->buf[cs->cdw++] = R_0084FC_CP_STRMOUT_CNTL >> 2;  /* register */
+        cs->buf[cs->cdw++] = 0;
+        cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* reference value */
+        cs->buf[cs->cdw++] = S_0084FC_OFFSET_UPDATE_DONE(1); /* mask */
+        cs->buf[cs->cdw++] = 4; /* poll interval */
+}
+void evergreen_set_streamout_enable(struct si_context *ctx, unsigned buffer_enable_bit)
+{
+        struct radeon_winsys_cs *cs = ctx->cs;
+        if (buffer_enable_bit) {
+                cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
+                cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - SI_CONTEXT_REG_OFFSET) >> 2;
+                cs->buf[cs->cdw++] = S_028B94_STREAMOUT_0_EN(1);
+                cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
+                cs->buf[cs->cdw++] = (R_028B98_VGT_STRMOUT_BUFFER_CONFIG - SI_CONTEXT_REG_OFFSET) >> 2;
+                cs->buf[cs->cdw++] = S_028B98_STREAM_0_BUFFER_EN(buffer_enable_bit);
+        } else {
+                cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
+                cs->buf[cs->cdw++] = (R_028B94_VGT_STRMOUT_CONFIG - SI_CONTEXT_REG_OFFSET) >> 2;
+                cs->buf[cs->cdw++] = S_028B94_STREAMOUT_0_EN(0);
+        }
+}
+#endif
+struct pipe_stream_output_target *
+si_create_so_target(struct pipe_context *ctx,
+                    struct pipe_resource *buffer,
+                    unsigned buffer_offset,
+                    unsigned buffer_size)
+{
+#if 0
+        struct si_context *rctx = (struct r600_context *)ctx;
+        struct si_so_target *t;
+        void *ptr;
+        t = CALLOC_STRUCT(si_so_target);
+        if (!t) {
+                return NULL;
+        }
+        t->b.reference.count = 1;
+        t->b.context = ctx;
+        pipe_resource_reference(&t->b.buffer, buffer);
+        t->b.buffer_offset = buffer_offset;
+        t->b.buffer_size = buffer_size;
+        t->filled_size = si_resource_create_custom(ctx->screen, PIPE_USAGE_STATIC, 4);
+        ptr = rctx->ws->buffer_map(t->filled_size->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
+        memset(ptr, 0, t->filled_size->buf->size);
+        rctx->ws->buffer_unmap(t->filled_size->cs_buf);
+        return &t->b;
+#endif
+        return NULL;
+}
+void si_so_target_destroy(struct pipe_context *ctx,
+                          struct pipe_stream_output_target *target)
+{
+#if 0
+        struct si_so_target *t = (struct r600_so_target*)target;
+        pipe_resource_reference(&t->b.buffer, NULL);
+        si_resource_reference(&t->filled_size, NULL);
+        FREE(t);
+#endif
+}
+void si_set_so_targets(struct pipe_context *ctx,
+                       unsigned num_targets,
+                       struct pipe_stream_output_target **targets,
+                       unsigned append_bitmask)
+{
+        assert(num_targets == 0);
+#if 0
+        struct si_context *rctx = (struct r600_context *)ctx;
+        unsigned i;
+        /* Stop streamout. */
+        if (rctx->num_so_targets) {
+                si_context_streamout_end(rctx);
+        }
+        /* Set the new targets. */
+        for (i = 0; i < num_targets; i++) {
+                pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
+        }
+        for (; i < rctx->num_so_targets; i++) {
+                pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
+        }
+        rctx->num_so_targets = num_targets;
+        rctx->streamout_start = num_targets != 0;
+        rctx->streamout_append_bitmask = append_bitmask;
+#endif
+}

 /contrib/sdk/sources/Mesa/src/gallium/drivers/radeonsi/sid.h
 ,0 → 1,8567
+/*
+ * Southern Islands Register documentation
+ *
+ * Copyright (C) 2011  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef SID_H
+#define SID_H
+/* si values */
+#define SI_CONFIG_REG_OFFSET                 0x00008000
+#define SI_CONFIG_REG_END                    0x0000B000
+#define SI_SH_REG_OFFSET                     0x0000B000
+#define SI_SH_REG_END                        0x0000C000
+#define SI_CONTEXT_REG_OFFSET                0x00028000
+#define SI_CONTEXT_REG_END                   0x00029000
+#define CIK_UCONFIG_REG_OFFSET               0x00030000
+#define CIK_UCONFIG_REG_END                  0x00031000
+#define EVENT_TYPE_CACHE_FLUSH                  0x6
+#define EVENT_TYPE_PS_PARTIAL_FLUSH            0x10
+#define EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT 0x14
+#define EVENT_TYPE_ZPASS_DONE                  0x15
+#define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT   0x16
+#define EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH        0x1f
+#define EVENT_TYPE_SAMPLE_STREAMOUTSTATS        0x20
+#define         EVENT_TYPE(x)                           ((x) << 0)
+#define         EVENT_INDEX(x)                          ((x) << 8)
+                /* 0 - any non-TS event
+                 * 1 - ZPASS_DONE
+                 * 2 - SAMPLE_PIPELINESTAT
+                 * 3 - SAMPLE_STREAMOUTSTAT*
+                 * 4 - *S_PARTIAL_FLUSH
+                 * 5 - TS events
+                 */
+#define EVENT_WRITE_INV_L2                   0x100000
+#define PREDICATION_OP_CLEAR 0x0
+#define PREDICATION_OP_ZPASS 0x1
+#define PREDICATION_OP_PRIMCOUNT 0x2
+#define PRED_OP(x) ((x) << 16)
+#define PREDICATION_CONTINUE (1 << 31)
+#define PREDICATION_HINT_WAIT (0 << 12)
+#define PREDICATION_HINT_NOWAIT_DRAW (1 << 12)
+#define PREDICATION_DRAW_NOT_VISIBLE (0 << 8)
+#define PREDICATION_DRAW_VISIBLE (1 << 8)
+#define R600_TEXEL_PITCH_ALIGNMENT_MASK        0x7
+#define PKT3_NOP                               0x10
+#define PKT3_DISPATCH_DIRECT                   0x15
+#define PKT3_DISPATCH_INDIRECT                 0x16
+#define PKT3_OCCLUSION_QUERY                   0x1F /* new for CIK */
+#define PKT3_SET_PREDICATION                   0x20
+#define PKT3_COND_EXEC                         0x22
+#define PKT3_PRED_EXEC                         0x23
+#define PKT3_DRAW_INDEX_2                      0x27
+#define PKT3_CONTEXT_CONTROL                   0x28
+#define PKT3_INDEX_TYPE                        0x2A
+#define PKT3_DRAW_INDEX_AUTO                   0x2D
+#define PKT3_DRAW_INDEX_IMMD                   0x2E /* not on CIK */
+#define PKT3_NUM_INSTANCES                     0x2F
+#define PKT3_STRMOUT_BUFFER_UPDATE             0x34
+#define PKT3_WRITE_DATA                        0x37
+#define     PKT3_WRITE_DATA_DST_SEL(x)             ((x) << 8)
+#define     PKT3_WRITE_DATA_DST_SEL_REG            0
+#define     PKT3_WRITE_DATA_DST_SEL_MEM_SYNC       1
+#define     PKT3_WRITE_DATA_DST_SEL_TC_OR_L2       2
+#define     PKT3_WRITE_DATA_DST_SEL_GDS            3
+#define     PKT3_WRITE_DATA_DST_SEL_RESERVED_4     4
+#define     PKT3_WRITE_DATA_DST_SEL_MEM_ASYNC      5
+#define     PKT3_WR_ONE_ADDR                       (1 << 16)
+#define PKT3_WRITE_DATA_WR_CONFIRM                 (1 << 20)
+#define PKT3_WRITE_DATA_ENGINE_SEL(x)              ((x) << 30)
+#define PKT3_WRITE_DATA_ENGINE_SEL_ME              0
+#define PKT3_WRITE_DATA_ENGINE_SEL_PFP             1
+#define PKT3_WRITE_DATA_ENGINE_SEL_CE              2
+#define PKT3_MEM_SEMAPHORE                     0x39
+#define PKT3_MPEG_INDEX                        0x3A /* not on CIK */
+#define PKT3_WAIT_REG_MEM                      0x3C
+#define         WAIT_REG_MEM_EQUAL              3
+#define PKT3_MEM_WRITE                         0x3D /* not on CIK */
+#define PKT3_INDIRECT_BUFFER                   0x32
+#define PKT3_SURFACE_SYNC                      0x43 /* deprecated on CIK, use ACQUIRE_MEM */
+#define PKT3_ME_INITIALIZE                     0x44 /* not on CIK */
+#define PKT3_COND_WRITE                        0x45
+#define PKT3_EVENT_WRITE                       0x46
+#define PKT3_EVENT_WRITE_EOP                   0x47
+#define PKT3_EVENT_WRITE_EOS                   0x48
+#define PKT3_ONE_REG_WRITE                     0x57 /* not on CIK */
+#define PKT3_ACQUIRE_MEM                       0x58 /* new for CIK */
+#define PKT3_SET_CONFIG_REG                    0x68
+#define PKT3_SET_CONTEXT_REG                   0x69
+#define PKT3_SET_SH_REG                        0x76
+#define PKT3_SET_SH_REG_OFFSET                 0x77
+#define PKT3_SET_UCONFIG_REG                   0x79 /* new for CIK */
+#define PKT_TYPE_S(x)                   (((x) & 0x3) << 30)
+#define PKT_TYPE_G(x)                   (((x) >> 30) & 0x3)
+#define PKT_TYPE_C                      0x3FFFFFFF
+#define PKT_COUNT_S(x)                  (((x) & 0x3FFF) << 16)
+#define PKT_COUNT_G(x)                  (((x) >> 16) & 0x3FFF)
+#define PKT_COUNT_C                     0xC000FFFF
+#define PKT0_BASE_INDEX_S(x)            (((x) & 0xFFFF) << 0)
+#define PKT0_BASE_INDEX_G(x)            (((x) >> 0) & 0xFFFF)
+#define PKT0_BASE_INDEX_C               0xFFFF0000
+#define PKT3_IT_OPCODE_S(x)             (((x) & 0xFF) << 8)
+#define PKT3_IT_OPCODE_G(x)             (((x) >> 8) & 0xFF)
+#define PKT3_IT_OPCODE_C                0xFFFF00FF
+#define PKT3_PREDICATE(x)               (((x) >> 0) & 0x1)
+#define PKT3_SHADER_TYPE_S(x)           (((x) & 0x1) << 1)
+#define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) | PKT_COUNT_S(count))
+#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate))
+#define R_0084FC_CP_STRMOUT_CNTL                                        0x0084FC
+#define   S_0084FC_OFFSET_UPDATE_DONE(x)                              (((x) & 0x1) << 0)
+#define R_0085F0_CP_COHER_CNTL                                          0x0085F0
+#define   S_0085F0_DEST_BASE_0_ENA(x)                                 (((x) & 0x1) << 0)
+#define   G_0085F0_DEST_BASE_0_ENA(x)                                 (((x) >> 0) & 0x1)
+#define   C_0085F0_DEST_BASE_0_ENA                                    0xFFFFFFFE
+#define   S_0085F0_DEST_BASE_1_ENA(x)                                 (((x) & 0x1) << 1)
+#define   G_0085F0_DEST_BASE_1_ENA(x)                                 (((x) >> 1) & 0x1)
+#define   C_0085F0_DEST_BASE_1_ENA                                    0xFFFFFFFD
+#define   S_0085F0_CB0_DEST_BASE_ENA_SHIFT                            6
+#define   S_0085F0_CB0_DEST_BASE_ENA(x)                               (((x) & 0x1) << 6)
+#define   G_0085F0_CB0_DEST_BASE_ENA(x)                               (((x) >> 6) & 0x1)
+#define   C_0085F0_CB0_DEST_BASE_ENA                                  0xFFFFFFBF
+#define   S_0085F0_CB1_DEST_BASE_ENA(x)                               (((x) & 0x1) << 7)
+#define   G_0085F0_CB1_DEST_BASE_ENA(x)                               (((x) >> 7) & 0x1)
+#define   C_0085F0_CB1_DEST_BASE_ENA                                  0xFFFFFF7F
+#define   S_0085F0_CB2_DEST_BASE_ENA(x)                               (((x) & 0x1) << 8)
+#define   G_0085F0_CB2_DEST_BASE_ENA(x)                               (((x) >> 8) & 0x1)
+#define   C_0085F0_CB2_DEST_BASE_ENA                                  0xFFFFFEFF
+#define   S_0085F0_CB3_DEST_BASE_ENA(x)                               (((x) & 0x1) << 9)
+#define   G_0085F0_CB3_DEST_BASE_ENA(x)                               (((x) >> 9) & 0x1)
+#define   C_0085F0_CB3_DEST_BASE_ENA                                  0xFFFFFDFF
+#define   S_0085F0_CB4_DEST_BASE_ENA(x)                               (((x) & 0x1) << 10)
+#define   G_0085F0_CB4_DEST_BASE_ENA(x)                               (((x) >> 10) & 0x1)
+#define   C_0085F0_CB4_DEST_BASE_ENA                                  0xFFFFFBFF
+#define   S_0085F0_CB5_DEST_BASE_ENA(x)                               (((x) & 0x1) << 11)
+#define   G_0085F0_CB5_DEST_BASE_ENA(x)                               (((x) >> 11) & 0x1)
+#define   C_0085F0_CB5_DEST_BASE_ENA                                  0xFFFFF7FF
+#define   S_0085F0_CB6_DEST_BASE_ENA(x)                               (((x) & 0x1) << 12)
+#define   G_0085F0_CB6_DEST_BASE_ENA(x)                               (((x) >> 12) & 0x1)
+#define   C_0085F0_CB6_DEST_BASE_ENA                                  0xFFFFEFFF
+#define   S_0085F0_CB7_DEST_BASE_ENA(x)                               (((x) & 0x1) << 13)
+#define   G_0085F0_CB7_DEST_BASE_ENA(x)                               (((x) >> 13) & 0x1)
+#define   C_0085F0_CB7_DEST_BASE_ENA                                  0xFFFFDFFF
+#define   S_0085F0_DB_DEST_BASE_ENA(x)                                (((x) & 0x1) << 14)
+#define   G_0085F0_DB_DEST_BASE_ENA(x)                                (((x) >> 14) & 0x1)
+#define   C_0085F0_DB_DEST_BASE_ENA                                   0xFFFFBFFF
+#define   S_0085F0_DEST_BASE_2_ENA(x)                                 (((x) & 0x1) << 19)
+#define   G_0085F0_DEST_BASE_2_ENA(x)                                 (((x) >> 19) & 0x1)
+#define   C_0085F0_DEST_BASE_2_ENA                                    0xFFF7FFFF
+#define   S_0085F0_DEST_BASE_3_ENA(x)                                 (((x) & 0x1) << 21)
+#define   G_0085F0_DEST_BASE_3_ENA(x)                                 (((x) >> 21) & 0x1)
+#define   C_0085F0_DEST_BASE_3_ENA                                    0xFFDFFFFF
+#define   S_0085F0_TCL1_ACTION_ENA(x)                                 (((x) & 0x1) << 22)
+#define   G_0085F0_TCL1_ACTION_ENA(x)                                 (((x) >> 22) & 0x1)
+#define   C_0085F0_TCL1_ACTION_ENA                                    0xFFBFFFFF
+#define   S_0085F0_TC_ACTION_ENA(x)                                   (((x) & 0x1) << 23)
+#define   G_0085F0_TC_ACTION_ENA(x)                                   (((x) >> 23) & 0x1)
+#define   C_0085F0_TC_ACTION_ENA                                      0xFF7FFFFF
+#define   S_0085F0_CB_ACTION_ENA(x)                                   (((x) & 0x1) << 25)
+#define   G_0085F0_CB_ACTION_ENA(x)                                   (((x) >> 25) & 0x1)
+#define   C_0085F0_CB_ACTION_ENA                                      0xFDFFFFFF
+#define   S_0085F0_DB_ACTION_ENA(x)                                   (((x) & 0x1) << 26)
+#define   G_0085F0_DB_ACTION_ENA(x)                                   (((x) >> 26) & 0x1)
+#define   C_0085F0_DB_ACTION_ENA                                      0xFBFFFFFF
+#define   S_0085F0_SH_KCACHE_ACTION_ENA(x)                            (((x) & 0x1) << 27)
+#define   G_0085F0_SH_KCACHE_ACTION_ENA(x)                            (((x) >> 27) & 0x1)
+#define   C_0085F0_SH_KCACHE_ACTION_ENA                               0xF7FFFFFF
+#define   S_0085F0_SH_ICACHE_ACTION_ENA(x)                            (((x) & 0x1) << 29)
+#define   G_0085F0_SH_ICACHE_ACTION_ENA(x)                            (((x) >> 29) & 0x1)
+#define   C_0085F0_SH_ICACHE_ACTION_ENA                               0xDFFFFFFF
+#define R_0085F4_CP_COHER_SIZE                                          0x0085F4
+#define R_0085F8_CP_COHER_BASE                                          0x0085F8
+/* CIK */
+#define R_0301E4_CP_COHER_BASE_HI                                       0x0301E4
+#define   S_0301E4_COHER_BASE_HI_256B(x)                              (((x) & 0xFF) << 0)
+#define   G_0301E4_COHER_BASE_HI_256B(x)                              (((x) >> 0) & 0xFF)
+#define   C_0301E4_COHER_BASE_HI_256B                                 0xFFFFFF00
+#define R_0301F0_CP_COHER_CNTL                                          0x0301F0
+#define   S_0301F0_DEST_BASE_0_ENA(x)                                 (((x) & 0x1) << 0)
+#define   G_0301F0_DEST_BASE_0_ENA(x)                                 (((x) >> 0) & 0x1)
+#define   C_0301F0_DEST_BASE_0_ENA                                    0xFFFFFFFE
+#define   S_0301F0_DEST_BASE_1_ENA(x)                                 (((x) & 0x1) << 1)
+#define   G_0301F0_DEST_BASE_1_ENA(x)                                 (((x) >> 1) & 0x1)
+#define   C_0301F0_DEST_BASE_1_ENA                                    0xFFFFFFFD
+#define   S_0301F0_CB0_DEST_BASE_ENA(x)                               (((x) & 0x1) << 6)
+#define   G_0301F0_CB0_DEST_BASE_ENA(x)                               (((x) >> 6) & 0x1)
+#define   C_0301F0_CB0_DEST_BASE_ENA                                  0xFFFFFFBF
+#define   S_0301F0_CB1_DEST_BASE_ENA(x)                               (((x) & 0x1) << 7)
+#define   G_0301F0_CB1_DEST_BASE_ENA(x)                               (((x) >> 7) & 0x1)
+#define   C_0301F0_CB1_DEST_BASE_ENA                                  0xFFFFFF7F
+#define   S_0301F0_CB2_DEST_BASE_ENA(x)                               (((x) & 0x1) << 8)
+#define   G_0301F0_CB2_DEST_BASE_ENA(x)                               (((x) >> 8) & 0x1)
+#define   C_0301F0_CB2_DEST_BASE_ENA                                  0xFFFFFEFF
+#define   S_0301F0_CB3_DEST_BASE_ENA(x)                               (((x) & 0x1) << 9)
+#define   G_0301F0_CB3_DEST_BASE_ENA(x)                               (((x) >> 9) & 0x1)
+#define   C_0301F0_CB3_DEST_BASE_ENA                                  0xFFFFFDFF
+#define   S_0301F0_CB4_DEST_BASE_ENA(x)                               (((x) & 0x1) << 10)
+#define   G_0301F0_CB4_DEST_BASE_ENA(x)                               (((x) >> 10) & 0x1)
+#define   C_0301F0_CB4_DEST_BASE_ENA                                  0xFFFFFBFF
+#define   S_0301F0_CB5_DEST_BASE_ENA(x)                               (((x) & 0x1) << 11)
+#define   G_0301F0_CB5_DEST_BASE_ENA(x)                               (((x) >> 11) & 0x1)
+#define   C_0301F0_CB5_DEST_BASE_ENA                                  0xFFFFF7FF
+#define   S_0301F0_CB6_DEST_BASE_ENA(x)                               (((x) & 0x1) << 12)
+#define   G_0301F0_CB6_DEST_BASE_ENA(x)                               (((x) >> 12) & 0x1)
+#define   C_0301F0_CB6_DEST_BASE_ENA                                  0xFFFFEFFF
+#define   S_0301F0_CB7_DEST_BASE_ENA(x)                               (((x) & 0x1) << 13)
+#define   G_0301F0_CB7_DEST_BASE_ENA(x)                               (((x) >> 13) & 0x1)
+#define   C_0301F0_CB7_DEST_BASE_ENA                                  0xFFFFDFFF
+#define   S_0301F0_DB_DEST_BASE_ENA(x)                                (((x) & 0x1) << 14)
+#define   G_0301F0_DB_DEST_BASE_ENA(x)                                (((x) >> 14) & 0x1)
+#define   C_0301F0_DB_DEST_BASE_ENA                                   0xFFFFBFFF
+#define   S_0301F0_TCL1_VOL_ACTION_ENA(x)                             (((x) & 0x1) << 15)
+#define   G_0301F0_TCL1_VOL_ACTION_ENA(x)                             (((x) >> 15) & 0x1)
+#define   C_0301F0_TCL1_VOL_ACTION_ENA                                0xFFFF7FFF
+#define   S_0301F0_TC_VOL_ACTION_ENA(x)                               (((x) & 0x1) << 16)
+#define   G_0301F0_TC_VOL_ACTION_ENA(x)                               (((x) >> 16) & 0x1)
+#define   C_0301F0_TC_VOL_ACTION_ENA                                  0xFFFEFFFF
+#define   S_0301F0_TC_WB_ACTION_ENA(x)                                (((x) & 0x1) << 18)
+#define   G_0301F0_TC_WB_ACTION_ENA(x)                                (((x) >> 18) & 0x1)
+#define   C_0301F0_TC_WB_ACTION_ENA                                   0xFFFBFFFF
+#define   S_0301F0_DEST_BASE_2_ENA(x)                                 (((x) & 0x1) << 19)
+#define   G_0301F0_DEST_BASE_2_ENA(x)                                 (((x) >> 19) & 0x1)
+#define   C_0301F0_DEST_BASE_2_ENA                                    0xFFF7FFFF
+#define   S_0301F0_DEST_BASE_3_ENA(x)                                 (((x) & 0x1) << 21)
+#define   G_0301F0_DEST_BASE_3_ENA(x)                                 (((x) >> 21) & 0x1)
+#define   C_0301F0_DEST_BASE_3_ENA                                    0xFFDFFFFF
+#define   S_0301F0_TCL1_ACTION_ENA(x)                                 (((x) & 0x1) << 22)
+#define   G_0301F0_TCL1_ACTION_ENA(x)                                 (((x) >> 22) & 0x1)
+#define   C_0301F0_TCL1_ACTION_ENA                                    0xFFBFFFFF
+#define   S_0301F0_TC_ACTION_ENA(x)                                   (((x) & 0x1) << 23)
+#define   G_0301F0_TC_ACTION_ENA(x)                                   (((x) >> 23) & 0x1)
+#define   C_0301F0_TC_ACTION_ENA                                      0xFF7FFFFF
+#define   S_0301F0_CB_ACTION_ENA(x)                                   (((x) & 0x1) << 25)
+#define   G_0301F0_CB_ACTION_ENA(x)                                   (((x) >> 25) & 0x1)
+#define   C_0301F0_CB_ACTION_ENA                                      0xFDFFFFFF
+#define   S_0301F0_DB_ACTION_ENA(x)                                   (((x) & 0x1) << 26)
+#define   G_0301F0_DB_ACTION_ENA(x)                                   (((x) >> 26) & 0x1)
+#define   C_0301F0_DB_ACTION_ENA                                      0xFBFFFFFF
+#define   S_0301F0_SH_KCACHE_ACTION_ENA(x)                            (((x) & 0x1) << 27)
+#define   G_0301F0_SH_KCACHE_ACTION_ENA(x)                            (((x) >> 27) & 0x1)
+#define   C_0301F0_SH_KCACHE_ACTION_ENA                               0xF7FFFFFF
+#define   S_0301F0_SH_KCACHE_VOL_ACTION_ENA(x)                        (((x) & 0x1) << 28)
+#define   G_0301F0_SH_KCACHE_VOL_ACTION_ENA(x)                        (((x) >> 28) & 0x1)
+#define   C_0301F0_SH_KCACHE_VOL_ACTION_ENA                           0xEFFFFFFF
+#define   S_0301F0_SH_ICACHE_ACTION_ENA(x)                            (((x) & 0x1) << 29)
+#define   G_0301F0_SH_ICACHE_ACTION_ENA(x)                            (((x) >> 29) & 0x1)
+#define   C_0301F0_SH_ICACHE_ACTION_ENA                               0xDFFFFFFF
+#define R_0301F4_CP_COHER_SIZE                                          0x0301F4
+#define R_0301F8_CP_COHER_BASE                                          0x0301F8
+#define R_030230_CP_COHER_SIZE_HI                                       0x030230
+#define   S_030230_COHER_SIZE_HI_256B(x)                              (((x) & 0xFF) << 0)
+#define   G_030230_COHER_SIZE_HI_256B(x)                              (((x) >> 0) & 0xFF)
+#define   C_030230_COHER_SIZE_HI_256B                                 0xFFFFFF00
+/*     */
+#define R_0088B0_VGT_VTX_VECT_EJECT_REG                                 0x0088B0
+#define   S_0088B0_PRIM_COUNT(x)                                      (((x) & 0x3FF) << 0)
+#define   G_0088B0_PRIM_COUNT(x)                                      (((x) >> 0) & 0x3FF)
+#define   C_0088B0_PRIM_COUNT                                         0xFFFFFC00
+#define R_0088C4_VGT_CACHE_INVALIDATION                                 0x0088C4
+#define   S_0088C4_VS_NO_EXTRA_BUFFER(x)                              (((x) & 0x1) << 5)
+#define   G_0088C4_VS_NO_EXTRA_BUFFER(x)                              (((x) >> 5) & 0x1)
+#define   C_0088C4_VS_NO_EXTRA_BUFFER                                 0xFFFFFFDF
+#define   S_0088C4_STREAMOUT_FULL_FLUSH(x)                            (((x) & 0x1) << 13)
+#define   G_0088C4_STREAMOUT_FULL_FLUSH(x)                            (((x) >> 13) & 0x1)
+#define   C_0088C4_STREAMOUT_FULL_FLUSH                               0xFFFFDFFF
+#define   S_0088C4_ES_LIMIT(x)                                        (((x) & 0x1F) << 16)
+#define   G_0088C4_ES_LIMIT(x)                                        (((x) >> 16) & 0x1F)
+#define   C_0088C4_ES_LIMIT                                           0xFFE0FFFF
+#define R_0088C8_VGT_ESGS_RING_SIZE                                     0x0088C8
+#define R_0088CC_VGT_GSVS_RING_SIZE                                     0x0088CC
+/* CIK */
+#define R_030900_VGT_ESGS_RING_SIZE                                     0x030900
+#define R_030904_VGT_GSVS_RING_SIZE                                     0x030904
+/*     */
+#define R_0088D4_VGT_GS_VERTEX_REUSE                                    0x0088D4
+#define   S_0088D4_VERT_REUSE(x)                                      (((x) & 0x1F) << 0)
+#define   G_0088D4_VERT_REUSE(x)                                      (((x) >> 0) & 0x1F)
+#define   C_0088D4_VERT_REUSE                                         0xFFFFFFE0
+#define R_008958_VGT_PRIMITIVE_TYPE                                     0x008958
+#define   S_008958_PRIM_TYPE(x)                                       (((x) & 0x3F) << 0)
+#define   G_008958_PRIM_TYPE(x)                                       (((x) >> 0) & 0x3F)
+#define   C_008958_PRIM_TYPE                                          0xFFFFFFC0
+#define     V_008958_DI_PT_NONE                                     0x00
+#define     V_008958_DI_PT_POINTLIST                                0x01
+#define     V_008958_DI_PT_LINELIST                                 0x02
+#define     V_008958_DI_PT_LINESTRIP                                0x03
+#define     V_008958_DI_PT_TRILIST                                  0x04
+#define     V_008958_DI_PT_TRIFAN                                   0x05
+#define     V_008958_DI_PT_TRISTRIP                                 0x06
+#define     V_008958_DI_PT_UNUSED_0                                 0x07
+#define     V_008958_DI_PT_UNUSED_1                                 0x08
+#define     V_008958_DI_PT_PATCH                                    0x09
+#define     V_008958_DI_PT_LINELIST_ADJ                             0x0A
+#define     V_008958_DI_PT_LINESTRIP_ADJ                            0x0B
+#define     V_008958_DI_PT_TRILIST_ADJ                              0x0C
+#define     V_008958_DI_PT_TRISTRIP_ADJ                             0x0D
+#define     V_008958_DI_PT_UNUSED_3                                 0x0E
+#define     V_008958_DI_PT_UNUSED_4                                 0x0F
+#define     V_008958_DI_PT_TRI_WITH_WFLAGS                          0x10
+#define     V_008958_DI_PT_RECTLIST                                 0x11
+#define     V_008958_DI_PT_LINELOOP                                 0x12
+#define     V_008958_DI_PT_QUADLIST                                 0x13
+#define     V_008958_DI_PT_QUADSTRIP                                0x14
+#define     V_008958_DI_PT_POLYGON                                  0x15
+#define     V_008958_DI_PT_2D_COPY_RECT_LIST_V0                     0x16
+#define     V_008958_DI_PT_2D_COPY_RECT_LIST_V1                     0x17
+#define     V_008958_DI_PT_2D_COPY_RECT_LIST_V2                     0x18
+#define     V_008958_DI_PT_2D_COPY_RECT_LIST_V3                     0x19
+#define     V_008958_DI_PT_2D_FILL_RECT_LIST                        0x1A
+#define     V_008958_DI_PT_2D_LINE_STRIP                            0x1B
+#define     V_008958_DI_PT_2D_TRI_STRIP                             0x1C
+#define R_00895C_VGT_INDEX_TYPE                                         0x00895C
+#define   S_00895C_INDEX_TYPE(x)                                      (((x) & 0x03) << 0)
+#define   G_00895C_INDEX_TYPE(x)                                      (((x) >> 0) & 0x03)
+#define   C_00895C_INDEX_TYPE                                         0xFFFFFFFC
+#define     V_00895C_DI_INDEX_SIZE_16_BIT                           0x00
+#define     V_00895C_DI_INDEX_SIZE_32_BIT                           0x01
+#define R_008960_VGT_STRMOUT_BUFFER_FILLED_SIZE_0                       0x008960
+#define R_008964_VGT_STRMOUT_BUFFER_FILLED_SIZE_1                       0x008964
+#define R_008968_VGT_STRMOUT_BUFFER_FILLED_SIZE_2                       0x008968
+#define R_00896C_VGT_STRMOUT_BUFFER_FILLED_SIZE_3                       0x00896C
+#define R_008970_VGT_NUM_INDICES                                        0x008970
+#define R_008974_VGT_NUM_INSTANCES                                      0x008974
+#define R_008988_VGT_TF_RING_SIZE                                       0x008988
+#define   S_008988_SIZE(x)                                            (((x) & 0xFFFF) << 0)
+#define   G_008988_SIZE(x)                                            (((x) >> 0) & 0xFFFF)
+#define   C_008988_SIZE                                               0xFFFF0000
+#define R_0089B0_VGT_HS_OFFCHIP_PARAM                                   0x0089B0
+#define   S_0089B0_OFFCHIP_BUFFERING(x)                               (((x) & 0x7F) << 0)
+#define   G_0089B0_OFFCHIP_BUFFERING(x)                               (((x) >> 0) & 0x7F)
+#define   C_0089B0_OFFCHIP_BUFFERING                                  0xFFFFFF80
+#define R_0089B8_VGT_TF_MEMORY_BASE                                     0x0089B8
+#define R_008A14_PA_CL_ENHANCE                                          0x008A14
+#define   S_008A14_CLIP_VTX_REORDER_ENA(x)                            (((x) & 0x1) << 0)
+#define   G_008A14_CLIP_VTX_REORDER_ENA(x)                            (((x) >> 0) & 0x1)
+#define   C_008A14_CLIP_VTX_REORDER_ENA                               0xFFFFFFFE
+#define   S_008A14_NUM_CLIP_SEQ(x)                                    (((x) & 0x03) << 1)
+#define   G_008A14_NUM_CLIP_SEQ(x)                                    (((x) >> 1) & 0x03)
+#define   C_008A14_NUM_CLIP_SEQ                                       0xFFFFFFF9
+#define   S_008A14_CLIPPED_PRIM_SEQ_STALL(x)                          (((x) & 0x1) << 3)
+#define   G_008A14_CLIPPED_PRIM_SEQ_STALL(x)                          (((x) >> 3) & 0x1)
+#define   C_008A14_CLIPPED_PRIM_SEQ_STALL                             0xFFFFFFF7
+#define   S_008A14_VE_NAN_PROC_DISABLE(x)                             (((x) & 0x1) << 4)
+#define   G_008A14_VE_NAN_PROC_DISABLE(x)                             (((x) >> 4) & 0x1)
+#define   C_008A14_VE_NAN_PROC_DISABLE                                0xFFFFFFEF
+#define R_008A60_PA_SU_LINE_STIPPLE_VALUE                               0x008A60
+#define   S_008A60_LINE_STIPPLE_VALUE(x)                              (((x) & 0xFFFFFF) << 0)
+#define   G_008A60_LINE_STIPPLE_VALUE(x)                              (((x) >> 0) & 0xFFFFFF)
+#define   C_008A60_LINE_STIPPLE_VALUE                                 0xFF000000
+#define R_008B10_PA_SC_LINE_STIPPLE_STATE                               0x008B10
+#define   S_008B10_CURRENT_PTR(x)                                     (((x) & 0x0F) << 0)
+#define   G_008B10_CURRENT_PTR(x)                                     (((x) >> 0) & 0x0F)
+#define   C_008B10_CURRENT_PTR                                        0xFFFFFFF0
+#define   S_008B10_CURRENT_COUNT(x)                                   (((x) & 0xFF) << 8)
+#define   G_008B10_CURRENT_COUNT(x)                                   (((x) >> 8) & 0xFF)
+#define   C_008B10_CURRENT_COUNT                                      0xFFFF00FF
+/* CIK */
+#define R_030908_VGT_PRIMITIVE_TYPE                                     0x030908
+#define   S_030908_PRIM_TYPE(x)                                       (((x) & 0x3F) << 0)
+#define   G_030908_PRIM_TYPE(x)                                       (((x) >> 0) & 0x3F)
+#define   C_030908_PRIM_TYPE                                          0xFFFFFFC0
+#define     V_030908_DI_PT_NONE                                     0x00
+#define     V_030908_DI_PT_POINTLIST                                0x01
+#define     V_030908_DI_PT_LINELIST                                 0x02
+#define     V_030908_DI_PT_LINESTRIP                                0x03
+#define     V_030908_DI_PT_TRILIST                                  0x04
+#define     V_030908_DI_PT_TRIFAN                                   0x05
+#define     V_030908_DI_PT_TRISTRIP                                 0x06
+#define     V_030908_DI_PT_PATCH                                    0x09
+#define     V_030908_DI_PT_LINELIST_ADJ                             0x0A
+#define     V_030908_DI_PT_LINESTRIP_ADJ                            0x0B
+#define     V_030908_DI_PT_TRILIST_ADJ                              0x0C
+#define     V_030908_DI_PT_TRISTRIP_ADJ                             0x0D
+#define     V_030908_DI_PT_TRI_WITH_WFLAGS                          0x10
+#define     V_030908_DI_PT_RECTLIST                                 0x11
+#define     V_030908_DI_PT_LINELOOP                                 0x12
+#define     V_030908_DI_PT_QUADLIST                                 0x13
+#define     V_030908_DI_PT_QUADSTRIP                                0x14
+#define     V_030908_DI_PT_POLYGON                                  0x15
+#define     V_030908_DI_PT_2D_COPY_RECT_LIST_V0                     0x16
+#define     V_030908_DI_PT_2D_COPY_RECT_LIST_V1                     0x17
+#define     V_030908_DI_PT_2D_COPY_RECT_LIST_V2                     0x18
+#define     V_030908_DI_PT_2D_COPY_RECT_LIST_V3                     0x19
+#define     V_030908_DI_PT_2D_FILL_RECT_LIST                        0x1A
+#define     V_030908_DI_PT_2D_LINE_STRIP                            0x1B
+#define     V_030908_DI_PT_2D_TRI_STRIP                             0x1C
+#define R_03090C_VGT_INDEX_TYPE                                         0x03090C
+#define   S_03090C_INDEX_TYPE(x)                                      (((x) & 0x03) << 0)
+#define   G_03090C_INDEX_TYPE(x)                                      (((x) >> 0) & 0x03)
+#define   C_03090C_INDEX_TYPE                                         0xFFFFFFFC
+#define     V_03090C_DI_INDEX_SIZE_16_BIT                           0x00
+#define     V_03090C_DI_INDEX_SIZE_32_BIT                           0x01
+#define R_030910_VGT_STRMOUT_BUFFER_FILLED_SIZE_0                       0x030910
+#define R_030914_VGT_STRMOUT_BUFFER_FILLED_SIZE_1                       0x030914
+#define R_030918_VGT_STRMOUT_BUFFER_FILLED_SIZE_2                       0x030918
+#define R_03091C_VGT_STRMOUT_BUFFER_FILLED_SIZE_3                       0x03091C
+#define R_030930_VGT_NUM_INDICES                                        0x030930
+#define R_030934_VGT_NUM_INSTANCES                                      0x030934
+#define R_030938_VGT_TF_RING_SIZE                                       0x030938
+#define   S_030938_SIZE(x)                                            (((x) & 0xFFFF) << 0)
+#define   G_030938_SIZE(x)                                            (((x) >> 0) & 0xFFFF)
+#define   C_030938_SIZE                                               0xFFFF0000
+#define R_03093C_VGT_HS_OFFCHIP_PARAM                                   0x03093C
+#define   S_03093C_OFFCHIP_BUFFERING(x)                               (((x) & 0x1FF) << 0)
+#define   G_03093C_OFFCHIP_BUFFERING(x)                               (((x) >> 0) & 0x1FF)
+#define   C_03093C_OFFCHIP_BUFFERING                                  0xFFFFFE00
+#define   S_03093C_OFFCHIP_GRANULARITY(x)                             (((x) & 0x03) << 9)
+#define   G_03093C_OFFCHIP_GRANULARITY(x)                             (((x) >> 9) & 0x03)
+#define   C_03093C_OFFCHIP_GRANULARITY                                0xFFFFF9FF
+#define     V_03093C_X_8K_DWORDS                                    0x00
+#define     V_03093C_X_4K_DWORDS                                    0x01
+#define     V_03093C_X_2K_DWORDS                                    0x02
+#define     V_03093C_X_1K_DWORDS                                    0x03
+#define R_030940_VGT_TF_MEMORY_BASE                                     0x030940
+#define R_030A00_PA_SU_LINE_STIPPLE_VALUE                               0x030A00
+#define   S_030A00_LINE_STIPPLE_VALUE(x)                              (((x) & 0xFFFFFF) << 0)
+#define   G_030A00_LINE_STIPPLE_VALUE(x)                              (((x) >> 0) & 0xFFFFFF)
+#define   C_030A00_LINE_STIPPLE_VALUE                                 0xFF000000
+#define R_030A04_PA_SC_LINE_STIPPLE_STATE                               0x030A04
+#define   S_030A04_CURRENT_PTR(x)                                     (((x) & 0x0F) << 0)
+#define   G_030A04_CURRENT_PTR(x)                                     (((x) >> 0) & 0x0F)
+#define   C_030A04_CURRENT_PTR                                        0xFFFFFFF0
+#define   S_030A04_CURRENT_COUNT(x)                                   (((x) & 0xFF) << 8)
+#define   G_030A04_CURRENT_COUNT(x)                                   (((x) >> 8) & 0xFF)
+#define   C_030A04_CURRENT_COUNT                                      0xFFFF00FF
+/*     */
+#define R_008BF0_PA_SC_ENHANCE                                          0x008BF0
+#define   S_008BF0_ENABLE_PA_SC_OUT_OF_ORDER(x)                       (((x) & 0x1) << 0)
+#define   G_008BF0_ENABLE_PA_SC_OUT_OF_ORDER(x)                       (((x) >> 0) & 0x1)
+#define   C_008BF0_ENABLE_PA_SC_OUT_OF_ORDER                          0xFFFFFFFE
+#define   S_008BF0_DISABLE_SC_DB_TILE_FIX(x)                          (((x) & 0x1) << 1)
+#define   G_008BF0_DISABLE_SC_DB_TILE_FIX(x)                          (((x) >> 1) & 0x1)
+#define   C_008BF0_DISABLE_SC_DB_TILE_FIX                             0xFFFFFFFD
+#define   S_008BF0_DISABLE_AA_MASK_FULL_FIX(x)                        (((x) & 0x1) << 2)
+#define   G_008BF0_DISABLE_AA_MASK_FULL_FIX(x)                        (((x) >> 2) & 0x1)
+#define   C_008BF0_DISABLE_AA_MASK_FULL_FIX                           0xFFFFFFFB
+#define   S_008BF0_ENABLE_1XMSAA_SAMPLE_LOCATIONS(x)                  (((x) & 0x1) << 3)
+#define   G_008BF0_ENABLE_1XMSAA_SAMPLE_LOCATIONS(x)                  (((x) >> 3) & 0x1)
+#define   C_008BF0_ENABLE_1XMSAA_SAMPLE_LOCATIONS                     0xFFFFFFF7
+#define   S_008BF0_ENABLE_1XMSAA_SAMPLE_LOC_CENTROID(x)               (((x) & 0x1) << 4)
+#define   G_008BF0_ENABLE_1XMSAA_SAMPLE_LOC_CENTROID(x)               (((x) >> 4) & 0x1)
+#define   C_008BF0_ENABLE_1XMSAA_SAMPLE_LOC_CENTROID                  0xFFFFFFEF
+#define   S_008BF0_DISABLE_SCISSOR_FIX(x)                             (((x) & 0x1) << 5)
+#define   G_008BF0_DISABLE_SCISSOR_FIX(x)                             (((x) >> 5) & 0x1)
+#define   C_008BF0_DISABLE_SCISSOR_FIX                                0xFFFFFFDF
+#define   S_008BF0_DISABLE_PW_BUBBLE_COLLAPSE(x)                      (((x) & 0x03) << 6)
+#define   G_008BF0_DISABLE_PW_BUBBLE_COLLAPSE(x)                      (((x) >> 6) & 0x03)
+#define   C_008BF0_DISABLE_PW_BUBBLE_COLLAPSE                         0xFFFFFF3F
+#define   S_008BF0_SEND_UNLIT_STILES_TO_PACKER(x)                     (((x) & 0x1) << 8)
+#define   G_008BF0_SEND_UNLIT_STILES_TO_PACKER(x)                     (((x) >> 8) & 0x1)
+#define   C_008BF0_SEND_UNLIT_STILES_TO_PACKER                        0xFFFFFEFF
+#define   S_008BF0_DISABLE_DUALGRAD_PERF_OPTIMIZATION(x)              (((x) & 0x1) << 9)
+#define   G_008BF0_DISABLE_DUALGRAD_PERF_OPTIMIZATION(x)              (((x) >> 9) & 0x1)
+#define   C_008BF0_DISABLE_DUALGRAD_PERF_OPTIMIZATION                 0xFFFFFDFF
+#define R_008C08_SQC_CACHES                                             0x008C08
+#define   S_008C08_INST_INVALIDATE(x)                                 (((x) & 0x1) << 0)
+#define   G_008C08_INST_INVALIDATE(x)                                 (((x) >> 0) & 0x1)
+#define   C_008C08_INST_INVALIDATE                                    0xFFFFFFFE
+#define   S_008C08_DATA_INVALIDATE(x)                                 (((x) & 0x1) << 1)
+#define   G_008C08_DATA_INVALIDATE(x)                                 (((x) >> 1) & 0x1)
+#define   C_008C08_DATA_INVALIDATE                                    0xFFFFFFFD
+/* CIK */
+#define R_030D20_SQC_CACHES                                             0x030D20
+#define   S_030D20_INST_INVALIDATE(x)                                 (((x) & 0x1) << 0)
+#define   G_030D20_INST_INVALIDATE(x)                                 (((x) >> 0) & 0x1)
+#define   C_030D20_INST_INVALIDATE                                    0xFFFFFFFE
+#define   S_030D20_DATA_INVALIDATE(x)                                 (((x) & 0x1) << 1)
+#define   G_030D20_DATA_INVALIDATE(x)                                 (((x) >> 1) & 0x1)
+#define   C_030D20_DATA_INVALIDATE                                    0xFFFFFFFD
+#define   S_030D20_INVALIDATE_VOLATILE(x)                             (((x) & 0x1) << 2)
+#define   G_030D20_INVALIDATE_VOLATILE(x)                             (((x) >> 2) & 0x1)
+#define   C_030D20_INVALIDATE_VOLATILE                                0xFFFFFFFB
+/*     */
+#define R_008C0C_SQ_RANDOM_WAVE_PRI                                     0x008C0C
+#define   S_008C0C_RET(x)                                             (((x) & 0x7F) << 0)
+#define   G_008C0C_RET(x)                                             (((x) >> 0) & 0x7F)
+#define   C_008C0C_RET                                                0xFFFFFF80
+#define   S_008C0C_RUI(x)                                             (((x) & 0x07) << 7)
+#define   G_008C0C_RUI(x)                                             (((x) >> 7) & 0x07)
+#define   C_008C0C_RUI                                                0xFFFFFC7F
+#define   S_008C0C_RNG(x)                                             (((x) & 0x7FF) << 10)
+#define   G_008C0C_RNG(x)                                             (((x) >> 10) & 0x7FF)
+#define   C_008C0C_RNG                                                0xFFE003FF
+#if 0
+/* CIK */
+#define R_008DFC_SQ_FLAT_1                                              0x008DFC
+#define   S_008DFC_ADDR(x)                                            (((x) & 0xFF) << 0)
+#define   G_008DFC_ADDR(x)                                            (((x) >> 0) & 0xFF)
+#define   C_008DFC_ADDR                                               0xFFFFFF00
+#define     V_008DFC_SQ_VGPR                                        0x00
+#define   S_008DFC_DATA(x)                                            (((x) & 0xFF) << 8)
+#define   G_008DFC_DATA(x)                                            (((x) >> 8) & 0xFF)
+#define   C_008DFC_DATA                                               0xFFFF00FF
+#define     V_008DFC_SQ_VGPR                                        0x00
+#define   S_008DFC_TFE(x)                                             (((x) & 0x1) << 23)
+#define   G_008DFC_TFE(x)                                             (((x) >> 23) & 0x1)
+#define   C_008DFC_TFE                                                0xFF7FFFFF
+#define   S_008DFC_VDST(x)                                            (((x) & 0xFF) << 24)
+#define   G_008DFC_VDST(x)                                            (((x) >> 24) & 0xFF)
+#define   C_008DFC_VDST                                               0x00FFFFFF
+#define     V_008DFC_SQ_VGPR                                        0x00
+/*     */
+#define R_008DFC_SQ_INST                                                0x008DFC
+#define R_008DFC_SQ_VOP1                                                0x008DFC
+#define   S_008DFC_SRC0(x)                                            (((x) & 0x1FF) << 0)
+#define   G_008DFC_SRC0(x)                                            (((x) >> 0) & 0x1FF)
+#define   C_008DFC_SRC0                                               0xFFFFFE00
+#define     V_008DFC_SQ_SGPR                                        0x00
+/* CIK */
+#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
+#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
+/*     */
+#define     V_008DFC_SQ_VCC_LO                                      0x6A
+#define     V_008DFC_SQ_VCC_HI                                      0x6B
+#define     V_008DFC_SQ_TBA_LO                                      0x6C
+#define     V_008DFC_SQ_TBA_HI                                      0x6D
+#define     V_008DFC_SQ_TMA_LO                                      0x6E
+#define     V_008DFC_SQ_TMA_HI                                      0x6F
+#define     V_008DFC_SQ_TTMP0                                       0x70
+#define     V_008DFC_SQ_TTMP1                                       0x71
+#define     V_008DFC_SQ_TTMP2                                       0x72
+#define     V_008DFC_SQ_TTMP3                                       0x73
+#define     V_008DFC_SQ_TTMP4                                       0x74
+#define     V_008DFC_SQ_TTMP5                                       0x75
+#define     V_008DFC_SQ_TTMP6                                       0x76
+#define     V_008DFC_SQ_TTMP7                                       0x77
+#define     V_008DFC_SQ_TTMP8                                       0x78
+#define     V_008DFC_SQ_TTMP9                                       0x79
+#define     V_008DFC_SQ_TTMP10                                      0x7A
+#define     V_008DFC_SQ_TTMP11                                      0x7B
+#define     V_008DFC_SQ_M0                                          0x7C
+#define     V_008DFC_SQ_EXEC_LO                                     0x7E
+#define     V_008DFC_SQ_EXEC_HI                                     0x7F
+#define     V_008DFC_SQ_SRC_0                                       0x80
+#define     V_008DFC_SQ_SRC_1_INT                                   0x81
+#define     V_008DFC_SQ_SRC_2_INT                                   0x82
+#define     V_008DFC_SQ_SRC_3_INT                                   0x83
+#define     V_008DFC_SQ_SRC_4_INT                                   0x84
+#define     V_008DFC_SQ_SRC_5_INT                                   0x85
+#define     V_008DFC_SQ_SRC_6_INT                                   0x86
+#define     V_008DFC_SQ_SRC_7_INT                                   0x87
+#define     V_008DFC_SQ_SRC_8_INT                                   0x88
+#define     V_008DFC_SQ_SRC_9_INT                                   0x89
+#define     V_008DFC_SQ_SRC_10_INT                                  0x8A
+#define     V_008DFC_SQ_SRC_11_INT                                  0x8B
+#define     V_008DFC_SQ_SRC_12_INT                                  0x8C
+#define     V_008DFC_SQ_SRC_13_INT                                  0x8D
+#define     V_008DFC_SQ_SRC_14_INT                                  0x8E
+#define     V_008DFC_SQ_SRC_15_INT                                  0x8F
+#define     V_008DFC_SQ_SRC_16_INT                                  0x90
+#define     V_008DFC_SQ_SRC_17_INT                                  0x91
+#define     V_008DFC_SQ_SRC_18_INT                                  0x92
+#define     V_008DFC_SQ_SRC_19_INT                                  0x93
+#define     V_008DFC_SQ_SRC_20_INT                                  0x94
+#define     V_008DFC_SQ_SRC_21_INT                                  0x95
+#define     V_008DFC_SQ_SRC_22_INT                                  0x96
+#define     V_008DFC_SQ_SRC_23_INT                                  0x97
+#define     V_008DFC_SQ_SRC_24_INT                                  0x98
+#define     V_008DFC_SQ_SRC_25_INT                                  0x99
+#define     V_008DFC_SQ_SRC_26_INT                                  0x9A
+#define     V_008DFC_SQ_SRC_27_INT                                  0x9B
+#define     V_008DFC_SQ_SRC_28_INT                                  0x9C
+#define     V_008DFC_SQ_SRC_29_INT                                  0x9D
+#define     V_008DFC_SQ_SRC_30_INT                                  0x9E
+#define     V_008DFC_SQ_SRC_31_INT                                  0x9F
+#define     V_008DFC_SQ_SRC_32_INT                                  0xA0
+#define     V_008DFC_SQ_SRC_33_INT                                  0xA1
+#define     V_008DFC_SQ_SRC_34_INT                                  0xA2
+#define     V_008DFC_SQ_SRC_35_INT                                  0xA3
+#define     V_008DFC_SQ_SRC_36_INT                                  0xA4
+#define     V_008DFC_SQ_SRC_37_INT                                  0xA5
+#define     V_008DFC_SQ_SRC_38_INT                                  0xA6
+#define     V_008DFC_SQ_SRC_39_INT                                  0xA7
+#define     V_008DFC_SQ_SRC_40_INT                                  0xA8
+#define     V_008DFC_SQ_SRC_41_INT                                  0xA9
+#define     V_008DFC_SQ_SRC_42_INT                                  0xAA
+#define     V_008DFC_SQ_SRC_43_INT                                  0xAB
+#define     V_008DFC_SQ_SRC_44_INT                                  0xAC
+#define     V_008DFC_SQ_SRC_45_INT                                  0xAD
+#define     V_008DFC_SQ_SRC_46_INT                                  0xAE
+#define     V_008DFC_SQ_SRC_47_INT                                  0xAF
+#define     V_008DFC_SQ_SRC_48_INT                                  0xB0
+#define     V_008DFC_SQ_SRC_49_INT                                  0xB1
+#define     V_008DFC_SQ_SRC_50_INT                                  0xB2
+#define     V_008DFC_SQ_SRC_51_INT                                  0xB3
+#define     V_008DFC_SQ_SRC_52_INT                                  0xB4
+#define     V_008DFC_SQ_SRC_53_INT                                  0xB5
+#define     V_008DFC_SQ_SRC_54_INT                                  0xB6
+#define     V_008DFC_SQ_SRC_55_INT                                  0xB7
+#define     V_008DFC_SQ_SRC_56_INT                                  0xB8
+#define     V_008DFC_SQ_SRC_57_INT                                  0xB9
+#define     V_008DFC_SQ_SRC_58_INT                                  0xBA
+#define     V_008DFC_SQ_SRC_59_INT                                  0xBB
+#define     V_008DFC_SQ_SRC_60_INT                                  0xBC
+#define     V_008DFC_SQ_SRC_61_INT                                  0xBD
+#define     V_008DFC_SQ_SRC_62_INT                                  0xBE
+#define     V_008DFC_SQ_SRC_63_INT                                  0xBF
+#define     V_008DFC_SQ_SRC_64_INT                                  0xC0
+#define     V_008DFC_SQ_SRC_M_1_INT                                 0xC1
+#define     V_008DFC_SQ_SRC_M_2_INT                                 0xC2
+#define     V_008DFC_SQ_SRC_M_3_INT                                 0xC3
+#define     V_008DFC_SQ_SRC_M_4_INT                                 0xC4
+#define     V_008DFC_SQ_SRC_M_5_INT                                 0xC5
+#define     V_008DFC_SQ_SRC_M_6_INT                                 0xC6
+#define     V_008DFC_SQ_SRC_M_7_INT                                 0xC7
+#define     V_008DFC_SQ_SRC_M_8_INT                                 0xC8
+#define     V_008DFC_SQ_SRC_M_9_INT                                 0xC9
+#define     V_008DFC_SQ_SRC_M_10_INT                                0xCA
+#define     V_008DFC_SQ_SRC_M_11_INT                                0xCB
+#define     V_008DFC_SQ_SRC_M_12_INT                                0xCC
+#define     V_008DFC_SQ_SRC_M_13_INT                                0xCD
+#define     V_008DFC_SQ_SRC_M_14_INT                                0xCE
+#define     V_008DFC_SQ_SRC_M_15_INT                                0xCF
+#define     V_008DFC_SQ_SRC_M_16_INT                                0xD0
+#define     V_008DFC_SQ_SRC_0_5                                     0xF0
+#define     V_008DFC_SQ_SRC_M_0_5                                   0xF1
+#define     V_008DFC_SQ_SRC_1                                       0xF2
+#define     V_008DFC_SQ_SRC_M_1                                     0xF3
+#define     V_008DFC_SQ_SRC_2                                       0xF4
+#define     V_008DFC_SQ_SRC_M_2                                     0xF5
+#define     V_008DFC_SQ_SRC_4                                       0xF6
+#define     V_008DFC_SQ_SRC_M_4                                     0xF7
+#define     V_008DFC_SQ_SRC_VCCZ                                    0xFB
+#define     V_008DFC_SQ_SRC_EXECZ                                   0xFC
+#define     V_008DFC_SQ_SRC_SCC                                     0xFD
+#define     V_008DFC_SQ_SRC_LDS_DIRECT                              0xFE
+#define     V_008DFC_SQ_SRC_VGPR                                    0x100
+#define   S_008DFC_OP(x)                                              (((x) & 0xFF) << 9)
+#define   G_008DFC_OP(x)                                              (((x) >> 9) & 0xFF)
+#define   C_008DFC_OP                                                 0xFFFE01FF
+#define     V_008DFC_SQ_V_NOP                                       0x00
+#define     V_008DFC_SQ_V_MOV_B32                                   0x01
+#define     V_008DFC_SQ_V_READFIRSTLANE_B32                         0x02
+#define     V_008DFC_SQ_V_CVT_I32_F64                               0x03
+#define     V_008DFC_SQ_V_CVT_F64_I32                               0x04
+#define     V_008DFC_SQ_V_CVT_F32_I32                               0x05
+#define     V_008DFC_SQ_V_CVT_F32_U32                               0x06
+#define     V_008DFC_SQ_V_CVT_U32_F32                               0x07
+#define     V_008DFC_SQ_V_CVT_I32_F32                               0x08
+#define     V_008DFC_SQ_V_MOV_FED_B32                               0x09
+#define     V_008DFC_SQ_V_CVT_F16_F32                               0x0A
+#define     V_008DFC_SQ_V_CVT_F32_F16                               0x0B
+#define     V_008DFC_SQ_V_CVT_RPI_I32_F32                           0x0C
+#define     V_008DFC_SQ_V_CVT_FLR_I32_F32                           0x0D
+#define     V_008DFC_SQ_V_CVT_OFF_F32_I4                            0x0E
+#define     V_008DFC_SQ_V_CVT_F32_F64                               0x0F
+#define     V_008DFC_SQ_V_CVT_F64_F32                               0x10
+#define     V_008DFC_SQ_V_CVT_F32_UBYTE0                            0x11
+#define     V_008DFC_SQ_V_CVT_F32_UBYTE1                            0x12
+#define     V_008DFC_SQ_V_CVT_F32_UBYTE2                            0x13
+#define     V_008DFC_SQ_V_CVT_F32_UBYTE3                            0x14
+#define     V_008DFC_SQ_V_CVT_U32_F64                               0x15
+#define     V_008DFC_SQ_V_CVT_F64_U32                               0x16
+/* CIK */
+#define     V_008DFC_SQ_V_TRUNC_F64                                 0x17
+#define     V_008DFC_SQ_V_CEIL_F64                                  0x18
+#define     V_008DFC_SQ_V_RNDNE_F64                                 0x19
+#define     V_008DFC_SQ_V_FLOOR_F64                                 0x1A
+/*     */
+#define     V_008DFC_SQ_V_FRACT_F32                                 0x20
+#define     V_008DFC_SQ_V_TRUNC_F32                                 0x21
+#define     V_008DFC_SQ_V_CEIL_F32                                  0x22
+#define     V_008DFC_SQ_V_RNDNE_F32                                 0x23
+#define     V_008DFC_SQ_V_FLOOR_F32                                 0x24
+#define     V_008DFC_SQ_V_EXP_F32                                   0x25
+#define     V_008DFC_SQ_V_LOG_CLAMP_F32                             0x26
+#define     V_008DFC_SQ_V_LOG_F32                                   0x27
+#define     V_008DFC_SQ_V_RCP_CLAMP_F32                             0x28
+#define     V_008DFC_SQ_V_RCP_LEGACY_F32                            0x29
+#define     V_008DFC_SQ_V_RCP_F32                                   0x2A
+#define     V_008DFC_SQ_V_RCP_IFLAG_F32                             0x2B
+#define     V_008DFC_SQ_V_RSQ_CLAMP_F32                             0x2C
+#define     V_008DFC_SQ_V_RSQ_LEGACY_F32                            0x2D
+#define     V_008DFC_SQ_V_RSQ_F32                                   0x2E
+#define     V_008DFC_SQ_V_RCP_F64                                   0x2F
+#define     V_008DFC_SQ_V_RCP_CLAMP_F64                             0x30
+#define     V_008DFC_SQ_V_RSQ_F64                                   0x31
+#define     V_008DFC_SQ_V_RSQ_CLAMP_F64                             0x32
+#define     V_008DFC_SQ_V_SQRT_F32                                  0x33
+#define     V_008DFC_SQ_V_SQRT_F64                                  0x34
+#define     V_008DFC_SQ_V_SIN_F32                                   0x35
+#define     V_008DFC_SQ_V_COS_F32                                   0x36
+#define     V_008DFC_SQ_V_NOT_B32                                   0x37
+#define     V_008DFC_SQ_V_BFREV_B32                                 0x38
+#define     V_008DFC_SQ_V_FFBH_U32                                  0x39
+#define     V_008DFC_SQ_V_FFBL_B32                                  0x3A
+#define     V_008DFC_SQ_V_FFBH_I32                                  0x3B
+#define     V_008DFC_SQ_V_FREXP_EXP_I32_F64                         0x3C
+#define     V_008DFC_SQ_V_FREXP_MANT_F64                            0x3D
+#define     V_008DFC_SQ_V_FRACT_F64                                 0x3E
+#define     V_008DFC_SQ_V_FREXP_EXP_I32_F32                         0x3F
+#define     V_008DFC_SQ_V_FREXP_MANT_F32                            0x40
+#define     V_008DFC_SQ_V_CLREXCP                                   0x41
+#define     V_008DFC_SQ_V_MOVRELD_B32                               0x42
+#define     V_008DFC_SQ_V_MOVRELS_B32                               0x43
+#define     V_008DFC_SQ_V_MOVRELSD_B32                              0x44
+/* CIK */
+#define     V_008DFC_SQ_V_LOG_LEGACY_F32                            0x45
+#define     V_008DFC_SQ_V_EXP_LEGACY_F32                            0x46
+/*     */
+#define   S_008DFC_VDST(x)                                            (((x) & 0xFF) << 17)
+#define   G_008DFC_VDST(x)                                            (((x) >> 17) & 0xFF)
+#define   C_008DFC_VDST                                               0xFE01FFFF
+#define     V_008DFC_SQ_VGPR                                        0x00
+#define   S_008DFC_ENCODING(x)                                        (((x) & 0x7F) << 25)
+#define   G_008DFC_ENCODING(x)                                        (((x) >> 25) & 0x7F)
+#define   C_008DFC_ENCODING                                           0x01FFFFFF
+#define     V_008DFC_SQ_ENC_VOP1_FIELD                              0x3F
+#define R_008DFC_SQ_MIMG_1                                              0x008DFC
+#define   S_008DFC_VADDR(x)                                           (((x) & 0xFF) << 0)
+#define   G_008DFC_VADDR(x)                                           (((x) >> 0) & 0xFF)
+#define   C_008DFC_VADDR                                              0xFFFFFF00
+#define     V_008DFC_SQ_VGPR                                        0x00
+#define   S_008DFC_VDATA(x)                                           (((x) & 0xFF) << 8)
+#define   G_008DFC_VDATA(x)                                           (((x) >> 8) & 0xFF)
+#define   C_008DFC_VDATA                                              0xFFFF00FF
+#define     V_008DFC_SQ_VGPR                                        0x00
+#define   S_008DFC_SRSRC(x)                                           (((x) & 0x1F) << 16)
+#define   G_008DFC_SRSRC(x)                                           (((x) >> 16) & 0x1F)
+#define   C_008DFC_SRSRC                                              0xFFE0FFFF
+#define   S_008DFC_SSAMP(x)                                           (((x) & 0x1F) << 21)
+#define   G_008DFC_SSAMP(x)                                           (((x) >> 21) & 0x1F)
+#define   C_008DFC_SSAMP                                              0xFC1FFFFF
+#define R_008DFC_SQ_VOP3_1                                              0x008DFC
+#define   S_008DFC_SRC0(x)                                            (((x) & 0x1FF) << 0)
+#define   G_008DFC_SRC0(x)                                            (((x) >> 0) & 0x1FF)
+#define   C_008DFC_SRC0                                               0xFFFFFE00
+#define     V_008DFC_SQ_SGPR                                        0x00
+/* CIK */
+#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
+#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
+/*     */
+#define     V_008DFC_SQ_VCC_LO                                      0x6A
+#define     V_008DFC_SQ_VCC_HI                                      0x6B
+#define     V_008DFC_SQ_TBA_LO                                      0x6C
+#define     V_008DFC_SQ_TBA_HI                                      0x6D
+#define     V_008DFC_SQ_TMA_LO                                      0x6E
+#define     V_008DFC_SQ_TMA_HI                                      0x6F
+#define     V_008DFC_SQ_TTMP0                                       0x70
+#define     V_008DFC_SQ_TTMP1                                       0x71
+#define     V_008DFC_SQ_TTMP2                                       0x72
+#define     V_008DFC_SQ_TTMP3                                       0x73
+#define     V_008DFC_SQ_TTMP4                                       0x74
+#define     V_008DFC_SQ_TTMP5                                       0x75
+#define     V_008DFC_SQ_TTMP6                                       0x76
+#define     V_008DFC_SQ_TTMP7                                       0x77
+#define     V_008DFC_SQ_TTMP8                                       0x78
+#define     V_008DFC_SQ_TTMP9                                       0x79
+#define     V_008DFC_SQ_TTMP10                                      0x7A
+#define     V_008DFC_SQ_TTMP11                                      0x7B
+#define     V_008DFC_SQ_M0                                          0x7C
+#define     V_008DFC_SQ_EXEC_LO                                     0x7E
+#define     V_008DFC_SQ_EXEC_HI                                     0x7F
+#define     V_008DFC_SQ_SRC_0                                       0x80
+#define     V_008DFC_SQ_SRC_1_INT                                   0x81
+#define     V_008DFC_SQ_SRC_2_INT                                   0x82
+#define     V_008DFC_SQ_SRC_3_INT                                   0x83
+#define     V_008DFC_SQ_SRC_4_INT                                   0x84
+#define     V_008DFC_SQ_SRC_5_INT                                   0x85
+#define     V_008DFC_SQ_SRC_6_INT                                   0x86
+#define     V_008DFC_SQ_SRC_7_INT                                   0x87
+#define     V_008DFC_SQ_SRC_8_INT                                   0x88
+#define     V_008DFC_SQ_SRC_9_INT                                   0x89
+#define     V_008DFC_SQ_SRC_10_INT                                  0x8A
+#define     V_008DFC_SQ_SRC_11_INT                                  0x8B
+#define     V_008DFC_SQ_SRC_12_INT                                  0x8C
+#define     V_008DFC_SQ_SRC_13_INT                                  0x8D
+#define     V_008DFC_SQ_SRC_14_INT                                  0x8E
+#define     V_008DFC_SQ_SRC_15_INT                                  0x8F
+#define     V_008DFC_SQ_SRC_16_INT                                  0x90
+#define     V_008DFC_SQ_SRC_17_INT                                  0x91
+#define     V_008DFC_SQ_SRC_18_INT                                  0x92
+#define     V_008DFC_SQ_SRC_19_INT                                  0x93
+#define     V_008DFC_SQ_SRC_20_INT                                  0x94
+#define     V_008DFC_SQ_SRC_21_INT                                  0x95
+#define     V_008DFC_SQ_SRC_22_INT                                  0x96
+#define     V_008DFC_SQ_SRC_23_INT                                  0x97
+#define     V_008DFC_SQ_SRC_24_INT                                  0x98
+#define     V_008DFC_SQ_SRC_25_INT                                  0x99
+#define     V_008DFC_SQ_SRC_26_INT                                  0x9A
+#define     V_008DFC_SQ_SRC_27_INT                                  0x9B
+#define     V_008DFC_SQ_SRC_28_INT                                  0x9C
+#define     V_008DFC_SQ_SRC_29_INT                                  0x9D
+#define     V_008DFC_SQ_SRC_30_INT                                  0x9E
+#define     V_008DFC_SQ_SRC_31_INT                                  0x9F
+#define     V_008DFC_SQ_SRC_32_INT                                  0xA0
+#define     V_008DFC_SQ_SRC_33_INT                                  0xA1
+#define     V_008DFC_SQ_SRC_34_INT                                  0xA2
+#define     V_008DFC_SQ_SRC_35_INT                                  0xA3
+#define     V_008DFC_SQ_SRC_36_INT                                  0xA4
+#define     V_008DFC_SQ_SRC_37_INT                                  0xA5
+#define     V_008DFC_SQ_SRC_38_INT                                  0xA6
+#define     V_008DFC_SQ_SRC_39_INT                                  0xA7
+#define     V_008DFC_SQ_SRC_40_INT                                  0xA8
+#define     V_008DFC_SQ_SRC_41_INT                                  0xA9
+#define     V_008DFC_SQ_SRC_42_INT                                  0xAA
+#define     V_008DFC_SQ_SRC_43_INT                                  0xAB
+#define     V_008DFC_SQ_SRC_44_INT                                  0xAC
+#define     V_008DFC_SQ_SRC_45_INT                                  0xAD
+#define     V_008DFC_SQ_SRC_46_INT                                  0xAE
+#define     V_008DFC_SQ_SRC_47_INT                                  0xAF
+#define     V_008DFC_SQ_SRC_48_INT                                  0xB0
+#define     V_008DFC_SQ_SRC_49_INT                                  0xB1
+#define     V_008DFC_SQ_SRC_50_INT                                  0xB2
+#define     V_008DFC_SQ_SRC_51_INT                                  0xB3
+#define     V_008DFC_SQ_SRC_52_INT                                  0xB4
+#define     V_008DFC_SQ_SRC_53_INT                                  0xB5
+#define     V_008DFC_SQ_SRC_54_INT                                  0xB6
+#define     V_008DFC_SQ_SRC_55_INT                                  0xB7
+#define     V_008DFC_SQ_SRC_56_INT                                  0xB8
+#define     V_008DFC_SQ_SRC_57_INT                                  0xB9
+#define     V_008DFC_SQ_SRC_58_INT                                  0xBA
+#define     V_008DFC_SQ_SRC_59_INT                                  0xBB
+#define     V_008DFC_SQ_SRC_60_INT                                  0xBC
+#define     V_008DFC_SQ_SRC_61_INT                                  0xBD
+#define     V_008DFC_SQ_SRC_62_INT                                  0xBE
+#define     V_008DFC_SQ_SRC_63_INT                                  0xBF
+#define     V_008DFC_SQ_SRC_64_INT                                  0xC0
+#define     V_008DFC_SQ_SRC_M_1_INT                                 0xC1
+#define     V_008DFC_SQ_SRC_M_2_INT                                 0xC2
+#define     V_008DFC_SQ_SRC_M_3_INT                                 0xC3
+#define     V_008DFC_SQ_SRC_M_4_INT                                 0xC4
+#define     V_008DFC_SQ_SRC_M_5_INT                                 0xC5
+#define     V_008DFC_SQ_SRC_M_6_INT                                 0xC6
+#define     V_008DFC_SQ_SRC_M_7_INT                                 0xC7
+#define     V_008DFC_SQ_SRC_M_8_INT                                 0xC8
+#define     V_008DFC_SQ_SRC_M_9_INT                                 0xC9
+#define     V_008DFC_SQ_SRC_M_10_INT                                0xCA
+#define     V_008DFC_SQ_SRC_M_11_INT                                0xCB
+#define     V_008DFC_SQ_SRC_M_12_INT                                0xCC
+#define     V_008DFC_SQ_SRC_M_13_INT                                0xCD
+#define     V_008DFC_SQ_SRC_M_14_INT                                0xCE
+#define     V_008DFC_SQ_SRC_M_15_INT                                0xCF
+#define     V_008DFC_SQ_SRC_M_16_INT                                0xD0
+#define     V_008DFC_SQ_SRC_0_5                                     0xF0
+#define     V_008DFC_SQ_SRC_M_0_5                                   0xF1
+#define     V_008DFC_SQ_SRC_1                                       0xF2
+#define     V_008DFC_SQ_SRC_M_1                                     0xF3
+#define     V_008DFC_SQ_SRC_2                                       0xF4
+#define     V_008DFC_SQ_SRC_M_2                                     0xF5
+#define     V_008DFC_SQ_SRC_4                                       0xF6
+#define     V_008DFC_SQ_SRC_M_4                                     0xF7
+#define     V_008DFC_SQ_SRC_VCCZ                                    0xFB
+#define     V_008DFC_SQ_SRC_EXECZ                                   0xFC
+#define     V_008DFC_SQ_SRC_SCC                                     0xFD
+#define     V_008DFC_SQ_SRC_LDS_DIRECT                              0xFE
+#define     V_008DFC_SQ_SRC_VGPR                                    0x100
+#define   S_008DFC_SRC1(x)                                            (((x) & 0x1FF) << 9)
+#define   G_008DFC_SRC1(x)                                            (((x) >> 9) & 0x1FF)
+#define   C_008DFC_SRC1                                               0xFFFC01FF
+#define     V_008DFC_SQ_SGPR                                        0x00
+/* CIK */
+#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
+#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
+/*     */
+#define     V_008DFC_SQ_VCC_LO                                      0x6A
+#define     V_008DFC_SQ_VCC_HI                                      0x6B
+#define     V_008DFC_SQ_TBA_LO                                      0x6C
+#define     V_008DFC_SQ_TBA_HI                                      0x6D
+#define     V_008DFC_SQ_TMA_LO                                      0x6E
+#define     V_008DFC_SQ_TMA_HI                                      0x6F
+#define     V_008DFC_SQ_TTMP0                                       0x70
+#define     V_008DFC_SQ_TTMP1                                       0x71
+#define     V_008DFC_SQ_TTMP2                                       0x72
+#define     V_008DFC_SQ_TTMP3                                       0x73
+#define     V_008DFC_SQ_TTMP4                                       0x74
+#define     V_008DFC_SQ_TTMP5                                       0x75
+#define     V_008DFC_SQ_TTMP6                                       0x76
+#define     V_008DFC_SQ_TTMP7                                       0x77
+#define     V_008DFC_SQ_TTMP8                                       0x78
+#define     V_008DFC_SQ_TTMP9                                       0x79
+#define     V_008DFC_SQ_TTMP10                                      0x7A
+#define     V_008DFC_SQ_TTMP11                                      0x7B
+#define     V_008DFC_SQ_M0                                          0x7C
+#define     V_008DFC_SQ_EXEC_LO                                     0x7E
+#define     V_008DFC_SQ_EXEC_HI                                     0x7F
+#define     V_008DFC_SQ_SRC_0                                       0x80
+#define     V_008DFC_SQ_SRC_1_INT                                   0x81
+#define     V_008DFC_SQ_SRC_2_INT                                   0x82
+#define     V_008DFC_SQ_SRC_3_INT                                   0x83
+#define     V_008DFC_SQ_SRC_4_INT                                   0x84
+#define     V_008DFC_SQ_SRC_5_INT                                   0x85
+#define     V_008DFC_SQ_SRC_6_INT                                   0x86
+#define     V_008DFC_SQ_SRC_7_INT                                   0x87
+#define     V_008DFC_SQ_SRC_8_INT                                   0x88
+#define     V_008DFC_SQ_SRC_9_INT                                   0x89
+#define     V_008DFC_SQ_SRC_10_INT                                  0x8A
+#define     V_008DFC_SQ_SRC_11_INT                                  0x8B
+#define     V_008DFC_SQ_SRC_12_INT                                  0x8C
+#define     V_008DFC_SQ_SRC_13_INT                                  0x8D
+#define     V_008DFC_SQ_SRC_14_INT                                  0x8E
+#define     V_008DFC_SQ_SRC_15_INT                                  0x8F
+#define     V_008DFC_SQ_SRC_16_INT                                  0x90
+#define     V_008DFC_SQ_SRC_17_INT                                  0x91
+#define     V_008DFC_SQ_SRC_18_INT                                  0x92
+#define     V_008DFC_SQ_SRC_19_INT                                  0x93
+#define     V_008DFC_SQ_SRC_20_INT                                  0x94
+#define     V_008DFC_SQ_SRC_21_INT                                  0x95
+#define     V_008DFC_SQ_SRC_22_INT                                  0x96
+#define     V_008DFC_SQ_SRC_23_INT                                  0x97
+#define     V_008DFC_SQ_SRC_24_INT                                  0x98
+#define     V_008DFC_SQ_SRC_25_INT                                  0x99
+#define     V_008DFC_SQ_SRC_26_INT                                  0x9A
+#define     V_008DFC_SQ_SRC_27_INT                                  0x9B
+#define     V_008DFC_SQ_SRC_28_INT                                  0x9C
+#define     V_008DFC_SQ_SRC_29_INT                                  0x9D
+#define     V_008DFC_SQ_SRC_30_INT                                  0x9E
+#define     V_008DFC_SQ_SRC_31_INT                                  0x9F
+#define     V_008DFC_SQ_SRC_32_INT                                  0xA0
+#define     V_008DFC_SQ_SRC_33_INT                                  0xA1
+#define     V_008DFC_SQ_SRC_34_INT                                  0xA2
+#define     V_008DFC_SQ_SRC_35_INT                                  0xA3
+#define     V_008DFC_SQ_SRC_36_INT                                  0xA4
+#define     V_008DFC_SQ_SRC_37_INT                                  0xA5
+#define     V_008DFC_SQ_SRC_38_INT                                  0xA6
+#define     V_008DFC_SQ_SRC_39_INT                                  0xA7
+#define     V_008DFC_SQ_SRC_40_INT                                  0xA8
+#define     V_008DFC_SQ_SRC_41_INT                                  0xA9
+#define     V_008DFC_SQ_SRC_42_INT                                  0xAA
+#define     V_008DFC_SQ_SRC_43_INT                                  0xAB
+#define     V_008DFC_SQ_SRC_44_INT                                  0xAC
+#define     V_008DFC_SQ_SRC_45_INT                                  0xAD
+#define     V_008DFC_SQ_SRC_46_INT                                  0xAE
+#define     V_008DFC_SQ_SRC_47_INT                                  0xAF
+#define     V_008DFC_SQ_SRC_48_INT                                  0xB0
+#define     V_008DFC_SQ_SRC_49_INT                                  0xB1
+#define     V_008DFC_SQ_SRC_50_INT                                  0xB2
+#define     V_008DFC_SQ_SRC_51_INT                                  0xB3
+#define     V_008DFC_SQ_SRC_52_INT                                  0xB4
+#define     V_008DFC_SQ_SRC_53_INT                                  0xB5
+#define     V_008DFC_SQ_SRC_54_INT                                  0xB6
+#define     V_008DFC_SQ_SRC_55_INT                                  0xB7
+#define     V_008DFC_SQ_SRC_56_INT                                  0xB8
+#define     V_008DFC_SQ_SRC_57_INT                                  0xB9
+#define     V_008DFC_SQ_SRC_58_INT                                  0xBA
+#define     V_008DFC_SQ_SRC_59_INT                                  0xBB
+#define     V_008DFC_SQ_SRC_60_INT                                  0xBC
+#define     V_008DFC_SQ_SRC_61_INT                                  0xBD
+#define     V_008DFC_SQ_SRC_62_INT                                  0xBE
+#define     V_008DFC_SQ_SRC_63_INT                                  0xBF
+#define     V_008DFC_SQ_SRC_64_INT                                  0xC0
+#define     V_008DFC_SQ_SRC_M_1_INT                                 0xC1
+#define     V_008DFC_SQ_SRC_M_2_INT                                 0xC2
+#define     V_008DFC_SQ_SRC_M_3_INT                                 0xC3
+#define     V_008DFC_SQ_SRC_M_4_INT                                 0xC4
+#define     V_008DFC_SQ_SRC_M_5_INT                                 0xC5
+#define     V_008DFC_SQ_SRC_M_6_INT                                 0xC6
+#define     V_008DFC_SQ_SRC_M_7_INT                                 0xC7
+#define     V_008DFC_SQ_SRC_M_8_INT                                 0xC8
+#define     V_008DFC_SQ_SRC_M_9_INT                                 0xC9
+#define     V_008DFC_SQ_SRC_M_10_INT                                0xCA
+#define     V_008DFC_SQ_SRC_M_11_INT                                0xCB
+#define     V_008DFC_SQ_SRC_M_12_INT                                0xCC
+#define     V_008DFC_SQ_SRC_M_13_INT                                0xCD
+#define     V_008DFC_SQ_SRC_M_14_INT                                0xCE
+#define     V_008DFC_SQ_SRC_M_15_INT                                0xCF
+#define     V_008DFC_SQ_SRC_M_16_INT                                0xD0
+#define     V_008DFC_SQ_SRC_0_5                                     0xF0
+#define     V_008DFC_SQ_SRC_M_0_5                                   0xF1
+#define     V_008DFC_SQ_SRC_1                                       0xF2
+#define     V_008DFC_SQ_SRC_M_1                                     0xF3
+#define     V_008DFC_SQ_SRC_2                                       0xF4
+#define     V_008DFC_SQ_SRC_M_2                                     0xF5
+#define     V_008DFC_SQ_SRC_4                                       0xF6
+#define     V_008DFC_SQ_SRC_M_4                                     0xF7
+#define     V_008DFC_SQ_SRC_VCCZ                                    0xFB
+#define     V_008DFC_SQ_SRC_EXECZ                                   0xFC
+#define     V_008DFC_SQ_SRC_SCC                                     0xFD
+#define     V_008DFC_SQ_SRC_LDS_DIRECT                              0xFE
+#define     V_008DFC_SQ_SRC_VGPR                                    0x100
+#define   S_008DFC_SRC2(x)                                            (((x) & 0x1FF) << 18)
+#define   G_008DFC_SRC2(x)                                            (((x) >> 18) & 0x1FF)
+#define   C_008DFC_SRC2                                               0xF803FFFF
+#define     V_008DFC_SQ_SGPR                                        0x00
+/* CIK */
+#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
+#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
+/*     */
+#define     V_008DFC_SQ_VCC_LO                                      0x6A
+#define     V_008DFC_SQ_VCC_HI                                      0x6B
+#define     V_008DFC_SQ_TBA_LO                                      0x6C
+#define     V_008DFC_SQ_TBA_HI                                      0x6D
+#define     V_008DFC_SQ_TMA_LO                                      0x6E
+#define     V_008DFC_SQ_TMA_HI                                      0x6F
+#define     V_008DFC_SQ_TTMP0                                       0x70
+#define     V_008DFC_SQ_TTMP1                                       0x71
+#define     V_008DFC_SQ_TTMP2                                       0x72
+#define     V_008DFC_SQ_TTMP3                                       0x73
+#define     V_008DFC_SQ_TTMP4                                       0x74
+#define     V_008DFC_SQ_TTMP5                                       0x75
+#define     V_008DFC_SQ_TTMP6                                       0x76
+#define     V_008DFC_SQ_TTMP7                                       0x77
+#define     V_008DFC_SQ_TTMP8                                       0x78
+#define     V_008DFC_SQ_TTMP9                                       0x79
+#define     V_008DFC_SQ_TTMP10                                      0x7A
+#define     V_008DFC_SQ_TTMP11                                      0x7B
+#define     V_008DFC_SQ_M0                                          0x7C
+#define     V_008DFC_SQ_EXEC_LO                                     0x7E
+#define     V_008DFC_SQ_EXEC_HI                                     0x7F
+#define     V_008DFC_SQ_SRC_0                                       0x80
+#define     V_008DFC_SQ_SRC_1_INT                                   0x81
+#define     V_008DFC_SQ_SRC_2_INT                                   0x82
+#define     V_008DFC_SQ_SRC_3_INT                                   0x83
+#define     V_008DFC_SQ_SRC_4_INT                                   0x84
+#define     V_008DFC_SQ_SRC_5_INT                                   0x85
+#define     V_008DFC_SQ_SRC_6_INT                                   0x86
+#define     V_008DFC_SQ_SRC_7_INT                                   0x87
+#define     V_008DFC_SQ_SRC_8_INT                                   0x88
+#define     V_008DFC_SQ_SRC_9_INT                                   0x89
+#define     V_008DFC_SQ_SRC_10_INT                                  0x8A
+#define     V_008DFC_SQ_SRC_11_INT                                  0x8B
+#define     V_008DFC_SQ_SRC_12_INT                                  0x8C
+#define     V_008DFC_SQ_SRC_13_INT                                  0x8D
+#define     V_008DFC_SQ_SRC_14_INT                                  0x8E
+#define     V_008DFC_SQ_SRC_15_INT                                  0x8F
+#define     V_008DFC_SQ_SRC_16_INT                                  0x90
+#define     V_008DFC_SQ_SRC_17_INT                                  0x91
+#define     V_008DFC_SQ_SRC_18_INT                                  0x92
+#define     V_008DFC_SQ_SRC_19_INT                                  0x93
+#define     V_008DFC_SQ_SRC_20_INT                                  0x94
+#define     V_008DFC_SQ_SRC_21_INT                                  0x95
+#define     V_008DFC_SQ_SRC_22_INT                                  0x96
+#define     V_008DFC_SQ_SRC_23_INT                                  0x97
+#define     V_008DFC_SQ_SRC_24_INT                                  0x98
+#define     V_008DFC_SQ_SRC_25_INT                                  0x99
+#define     V_008DFC_SQ_SRC_26_INT                                  0x9A
+#define     V_008DFC_SQ_SRC_27_INT                                  0x9B
+#define     V_008DFC_SQ_SRC_28_INT                                  0x9C
+#define     V_008DFC_SQ_SRC_29_INT                                  0x9D
+#define     V_008DFC_SQ_SRC_30_INT                                  0x9E
+#define     V_008DFC_SQ_SRC_31_INT                                  0x9F
+#define     V_008DFC_SQ_SRC_32_INT                                  0xA0
+#define     V_008DFC_SQ_SRC_33_INT                                  0xA1
+#define     V_008DFC_SQ_SRC_34_INT                                  0xA2
+#define     V_008DFC_SQ_SRC_35_INT                                  0xA3
+#define     V_008DFC_SQ_SRC_36_INT                                  0xA4
+#define     V_008DFC_SQ_SRC_37_INT                                  0xA5
+#define     V_008DFC_SQ_SRC_38_INT                                  0xA6
+#define     V_008DFC_SQ_SRC_39_INT                                  0xA7
+#define     V_008DFC_SQ_SRC_40_INT                                  0xA8
+#define     V_008DFC_SQ_SRC_41_INT                                  0xA9
+#define     V_008DFC_SQ_SRC_42_INT                                  0xAA
+#define     V_008DFC_SQ_SRC_43_INT                                  0xAB
+#define     V_008DFC_SQ_SRC_44_INT                                  0xAC
+#define     V_008DFC_SQ_SRC_45_INT                                  0xAD
+#define     V_008DFC_SQ_SRC_46_INT                                  0xAE
+#define     V_008DFC_SQ_SRC_47_INT                                  0xAF
+#define     V_008DFC_SQ_SRC_48_INT                                  0xB0
+#define     V_008DFC_SQ_SRC_49_INT                                  0xB1
+#define     V_008DFC_SQ_SRC_50_INT                                  0xB2
+#define     V_008DFC_SQ_SRC_51_INT                                  0xB3
+#define     V_008DFC_SQ_SRC_52_INT                                  0xB4
+#define     V_008DFC_SQ_SRC_53_INT                                  0xB5
+#define     V_008DFC_SQ_SRC_54_INT                                  0xB6
+#define     V_008DFC_SQ_SRC_55_INT                                  0xB7
+#define     V_008DFC_SQ_SRC_56_INT                                  0xB8
+#define     V_008DFC_SQ_SRC_57_INT                                  0xB9
+#define     V_008DFC_SQ_SRC_58_INT                                  0xBA
+#define     V_008DFC_SQ_SRC_59_INT                                  0xBB
+#define     V_008DFC_SQ_SRC_60_INT                                  0xBC
+#define     V_008DFC_SQ_SRC_61_INT                                  0xBD
+#define     V_008DFC_SQ_SRC_62_INT                                  0xBE
+#define     V_008DFC_SQ_SRC_63_INT                                  0xBF
+#define     V_008DFC_SQ_SRC_64_INT                                  0xC0
+#define     V_008DFC_SQ_SRC_M_1_INT                                 0xC1
+#define     V_008DFC_SQ_SRC_M_2_INT                                 0xC2
+#define     V_008DFC_SQ_SRC_M_3_INT                                 0xC3
+#define     V_008DFC_SQ_SRC_M_4_INT                                 0xC4
+#define     V_008DFC_SQ_SRC_M_5_INT                                 0xC5
+#define     V_008DFC_SQ_SRC_M_6_INT                                 0xC6
+#define     V_008DFC_SQ_SRC_M_7_INT                                 0xC7
+#define     V_008DFC_SQ_SRC_M_8_INT                                 0xC8
+#define     V_008DFC_SQ_SRC_M_9_INT                                 0xC9
+#define     V_008DFC_SQ_SRC_M_10_INT                                0xCA
+#define     V_008DFC_SQ_SRC_M_11_INT                                0xCB
+#define     V_008DFC_SQ_SRC_M_12_INT                                0xCC
+#define     V_008DFC_SQ_SRC_M_13_INT                                0xCD
+#define     V_008DFC_SQ_SRC_M_14_INT                                0xCE
+#define     V_008DFC_SQ_SRC_M_15_INT                                0xCF
+#define     V_008DFC_SQ_SRC_M_16_INT                                0xD0
+#define     V_008DFC_SQ_SRC_0_5                                     0xF0
+#define     V_008DFC_SQ_SRC_M_0_5                                   0xF1
+#define     V_008DFC_SQ_SRC_1                                       0xF2
+#define     V_008DFC_SQ_SRC_M_1                                     0xF3
+#define     V_008DFC_SQ_SRC_2                                       0xF4
+#define     V_008DFC_SQ_SRC_M_2                                     0xF5
+#define     V_008DFC_SQ_SRC_4                                       0xF6
+#define     V_008DFC_SQ_SRC_M_4                                     0xF7
+#define     V_008DFC_SQ_SRC_VCCZ                                    0xFB
+#define     V_008DFC_SQ_SRC_EXECZ                                   0xFC
+#define     V_008DFC_SQ_SRC_SCC                                     0xFD
+#define     V_008DFC_SQ_SRC_LDS_DIRECT                              0xFE
+#define     V_008DFC_SQ_SRC_VGPR                                    0x100
+#define   S_008DFC_OMOD(x)                                            (((x) & 0x03) << 27)
+#define   G_008DFC_OMOD(x)                                            (((x) >> 27) & 0x03)
+#define   C_008DFC_OMOD                                               0xE7FFFFFF
+#define     V_008DFC_SQ_OMOD_OFF                                    0x00
+#define     V_008DFC_SQ_OMOD_M2                                     0x01
+#define     V_008DFC_SQ_OMOD_M4                                     0x02
+#define     V_008DFC_SQ_OMOD_D2                                     0x03
+#define   S_008DFC_NEG(x)                                             (((x) & 0x07) << 29)
+#define   G_008DFC_NEG(x)                                             (((x) >> 29) & 0x07)
+#define   C_008DFC_NEG                                                0x1FFFFFFF
+#define R_008DFC_SQ_MUBUF_1                                             0x008DFC
+#define   S_008DFC_VADDR(x)                                           (((x) & 0xFF) << 0)
+#define   G_008DFC_VADDR(x)                                           (((x) >> 0) & 0xFF)
+#define   C_008DFC_VADDR                                              0xFFFFFF00
+#define     V_008DFC_SQ_VGPR                                        0x00
+#define   S_008DFC_VDATA(x)                                           (((x) & 0xFF) << 8)
+#define   G_008DFC_VDATA(x)                                           (((x) >> 8) & 0xFF)
+#define   C_008DFC_VDATA                                              0xFFFF00FF
+#define     V_008DFC_SQ_VGPR                                        0x00
+#define   S_008DFC_SRSRC(x)                                           (((x) & 0x1F) << 16)
+#define   G_008DFC_SRSRC(x)                                           (((x) >> 16) & 0x1F)
+#define   C_008DFC_SRSRC                                              0xFFE0FFFF
+#define   S_008DFC_SLC(x)                                             (((x) & 0x1) << 22)
+#define   G_008DFC_SLC(x)                                             (((x) >> 22) & 0x1)
+#define   C_008DFC_SLC                                                0xFFBFFFFF
+#define   S_008DFC_TFE(x)                                             (((x) & 0x1) << 23)
+#define   G_008DFC_TFE(x)                                             (((x) >> 23) & 0x1)
+#define   C_008DFC_TFE                                                0xFF7FFFFF
+#define   S_008DFC_SOFFSET(x)                                         (((x) & 0xFF) << 24)
+#define   G_008DFC_SOFFSET(x)                                         (((x) >> 24) & 0xFF)
+#define   C_008DFC_SOFFSET                                            0x00FFFFFF
+#define     V_008DFC_SQ_SGPR                                        0x00
+/* CIK */
+#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
+#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
+/*     */
+#define     V_008DFC_SQ_VCC_LO                                      0x6A
+#define     V_008DFC_SQ_VCC_HI                                      0x6B
+#define     V_008DFC_SQ_TBA_LO                                      0x6C
+#define     V_008DFC_SQ_TBA_HI                                      0x6D
+#define     V_008DFC_SQ_TMA_LO                                      0x6E
+#define     V_008DFC_SQ_TMA_HI                                      0x6F
+#define     V_008DFC_SQ_TTMP0                                       0x70
+#define     V_008DFC_SQ_TTMP1                                       0x71
+#define     V_008DFC_SQ_TTMP2                                       0x72
+#define     V_008DFC_SQ_TTMP3                                       0x73
+#define     V_008DFC_SQ_TTMP4                                       0x74
+#define     V_008DFC_SQ_TTMP5                                       0x75
+#define     V_008DFC_SQ_TTMP6                                       0x76
+#define     V_008DFC_SQ_TTMP7                                       0x77
+#define     V_008DFC_SQ_TTMP8                                       0x78
+#define     V_008DFC_SQ_TTMP9                                       0x79
+#define     V_008DFC_SQ_TTMP10                                      0x7A
+#define     V_008DFC_SQ_TTMP11                                      0x7B
+#define     V_008DFC_SQ_M0                                          0x7C
+#define     V_008DFC_SQ_EXEC_LO                                     0x7E
+#define     V_008DFC_SQ_EXEC_HI                                     0x7F
+#define     V_008DFC_SQ_SRC_0                                       0x80
+#define     V_008DFC_SQ_SRC_1_INT                                   0x81
+#define     V_008DFC_SQ_SRC_2_INT                                   0x82
+#define     V_008DFC_SQ_SRC_3_INT                                   0x83
+#define     V_008DFC_SQ_SRC_4_INT                                   0x84
+#define     V_008DFC_SQ_SRC_5_INT                                   0x85
+#define     V_008DFC_SQ_SRC_6_INT                                   0x86
+#define     V_008DFC_SQ_SRC_7_INT                                   0x87
+#define     V_008DFC_SQ_SRC_8_INT                                   0x88
+#define     V_008DFC_SQ_SRC_9_INT                                   0x89
+#define     V_008DFC_SQ_SRC_10_INT                                  0x8A
+#define     V_008DFC_SQ_SRC_11_INT                                  0x8B
+#define     V_008DFC_SQ_SRC_12_INT                                  0x8C
+#define     V_008DFC_SQ_SRC_13_INT                                  0x8D
+#define     V_008DFC_SQ_SRC_14_INT                                  0x8E
+#define     V_008DFC_SQ_SRC_15_INT                                  0x8F
+#define     V_008DFC_SQ_SRC_16_INT                                  0x90
+#define     V_008DFC_SQ_SRC_17_INT                                  0x91
+#define     V_008DFC_SQ_SRC_18_INT                                  0x92
+#define     V_008DFC_SQ_SRC_19_INT                                  0x93
+#define     V_008DFC_SQ_SRC_20_INT                                  0x94
+#define     V_008DFC_SQ_SRC_21_INT                                  0x95
+#define     V_008DFC_SQ_SRC_22_INT                                  0x96
+#define     V_008DFC_SQ_SRC_23_INT                                  0x97
+#define     V_008DFC_SQ_SRC_24_INT                                  0x98
+#define     V_008DFC_SQ_SRC_25_INT                                  0x99
+#define     V_008DFC_SQ_SRC_26_INT                                  0x9A
+#define     V_008DFC_SQ_SRC_27_INT                                  0x9B
+#define     V_008DFC_SQ_SRC_28_INT                                  0x9C
+#define     V_008DFC_SQ_SRC_29_INT                                  0x9D
+#define     V_008DFC_SQ_SRC_30_INT                                  0x9E
+#define     V_008DFC_SQ_SRC_31_INT                                  0x9F
+#define     V_008DFC_SQ_SRC_32_INT                                  0xA0
+#define     V_008DFC_SQ_SRC_33_INT                                  0xA1
+#define     V_008DFC_SQ_SRC_34_INT                                  0xA2
+#define     V_008DFC_SQ_SRC_35_INT                                  0xA3
+#define     V_008DFC_SQ_SRC_36_INT                                  0xA4
+#define     V_008DFC_SQ_SRC_37_INT                                  0xA5
+#define     V_008DFC_SQ_SRC_38_INT                                  0xA6
+#define     V_008DFC_SQ_SRC_39_INT                                  0xA7
+#define     V_008DFC_SQ_SRC_40_INT                                  0xA8
+#define     V_008DFC_SQ_SRC_41_INT                                  0xA9
+#define     V_008DFC_SQ_SRC_42_INT                                  0xAA
+#define     V_008DFC_SQ_SRC_43_INT                                  0xAB
+#define     V_008DFC_SQ_SRC_44_INT                                  0xAC
+#define     V_008DFC_SQ_SRC_45_INT                                  0xAD
+#define     V_008DFC_SQ_SRC_46_INT                                  0xAE
+#define     V_008DFC_SQ_SRC_47_INT                                  0xAF
+#define     V_008DFC_SQ_SRC_48_INT                                  0xB0
+#define     V_008DFC_SQ_SRC_49_INT                                  0xB1
+#define     V_008DFC_SQ_SRC_50_INT                                  0xB2
+#define     V_008DFC_SQ_SRC_51_INT                                  0xB3
+#define     V_008DFC_SQ_SRC_52_INT                                  0xB4
+#define     V_008DFC_SQ_SRC_53_INT                                  0xB5
+#define     V_008DFC_SQ_SRC_54_INT                                  0xB6
+#define     V_008DFC_SQ_SRC_55_INT                                  0xB7
+#define     V_008DFC_SQ_SRC_56_INT                                  0xB8
+#define     V_008DFC_SQ_SRC_57_INT                                  0xB9
+#define     V_008DFC_SQ_SRC_58_INT                                  0xBA
+#define     V_008DFC_SQ_SRC_59_INT                                  0xBB
+#define     V_008DFC_SQ_SRC_60_INT                                  0xBC
+#define     V_008DFC_SQ_SRC_61_INT                                  0xBD
+#define     V_008DFC_SQ_SRC_62_INT                                  0xBE
+#define     V_008DFC_SQ_SRC_63_INT                                  0xBF
+#define     V_008DFC_SQ_SRC_64_INT                                  0xC0
+#define     V_008DFC_SQ_SRC_M_1_INT                                 0xC1
+#define     V_008DFC_SQ_SRC_M_2_INT                                 0xC2
+#define     V_008DFC_SQ_SRC_M_3_INT                                 0xC3
+#define     V_008DFC_SQ_SRC_M_4_INT                                 0xC4
+#define     V_008DFC_SQ_SRC_M_5_INT                                 0xC5
+#define     V_008DFC_SQ_SRC_M_6_INT                                 0xC6
+#define     V_008DFC_SQ_SRC_M_7_INT                                 0xC7
+#define     V_008DFC_SQ_SRC_M_8_INT                                 0xC8
+#define     V_008DFC_SQ_SRC_M_9_INT                                 0xC9
+#define     V_008DFC_SQ_SRC_M_10_INT                                0xCA
+#define     V_008DFC_SQ_SRC_M_11_INT                                0xCB
+#define     V_008DFC_SQ_SRC_M_12_INT                                0xCC
+#define     V_008DFC_SQ_SRC_M_13_INT                                0xCD
+#define     V_008DFC_SQ_SRC_M_14_INT                                0xCE
+#define     V_008DFC_SQ_SRC_M_15_INT                                0xCF
+#define     V_008DFC_SQ_SRC_M_16_INT                                0xD0
+#define     V_008DFC_SQ_SRC_0_5                                     0xF0
+#define     V_008DFC_SQ_SRC_M_0_5                                   0xF1
+#define     V_008DFC_SQ_SRC_1                                       0xF2
+#define     V_008DFC_SQ_SRC_M_1                                     0xF3
+#define     V_008DFC_SQ_SRC_2                                       0xF4
+#define     V_008DFC_SQ_SRC_M_2                                     0xF5
+#define     V_008DFC_SQ_SRC_4                                       0xF6
+#define     V_008DFC_SQ_SRC_M_4                                     0xF7
+#define     V_008DFC_SQ_SRC_VCCZ                                    0xFB
+#define     V_008DFC_SQ_SRC_EXECZ                                   0xFC
+#define     V_008DFC_SQ_SRC_SCC                                     0xFD
+#define     V_008DFC_SQ_SRC_LDS_DIRECT                              0xFE
+#define R_008DFC_SQ_DS_0                                                0x008DFC
+#define   S_008DFC_OFFSET0(x)                                         (((x) & 0xFF) << 0)
+#define   G_008DFC_OFFSET0(x)                                         (((x) >> 0) & 0xFF)
+#define   C_008DFC_OFFSET0                                            0xFFFFFF00
+#define   S_008DFC_OFFSET1(x)                                         (((x) & 0xFF) << 8)
+#define   G_008DFC_OFFSET1(x)                                         (((x) >> 8) & 0xFF)
+#define   C_008DFC_OFFSET1                                            0xFFFF00FF
+#define   S_008DFC_GDS(x)                                             (((x) & 0x1) << 17)
+#define   G_008DFC_GDS(x)                                             (((x) >> 17) & 0x1)
+#define   C_008DFC_GDS                                                0xFFFDFFFF
+#define   S_008DFC_OP(x)                                              (((x) & 0xFF) << 18)
+#define   G_008DFC_OP(x)                                              (((x) >> 18) & 0xFF)
+#define   C_008DFC_OP                                                 0xFC03FFFF
+#define     V_008DFC_SQ_DS_ADD_U32                                  0x00
+#define     V_008DFC_SQ_DS_SUB_U32                                  0x01
+#define     V_008DFC_SQ_DS_RSUB_U32                                 0x02
+#define     V_008DFC_SQ_DS_INC_U32                                  0x03
+#define     V_008DFC_SQ_DS_DEC_U32                                  0x04
+#define     V_008DFC_SQ_DS_MIN_I32                                  0x05
+#define     V_008DFC_SQ_DS_MAX_I32                                  0x06
+#define     V_008DFC_SQ_DS_MIN_U32                                  0x07
+#define     V_008DFC_SQ_DS_MAX_U32                                  0x08
+#define     V_008DFC_SQ_DS_AND_B32                                  0x09
+#define     V_008DFC_SQ_DS_OR_B32                                   0x0A
+#define     V_008DFC_SQ_DS_XOR_B32                                  0x0B
+#define     V_008DFC_SQ_DS_MSKOR_B32                                0x0C
+#define     V_008DFC_SQ_DS_WRITE_B32                                0x0D
+#define     V_008DFC_SQ_DS_WRITE2_B32                               0x0E
+#define     V_008DFC_SQ_DS_WRITE2ST64_B32                           0x0F
+#define     V_008DFC_SQ_DS_CMPST_B32                                0x10
+#define     V_008DFC_SQ_DS_CMPST_F32                                0x11
+#define     V_008DFC_SQ_DS_MIN_F32                                  0x12
+#define     V_008DFC_SQ_DS_MAX_F32                                  0x13
+/* CIK */
+#define     V_008DFC_SQ_DS_NOP                                      0x14
+/*     */
+#define     V_008DFC_SQ_DS_GWS_INIT                                 0x19
+#define     V_008DFC_SQ_DS_GWS_SEMA_V                               0x1A
+#define     V_008DFC_SQ_DS_GWS_SEMA_BR                              0x1B
+#define     V_008DFC_SQ_DS_GWS_SEMA_P                               0x1C
+#define     V_008DFC_SQ_DS_GWS_BARRIER                              0x1D
+#define     V_008DFC_SQ_DS_WRITE_B8                                 0x1E
+#define     V_008DFC_SQ_DS_WRITE_B16                                0x1F
+#define     V_008DFC_SQ_DS_ADD_RTN_U32                              0x20
+#define     V_008DFC_SQ_DS_SUB_RTN_U32                              0x21
+#define     V_008DFC_SQ_DS_RSUB_RTN_U32                             0x22
+#define     V_008DFC_SQ_DS_INC_RTN_U32                              0x23
+#define     V_008DFC_SQ_DS_DEC_RTN_U32                              0x24
+#define     V_008DFC_SQ_DS_MIN_RTN_I32                              0x25
+#define     V_008DFC_SQ_DS_MAX_RTN_I32                              0x26
+#define     V_008DFC_SQ_DS_MIN_RTN_U32                              0x27
+#define     V_008DFC_SQ_DS_MAX_RTN_U32                              0x28
+#define     V_008DFC_SQ_DS_AND_RTN_B32                              0x29
+#define     V_008DFC_SQ_DS_OR_RTN_B32                               0x2A
+#define     V_008DFC_SQ_DS_XOR_RTN_B32                              0x2B
+#define     V_008DFC_SQ_DS_MSKOR_RTN_B32                            0x2C
+#define     V_008DFC_SQ_DS_WRXCHG_RTN_B32                           0x2D
+#define     V_008DFC_SQ_DS_WRXCHG2_RTN_B32                          0x2E
+#define     V_008DFC_SQ_DS_WRXCHG2ST64_RTN_B32                      0x2F
+#define     V_008DFC_SQ_DS_CMPST_RTN_B32                            0x30
+#define     V_008DFC_SQ_DS_CMPST_RTN_F32                            0x31
+#define     V_008DFC_SQ_DS_MIN_RTN_F32                              0x32
+#define     V_008DFC_SQ_DS_MAX_RTN_F32                              0x33
+#define     V_008DFC_SQ_DS_SWIZZLE_B32                              0x35
+#define     V_008DFC_SQ_DS_READ_B32                                 0x36
+#define     V_008DFC_SQ_DS_READ2_B32                                0x37
+#define     V_008DFC_SQ_DS_READ2ST64_B32                            0x38
+#define     V_008DFC_SQ_DS_READ_I8                                  0x39
+#define     V_008DFC_SQ_DS_READ_U8                                  0x3A
+#define     V_008DFC_SQ_DS_READ_I16                                 0x3B
+#define     V_008DFC_SQ_DS_READ_U16                                 0x3C
+#define     V_008DFC_SQ_DS_CONSUME                                  0x3D
+#define     V_008DFC_SQ_DS_APPEND                                   0x3E
+#define     V_008DFC_SQ_DS_ORDERED_COUNT                            0x3F
+#define     V_008DFC_SQ_DS_ADD_U64                                  0x40
+#define     V_008DFC_SQ_DS_SUB_U64                                  0x41
+#define     V_008DFC_SQ_DS_RSUB_U64                                 0x42
+#define     V_008DFC_SQ_DS_INC_U64                                  0x43
+#define     V_008DFC_SQ_DS_DEC_U64                                  0x44
+#define     V_008DFC_SQ_DS_MIN_I64                                  0x45
+#define     V_008DFC_SQ_DS_MAX_I64                                  0x46
+#define     V_008DFC_SQ_DS_MIN_U64                                  0x47
+#define     V_008DFC_SQ_DS_MAX_U64                                  0x48
+#define     V_008DFC_SQ_DS_AND_B64                                  0x49
+#define     V_008DFC_SQ_DS_OR_B64                                   0x4A
+#define     V_008DFC_SQ_DS_XOR_B64                                  0x4B
+#define     V_008DFC_SQ_DS_MSKOR_B64                                0x4C
+#define     V_008DFC_SQ_DS_WRITE_B64                                0x4D
+#define     V_008DFC_SQ_DS_WRITE2_B64                               0x4E
+#define     V_008DFC_SQ_DS_WRITE2ST64_B64                           0x4F
+#define     V_008DFC_SQ_DS_CMPST_B64                                0x50
+#define     V_008DFC_SQ_DS_CMPST_F64                                0x51
+#define     V_008DFC_SQ_DS_MIN_F64                                  0x52
+#define     V_008DFC_SQ_DS_MAX_F64                                  0x53
+#define     V_008DFC_SQ_DS_ADD_RTN_U64                              0x60
+#define     V_008DFC_SQ_DS_SUB_RTN_U64                              0x61
+#define     V_008DFC_SQ_DS_RSUB_RTN_U64                             0x62
+#define     V_008DFC_SQ_DS_INC_RTN_U64                              0x63
+#define     V_008DFC_SQ_DS_DEC_RTN_U64                              0x64
+#define     V_008DFC_SQ_DS_MIN_RTN_I64                              0x65
+#define     V_008DFC_SQ_DS_MAX_RTN_I64                              0x66
+#define     V_008DFC_SQ_DS_MIN_RTN_U64                              0x67
+#define     V_008DFC_SQ_DS_MAX_RTN_U64                              0x68
+#define     V_008DFC_SQ_DS_AND_RTN_B64                              0x69
+#define     V_008DFC_SQ_DS_OR_RTN_B64                               0x6A
+#define     V_008DFC_SQ_DS_XOR_RTN_B64                              0x6B
+#define     V_008DFC_SQ_DS_MSKOR_RTN_B64                            0x6C
+#define     V_008DFC_SQ_DS_WRXCHG_RTN_B64                           0x6D
+#define     V_008DFC_SQ_DS_WRXCHG2_RTN_B64                          0x6E
+#define     V_008DFC_SQ_DS_WRXCHG2ST64_RTN_B64                      0x6F
+#define     V_008DFC_SQ_DS_CMPST_RTN_B64                            0x70
+#define     V_008DFC_SQ_DS_CMPST_RTN_F64                            0x71
+#define     V_008DFC_SQ_DS_MIN_RTN_F64                              0x72
+#define     V_008DFC_SQ_DS_MAX_RTN_F64                              0x73
+#define     V_008DFC_SQ_DS_READ_B64                                 0x76
+#define     V_008DFC_SQ_DS_READ2_B64                                0x77
+#define     V_008DFC_SQ_DS_READ2ST64_B64                            0x78
+/* CIK */
+#define     V_008DFC_SQ_DS_CONDXCHG32_RTN_B64                       0x7E
+/*     */
+#define     V_008DFC_SQ_DS_ADD_SRC2_U32                             0x80
+#define     V_008DFC_SQ_DS_SUB_SRC2_U32                             0x81
+#define     V_008DFC_SQ_DS_RSUB_SRC2_U32                            0x82
+#define     V_008DFC_SQ_DS_INC_SRC2_U32                             0x83
+#define     V_008DFC_SQ_DS_DEC_SRC2_U32                             0x84
+#define     V_008DFC_SQ_DS_MIN_SRC2_I32                             0x85
+#define     V_008DFC_SQ_DS_MAX_SRC2_I32                             0x86
+#define     V_008DFC_SQ_DS_MIN_SRC2_U32                             0x87
+#define     V_008DFC_SQ_DS_MAX_SRC2_U32                             0x88
+#define     V_008DFC_SQ_DS_AND_SRC2_B32                             0x89
+#define     V_008DFC_SQ_DS_OR_SRC2_B32                              0x8A
+#define     V_008DFC_SQ_DS_XOR_SRC2_B32                             0x8B
+#define     V_008DFC_SQ_DS_WRITE_SRC2_B32                           0x8D
+#define     V_008DFC_SQ_DS_MIN_SRC2_F32                             0x92
+#define     V_008DFC_SQ_DS_MAX_SRC2_F32                             0x93
+#define     V_008DFC_SQ_DS_ADD_SRC2_U64                             0xC0
+#define     V_008DFC_SQ_DS_SUB_SRC2_U64                             0xC1
+#define     V_008DFC_SQ_DS_RSUB_SRC2_U64                            0xC2
+#define     V_008DFC_SQ_DS_INC_SRC2_U64                             0xC3
+#define     V_008DFC_SQ_DS_DEC_SRC2_U64                             0xC4
+#define     V_008DFC_SQ_DS_MIN_SRC2_I64                             0xC5
+#define     V_008DFC_SQ_DS_MAX_SRC2_I64                             0xC6
+#define     V_008DFC_SQ_DS_MIN_SRC2_U64                             0xC7
+#define     V_008DFC_SQ_DS_MAX_SRC2_U64                             0xC8
+#define     V_008DFC_SQ_DS_AND_SRC2_B64                             0xC9
+#define     V_008DFC_SQ_DS_OR_SRC2_B64                              0xCA
+#define     V_008DFC_SQ_DS_XOR_SRC2_B64                             0xCB
+#define     V_008DFC_SQ_DS_WRITE_SRC2_B64                           0xCD
+#define     V_008DFC_SQ_DS_MIN_SRC2_F64                             0xD2
+#define     V_008DFC_SQ_DS_MAX_SRC2_F64                             0xD3
+/* CIK */
+#define     V_008DFC_SQ_DS_WRITE_B96                                0xDE
+#define     V_008DFC_SQ_DS_WRITE_B128                               0xDF
+#define     V_008DFC_SQ_DS_CONDXCHG32_RTN_B128                      0xFD
+#define     V_008DFC_SQ_DS_READ_B96                                 0xFE
+#define     V_008DFC_SQ_DS_READ_B128                                0xFF
+/*     */
+#define   S_008DFC_ENCODING(x)                                        (((x) & 0x3F) << 26)
+#define   G_008DFC_ENCODING(x)                                        (((x) >> 26) & 0x3F)
+#define   C_008DFC_ENCODING                                           0x03FFFFFF
+#define     V_008DFC_SQ_ENC_DS_FIELD                                0x36
+#define R_008DFC_SQ_SOPC                                                0x008DFC
+#define   S_008DFC_SSRC0(x)                                           (((x) & 0xFF) << 0)
+#define   G_008DFC_SSRC0(x)                                           (((x) >> 0) & 0xFF)
+#define   C_008DFC_SSRC0                                              0xFFFFFF00
+#define     V_008DFC_SQ_SGPR                                        0x00
+/* CIK */
+#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
+#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
+/*     */
+#define     V_008DFC_SQ_VCC_LO                                      0x6A
+#define     V_008DFC_SQ_VCC_HI                                      0x6B
+#define     V_008DFC_SQ_TBA_LO                                      0x6C
+#define     V_008DFC_SQ_TBA_HI                                      0x6D
+#define     V_008DFC_SQ_TMA_LO                                      0x6E
+#define     V_008DFC_SQ_TMA_HI                                      0x6F
+#define     V_008DFC_SQ_TTMP0                                       0x70
+#define     V_008DFC_SQ_TTMP1                                       0x71
+#define     V_008DFC_SQ_TTMP2                                       0x72
+#define     V_008DFC_SQ_TTMP3                                       0x73
+#define     V_008DFC_SQ_TTMP4                                       0x74
+#define     V_008DFC_SQ_TTMP5                                       0x75
+#define     V_008DFC_SQ_TTMP6                                       0x76
+#define     V_008DFC_SQ_TTMP7                                       0x77
+#define     V_008DFC_SQ_TTMP8                                       0x78
+#define     V_008DFC_SQ_TTMP9                                       0x79
+#define     V_008DFC_SQ_TTMP10                                      0x7A
+#define     V_008DFC_SQ_TTMP11                                      0x7B
+#define     V_008DFC_SQ_M0                                          0x7C
+#define     V_008DFC_SQ_EXEC_LO                                     0x7E
+#define     V_008DFC_SQ_EXEC_HI                                     0x7F
+#define     V_008DFC_SQ_SRC_0                                       0x80
+#define     V_008DFC_SQ_SRC_1_INT                                   0x81
+#define     V_008DFC_SQ_SRC_2_INT                                   0x82
+#define     V_008DFC_SQ_SRC_3_INT                                   0x83
+#define     V_008DFC_SQ_SRC_4_INT                                   0x84
+#define     V_008DFC_SQ_SRC_5_INT                                   0x85
+#define     V_008DFC_SQ_SRC_6_INT                                   0x86
+#define     V_008DFC_SQ_SRC_7_INT                                   0x87
+#define     V_008DFC_SQ_SRC_8_INT                                   0x88
+#define     V_008DFC_SQ_SRC_9_INT                                   0x89
+#define     V_008DFC_SQ_SRC_10_INT                                  0x8A
+#define     V_008DFC_SQ_SRC_11_INT                                  0x8B
+#define     V_008DFC_SQ_SRC_12_INT                                  0x8C
+#define     V_008DFC_SQ_SRC_13_INT                                  0x8D
+#define     V_008DFC_SQ_SRC_14_INT                                  0x8E
+#define     V_008DFC_SQ_SRC_15_INT                                  0x8F
+#define     V_008DFC_SQ_SRC_16_INT                                  0x90
+#define     V_008DFC_SQ_SRC_17_INT                                  0x91
+#define     V_008DFC_SQ_SRC_18_INT                                  0x92
+#define     V_008DFC_SQ_SRC_19_INT                                  0x93
+#define     V_008DFC_SQ_SRC_20_INT                                  0x94
+#define     V_008DFC_SQ_SRC_21_INT                                  0x95
+#define     V_008DFC_SQ_SRC_22_INT                                  0x96
+#define     V_008DFC_SQ_SRC_23_INT                                  0x97
+#define     V_008DFC_SQ_SRC_24_INT                                  0x98
+#define     V_008DFC_SQ_SRC_25_INT                                  0x99
+#define     V_008DFC_SQ_SRC_26_INT                                  0x9A
+#define     V_008DFC_SQ_SRC_27_INT                                  0x9B
+#define     V_008DFC_SQ_SRC_28_INT                                  0x9C
+#define     V_008DFC_SQ_SRC_29_INT                                  0x9D
+#define     V_008DFC_SQ_SRC_30_INT                                  0x9E
+#define     V_008DFC_SQ_SRC_31_INT                                  0x9F
+#define     V_008DFC_SQ_SRC_32_INT                                  0xA0
+#define     V_008DFC_SQ_SRC_33_INT                                  0xA1
+#define     V_008DFC_SQ_SRC_34_INT                                  0xA2
+#define     V_008DFC_SQ_SRC_35_INT                                  0xA3
+#define     V_008DFC_SQ_SRC_36_INT                                  0xA4
+#define     V_008DFC_SQ_SRC_37_INT                                  0xA5
+#define     V_008DFC_SQ_SRC_38_INT                                  0xA6
+#define     V_008DFC_SQ_SRC_39_INT                                  0xA7
+#define     V_008DFC_SQ_SRC_40_INT                                  0xA8
+#define     V_008DFC_SQ_SRC_41_INT                                  0xA9
+#define     V_008DFC_SQ_SRC_42_INT                                  0xAA
+#define     V_008DFC_SQ_SRC_43_INT                                  0xAB
+#define     V_008DFC_SQ_SRC_44_INT                                  0xAC
+#define     V_008DFC_SQ_SRC_45_INT                                  0xAD
+#define     V_008DFC_SQ_SRC_46_INT                                  0xAE
+#define     V_008DFC_SQ_SRC_47_INT                                  0xAF
+#define     V_008DFC_SQ_SRC_48_INT                                  0xB0
+#define     V_008DFC_SQ_SRC_49_INT                                  0xB1
+#define     V_008DFC_SQ_SRC_50_INT                                  0xB2
+#define     V_008DFC_SQ_SRC_51_INT                                  0xB3
+#define     V_008DFC_SQ_SRC_52_INT                                  0xB4
+#define     V_008DFC_SQ_SRC_53_INT                                  0xB5
+#define     V_008DFC_SQ_SRC_54_INT                                  0xB6
+#define     V_008DFC_SQ_SRC_55_INT                                  0xB7
+#define     V_008DFC_SQ_SRC_56_INT                                  0xB8
+#define     V_008DFC_SQ_SRC_57_INT                                  0xB9
+#define     V_008DFC_SQ_SRC_58_INT                                  0xBA
+#define     V_008DFC_SQ_SRC_59_INT                                  0xBB
+#define     V_008DFC_SQ_SRC_60_INT                                  0xBC
+#define     V_008DFC_SQ_SRC_61_INT                                  0xBD
+#define     V_008DFC_SQ_SRC_62_INT                                  0xBE
+#define     V_008DFC_SQ_SRC_63_INT                                  0xBF
+#define     V_008DFC_SQ_SRC_64_INT                                  0xC0
+#define     V_008DFC_SQ_SRC_M_1_INT                                 0xC1
+#define     V_008DFC_SQ_SRC_M_2_INT                                 0xC2
+#define     V_008DFC_SQ_SRC_M_3_INT                                 0xC3
+#define     V_008DFC_SQ_SRC_M_4_INT                                 0xC4
+#define     V_008DFC_SQ_SRC_M_5_INT                                 0xC5
+#define     V_008DFC_SQ_SRC_M_6_INT                                 0xC6
+#define     V_008DFC_SQ_SRC_M_7_INT                                 0xC7
+#define     V_008DFC_SQ_SRC_M_8_INT                                 0xC8
+#define     V_008DFC_SQ_SRC_M_9_INT                                 0xC9
+#define     V_008DFC_SQ_SRC_M_10_INT                                0xCA
+#define     V_008DFC_SQ_SRC_M_11_INT                                0xCB
+#define     V_008DFC_SQ_SRC_M_12_INT                                0xCC
+#define     V_008DFC_SQ_SRC_M_13_INT                                0xCD
+#define     V_008DFC_SQ_SRC_M_14_INT                                0xCE
+#define     V_008DFC_SQ_SRC_M_15_INT                                0xCF
+#define     V_008DFC_SQ_SRC_M_16_INT                                0xD0
+#define     V_008DFC_SQ_SRC_0_5                                     0xF0
+#define     V_008DFC_SQ_SRC_M_0_5                                   0xF1
+#define     V_008DFC_SQ_SRC_1                                       0xF2
+#define     V_008DFC_SQ_SRC_M_1                                     0xF3
+#define     V_008DFC_SQ_SRC_2                                       0xF4
+#define     V_008DFC_SQ_SRC_M_2                                     0xF5
+#define     V_008DFC_SQ_SRC_4                                       0xF6
+#define     V_008DFC_SQ_SRC_M_4                                     0xF7
+#define     V_008DFC_SQ_SRC_VCCZ                                    0xFB
+#define     V_008DFC_SQ_SRC_EXECZ                                   0xFC
+#define     V_008DFC_SQ_SRC_SCC                                     0xFD
+#define     V_008DFC_SQ_SRC_LDS_DIRECT                              0xFE
+#define   S_008DFC_SSRC1(x)                                           (((x) & 0xFF) << 8)
+#define   G_008DFC_SSRC1(x)                                           (((x) >> 8) & 0xFF)
+#define   C_008DFC_SSRC1                                              0xFFFF00FF
+#define     V_008DFC_SQ_SGPR                                        0x00
+/* CIK */
+#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
+#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
+/*     */
+#define     V_008DFC_SQ_VCC_LO                                      0x6A
+#define     V_008DFC_SQ_VCC_HI                                      0x6B
+#define     V_008DFC_SQ_TBA_LO                                      0x6C
+#define     V_008DFC_SQ_TBA_HI                                      0x6D
+#define     V_008DFC_SQ_TMA_LO                                      0x6E
+#define     V_008DFC_SQ_TMA_HI                                      0x6F
+#define     V_008DFC_SQ_TTMP0                                       0x70
+#define     V_008DFC_SQ_TTMP1                                       0x71
+#define     V_008DFC_SQ_TTMP2                                       0x72
+#define     V_008DFC_SQ_TTMP3                                       0x73
+#define     V_008DFC_SQ_TTMP4                                       0x74
+#define     V_008DFC_SQ_TTMP5                                       0x75
+#define     V_008DFC_SQ_TTMP6                                       0x76
+#define     V_008DFC_SQ_TTMP7                                       0x77
+#define     V_008DFC_SQ_TTMP8                                       0x78
+#define     V_008DFC_SQ_TTMP9                                       0x79
+#define     V_008DFC_SQ_TTMP10                                      0x7A
+#define     V_008DFC_SQ_TTMP11                                      0x7B
+#define     V_008DFC_SQ_M0                                          0x7C
+#define     V_008DFC_SQ_EXEC_LO                                     0x7E
+#define     V_008DFC_SQ_EXEC_HI                                     0x7F
+#define     V_008DFC_SQ_SRC_0                                       0x80
+#define     V_008DFC_SQ_SRC_1_INT                                   0x81
+#define     V_008DFC_SQ_SRC_2_INT                                   0x82
+#define     V_008DFC_SQ_SRC_3_INT                                   0x83
+#define     V_008DFC_SQ_SRC_4_INT                                   0x84
+#define     V_008DFC_SQ_SRC_5_INT                                   0x85
+#define     V_008DFC_SQ_SRC_6_INT                                   0x86
+#define     V_008DFC_SQ_SRC_7_INT                                   0x87
+#define     V_008DFC_SQ_SRC_8_INT                                   0x88
+#define     V_008DFC_SQ_SRC_9_INT                                   0x89
+#define     V_008DFC_SQ_SRC_10_INT                                  0x8A
+#define     V_008DFC_SQ_SRC_11_INT                                  0x8B
+#define     V_008DFC_SQ_SRC_12_INT                                  0x8C
+#define     V_008DFC_SQ_SRC_13_INT                                  0x8D
+#define     V_008DFC_SQ_SRC_14_INT                                  0x8E
+#define     V_008DFC_SQ_SRC_15_INT                                  0x8F
+#define     V_008DFC_SQ_SRC_16_INT                                  0x90
+#define     V_008DFC_SQ_SRC_17_INT                                  0x91
+#define     V_008DFC_SQ_SRC_18_INT                                  0x92
+#define     V_008DFC_SQ_SRC_19_INT                                  0x93
+#define     V_008DFC_SQ_SRC_20_INT                                  0x94
+#define     V_008DFC_SQ_SRC_21_INT                                  0x95
+#define     V_008DFC_SQ_SRC_22_INT                                  0x96
+#define     V_008DFC_SQ_SRC_23_INT                                  0x97
+#define     V_008DFC_SQ_SRC_24_INT                                  0x98
+#define     V_008DFC_SQ_SRC_25_INT                                  0x99
+#define     V_008DFC_SQ_SRC_26_INT                                  0x9A
+#define     V_008DFC_SQ_SRC_27_INT                                  0x9B
+#define     V_008DFC_SQ_SRC_28_INT                                  0x9C
+#define     V_008DFC_SQ_SRC_29_INT                                  0x9D
+#define     V_008DFC_SQ_SRC_30_INT                                  0x9E
+#define     V_008DFC_SQ_SRC_31_INT                                  0x9F
+#define     V_008DFC_SQ_SRC_32_INT                                  0xA0
+#define     V_008DFC_SQ_SRC_33_INT                                  0xA1
+#define     V_008DFC_SQ_SRC_34_INT                                  0xA2
+#define     V_008DFC_SQ_SRC_35_INT                                  0xA3
+#define     V_008DFC_SQ_SRC_36_INT                                  0xA4
+#define     V_008DFC_SQ_SRC_37_INT                                  0xA5
+#define     V_008DFC_SQ_SRC_38_INT                                  0xA6
+#define     V_008DFC_SQ_SRC_39_INT                                  0xA7
+#define     V_008DFC_SQ_SRC_40_INT                                  0xA8
+#define     V_008DFC_SQ_SRC_41_INT                                  0xA9
+#define     V_008DFC_SQ_SRC_42_INT                                  0xAA
+#define     V_008DFC_SQ_SRC_43_INT                                  0xAB
+#define     V_008DFC_SQ_SRC_44_INT                                  0xAC
+#define     V_008DFC_SQ_SRC_45_INT                                  0xAD
+#define     V_008DFC_SQ_SRC_46_INT                                  0xAE
+#define     V_008DFC_SQ_SRC_47_INT                                  0xAF
+#define     V_008DFC_SQ_SRC_48_INT                                  0xB0
+#define     V_008DFC_SQ_SRC_49_INT                                  0xB1
+#define     V_008DFC_SQ_SRC_50_INT                                  0xB2
+#define     V_008DFC_SQ_SRC_51_INT                                  0xB3
+#define     V_008DFC_SQ_SRC_52_INT                                  0xB4
+#define     V_008DFC_SQ_SRC_53_INT                                  0xB5
+#define     V_008DFC_SQ_SRC_54_INT                                  0xB6
+#define     V_008DFC_SQ_SRC_55_INT                                  0xB7
+#define     V_008DFC_SQ_SRC_56_INT                                  0xB8
+#define     V_008DFC_SQ_SRC_57_INT                                  0xB9
+#define     V_008DFC_SQ_SRC_58_INT                                  0xBA
+#define     V_008DFC_SQ_SRC_59_INT                                  0xBB
+#define     V_008DFC_SQ_SRC_60_INT                                  0xBC
+#define     V_008DFC_SQ_SRC_61_INT                                  0xBD
+#define     V_008DFC_SQ_SRC_62_INT                                  0xBE
+#define     V_008DFC_SQ_SRC_63_INT                                  0xBF
+#define     V_008DFC_SQ_SRC_64_INT                                  0xC0
+#define     V_008DFC_SQ_SRC_M_1_INT                                 0xC1
+#define     V_008DFC_SQ_SRC_M_2_INT                                 0xC2
+#define     V_008DFC_SQ_SRC_M_3_INT                                 0xC3
+#define     V_008DFC_SQ_SRC_M_4_INT                                 0xC4
+#define     V_008DFC_SQ_SRC_M_5_INT                                 0xC5
+#define     V_008DFC_SQ_SRC_M_6_INT                                 0xC6
+#define     V_008DFC_SQ_SRC_M_7_INT                                 0xC7
+#define     V_008DFC_SQ_SRC_M_8_INT                                 0xC8
+#define     V_008DFC_SQ_SRC_M_9_INT                                 0xC9
+#define     V_008DFC_SQ_SRC_M_10_INT                                0xCA
+#define     V_008DFC_SQ_SRC_M_11_INT                                0xCB
+#define     V_008DFC_SQ_SRC_M_12_INT                                0xCC
+#define     V_008DFC_SQ_SRC_M_13_INT                                0xCD
+#define     V_008DFC_SQ_SRC_M_14_INT                                0xCE
+#define     V_008DFC_SQ_SRC_M_15_INT                                0xCF
+#define     V_008DFC_SQ_SRC_M_16_INT                                0xD0
+#define     V_008DFC_SQ_SRC_0_5                                     0xF0
+#define     V_008DFC_SQ_SRC_M_0_5                                   0xF1
+#define     V_008DFC_SQ_SRC_1                                       0xF2
+#define     V_008DFC_SQ_SRC_M_1                                     0xF3
+#define     V_008DFC_SQ_SRC_2                                       0xF4
+#define     V_008DFC_SQ_SRC_M_2                                     0xF5
+#define     V_008DFC_SQ_SRC_4                                       0xF6
+#define     V_008DFC_SQ_SRC_M_4                                     0xF7
+#define     V_008DFC_SQ_SRC_VCCZ                                    0xFB
+#define     V_008DFC_SQ_SRC_EXECZ                                   0xFC
+#define     V_008DFC_SQ_SRC_SCC                                     0xFD
+#define     V_008DFC_SQ_SRC_LDS_DIRECT                              0xFE
+#define   S_008DFC_OP(x)                                              (((x) & 0x7F) << 16)
+#define   G_008DFC_OP(x)                                              (((x) >> 16) & 0x7F)
+#define   C_008DFC_OP                                                 0xFF80FFFF
+#define     V_008DFC_SQ_S_CMP_EQ_I32                                0x00
+#define     V_008DFC_SQ_S_CMP_LG_I32                                0x01
+#define     V_008DFC_SQ_S_CMP_GT_I32                                0x02
+#define     V_008DFC_SQ_S_CMP_GE_I32                                0x03
+#define     V_008DFC_SQ_S_CMP_LT_I32                                0x04
+#define     V_008DFC_SQ_S_CMP_LE_I32                                0x05
+#define     V_008DFC_SQ_S_CMP_EQ_U32                                0x06
+#define     V_008DFC_SQ_S_CMP_LG_U32                                0x07
+#define     V_008DFC_SQ_S_CMP_GT_U32                                0x08
+#define     V_008DFC_SQ_S_CMP_GE_U32                                0x09
+#define     V_008DFC_SQ_S_CMP_LT_U32                                0x0A
+#define     V_008DFC_SQ_S_CMP_LE_U32                                0x0B
+#define     V_008DFC_SQ_S_BITCMP0_B32                               0x0C
+#define     V_008DFC_SQ_S_BITCMP1_B32                               0x0D
+#define     V_008DFC_SQ_S_BITCMP0_B64                               0x0E
+#define     V_008DFC_SQ_S_BITCMP1_B64                               0x0F
+#define     V_008DFC_SQ_S_SETVSKIP                                  0x10
+#define   S_008DFC_ENCODING(x)                                        (((x) & 0x1FF) << 23)
+#define   G_008DFC_ENCODING(x)                                        (((x) >> 23) & 0x1FF)
+#define   C_008DFC_ENCODING                                           0x007FFFFF
+#define     V_008DFC_SQ_ENC_SOPC_FIELD                              0x17E
+#endif
+#define R_008DFC_SQ_EXP_0                                               0x008DFC
+#define   S_008DFC_EN(x)                                              (((x) & 0x0F) << 0)
+#define   G_008DFC_EN(x)                                              (((x) >> 0) & 0x0F)
+#define   C_008DFC_EN                                                 0xFFFFFFF0
+#define   S_008DFC_TGT(x)                                             (((x) & 0x3F) << 4)
+#define   G_008DFC_TGT(x)                                             (((x) >> 4) & 0x3F)
+#define   C_008DFC_TGT                                                0xFFFFFC0F
+#define     V_008DFC_SQ_EXP_MRT                                     0x00
+#define     V_008DFC_SQ_EXP_MRTZ                                    0x08
+#define     V_008DFC_SQ_EXP_NULL                                    0x09
+#define     V_008DFC_SQ_EXP_POS                                     0x0C
+#define     V_008DFC_SQ_EXP_PARAM                                   0x20
+#define   S_008DFC_COMPR(x)                                           (((x) & 0x1) << 10)
+#define   G_008DFC_COMPR(x)                                           (((x) >> 10) & 0x1)
+#define   C_008DFC_COMPR                                              0xFFFFFBFF
+#define   S_008DFC_DONE(x)                                            (((x) & 0x1) << 11)
+#define   G_008DFC_DONE(x)                                            (((x) >> 11) & 0x1)
+#define   C_008DFC_DONE                                               0xFFFFF7FF
+#define   S_008DFC_VM(x)                                              (((x) & 0x1) << 12)
+#define   G_008DFC_VM(x)                                              (((x) >> 12) & 0x1)
+#define   C_008DFC_VM                                                 0xFFFFEFFF
+#define   S_008DFC_ENCODING(x)                                        (((x) & 0x3F) << 26)
+#define   G_008DFC_ENCODING(x)                                        (((x) >> 26) & 0x3F)
+#define   C_008DFC_ENCODING                                           0x03FFFFFF
+#define     V_008DFC_SQ_ENC_EXP_FIELD                               0x3E
+#if 0
+#define R_008DFC_SQ_MIMG_0                                              0x008DFC
+#define   S_008DFC_DMASK(x)                                           (((x) & 0x0F) << 8)
+#define   G_008DFC_DMASK(x)                                           (((x) >> 8) & 0x0F)
+#define   C_008DFC_DMASK                                              0xFFFFF0FF
+#define   S_008DFC_UNORM(x)                                           (((x) & 0x1) << 12)
+#define   G_008DFC_UNORM(x)                                           (((x) >> 12) & 0x1)
+#define   C_008DFC_UNORM                                              0xFFFFEFFF
+#define   S_008DFC_GLC(x)                                             (((x) & 0x1) << 13)
+#define   G_008DFC_GLC(x)                                             (((x) >> 13) & 0x1)
+#define   C_008DFC_GLC                                                0xFFFFDFFF
+#define   S_008DFC_DA(x)                                              (((x) & 0x1) << 14)
+#define   G_008DFC_DA(x)                                              (((x) >> 14) & 0x1)
+#define   C_008DFC_DA                                                 0xFFFFBFFF
+#define   S_008DFC_R128(x)                                            (((x) & 0x1) << 15)
+#define   G_008DFC_R128(x)                                            (((x) >> 15) & 0x1)
+#define   C_008DFC_R128                                               0xFFFF7FFF
+#define   S_008DFC_TFE(x)                                             (((x) & 0x1) << 16)
+#define   G_008DFC_TFE(x)                                             (((x) >> 16) & 0x1)
+#define   C_008DFC_TFE                                                0xFFFEFFFF
+#define   S_008DFC_LWE(x)                                             (((x) & 0x1) << 17)
+#define   G_008DFC_LWE(x)                                             (((x) >> 17) & 0x1)
+#define   C_008DFC_LWE                                                0xFFFDFFFF
+#define   S_008DFC_OP(x)                                              (((x) & 0x7F) << 18)
+#define   G_008DFC_OP(x)                                              (((x) >> 18) & 0x7F)
+#define   C_008DFC_OP                                                 0xFE03FFFF
+#define     V_008DFC_SQ_IMAGE_LOAD                                  0x00
+#define     V_008DFC_SQ_IMAGE_LOAD_MIP                              0x01
+#define     V_008DFC_SQ_IMAGE_LOAD_PCK                              0x02
+#define     V_008DFC_SQ_IMAGE_LOAD_PCK_SGN                          0x03
+#define     V_008DFC_SQ_IMAGE_LOAD_MIP_PCK                          0x04
+#define     V_008DFC_SQ_IMAGE_LOAD_MIP_PCK_SGN                      0x05
+#define     V_008DFC_SQ_IMAGE_STORE                                 0x08
+#define     V_008DFC_SQ_IMAGE_STORE_MIP                             0x09
+#define     V_008DFC_SQ_IMAGE_STORE_PCK                             0x0A
+#define     V_008DFC_SQ_IMAGE_STORE_MIP_PCK                         0x0B
+#define     V_008DFC_SQ_IMAGE_GET_RESINFO                           0x0E
+#define     V_008DFC_SQ_IMAGE_ATOMIC_SWAP                           0x0F
+#define     V_008DFC_SQ_IMAGE_ATOMIC_CMPSWAP                        0x10
+#define     V_008DFC_SQ_IMAGE_ATOMIC_ADD                            0x11
+#define     V_008DFC_SQ_IMAGE_ATOMIC_SUB                            0x12
+#define     V_008DFC_SQ_IMAGE_ATOMIC_RSUB                           0x13 /* not on CIK */
+#define     V_008DFC_SQ_IMAGE_ATOMIC_SMIN                           0x14
+#define     V_008DFC_SQ_IMAGE_ATOMIC_UMIN                           0x15
+#define     V_008DFC_SQ_IMAGE_ATOMIC_SMAX                           0x16
+#define     V_008DFC_SQ_IMAGE_ATOMIC_UMAX                           0x17
+#define     V_008DFC_SQ_IMAGE_ATOMIC_AND                            0x18
+#define     V_008DFC_SQ_IMAGE_ATOMIC_OR                             0x19
+#define     V_008DFC_SQ_IMAGE_ATOMIC_XOR                            0x1A
+#define     V_008DFC_SQ_IMAGE_ATOMIC_INC                            0x1B
+#define     V_008DFC_SQ_IMAGE_ATOMIC_DEC                            0x1C
+#define     V_008DFC_SQ_IMAGE_ATOMIC_FCMPSWAP                       0x1D
+#define     V_008DFC_SQ_IMAGE_ATOMIC_FMIN                           0x1E
+#define     V_008DFC_SQ_IMAGE_ATOMIC_FMAX                           0x1F
+#define     V_008DFC_SQ_IMAGE_SAMPLE                                0x20
+#define     V_008DFC_SQ_IMAGE_SAMPLE_CL                             0x21
+#define     V_008DFC_SQ_IMAGE_SAMPLE_D                              0x22
+#define     V_008DFC_SQ_IMAGE_SAMPLE_D_CL                           0x23
+#define     V_008DFC_SQ_IMAGE_SAMPLE_L                              0x24
+#define     V_008DFC_SQ_IMAGE_SAMPLE_B                              0x25
+#define     V_008DFC_SQ_IMAGE_SAMPLE_B_CL                           0x26
+#define     V_008DFC_SQ_IMAGE_SAMPLE_LZ                             0x27
+#define     V_008DFC_SQ_IMAGE_SAMPLE_C                              0x28
+#define     V_008DFC_SQ_IMAGE_SAMPLE_C_CL                           0x29
+#define     V_008DFC_SQ_IMAGE_SAMPLE_C_D                            0x2A
+#define     V_008DFC_SQ_IMAGE_SAMPLE_C_D_CL                         0x2B
+#define     V_008DFC_SQ_IMAGE_SAMPLE_C_L                            0x2C
+#define     V_008DFC_SQ_IMAGE_SAMPLE_C_B                            0x2D
+#define     V_008DFC_SQ_IMAGE_SAMPLE_C_B_CL                         0x2E
+#define     V_008DFC_SQ_IMAGE_SAMPLE_C_LZ                           0x2F
+#define     V_008DFC_SQ_IMAGE_SAMPLE_O                              0x30
+#define     V_008DFC_SQ_IMAGE_SAMPLE_CL_O                           0x31
+#define     V_008DFC_SQ_IMAGE_SAMPLE_D_O                            0x32
+#define     V_008DFC_SQ_IMAGE_SAMPLE_D_CL_O                         0x33
+#define     V_008DFC_SQ_IMAGE_SAMPLE_L_O                            0x34
+#define     V_008DFC_SQ_IMAGE_SAMPLE_B_O                            0x35
+#define     V_008DFC_SQ_IMAGE_SAMPLE_B_CL_O                         0x36
+#define     V_008DFC_SQ_IMAGE_SAMPLE_LZ_O                           0x37
+#define     V_008DFC_SQ_IMAGE_SAMPLE_C_O                            0x38
+#define     V_008DFC_SQ_IMAGE_SAMPLE_C_CL_O                         0x39
+#define     V_008DFC_SQ_IMAGE_SAMPLE_C_D_O                          0x3A
+#define     V_008DFC_SQ_IMAGE_SAMPLE_C_D_CL_O                       0x3B
+#define     V_008DFC_SQ_IMAGE_SAMPLE_C_L_O                          0x3C
+#define     V_008DFC_SQ_IMAGE_SAMPLE_C_B_O                          0x3D
+#define     V_008DFC_SQ_IMAGE_SAMPLE_C_B_CL_O                       0x3E
+#define     V_008DFC_SQ_IMAGE_SAMPLE_C_LZ_O                         0x3F
+#define     V_008DFC_SQ_IMAGE_GATHER4                               0x40
+#define     V_008DFC_SQ_IMAGE_GATHER4_CL                            0x41
+#define     V_008DFC_SQ_IMAGE_GATHER4_L                             0x44
+#define     V_008DFC_SQ_IMAGE_GATHER4_B                             0x45
+#define     V_008DFC_SQ_IMAGE_GATHER4_B_CL                          0x46
+#define     V_008DFC_SQ_IMAGE_GATHER4_LZ                            0x47
+#define     V_008DFC_SQ_IMAGE_GATHER4_C                             0x48
+#define     V_008DFC_SQ_IMAGE_GATHER4_C_CL                          0x49
+#define     V_008DFC_SQ_IMAGE_GATHER4_C_L                           0x4C
+#define     V_008DFC_SQ_IMAGE_GATHER4_C_B                           0x4D
+#define     V_008DFC_SQ_IMAGE_GATHER4_C_B_CL                        0x4E
+#define     V_008DFC_SQ_IMAGE_GATHER4_C_LZ                          0x4F
+#define     V_008DFC_SQ_IMAGE_GATHER4_O                             0x50
+#define     V_008DFC_SQ_IMAGE_GATHER4_CL_O                          0x51
+#define     V_008DFC_SQ_IMAGE_GATHER4_L_O                           0x54
+#define     V_008DFC_SQ_IMAGE_GATHER4_B_O                           0x55
+#define     V_008DFC_SQ_IMAGE_GATHER4_B_CL_O                        0x56
+#define     V_008DFC_SQ_IMAGE_GATHER4_LZ_O                          0x57
+#define     V_008DFC_SQ_IMAGE_GATHER4_C_O                           0x58
+#define     V_008DFC_SQ_IMAGE_GATHER4_C_CL_O                        0x59
+#define     V_008DFC_SQ_IMAGE_GATHER4_C_L_O                         0x5C
+#define     V_008DFC_SQ_IMAGE_GATHER4_C_B_O                         0x5D
+#define     V_008DFC_SQ_IMAGE_GATHER4_C_B_CL_O                      0x5E
+#define     V_008DFC_SQ_IMAGE_GATHER4_C_LZ_O                        0x5F
+#define     V_008DFC_SQ_IMAGE_GET_LOD                               0x60
+#define     V_008DFC_SQ_IMAGE_SAMPLE_CD                             0x68
+#define     V_008DFC_SQ_IMAGE_SAMPLE_CD_CL                          0x69
+#define     V_008DFC_SQ_IMAGE_SAMPLE_C_CD                           0x6A
+#define     V_008DFC_SQ_IMAGE_SAMPLE_C_CD_CL                        0x6B
+#define     V_008DFC_SQ_IMAGE_SAMPLE_CD_O                           0x6C
+#define     V_008DFC_SQ_IMAGE_SAMPLE_CD_CL_O                        0x6D
+#define     V_008DFC_SQ_IMAGE_SAMPLE_C_CD_O                         0x6E
+#define     V_008DFC_SQ_IMAGE_SAMPLE_C_CD_CL_O                      0x6F
+#define   S_008DFC_SLC(x)                                             (((x) & 0x1) << 25)
+#define   G_008DFC_SLC(x)                                             (((x) >> 25) & 0x1)
+#define   C_008DFC_SLC                                                0xFDFFFFFF
+#define   S_008DFC_ENCODING(x)                                        (((x) & 0x3F) << 26)
+#define   G_008DFC_ENCODING(x)                                        (((x) >> 26) & 0x3F)
+#define   C_008DFC_ENCODING                                           0x03FFFFFF
+#define     V_008DFC_SQ_ENC_MIMG_FIELD                              0x3C
+#define R_008DFC_SQ_SOPP                                                0x008DFC
+#define   S_008DFC_SIMM16(x)                                          (((x) & 0xFFFF) << 0)
+#define   G_008DFC_SIMM16(x)                                          (((x) >> 0) & 0xFFFF)
+#define   C_008DFC_SIMM16                                             0xFFFF0000
+#define   S_008DFC_OP(x)                                              (((x) & 0x7F) << 16)
+#define   G_008DFC_OP(x)                                              (((x) >> 16) & 0x7F)
+#define   C_008DFC_OP                                                 0xFF80FFFF
+#define     V_008DFC_SQ_S_NOP                                       0x00
+#define     V_008DFC_SQ_S_ENDPGM                                    0x01
+#define     V_008DFC_SQ_S_BRANCH                                    0x02
+#define     V_008DFC_SQ_S_CBRANCH_SCC0                              0x04
+#define     V_008DFC_SQ_S_CBRANCH_SCC1                              0x05
+#define     V_008DFC_SQ_S_CBRANCH_VCCZ                              0x06
+#define     V_008DFC_SQ_S_CBRANCH_VCCNZ                             0x07
+#define     V_008DFC_SQ_S_CBRANCH_EXECZ                             0x08
+#define     V_008DFC_SQ_S_CBRANCH_EXECNZ                            0x09
+#define     V_008DFC_SQ_S_BARRIER                                   0x0A
+/* CIK */
+#define     V_008DFC_SQ_S_SETKILL                                   0x0B
+/*     */
+#define     V_008DFC_SQ_S_WAITCNT                                   0x0C
+#define     V_008DFC_SQ_S_SETHALT                                   0x0D
+#define     V_008DFC_SQ_S_SLEEP                                     0x0E
+#define     V_008DFC_SQ_S_SETPRIO                                   0x0F
+#define     V_008DFC_SQ_S_SENDMSG                                   0x10
+#define     V_008DFC_SQ_S_SENDMSGHALT                               0x11
+#define     V_008DFC_SQ_S_TRAP                                      0x12
+#define     V_008DFC_SQ_S_ICACHE_INV                                0x13
+#define     V_008DFC_SQ_S_INCPERFLEVEL                              0x14
+#define     V_008DFC_SQ_S_DECPERFLEVEL                              0x15
+#define     V_008DFC_SQ_S_TTRACEDATA                                0x16
+/* CIK */
+#define     V_008DFC_SQ_S_CBRANCH_CDBGSYS                           0x17
+#define     V_008DFC_SQ_S_CBRANCH_CDBGUSER                          0x18
+#define     V_008DFC_SQ_S_CBRANCH_CDBGSYS_OR_USER                   0x19
+#define     V_008DFC_SQ_S_CBRANCH_CDBGSYS_AND_USER                  0x1A
+/*     */
+#define   S_008DFC_ENCODING(x)                                        (((x) & 0x1FF) << 23)
+#define   G_008DFC_ENCODING(x)                                        (((x) >> 23) & 0x1FF)
+#define   C_008DFC_ENCODING                                           0x007FFFFF
+#define     V_008DFC_SQ_ENC_SOPP_FIELD                              0x17F
+#define R_008DFC_SQ_VINTRP                                              0x008DFC
+#define   S_008DFC_VSRC(x)                                            (((x) & 0xFF) << 0)
+#define   G_008DFC_VSRC(x)                                            (((x) >> 0) & 0xFF)
+#define   C_008DFC_VSRC                                               0xFFFFFF00
+#define     V_008DFC_SQ_VGPR                                        0x00
+#define   S_008DFC_ATTRCHAN(x)                                        (((x) & 0x03) << 8)
+#define   G_008DFC_ATTRCHAN(x)                                        (((x) >> 8) & 0x03)
+#define   C_008DFC_ATTRCHAN                                           0xFFFFFCFF
+#define     V_008DFC_SQ_CHAN_X                                      0x00
+#define     V_008DFC_SQ_CHAN_Y                                      0x01
+#define     V_008DFC_SQ_CHAN_Z                                      0x02
+#define     V_008DFC_SQ_CHAN_W                                      0x03
+#define   S_008DFC_ATTR(x)                                            (((x) & 0x3F) << 10)
+#define   G_008DFC_ATTR(x)                                            (((x) >> 10) & 0x3F)
+#define   C_008DFC_ATTR                                               0xFFFF03FF
+#define     V_008DFC_SQ_ATTR                                        0x00
+#define   S_008DFC_OP(x)                                              (((x) & 0x03) << 16)
+#define   G_008DFC_OP(x)                                              (((x) >> 16) & 0x03)
+#define   C_008DFC_OP                                                 0xFFFCFFFF
+#define     V_008DFC_SQ_V_INTERP_P1_F32                             0x00
+#define     V_008DFC_SQ_V_INTERP_P2_F32                             0x01
+#define     V_008DFC_SQ_V_INTERP_MOV_F32                            0x02
+#define   S_008DFC_VDST(x)                                            (((x) & 0xFF) << 18)
+#define   G_008DFC_VDST(x)                                            (((x) >> 18) & 0xFF)
+#define   C_008DFC_VDST                                               0xFC03FFFF
+#define     V_008DFC_SQ_VGPR                                        0x00
+#define   S_008DFC_ENCODING(x)                                        (((x) & 0x3F) << 26)
+#define   G_008DFC_ENCODING(x)                                        (((x) >> 26) & 0x3F)
+#define   C_008DFC_ENCODING                                           0x03FFFFFF
+#define     V_008DFC_SQ_ENC_VINTRP_FIELD                            0x32
+#define R_008DFC_SQ_MTBUF_0                                             0x008DFC
+#define   S_008DFC_OFFSET(x)                                          (((x) & 0xFFF) << 0)
+#define   G_008DFC_OFFSET(x)                                          (((x) >> 0) & 0xFFF)
+#define   C_008DFC_OFFSET                                             0xFFFFF000
+#define   S_008DFC_OFFEN(x)                                           (((x) & 0x1) << 12)
+#define   G_008DFC_OFFEN(x)                                           (((x) >> 12) & 0x1)
+#define   C_008DFC_OFFEN                                              0xFFFFEFFF
+#define   S_008DFC_IDXEN(x)                                           (((x) & 0x1) << 13)
+#define   G_008DFC_IDXEN(x)                                           (((x) >> 13) & 0x1)
+#define   C_008DFC_IDXEN                                              0xFFFFDFFF
+#define   S_008DFC_GLC(x)                                             (((x) & 0x1) << 14)
+#define   G_008DFC_GLC(x)                                             (((x) >> 14) & 0x1)
+#define   C_008DFC_GLC                                                0xFFFFBFFF
+#define   S_008DFC_ADDR64(x)                                          (((x) & 0x1) << 15)
+#define   G_008DFC_ADDR64(x)                                          (((x) >> 15) & 0x1)
+#define   C_008DFC_ADDR64                                             0xFFFF7FFF
+#define   S_008DFC_OP(x)                                              (((x) & 0x07) << 16)
+#define   G_008DFC_OP(x)                                              (((x) >> 16) & 0x07)
+#define   C_008DFC_OP                                                 0xFFF8FFFF
+#define     V_008DFC_SQ_TBUFFER_LOAD_FORMAT_X                       0x00
+#define     V_008DFC_SQ_TBUFFER_LOAD_FORMAT_XY                      0x01
+#define     V_008DFC_SQ_TBUFFER_LOAD_FORMAT_XYZ                     0x02
+#define     V_008DFC_SQ_TBUFFER_LOAD_FORMAT_XYZW                    0x03
+#define     V_008DFC_SQ_TBUFFER_STORE_FORMAT_X                      0x04
+#define     V_008DFC_SQ_TBUFFER_STORE_FORMAT_XY                     0x05
+#define     V_008DFC_SQ_TBUFFER_STORE_FORMAT_XYZ                    0x06
+#define     V_008DFC_SQ_TBUFFER_STORE_FORMAT_XYZW                   0x07
+#define   S_008DFC_DFMT(x)                                            (((x) & 0x0F) << 19)
+#define   G_008DFC_DFMT(x)                                            (((x) >> 19) & 0x0F)
+#define   C_008DFC_DFMT                                               0xFF87FFFF
+#define   S_008DFC_NFMT(x)                                            (((x) & 0x07) << 23)
+#define   G_008DFC_NFMT(x)                                            (((x) >> 23) & 0x07)
+#define   C_008DFC_NFMT                                               0xFC7FFFFF
+#define   S_008DFC_ENCODING(x)                                        (((x) & 0x3F) << 26)
+#define   G_008DFC_ENCODING(x)                                        (((x) >> 26) & 0x3F)
+#define   C_008DFC_ENCODING                                           0x03FFFFFF
+#define     V_008DFC_SQ_ENC_MTBUF_FIELD                             0x3A
+#define R_008DFC_SQ_SMRD                                                0x008DFC
+#define   S_008DFC_OFFSET(x)                                          (((x) & 0xFF) << 0)
+#define   G_008DFC_OFFSET(x)                                          (((x) >> 0) & 0xFF)
+#define   C_008DFC_OFFSET                                             0xFFFFFF00
+#define     V_008DFC_SQ_SGPR                                        0x00
+/* CIK */
+#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
+#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
+/*     */
+#define     V_008DFC_SQ_VCC_LO                                      0x6A
+#define     V_008DFC_SQ_VCC_HI                                      0x6B
+#define     V_008DFC_SQ_TBA_LO                                      0x6C
+#define     V_008DFC_SQ_TBA_HI                                      0x6D
+#define     V_008DFC_SQ_TMA_LO                                      0x6E
+#define     V_008DFC_SQ_TMA_HI                                      0x6F
+#define     V_008DFC_SQ_TTMP0                                       0x70
+#define     V_008DFC_SQ_TTMP1                                       0x71
+#define     V_008DFC_SQ_TTMP2                                       0x72
+#define     V_008DFC_SQ_TTMP3                                       0x73
+#define     V_008DFC_SQ_TTMP4                                       0x74
+#define     V_008DFC_SQ_TTMP5                                       0x75
+#define     V_008DFC_SQ_TTMP6                                       0x76
+#define     V_008DFC_SQ_TTMP7                                       0x77
+#define     V_008DFC_SQ_TTMP8                                       0x78
+#define     V_008DFC_SQ_TTMP9                                       0x79
+#define     V_008DFC_SQ_TTMP10                                      0x7A
+#define     V_008DFC_SQ_TTMP11                                      0x7B
+/* CIK */
+#define     V_008DFC_SQ_SRC_LITERAL                                 0xFF
+/*     */
+#define   S_008DFC_IMM(x)                                             (((x) & 0x1) << 8)
+#define   G_008DFC_IMM(x)                                             (((x) >> 8) & 0x1)
+#define   C_008DFC_IMM                                                0xFFFFFEFF
+#define   S_008DFC_SBASE(x)                                           (((x) & 0x3F) << 9)
+#define   G_008DFC_SBASE(x)                                           (((x) >> 9) & 0x3F)
+#define   C_008DFC_SBASE                                              0xFFFF81FF
+#define   S_008DFC_SDST(x)                                            (((x) & 0x7F) << 15)
+#define   G_008DFC_SDST(x)                                            (((x) >> 15) & 0x7F)
+#define   C_008DFC_SDST                                               0xFFC07FFF
+#define     V_008DFC_SQ_SGPR                                        0x00
+/* CIK */
+#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
+#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
+/*     */
+#define     V_008DFC_SQ_VCC_LO                                      0x6A
+#define     V_008DFC_SQ_VCC_HI                                      0x6B
+#define     V_008DFC_SQ_TBA_LO                                      0x6C
+#define     V_008DFC_SQ_TBA_HI                                      0x6D
+#define     V_008DFC_SQ_TMA_LO                                      0x6E
+#define     V_008DFC_SQ_TMA_HI                                      0x6F
+#define     V_008DFC_SQ_TTMP0                                       0x70
+#define     V_008DFC_SQ_TTMP1                                       0x71
+#define     V_008DFC_SQ_TTMP2                                       0x72
+#define     V_008DFC_SQ_TTMP3                                       0x73
+#define     V_008DFC_SQ_TTMP4                                       0x74
+#define     V_008DFC_SQ_TTMP5                                       0x75
+#define     V_008DFC_SQ_TTMP6                                       0x76
+#define     V_008DFC_SQ_TTMP7                                       0x77
+#define     V_008DFC_SQ_TTMP8                                       0x78
+#define     V_008DFC_SQ_TTMP9                                       0x79
+#define     V_008DFC_SQ_TTMP10                                      0x7A
+#define     V_008DFC_SQ_TTMP11                                      0x7B
+#define     V_008DFC_SQ_M0                                          0x7C
+#define     V_008DFC_SQ_EXEC_LO                                     0x7E
+#define     V_008DFC_SQ_EXEC_HI                                     0x7F
+#define   S_008DFC_OP(x)                                              (((x) & 0x1F) << 22)
+#define   G_008DFC_OP(x)                                              (((x) >> 22) & 0x1F)
+#define   C_008DFC_OP                                                 0xF83FFFFF
+#define     V_008DFC_SQ_S_LOAD_DWORD                                0x00
+#define     V_008DFC_SQ_S_LOAD_DWORDX2                              0x01
+#define     V_008DFC_SQ_S_LOAD_DWORDX4                              0x02
+#define     V_008DFC_SQ_S_LOAD_DWORDX8                              0x03
+#define     V_008DFC_SQ_S_LOAD_DWORDX16                             0x04
+#define     V_008DFC_SQ_S_BUFFER_LOAD_DWORD                         0x08
+#define     V_008DFC_SQ_S_BUFFER_LOAD_DWORDX2                       0x09
+#define     V_008DFC_SQ_S_BUFFER_LOAD_DWORDX4                       0x0A
+#define     V_008DFC_SQ_S_BUFFER_LOAD_DWORDX8                       0x0B
+#define     V_008DFC_SQ_S_BUFFER_LOAD_DWORDX16                      0x0C
+/* CIK */
+#define     V_008DFC_SQ_S_DCACHE_INV_VOL                            0x1D
+/*     */
+#define     V_008DFC_SQ_S_MEMTIME                                   0x1E
+#define     V_008DFC_SQ_S_DCACHE_INV                                0x1F
+#define   S_008DFC_ENCODING(x)                                        (((x) & 0x1F) << 27)
+#define   G_008DFC_ENCODING(x)                                        (((x) >> 27) & 0x1F)
+#define   C_008DFC_ENCODING                                           0x07FFFFFF
+#define     V_008DFC_SQ_ENC_SMRD_FIELD                              0x18
+/* CIK */
+#define R_008DFC_SQ_FLAT_0                                              0x008DFC
+#define   S_008DFC_GLC(x)                                             (((x) & 0x1) << 16)
+#define   G_008DFC_GLC(x)                                             (((x) >> 16) & 0x1)
+#define   C_008DFC_GLC                                                0xFFFEFFFF
+#define   S_008DFC_SLC(x)                                             (((x) & 0x1) << 17)
+#define   G_008DFC_SLC(x)                                             (((x) >> 17) & 0x1)
+#define   C_008DFC_SLC                                                0xFFFDFFFF
+#define   S_008DFC_OP(x)                                              (((x) & 0x7F) << 18)
+#define   G_008DFC_OP(x)                                              (((x) >> 18) & 0x7F)
+#define   C_008DFC_OP                                                 0xFE03FFFF
+#define     V_008DFC_SQ_FLAT_LOAD_UBYTE                             0x08
+#define     V_008DFC_SQ_FLAT_LOAD_SBYTE                             0x09
+#define     V_008DFC_SQ_FLAT_LOAD_USHORT                            0x0A
+#define     V_008DFC_SQ_FLAT_LOAD_SSHORT                            0x0B
+#define     V_008DFC_SQ_FLAT_LOAD_DWORD                             0x0C
+#define     V_008DFC_SQ_FLAT_LOAD_DWORDX2                           0x0D
+#define     V_008DFC_SQ_FLAT_LOAD_DWORDX4                           0x0E
+#define     V_008DFC_SQ_FLAT_LOAD_DWORDX3                           0x0F
+#define     V_008DFC_SQ_FLAT_STORE_BYTE                             0x18
+#define     V_008DFC_SQ_FLAT_STORE_SHORT                            0x1A
+#define     V_008DFC_SQ_FLAT_STORE_DWORD                            0x1C
+#define     V_008DFC_SQ_FLAT_STORE_DWORDX2                          0x1D
+#define     V_008DFC_SQ_FLAT_STORE_DWORDX4                          0x1E
+#define     V_008DFC_SQ_FLAT_STORE_DWORDX3                          0x1F
+#define     V_008DFC_SQ_FLAT_ATOMIC_SWAP                            0x30
+#define     V_008DFC_SQ_FLAT_ATOMIC_CMPSWAP                         0x31
+#define     V_008DFC_SQ_FLAT_ATOMIC_ADD                             0x32
+#define     V_008DFC_SQ_FLAT_ATOMIC_SUB                             0x33
+#define     V_008DFC_SQ_FLAT_ATOMIC_SMIN                            0x35
+#define     V_008DFC_SQ_FLAT_ATOMIC_UMIN                            0x36
+#define     V_008DFC_SQ_FLAT_ATOMIC_SMAX                            0x37
+#define     V_008DFC_SQ_FLAT_ATOMIC_UMAX                            0x38
+#define     V_008DFC_SQ_FLAT_ATOMIC_AND                             0x39
+#define     V_008DFC_SQ_FLAT_ATOMIC_OR                              0x3A
+#define     V_008DFC_SQ_FLAT_ATOMIC_XOR                             0x3B
+#define     V_008DFC_SQ_FLAT_ATOMIC_INC                             0x3C
+#define     V_008DFC_SQ_FLAT_ATOMIC_DEC                             0x3D
+#define     V_008DFC_SQ_FLAT_ATOMIC_FCMPSWAP                        0x3E
+#define     V_008DFC_SQ_FLAT_ATOMIC_FMIN                            0x3F
+#define     V_008DFC_SQ_FLAT_ATOMIC_FMAX                            0x40
+#define     V_008DFC_SQ_FLAT_ATOMIC_SWAP_X2                         0x50
+#define     V_008DFC_SQ_FLAT_ATOMIC_CMPSWAP_X2                      0x51
+#define     V_008DFC_SQ_FLAT_ATOMIC_ADD_X2                          0x52
+#define     V_008DFC_SQ_FLAT_ATOMIC_SUB_X2                          0x53
+#define     V_008DFC_SQ_FLAT_ATOMIC_SMIN_X2                         0x55
+#define     V_008DFC_SQ_FLAT_ATOMIC_UMIN_X2                         0x56
+#define     V_008DFC_SQ_FLAT_ATOMIC_SMAX_X2                         0x57
+#define     V_008DFC_SQ_FLAT_ATOMIC_UMAX_X2                         0x58
+#define     V_008DFC_SQ_FLAT_ATOMIC_AND_X2                          0x59
+#define     V_008DFC_SQ_FLAT_ATOMIC_OR_X2                           0x5A
+#define     V_008DFC_SQ_FLAT_ATOMIC_XOR_X2                          0x5B
+#define     V_008DFC_SQ_FLAT_ATOMIC_INC_X2                          0x5C
+#define     V_008DFC_SQ_FLAT_ATOMIC_DEC_X2                          0x5D
+#define     V_008DFC_SQ_FLAT_ATOMIC_FCMPSWAP_X2                     0x5E
+#define     V_008DFC_SQ_FLAT_ATOMIC_FMIN_X2                         0x5F
+#define     V_008DFC_SQ_FLAT_ATOMIC_FMAX_X2                         0x60
+#define   S_008DFC_ENCODING(x)                                        (((x) & 0x3F) << 26)
+#define   G_008DFC_ENCODING(x)                                        (((x) >> 26) & 0x3F)
+#define   C_008DFC_ENCODING                                           0x03FFFFFF
+#define     V_008DFC_SQ_ENC_FLAT_FIELD                              0x37
+/*     */
+#define R_008DFC_SQ_EXP_1                                               0x008DFC
+#define   S_008DFC_VSRC0(x)                                           (((x) & 0xFF) << 0)
+#define   G_008DFC_VSRC0(x)                                           (((x) >> 0) & 0xFF)
+#define   C_008DFC_VSRC0                                              0xFFFFFF00
+#define     V_008DFC_SQ_VGPR                                        0x00
+#define   S_008DFC_VSRC1(x)                                           (((x) & 0xFF) << 8)
+#define   G_008DFC_VSRC1(x)                                           (((x) >> 8) & 0xFF)
+#define   C_008DFC_VSRC1                                              0xFFFF00FF
+#define     V_008DFC_SQ_VGPR                                        0x00
+#define   S_008DFC_VSRC2(x)                                           (((x) & 0xFF) << 16)
+#define   G_008DFC_VSRC2(x)                                           (((x) >> 16) & 0xFF)
+#define   C_008DFC_VSRC2                                              0xFF00FFFF
+#define     V_008DFC_SQ_VGPR                                        0x00
+#define   S_008DFC_VSRC3(x)                                           (((x) & 0xFF) << 24)
+#define   G_008DFC_VSRC3(x)                                           (((x) >> 24) & 0xFF)
+#define   C_008DFC_VSRC3                                              0x00FFFFFF
+#define     V_008DFC_SQ_VGPR                                        0x00
+#define R_008DFC_SQ_DS_1                                                0x008DFC
+#define   S_008DFC_ADDR(x)                                            (((x) & 0xFF) << 0)
+#define   G_008DFC_ADDR(x)                                            (((x) >> 0) & 0xFF)
+#define   C_008DFC_ADDR                                               0xFFFFFF00
+#define     V_008DFC_SQ_VGPR                                        0x00
+#define   S_008DFC_DATA0(x)                                           (((x) & 0xFF) << 8)
+#define   G_008DFC_DATA0(x)                                           (((x) >> 8) & 0xFF)
+#define   C_008DFC_DATA0                                              0xFFFF00FF
+#define     V_008DFC_SQ_VGPR                                        0x00
+#define   S_008DFC_DATA1(x)                                           (((x) & 0xFF) << 16)
+#define   G_008DFC_DATA1(x)                                           (((x) >> 16) & 0xFF)
+#define   C_008DFC_DATA1                                              0xFF00FFFF
+#define     V_008DFC_SQ_VGPR                                        0x00
+#define   S_008DFC_VDST(x)                                            (((x) & 0xFF) << 24)
+#define   G_008DFC_VDST(x)                                            (((x) >> 24) & 0xFF)
+#define   C_008DFC_VDST                                               0x00FFFFFF
+#define     V_008DFC_SQ_VGPR                                        0x00
+#define R_008DFC_SQ_VOPC                                                0x008DFC
+#define   S_008DFC_SRC0(x)                                            (((x) & 0x1FF) << 0)
+#define   G_008DFC_SRC0(x)                                            (((x) >> 0) & 0x1FF)
+#define   C_008DFC_SRC0                                               0xFFFFFE00
+#define     V_008DFC_SQ_SGPR                                        0x00
+#define     V_008DFC_SQ_VCC_LO                                      0x6A
+#define     V_008DFC_SQ_VCC_HI                                      0x6B
+#define     V_008DFC_SQ_TBA_LO                                      0x6C
+#define     V_008DFC_SQ_TBA_HI                                      0x6D
+#define     V_008DFC_SQ_TMA_LO                                      0x6E
+#define     V_008DFC_SQ_TMA_HI                                      0x6F
+#define     V_008DFC_SQ_TTMP0                                       0x70
+#define     V_008DFC_SQ_TTMP1                                       0x71
+#define     V_008DFC_SQ_TTMP2                                       0x72
+#define     V_008DFC_SQ_TTMP3                                       0x73
+#define     V_008DFC_SQ_TTMP4                                       0x74
+#define     V_008DFC_SQ_TTMP5                                       0x75
+#define     V_008DFC_SQ_TTMP6                                       0x76
+#define     V_008DFC_SQ_TTMP7                                       0x77
+#define     V_008DFC_SQ_TTMP8                                       0x78
+#define     V_008DFC_SQ_TTMP9                                       0x79
+#define     V_008DFC_SQ_TTMP10                                      0x7A
+#define     V_008DFC_SQ_TTMP11                                      0x7B
+#define     V_008DFC_SQ_M0                                          0x7C
+#define     V_008DFC_SQ_EXEC_LO                                     0x7E
+#define     V_008DFC_SQ_EXEC_HI                                     0x7F
+#define     V_008DFC_SQ_SRC_0                                       0x80
+#define     V_008DFC_SQ_SRC_1_INT                                   0x81
+#define     V_008DFC_SQ_SRC_2_INT                                   0x82
+#define     V_008DFC_SQ_SRC_3_INT                                   0x83
+#define     V_008DFC_SQ_SRC_4_INT                                   0x84
+#define     V_008DFC_SQ_SRC_5_INT                                   0x85
+#define     V_008DFC_SQ_SRC_6_INT                                   0x86
+#define     V_008DFC_SQ_SRC_7_INT                                   0x87
+#define     V_008DFC_SQ_SRC_8_INT                                   0x88
+#define     V_008DFC_SQ_SRC_9_INT                                   0x89
+#define     V_008DFC_SQ_SRC_10_INT                                  0x8A
+#define     V_008DFC_SQ_SRC_11_INT                                  0x8B
+#define     V_008DFC_SQ_SRC_12_INT                                  0x8C
+#define     V_008DFC_SQ_SRC_13_INT                                  0x8D
+#define     V_008DFC_SQ_SRC_14_INT                                  0x8E
+#define     V_008DFC_SQ_SRC_15_INT                                  0x8F
+#define     V_008DFC_SQ_SRC_16_INT                                  0x90
+#define     V_008DFC_SQ_SRC_17_INT                                  0x91
+#define     V_008DFC_SQ_SRC_18_INT                                  0x92
+#define     V_008DFC_SQ_SRC_19_INT                                  0x93
+#define     V_008DFC_SQ_SRC_20_INT                                  0x94
+#define     V_008DFC_SQ_SRC_21_INT                                  0x95
+#define     V_008DFC_SQ_SRC_22_INT                                  0x96
+#define     V_008DFC_SQ_SRC_23_INT                                  0x97
+#define     V_008DFC_SQ_SRC_24_INT                                  0x98
+#define     V_008DFC_SQ_SRC_25_INT                                  0x99
+#define     V_008DFC_SQ_SRC_26_INT                                  0x9A
+#define     V_008DFC_SQ_SRC_27_INT                                  0x9B
+#define     V_008DFC_SQ_SRC_28_INT                                  0x9C
+#define     V_008DFC_SQ_SRC_29_INT                                  0x9D
+#define     V_008DFC_SQ_SRC_30_INT                                  0x9E
+#define     V_008DFC_SQ_SRC_31_INT                                  0x9F
+#define     V_008DFC_SQ_SRC_32_INT                                  0xA0
+#define     V_008DFC_SQ_SRC_33_INT                                  0xA1
+#define     V_008DFC_SQ_SRC_34_INT                                  0xA2
+#define     V_008DFC_SQ_SRC_35_INT                                  0xA3
+#define     V_008DFC_SQ_SRC_36_INT                                  0xA4
+#define     V_008DFC_SQ_SRC_37_INT                                  0xA5
+#define     V_008DFC_SQ_SRC_38_INT                                  0xA6
+#define     V_008DFC_SQ_SRC_39_INT                                  0xA7
+#define     V_008DFC_SQ_SRC_40_INT                                  0xA8
+#define     V_008DFC_SQ_SRC_41_INT                                  0xA9
+#define     V_008DFC_SQ_SRC_42_INT                                  0xAA
+#define     V_008DFC_SQ_SRC_43_INT                                  0xAB
+#define     V_008DFC_SQ_SRC_44_INT                                  0xAC
+#define     V_008DFC_SQ_SRC_45_INT                                  0xAD
+#define     V_008DFC_SQ_SRC_46_INT                                  0xAE
+#define     V_008DFC_SQ_SRC_47_INT                                  0xAF
+#define     V_008DFC_SQ_SRC_48_INT                                  0xB0
+#define     V_008DFC_SQ_SRC_49_INT                                  0xB1
+#define     V_008DFC_SQ_SRC_50_INT                                  0xB2
+#define     V_008DFC_SQ_SRC_51_INT                                  0xB3
+#define     V_008DFC_SQ_SRC_52_INT                                  0xB4
+#define     V_008DFC_SQ_SRC_53_INT                                  0xB5
+#define     V_008DFC_SQ_SRC_54_INT                                  0xB6
+#define     V_008DFC_SQ_SRC_55_INT                                  0xB7
+#define     V_008DFC_SQ_SRC_56_INT                                  0xB8
+#define     V_008DFC_SQ_SRC_57_INT                                  0xB9
+#define     V_008DFC_SQ_SRC_58_INT                                  0xBA
+#define     V_008DFC_SQ_SRC_59_INT                                  0xBB
+#define     V_008DFC_SQ_SRC_60_INT                                  0xBC
+#define     V_008DFC_SQ_SRC_61_INT                                  0xBD
+#define     V_008DFC_SQ_SRC_62_INT                                  0xBE
+#define     V_008DFC_SQ_SRC_63_INT                                  0xBF
+#define     V_008DFC_SQ_SRC_64_INT                                  0xC0
+#define     V_008DFC_SQ_SRC_M_1_INT                                 0xC1
+#define     V_008DFC_SQ_SRC_M_2_INT                                 0xC2
+#define     V_008DFC_SQ_SRC_M_3_INT                                 0xC3
+#define     V_008DFC_SQ_SRC_M_4_INT                                 0xC4
+#define     V_008DFC_SQ_SRC_M_5_INT                                 0xC5
+#define     V_008DFC_SQ_SRC_M_6_INT                                 0xC6
+#define     V_008DFC_SQ_SRC_M_7_INT                                 0xC7
+#define     V_008DFC_SQ_SRC_M_8_INT                                 0xC8
+#define     V_008DFC_SQ_SRC_M_9_INT                                 0xC9
+#define     V_008DFC_SQ_SRC_M_10_INT                                0xCA
+#define     V_008DFC_SQ_SRC_M_11_INT                                0xCB
+#define     V_008DFC_SQ_SRC_M_12_INT                                0xCC
+#define     V_008DFC_SQ_SRC_M_13_INT                                0xCD
+#define     V_008DFC_SQ_SRC_M_14_INT                                0xCE
+#define     V_008DFC_SQ_SRC_M_15_INT                                0xCF
+#define     V_008DFC_SQ_SRC_M_16_INT                                0xD0
+#define     V_008DFC_SQ_SRC_0_5                                     0xF0
+#define     V_008DFC_SQ_SRC_M_0_5                                   0xF1
+#define     V_008DFC_SQ_SRC_1                                       0xF2
+#define     V_008DFC_SQ_SRC_M_1                                     0xF3
+#define     V_008DFC_SQ_SRC_2                                       0xF4
+#define     V_008DFC_SQ_SRC_M_2                                     0xF5
+#define     V_008DFC_SQ_SRC_4                                       0xF6
+#define     V_008DFC_SQ_SRC_M_4                                     0xF7
+#define     V_008DFC_SQ_SRC_VCCZ                                    0xFB
+#define     V_008DFC_SQ_SRC_EXECZ                                   0xFC
+#define     V_008DFC_SQ_SRC_SCC                                     0xFD
+#define     V_008DFC_SQ_SRC_LDS_DIRECT                              0xFE
+#define     V_008DFC_SQ_SRC_VGPR                                    0x100
+#define   S_008DFC_VSRC1(x)                                           (((x) & 0xFF) << 9)
+#define   G_008DFC_VSRC1(x)                                           (((x) >> 9) & 0xFF)
+#define   C_008DFC_VSRC1                                              0xFFFE01FF
+#define     V_008DFC_SQ_VGPR                                        0x00
+#define   S_008DFC_OP(x)                                              (((x) & 0xFF) << 17)
+#define   G_008DFC_OP(x)                                              (((x) >> 17) & 0xFF)
+#define   C_008DFC_OP                                                 0xFE01FFFF
+#define     V_008DFC_SQ_V_CMP_F_F32                                 0x00
+#define     V_008DFC_SQ_V_CMP_LT_F32                                0x01
+#define     V_008DFC_SQ_V_CMP_EQ_F32                                0x02
+#define     V_008DFC_SQ_V_CMP_LE_F32                                0x03
+#define     V_008DFC_SQ_V_CMP_GT_F32                                0x04
+#define     V_008DFC_SQ_V_CMP_LG_F32                                0x05
+#define     V_008DFC_SQ_V_CMP_GE_F32                                0x06
+#define     V_008DFC_SQ_V_CMP_O_F32                                 0x07
+#define     V_008DFC_SQ_V_CMP_U_F32                                 0x08
+#define     V_008DFC_SQ_V_CMP_NGE_F32                               0x09
+#define     V_008DFC_SQ_V_CMP_NLG_F32                               0x0A
+#define     V_008DFC_SQ_V_CMP_NGT_F32                               0x0B
+#define     V_008DFC_SQ_V_CMP_NLE_F32                               0x0C
+#define     V_008DFC_SQ_V_CMP_NEQ_F32                               0x0D
+#define     V_008DFC_SQ_V_CMP_NLT_F32                               0x0E
+#define     V_008DFC_SQ_V_CMP_TRU_F32                               0x0F
+#define     V_008DFC_SQ_V_CMPX_F_F32                                0x10
+#define     V_008DFC_SQ_V_CMPX_LT_F32                               0x11
+#define     V_008DFC_SQ_V_CMPX_EQ_F32                               0x12
+#define     V_008DFC_SQ_V_CMPX_LE_F32                               0x13
+#define     V_008DFC_SQ_V_CMPX_GT_F32                               0x14
+#define     V_008DFC_SQ_V_CMPX_LG_F32                               0x15
+#define     V_008DFC_SQ_V_CMPX_GE_F32                               0x16
+#define     V_008DFC_SQ_V_CMPX_O_F32                                0x17
+#define     V_008DFC_SQ_V_CMPX_U_F32                                0x18
+#define     V_008DFC_SQ_V_CMPX_NGE_F32                              0x19
+#define     V_008DFC_SQ_V_CMPX_NLG_F32                              0x1A
+#define     V_008DFC_SQ_V_CMPX_NGT_F32                              0x1B
+#define     V_008DFC_SQ_V_CMPX_NLE_F32                              0x1C
+#define     V_008DFC_SQ_V_CMPX_NEQ_F32                              0x1D
+#define     V_008DFC_SQ_V_CMPX_NLT_F32                              0x1E
+#define     V_008DFC_SQ_V_CMPX_TRU_F32                              0x1F
+#define     V_008DFC_SQ_V_CMP_F_F64                                 0x20
+#define     V_008DFC_SQ_V_CMP_LT_F64                                0x21
+#define     V_008DFC_SQ_V_CMP_EQ_F64                                0x22
+#define     V_008DFC_SQ_V_CMP_LE_F64                                0x23
+#define     V_008DFC_SQ_V_CMP_GT_F64                                0x24
+#define     V_008DFC_SQ_V_CMP_LG_F64                                0x25
+#define     V_008DFC_SQ_V_CMP_GE_F64                                0x26
+#define     V_008DFC_SQ_V_CMP_O_F64                                 0x27
+#define     V_008DFC_SQ_V_CMP_U_F64                                 0x28
+#define     V_008DFC_SQ_V_CMP_NGE_F64                               0x29
+#define     V_008DFC_SQ_V_CMP_NLG_F64                               0x2A
+#define     V_008DFC_SQ_V_CMP_NGT_F64                               0x2B
+#define     V_008DFC_SQ_V_CMP_NLE_F64                               0x2C
+#define     V_008DFC_SQ_V_CMP_NEQ_F64                               0x2D
+#define     V_008DFC_SQ_V_CMP_NLT_F64                               0x2E
+#define     V_008DFC_SQ_V_CMP_TRU_F64                               0x2F
+#define     V_008DFC_SQ_V_CMPX_F_F64                                0x30
+#define     V_008DFC_SQ_V_CMPX_LT_F64                               0x31
+#define     V_008DFC_SQ_V_CMPX_EQ_F64                               0x32
+#define     V_008DFC_SQ_V_CMPX_LE_F64                               0x33
+#define     V_008DFC_SQ_V_CMPX_GT_F64                               0x34
+#define     V_008DFC_SQ_V_CMPX_LG_F64                               0x35
+#define     V_008DFC_SQ_V_CMPX_GE_F64                               0x36
+#define     V_008DFC_SQ_V_CMPX_O_F64                                0x37
+#define     V_008DFC_SQ_V_CMPX_U_F64                                0x38
+#define     V_008DFC_SQ_V_CMPX_NGE_F64                              0x39
+#define     V_008DFC_SQ_V_CMPX_NLG_F64                              0x3A
+#define     V_008DFC_SQ_V_CMPX_NGT_F64                              0x3B
+#define     V_008DFC_SQ_V_CMPX_NLE_F64                              0x3C
+#define     V_008DFC_SQ_V_CMPX_NEQ_F64                              0x3D
+#define     V_008DFC_SQ_V_CMPX_NLT_F64                              0x3E
+#define     V_008DFC_SQ_V_CMPX_TRU_F64                              0x3F
+#define     V_008DFC_SQ_V_CMPS_F_F32                                0x40
+#define     V_008DFC_SQ_V_CMPS_LT_F32                               0x41
+#define     V_008DFC_SQ_V_CMPS_EQ_F32                               0x42
+#define     V_008DFC_SQ_V_CMPS_LE_F32                               0x43
+#define     V_008DFC_SQ_V_CMPS_GT_F32                               0x44
+#define     V_008DFC_SQ_V_CMPS_LG_F32                               0x45
+#define     V_008DFC_SQ_V_CMPS_GE_F32                               0x46
+#define     V_008DFC_SQ_V_CMPS_O_F32                                0x47
+#define     V_008DFC_SQ_V_CMPS_U_F32                                0x48
+#define     V_008DFC_SQ_V_CMPS_NGE_F32                              0x49
+#define     V_008DFC_SQ_V_CMPS_NLG_F32                              0x4A
+#define     V_008DFC_SQ_V_CMPS_NGT_F32                              0x4B
+#define     V_008DFC_SQ_V_CMPS_NLE_F32                              0x4C
+#define     V_008DFC_SQ_V_CMPS_NEQ_F32                              0x4D
+#define     V_008DFC_SQ_V_CMPS_NLT_F32                              0x4E
+#define     V_008DFC_SQ_V_CMPS_TRU_F32                              0x4F
+#define     V_008DFC_SQ_V_CMPSX_F_F32                               0x50
+#define     V_008DFC_SQ_V_CMPSX_LT_F32                              0x51
+#define     V_008DFC_SQ_V_CMPSX_EQ_F32                              0x52
+#define     V_008DFC_SQ_V_CMPSX_LE_F32                              0x53
+#define     V_008DFC_SQ_V_CMPSX_GT_F32                              0x54
+#define     V_008DFC_SQ_V_CMPSX_LG_F32                              0x55
+#define     V_008DFC_SQ_V_CMPSX_GE_F32                              0x56
+#define     V_008DFC_SQ_V_CMPSX_O_F32                               0x57
+#define     V_008DFC_SQ_V_CMPSX_U_F32                               0x58
+#define     V_008DFC_SQ_V_CMPSX_NGE_F32                             0x59
+#define     V_008DFC_SQ_V_CMPSX_NLG_F32                             0x5A
+#define     V_008DFC_SQ_V_CMPSX_NGT_F32                             0x5B
+#define     V_008DFC_SQ_V_CMPSX_NLE_F32                             0x5C
+#define     V_008DFC_SQ_V_CMPSX_NEQ_F32                             0x5D
+#define     V_008DFC_SQ_V_CMPSX_NLT_F32                             0x5E
+#define     V_008DFC_SQ_V_CMPSX_TRU_F32                             0x5F
+#define     V_008DFC_SQ_V_CMPS_F_F64                                0x60
+#define     V_008DFC_SQ_V_CMPS_LT_F64                               0x61
+#define     V_008DFC_SQ_V_CMPS_EQ_F64                               0x62
+#define     V_008DFC_SQ_V_CMPS_LE_F64                               0x63
+#define     V_008DFC_SQ_V_CMPS_GT_F64                               0x64
+#define     V_008DFC_SQ_V_CMPS_LG_F64                               0x65
+#define     V_008DFC_SQ_V_CMPS_GE_F64                               0x66
+#define     V_008DFC_SQ_V_CMPS_O_F64                                0x67
+#define     V_008DFC_SQ_V_CMPS_U_F64                                0x68
+#define     V_008DFC_SQ_V_CMPS_NGE_F64                              0x69
+#define     V_008DFC_SQ_V_CMPS_NLG_F64                              0x6A
+#define     V_008DFC_SQ_V_CMPS_NGT_F64                              0x6B
+#define     V_008DFC_SQ_V_CMPS_NLE_F64                              0x6C
+#define     V_008DFC_SQ_V_CMPS_NEQ_F64                              0x6D
+#define     V_008DFC_SQ_V_CMPS_NLT_F64                              0x6E
+#define     V_008DFC_SQ_V_CMPS_TRU_F64                              0x6F
+#define     V_008DFC_SQ_V_CMPSX_F_F64                               0x70
+#define     V_008DFC_SQ_V_CMPSX_LT_F64                              0x71
+#define     V_008DFC_SQ_V_CMPSX_EQ_F64                              0x72
+#define     V_008DFC_SQ_V_CMPSX_LE_F64                              0x73
+#define     V_008DFC_SQ_V_CMPSX_GT_F64                              0x74
+#define     V_008DFC_SQ_V_CMPSX_LG_F64                              0x75
+#define     V_008DFC_SQ_V_CMPSX_GE_F64                              0x76
+#define     V_008DFC_SQ_V_CMPSX_O_F64                               0x77
+#define     V_008DFC_SQ_V_CMPSX_U_F64                               0x78
+#define     V_008DFC_SQ_V_CMPSX_NGE_F64                             0x79
+#define     V_008DFC_SQ_V_CMPSX_NLG_F64                             0x7A
+#define     V_008DFC_SQ_V_CMPSX_NGT_F64                             0x7B
+#define     V_008DFC_SQ_V_CMPSX_NLE_F64                             0x7C
+#define     V_008DFC_SQ_V_CMPSX_NEQ_F64                             0x7D
+#define     V_008DFC_SQ_V_CMPSX_NLT_F64                             0x7E
+#define     V_008DFC_SQ_V_CMPSX_TRU_F64                             0x7F
+#define     V_008DFC_SQ_V_CMP_F_I32                                 0x80
+#define     V_008DFC_SQ_V_CMP_LT_I32                                0x81
+#define     V_008DFC_SQ_V_CMP_EQ_I32                                0x82
+#define     V_008DFC_SQ_V_CMP_LE_I32                                0x83
+#define     V_008DFC_SQ_V_CMP_GT_I32                                0x84
+#define     V_008DFC_SQ_V_CMP_NE_I32                                0x85
+#define     V_008DFC_SQ_V_CMP_GE_I32                                0x86
+#define     V_008DFC_SQ_V_CMP_T_I32                                 0x87
+#define     V_008DFC_SQ_V_CMP_CLASS_F32                             0x88
+#define     V_008DFC_SQ_V_CMPX_F_I32                                0x90
+#define     V_008DFC_SQ_V_CMPX_LT_I32                               0x91
+#define     V_008DFC_SQ_V_CMPX_EQ_I32                               0x92
+#define     V_008DFC_SQ_V_CMPX_LE_I32                               0x93
+#define     V_008DFC_SQ_V_CMPX_GT_I32                               0x94
+#define     V_008DFC_SQ_V_CMPX_NE_I32                               0x95
+#define     V_008DFC_SQ_V_CMPX_GE_I32                               0x96
+#define     V_008DFC_SQ_V_CMPX_T_I32                                0x97
+#define     V_008DFC_SQ_V_CMPX_CLASS_F32                            0x98
+#define     V_008DFC_SQ_V_CMP_F_I64                                 0xA0
+#define     V_008DFC_SQ_V_CMP_LT_I64                                0xA1
+#define     V_008DFC_SQ_V_CMP_EQ_I64                                0xA2
+#define     V_008DFC_SQ_V_CMP_LE_I64                                0xA3
+#define     V_008DFC_SQ_V_CMP_GT_I64                                0xA4
+#define     V_008DFC_SQ_V_CMP_NE_I64                                0xA5
+#define     V_008DFC_SQ_V_CMP_GE_I64                                0xA6
+#define     V_008DFC_SQ_V_CMP_T_I64                                 0xA7
+#define     V_008DFC_SQ_V_CMP_CLASS_F64                             0xA8
+#define     V_008DFC_SQ_V_CMPX_F_I64                                0xB0
+#define     V_008DFC_SQ_V_CMPX_LT_I64                               0xB1
+#define     V_008DFC_SQ_V_CMPX_EQ_I64                               0xB2
+#define     V_008DFC_SQ_V_CMPX_LE_I64                               0xB3
+#define     V_008DFC_SQ_V_CMPX_GT_I64                               0xB4
+#define     V_008DFC_SQ_V_CMPX_NE_I64                               0xB5
+#define     V_008DFC_SQ_V_CMPX_GE_I64                               0xB6
+#define     V_008DFC_SQ_V_CMPX_T_I64                                0xB7
+#define     V_008DFC_SQ_V_CMPX_CLASS_F64                            0xB8
+#define     V_008DFC_SQ_V_CMP_F_U32                                 0xC0
+#define     V_008DFC_SQ_V_CMP_LT_U32                                0xC1
+#define     V_008DFC_SQ_V_CMP_EQ_U32                                0xC2
+#define     V_008DFC_SQ_V_CMP_LE_U32                                0xC3
+#define     V_008DFC_SQ_V_CMP_GT_U32                                0xC4
+#define     V_008DFC_SQ_V_CMP_NE_U32                                0xC5
+#define     V_008DFC_SQ_V_CMP_GE_U32                                0xC6
+#define     V_008DFC_SQ_V_CMP_T_U32                                 0xC7
+#define     V_008DFC_SQ_V_CMPX_F_U32                                0xD0
+#define     V_008DFC_SQ_V_CMPX_LT_U32                               0xD1
+#define     V_008DFC_SQ_V_CMPX_EQ_U32                               0xD2
+#define     V_008DFC_SQ_V_CMPX_LE_U32                               0xD3
+#define     V_008DFC_SQ_V_CMPX_GT_U32                               0xD4
+#define     V_008DFC_SQ_V_CMPX_NE_U32                               0xD5
+#define     V_008DFC_SQ_V_CMPX_GE_U32                               0xD6
+#define     V_008DFC_SQ_V_CMPX_T_U32                                0xD7
+#define     V_008DFC_SQ_V_CMP_F_U64                                 0xE0
+#define     V_008DFC_SQ_V_CMP_LT_U64                                0xE1
+#define     V_008DFC_SQ_V_CMP_EQ_U64                                0xE2
+#define     V_008DFC_SQ_V_CMP_LE_U64                                0xE3
+#define     V_008DFC_SQ_V_CMP_GT_U64                                0xE4
+#define     V_008DFC_SQ_V_CMP_NE_U64                                0xE5
+#define     V_008DFC_SQ_V_CMP_GE_U64                                0xE6
+#define     V_008DFC_SQ_V_CMP_T_U64                                 0xE7
+#define     V_008DFC_SQ_V_CMPX_F_U64                                0xF0
+#define     V_008DFC_SQ_V_CMPX_LT_U64                               0xF1
+#define     V_008DFC_SQ_V_CMPX_EQ_U64                               0xF2
+#define     V_008DFC_SQ_V_CMPX_LE_U64                               0xF3
+#define     V_008DFC_SQ_V_CMPX_GT_U64                               0xF4
+#define     V_008DFC_SQ_V_CMPX_NE_U64                               0xF5
+#define     V_008DFC_SQ_V_CMPX_GE_U64                               0xF6
+#define     V_008DFC_SQ_V_CMPX_T_U64                                0xF7
+#define   S_008DFC_ENCODING(x)                                        (((x) & 0x7F) << 25)
+#define   G_008DFC_ENCODING(x)                                        (((x) >> 25) & 0x7F)
+#define   C_008DFC_ENCODING                                           0x01FFFFFF
+#define     V_008DFC_SQ_ENC_VOPC_FIELD                              0x3E
+#define R_008DFC_SQ_SOP1                                                0x008DFC
+#define   S_008DFC_SSRC0(x)                                           (((x) & 0xFF) << 0)
+#define   G_008DFC_SSRC0(x)                                           (((x) >> 0) & 0xFF)
+#define   C_008DFC_SSRC0                                              0xFFFFFF00
+#define     V_008DFC_SQ_SGPR                                        0x00
+/* CIK */
+#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
+#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
+/*     */
+#define     V_008DFC_SQ_VCC_LO                                      0x6A
+#define     V_008DFC_SQ_VCC_HI                                      0x6B
+#define     V_008DFC_SQ_TBA_LO                                      0x6C
+#define     V_008DFC_SQ_TBA_HI                                      0x6D
+#define     V_008DFC_SQ_TMA_LO                                      0x6E
+#define     V_008DFC_SQ_TMA_HI                                      0x6F
+#define     V_008DFC_SQ_TTMP0                                       0x70
+#define     V_008DFC_SQ_TTMP1                                       0x71
+#define     V_008DFC_SQ_TTMP2                                       0x72
+#define     V_008DFC_SQ_TTMP3                                       0x73
+#define     V_008DFC_SQ_TTMP4                                       0x74
+#define     V_008DFC_SQ_TTMP5                                       0x75
+#define     V_008DFC_SQ_TTMP6                                       0x76
+#define     V_008DFC_SQ_TTMP7                                       0x77
+#define     V_008DFC_SQ_TTMP8                                       0x78
+#define     V_008DFC_SQ_TTMP9                                       0x79
+#define     V_008DFC_SQ_TTMP10                                      0x7A
+#define     V_008DFC_SQ_TTMP11                                      0x7B
+#define     V_008DFC_SQ_M0                                          0x7C
+#define     V_008DFC_SQ_EXEC_LO                                     0x7E
+#define     V_008DFC_SQ_EXEC_HI                                     0x7F
+#define     V_008DFC_SQ_SRC_0                                       0x80
+#define     V_008DFC_SQ_SRC_1_INT                                   0x81
+#define     V_008DFC_SQ_SRC_2_INT                                   0x82
+#define     V_008DFC_SQ_SRC_3_INT                                   0x83
+#define     V_008DFC_SQ_SRC_4_INT                                   0x84
+#define     V_008DFC_SQ_SRC_5_INT                                   0x85
+#define     V_008DFC_SQ_SRC_6_INT                                   0x86
+#define     V_008DFC_SQ_SRC_7_INT                                   0x87
+#define     V_008DFC_SQ_SRC_8_INT                                   0x88
+#define     V_008DFC_SQ_SRC_9_INT                                   0x89
+#define     V_008DFC_SQ_SRC_10_INT                                  0x8A
+#define     V_008DFC_SQ_SRC_11_INT                                  0x8B
+#define     V_008DFC_SQ_SRC_12_INT                                  0x8C
+#define     V_008DFC_SQ_SRC_13_INT                                  0x8D
+#define     V_008DFC_SQ_SRC_14_INT                                  0x8E
+#define     V_008DFC_SQ_SRC_15_INT                                  0x8F
+#define     V_008DFC_SQ_SRC_16_INT                                  0x90
+#define     V_008DFC_SQ_SRC_17_INT                                  0x91
+#define     V_008DFC_SQ_SRC_18_INT                                  0x92
+#define     V_008DFC_SQ_SRC_19_INT                                  0x93
+#define     V_008DFC_SQ_SRC_20_INT                                  0x94
+#define     V_008DFC_SQ_SRC_21_INT                                  0x95
+#define     V_008DFC_SQ_SRC_22_INT                                  0x96
+#define     V_008DFC_SQ_SRC_23_INT                                  0x97
+#define     V_008DFC_SQ_SRC_24_INT                                  0x98
+#define     V_008DFC_SQ_SRC_25_INT                                  0x99
+#define     V_008DFC_SQ_SRC_26_INT                                  0x9A
+#define     V_008DFC_SQ_SRC_27_INT                                  0x9B
+#define     V_008DFC_SQ_SRC_28_INT                                  0x9C
+#define     V_008DFC_SQ_SRC_29_INT                                  0x9D
+#define     V_008DFC_SQ_SRC_30_INT                                  0x9E
+#define     V_008DFC_SQ_SRC_31_INT                                  0x9F
+#define     V_008DFC_SQ_SRC_32_INT                                  0xA0
+#define     V_008DFC_SQ_SRC_33_INT                                  0xA1
+#define     V_008DFC_SQ_SRC_34_INT                                  0xA2
+#define     V_008DFC_SQ_SRC_35_INT                                  0xA3
+#define     V_008DFC_SQ_SRC_36_INT                                  0xA4
+#define     V_008DFC_SQ_SRC_37_INT                                  0xA5
+#define     V_008DFC_SQ_SRC_38_INT                                  0xA6
+#define     V_008DFC_SQ_SRC_39_INT                                  0xA7
+#define     V_008DFC_SQ_SRC_40_INT                                  0xA8
+#define     V_008DFC_SQ_SRC_41_INT                                  0xA9
+#define     V_008DFC_SQ_SRC_42_INT                                  0xAA
+#define     V_008DFC_SQ_SRC_43_INT                                  0xAB
+#define     V_008DFC_SQ_SRC_44_INT                                  0xAC
+#define     V_008DFC_SQ_SRC_45_INT                                  0xAD
+#define     V_008DFC_SQ_SRC_46_INT                                  0xAE
+#define     V_008DFC_SQ_SRC_47_INT                                  0xAF
+#define     V_008DFC_SQ_SRC_48_INT                                  0xB0
+#define     V_008DFC_SQ_SRC_49_INT                                  0xB1
+#define     V_008DFC_SQ_SRC_50_INT                                  0xB2
+#define     V_008DFC_SQ_SRC_51_INT                                  0xB3
+#define     V_008DFC_SQ_SRC_52_INT                                  0xB4
+#define     V_008DFC_SQ_SRC_53_INT                                  0xB5
+#define     V_008DFC_SQ_SRC_54_INT                                  0xB6
+#define     V_008DFC_SQ_SRC_55_INT                                  0xB7
+#define     V_008DFC_SQ_SRC_56_INT                                  0xB8
+#define     V_008DFC_SQ_SRC_57_INT                                  0xB9
+#define     V_008DFC_SQ_SRC_58_INT                                  0xBA
+#define     V_008DFC_SQ_SRC_59_INT                                  0xBB
+#define     V_008DFC_SQ_SRC_60_INT                                  0xBC
+#define     V_008DFC_SQ_SRC_61_INT                                  0xBD
+#define     V_008DFC_SQ_SRC_62_INT                                  0xBE
+#define     V_008DFC_SQ_SRC_63_INT                                  0xBF
+#define     V_008DFC_SQ_SRC_64_INT                                  0xC0
+#define     V_008DFC_SQ_SRC_M_1_INT                                 0xC1
+#define     V_008DFC_SQ_SRC_M_2_INT                                 0xC2
+#define     V_008DFC_SQ_SRC_M_3_INT                                 0xC3
+#define     V_008DFC_SQ_SRC_M_4_INT                                 0xC4
+#define     V_008DFC_SQ_SRC_M_5_INT                                 0xC5
+#define     V_008DFC_SQ_SRC_M_6_INT                                 0xC6
+#define     V_008DFC_SQ_SRC_M_7_INT                                 0xC7
+#define     V_008DFC_SQ_SRC_M_8_INT                                 0xC8
+#define     V_008DFC_SQ_SRC_M_9_INT                                 0xC9
+#define     V_008DFC_SQ_SRC_M_10_INT                                0xCA
+#define     V_008DFC_SQ_SRC_M_11_INT                                0xCB
+#define     V_008DFC_SQ_SRC_M_12_INT                                0xCC
+#define     V_008DFC_SQ_SRC_M_13_INT                                0xCD
+#define     V_008DFC_SQ_SRC_M_14_INT                                0xCE
+#define     V_008DFC_SQ_SRC_M_15_INT                                0xCF
+#define     V_008DFC_SQ_SRC_M_16_INT                                0xD0
+#define     V_008DFC_SQ_SRC_0_5                                     0xF0
+#define     V_008DFC_SQ_SRC_M_0_5                                   0xF1
+#define     V_008DFC_SQ_SRC_1                                       0xF2
+#define     V_008DFC_SQ_SRC_M_1                                     0xF3
+#define     V_008DFC_SQ_SRC_2                                       0xF4
+#define     V_008DFC_SQ_SRC_M_2                                     0xF5
+#define     V_008DFC_SQ_SRC_4                                       0xF6
+#define     V_008DFC_SQ_SRC_M_4                                     0xF7
+#define     V_008DFC_SQ_SRC_VCCZ                                    0xFB
+#define     V_008DFC_SQ_SRC_EXECZ                                   0xFC
+#define     V_008DFC_SQ_SRC_SCC                                     0xFD
+#define     V_008DFC_SQ_SRC_LDS_DIRECT                              0xFE
+#define   S_008DFC_OP(x)                                              (((x) & 0xFF) << 8)
+#define   G_008DFC_OP(x)                                              (((x) >> 8) & 0xFF)
+#define   C_008DFC_OP                                                 0xFFFF00FF
+#define     V_008DFC_SQ_S_MOV_B32                                   0x03
+#define     V_008DFC_SQ_S_MOV_B64                                   0x04
+#define     V_008DFC_SQ_S_CMOV_B32                                  0x05
+#define     V_008DFC_SQ_S_CMOV_B64                                  0x06
+#define     V_008DFC_SQ_S_NOT_B32                                   0x07
+#define     V_008DFC_SQ_S_NOT_B64                                   0x08
+#define     V_008DFC_SQ_S_WQM_B32                                   0x09
+#define     V_008DFC_SQ_S_WQM_B64                                   0x0A
+#define     V_008DFC_SQ_S_BREV_B32                                  0x0B
+#define     V_008DFC_SQ_S_BREV_B64                                  0x0C
+#define     V_008DFC_SQ_S_BCNT0_I32_B32                             0x0D
+#define     V_008DFC_SQ_S_BCNT0_I32_B64                             0x0E
+#define     V_008DFC_SQ_S_BCNT1_I32_B32                             0x0F
+#define     V_008DFC_SQ_S_BCNT1_I32_B64                             0x10
+#define     V_008DFC_SQ_S_FF0_I32_B32                               0x11
+#define     V_008DFC_SQ_S_FF0_I32_B64                               0x12
+#define     V_008DFC_SQ_S_FF1_I32_B32                               0x13
+#define     V_008DFC_SQ_S_FF1_I32_B64                               0x14
+#define     V_008DFC_SQ_S_FLBIT_I32_B32                             0x15
+#define     V_008DFC_SQ_S_FLBIT_I32_B64                             0x16
+#define     V_008DFC_SQ_S_FLBIT_I32                                 0x17
+#define     V_008DFC_SQ_S_FLBIT_I32_I64                             0x18
+#define     V_008DFC_SQ_S_SEXT_I32_I8                               0x19
+#define     V_008DFC_SQ_S_SEXT_I32_I16                              0x1A
+#define     V_008DFC_SQ_S_BITSET0_B32                               0x1B
+#define     V_008DFC_SQ_S_BITSET0_B64                               0x1C
+#define     V_008DFC_SQ_S_BITSET1_B32                               0x1D
+#define     V_008DFC_SQ_S_BITSET1_B64                               0x1E
+#define     V_008DFC_SQ_S_GETPC_B64                                 0x1F
+#define     V_008DFC_SQ_S_SETPC_B64                                 0x20
+#define     V_008DFC_SQ_S_SWAPPC_B64                                0x21
+#define     V_008DFC_SQ_S_RFE_B64                                   0x22
+#define     V_008DFC_SQ_S_AND_SAVEEXEC_B64                          0x24
+#define     V_008DFC_SQ_S_OR_SAVEEXEC_B64                           0x25
+#define     V_008DFC_SQ_S_XOR_SAVEEXEC_B64                          0x26
+#define     V_008DFC_SQ_S_ANDN2_SAVEEXEC_B64                        0x27
+#define     V_008DFC_SQ_S_ORN2_SAVEEXEC_B64                         0x28
+#define     V_008DFC_SQ_S_NAND_SAVEEXEC_B64                         0x29
+#define     V_008DFC_SQ_S_NOR_SAVEEXEC_B64                          0x2A
+#define     V_008DFC_SQ_S_XNOR_SAVEEXEC_B64                         0x2B
+#define     V_008DFC_SQ_S_QUADMASK_B32                              0x2C
+#define     V_008DFC_SQ_S_QUADMASK_B64                              0x2D
+#define     V_008DFC_SQ_S_MOVRELS_B32                               0x2E
+#define     V_008DFC_SQ_S_MOVRELS_B64                               0x2F
+#define     V_008DFC_SQ_S_MOVRELD_B32                               0x30
+#define     V_008DFC_SQ_S_MOVRELD_B64                               0x31
+#define     V_008DFC_SQ_S_CBRANCH_JOIN                              0x32
+#define     V_008DFC_SQ_S_MOV_REGRD_B32                             0x33
+#define     V_008DFC_SQ_S_ABS_I32                                   0x34
+#define     V_008DFC_SQ_S_MOV_FED_B32                               0x35
+#define   S_008DFC_SDST(x)                                            (((x) & 0x7F) << 16)
+#define   G_008DFC_SDST(x)                                            (((x) >> 16) & 0x7F)
+#define   C_008DFC_SDST                                               0xFF80FFFF
+#define     V_008DFC_SQ_SGPR                                        0x00
+/* CIK */
+#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
+#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
+/*     */
+#define     V_008DFC_SQ_VCC_LO                                      0x6A
+#define     V_008DFC_SQ_VCC_HI                                      0x6B
+#define     V_008DFC_SQ_TBA_LO                                      0x6C
+#define     V_008DFC_SQ_TBA_HI                                      0x6D
+#define     V_008DFC_SQ_TMA_LO                                      0x6E
+#define     V_008DFC_SQ_TMA_HI                                      0x6F
+#define     V_008DFC_SQ_TTMP0                                       0x70
+#define     V_008DFC_SQ_TTMP1                                       0x71
+#define     V_008DFC_SQ_TTMP2                                       0x72
+#define     V_008DFC_SQ_TTMP3                                       0x73
+#define     V_008DFC_SQ_TTMP4                                       0x74
+#define     V_008DFC_SQ_TTMP5                                       0x75
+#define     V_008DFC_SQ_TTMP6                                       0x76
+#define     V_008DFC_SQ_TTMP7                                       0x77
+#define     V_008DFC_SQ_TTMP8                                       0x78
+#define     V_008DFC_SQ_TTMP9                                       0x79
+#define     V_008DFC_SQ_TTMP10                                      0x7A
+#define     V_008DFC_SQ_TTMP11                                      0x7B
+#define     V_008DFC_SQ_M0                                          0x7C
+#define     V_008DFC_SQ_EXEC_LO                                     0x7E
+#define     V_008DFC_SQ_EXEC_HI                                     0x7F
+#define   S_008DFC_ENCODING(x)                                        (((x) & 0x1FF) << 23)
+#define   G_008DFC_ENCODING(x)                                        (((x) >> 23) & 0x1FF)
+#define   C_008DFC_ENCODING                                           0x007FFFFF
+#define     V_008DFC_SQ_ENC_SOP1_FIELD                              0x17D
+#define R_008DFC_SQ_MTBUF_1                                             0x008DFC
+#define   S_008DFC_VADDR(x)                                           (((x) & 0xFF) << 0)
+#define   G_008DFC_VADDR(x)                                           (((x) >> 0) & 0xFF)
+#define   C_008DFC_VADDR                                              0xFFFFFF00
+#define     V_008DFC_SQ_VGPR                                        0x00
+#define   S_008DFC_VDATA(x)                                           (((x) & 0xFF) << 8)
+#define   G_008DFC_VDATA(x)                                           (((x) >> 8) & 0xFF)
+#define   C_008DFC_VDATA                                              0xFFFF00FF
+#define     V_008DFC_SQ_VGPR                                        0x00
+#define   S_008DFC_SRSRC(x)                                           (((x) & 0x1F) << 16)
+#define   G_008DFC_SRSRC(x)                                           (((x) >> 16) & 0x1F)
+#define   C_008DFC_SRSRC                                              0xFFE0FFFF
+#define   S_008DFC_SLC(x)                                             (((x) & 0x1) << 22)
+#define   G_008DFC_SLC(x)                                             (((x) >> 22) & 0x1)
+#define   C_008DFC_SLC                                                0xFFBFFFFF
+#define   S_008DFC_TFE(x)                                             (((x) & 0x1) << 23)
+#define   G_008DFC_TFE(x)                                             (((x) >> 23) & 0x1)
+#define   C_008DFC_TFE                                                0xFF7FFFFF
+#define   S_008DFC_SOFFSET(x)                                         (((x) & 0xFF) << 24)
+#define   G_008DFC_SOFFSET(x)                                         (((x) >> 24) & 0xFF)
+#define   C_008DFC_SOFFSET                                            0x00FFFFFF
+#define     V_008DFC_SQ_SGPR                                        0x00
+/* CIK */
+#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
+#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
+/*     */
+#define     V_008DFC_SQ_VCC_LO                                      0x6A
+#define     V_008DFC_SQ_VCC_HI                                      0x6B
+#define     V_008DFC_SQ_TBA_LO                                      0x6C
+#define     V_008DFC_SQ_TBA_HI                                      0x6D
+#define     V_008DFC_SQ_TMA_LO                                      0x6E
+#define     V_008DFC_SQ_TMA_HI                                      0x6F
+#define     V_008DFC_SQ_TTMP0                                       0x70
+#define     V_008DFC_SQ_TTMP1                                       0x71
+#define     V_008DFC_SQ_TTMP2                                       0x72
+#define     V_008DFC_SQ_TTMP3                                       0x73
+#define     V_008DFC_SQ_TTMP4                                       0x74
+#define     V_008DFC_SQ_TTMP5                                       0x75
+#define     V_008DFC_SQ_TTMP6                                       0x76
+#define     V_008DFC_SQ_TTMP7                                       0x77
+#define     V_008DFC_SQ_TTMP8                                       0x78
+#define     V_008DFC_SQ_TTMP9                                       0x79
+#define     V_008DFC_SQ_TTMP10                                      0x7A
+#define     V_008DFC_SQ_TTMP11                                      0x7B
+#define     V_008DFC_SQ_M0                                          0x7C
+#define     V_008DFC_SQ_EXEC_LO                                     0x7E
+#define     V_008DFC_SQ_EXEC_HI                                     0x7F
+#define     V_008DFC_SQ_SRC_0                                       0x80
+#define     V_008DFC_SQ_SRC_1_INT                                   0x81
+#define     V_008DFC_SQ_SRC_2_INT                                   0x82
+#define     V_008DFC_SQ_SRC_3_INT                                   0x83
+#define     V_008DFC_SQ_SRC_4_INT                                   0x84
+#define     V_008DFC_SQ_SRC_5_INT                                   0x85
+#define     V_008DFC_SQ_SRC_6_INT                                   0x86
+#define     V_008DFC_SQ_SRC_7_INT                                   0x87
+#define     V_008DFC_SQ_SRC_8_INT                                   0x88
+#define     V_008DFC_SQ_SRC_9_INT                                   0x89
+#define     V_008DFC_SQ_SRC_10_INT                                  0x8A
+#define     V_008DFC_SQ_SRC_11_INT                                  0x8B
+#define     V_008DFC_SQ_SRC_12_INT                                  0x8C
+#define     V_008DFC_SQ_SRC_13_INT                                  0x8D
+#define     V_008DFC_SQ_SRC_14_INT                                  0x8E
+#define     V_008DFC_SQ_SRC_15_INT                                  0x8F
+#define     V_008DFC_SQ_SRC_16_INT                                  0x90
+#define     V_008DFC_SQ_SRC_17_INT                                  0x91
+#define     V_008DFC_SQ_SRC_18_INT                                  0x92
+#define     V_008DFC_SQ_SRC_19_INT                                  0x93
+#define     V_008DFC_SQ_SRC_20_INT                                  0x94
+#define     V_008DFC_SQ_SRC_21_INT                                  0x95
+#define     V_008DFC_SQ_SRC_22_INT                                  0x96
+#define     V_008DFC_SQ_SRC_23_INT                                  0x97
+#define     V_008DFC_SQ_SRC_24_INT                                  0x98
+#define     V_008DFC_SQ_SRC_25_INT                                  0x99
+#define     V_008DFC_SQ_SRC_26_INT                                  0x9A
+#define     V_008DFC_SQ_SRC_27_INT                                  0x9B
+#define     V_008DFC_SQ_SRC_28_INT                                  0x9C
+#define     V_008DFC_SQ_SRC_29_INT                                  0x9D
+#define     V_008DFC_SQ_SRC_30_INT                                  0x9E
+#define     V_008DFC_SQ_SRC_31_INT                                  0x9F
+#define     V_008DFC_SQ_SRC_32_INT                                  0xA0
+#define     V_008DFC_SQ_SRC_33_INT                                  0xA1
+#define     V_008DFC_SQ_SRC_34_INT                                  0xA2
+#define     V_008DFC_SQ_SRC_35_INT                                  0xA3
+#define     V_008DFC_SQ_SRC_36_INT                                  0xA4
+#define     V_008DFC_SQ_SRC_37_INT                                  0xA5
+#define     V_008DFC_SQ_SRC_38_INT                                  0xA6
+#define     V_008DFC_SQ_SRC_39_INT                                  0xA7
+#define     V_008DFC_SQ_SRC_40_INT                                  0xA8
+#define     V_008DFC_SQ_SRC_41_INT                                  0xA9
+#define     V_008DFC_SQ_SRC_42_INT                                  0xAA
+#define     V_008DFC_SQ_SRC_43_INT                                  0xAB
+#define     V_008DFC_SQ_SRC_44_INT                                  0xAC
+#define     V_008DFC_SQ_SRC_45_INT                                  0xAD
+#define     V_008DFC_SQ_SRC_46_INT                                  0xAE
+#define     V_008DFC_SQ_SRC_47_INT                                  0xAF
+#define     V_008DFC_SQ_SRC_48_INT                                  0xB0
+#define     V_008DFC_SQ_SRC_49_INT                                  0xB1
+#define     V_008DFC_SQ_SRC_50_INT                                  0xB2
+#define     V_008DFC_SQ_SRC_51_INT                                  0xB3
+#define     V_008DFC_SQ_SRC_52_INT                                  0xB4
+#define     V_008DFC_SQ_SRC_53_INT                                  0xB5
+#define     V_008DFC_SQ_SRC_54_INT                                  0xB6
+#define     V_008DFC_SQ_SRC_55_INT                                  0xB7
+#define     V_008DFC_SQ_SRC_56_INT                                  0xB8
+#define     V_008DFC_SQ_SRC_57_INT                                  0xB9
+#define     V_008DFC_SQ_SRC_58_INT                                  0xBA
+#define     V_008DFC_SQ_SRC_59_INT                                  0xBB
+#define     V_008DFC_SQ_SRC_60_INT                                  0xBC
+#define     V_008DFC_SQ_SRC_61_INT                                  0xBD
+#define     V_008DFC_SQ_SRC_62_INT                                  0xBE
+#define     V_008DFC_SQ_SRC_63_INT                                  0xBF
+#define     V_008DFC_SQ_SRC_64_INT                                  0xC0
+#define     V_008DFC_SQ_SRC_M_1_INT                                 0xC1
+#define     V_008DFC_SQ_SRC_M_2_INT                                 0xC2
+#define     V_008DFC_SQ_SRC_M_3_INT                                 0xC3
+#define     V_008DFC_SQ_SRC_M_4_INT                                 0xC4
+#define     V_008DFC_SQ_SRC_M_5_INT                                 0xC5
+#define     V_008DFC_SQ_SRC_M_6_INT                                 0xC6
+#define     V_008DFC_SQ_SRC_M_7_INT                                 0xC7
+#define     V_008DFC_SQ_SRC_M_8_INT                                 0xC8
+#define     V_008DFC_SQ_SRC_M_9_INT                                 0xC9
+#define     V_008DFC_SQ_SRC_M_10_INT                                0xCA
+#define     V_008DFC_SQ_SRC_M_11_INT                                0xCB
+#define     V_008DFC_SQ_SRC_M_12_INT                                0xCC
+#define     V_008DFC_SQ_SRC_M_13_INT                                0xCD
+#define     V_008DFC_SQ_SRC_M_14_INT                                0xCE
+#define     V_008DFC_SQ_SRC_M_15_INT                                0xCF
+#define     V_008DFC_SQ_SRC_M_16_INT                                0xD0
+#define     V_008DFC_SQ_SRC_0_5                                     0xF0
+#define     V_008DFC_SQ_SRC_M_0_5                                   0xF1
+#define     V_008DFC_SQ_SRC_1                                       0xF2
+#define     V_008DFC_SQ_SRC_M_1                                     0xF3
+#define     V_008DFC_SQ_SRC_2                                       0xF4
+#define     V_008DFC_SQ_SRC_M_2                                     0xF5
+#define     V_008DFC_SQ_SRC_4                                       0xF6
+#define     V_008DFC_SQ_SRC_M_4                                     0xF7
+#define     V_008DFC_SQ_SRC_VCCZ                                    0xFB
+#define     V_008DFC_SQ_SRC_EXECZ                                   0xFC
+#define     V_008DFC_SQ_SRC_SCC                                     0xFD
+#define     V_008DFC_SQ_SRC_LDS_DIRECT                              0xFE
+#define R_008DFC_SQ_SOP2                                                0x008DFC
+#define   S_008DFC_SSRC0(x)                                           (((x) & 0xFF) << 0)
+#define   G_008DFC_SSRC0(x)                                           (((x) >> 0) & 0xFF)
+#define   C_008DFC_SSRC0                                              0xFFFFFF00
+#define     V_008DFC_SQ_SGPR                                        0x00
+/* CIK */
+#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
+#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
+/*     */
+#define     V_008DFC_SQ_VCC_LO                                      0x6A
+#define     V_008DFC_SQ_VCC_HI                                      0x6B
+#define     V_008DFC_SQ_TBA_LO                                      0x6C
+#define     V_008DFC_SQ_TBA_HI                                      0x6D
+#define     V_008DFC_SQ_TMA_LO                                      0x6E
+#define     V_008DFC_SQ_TMA_HI                                      0x6F
+#define     V_008DFC_SQ_TTMP0                                       0x70
+#define     V_008DFC_SQ_TTMP1                                       0x71
+#define     V_008DFC_SQ_TTMP2                                       0x72
+#define     V_008DFC_SQ_TTMP3                                       0x73
+#define     V_008DFC_SQ_TTMP4                                       0x74
+#define     V_008DFC_SQ_TTMP5                                       0x75
+#define     V_008DFC_SQ_TTMP6                                       0x76
+#define     V_008DFC_SQ_TTMP7                                       0x77
+#define     V_008DFC_SQ_TTMP8                                       0x78
+#define     V_008DFC_SQ_TTMP9                                       0x79
+#define     V_008DFC_SQ_TTMP10                                      0x7A
+#define     V_008DFC_SQ_TTMP11                                      0x7B
+#define     V_008DFC_SQ_M0                                          0x7C
+#define     V_008DFC_SQ_EXEC_LO                                     0x7E
+#define     V_008DFC_SQ_EXEC_HI                                     0x7F
+#define     V_008DFC_SQ_SRC_0                                       0x80
+#define     V_008DFC_SQ_SRC_1_INT                                   0x81
+#define     V_008DFC_SQ_SRC_2_INT                                   0x82
+#define     V_008DFC_SQ_SRC_3_INT                                   0x83
+#define     V_008DFC_SQ_SRC_4_INT                                   0x84
+#define     V_008DFC_SQ_SRC_5_INT                                   0x85
+#define     V_008DFC_SQ_SRC_6_INT                                   0x86
+#define     V_008DFC_SQ_SRC_7_INT                                   0x87
+#define     V_008DFC_SQ_SRC_8_INT                                   0x88
+#define     V_008DFC_SQ_SRC_9_INT                                   0x89
+#define     V_008DFC_SQ_SRC_10_INT                                  0x8A
+#define     V_008DFC_SQ_SRC_11_INT                                  0x8B
+#define     V_008DFC_SQ_SRC_12_INT                                  0x8C
+#define     V_008DFC_SQ_SRC_13_INT                                  0x8D
+#define     V_008DFC_SQ_SRC_14_INT                                  0x8E
+#define     V_008DFC_SQ_SRC_15_INT                                  0x8F
+#define     V_008DFC_SQ_SRC_16_INT                                  0x90
+#define     V_008DFC_SQ_SRC_17_INT                                  0x91
+#define     V_008DFC_SQ_SRC_18_INT                                  0x92
+#define     V_008DFC_SQ_SRC_19_INT                                  0x93
+#define     V_008DFC_SQ_SRC_20_INT                                  0x94
+#define     V_008DFC_SQ_SRC_21_INT                                  0x95
+#define     V_008DFC_SQ_SRC_22_INT                                  0x96
+#define     V_008DFC_SQ_SRC_23_INT                                  0x97
+#define     V_008DFC_SQ_SRC_24_INT                                  0x98
+#define     V_008DFC_SQ_SRC_25_INT                                  0x99
+#define     V_008DFC_SQ_SRC_26_INT                                  0x9A
+#define     V_008DFC_SQ_SRC_27_INT                                  0x9B
+#define     V_008DFC_SQ_SRC_28_INT                                  0x9C
+#define     V_008DFC_SQ_SRC_29_INT                                  0x9D
+#define     V_008DFC_SQ_SRC_30_INT                                  0x9E
+#define     V_008DFC_SQ_SRC_31_INT                                  0x9F
+#define     V_008DFC_SQ_SRC_32_INT                                  0xA0
+#define     V_008DFC_SQ_SRC_33_INT                                  0xA1
+#define     V_008DFC_SQ_SRC_34_INT                                  0xA2
+#define     V_008DFC_SQ_SRC_35_INT                                  0xA3
+#define     V_008DFC_SQ_SRC_36_INT                                  0xA4
+#define     V_008DFC_SQ_SRC_37_INT                                  0xA5
+#define     V_008DFC_SQ_SRC_38_INT                                  0xA6
+#define     V_008DFC_SQ_SRC_39_INT                                  0xA7
+#define     V_008DFC_SQ_SRC_40_INT                                  0xA8
+#define     V_008DFC_SQ_SRC_41_INT                                  0xA9
+#define     V_008DFC_SQ_SRC_42_INT                                  0xAA
+#define     V_008DFC_SQ_SRC_43_INT                                  0xAB
+#define     V_008DFC_SQ_SRC_44_INT                                  0xAC
+#define     V_008DFC_SQ_SRC_45_INT                                  0xAD
+#define     V_008DFC_SQ_SRC_46_INT                                  0xAE
+#define     V_008DFC_SQ_SRC_47_INT                                  0xAF
+#define     V_008DFC_SQ_SRC_48_INT                                  0xB0
+#define     V_008DFC_SQ_SRC_49_INT                                  0xB1
+#define     V_008DFC_SQ_SRC_50_INT                                  0xB2
+#define     V_008DFC_SQ_SRC_51_INT                                  0xB3
+#define     V_008DFC_SQ_SRC_52_INT                                  0xB4
+#define     V_008DFC_SQ_SRC_53_INT                                  0xB5
+#define     V_008DFC_SQ_SRC_54_INT                                  0xB6
+#define     V_008DFC_SQ_SRC_55_INT                                  0xB7
+#define     V_008DFC_SQ_SRC_56_INT                                  0xB8
+#define     V_008DFC_SQ_SRC_57_INT                                  0xB9
+#define     V_008DFC_SQ_SRC_58_INT                                  0xBA
+#define     V_008DFC_SQ_SRC_59_INT                                  0xBB
+#define     V_008DFC_SQ_SRC_60_INT                                  0xBC
+#define     V_008DFC_SQ_SRC_61_INT                                  0xBD
+#define     V_008DFC_SQ_SRC_62_INT                                  0xBE
+#define     V_008DFC_SQ_SRC_63_INT                                  0xBF
+#define     V_008DFC_SQ_SRC_64_INT                                  0xC0
+#define     V_008DFC_SQ_SRC_M_1_INT                                 0xC1
+#define     V_008DFC_SQ_SRC_M_2_INT                                 0xC2
+#define     V_008DFC_SQ_SRC_M_3_INT                                 0xC3
+#define     V_008DFC_SQ_SRC_M_4_INT                                 0xC4
+#define     V_008DFC_SQ_SRC_M_5_INT                                 0xC5
+#define     V_008DFC_SQ_SRC_M_6_INT                                 0xC6
+#define     V_008DFC_SQ_SRC_M_7_INT                                 0xC7
+#define     V_008DFC_SQ_SRC_M_8_INT                                 0xC8
+#define     V_008DFC_SQ_SRC_M_9_INT                                 0xC9
+#define     V_008DFC_SQ_SRC_M_10_INT                                0xCA
+#define     V_008DFC_SQ_SRC_M_11_INT                                0xCB
+#define     V_008DFC_SQ_SRC_M_12_INT                                0xCC
+#define     V_008DFC_SQ_SRC_M_13_INT                                0xCD
+#define     V_008DFC_SQ_SRC_M_14_INT                                0xCE
+#define     V_008DFC_SQ_SRC_M_15_INT                                0xCF
+#define     V_008DFC_SQ_SRC_M_16_INT                                0xD0
+#define     V_008DFC_SQ_SRC_0_5                                     0xF0
+#define     V_008DFC_SQ_SRC_M_0_5                                   0xF1
+#define     V_008DFC_SQ_SRC_1                                       0xF2
+#define     V_008DFC_SQ_SRC_M_1                                     0xF3
+#define     V_008DFC_SQ_SRC_2                                       0xF4
+#define     V_008DFC_SQ_SRC_M_2                                     0xF5
+#define     V_008DFC_SQ_SRC_4                                       0xF6
+#define     V_008DFC_SQ_SRC_M_4                                     0xF7
+#define     V_008DFC_SQ_SRC_VCCZ                                    0xFB
+#define     V_008DFC_SQ_SRC_EXECZ                                   0xFC
+#define     V_008DFC_SQ_SRC_SCC                                     0xFD
+#define     V_008DFC_SQ_SRC_LDS_DIRECT                              0xFE
+#define   S_008DFC_SSRC1(x)                                           (((x) & 0xFF) << 8)
+#define   G_008DFC_SSRC1(x)                                           (((x) >> 8) & 0xFF)
+#define   C_008DFC_SSRC1                                              0xFFFF00FF
+#define     V_008DFC_SQ_SGPR                                        0x00
+/* CIK */
+#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
+#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
+/*     */
+#define     V_008DFC_SQ_VCC_LO                                      0x6A
+#define     V_008DFC_SQ_VCC_HI                                      0x6B
+#define     V_008DFC_SQ_TBA_LO                                      0x6C
+#define     V_008DFC_SQ_TBA_HI                                      0x6D
+#define     V_008DFC_SQ_TMA_LO                                      0x6E
+#define     V_008DFC_SQ_TMA_HI                                      0x6F
+#define     V_008DFC_SQ_TTMP0                                       0x70
+#define     V_008DFC_SQ_TTMP1                                       0x71
+#define     V_008DFC_SQ_TTMP2                                       0x72
+#define     V_008DFC_SQ_TTMP3                                       0x73
+#define     V_008DFC_SQ_TTMP4                                       0x74
+#define     V_008DFC_SQ_TTMP5                                       0x75
+#define     V_008DFC_SQ_TTMP6                                       0x76
+#define     V_008DFC_SQ_TTMP7                                       0x77
+#define     V_008DFC_SQ_TTMP8                                       0x78
+#define     V_008DFC_SQ_TTMP9                                       0x79
+#define     V_008DFC_SQ_TTMP10                                      0x7A
+#define     V_008DFC_SQ_TTMP11                                      0x7B
+#define     V_008DFC_SQ_M0                                          0x7C
+#define     V_008DFC_SQ_EXEC_LO                                     0x7E
+#define     V_008DFC_SQ_EXEC_HI                                     0x7F
+#define     V_008DFC_SQ_SRC_0                                       0x80
+#define     V_008DFC_SQ_SRC_1_INT                                   0x81
+#define     V_008DFC_SQ_SRC_2_INT                                   0x82
+#define     V_008DFC_SQ_SRC_3_INT                                   0x83
+#define     V_008DFC_SQ_SRC_4_INT                                   0x84
+#define     V_008DFC_SQ_SRC_5_INT                                   0x85
+#define     V_008DFC_SQ_SRC_6_INT                                   0x86
+#define     V_008DFC_SQ_SRC_7_INT                                   0x87
+#define     V_008DFC_SQ_SRC_8_INT                                   0x88
+#define     V_008DFC_SQ_SRC_9_INT                                   0x89
+#define     V_008DFC_SQ_SRC_10_INT                                  0x8A
+#define     V_008DFC_SQ_SRC_11_INT                                  0x8B
+#define     V_008DFC_SQ_SRC_12_INT                                  0x8C
+#define     V_008DFC_SQ_SRC_13_INT                                  0x8D
+#define     V_008DFC_SQ_SRC_14_INT                                  0x8E
+#define     V_008DFC_SQ_SRC_15_INT                                  0x8F
+#define     V_008DFC_SQ_SRC_16_INT                                  0x90
+#define     V_008DFC_SQ_SRC_17_INT                                  0x91
+#define     V_008DFC_SQ_SRC_18_INT                                  0x92
+#define     V_008DFC_SQ_SRC_19_INT                                  0x93
+#define     V_008DFC_SQ_SRC_20_INT                                  0x94
+#define     V_008DFC_SQ_SRC_21_INT                                  0x95
+#define     V_008DFC_SQ_SRC_22_INT                                  0x96
+#define     V_008DFC_SQ_SRC_23_INT                                  0x97
+#define     V_008DFC_SQ_SRC_24_INT                                  0x98
+#define     V_008DFC_SQ_SRC_25_INT                                  0x99
+#define     V_008DFC_SQ_SRC_26_INT                                  0x9A
+#define     V_008DFC_SQ_SRC_27_INT                                  0x9B
+#define     V_008DFC_SQ_SRC_28_INT                                  0x9C
+#define     V_008DFC_SQ_SRC_29_INT                                  0x9D
+#define     V_008DFC_SQ_SRC_30_INT                                  0x9E
+#define     V_008DFC_SQ_SRC_31_INT                                  0x9F
+#define     V_008DFC_SQ_SRC_32_INT                                  0xA0
+#define     V_008DFC_SQ_SRC_33_INT                                  0xA1
+#define     V_008DFC_SQ_SRC_34_INT                                  0xA2
+#define     V_008DFC_SQ_SRC_35_INT                                  0xA3
+#define     V_008DFC_SQ_SRC_36_INT                                  0xA4
+#define     V_008DFC_SQ_SRC_37_INT                                  0xA5
+#define     V_008DFC_SQ_SRC_38_INT                                  0xA6
+#define     V_008DFC_SQ_SRC_39_INT                                  0xA7
+#define     V_008DFC_SQ_SRC_40_INT                                  0xA8
+#define     V_008DFC_SQ_SRC_41_INT                                  0xA9
+#define     V_008DFC_SQ_SRC_42_INT                                  0xAA
+#define     V_008DFC_SQ_SRC_43_INT                                  0xAB
+#define     V_008DFC_SQ_SRC_44_INT                                  0xAC
+#define     V_008DFC_SQ_SRC_45_INT                                  0xAD
+#define     V_008DFC_SQ_SRC_46_INT                                  0xAE
+#define     V_008DFC_SQ_SRC_47_INT                                  0xAF
+#define     V_008DFC_SQ_SRC_48_INT                                  0xB0
+#define     V_008DFC_SQ_SRC_49_INT                                  0xB1
+#define     V_008DFC_SQ_SRC_50_INT                                  0xB2
+#define     V_008DFC_SQ_SRC_51_INT                                  0xB3
+#define     V_008DFC_SQ_SRC_52_INT                                  0xB4
+#define     V_008DFC_SQ_SRC_53_INT                                  0xB5
+#define     V_008DFC_SQ_SRC_54_INT                                  0xB6
+#define     V_008DFC_SQ_SRC_55_INT                                  0xB7
+#define     V_008DFC_SQ_SRC_56_INT                                  0xB8
+#define     V_008DFC_SQ_SRC_57_INT                                  0xB9
+#define     V_008DFC_SQ_SRC_58_INT                                  0xBA
+#define     V_008DFC_SQ_SRC_59_INT                                  0xBB
+#define     V_008DFC_SQ_SRC_60_INT                                  0xBC
+#define     V_008DFC_SQ_SRC_61_INT                                  0xBD
+#define     V_008DFC_SQ_SRC_62_INT                                  0xBE
+#define     V_008DFC_SQ_SRC_63_INT                                  0xBF
+#define     V_008DFC_SQ_SRC_64_INT                                  0xC0
+#define     V_008DFC_SQ_SRC_M_1_INT                                 0xC1
+#define     V_008DFC_SQ_SRC_M_2_INT                                 0xC2
+#define     V_008DFC_SQ_SRC_M_3_INT                                 0xC3
+#define     V_008DFC_SQ_SRC_M_4_INT                                 0xC4
+#define     V_008DFC_SQ_SRC_M_5_INT                                 0xC5
+#define     V_008DFC_SQ_SRC_M_6_INT                                 0xC6
+#define     V_008DFC_SQ_SRC_M_7_INT                                 0xC7
+#define     V_008DFC_SQ_SRC_M_8_INT                                 0xC8
+#define     V_008DFC_SQ_SRC_M_9_INT                                 0xC9
+#define     V_008DFC_SQ_SRC_M_10_INT                                0xCA
+#define     V_008DFC_SQ_SRC_M_11_INT                                0xCB
+#define     V_008DFC_SQ_SRC_M_12_INT                                0xCC
+#define     V_008DFC_SQ_SRC_M_13_INT                                0xCD
+#define     V_008DFC_SQ_SRC_M_14_INT                                0xCE
+#define     V_008DFC_SQ_SRC_M_15_INT                                0xCF
+#define     V_008DFC_SQ_SRC_M_16_INT                                0xD0
+#define     V_008DFC_SQ_SRC_0_5                                     0xF0
+#define     V_008DFC_SQ_SRC_M_0_5                                   0xF1
+#define     V_008DFC_SQ_SRC_1                                       0xF2
+#define     V_008DFC_SQ_SRC_M_1                                     0xF3
+#define     V_008DFC_SQ_SRC_2                                       0xF4
+#define     V_008DFC_SQ_SRC_M_2                                     0xF5
+#define     V_008DFC_SQ_SRC_4                                       0xF6
+#define     V_008DFC_SQ_SRC_M_4                                     0xF7
+#define     V_008DFC_SQ_SRC_VCCZ                                    0xFB
+#define     V_008DFC_SQ_SRC_EXECZ                                   0xFC
+#define     V_008DFC_SQ_SRC_SCC                                     0xFD
+#define     V_008DFC_SQ_SRC_LDS_DIRECT                              0xFE
+#define   S_008DFC_SDST(x)                                            (((x) & 0x7F) << 16)
+#define   G_008DFC_SDST(x)                                            (((x) >> 16) & 0x7F)
+#define   C_008DFC_SDST                                               0xFF80FFFF
+#define     V_008DFC_SQ_SGPR                                        0x00
+/* CIK */
+#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
+#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
+/*     */
+#define     V_008DFC_SQ_VCC_LO                                      0x6A
+#define     V_008DFC_SQ_VCC_HI                                      0x6B
+#define     V_008DFC_SQ_TBA_LO                                      0x6C
+#define     V_008DFC_SQ_TBA_HI                                      0x6D
+#define     V_008DFC_SQ_TMA_LO                                      0x6E
+#define     V_008DFC_SQ_TMA_HI                                      0x6F
+#define     V_008DFC_SQ_TTMP0                                       0x70
+#define     V_008DFC_SQ_TTMP1                                       0x71
+#define     V_008DFC_SQ_TTMP2                                       0x72
+#define     V_008DFC_SQ_TTMP3                                       0x73
+#define     V_008DFC_SQ_TTMP4                                       0x74
+#define     V_008DFC_SQ_TTMP5                                       0x75
+#define     V_008DFC_SQ_TTMP6                                       0x76
+#define     V_008DFC_SQ_TTMP7                                       0x77
+#define     V_008DFC_SQ_TTMP8                                       0x78
+#define     V_008DFC_SQ_TTMP9                                       0x79
+#define     V_008DFC_SQ_TTMP10                                      0x7A
+#define     V_008DFC_SQ_TTMP11                                      0x7B
+#define     V_008DFC_SQ_M0                                          0x7C
+#define     V_008DFC_SQ_EXEC_LO                                     0x7E
+#define     V_008DFC_SQ_EXEC_HI                                     0x7F
+#define   S_008DFC_OP(x)                                              (((x) & 0x7F) << 23)
+#define   G_008DFC_OP(x)                                              (((x) >> 23) & 0x7F)
+#define   C_008DFC_OP                                                 0xC07FFFFF
+#define     V_008DFC_SQ_S_ADD_U32                                   0x00
+#define     V_008DFC_SQ_S_SUB_U32                                   0x01
+#define     V_008DFC_SQ_S_ADD_I32                                   0x02
+#define     V_008DFC_SQ_S_SUB_I32                                   0x03
+#define     V_008DFC_SQ_S_ADDC_U32                                  0x04
+#define     V_008DFC_SQ_S_SUBB_U32                                  0x05
+#define     V_008DFC_SQ_S_MIN_I32                                   0x06
+#define     V_008DFC_SQ_S_MIN_U32                                   0x07
+#define     V_008DFC_SQ_S_MAX_I32                                   0x08
+#define     V_008DFC_SQ_S_MAX_U32                                   0x09
+#define     V_008DFC_SQ_S_CSELECT_B32                               0x0A
+#define     V_008DFC_SQ_S_CSELECT_B64                               0x0B
+#define     V_008DFC_SQ_S_AND_B32                                   0x0E
+#define     V_008DFC_SQ_S_AND_B64                                   0x0F
+#define     V_008DFC_SQ_S_OR_B32                                    0x10
+#define     V_008DFC_SQ_S_OR_B64                                    0x11
+#define     V_008DFC_SQ_S_XOR_B32                                   0x12
+#define     V_008DFC_SQ_S_XOR_B64                                   0x13
+#define     V_008DFC_SQ_S_ANDN2_B32                                 0x14
+#define     V_008DFC_SQ_S_ANDN2_B64                                 0x15
+#define     V_008DFC_SQ_S_ORN2_B32                                  0x16
+#define     V_008DFC_SQ_S_ORN2_B64                                  0x17
+#define     V_008DFC_SQ_S_NAND_B32                                  0x18
+#define     V_008DFC_SQ_S_NAND_B64                                  0x19
+#define     V_008DFC_SQ_S_NOR_B32                                   0x1A
+#define     V_008DFC_SQ_S_NOR_B64                                   0x1B
+#define     V_008DFC_SQ_S_XNOR_B32                                  0x1C
+#define     V_008DFC_SQ_S_XNOR_B64                                  0x1D
+#define     V_008DFC_SQ_S_LSHL_B32                                  0x1E
+#define     V_008DFC_SQ_S_LSHL_B64                                  0x1F
+#define     V_008DFC_SQ_S_LSHR_B32                                  0x20
+#define     V_008DFC_SQ_S_LSHR_B64                                  0x21
+#define     V_008DFC_SQ_S_ASHR_I32                                  0x22
+#define     V_008DFC_SQ_S_ASHR_I64                                  0x23
+#define     V_008DFC_SQ_S_BFM_B32                                   0x24
+#define     V_008DFC_SQ_S_BFM_B64                                   0x25
+#define     V_008DFC_SQ_S_MUL_I32                                   0x26
+#define     V_008DFC_SQ_S_BFE_U32                                   0x27
+#define     V_008DFC_SQ_S_BFE_I32                                   0x28
+#define     V_008DFC_SQ_S_BFE_U64                                   0x29
+#define     V_008DFC_SQ_S_BFE_I64                                   0x2A
+#define     V_008DFC_SQ_S_CBRANCH_G_FORK                            0x2B
+#define     V_008DFC_SQ_S_ABSDIFF_I32                               0x2C
+#define   S_008DFC_ENCODING(x)                                        (((x) & 0x03) << 30)
+#define   G_008DFC_ENCODING(x)                                        (((x) >> 30) & 0x03)
+#define   C_008DFC_ENCODING                                           0x3FFFFFFF
+#define     V_008DFC_SQ_ENC_SOP2_FIELD                              0x02
+#define R_008DFC_SQ_SOPK                                                0x008DFC
+#define   S_008DFC_SIMM16(x)                                          (((x) & 0xFFFF) << 0)
+#define   G_008DFC_SIMM16(x)                                          (((x) >> 0) & 0xFFFF)
+#define   C_008DFC_SIMM16                                             0xFFFF0000
+#define   S_008DFC_SDST(x)                                            (((x) & 0x7F) << 16)
+#define   G_008DFC_SDST(x)                                            (((x) >> 16) & 0x7F)
+#define   C_008DFC_SDST                                               0xFF80FFFF
+#define     V_008DFC_SQ_SGPR                                        0x00
+/* CIK */
+#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
+#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
+/*     */
+#define     V_008DFC_SQ_VCC_LO                                      0x6A
+#define     V_008DFC_SQ_VCC_HI                                      0x6B
+#define     V_008DFC_SQ_TBA_LO                                      0x6C
+#define     V_008DFC_SQ_TBA_HI                                      0x6D
+#define     V_008DFC_SQ_TMA_LO                                      0x6E
+#define     V_008DFC_SQ_TMA_HI                                      0x6F
+#define     V_008DFC_SQ_TTMP0                                       0x70
+#define     V_008DFC_SQ_TTMP1                                       0x71
+#define     V_008DFC_SQ_TTMP2                                       0x72
+#define     V_008DFC_SQ_TTMP3                                       0x73
+#define     V_008DFC_SQ_TTMP4                                       0x74
+#define     V_008DFC_SQ_TTMP5                                       0x75
+#define     V_008DFC_SQ_TTMP6                                       0x76
+#define     V_008DFC_SQ_TTMP7                                       0x77
+#define     V_008DFC_SQ_TTMP8                                       0x78
+#define     V_008DFC_SQ_TTMP9                                       0x79
+#define     V_008DFC_SQ_TTMP10                                      0x7A
+#define     V_008DFC_SQ_TTMP11                                      0x7B
+#define     V_008DFC_SQ_M0                                          0x7C
+#define     V_008DFC_SQ_EXEC_LO                                     0x7E
+#define     V_008DFC_SQ_EXEC_HI                                     0x7F
+#define   S_008DFC_OP(x)                                              (((x) & 0x1F) << 23)
+#define   G_008DFC_OP(x)                                              (((x) >> 23) & 0x1F)
+#define   C_008DFC_OP                                                 0xF07FFFFF
+#define     V_008DFC_SQ_S_MOVK_I32                                  0x00
+#define     V_008DFC_SQ_S_CMOVK_I32                                 0x02
+#define     V_008DFC_SQ_S_CMPK_EQ_I32                               0x03
+#define     V_008DFC_SQ_S_CMPK_LG_I32                               0x04
+#define     V_008DFC_SQ_S_CMPK_GT_I32                               0x05
+#define     V_008DFC_SQ_S_CMPK_GE_I32                               0x06
+#define     V_008DFC_SQ_S_CMPK_LT_I32                               0x07
+#define     V_008DFC_SQ_S_CMPK_LE_I32                               0x08
+#define     V_008DFC_SQ_S_CMPK_EQ_U32                               0x09
+#define     V_008DFC_SQ_S_CMPK_LG_U32                               0x0A
+#define     V_008DFC_SQ_S_CMPK_GT_U32                               0x0B
+#define     V_008DFC_SQ_S_CMPK_GE_U32                               0x0C
+#define     V_008DFC_SQ_S_CMPK_LT_U32                               0x0D
+#define     V_008DFC_SQ_S_CMPK_LE_U32                               0x0E
+#define     V_008DFC_SQ_S_ADDK_I32                                  0x0F
+#define     V_008DFC_SQ_S_MULK_I32                                  0x10
+#define     V_008DFC_SQ_S_CBRANCH_I_FORK                            0x11
+#define     V_008DFC_SQ_S_GETREG_B32                                0x12
+#define     V_008DFC_SQ_S_SETREG_B32                                0x13
+#define     V_008DFC_SQ_S_GETREG_REGRD_B32                          0x14
+#define     V_008DFC_SQ_S_SETREG_IMM32_B32                          0x15
+#define   S_008DFC_ENCODING(x)                                        (((x) & 0x0F) << 28)
+#define   G_008DFC_ENCODING(x)                                        (((x) >> 28) & 0x0F)
+#define   C_008DFC_ENCODING                                           0x0FFFFFFF
+#define     V_008DFC_SQ_ENC_SOPK_FIELD                              0x0B
+#define R_008DFC_SQ_VOP3_0                                              0x008DFC
+#define   S_008DFC_VDST(x)                                            (((x) & 0xFF) << 0)
+#define   G_008DFC_VDST(x)                                            (((x) >> 0) & 0xFF)
+#define   C_008DFC_VDST                                               0xFFFFFF00
+#define     V_008DFC_SQ_VGPR                                        0x00
+#define   S_008DFC_ABS(x)                                             (((x) & 0x07) << 8)
+#define   G_008DFC_ABS(x)                                             (((x) >> 8) & 0x07)
+#define   C_008DFC_ABS                                                0xFFFFF8FF
+#define   S_008DFC_CLAMP(x)                                           (((x) & 0x1) << 11)
+#define   G_008DFC_CLAMP(x)                                           (((x) >> 11) & 0x1)
+#define   C_008DFC_CLAMP                                              0xFFFFF7FF
+#define   S_008DFC_OP(x)                                              (((x) & 0x1FF) << 17)
+#define   G_008DFC_OP(x)                                              (((x) >> 17) & 0x1FF)
+#define   C_008DFC_OP                                                 0xFC01FFFF
+#define     V_008DFC_SQ_V_OPC_OFFSET                                0x00
+#define     V_008DFC_SQ_V_OP2_OFFSET                                0x100
+#define     V_008DFC_SQ_V_MAD_LEGACY_F32                            0x140
+#define     V_008DFC_SQ_V_MAD_F32                                   0x141
+#define     V_008DFC_SQ_V_MAD_I32_I24                               0x142
+#define     V_008DFC_SQ_V_MAD_U32_U24                               0x143
+#define     V_008DFC_SQ_V_CUBEID_F32                                0x144
+#define     V_008DFC_SQ_V_CUBESC_F32                                0x145
+#define     V_008DFC_SQ_V_CUBETC_F32                                0x146
+#define     V_008DFC_SQ_V_CUBEMA_F32                                0x147
+#define     V_008DFC_SQ_V_BFE_U32                                   0x148
+#define     V_008DFC_SQ_V_BFE_I32                                   0x149
+#define     V_008DFC_SQ_V_BFI_B32                                   0x14A
+#define     V_008DFC_SQ_V_FMA_F32                                   0x14B
+#define     V_008DFC_SQ_V_FMA_F64                                   0x14C
+#define     V_008DFC_SQ_V_LERP_U8                                   0x14D
+#define     V_008DFC_SQ_V_ALIGNBIT_B32                              0x14E
+#define     V_008DFC_SQ_V_ALIGNBYTE_B32                             0x14F
+#define     V_008DFC_SQ_V_MULLIT_F32                                0x150
+#define     V_008DFC_SQ_V_MIN3_F32                                  0x151
+#define     V_008DFC_SQ_V_MIN3_I32                                  0x152
+#define     V_008DFC_SQ_V_MIN3_U32                                  0x153
+#define     V_008DFC_SQ_V_MAX3_F32                                  0x154
+#define     V_008DFC_SQ_V_MAX3_I32                                  0x155
+#define     V_008DFC_SQ_V_MAX3_U32                                  0x156
+#define     V_008DFC_SQ_V_MED3_F32                                  0x157
+#define     V_008DFC_SQ_V_MED3_I32                                  0x158
+#define     V_008DFC_SQ_V_MED3_U32                                  0x159
+#define     V_008DFC_SQ_V_SAD_U8                                    0x15A
+#define     V_008DFC_SQ_V_SAD_HI_U8                                 0x15B
+#define     V_008DFC_SQ_V_SAD_U16                                   0x15C
+#define     V_008DFC_SQ_V_SAD_U32                                   0x15D
+#define     V_008DFC_SQ_V_CVT_PK_U8_F32                             0x15E
+#define     V_008DFC_SQ_V_DIV_FIXUP_F32                             0x15F
+#define     V_008DFC_SQ_V_DIV_FIXUP_F64                             0x160
+#define     V_008DFC_SQ_V_LSHL_B64                                  0x161
+#define     V_008DFC_SQ_V_LSHR_B64                                  0x162
+#define     V_008DFC_SQ_V_ASHR_I64                                  0x163
+#define     V_008DFC_SQ_V_ADD_F64                                   0x164
+#define     V_008DFC_SQ_V_MUL_F64                                   0x165
+#define     V_008DFC_SQ_V_MIN_F64                                   0x166
+#define     V_008DFC_SQ_V_MAX_F64                                   0x167
+#define     V_008DFC_SQ_V_LDEXP_F64                                 0x168
+#define     V_008DFC_SQ_V_MUL_LO_U32                                0x169
+#define     V_008DFC_SQ_V_MUL_HI_U32                                0x16A
+#define     V_008DFC_SQ_V_MUL_LO_I32                                0x16B
+#define     V_008DFC_SQ_V_MUL_HI_I32                                0x16C
+#define     V_008DFC_SQ_V_DIV_SCALE_F32                             0x16D
+#define     V_008DFC_SQ_V_DIV_SCALE_F64                             0x16E
+#define     V_008DFC_SQ_V_DIV_FMAS_F32                              0x16F
+#define     V_008DFC_SQ_V_DIV_FMAS_F64                              0x170
+#define     V_008DFC_SQ_V_MSAD_U8                                   0x171
+#define     V_008DFC_SQ_V_QSAD_U8                                   0x172
+#define     V_008DFC_SQ_V_MQSAD_U8                                  0x173
+#define     V_008DFC_SQ_V_TRIG_PREOP_F64                            0x174
+/* CIK */
+#define     V_008DFC_SQ_V_MQSAD_U32_U8                              0x175
+#define     V_008DFC_SQ_V_MAD_U64_U32                               0x176
+#define     V_008DFC_SQ_V_MAD_I64_I32                               0x177
+/*     */
+#define     V_008DFC_SQ_V_OP1_OFFSET                                0x180
+#define   S_008DFC_ENCODING(x)                                        (((x) & 0x3F) << 26)
+#define   G_008DFC_ENCODING(x)                                        (((x) >> 26) & 0x3F)
+#define   C_008DFC_ENCODING                                           0x03FFFFFF
+#define     V_008DFC_SQ_ENC_VOP3_FIELD                              0x34
+#define R_008DFC_SQ_VOP2                                                0x008DFC
+#define   S_008DFC_SRC0(x)                                            (((x) & 0x1FF) << 0)
+#define   G_008DFC_SRC0(x)                                            (((x) >> 0) & 0x1FF)
+#define   C_008DFC_SRC0                                               0xFFFFFE00
+#define     V_008DFC_SQ_SGPR                                        0x00
+/* CIK */
+#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
+#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
+/*     */
+#define     V_008DFC_SQ_VCC_LO                                      0x6A
+#define     V_008DFC_SQ_VCC_HI                                      0x6B
+#define     V_008DFC_SQ_TBA_LO                                      0x6C
+#define     V_008DFC_SQ_TBA_HI                                      0x6D
+#define     V_008DFC_SQ_TMA_LO                                      0x6E
+#define     V_008DFC_SQ_TMA_HI                                      0x6F
+#define     V_008DFC_SQ_TTMP0                                       0x70
+#define     V_008DFC_SQ_TTMP1                                       0x71
+#define     V_008DFC_SQ_TTMP2                                       0x72
+#define     V_008DFC_SQ_TTMP3                                       0x73
+#define     V_008DFC_SQ_TTMP4                                       0x74
+#define     V_008DFC_SQ_TTMP5                                       0x75
+#define     V_008DFC_SQ_TTMP6                                       0x76
+#define     V_008DFC_SQ_TTMP7                                       0x77
+#define     V_008DFC_SQ_TTMP8                                       0x78
+#define     V_008DFC_SQ_TTMP9                                       0x79
+#define     V_008DFC_SQ_TTMP10                                      0x7A
+#define     V_008DFC_SQ_TTMP11                                      0x7B
+#define     V_008DFC_SQ_M0                                          0x7C
+#define     V_008DFC_SQ_EXEC_LO                                     0x7E
+#define     V_008DFC_SQ_EXEC_HI                                     0x7F
+#define     V_008DFC_SQ_SRC_0                                       0x80
+#define     V_008DFC_SQ_SRC_1_INT                                   0x81
+#define     V_008DFC_SQ_SRC_2_INT                                   0x82
+#define     V_008DFC_SQ_SRC_3_INT                                   0x83
+#define     V_008DFC_SQ_SRC_4_INT                                   0x84
+#define     V_008DFC_SQ_SRC_5_INT                                   0x85
+#define     V_008DFC_SQ_SRC_6_INT                                   0x86
+#define     V_008DFC_SQ_SRC_7_INT                                   0x87
+#define     V_008DFC_SQ_SRC_8_INT                                   0x88
+#define     V_008DFC_SQ_SRC_9_INT                                   0x89
+#define     V_008DFC_SQ_SRC_10_INT                                  0x8A
+#define     V_008DFC_SQ_SRC_11_INT                                  0x8B
+#define     V_008DFC_SQ_SRC_12_INT                                  0x8C
+#define     V_008DFC_SQ_SRC_13_INT                                  0x8D
+#define     V_008DFC_SQ_SRC_14_INT                                  0x8E
+#define     V_008DFC_SQ_SRC_15_INT                                  0x8F
+#define     V_008DFC_SQ_SRC_16_INT                                  0x90
+#define     V_008DFC_SQ_SRC_17_INT                                  0x91
+#define     V_008DFC_SQ_SRC_18_INT                                  0x92
+#define     V_008DFC_SQ_SRC_19_INT                                  0x93
+#define     V_008DFC_SQ_SRC_20_INT                                  0x94
+#define     V_008DFC_SQ_SRC_21_INT                                  0x95
+#define     V_008DFC_SQ_SRC_22_INT                                  0x96
+#define     V_008DFC_SQ_SRC_23_INT                                  0x97
+#define     V_008DFC_SQ_SRC_24_INT                                  0x98
+#define     V_008DFC_SQ_SRC_25_INT                                  0x99
+#define     V_008DFC_SQ_SRC_26_INT                                  0x9A
+#define     V_008DFC_SQ_SRC_27_INT                                  0x9B
+#define     V_008DFC_SQ_SRC_28_INT                                  0x9C
+#define     V_008DFC_SQ_SRC_29_INT                                  0x9D
+#define     V_008DFC_SQ_SRC_30_INT                                  0x9E
+#define     V_008DFC_SQ_SRC_31_INT                                  0x9F
+#define     V_008DFC_SQ_SRC_32_INT                                  0xA0
+#define     V_008DFC_SQ_SRC_33_INT                                  0xA1
+#define     V_008DFC_SQ_SRC_34_INT                                  0xA2
+#define     V_008DFC_SQ_SRC_35_INT                                  0xA3
+#define     V_008DFC_SQ_SRC_36_INT                                  0xA4
+#define     V_008DFC_SQ_SRC_37_INT                                  0xA5
+#define     V_008DFC_SQ_SRC_38_INT                                  0xA6
+#define     V_008DFC_SQ_SRC_39_INT                                  0xA7
+#define     V_008DFC_SQ_SRC_40_INT                                  0xA8
+#define     V_008DFC_SQ_SRC_41_INT                                  0xA9
+#define     V_008DFC_SQ_SRC_42_INT                                  0xAA
+#define     V_008DFC_SQ_SRC_43_INT                                  0xAB
+#define     V_008DFC_SQ_SRC_44_INT                                  0xAC
+#define     V_008DFC_SQ_SRC_45_INT                                  0xAD
+#define     V_008DFC_SQ_SRC_46_INT                                  0xAE
+#define     V_008DFC_SQ_SRC_47_INT                                  0xAF
+#define     V_008DFC_SQ_SRC_48_INT                                  0xB0
+#define     V_008DFC_SQ_SRC_49_INT                                  0xB1
+#define     V_008DFC_SQ_SRC_50_INT                                  0xB2
+#define     V_008DFC_SQ_SRC_51_INT                                  0xB3
+#define     V_008DFC_SQ_SRC_52_INT                                  0xB4
+#define     V_008DFC_SQ_SRC_53_INT                                  0xB5
+#define     V_008DFC_SQ_SRC_54_INT                                  0xB6
+#define     V_008DFC_SQ_SRC_55_INT                                  0xB7
+#define     V_008DFC_SQ_SRC_56_INT                                  0xB8
+#define     V_008DFC_SQ_SRC_57_INT                                  0xB9
+#define     V_008DFC_SQ_SRC_58_INT                                  0xBA
+#define     V_008DFC_SQ_SRC_59_INT                                  0xBB
+#define     V_008DFC_SQ_SRC_60_INT                                  0xBC
+#define     V_008DFC_SQ_SRC_61_INT                                  0xBD
+#define     V_008DFC_SQ_SRC_62_INT                                  0xBE
+#define     V_008DFC_SQ_SRC_63_INT                                  0xBF
+#define     V_008DFC_SQ_SRC_64_INT                                  0xC0
+#define     V_008DFC_SQ_SRC_M_1_INT                                 0xC1
+#define     V_008DFC_SQ_SRC_M_2_INT                                 0xC2
+#define     V_008DFC_SQ_SRC_M_3_INT                                 0xC3
+#define     V_008DFC_SQ_SRC_M_4_INT                                 0xC4
+#define     V_008DFC_SQ_SRC_M_5_INT                                 0xC5
+#define     V_008DFC_SQ_SRC_M_6_INT                                 0xC6
+#define     V_008DFC_SQ_SRC_M_7_INT                                 0xC7
+#define     V_008DFC_SQ_SRC_M_8_INT                                 0xC8
+#define     V_008DFC_SQ_SRC_M_9_INT                                 0xC9
+#define     V_008DFC_SQ_SRC_M_10_INT                                0xCA
+#define     V_008DFC_SQ_SRC_M_11_INT                                0xCB
+#define     V_008DFC_SQ_SRC_M_12_INT                                0xCC
+#define     V_008DFC_SQ_SRC_M_13_INT                                0xCD
+#define     V_008DFC_SQ_SRC_M_14_INT                                0xCE
+#define     V_008DFC_SQ_SRC_M_15_INT                                0xCF
+#define     V_008DFC_SQ_SRC_M_16_INT                                0xD0
+#define     V_008DFC_SQ_SRC_0_5                                     0xF0
+#define     V_008DFC_SQ_SRC_M_0_5                                   0xF1
+#define     V_008DFC_SQ_SRC_1                                       0xF2
+#define     V_008DFC_SQ_SRC_M_1                                     0xF3
+#define     V_008DFC_SQ_SRC_2                                       0xF4
+#define     V_008DFC_SQ_SRC_M_2                                     0xF5
+#define     V_008DFC_SQ_SRC_4                                       0xF6
+#define     V_008DFC_SQ_SRC_M_4                                     0xF7
+#define     V_008DFC_SQ_SRC_VCCZ                                    0xFB
+#define     V_008DFC_SQ_SRC_EXECZ                                   0xFC
+#define     V_008DFC_SQ_SRC_SCC                                     0xFD
+#define     V_008DFC_SQ_SRC_LDS_DIRECT                              0xFE
+#define     V_008DFC_SQ_SRC_VGPR                                    0x100
+#define   S_008DFC_VSRC1(x)                                           (((x) & 0xFF) << 9)
+#define   G_008DFC_VSRC1(x)                                           (((x) >> 9) & 0xFF)
+#define   C_008DFC_VSRC1                                              0xFFFE01FF
+#define     V_008DFC_SQ_VGPR                                        0x00
+#define   S_008DFC_VDST(x)                                            (((x) & 0xFF) << 17)
+#define   G_008DFC_VDST(x)                                            (((x) >> 17) & 0xFF)
+#define   C_008DFC_VDST                                               0xFE01FFFF
+#define     V_008DFC_SQ_VGPR                                        0x00
+#define   S_008DFC_OP(x)                                              (((x) & 0x3F) << 25)
+#define   G_008DFC_OP(x)                                              (((x) >> 25) & 0x3F)
+#define   C_008DFC_OP                                                 0x81FFFFFF
+#define     V_008DFC_SQ_V_CNDMASK_B32                               0x00
+#define     V_008DFC_SQ_V_READLANE_B32                              0x01
+#define     V_008DFC_SQ_V_WRITELANE_B32                             0x02
+#define     V_008DFC_SQ_V_ADD_F32                                   0x03
+#define     V_008DFC_SQ_V_SUB_F32                                   0x04
+#define     V_008DFC_SQ_V_SUBREV_F32                                0x05
+#define     V_008DFC_SQ_V_MAC_LEGACY_F32                            0x06
+#define     V_008DFC_SQ_V_MUL_LEGACY_F32                            0x07
+#define     V_008DFC_SQ_V_MUL_F32                                   0x08
+#define     V_008DFC_SQ_V_MUL_I32_I24                               0x09
+#define     V_008DFC_SQ_V_MUL_HI_I32_I24                            0x0A
+#define     V_008DFC_SQ_V_MUL_U32_U24                               0x0B
+#define     V_008DFC_SQ_V_MUL_HI_U32_U24                            0x0C
+#define     V_008DFC_SQ_V_MIN_LEGACY_F32                            0x0D
+#define     V_008DFC_SQ_V_MAX_LEGACY_F32                            0x0E
+#define     V_008DFC_SQ_V_MIN_F32                                   0x0F
+#define     V_008DFC_SQ_V_MAX_F32                                   0x10
+#define     V_008DFC_SQ_V_MIN_I32                                   0x11
+#define     V_008DFC_SQ_V_MAX_I32                                   0x12
+#define     V_008DFC_SQ_V_MIN_U32                                   0x13
+#define     V_008DFC_SQ_V_MAX_U32                                   0x14
+#define     V_008DFC_SQ_V_LSHR_B32                                  0x15
+#define     V_008DFC_SQ_V_LSHRREV_B32                               0x16
+#define     V_008DFC_SQ_V_ASHR_I32                                  0x17
+#define     V_008DFC_SQ_V_ASHRREV_I32                               0x18
+#define     V_008DFC_SQ_V_LSHL_B32                                  0x19
+#define     V_008DFC_SQ_V_LSHLREV_B32                               0x1A
+#define     V_008DFC_SQ_V_AND_B32                                   0x1B
+#define     V_008DFC_SQ_V_OR_B32                                    0x1C
+#define     V_008DFC_SQ_V_XOR_B32                                   0x1D
+#define     V_008DFC_SQ_V_BFM_B32                                   0x1E
+#define     V_008DFC_SQ_V_MAC_F32                                   0x1F
+#define     V_008DFC_SQ_V_MADMK_F32                                 0x20
+#define     V_008DFC_SQ_V_MADAK_F32                                 0x21
+#define     V_008DFC_SQ_V_BCNT_U32_B32                              0x22
+#define     V_008DFC_SQ_V_MBCNT_LO_U32_B32                          0x23
+#define     V_008DFC_SQ_V_MBCNT_HI_U32_B32                          0x24
+#define     V_008DFC_SQ_V_ADD_I32                                   0x25
+#define     V_008DFC_SQ_V_SUB_I32                                   0x26
+#define     V_008DFC_SQ_V_SUBREV_I32                                0x27
+#define     V_008DFC_SQ_V_ADDC_U32                                  0x28
+#define     V_008DFC_SQ_V_SUBB_U32                                  0x29
+#define     V_008DFC_SQ_V_SUBBREV_U32                               0x2A
+#define     V_008DFC_SQ_V_LDEXP_F32                                 0x2B
+#define     V_008DFC_SQ_V_CVT_PKACCUM_U8_F32                        0x2C
+#define     V_008DFC_SQ_V_CVT_PKNORM_I16_F32                        0x2D
+#define     V_008DFC_SQ_V_CVT_PKNORM_U16_F32                        0x2E
+#define     V_008DFC_SQ_V_CVT_PKRTZ_F16_F32                         0x2F
+#define     V_008DFC_SQ_V_CVT_PK_U16_U32                            0x30
+#define     V_008DFC_SQ_V_CVT_PK_I16_I32                            0x31
+#define   S_008DFC_ENCODING(x)                                        (((x) & 0x1) << 31)
+#define   G_008DFC_ENCODING(x)                                        (((x) >> 31) & 0x1)
+#define   C_008DFC_ENCODING                                           0x7FFFFFFF
+#define R_008DFC_SQ_VOP3_0_SDST_ENC                                     0x008DFC
+#define   S_008DFC_VDST(x)                                            (((x) & 0xFF) << 0)
+#define   G_008DFC_VDST(x)                                            (((x) >> 0) & 0xFF)
+#define   C_008DFC_VDST                                               0xFFFFFF00
+#define     V_008DFC_SQ_VGPR                                        0x00
+#define   S_008DFC_SDST(x)                                            (((x) & 0x7F) << 8)
+#define   G_008DFC_SDST(x)                                            (((x) >> 8) & 0x7F)
+#define   C_008DFC_SDST                                               0xFFFF80FF
+#define     V_008DFC_SQ_SGPR                                        0x00
+/* CIK */
+#define     V_008DFC_SQ_FLAT_SCRATCH_LO                             0x68
+#define     V_008DFC_SQ_FLAT_SCRATCH_HI                             0x69
+/*     */
+#define     V_008DFC_SQ_VCC_LO                                      0x6A
+#define     V_008DFC_SQ_VCC_HI                                      0x6B
+#define     V_008DFC_SQ_TBA_LO                                      0x6C
+#define     V_008DFC_SQ_TBA_HI                                      0x6D
+#define     V_008DFC_SQ_TMA_LO                                      0x6E
+#define     V_008DFC_SQ_TMA_HI                                      0x6F
+#define     V_008DFC_SQ_TTMP0                                       0x70
+#define     V_008DFC_SQ_TTMP1                                       0x71
+#define     V_008DFC_SQ_TTMP2                                       0x72
+#define     V_008DFC_SQ_TTMP3                                       0x73
+#define     V_008DFC_SQ_TTMP4                                       0x74
+#define     V_008DFC_SQ_TTMP5                                       0x75
+#define     V_008DFC_SQ_TTMP6                                       0x76
+#define     V_008DFC_SQ_TTMP7                                       0x77
+#define     V_008DFC_SQ_TTMP8                                       0x78
+#define     V_008DFC_SQ_TTMP9                                       0x79
+#define     V_008DFC_SQ_TTMP10                                      0x7A
+#define     V_008DFC_SQ_TTMP11                                      0x7B
+#define   S_008DFC_OP(x)                                              (((x) & 0x1FF) << 17)
+#define   G_008DFC_OP(x)                                              (((x) >> 17) & 0x1FF)
+#define   C_008DFC_OP                                                 0xFC01FFFF
+#define     V_008DFC_SQ_V_OPC_OFFSET                                0x00
+#define     V_008DFC_SQ_V_OP2_OFFSET                                0x100
+#define     V_008DFC_SQ_V_MAD_LEGACY_F32                            0x140
+#define     V_008DFC_SQ_V_MAD_F32                                   0x141
+#define     V_008DFC_SQ_V_MAD_I32_I24                               0x142
+#define     V_008DFC_SQ_V_MAD_U32_U24                               0x143
+#define     V_008DFC_SQ_V_CUBEID_F32                                0x144
+#define     V_008DFC_SQ_V_CUBESC_F32                                0x145
+#define     V_008DFC_SQ_V_CUBETC_F32                                0x146
+#define     V_008DFC_SQ_V_CUBEMA_F32                                0x147
+#define     V_008DFC_SQ_V_BFE_U32                                   0x148
+#define     V_008DFC_SQ_V_BFE_I32                                   0x149
+#define     V_008DFC_SQ_V_BFI_B32                                   0x14A
+#define     V_008DFC_SQ_V_FMA_F32                                   0x14B
+#define     V_008DFC_SQ_V_FMA_F64                                   0x14C
+#define     V_008DFC_SQ_V_LERP_U8                                   0x14D
+#define     V_008DFC_SQ_V_ALIGNBIT_B32                              0x14E
+#define     V_008DFC_SQ_V_ALIGNBYTE_B32                             0x14F
+#define     V_008DFC_SQ_V_MULLIT_F32                                0x150
+#define     V_008DFC_SQ_V_MIN3_F32                                  0x151
+#define     V_008DFC_SQ_V_MIN3_I32                                  0x152
+#define     V_008DFC_SQ_V_MIN3_U32                                  0x153
+#define     V_008DFC_SQ_V_MAX3_F32                                  0x154
+#define     V_008DFC_SQ_V_MAX3_I32                                  0x155
+#define     V_008DFC_SQ_V_MAX3_U32                                  0x156
+#define     V_008DFC_SQ_V_MED3_F32                                  0x157
+#define     V_008DFC_SQ_V_MED3_I32                                  0x158
+#define     V_008DFC_SQ_V_MED3_U32                                  0x159
+#define     V_008DFC_SQ_V_SAD_U8                                    0x15A
+#define     V_008DFC_SQ_V_SAD_HI_U8                                 0x15B
+#define     V_008DFC_SQ_V_SAD_U16                                   0x15C
+#define     V_008DFC_SQ_V_SAD_U32                                   0x15D
+#define     V_008DFC_SQ_V_CVT_PK_U8_F32                             0x15E
+#define     V_008DFC_SQ_V_DIV_FIXUP_F32                             0x15F
+#define     V_008DFC_SQ_V_DIV_FIXUP_F64                             0x160
+#define     V_008DFC_SQ_V_LSHL_B64                                  0x161
+#define     V_008DFC_SQ_V_LSHR_B64                                  0x162
+#define     V_008DFC_SQ_V_ASHR_I64                                  0x163
+#define     V_008DFC_SQ_V_ADD_F64                                   0x164
+#define     V_008DFC_SQ_V_MUL_F64                                   0x165
+#define     V_008DFC_SQ_V_MIN_F64                                   0x166
+#define     V_008DFC_SQ_V_MAX_F64                                   0x167
+#define     V_008DFC_SQ_V_LDEXP_F64                                 0x168
+#define     V_008DFC_SQ_V_MUL_LO_U32                                0x169
+#define     V_008DFC_SQ_V_MUL_HI_U32                                0x16A
+#define     V_008DFC_SQ_V_MUL_LO_I32                                0x16B
+#define     V_008DFC_SQ_V_MUL_HI_I32                                0x16C
+#define     V_008DFC_SQ_V_DIV_SCALE_F32                             0x16D
+#define     V_008DFC_SQ_V_DIV_SCALE_F64                             0x16E
+#define     V_008DFC_SQ_V_DIV_FMAS_F32                              0x16F
+#define     V_008DFC_SQ_V_DIV_FMAS_F64                              0x170
+#define     V_008DFC_SQ_V_MSAD_U8                                   0x171
+#define     V_008DFC_SQ_V_QSAD_U8                                   0x172
+#define     V_008DFC_SQ_V_MQSAD_U8                                  0x173
+#define     V_008DFC_SQ_V_TRIG_PREOP_F64                            0x174
+/* CIK */
+#define     V_008DFC_SQ_V_MQSAD_U32_U8                              0x175
+#define     V_008DFC_SQ_V_MAD_U64_U32                               0x176
+#define     V_008DFC_SQ_V_MAD_I64_I32                               0x177
+/*     */
+#define     V_008DFC_SQ_V_OP1_OFFSET                                0x180
+#define   S_008DFC_ENCODING(x)                                        (((x) & 0x3F) << 26)
+#define   G_008DFC_ENCODING(x)                                        (((x) >> 26) & 0x3F)
+#define   C_008DFC_ENCODING                                           0x03FFFFFF
+#define     V_008DFC_SQ_ENC_VOP3_FIELD                              0x34
+#define R_008DFC_SQ_MUBUF_0                                             0x008DFC
+#define   S_008DFC_OFFSET(x)                                          (((x) & 0xFFF) << 0)
+#define   G_008DFC_OFFSET(x)                                          (((x) >> 0) & 0xFFF)
+#define   C_008DFC_OFFSET                                             0xFFFFF000
+#define   S_008DFC_OFFEN(x)                                           (((x) & 0x1) << 12)
+#define   G_008DFC_OFFEN(x)                                           (((x) >> 12) & 0x1)
+#define   C_008DFC_OFFEN                                              0xFFFFEFFF
+#define   S_008DFC_IDXEN(x)                                           (((x) & 0x1) << 13)
+#define   G_008DFC_IDXEN(x)                                           (((x) >> 13) & 0x1)
+#define   C_008DFC_IDXEN                                              0xFFFFDFFF
+#define   S_008DFC_GLC(x)                                             (((x) & 0x1) << 14)
+#define   G_008DFC_GLC(x)                                             (((x) >> 14) & 0x1)
+#define   C_008DFC_GLC                                                0xFFFFBFFF
+#define   S_008DFC_ADDR64(x)                                          (((x) & 0x1) << 15)
+#define   G_008DFC_ADDR64(x)                                          (((x) >> 15) & 0x1)
+#define   C_008DFC_ADDR64                                             0xFFFF7FFF
+#define   S_008DFC_LDS(x)                                             (((x) & 0x1) << 16)
+#define   G_008DFC_LDS(x)                                             (((x) >> 16) & 0x1)
+#define   C_008DFC_LDS                                                0xFFFEFFFF
+#define   S_008DFC_OP(x)                                              (((x) & 0x7F) << 18)
+#define   G_008DFC_OP(x)                                              (((x) >> 18) & 0x7F)
+#define   C_008DFC_OP                                                 0xFE03FFFF
+#define     V_008DFC_SQ_BUFFER_LOAD_FORMAT_X                        0x00
+#define     V_008DFC_SQ_BUFFER_LOAD_FORMAT_XY                       0x01
+#define     V_008DFC_SQ_BUFFER_LOAD_FORMAT_XYZ                      0x02
+#define     V_008DFC_SQ_BUFFER_LOAD_FORMAT_XYZW                     0x03
+#define     V_008DFC_SQ_BUFFER_STORE_FORMAT_X                       0x04
+#define     V_008DFC_SQ_BUFFER_STORE_FORMAT_XY                      0x05
+#define     V_008DFC_SQ_BUFFER_STORE_FORMAT_XYZ                     0x06
+#define     V_008DFC_SQ_BUFFER_STORE_FORMAT_XYZW                    0x07
+#define     V_008DFC_SQ_BUFFER_LOAD_UBYTE                           0x08
+#define     V_008DFC_SQ_BUFFER_LOAD_SBYTE                           0x09
+#define     V_008DFC_SQ_BUFFER_LOAD_USHORT                          0x0A
+#define     V_008DFC_SQ_BUFFER_LOAD_SSHORT                          0x0B
+#define     V_008DFC_SQ_BUFFER_LOAD_DWORD                           0x0C
+#define     V_008DFC_SQ_BUFFER_LOAD_DWORDX2                         0x0D
+#define     V_008DFC_SQ_BUFFER_LOAD_DWORDX4                         0x0E
+/* CIK */
+#define     V_008DFC_SQ_BUFFER_LOAD_DWORDX3                         0x0F
+/*     */
+#define     V_008DFC_SQ_BUFFER_STORE_BYTE                           0x18
+#define     V_008DFC_SQ_BUFFER_STORE_SHORT                          0x1A
+#define     V_008DFC_SQ_BUFFER_STORE_DWORD                          0x1C
+#define     V_008DFC_SQ_BUFFER_STORE_DWORDX2                        0x1D
+#define     V_008DFC_SQ_BUFFER_STORE_DWORDX4                        0x1E
+/* CIK */
+#define     V_008DFC_SQ_BUFFER_STORE_DWORDX3                        0x1F
+/*     */
+#define     V_008DFC_SQ_BUFFER_ATOMIC_SWAP                          0x30
+#define     V_008DFC_SQ_BUFFER_ATOMIC_CMPSWAP                       0x31
+#define     V_008DFC_SQ_BUFFER_ATOMIC_ADD                           0x32
+#define     V_008DFC_SQ_BUFFER_ATOMIC_SUB                           0x33
+#define     V_008DFC_SQ_BUFFER_ATOMIC_RSUB                          0x34 /* not on CIK */
+#define     V_008DFC_SQ_BUFFER_ATOMIC_SMIN                          0x35
+#define     V_008DFC_SQ_BUFFER_ATOMIC_UMIN                          0x36
+#define     V_008DFC_SQ_BUFFER_ATOMIC_SMAX                          0x37
+#define     V_008DFC_SQ_BUFFER_ATOMIC_UMAX                          0x38
+#define     V_008DFC_SQ_BUFFER_ATOMIC_AND                           0x39
+#define     V_008DFC_SQ_BUFFER_ATOMIC_OR                            0x3A
+#define     V_008DFC_SQ_BUFFER_ATOMIC_XOR                           0x3B
+#define     V_008DFC_SQ_BUFFER_ATOMIC_INC                           0x3C
+#define     V_008DFC_SQ_BUFFER_ATOMIC_DEC                           0x3D
+#define     V_008DFC_SQ_BUFFER_ATOMIC_FCMPSWAP                      0x3E
+#define     V_008DFC_SQ_BUFFER_ATOMIC_FMIN                          0x3F
+#define     V_008DFC_SQ_BUFFER_ATOMIC_FMAX                          0x40
+#define     V_008DFC_SQ_BUFFER_ATOMIC_SWAP_X2                       0x50
+#define     V_008DFC_SQ_BUFFER_ATOMIC_CMPSWAP_X2                    0x51
+#define     V_008DFC_SQ_BUFFER_ATOMIC_ADD_X2                        0x52
+#define     V_008DFC_SQ_BUFFER_ATOMIC_SUB_X2                        0x53
+#define     V_008DFC_SQ_BUFFER_ATOMIC_RSUB_X2                       0x54 /* not on CIK */
+#define     V_008DFC_SQ_BUFFER_ATOMIC_SMIN_X2                       0x55
+#define     V_008DFC_SQ_BUFFER_ATOMIC_UMIN_X2                       0x56
+#define     V_008DFC_SQ_BUFFER_ATOMIC_SMAX_X2                       0x57
+#define     V_008DFC_SQ_BUFFER_ATOMIC_UMAX_X2                       0x58
+#define     V_008DFC_SQ_BUFFER_ATOMIC_AND_X2                        0x59
+#define     V_008DFC_SQ_BUFFER_ATOMIC_OR_X2                         0x5A
+#define     V_008DFC_SQ_BUFFER_ATOMIC_XOR_X2                        0x5B
+#define     V_008DFC_SQ_BUFFER_ATOMIC_INC_X2                        0x5C
+#define     V_008DFC_SQ_BUFFER_ATOMIC_DEC_X2                        0x5D
+#define     V_008DFC_SQ_BUFFER_ATOMIC_FCMPSWAP_X2                   0x5E
+#define     V_008DFC_SQ_BUFFER_ATOMIC_FMIN_X2                       0x5F
+#define     V_008DFC_SQ_BUFFER_ATOMIC_FMAX_X2                       0x60
+#define     V_008DFC_SQ_BUFFER_WBINVL1_SC                           0x70
+/* CIK */
+#define     V_008DFC_SQ_BUFFER_WBINVL1_VOL                          0x70
+/*     */
+#define     V_008DFC_SQ_BUFFER_WBINVL1                              0x71
+#define   S_008DFC_ENCODING(x)                                        (((x) & 0x3F) << 26)
+#define   G_008DFC_ENCODING(x)                                        (((x) >> 26) & 0x3F)
+#define   C_008DFC_ENCODING                                           0x03FFFFFF
+#define     V_008DFC_SQ_ENC_MUBUF_FIELD                             0x38
+#endif
+#define R_008F00_SQ_BUF_RSRC_WORD0                                      0x008F00
+#define R_008F04_SQ_BUF_RSRC_WORD1                                      0x008F04
+#define   S_008F04_BASE_ADDRESS_HI(x)                                 (((x) & 0xFFFF) << 0)
+#define   G_008F04_BASE_ADDRESS_HI(x)                                 (((x) >> 0) & 0xFFFF)
+#define   C_008F04_BASE_ADDRESS_HI                                    0xFFFF0000
+#define   S_008F04_STRIDE(x)                                          (((x) & 0x3FFF) << 16)
+#define   G_008F04_STRIDE(x)                                          (((x) >> 16) & 0x3FFF)
+#define   C_008F04_STRIDE                                             0xC000FFFF
+#define   S_008F04_CACHE_SWIZZLE(x)                                   (((x) & 0x1) << 30)
+#define   G_008F04_CACHE_SWIZZLE(x)                                   (((x) >> 30) & 0x1)
+#define   C_008F04_CACHE_SWIZZLE                                      0xBFFFFFFF
+#define   S_008F04_SWIZZLE_ENABLE(x)                                  (((x) & 0x1) << 31)
+#define   G_008F04_SWIZZLE_ENABLE(x)                                  (((x) >> 31) & 0x1)
+#define   C_008F04_SWIZZLE_ENABLE                                     0x7FFFFFFF
+#define R_008F08_SQ_BUF_RSRC_WORD2                                      0x008F08
+#define R_008F0C_SQ_BUF_RSRC_WORD3                                      0x008F0C
+#define   S_008F0C_DST_SEL_X(x)                                       (((x) & 0x07) << 0)
+#define   G_008F0C_DST_SEL_X(x)                                       (((x) >> 0) & 0x07)
+#define   C_008F0C_DST_SEL_X                                          0xFFFFFFF8
+#define     V_008F0C_SQ_SEL_0                                       0x00
+#define     V_008F0C_SQ_SEL_1                                       0x01
+#define     V_008F0C_SQ_SEL_RESERVED_0                              0x02
+#define     V_008F0C_SQ_SEL_RESERVED_1                              0x03
+#define     V_008F0C_SQ_SEL_X                                       0x04
+#define     V_008F0C_SQ_SEL_Y                                       0x05
+#define     V_008F0C_SQ_SEL_Z                                       0x06
+#define     V_008F0C_SQ_SEL_W                                       0x07
+#define   S_008F0C_DST_SEL_Y(x)                                       (((x) & 0x07) << 3)
+#define   G_008F0C_DST_SEL_Y(x)                                       (((x) >> 3) & 0x07)
+#define   C_008F0C_DST_SEL_Y                                          0xFFFFFFC7
+#define     V_008F0C_SQ_SEL_0                                       0x00
+#define     V_008F0C_SQ_SEL_1                                       0x01
+#define     V_008F0C_SQ_SEL_RESERVED_0                              0x02
+#define     V_008F0C_SQ_SEL_RESERVED_1                              0x03
+#define     V_008F0C_SQ_SEL_X                                       0x04
+#define     V_008F0C_SQ_SEL_Y                                       0x05
+#define     V_008F0C_SQ_SEL_Z                                       0x06
+#define     V_008F0C_SQ_SEL_W                                       0x07
+#define   S_008F0C_DST_SEL_Z(x)                                       (((x) & 0x07) << 6)
+#define   G_008F0C_DST_SEL_Z(x)                                       (((x) >> 6) & 0x07)
+#define   C_008F0C_DST_SEL_Z                                          0xFFFFFE3F
+#define     V_008F0C_SQ_SEL_0                                       0x00
+#define     V_008F0C_SQ_SEL_1                                       0x01
+#define     V_008F0C_SQ_SEL_RESERVED_0                              0x02
+#define     V_008F0C_SQ_SEL_RESERVED_1                              0x03
+#define     V_008F0C_SQ_SEL_X                                       0x04
+#define     V_008F0C_SQ_SEL_Y                                       0x05
+#define     V_008F0C_SQ_SEL_Z                                       0x06
+#define     V_008F0C_SQ_SEL_W                                       0x07
+#define   S_008F0C_DST_SEL_W(x)                                       (((x) & 0x07) << 9)
+#define   G_008F0C_DST_SEL_W(x)                                       (((x) >> 9) & 0x07)
+#define   C_008F0C_DST_SEL_W                                          0xFFFFF1FF
+#define     V_008F0C_SQ_SEL_0                                       0x00
+#define     V_008F0C_SQ_SEL_1                                       0x01
+#define     V_008F0C_SQ_SEL_RESERVED_0                              0x02
+#define     V_008F0C_SQ_SEL_RESERVED_1                              0x03
+#define     V_008F0C_SQ_SEL_X                                       0x04
+#define     V_008F0C_SQ_SEL_Y                                       0x05
+#define     V_008F0C_SQ_SEL_Z                                       0x06
+#define     V_008F0C_SQ_SEL_W                                       0x07
+#define   S_008F0C_NUM_FORMAT(x)                                      (((x) & 0x07) << 12)
+#define   G_008F0C_NUM_FORMAT(x)                                      (((x) >> 12) & 0x07)
+#define   C_008F0C_NUM_FORMAT                                         0xFFFF8FFF
+#define     V_008F0C_BUF_NUM_FORMAT_UNORM                           0x00
+#define     V_008F0C_BUF_NUM_FORMAT_SNORM                           0x01
+#define     V_008F0C_BUF_NUM_FORMAT_USCALED                         0x02
+#define     V_008F0C_BUF_NUM_FORMAT_SSCALED                         0x03
+#define     V_008F0C_BUF_NUM_FORMAT_UINT                            0x04
+#define     V_008F0C_BUF_NUM_FORMAT_SINT                            0x05
+#define     V_008F0C_BUF_NUM_FORMAT_SNORM_OGL                       0x06
+#define     V_008F0C_BUF_NUM_FORMAT_FLOAT                           0x07
+#define   S_008F0C_DATA_FORMAT(x)                                     (((x) & 0x0F) << 15)
+#define   G_008F0C_DATA_FORMAT(x)                                     (((x) >> 15) & 0x0F)
+#define   C_008F0C_DATA_FORMAT                                        0xFFF87FFF
+#define     V_008F0C_BUF_DATA_FORMAT_INVALID                        0x00
+#define     V_008F0C_BUF_DATA_FORMAT_8                              0x01
+#define     V_008F0C_BUF_DATA_FORMAT_16                             0x02
+#define     V_008F0C_BUF_DATA_FORMAT_8_8                            0x03
+#define     V_008F0C_BUF_DATA_FORMAT_32                             0x04
+#define     V_008F0C_BUF_DATA_FORMAT_16_16                          0x05
+#define     V_008F0C_BUF_DATA_FORMAT_10_11_11                       0x06
+#define     V_008F0C_BUF_DATA_FORMAT_11_11_10                       0x07
+#define     V_008F0C_BUF_DATA_FORMAT_10_10_10_2                     0x08
+#define     V_008F0C_BUF_DATA_FORMAT_2_10_10_10                     0x09
+#define     V_008F0C_BUF_DATA_FORMAT_8_8_8_8                        0x0A
+#define     V_008F0C_BUF_DATA_FORMAT_32_32                          0x0B
+#define     V_008F0C_BUF_DATA_FORMAT_16_16_16_16                    0x0C
+#define     V_008F0C_BUF_DATA_FORMAT_32_32_32                       0x0D
+#define     V_008F0C_BUF_DATA_FORMAT_32_32_32_32                    0x0E
+#define     V_008F0C_BUF_DATA_FORMAT_RESERVED_15                    0x0F
+#define   S_008F0C_ELEMENT_SIZE(x)                                    (((x) & 0x03) << 19)
+#define   G_008F0C_ELEMENT_SIZE(x)                                    (((x) >> 19) & 0x03)
+#define   C_008F0C_ELEMENT_SIZE                                       0xFFE7FFFF
+#define   S_008F0C_INDEX_STRIDE(x)                                    (((x) & 0x03) << 21)
+#define   G_008F0C_INDEX_STRIDE(x)                                    (((x) >> 21) & 0x03)
+#define   C_008F0C_INDEX_STRIDE                                       0xFF9FFFFF
+#define   S_008F0C_ADD_TID_ENABLE(x)                                  (((x) & 0x1) << 23)
+#define   G_008F0C_ADD_TID_ENABLE(x)                                  (((x) >> 23) & 0x1)
+#define   C_008F0C_ADD_TID_ENABLE                                     0xFF7FFFFF
+/* CIK */
+#define   S_008F0C_ATC(x)                                             (((x) & 0x1) << 24)
+#define   G_008F0C_ATC(x)                                             (((x) >> 24) & 0x1)
+#define   C_008F0C_ATC                                                0xFEFFFFFF
+/*     */
+#define   S_008F0C_HASH_ENABLE(x)                                     (((x) & 0x1) << 25)
+#define   G_008F0C_HASH_ENABLE(x)                                     (((x) >> 25) & 0x1)
+#define   C_008F0C_HASH_ENABLE                                        0xFDFFFFFF
+#define   S_008F0C_HEAP(x)                                            (((x) & 0x1) << 26)
+#define   G_008F0C_HEAP(x)                                            (((x) >> 26) & 0x1)
+#define   C_008F0C_HEAP                                               0xFBFFFFFF
+/* CIK */
+#define   S_008F0C_MTYPE(x)                                           (((x) & 0x07) << 27)
+#define   G_008F0C_MTYPE(x)                                           (((x) >> 27) & 0x07)
+#define   C_008F0C_MTYPE                                              0xC7FFFFFF
+/*     */
+#define   S_008F0C_TYPE(x)                                            (((x) & 0x03) << 30)
+#define   G_008F0C_TYPE(x)                                            (((x) >> 30) & 0x03)
+#define   C_008F0C_TYPE                                               0x3FFFFFFF
+#define     V_008F0C_SQ_RSRC_BUF                                    0x00
+#define     V_008F0C_SQ_RSRC_BUF_RSVD_1                             0x01
+#define     V_008F0C_SQ_RSRC_BUF_RSVD_2                             0x02
+#define     V_008F0C_SQ_RSRC_BUF_RSVD_3                             0x03
+#define R_008F10_SQ_IMG_RSRC_WORD0                                      0x008F10
+#define R_008F14_SQ_IMG_RSRC_WORD1                                      0x008F14
+#define   S_008F14_BASE_ADDRESS_HI(x)                                 (((x) & 0xFF) << 0)
+#define   G_008F14_BASE_ADDRESS_HI(x)                                 (((x) >> 0) & 0xFF)
+#define   C_008F14_BASE_ADDRESS_HI                                    0xFFFFFF00
+#define   S_008F14_MIN_LOD(x)                                         (((x) & 0xFFF) << 8)
+#define   G_008F14_MIN_LOD(x)                                         (((x) >> 8) & 0xFFF)
+#define   C_008F14_MIN_LOD                                            0xFFF000FF
+#define   S_008F14_DATA_FORMAT(x)                                     (((x) & 0x3F) << 20)
+#define   G_008F14_DATA_FORMAT(x)                                     (((x) >> 20) & 0x3F)
+#define   C_008F14_DATA_FORMAT                                        0xFC0FFFFF
+#define     V_008F14_IMG_DATA_FORMAT_INVALID                        0x00
+#define     V_008F14_IMG_DATA_FORMAT_8                              0x01
+#define     V_008F14_IMG_DATA_FORMAT_16                             0x02
+#define     V_008F14_IMG_DATA_FORMAT_8_8                            0x03
+#define     V_008F14_IMG_DATA_FORMAT_32                             0x04
+#define     V_008F14_IMG_DATA_FORMAT_16_16                          0x05
+#define     V_008F14_IMG_DATA_FORMAT_10_11_11                       0x06
+#define     V_008F14_IMG_DATA_FORMAT_11_11_10                       0x07
+#define     V_008F14_IMG_DATA_FORMAT_10_10_10_2                     0x08
+#define     V_008F14_IMG_DATA_FORMAT_2_10_10_10                     0x09
+#define     V_008F14_IMG_DATA_FORMAT_8_8_8_8                        0x0A
+#define     V_008F14_IMG_DATA_FORMAT_32_32                          0x0B
+#define     V_008F14_IMG_DATA_FORMAT_16_16_16_16                    0x0C
+#define     V_008F14_IMG_DATA_FORMAT_32_32_32                       0x0D
+#define     V_008F14_IMG_DATA_FORMAT_32_32_32_32                    0x0E
+#define     V_008F14_IMG_DATA_FORMAT_RESERVED_15                    0x0F
+#define     V_008F14_IMG_DATA_FORMAT_5_6_5                          0x10
+#define     V_008F14_IMG_DATA_FORMAT_1_5_5_5                        0x11
+#define     V_008F14_IMG_DATA_FORMAT_5_5_5_1                        0x12
+#define     V_008F14_IMG_DATA_FORMAT_4_4_4_4                        0x13
+#define     V_008F14_IMG_DATA_FORMAT_8_24                           0x14
+#define     V_008F14_IMG_DATA_FORMAT_24_8                           0x15
+#define     V_008F14_IMG_DATA_FORMAT_X24_8_32                       0x16
+#define     V_008F14_IMG_DATA_FORMAT_RESERVED_23                    0x17
+#define     V_008F14_IMG_DATA_FORMAT_RESERVED_24                    0x18
+#define     V_008F14_IMG_DATA_FORMAT_RESERVED_25                    0x19
+#define     V_008F14_IMG_DATA_FORMAT_RESERVED_26                    0x1A
+#define     V_008F14_IMG_DATA_FORMAT_RESERVED_27                    0x1B
+#define     V_008F14_IMG_DATA_FORMAT_RESERVED_28                    0x1C
+#define     V_008F14_IMG_DATA_FORMAT_RESERVED_29                    0x1D
+#define     V_008F14_IMG_DATA_FORMAT_RESERVED_30                    0x1E
+#define     V_008F14_IMG_DATA_FORMAT_RESERVED_31                    0x1F
+#define     V_008F14_IMG_DATA_FORMAT_GB_GR                          0x20
+#define     V_008F14_IMG_DATA_FORMAT_BG_RG                          0x21
+#define     V_008F14_IMG_DATA_FORMAT_5_9_9_9                        0x22
+#define     V_008F14_IMG_DATA_FORMAT_BC1                            0x23
+#define     V_008F14_IMG_DATA_FORMAT_BC2                            0x24
+#define     V_008F14_IMG_DATA_FORMAT_BC3                            0x25
+#define     V_008F14_IMG_DATA_FORMAT_BC4                            0x26
+#define     V_008F14_IMG_DATA_FORMAT_BC5                            0x27
+#define     V_008F14_IMG_DATA_FORMAT_BC6                            0x28
+#define     V_008F14_IMG_DATA_FORMAT_BC7                            0x29
+#define     V_008F14_IMG_DATA_FORMAT_RESERVED_42                    0x2A
+#define     V_008F14_IMG_DATA_FORMAT_RESERVED_43                    0x2B
+#define     V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1                   0x2C
+#define     V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1                   0x2D
+#define     V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1                   0x2E
+#define     V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2                   0x2F
+#define     V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2                   0x30
+#define     V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4                   0x31
+#define     V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1                 0x32
+#define     V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2                  0x33
+#define     V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2                 0x34
+#define     V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4                  0x35
+#define     V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8                  0x36
+#define     V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4                 0x37
+#define     V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8                 0x38
+#define     V_008F14_IMG_DATA_FORMAT_4_4                            0x39
+#define     V_008F14_IMG_DATA_FORMAT_6_5_5                          0x3A
+#define     V_008F14_IMG_DATA_FORMAT_1                              0x3B
+#define     V_008F14_IMG_DATA_FORMAT_1_REVERSED                     0x3C
+#define     V_008F14_IMG_DATA_FORMAT_32_AS_8                        0x3D
+#define     V_008F14_IMG_DATA_FORMAT_32_AS_8_8                      0x3E
+#define     V_008F14_IMG_DATA_FORMAT_32_AS_32_32_32_32              0x3F
+#define   S_008F14_NUM_FORMAT(x)                                      (((x) & 0x0F) << 26)
+#define   G_008F14_NUM_FORMAT(x)                                      (((x) >> 26) & 0x0F)
+#define   C_008F14_NUM_FORMAT                                         0xC3FFFFFF
+#define     V_008F14_IMG_NUM_FORMAT_UNORM                           0x00
+#define     V_008F14_IMG_NUM_FORMAT_SNORM                           0x01
+#define     V_008F14_IMG_NUM_FORMAT_USCALED                         0x02
+#define     V_008F14_IMG_NUM_FORMAT_SSCALED                         0x03
+#define     V_008F14_IMG_NUM_FORMAT_UINT                            0x04
+#define     V_008F14_IMG_NUM_FORMAT_SINT                            0x05
+#define     V_008F14_IMG_NUM_FORMAT_SNORM_OGL                       0x06
+#define     V_008F14_IMG_NUM_FORMAT_FLOAT                           0x07
+#define     V_008F14_IMG_NUM_FORMAT_RESERVED_8                      0x08
+#define     V_008F14_IMG_NUM_FORMAT_SRGB                            0x09
+#define     V_008F14_IMG_NUM_FORMAT_UBNORM                          0x0A
+#define     V_008F14_IMG_NUM_FORMAT_UBNORM_OGL                      0x0B
+#define     V_008F14_IMG_NUM_FORMAT_UBINT                           0x0C
+#define     V_008F14_IMG_NUM_FORMAT_UBSCALED                        0x0D
+#define     V_008F14_IMG_NUM_FORMAT_RESERVED_14                     0x0E
+#define     V_008F14_IMG_NUM_FORMAT_RESERVED_15                     0x0F
+/* CIK */
+#define   S_008F14_MTYPE(x)                                           (((x) & 0x03) << 30)
+#define   G_008F14_MTYPE(x)                                           (((x) >> 30) & 0x03)
+#define   C_008F14_MTYPE                                              0x3FFFFFFF
+/*     */
+#define R_008F18_SQ_IMG_RSRC_WORD2                                      0x008F18
+#define   S_008F18_WIDTH(x)                                           (((x) & 0x3FFF) << 0)
+#define   G_008F18_WIDTH(x)                                           (((x) >> 0) & 0x3FFF)
+#define   C_008F18_WIDTH                                              0xFFFFC000
+#define   S_008F18_HEIGHT(x)                                          (((x) & 0x3FFF) << 14)
+#define   G_008F18_HEIGHT(x)                                          (((x) >> 14) & 0x3FFF)
+#define   C_008F18_HEIGHT                                             0xF0003FFF
+#define   S_008F18_PERF_MOD(x)                                        (((x) & 0x07) << 28)
+#define   G_008F18_PERF_MOD(x)                                        (((x) >> 28) & 0x07)
+#define   C_008F18_PERF_MOD                                           0x8FFFFFFF
+#define   S_008F18_INTERLACED(x)                                      (((x) & 0x1) << 31)
+#define   G_008F18_INTERLACED(x)                                      (((x) >> 31) & 0x1)
+#define   C_008F18_INTERLACED                                         0x7FFFFFFF
+#define R_008F1C_SQ_IMG_RSRC_WORD3                                      0x008F1C
+#define   S_008F1C_DST_SEL_X(x)                                       (((x) & 0x07) << 0)
+#define   G_008F1C_DST_SEL_X(x)                                       (((x) >> 0) & 0x07)
+#define   C_008F1C_DST_SEL_X                                          0xFFFFFFF8
+#define     V_008F1C_SQ_SEL_0                                       0x00
+#define     V_008F1C_SQ_SEL_1                                       0x01
+#define     V_008F1C_SQ_SEL_RESERVED_0                              0x02
+#define     V_008F1C_SQ_SEL_RESERVED_1                              0x03
+#define     V_008F1C_SQ_SEL_X                                       0x04
+#define     V_008F1C_SQ_SEL_Y                                       0x05
+#define     V_008F1C_SQ_SEL_Z                                       0x06
+#define     V_008F1C_SQ_SEL_W                                       0x07
+#define   S_008F1C_DST_SEL_Y(x)                                       (((x) & 0x07) << 3)
+#define   G_008F1C_DST_SEL_Y(x)                                       (((x) >> 3) & 0x07)
+#define   C_008F1C_DST_SEL_Y                                          0xFFFFFFC7
+#define     V_008F1C_SQ_SEL_0                                       0x00
+#define     V_008F1C_SQ_SEL_1                                       0x01
+#define     V_008F1C_SQ_SEL_RESERVED_0                              0x02
+#define     V_008F1C_SQ_SEL_RESERVED_1                              0x03
+#define     V_008F1C_SQ_SEL_X                                       0x04
+#define     V_008F1C_SQ_SEL_Y                                       0x05
+#define     V_008F1C_SQ_SEL_Z                                       0x06
+#define     V_008F1C_SQ_SEL_W                                       0x07
+#define   S_008F1C_DST_SEL_Z(x)                                       (((x) & 0x07) << 6)
+#define   G_008F1C_DST_SEL_Z(x)                                       (((x) >> 6) & 0x07)
+#define   C_008F1C_DST_SEL_Z                                          0xFFFFFE3F
+#define     V_008F1C_SQ_SEL_0                                       0x00
+#define     V_008F1C_SQ_SEL_1                                       0x01
+#define     V_008F1C_SQ_SEL_RESERVED_0                              0x02
+#define     V_008F1C_SQ_SEL_RESERVED_1                              0x03
+#define     V_008F1C_SQ_SEL_X                                       0x04
+#define     V_008F1C_SQ_SEL_Y                                       0x05
+#define     V_008F1C_SQ_SEL_Z                                       0x06
+#define     V_008F1C_SQ_SEL_W                                       0x07
+#define   S_008F1C_DST_SEL_W(x)                                       (((x) & 0x07) << 9)
+#define   G_008F1C_DST_SEL_W(x)                                       (((x) >> 9) & 0x07)
+#define   C_008F1C_DST_SEL_W                                          0xFFFFF1FF
+#define     V_008F1C_SQ_SEL_0                                       0x00
+#define     V_008F1C_SQ_SEL_1                                       0x01
+#define     V_008F1C_SQ_SEL_RESERVED_0                              0x02
+#define     V_008F1C_SQ_SEL_RESERVED_1                              0x03
+#define     V_008F1C_SQ_SEL_X                                       0x04
+#define     V_008F1C_SQ_SEL_Y                                       0x05
+#define     V_008F1C_SQ_SEL_Z                                       0x06
+#define     V_008F1C_SQ_SEL_W                                       0x07
+#define   S_008F1C_BASE_LEVEL(x)                                      (((x) & 0x0F) << 12)
+#define   G_008F1C_BASE_LEVEL(x)                                      (((x) >> 12) & 0x0F)
+#define   C_008F1C_BASE_LEVEL                                         0xFFFF0FFF
+#define   S_008F1C_LAST_LEVEL(x)                                      (((x) & 0x0F) << 16)
+#define   G_008F1C_LAST_LEVEL(x)                                      (((x) >> 16) & 0x0F)
+#define   C_008F1C_LAST_LEVEL                                         0xFFF0FFFF
+#define   S_008F1C_TILING_INDEX(x)                                    (((x) & 0x1F) << 20)
+#define   G_008F1C_TILING_INDEX(x)                                    (((x) >> 20) & 0x1F)
+#define   C_008F1C_TILING_INDEX                                       0xFE0FFFFF
+#define   S_008F1C_POW2_PAD(x)                                        (((x) & 0x1) << 25)
+#define   G_008F1C_POW2_PAD(x)                                        (((x) >> 25) & 0x1)
+#define   C_008F1C_POW2_PAD                                           0xFDFFFFFF
+/* CIK */
+#define   S_008F1C_MTYPE(x)                                           (((x) & 0x1) << 26)
+#define   G_008F1C_MTYPE(x)                                           (((x) >> 26) & 0x1)
+#define   C_008F1C_MTYPE                                              0xFBFFFFFF
+#define   S_008F1C_ATC(x)                                             (((x) & 0x1) << 27)
+#define   G_008F1C_ATC(x)                                             (((x) >> 27) & 0x1)
+#define   C_008F1C_ATC                                                0xF7FFFFFF
+/*     */
+#define   S_008F1C_TYPE(x)                                            (((x) & 0x0F) << 28)
+#define   G_008F1C_TYPE(x)                                            (((x) >> 28) & 0x0F)
+#define   C_008F1C_TYPE                                               0x0FFFFFFF
+#define     V_008F1C_SQ_RSRC_IMG_RSVD_0                             0x00
+#define     V_008F1C_SQ_RSRC_IMG_RSVD_1                             0x01
+#define     V_008F1C_SQ_RSRC_IMG_RSVD_2                             0x02
+#define     V_008F1C_SQ_RSRC_IMG_RSVD_3                             0x03
+#define     V_008F1C_SQ_RSRC_IMG_RSVD_4                             0x04
+#define     V_008F1C_SQ_RSRC_IMG_RSVD_5                             0x05
+#define     V_008F1C_SQ_RSRC_IMG_RSVD_6                             0x06
+#define     V_008F1C_SQ_RSRC_IMG_RSVD_7                             0x07
+#define     V_008F1C_SQ_RSRC_IMG_1D                                 0x08
+#define     V_008F1C_SQ_RSRC_IMG_2D                                 0x09
+#define     V_008F1C_SQ_RSRC_IMG_3D                                 0x0A
+#define     V_008F1C_SQ_RSRC_IMG_CUBE                               0x0B
+#define     V_008F1C_SQ_RSRC_IMG_1D_ARRAY                           0x0C
+#define     V_008F1C_SQ_RSRC_IMG_2D_ARRAY                           0x0D
+#define     V_008F1C_SQ_RSRC_IMG_2D_MSAA                            0x0E
+#define     V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY                      0x0F
+#define R_008F20_SQ_IMG_RSRC_WORD4                                      0x008F20
+#define   S_008F20_DEPTH(x)                                           (((x) & 0x1FFF) << 0)
+#define   G_008F20_DEPTH(x)                                           (((x) >> 0) & 0x1FFF)
+#define   C_008F20_DEPTH                                              0xFFFFE000
+#define   S_008F20_PITCH(x)                                           (((x) & 0x3FFF) << 13)
+#define   G_008F20_PITCH(x)                                           (((x) >> 13) & 0x3FFF)
+#define   C_008F20_PITCH                                              0xF8001FFF
+#define R_008F24_SQ_IMG_RSRC_WORD5                                      0x008F24
+#define   S_008F24_BASE_ARRAY(x)                                      (((x) & 0x1FFF) << 0)
+#define   G_008F24_BASE_ARRAY(x)                                      (((x) >> 0) & 0x1FFF)
+#define   C_008F24_BASE_ARRAY                                         0xFFFFE000
+#define   S_008F24_LAST_ARRAY(x)                                      (((x) & 0x1FFF) << 13)
+#define   G_008F24_LAST_ARRAY(x)                                      (((x) >> 13) & 0x1FFF)
+#define   C_008F24_LAST_ARRAY                                         0xFC001FFF
+#define R_008F28_SQ_IMG_RSRC_WORD6                                      0x008F28
+#define   S_008F28_MIN_LOD_WARN(x)                                    (((x) & 0xFFF) << 0)
+#define   G_008F28_MIN_LOD_WARN(x)                                    (((x) >> 0) & 0xFFF)
+#define   C_008F28_MIN_LOD_WARN                                       0xFFFFF000
+/* CIK */
+#define   S_008F28_COUNTER_BANK_ID(x)                                 (((x) & 0xFF) << 12)
+#define   G_008F28_COUNTER_BANK_ID(x)                                 (((x) >> 12) & 0xFF)
+#define   C_008F28_COUNTER_BANK_ID                                    0xFFF00FFF
+#define   S_008F28_LOD_HDW_CNT_EN(x)                                  (((x) & 0x1) << 20)
+#define   G_008F28_LOD_HDW_CNT_EN(x)                                  (((x) >> 20) & 0x1)
+#define   C_008F28_LOD_HDW_CNT_EN                                     0xFFEFFFFF
+/*     */
+#define R_008F2C_SQ_IMG_RSRC_WORD7                                      0x008F2C
+#define R_008F30_SQ_IMG_SAMP_WORD0                                      0x008F30
+#define   S_008F30_CLAMP_X(x)                                         (((x) & 0x07) << 0)
+#define   G_008F30_CLAMP_X(x)                                         (((x) >> 0) & 0x07)
+#define   C_008F30_CLAMP_X                                            0xFFFFFFF8
+#define     V_008F30_SQ_TEX_WRAP                                    0x00
+#define     V_008F30_SQ_TEX_MIRROR                                  0x01
+#define     V_008F30_SQ_TEX_CLAMP_LAST_TEXEL                        0x02
+#define     V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL                  0x03
+#define     V_008F30_SQ_TEX_CLAMP_HALF_BORDER                       0x04
+#define     V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER                 0x05
+#define     V_008F30_SQ_TEX_CLAMP_BORDER                            0x06
+#define     V_008F30_SQ_TEX_MIRROR_ONCE_BORDER                      0x07
+#define   S_008F30_CLAMP_Y(x)                                         (((x) & 0x07) << 3)
+#define   G_008F30_CLAMP_Y(x)                                         (((x) >> 3) & 0x07)
+#define   C_008F30_CLAMP_Y                                            0xFFFFFFC7
+#define     V_008F30_SQ_TEX_WRAP                                    0x00
+#define     V_008F30_SQ_TEX_MIRROR                                  0x01
+#define     V_008F30_SQ_TEX_CLAMP_LAST_TEXEL                        0x02
+#define     V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL                  0x03
+#define     V_008F30_SQ_TEX_CLAMP_HALF_BORDER                       0x04
+#define     V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER                 0x05
+#define     V_008F30_SQ_TEX_CLAMP_BORDER                            0x06
+#define     V_008F30_SQ_TEX_MIRROR_ONCE_BORDER                      0x07
+#define   S_008F30_CLAMP_Z(x)                                         (((x) & 0x07) << 6)
+#define   G_008F30_CLAMP_Z(x)                                         (((x) >> 6) & 0x07)
+#define   C_008F30_CLAMP_Z                                            0xFFFFFE3F
+#define     V_008F30_SQ_TEX_WRAP                                    0x00
+#define     V_008F30_SQ_TEX_MIRROR                                  0x01
+#define     V_008F30_SQ_TEX_CLAMP_LAST_TEXEL                        0x02
+#define     V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL                  0x03
+#define     V_008F30_SQ_TEX_CLAMP_HALF_BORDER                       0x04
+#define     V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER                 0x05
+#define     V_008F30_SQ_TEX_CLAMP_BORDER                            0x06
+#define     V_008F30_SQ_TEX_MIRROR_ONCE_BORDER                      0x07
+#define   S_008F30_DEPTH_COMPARE_FUNC(x)                              (((x) & 0x07) << 12)
+#define   G_008F30_DEPTH_COMPARE_FUNC(x)                              (((x) >> 12) & 0x07)
+#define   C_008F30_DEPTH_COMPARE_FUNC                                 0xFFFF8FFF
+#define     V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER                     0x00
+#define     V_008F30_SQ_TEX_DEPTH_COMPARE_LESS                      0x01
+#define     V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL                     0x02
+#define     V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL                 0x03
+#define     V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER                   0x04
+#define     V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL                  0x05
+#define     V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL              0x06
+#define     V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS                    0x07
+#define   S_008F30_FORCE_UNNORMALIZED(x)                              (((x) & 0x1) << 15)
+#define   G_008F30_FORCE_UNNORMALIZED(x)                              (((x) >> 15) & 0x1)
+#define   C_008F30_FORCE_UNNORMALIZED                                 0xFFFF7FFF
+#define   S_008F30_MC_COORD_TRUNC(x)                                  (((x) & 0x1) << 19)
+#define   G_008F30_MC_COORD_TRUNC(x)                                  (((x) >> 19) & 0x1)
+#define   C_008F30_MC_COORD_TRUNC                                     0xFFF7FFFF
+#define   S_008F30_FORCE_DEGAMMA(x)                                   (((x) & 0x1) << 20)
+#define   G_008F30_FORCE_DEGAMMA(x)                                   (((x) >> 20) & 0x1)
+#define   C_008F30_FORCE_DEGAMMA                                      0xFFEFFFFF
+#define   S_008F30_TRUNC_COORD(x)                                     (((x) & 0x1) << 27)
+#define   G_008F30_TRUNC_COORD(x)                                     (((x) >> 27) & 0x1)
+#define   C_008F30_TRUNC_COORD                                        0xF7FFFFFF
+#define   S_008F30_DISABLE_CUBE_WRAP(x)                               (((x) & 0x1) << 28)
+#define   G_008F30_DISABLE_CUBE_WRAP(x)                               (((x) >> 28) & 0x1)
+#define   C_008F30_DISABLE_CUBE_WRAP                                  0xEFFFFFFF
+#define   S_008F30_FILTER_MODE(x)                                     (((x) & 0x03) << 29)
+#define   G_008F30_FILTER_MODE(x)                                     (((x) >> 29) & 0x03)
+#define   C_008F30_FILTER_MODE                                        0x9FFFFFFF
+#define R_008F34_SQ_IMG_SAMP_WORD1                                      0x008F34
+#define   S_008F34_MIN_LOD(x)                                         (((x) & 0xFFF) << 0)
+#define   G_008F34_MIN_LOD(x)                                         (((x) >> 0) & 0xFFF)
+#define   C_008F34_MIN_LOD                                            0xFFFFF000
+#define   S_008F34_MAX_LOD(x)                                         (((x) & 0xFFF) << 12)
+#define   G_008F34_MAX_LOD(x)                                         (((x) >> 12) & 0xFFF)
+#define   C_008F34_MAX_LOD                                            0xFF000FFF
+#define   S_008F34_PERF_MIP(x)                                        (((x) & 0x0F) << 24)
+#define   G_008F34_PERF_MIP(x)                                        (((x) >> 24) & 0x0F)
+#define   C_008F34_PERF_MIP                                           0xF0FFFFFF
+#define   S_008F34_PERF_Z(x)                                          (((x) & 0x0F) << 28)
+#define   G_008F34_PERF_Z(x)                                          (((x) >> 28) & 0x0F)
+#define   C_008F34_PERF_Z                                             0x0FFFFFFF
+#define R_008F38_SQ_IMG_SAMP_WORD2                                      0x008F38
+#define   S_008F38_LOD_BIAS(x)                                        (((x) & 0x3FFF) << 0)
+#define   G_008F38_LOD_BIAS(x)                                        (((x) >> 0) & 0x3FFF)
+#define   C_008F38_LOD_BIAS                                           0xFFFFC000
+#define   S_008F38_LOD_BIAS_SEC(x)                                    (((x) & 0x3F) << 14)
+#define   G_008F38_LOD_BIAS_SEC(x)                                    (((x) >> 14) & 0x3F)
+#define   C_008F38_LOD_BIAS_SEC                                       0xFFF03FFF
+#define   S_008F38_XY_MAG_FILTER(x)                                   (((x) & 0x03) << 20)
+#define   G_008F38_XY_MAG_FILTER(x)                                   (((x) >> 20) & 0x03)
+#define   C_008F38_XY_MAG_FILTER                                      0xFFCFFFFF
+#define     V_008F38_SQ_TEX_XY_FILTER_POINT                         0x00
+#define     V_008F38_SQ_TEX_XY_FILTER_BILINEAR                      0x01
+#define   S_008F38_XY_MIN_FILTER(x)                                   (((x) & 0x03) << 22)
+#define   G_008F38_XY_MIN_FILTER(x)                                   (((x) >> 22) & 0x03)
+#define   C_008F38_XY_MIN_FILTER                                      0xFF3FFFFF
+#define     V_008F38_SQ_TEX_XY_FILTER_POINT                         0x00
+#define     V_008F38_SQ_TEX_XY_FILTER_BILINEAR                      0x01
+#define   S_008F38_Z_FILTER(x)                                        (((x) & 0x03) << 24)
+#define   G_008F38_Z_FILTER(x)                                        (((x) >> 24) & 0x03)
+#define   C_008F38_Z_FILTER                                           0xFCFFFFFF
+#define     V_008F38_SQ_TEX_Z_FILTER_NONE                           0x00
+#define     V_008F38_SQ_TEX_Z_FILTER_POINT                          0x01
+#define     V_008F38_SQ_TEX_Z_FILTER_LINEAR                         0x02
+#define   S_008F38_MIP_FILTER(x)                                      (((x) & 0x03) << 26)
+#define   G_008F38_MIP_FILTER(x)                                      (((x) >> 26) & 0x03)
+#define   C_008F38_MIP_FILTER                                         0xF3FFFFFF
+#define     V_008F38_SQ_TEX_Z_FILTER_NONE                           0x00
+#define     V_008F38_SQ_TEX_Z_FILTER_POINT                          0x01
+#define     V_008F38_SQ_TEX_Z_FILTER_LINEAR                         0x02
+#define   S_008F38_MIP_POINT_PRECLAMP(x)                              (((x) & 0x1) << 28)
+#define   G_008F38_MIP_POINT_PRECLAMP(x)                              (((x) >> 28) & 0x1)
+#define   C_008F38_MIP_POINT_PRECLAMP                                 0xEFFFFFFF
+#define   S_008F38_DISABLE_LSB_CEIL(x)                                (((x) & 0x1) << 29)
+#define   G_008F38_DISABLE_LSB_CEIL(x)                                (((x) >> 29) & 0x1)
+#define   C_008F38_DISABLE_LSB_CEIL                                   0xDFFFFFFF
+#define   S_008F38_FILTER_PREC_FIX(x)                                 (((x) & 0x1) << 30)
+#define   G_008F38_FILTER_PREC_FIX(x)                                 (((x) >> 30) & 0x1)
+#define   C_008F38_FILTER_PREC_FIX                                    0xBFFFFFFF
+#define R_008F3C_SQ_IMG_SAMP_WORD3                                      0x008F3C
+#define   S_008F3C_BORDER_COLOR_PTR(x)                                (((x) & 0xFFF) << 0)
+#define   G_008F3C_BORDER_COLOR_PTR(x)                                (((x) >> 0) & 0xFFF)
+#define   C_008F3C_BORDER_COLOR_PTR                                   0xFFFFF000
+#define   S_008F3C_BORDER_COLOR_TYPE(x)                               (((x) & 0x03) << 30)
+#define   G_008F3C_BORDER_COLOR_TYPE(x)                               (((x) >> 30) & 0x03)
+#define   C_008F3C_BORDER_COLOR_TYPE                                  0x3FFFFFFF
+#define     V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK                0x00
+#define     V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK               0x01
+#define     V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE               0x02
+#define     V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER                   0x03
+#define R_0090DC_SPI_DYN_GPR_LOCK_EN                                    0x0090DC /* not on CIK */
+#define   S_0090DC_VS_LOW_THRESHOLD(x)                                (((x) & 0x0F) << 0)
+#define   G_0090DC_VS_LOW_THRESHOLD(x)                                (((x) >> 0) & 0x0F)
+#define   C_0090DC_VS_LOW_THRESHOLD                                   0xFFFFFFF0
+#define   S_0090DC_GS_LOW_THRESHOLD(x)                                (((x) & 0x0F) << 4)
+#define   G_0090DC_GS_LOW_THRESHOLD(x)                                (((x) >> 4) & 0x0F)
+#define   C_0090DC_GS_LOW_THRESHOLD                                   0xFFFFFF0F
+#define   S_0090DC_ES_LOW_THRESHOLD(x)                                (((x) & 0x0F) << 8)
+#define   G_0090DC_ES_LOW_THRESHOLD(x)                                (((x) >> 8) & 0x0F)
+#define   C_0090DC_ES_LOW_THRESHOLD                                   0xFFFFF0FF
+#define   S_0090DC_HS_LOW_THRESHOLD(x)                                (((x) & 0x0F) << 12)
+#define   G_0090DC_HS_LOW_THRESHOLD(x)                                (((x) >> 12) & 0x0F)
+#define   C_0090DC_HS_LOW_THRESHOLD                                   0xFFFF0FFF
+#define   S_0090DC_LS_LOW_THRESHOLD(x)                                (((x) & 0x0F) << 16)
+#define   G_0090DC_LS_LOW_THRESHOLD(x)                                (((x) >> 16) & 0x0F)
+#define   C_0090DC_LS_LOW_THRESHOLD                                   0xFFF0FFFF
+#define R_0090E0_SPI_STATIC_THREAD_MGMT_1                               0x0090E0 /* not on CIK */
+#define   S_0090E0_PS_CU_EN(x)                                        (((x) & 0xFFFF) << 0)
+#define   G_0090E0_PS_CU_EN(x)                                        (((x) >> 0) & 0xFFFF)
+#define   C_0090E0_PS_CU_EN                                           0xFFFF0000
+#define   S_0090E0_VS_CU_EN(x)                                        (((x) & 0xFFFF) << 16)
+#define   G_0090E0_VS_CU_EN(x)                                        (((x) >> 16) & 0xFFFF)
+#define   C_0090E0_VS_CU_EN                                           0x0000FFFF
+#define R_0090E4_SPI_STATIC_THREAD_MGMT_2                               0x0090E4 /* not on CIK */
+#define   S_0090E4_GS_CU_EN(x)                                        (((x) & 0xFFFF) << 0)
+#define   G_0090E4_GS_CU_EN(x)                                        (((x) >> 0) & 0xFFFF)
+#define   C_0090E4_GS_CU_EN                                           0xFFFF0000
+#define   S_0090E4_ES_CU_EN(x)                                        (((x) & 0xFFFF) << 16)
+#define   G_0090E4_ES_CU_EN(x)                                        (((x) >> 16) & 0xFFFF)
+#define   C_0090E4_ES_CU_EN                                           0x0000FFFF
+#define R_0090E8_SPI_STATIC_THREAD_MGMT_3                               0x0090E8 /* not on CIK */
+#define   S_0090E8_LSHS_CU_EN(x)                                      (((x) & 0xFFFF) << 0)
+#define   G_0090E8_LSHS_CU_EN(x)                                      (((x) >> 0) & 0xFFFF)
+#define   C_0090E8_LSHS_CU_EN                                         0xFFFF0000
+#define R_0090EC_SPI_PS_MAX_WAVE_ID                                     0x0090EC
+#define   S_0090EC_MAX_WAVE_ID(x)                                     (((x) & 0xFFF) << 0)
+#define   G_0090EC_MAX_WAVE_ID(x)                                     (((x) >> 0) & 0xFFF)
+#define   C_0090EC_MAX_WAVE_ID                                        0xFFFFF000
+/* CIK */
+#define R_0090E8_SPI_PS_MAX_WAVE_ID                                     0x0090E8
+#define   S_0090E8_MAX_WAVE_ID(x)                                     (((x) & 0xFFF) << 0)
+#define   G_0090E8_MAX_WAVE_ID(x)                                     (((x) >> 0) & 0xFFF)
+#define   C_0090E8_MAX_WAVE_ID                                        0xFFFFF000
+/*     */
+#define R_0090F0_SPI_ARB_PRIORITY                                       0x0090F0
+#define   S_0090F0_RING_ORDER_TS0(x)                                  (((x) & 0x07) << 0)
+#define   G_0090F0_RING_ORDER_TS0(x)                                  (((x) >> 0) & 0x07)
+#define   C_0090F0_RING_ORDER_TS0                                     0xFFFFFFF8
+#define     V_0090F0_X_R0                                           0x00
+#define   S_0090F0_RING_ORDER_TS1(x)                                  (((x) & 0x07) << 3)
+#define   G_0090F0_RING_ORDER_TS1(x)                                  (((x) >> 3) & 0x07)
+#define   C_0090F0_RING_ORDER_TS1                                     0xFFFFFFC7
+#define   S_0090F0_RING_ORDER_TS2(x)                                  (((x) & 0x07) << 6)
+#define   G_0090F0_RING_ORDER_TS2(x)                                  (((x) >> 6) & 0x07)
+#define   C_0090F0_RING_ORDER_TS2                                     0xFFFFFE3F
+/* CIK */
+#define R_00C700_SPI_ARB_PRIORITY                                       0x00C700
+#define   S_00C700_PIPE_ORDER_TS0(x)                                  (((x) & 0x07) << 0)
+#define   G_00C700_PIPE_ORDER_TS0(x)                                  (((x) >> 0) & 0x07)
+#define   C_00C700_PIPE_ORDER_TS0                                     0xFFFFFFF8
+#define   S_00C700_PIPE_ORDER_TS1(x)                                  (((x) & 0x07) << 3)
+#define   G_00C700_PIPE_ORDER_TS1(x)                                  (((x) >> 3) & 0x07)
+#define   C_00C700_PIPE_ORDER_TS1                                     0xFFFFFFC7
+#define   S_00C700_PIPE_ORDER_TS2(x)                                  (((x) & 0x07) << 6)
+#define   G_00C700_PIPE_ORDER_TS2(x)                                  (((x) >> 6) & 0x07)
+#define   C_00C700_PIPE_ORDER_TS2                                     0xFFFFFE3F
+#define   S_00C700_PIPE_ORDER_TS3(x)                                  (((x) & 0x07) << 9)
+#define   G_00C700_PIPE_ORDER_TS3(x)                                  (((x) >> 9) & 0x07)
+#define   C_00C700_PIPE_ORDER_TS3                                     0xFFFFF1FF
+#define   S_00C700_TS0_DUR_MULT(x)                                    (((x) & 0x03) << 12)
+#define   G_00C700_TS0_DUR_MULT(x)                                    (((x) >> 12) & 0x03)
+#define   C_00C700_TS0_DUR_MULT                                       0xFFFFCFFF
+#define   S_00C700_TS1_DUR_MULT(x)                                    (((x) & 0x03) << 14)
+#define   G_00C700_TS1_DUR_MULT(x)                                    (((x) >> 14) & 0x03)
+#define   C_00C700_TS1_DUR_MULT                                       0xFFFF3FFF
+#define   S_00C700_TS2_DUR_MULT(x)                                    (((x) & 0x03) << 16)
+#define   G_00C700_TS2_DUR_MULT(x)                                    (((x) >> 16) & 0x03)
+#define   C_00C700_TS2_DUR_MULT                                       0xFFFCFFFF
+#define   S_00C700_TS3_DUR_MULT(x)                                    (((x) & 0x03) << 18)
+#define   G_00C700_TS3_DUR_MULT(x)                                    (((x) >> 18) & 0x03)
+#define   C_00C700_TS3_DUR_MULT                                       0xFFF3FFFF
+/*     */
+#define R_0090F4_SPI_ARB_CYCLES_0                                       0x0090F4 /* moved to 0xC704 on CIK */
+#define   S_0090F4_TS0_DURATION(x)                                    (((x) & 0xFFFF) << 0)
+#define   G_0090F4_TS0_DURATION(x)                                    (((x) >> 0) & 0xFFFF)
+#define   C_0090F4_TS0_DURATION                                       0xFFFF0000
+#define   S_0090F4_TS1_DURATION(x)                                    (((x) & 0xFFFF) << 16)
+#define   G_0090F4_TS1_DURATION(x)                                    (((x) >> 16) & 0xFFFF)
+#define   C_0090F4_TS1_DURATION                                       0x0000FFFF
+#define R_0090F8_SPI_ARB_CYCLES_1                                       0x0090F8 /* moved to 0xC708 on CIK */
+#define   S_0090F8_TS2_DURATION(x)                                    (((x) & 0xFFFF) << 0)
+#define   G_0090F8_TS2_DURATION(x)                                    (((x) >> 0) & 0xFFFF)
+#define   C_0090F8_TS2_DURATION                                       0xFFFF0000
+/* CIK */
+#define R_008F40_SQ_FLAT_SCRATCH_WORD0                                  0x008F40
+#define   S_008F40_SIZE(x)                                            (((x) & 0x7FFFF) << 0)
+#define   G_008F40_SIZE(x)                                            (((x) >> 0) & 0x7FFFF)
+#define   C_008F40_SIZE                                               0xFFF80000
+#define R_008F44_SQ_FLAT_SCRATCH_WORD1                                  0x008F44
+#define   S_008F44_OFFSET(x)                                          (((x) & 0xFFFFFF) << 0)
+#define   G_008F44_OFFSET(x)                                          (((x) >> 0) & 0xFFFFFF)
+#define   C_008F44_OFFSET                                             0xFF000000
+/*     */
+#define R_009100_SPI_CONFIG_CNTL                                        0x009100
+#define   S_009100_GPR_WRITE_PRIORITY(x)                              (((x) & 0x1FFFFF) << 0)
+#define   G_009100_GPR_WRITE_PRIORITY(x)                              (((x) >> 0) & 0x1FFFFF)
+#define   C_009100_GPR_WRITE_PRIORITY                                 0xFFE00000
+#define   S_009100_EXP_PRIORITY_ORDER(x)                              (((x) & 0x07) << 21)
+#define   G_009100_EXP_PRIORITY_ORDER(x)                              (((x) >> 21) & 0x07)
+#define   C_009100_EXP_PRIORITY_ORDER                                 0xFF1FFFFF
+#define   S_009100_ENABLE_SQG_TOP_EVENTS(x)                           (((x) & 0x1) << 24)
+#define   G_009100_ENABLE_SQG_TOP_EVENTS(x)                           (((x) >> 24) & 0x1)
+#define   C_009100_ENABLE_SQG_TOP_EVENTS                              0xFEFFFFFF
+#define   S_009100_ENABLE_SQG_BOP_EVENTS(x)                           (((x) & 0x1) << 25)
+#define   G_009100_ENABLE_SQG_BOP_EVENTS(x)                           (((x) >> 25) & 0x1)
+#define   C_009100_ENABLE_SQG_BOP_EVENTS                              0xFDFFFFFF
+#define   S_009100_RSRC_MGMT_RESET(x)                                 (((x) & 0x1) << 26)
+#define   G_009100_RSRC_MGMT_RESET(x)                                 (((x) >> 26) & 0x1)
+#define   C_009100_RSRC_MGMT_RESET                                    0xFBFFFFFF
+#define R_00913C_SPI_CONFIG_CNTL_1                                      0x00913C
+#define   S_00913C_VTX_DONE_DELAY(x)                                  (((x) & 0x0F) << 0)
+#define   G_00913C_VTX_DONE_DELAY(x)                                  (((x) >> 0) & 0x0F)
+#define   C_00913C_VTX_DONE_DELAY                                     0xFFFFFFF0
+#define     V_00913C_X_DELAY_14_CLKS                                0x00
+#define     V_00913C_X_DELAY_16_CLKS                                0x01
+#define     V_00913C_X_DELAY_18_CLKS                                0x02
+#define     V_00913C_X_DELAY_20_CLKS                                0x03
+#define     V_00913C_X_DELAY_22_CLKS                                0x04
+#define     V_00913C_X_DELAY_24_CLKS                                0x05
+#define     V_00913C_X_DELAY_26_CLKS                                0x06
+#define     V_00913C_X_DELAY_28_CLKS                                0x07
+#define     V_00913C_X_DELAY_30_CLKS                                0x08
+#define     V_00913C_X_DELAY_32_CLKS                                0x09
+#define     V_00913C_X_DELAY_34_CLKS                                0x0A
+#define     V_00913C_X_DELAY_4_CLKS                                 0x0B
+#define     V_00913C_X_DELAY_6_CLKS                                 0x0C
+#define     V_00913C_X_DELAY_8_CLKS                                 0x0D
+#define     V_00913C_X_DELAY_10_CLKS                                0x0E
+#define     V_00913C_X_DELAY_12_CLKS                                0x0F
+#define   S_00913C_INTERP_ONE_PRIM_PER_ROW(x)                         (((x) & 0x1) << 4)
+#define   G_00913C_INTERP_ONE_PRIM_PER_ROW(x)                         (((x) >> 4) & 0x1)
+#define   C_00913C_INTERP_ONE_PRIM_PER_ROW                            0xFFFFFFEF
+#define   S_00913C_PC_LIMIT_ENABLE(x)                                 (((x) & 0x1) << 6)
+#define   G_00913C_PC_LIMIT_ENABLE(x)                                 (((x) >> 6) & 0x1)
+#define   C_00913C_PC_LIMIT_ENABLE                                    0xFFFFFFBF
+#define   S_00913C_PC_LIMIT_STRICT(x)                                 (((x) & 0x1) << 7)
+#define   G_00913C_PC_LIMIT_STRICT(x)                                 (((x) >> 7) & 0x1)
+#define   C_00913C_PC_LIMIT_STRICT                                    0xFFFFFF7F
+#define   S_00913C_PC_LIMIT_SIZE(x)                                   (((x) & 0xFFFF) << 16)
+#define   G_00913C_PC_LIMIT_SIZE(x)                                   (((x) >> 16) & 0xFFFF)
+#define   C_00913C_PC_LIMIT_SIZE                                      0x0000FFFF
+#define R_00936C_SPI_RESOURCE_RESERVE_CU_AB_0                           0x00936C
+#define   S_00936C_TYPE_A(x)                                          (((x) & 0x0F) << 0)
+#define   G_00936C_TYPE_A(x)                                          (((x) >> 0) & 0x0F)
+#define   C_00936C_TYPE_A                                             0xFFFFFFF0
+#define   S_00936C_VGPR_A(x)                                          (((x) & 0x07) << 4)
+#define   G_00936C_VGPR_A(x)                                          (((x) >> 4) & 0x07)
+#define   C_00936C_VGPR_A                                             0xFFFFFF8F
+#define   S_00936C_SGPR_A(x)                                          (((x) & 0x07) << 7)
+#define   G_00936C_SGPR_A(x)                                          (((x) >> 7) & 0x07)
+#define   C_00936C_SGPR_A                                             0xFFFFFC7F
+#define   S_00936C_LDS_A(x)                                           (((x) & 0x07) << 10)
+#define   G_00936C_LDS_A(x)                                           (((x) >> 10) & 0x07)
+#define   C_00936C_LDS_A                                              0xFFFFE3FF
+#define   S_00936C_WAVES_A(x)                                         (((x) & 0x03) << 13)
+#define   G_00936C_WAVES_A(x)                                         (((x) >> 13) & 0x03)
+#define   C_00936C_WAVES_A                                            0xFFFF9FFF
+#define   S_00936C_EN_A(x)                                            (((x) & 0x1) << 15)
+#define   G_00936C_EN_A(x)                                            (((x) >> 15) & 0x1)
+#define   C_00936C_EN_A                                               0xFFFF7FFF
+#define   S_00936C_TYPE_B(x)                                          (((x) & 0x0F) << 16)
+#define   G_00936C_TYPE_B(x)                                          (((x) >> 16) & 0x0F)
+#define   C_00936C_TYPE_B                                             0xFFF0FFFF
+#define   S_00936C_VGPR_B(x)                                          (((x) & 0x07) << 20)
+#define   G_00936C_VGPR_B(x)                                          (((x) >> 20) & 0x07)
+#define   C_00936C_VGPR_B                                             0xFF8FFFFF
+#define   S_00936C_SGPR_B(x)                                          (((x) & 0x07) << 23)
+#define   G_00936C_SGPR_B(x)                                          (((x) >> 23) & 0x07)
+#define   C_00936C_SGPR_B                                             0xFC7FFFFF
+#define   S_00936C_LDS_B(x)                                           (((x) & 0x07) << 26)
+#define   G_00936C_LDS_B(x)                                           (((x) >> 26) & 0x07)
+#define   C_00936C_LDS_B                                              0xE3FFFFFF
+#define   S_00936C_WAVES_B(x)                                         (((x) & 0x03) << 29)
+#define   G_00936C_WAVES_B(x)                                         (((x) >> 29) & 0x03)
+#define   C_00936C_WAVES_B                                            0x9FFFFFFF
+#define   S_00936C_EN_B(x)                                            (((x) & 0x1) << 31)
+#define   G_00936C_EN_B(x)                                            (((x) >> 31) & 0x1)
+#define   C_00936C_EN_B                                               0x7FFFFFFF
+#define R_00950C_TA_CS_BC_BASE_ADDR                                     0x00950C
+/* CIK */
+#define R_030E00_TA_CS_BC_BASE_ADDR                                     0x030E00
+#define R_030E04_TA_CS_BC_BASE_ADDR_HI                                  0x030E04
+#define   S_030E04_ADDRESS(x)                                         (((x) & 0xFF) << 0)
+#define   G_030E04_ADDRESS(x)                                         (((x) >> 0) & 0xFF)
+#define   C_030E04_ADDRESS                                            0xFFFFFF00
+/*     */
+#define R_009858_DB_SUBTILE_CONTROL                                     0x009858
+#define   S_009858_MSAA1_X(x)                                         (((x) & 0x03) << 0)
+#define   G_009858_MSAA1_X(x)                                         (((x) >> 0) & 0x03)
+#define   C_009858_MSAA1_X                                            0xFFFFFFFC
+#define   S_009858_MSAA1_Y(x)                                         (((x) & 0x03) << 2)
+#define   G_009858_MSAA1_Y(x)                                         (((x) >> 2) & 0x03)
+#define   C_009858_MSAA1_Y                                            0xFFFFFFF3
+#define   S_009858_MSAA2_X(x)                                         (((x) & 0x03) << 4)
+#define   G_009858_MSAA2_X(x)                                         (((x) >> 4) & 0x03)
+#define   C_009858_MSAA2_X                                            0xFFFFFFCF
+#define   S_009858_MSAA2_Y(x)                                         (((x) & 0x03) << 6)
+#define   G_009858_MSAA2_Y(x)                                         (((x) >> 6) & 0x03)
+#define   C_009858_MSAA2_Y                                            0xFFFFFF3F
+#define   S_009858_MSAA4_X(x)                                         (((x) & 0x03) << 8)
+#define   G_009858_MSAA4_X(x)                                         (((x) >> 8) & 0x03)
+#define   C_009858_MSAA4_X                                            0xFFFFFCFF
+#define   S_009858_MSAA4_Y(x)                                         (((x) & 0x03) << 10)
+#define   G_009858_MSAA4_Y(x)                                         (((x) >> 10) & 0x03)
+#define   C_009858_MSAA4_Y                                            0xFFFFF3FF
+#define   S_009858_MSAA8_X(x)                                         (((x) & 0x03) << 12)
+#define   G_009858_MSAA8_X(x)                                         (((x) >> 12) & 0x03)
+#define   C_009858_MSAA8_X                                            0xFFFFCFFF
+#define   S_009858_MSAA8_Y(x)                                         (((x) & 0x03) << 14)
+#define   G_009858_MSAA8_Y(x)                                         (((x) >> 14) & 0x03)
+#define   C_009858_MSAA8_Y                                            0xFFFF3FFF
+#define   S_009858_MSAA16_X(x)                                        (((x) & 0x03) << 16)
+#define   G_009858_MSAA16_X(x)                                        (((x) >> 16) & 0x03)
+#define   C_009858_MSAA16_X                                           0xFFFCFFFF
+#define   S_009858_MSAA16_Y(x)                                        (((x) & 0x03) << 18)
+#define   G_009858_MSAA16_Y(x)                                        (((x) >> 18) & 0x03)
+#define   C_009858_MSAA16_Y                                           0xFFF3FFFF
+#define R_009910_GB_TILE_MODE0                                          0x009910
+#define   S_009910_MICRO_TILE_MODE(x)                                 (((x) & 0x03) << 0)
+#define   G_009910_MICRO_TILE_MODE(x)                                 (((x) >> 0) & 0x03)
+#define   C_009910_MICRO_TILE_MODE                                    0xFFFFFFFC
+#define     V_009910_ADDR_SURF_DISPLAY_MICRO_TILING                 0x00
+#define     V_009910_ADDR_SURF_THIN_MICRO_TILING                    0x01
+#define     V_009910_ADDR_SURF_DEPTH_MICRO_TILING                   0x02
+#define     V_009910_ADDR_SURF_THICK_MICRO_TILING                   0x03
+#define   S_009910_ARRAY_MODE(x)                                      (((x) & 0x0F) << 2)
+#define   G_009910_ARRAY_MODE(x)                                      (((x) >> 2) & 0x0F)
+#define   C_009910_ARRAY_MODE                                         0xFFFFFFC3
+#define     V_009910_ARRAY_LINEAR_GENERAL                           0x00
+#define     V_009910_ARRAY_LINEAR_ALIGNED                           0x01
+#define     V_009910_ARRAY_1D_TILED_THIN1                           0x02
+#define     V_009910_ARRAY_1D_TILED_THICK                           0x03
+#define     V_009910_ARRAY_2D_TILED_THIN1                           0x04
+#define     V_009910_ARRAY_2D_TILED_THICK                           0x07
+#define     V_009910_ARRAY_2D_TILED_XTHICK                          0x08
+#define     V_009910_ARRAY_3D_TILED_THIN1                           0x0C
+#define     V_009910_ARRAY_3D_TILED_THICK                           0x0D
+#define     V_009910_ARRAY_3D_TILED_XTHICK                          0x0E
+#define     V_009910_ARRAY_POWER_SAVE                               0x0F
+#define   S_009910_PIPE_CONFIG(x)                                     (((x) & 0x1F) << 6)
+#define   G_009910_PIPE_CONFIG(x)                                     (((x) >> 6) & 0x1F)
+#define   C_009910_PIPE_CONFIG                                        0xFFFFF83F
+#define     V_009910_ADDR_SURF_P2                                   0x00
+#define     V_009910_ADDR_SURF_P2_RESERVED0                         0x01
+#define     V_009910_ADDR_SURF_P2_RESERVED1                         0x02
+#define     V_009910_ADDR_SURF_P2_RESERVED2                         0x03
+#define     V_009910_X_ADDR_SURF_P4_8X16                            0x04
+#define     V_009910_X_ADDR_SURF_P4_16X16                           0x05
+#define     V_009910_X_ADDR_SURF_P4_16X32                           0x06
+#define     V_009910_X_ADDR_SURF_P4_32X32                           0x07
+#define     V_009910_X_ADDR_SURF_P8_16X16_8X16                      0x08
+#define     V_009910_X_ADDR_SURF_P8_16X32_8X16                      0x09
+#define     V_009910_X_ADDR_SURF_P8_32X32_8X16                      0x0A
+#define     V_009910_X_ADDR_SURF_P8_16X32_16X16                     0x0B
+#define     V_009910_X_ADDR_SURF_P8_32X32_16X16                     0x0C
+#define     V_009910_X_ADDR_SURF_P8_32X32_16X32                     0x0D
+#define     V_009910_X_ADDR_SURF_P8_32X64_32X32                     0x0E
+#define   S_009910_TILE_SPLIT(x)                                      (((x) & 0x07) << 11)
+#define   G_009910_TILE_SPLIT(x)                                      (((x) >> 11) & 0x07)
+#define   C_009910_TILE_SPLIT                                         0xFFFFC7FF
+#define     V_009910_ADDR_SURF_TILE_SPLIT_64B                       0x00
+#define     V_009910_ADDR_SURF_TILE_SPLIT_128B                      0x01
+#define     V_009910_ADDR_SURF_TILE_SPLIT_256B                      0x02
+#define     V_009910_ADDR_SURF_TILE_SPLIT_512B                      0x03
+#define     V_009910_ADDR_SURF_TILE_SPLIT_1KB                       0x04
+#define     V_009910_ADDR_SURF_TILE_SPLIT_2KB                       0x05
+#define     V_009910_ADDR_SURF_TILE_SPLIT_4KB                       0x06
+#define   S_009910_BANK_WIDTH(x)                                      (((x) & 0x03) << 14)
+#define   G_009910_BANK_WIDTH(x)                                      (((x) >> 14) & 0x03)
+#define   C_009910_BANK_WIDTH                                         0xFFFF3FFF
+#define     V_009910_ADDR_SURF_BANK_WIDTH_1                         0x00
+#define     V_009910_ADDR_SURF_BANK_WIDTH_2                         0x01
+#define     V_009910_ADDR_SURF_BANK_WIDTH_4                         0x02
+#define     V_009910_ADDR_SURF_BANK_WIDTH_8                         0x03
+#define   S_009910_BANK_HEIGHT(x)                                     (((x) & 0x03) << 16)
+#define   G_009910_BANK_HEIGHT(x)                                     (((x) >> 16) & 0x03)
+#define   C_009910_BANK_HEIGHT                                        0xFFFCFFFF
+#define     V_009910_ADDR_SURF_BANK_HEIGHT_1                        0x00
+#define     V_009910_ADDR_SURF_BANK_HEIGHT_2                        0x01
+#define     V_009910_ADDR_SURF_BANK_HEIGHT_4                        0x02
+#define     V_009910_ADDR_SURF_BANK_HEIGHT_8                        0x03
+#define   S_009910_MACRO_TILE_ASPECT(x)                               (((x) & 0x03) << 18)
+#define   G_009910_MACRO_TILE_ASPECT(x)                               (((x) >> 18) & 0x03)
+#define   C_009910_MACRO_TILE_ASPECT                                  0xFFF3FFFF
+#define     V_009910_ADDR_SURF_MACRO_ASPECT_1                       0x00
+#define     V_009910_ADDR_SURF_MACRO_ASPECT_2                       0x01
+#define     V_009910_ADDR_SURF_MACRO_ASPECT_4                       0x02
+#define     V_009910_ADDR_SURF_MACRO_ASPECT_8                       0x03
+#define   S_009910_NUM_BANKS(x)                                       (((x) & 0x03) << 20)
+#define   G_009910_NUM_BANKS(x)                                       (((x) >> 20) & 0x03)
+#define   C_009910_NUM_BANKS                                          0xFFCFFFFF
+#define     V_009910_ADDR_SURF_2_BANK                               0x00
+#define     V_009910_ADDR_SURF_4_BANK                               0x01
+#define     V_009910_ADDR_SURF_8_BANK                               0x02
+#define     V_009910_ADDR_SURF_16_BANK                              0x03
+/* CIK */
+#define R_00B01C_SPI_SHADER_PGM_RSRC3_PS                                0x00B01C
+#define   S_00B01C_CU_EN(x)                                           (((x) & 0xFFFF) << 0)
+#define   G_00B01C_CU_EN(x)                                           (((x) >> 0) & 0xFFFF)
+#define   C_00B01C_CU_EN                                              0xFFFF0000
+#define   S_00B01C_WAVE_LIMIT(x)                                      (((x) & 0x3F) << 16)
+#define   G_00B01C_WAVE_LIMIT(x)                                      (((x) >> 16) & 0x3F)
+#define   C_00B01C_WAVE_LIMIT                                         0xFFC0FFFF
+#define   S_00B01C_LOCK_LOW_THRESHOLD(x)                              (((x) & 0x0F) << 22)
+#define   G_00B01C_LOCK_LOW_THRESHOLD(x)                              (((x) >> 22) & 0x0F)
+#define   C_00B01C_LOCK_LOW_THRESHOLD                                 0xFC3FFFFF
+/*     */
+#define R_00B020_SPI_SHADER_PGM_LO_PS                                   0x00B020
+#define R_00B024_SPI_SHADER_PGM_HI_PS                                   0x00B024
+#define   S_00B024_MEM_BASE(x)                                        (((x) & 0xFF) << 0)
+#define   G_00B024_MEM_BASE(x)                                        (((x) >> 0) & 0xFF)
+#define   C_00B024_MEM_BASE                                           0xFFFFFF00
+#define R_00B028_SPI_SHADER_PGM_RSRC1_PS                                0x00B028
+#define   S_00B028_VGPRS(x)                                           (((x) & 0x3F) << 0)
+#define   G_00B028_VGPRS(x)                                           (((x) >> 0) & 0x3F)
+#define   C_00B028_VGPRS                                              0xFFFFFFC0
+#define   S_00B028_SGPRS(x)                                           (((x) & 0x0F) << 6)
+#define   G_00B028_SGPRS(x)                                           (((x) >> 6) & 0x0F)
+#define   C_00B028_SGPRS                                              0xFFFFFC3F
+#define   S_00B028_PRIORITY(x)                                        (((x) & 0x03) << 10)
+#define   G_00B028_PRIORITY(x)                                        (((x) >> 10) & 0x03)
+#define   C_00B028_PRIORITY                                           0xFFFFF3FF
+#define   S_00B028_FLOAT_MODE(x)                                      (((x) & 0xFF) << 12)
+#define   G_00B028_FLOAT_MODE(x)                                      (((x) >> 12) & 0xFF)
+#define   C_00B028_FLOAT_MODE                                         0xFFF00FFF
+#define   S_00B028_PRIV(x)                                            (((x) & 0x1) << 20)
+#define   G_00B028_PRIV(x)                                            (((x) >> 20) & 0x1)
+#define   C_00B028_PRIV                                               0xFFEFFFFF
+#define   S_00B028_DX10_CLAMP(x)                                      (((x) & 0x1) << 21)
+#define   G_00B028_DX10_CLAMP(x)                                      (((x) >> 21) & 0x1)
+#define   C_00B028_DX10_CLAMP                                         0xFFDFFFFF
+#define   S_00B028_DEBUG_MODE(x)                                      (((x) & 0x1) << 22)
+#define   G_00B028_DEBUG_MODE(x)                                      (((x) >> 22) & 0x1)
+#define   C_00B028_DEBUG_MODE                                         0xFFBFFFFF
+#define   S_00B028_IEEE_MODE(x)                                       (((x) & 0x1) << 23)
+#define   G_00B028_IEEE_MODE(x)                                       (((x) >> 23) & 0x1)
+#define   C_00B028_IEEE_MODE                                          0xFF7FFFFF
+#define   S_00B028_CU_GROUP_DISABLE(x)                                (((x) & 0x1) << 24)
+#define   G_00B028_CU_GROUP_DISABLE(x)                                (((x) >> 24) & 0x1)
+#define   C_00B028_CU_GROUP_DISABLE                                   0xFEFFFFFF
+/* CIK */
+#define   S_00B028_CACHE_CTL(x)                                       (((x) & 0x07) << 25)
+#define   G_00B028_CACHE_CTL(x)                                       (((x) >> 25) & 0x07)
+#define   C_00B028_CACHE_CTL                                          0xF1FFFFFF
+#define   S_00B028_CDBG_USER(x)                                       (((x) & 0x1) << 28)
+#define   G_00B028_CDBG_USER(x)                                       (((x) >> 28) & 0x1)
+#define   C_00B028_CDBG_USER                                          0xEFFFFFFF
+/*    */
+#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS                                0x00B02C
+#define   S_00B02C_SCRATCH_EN(x)                                      (((x) & 0x1) << 0)
+#define   G_00B02C_SCRATCH_EN(x)                                      (((x) >> 0) & 0x1)
+#define   C_00B02C_SCRATCH_EN                                         0xFFFFFFFE
+#define   S_00B02C_USER_SGPR(x)                                       (((x) & 0x1F) << 1)
+#define   G_00B02C_USER_SGPR(x)                                       (((x) >> 1) & 0x1F)
+#define   C_00B02C_USER_SGPR                                          0xFFFFFFC1
+#define   S_00B02C_WAVE_CNT_EN(x)                                     (((x) & 0x1) << 7)
+#define   G_00B02C_WAVE_CNT_EN(x)                                     (((x) >> 7) & 0x1)
+#define   C_00B02C_WAVE_CNT_EN                                        0xFFFFFF7F
+#define   S_00B02C_EXTRA_LDS_SIZE(x)                                  (((x) & 0xFF) << 8)
+#define   G_00B02C_EXTRA_LDS_SIZE(x)                                  (((x) >> 8) & 0xFF)
+#define   C_00B02C_EXTRA_LDS_SIZE                                     0xFFFF00FF
+#define   S_00B02C_EXCP_EN(x)                                         (((x) & 0x7F) << 16) /* mask is 0x1FF on CIK */
+#define   G_00B02C_EXCP_EN(x)                                         (((x) >> 16) & 0x7F) /* mask is 0x1FF on CIK */
+#define   C_00B02C_EXCP_EN                                            0xFF80FFFF /* mask is 0x1FF on CIK */
+#define R_00B030_SPI_SHADER_USER_DATA_PS_0                              0x00B030
+#define R_00B034_SPI_SHADER_USER_DATA_PS_1                              0x00B034
+#define R_00B038_SPI_SHADER_USER_DATA_PS_2                              0x00B038
+#define R_00B03C_SPI_SHADER_USER_DATA_PS_3                              0x00B03C
+#define R_00B040_SPI_SHADER_USER_DATA_PS_4                              0x00B040
+#define R_00B044_SPI_SHADER_USER_DATA_PS_5                              0x00B044
+#define R_00B048_SPI_SHADER_USER_DATA_PS_6                              0x00B048
+#define R_00B04C_SPI_SHADER_USER_DATA_PS_7                              0x00B04C
+#define R_00B050_SPI_SHADER_USER_DATA_PS_8                              0x00B050
+#define R_00B054_SPI_SHADER_USER_DATA_PS_9                              0x00B054
+#define R_00B058_SPI_SHADER_USER_DATA_PS_10                             0x00B058
+#define R_00B05C_SPI_SHADER_USER_DATA_PS_11                             0x00B05C
+#define R_00B060_SPI_SHADER_USER_DATA_PS_12                             0x00B060
+#define R_00B064_SPI_SHADER_USER_DATA_PS_13                             0x00B064
+#define R_00B068_SPI_SHADER_USER_DATA_PS_14                             0x00B068
+#define R_00B06C_SPI_SHADER_USER_DATA_PS_15                             0x00B06C
+/* CIK */
+#define R_00B118_SPI_SHADER_PGM_RSRC3_VS                                0x00B118
+#define   S_00B118_CU_EN(x)                                           (((x) & 0xFFFF) << 0)
+#define   G_00B118_CU_EN(x)                                           (((x) >> 0) & 0xFFFF)
+#define   C_00B118_CU_EN                                              0xFFFF0000
+#define   S_00B118_WAVE_LIMIT(x)                                      (((x) & 0x3F) << 16)
+#define   G_00B118_WAVE_LIMIT(x)                                      (((x) >> 16) & 0x3F)
+#define   C_00B118_WAVE_LIMIT                                         0xFFC0FFFF
+#define   S_00B118_LOCK_LOW_THRESHOLD(x)                              (((x) & 0x0F) << 22)
+#define   G_00B118_LOCK_LOW_THRESHOLD(x)                              (((x) >> 22) & 0x0F)
+#define   C_00B118_LOCK_LOW_THRESHOLD                                 0xFC3FFFFF
+#define R_00B11C_SPI_SHADER_LATE_ALLOC_VS                               0x00B11C
+#define   S_00B11C_LIMIT(x)                                           (((x) & 0x3F) << 0)
+#define   G_00B11C_LIMIT(x)                                           (((x) >> 0) & 0x3F)
+#define   C_00B11C_LIMIT                                              0xFFFFFFC0
+/*     */
+#define R_00B120_SPI_SHADER_PGM_LO_VS                                   0x00B120
+#define R_00B124_SPI_SHADER_PGM_HI_VS                                   0x00B124
+#define   S_00B124_MEM_BASE(x)                                        (((x) & 0xFF) << 0)
+#define   G_00B124_MEM_BASE(x)                                        (((x) >> 0) & 0xFF)
+#define   C_00B124_MEM_BASE                                           0xFFFFFF00
+#define R_00B128_SPI_SHADER_PGM_RSRC1_VS                                0x00B128
+#define   S_00B128_VGPRS(x)                                           (((x) & 0x3F) << 0)
+#define   G_00B128_VGPRS(x)                                           (((x) >> 0) & 0x3F)
+#define   C_00B128_VGPRS                                              0xFFFFFFC0
+#define   S_00B128_SGPRS(x)                                           (((x) & 0x0F) << 6)
+#define   G_00B128_SGPRS(x)                                           (((x) >> 6) & 0x0F)
+#define   C_00B128_SGPRS                                              0xFFFFFC3F
+#define   S_00B128_PRIORITY(x)                                        (((x) & 0x03) << 10)
+#define   G_00B128_PRIORITY(x)                                        (((x) >> 10) & 0x03)
+#define   C_00B128_PRIORITY                                           0xFFFFF3FF
+#define   S_00B128_FLOAT_MODE(x)                                      (((x) & 0xFF) << 12)
+#define   G_00B128_FLOAT_MODE(x)                                      (((x) >> 12) & 0xFF)
+#define   C_00B128_FLOAT_MODE                                         0xFFF00FFF
+#define   S_00B128_PRIV(x)                                            (((x) & 0x1) << 20)
+#define   G_00B128_PRIV(x)                                            (((x) >> 20) & 0x1)
+#define   C_00B128_PRIV                                               0xFFEFFFFF
+#define   S_00B128_DX10_CLAMP(x)                                      (((x) & 0x1) << 21)
+#define   G_00B128_DX10_CLAMP(x)                                      (((x) >> 21) & 0x1)
+#define   C_00B128_DX10_CLAMP                                         0xFFDFFFFF
+#define   S_00B128_DEBUG_MODE(x)                                      (((x) & 0x1) << 22)
+#define   G_00B128_DEBUG_MODE(x)                                      (((x) >> 22) & 0x1)
+#define   C_00B128_DEBUG_MODE                                         0xFFBFFFFF
+#define   S_00B128_IEEE_MODE(x)                                       (((x) & 0x1) << 23)
+#define   G_00B128_IEEE_MODE(x)                                       (((x) >> 23) & 0x1)
+#define   C_00B128_IEEE_MODE                                          0xFF7FFFFF
+#define   S_00B128_VGPR_COMP_CNT(x)                                   (((x) & 0x03) << 24)
+#define   G_00B128_VGPR_COMP_CNT(x)                                   (((x) >> 24) & 0x03)
+#define   C_00B128_VGPR_COMP_CNT                                      0xFCFFFFFF
+#define   S_00B128_CU_GROUP_ENABLE(x)                                 (((x) & 0x1) << 26)
+#define   G_00B128_CU_GROUP_ENABLE(x)                                 (((x) >> 26) & 0x1)
+#define   C_00B128_CU_GROUP_ENABLE                                    0xFBFFFFFF
+/* CIK */
+#define   S_00B128_CACHE_CTL(x)                                       (((x) & 0x07) << 27)
+#define   G_00B128_CACHE_CTL(x)                                       (((x) >> 27) & 0x07)
+#define   C_00B128_CACHE_CTL                                          0xC7FFFFFF
+#define   S_00B128_CDBG_USER(x)                                       (((x) & 0x1) << 30)
+#define   G_00B128_CDBG_USER(x)                                       (((x) >> 30) & 0x1)
+#define   C_00B128_CDBG_USER                                          0xBFFFFFFF
+/*    */
+#define R_00B12C_SPI_SHADER_PGM_RSRC2_VS                                0x00B12C
+#define   S_00B12C_SCRATCH_EN(x)                                      (((x) & 0x1) << 0)
+#define   G_00B12C_SCRATCH_EN(x)                                      (((x) >> 0) & 0x1)
+#define   C_00B12C_SCRATCH_EN                                         0xFFFFFFFE
+#define   S_00B12C_USER_SGPR(x)                                       (((x) & 0x1F) << 1)
+#define   G_00B12C_USER_SGPR(x)                                       (((x) >> 1) & 0x1F)
+#define   C_00B12C_USER_SGPR                                          0xFFFFFFC1
+#define   S_00B12C_OC_LDS_EN(x)                                       (((x) & 0x1) << 7)
+#define   G_00B12C_OC_LDS_EN(x)                                       (((x) >> 7) & 0x1)
+#define   C_00B12C_OC_LDS_EN                                          0xFFFFFF7F
+#define   S_00B12C_SO_BASE0_EN(x)                                     (((x) & 0x1) << 8)
+#define   G_00B12C_SO_BASE0_EN(x)                                     (((x) >> 8) & 0x1)
+#define   C_00B12C_SO_BASE0_EN                                        0xFFFFFEFF
+#define   S_00B12C_SO_BASE1_EN(x)                                     (((x) & 0x1) << 9)
+#define   G_00B12C_SO_BASE1_EN(x)                                     (((x) >> 9) & 0x1)
+#define   C_00B12C_SO_BASE1_EN                                        0xFFFFFDFF
+#define   S_00B12C_SO_BASE2_EN(x)                                     (((x) & 0x1) << 10)
+#define   G_00B12C_SO_BASE2_EN(x)                                     (((x) >> 10) & 0x1)
+#define   C_00B12C_SO_BASE2_EN                                        0xFFFFFBFF
+#define   S_00B12C_SO_BASE3_EN(x)                                     (((x) & 0x1) << 11)
+#define   G_00B12C_SO_BASE3_EN(x)                                     (((x) >> 11) & 0x1)
+#define   C_00B12C_SO_BASE3_EN                                        0xFFFFF7FF
+#define   S_00B12C_SO_EN(x)                                           (((x) & 0x1) << 12)
+#define   G_00B12C_SO_EN(x)                                           (((x) >> 12) & 0x1)
+#define   C_00B12C_SO_EN                                              0xFFFFEFFF
+#define   S_00B12C_EXCP_EN(x)                                         (((x) & 0x7F) << 13) /* mask is 0x1FF on CIK */
+#define   G_00B12C_EXCP_EN(x)                                         (((x) >> 13) & 0x7F) /* mask is 0x1FF on CIK */
+#define   C_00B12C_EXCP_EN                                            0xFFF01FFF /* mask is 0x1FF on CIK */
+#define R_00B130_SPI_SHADER_USER_DATA_VS_0                              0x00B130
+#define R_00B134_SPI_SHADER_USER_DATA_VS_1                              0x00B134
+#define R_00B138_SPI_SHADER_USER_DATA_VS_2                              0x00B138
+#define R_00B13C_SPI_SHADER_USER_DATA_VS_3                              0x00B13C
+#define R_00B140_SPI_SHADER_USER_DATA_VS_4                              0x00B140
+#define R_00B144_SPI_SHADER_USER_DATA_VS_5                              0x00B144
+#define R_00B148_SPI_SHADER_USER_DATA_VS_6                              0x00B148
+#define R_00B14C_SPI_SHADER_USER_DATA_VS_7                              0x00B14C
+#define R_00B150_SPI_SHADER_USER_DATA_VS_8                              0x00B150
+#define R_00B154_SPI_SHADER_USER_DATA_VS_9                              0x00B154
+#define R_00B158_SPI_SHADER_USER_DATA_VS_10                             0x00B158
+#define R_00B15C_SPI_SHADER_USER_DATA_VS_11                             0x00B15C
+#define R_00B160_SPI_SHADER_USER_DATA_VS_12                             0x00B160
+#define R_00B164_SPI_SHADER_USER_DATA_VS_13                             0x00B164
+#define R_00B168_SPI_SHADER_USER_DATA_VS_14                             0x00B168
+#define R_00B16C_SPI_SHADER_USER_DATA_VS_15                             0x00B16C
+/* CIK */
+#define R_00B21C_SPI_SHADER_PGM_RSRC3_GS                                0x00B21C
+#define   S_00B21C_CU_EN(x)                                           (((x) & 0xFFFF) << 0)
+#define   G_00B21C_CU_EN(x)                                           (((x) >> 0) & 0xFFFF)
+#define   C_00B21C_CU_EN                                              0xFFFF0000
+#define   S_00B21C_WAVE_LIMIT(x)                                      (((x) & 0x3F) << 16)
+#define   G_00B21C_WAVE_LIMIT(x)                                      (((x) >> 16) & 0x3F)
+#define   C_00B21C_WAVE_LIMIT                                         0xFFC0FFFF
+#define   S_00B21C_LOCK_LOW_THRESHOLD(x)                              (((x) & 0x0F) << 22)
+#define   G_00B21C_LOCK_LOW_THRESHOLD(x)                              (((x) >> 22) & 0x0F)
+#define   C_00B21C_LOCK_LOW_THRESHOLD                                 0xFC3FFFFF
+/*     */
+#define R_00B220_SPI_SHADER_PGM_LO_GS                                   0x00B220
+#define R_00B224_SPI_SHADER_PGM_HI_GS                                   0x00B224
+#define   S_00B224_MEM_BASE(x)                                        (((x) & 0xFF) << 0)
+#define   G_00B224_MEM_BASE(x)                                        (((x) >> 0) & 0xFF)
+#define   C_00B224_MEM_BASE                                           0xFFFFFF00
+#define R_00B228_SPI_SHADER_PGM_RSRC1_GS                                0x00B228
+#define   S_00B228_VGPRS(x)                                           (((x) & 0x3F) << 0)
+#define   G_00B228_VGPRS(x)                                           (((x) >> 0) & 0x3F)
+#define   C_00B228_VGPRS                                              0xFFFFFFC0
+#define   S_00B228_SGPRS(x)                                           (((x) & 0x0F) << 6)
+#define   G_00B228_SGPRS(x)                                           (((x) >> 6) & 0x0F)
+#define   C_00B228_SGPRS                                              0xFFFFFC3F
+#define   S_00B228_PRIORITY(x)                                        (((x) & 0x03) << 10)
+#define   G_00B228_PRIORITY(x)                                        (((x) >> 10) & 0x03)
+#define   C_00B228_PRIORITY                                           0xFFFFF3FF
+#define   S_00B228_FLOAT_MODE(x)                                      (((x) & 0xFF) << 12)
+#define   G_00B228_FLOAT_MODE(x)                                      (((x) >> 12) & 0xFF)
+#define   C_00B228_FLOAT_MODE                                         0xFFF00FFF
+#define   S_00B228_PRIV(x)                                            (((x) & 0x1) << 20)
+#define   G_00B228_PRIV(x)                                            (((x) >> 20) & 0x1)
+#define   C_00B228_PRIV                                               0xFFEFFFFF
+#define   S_00B228_DX10_CLAMP(x)                                      (((x) & 0x1) << 21)
+#define   G_00B228_DX10_CLAMP(x)                                      (((x) >> 21) & 0x1)
+#define   C_00B228_DX10_CLAMP                                         0xFFDFFFFF
+#define   S_00B228_DEBUG_MODE(x)                                      (((x) & 0x1) << 22)
+#define   G_00B228_DEBUG_MODE(x)                                      (((x) >> 22) & 0x1)
+#define   C_00B228_DEBUG_MODE                                         0xFFBFFFFF
+#define   S_00B228_IEEE_MODE(x)                                       (((x) & 0x1) << 23)
+#define   G_00B228_IEEE_MODE(x)                                       (((x) >> 23) & 0x1)
+#define   C_00B228_IEEE_MODE                                          0xFF7FFFFF
+#define   S_00B228_CU_GROUP_ENABLE(x)                                 (((x) & 0x1) << 24)
+#define   G_00B228_CU_GROUP_ENABLE(x)                                 (((x) >> 24) & 0x1)
+#define   C_00B228_CU_GROUP_ENABLE                                    0xFEFFFFFF
+/* CIK */
+#define   S_00B228_CACHE_CTL(x)                                       (((x) & 0x07) << 25)
+#define   G_00B228_CACHE_CTL(x)                                       (((x) >> 25) & 0x07)
+#define   C_00B228_CACHE_CTL                                          0xF1FFFFFF
+#define   S_00B228_CDBG_USER(x)                                       (((x) & 0x1) << 28)
+#define   G_00B228_CDBG_USER(x)                                       (((x) >> 28) & 0x1)
+#define   C_00B228_CDBG_USER                                          0xEFFFFFFF
+/*     */
+#define R_00B22C_SPI_SHADER_PGM_RSRC2_GS                                0x00B22C
+#define   S_00B22C_SCRATCH_EN(x)                                      (((x) & 0x1) << 0)
+#define   G_00B22C_SCRATCH_EN(x)                                      (((x) >> 0) & 0x1)
+#define   C_00B22C_SCRATCH_EN                                         0xFFFFFFFE
+#define   S_00B22C_USER_SGPR(x)                                       (((x) & 0x1F) << 1)
+#define   G_00B22C_USER_SGPR(x)                                       (((x) >> 1) & 0x1F)
+#define   C_00B22C_USER_SGPR                                          0xFFFFFFC1
+#define   S_00B22C_EXCP_EN(x)                                         (((x) & 0x7F) << 7) /* mask is 0x1FF on CIK */
+#define   G_00B22C_EXCP_EN(x)                                         (((x) >> 7) & 0x7F) /* mask is 0x1FF on CIK */
+#define   C_00B22C_EXCP_EN                                            0xFFFFC07F /* mask is 0x1FF on CIK */
+#define R_00B230_SPI_SHADER_USER_DATA_GS_0                              0x00B230
+/* CIK */
+#define R_00B31C_SPI_SHADER_PGM_RSRC3_ES                                0x00B31C
+#define   S_00B31C_CU_EN(x)                                           (((x) & 0xFFFF) << 0)
+#define   G_00B31C_CU_EN(x)                                           (((x) >> 0) & 0xFFFF)
+#define   C_00B31C_CU_EN                                              0xFFFF0000
+#define   S_00B31C_WAVE_LIMIT(x)                                      (((x) & 0x3F) << 16)
+#define   G_00B31C_WAVE_LIMIT(x)                                      (((x) >> 16) & 0x3F)
+#define   C_00B31C_WAVE_LIMIT                                         0xFFC0FFFF
+#define   S_00B31C_LOCK_LOW_THRESHOLD(x)                              (((x) & 0x0F) << 22)
+#define   G_00B31C_LOCK_LOW_THRESHOLD(x)                              (((x) >> 22) & 0x0F)
+#define   C_00B31C_LOCK_LOW_THRESHOLD                                 0xFC3FFFFF
+/*     */
+#define R_00B320_SPI_SHADER_PGM_LO_ES                                   0x00B320
+#define R_00B324_SPI_SHADER_PGM_HI_ES                                   0x00B324
+#define   S_00B324_MEM_BASE(x)                                        (((x) & 0xFF) << 0)
+#define   G_00B324_MEM_BASE(x)                                        (((x) >> 0) & 0xFF)
+#define   C_00B324_MEM_BASE                                           0xFFFFFF00
+#define R_00B328_SPI_SHADER_PGM_RSRC1_ES                                0x00B328
+#define   S_00B328_VGPRS(x)                                           (((x) & 0x3F) << 0)
+#define   G_00B328_VGPRS(x)                                           (((x) >> 0) & 0x3F)
+#define   C_00B328_VGPRS                                              0xFFFFFFC0
+#define   S_00B328_SGPRS(x)                                           (((x) & 0x0F) << 6)
+#define   G_00B328_SGPRS(x)                                           (((x) >> 6) & 0x0F)
+#define   C_00B328_SGPRS                                              0xFFFFFC3F
+#define   S_00B328_PRIORITY(x)                                        (((x) & 0x03) << 10)
+#define   G_00B328_PRIORITY(x)                                        (((x) >> 10) & 0x03)
+#define   C_00B328_PRIORITY                                           0xFFFFF3FF
+#define   S_00B328_FLOAT_MODE(x)                                      (((x) & 0xFF) << 12)
+#define   G_00B328_FLOAT_MODE(x)                                      (((x) >> 12) & 0xFF)
+#define   C_00B328_FLOAT_MODE                                         0xFFF00FFF
+#define   S_00B328_PRIV(x)                                            (((x) & 0x1) << 20)
+#define   G_00B328_PRIV(x)                                            (((x) >> 20) & 0x1)
+#define   C_00B328_PRIV                                               0xFFEFFFFF
+#define   S_00B328_DX10_CLAMP(x)                                      (((x) & 0x1) << 21)
+#define   G_00B328_DX10_CLAMP(x)                                      (((x) >> 21) & 0x1)
+#define   C_00B328_DX10_CLAMP                                         0xFFDFFFFF
+#define   S_00B328_DEBUG_MODE(x)                                      (((x) & 0x1) << 22)
+#define   G_00B328_DEBUG_MODE(x)                                      (((x) >> 22) & 0x1)
+#define   C_00B328_DEBUG_MODE                                         0xFFBFFFFF
+#define   S_00B328_IEEE_MODE(x)                                       (((x) & 0x1) << 23)
+#define   G_00B328_IEEE_MODE(x)                                       (((x) >> 23) & 0x1)
+#define   C_00B328_IEEE_MODE                                          0xFF7FFFFF
+#define   S_00B328_VGPR_COMP_CNT(x)                                   (((x) & 0x03) << 24)
+#define   G_00B328_VGPR_COMP_CNT(x)                                   (((x) >> 24) & 0x03)
+#define   C_00B328_VGPR_COMP_CNT                                      0xFCFFFFFF
+#define   S_00B328_CU_GROUP_ENABLE(x)                                 (((x) & 0x1) << 26)
+#define   G_00B328_CU_GROUP_ENABLE(x)                                 (((x) >> 26) & 0x1)
+#define   C_00B328_CU_GROUP_ENABLE                                    0xFBFFFFFF
+/* CIK */
+#define   S_00B328_CACHE_CTL(x)                                       (((x) & 0x07) << 27)
+#define   G_00B328_CACHE_CTL(x)                                       (((x) >> 27) & 0x07)
+#define   C_00B328_CACHE_CTL                                          0xC7FFFFFF
+#define   S_00B328_CDBG_USER(x)                                       (((x) & 0x1) << 30)
+#define   G_00B328_CDBG_USER(x)                                       (((x) >> 30) & 0x1)
+#define   C_00B328_CDBG_USER                                          0xBFFFFFFF
+/*     */
+#define R_00B32C_SPI_SHADER_PGM_RSRC2_ES                                0x00B32C
+#define   S_00B32C_SCRATCH_EN(x)                                      (((x) & 0x1) << 0)
+#define   G_00B32C_SCRATCH_EN(x)                                      (((x) >> 0) & 0x1)
+#define   C_00B32C_SCRATCH_EN                                         0xFFFFFFFE
+#define   S_00B32C_USER_SGPR(x)                                       (((x) & 0x1F) << 1)
+#define   G_00B32C_USER_SGPR(x)                                       (((x) >> 1) & 0x1F)
+#define   C_00B32C_USER_SGPR                                          0xFFFFFFC1
+#define   S_00B32C_OC_LDS_EN(x)                                       (((x) & 0x1) << 7)
+#define   G_00B32C_OC_LDS_EN(x)                                       (((x) >> 7) & 0x1)
+#define   C_00B32C_OC_LDS_EN                                          0xFFFFFF7F
+#define   S_00B32C_EXCP_EN(x)                                         (((x) & 0x7F) << 8) /* mask is 0x1FF on CIK */
+#define   G_00B32C_EXCP_EN(x)                                         (((x) >> 8) & 0x7F) /* mask is 0x1FF on CIK */
+#define   C_00B32C_EXCP_EN                                            0xFFFF80FF /* mask is 0x1FF on CIK */
+#define R_00B330_SPI_SHADER_USER_DATA_ES_0                              0x00B330
+/* CIK */
+#define R_00B41C_SPI_SHADER_PGM_RSRC3_HS                                0x00B41C
+#define   S_00B41C_WAVE_LIMIT(x)                                      (((x) & 0x3F) << 0)
+#define   G_00B41C_WAVE_LIMIT(x)                                      (((x) >> 0) & 0x3F)
+#define   C_00B41C_WAVE_LIMIT                                         0xFFFFFFC0
+#define   S_00B41C_LOCK_LOW_THRESHOLD(x)                              (((x) & 0x0F) << 6)
+#define   G_00B41C_LOCK_LOW_THRESHOLD(x)                              (((x) >> 6) & 0x0F)
+#define   C_00B41C_LOCK_LOW_THRESHOLD                                 0xFFFFFC3F
+/*     */
+#define R_00B420_SPI_SHADER_PGM_LO_HS                                   0x00B420
+#define R_00B424_SPI_SHADER_PGM_HI_HS                                   0x00B424
+#define   S_00B424_MEM_BASE(x)                                        (((x) & 0xFF) << 0)
+#define   G_00B424_MEM_BASE(x)                                        (((x) >> 0) & 0xFF)
+#define   C_00B424_MEM_BASE                                           0xFFFFFF00
+#define R_00B428_SPI_SHADER_PGM_RSRC1_HS                                0x00B428
+#define   S_00B428_VGPRS(x)                                           (((x) & 0x3F) << 0)
+#define   G_00B428_VGPRS(x)                                           (((x) >> 0) & 0x3F)
+#define   C_00B428_VGPRS                                              0xFFFFFFC0
+#define   S_00B428_SGPRS(x)                                           (((x) & 0x0F) << 6)
+#define   G_00B428_SGPRS(x)                                           (((x) >> 6) & 0x0F)
+#define   C_00B428_SGPRS                                              0xFFFFFC3F
+#define   S_00B428_PRIORITY(x)                                        (((x) & 0x03) << 10)
+#define   G_00B428_PRIORITY(x)                                        (((x) >> 10) & 0x03)
+#define   C_00B428_PRIORITY                                           0xFFFFF3FF
+#define   S_00B428_FLOAT_MODE(x)                                      (((x) & 0xFF) << 12)
+#define   G_00B428_FLOAT_MODE(x)                                      (((x) >> 12) & 0xFF)
+#define   C_00B428_FLOAT_MODE                                         0xFFF00FFF
+#define   S_00B428_PRIV(x)                                            (((x) & 0x1) << 20)
+#define   G_00B428_PRIV(x)                                            (((x) >> 20) & 0x1)
+#define   C_00B428_PRIV                                               0xFFEFFFFF
+#define   S_00B428_DX10_CLAMP(x)                                      (((x) & 0x1) << 21)
+#define   G_00B428_DX10_CLAMP(x)                                      (((x) >> 21) & 0x1)
+#define   C_00B428_DX10_CLAMP                                         0xFFDFFFFF
+#define   S_00B428_DEBUG_MODE(x)                                      (((x) & 0x1) << 22)
+#define   G_00B428_DEBUG_MODE(x)                                      (((x) >> 22) & 0x1)
+#define   C_00B428_DEBUG_MODE                                         0xFFBFFFFF
+#define   S_00B428_IEEE_MODE(x)                                       (((x) & 0x1) << 23)
+#define   G_00B428_IEEE_MODE(x)                                       (((x) >> 23) & 0x1)
+#define   C_00B428_IEEE_MODE                                          0xFF7FFFFF
+/* CIK */
+#define   S_00B428_CACHE_CTL(x)                                       (((x) & 0x07) << 24)
+#define   G_00B428_CACHE_CTL(x)                                       (((x) >> 24) & 0x07)
+#define   C_00B428_CACHE_CTL                                          0xF8FFFFFF
+#define   S_00B428_CDBG_USER(x)                                       (((x) & 0x1) << 27)
+#define   G_00B428_CDBG_USER(x)                                       (((x) >> 27) & 0x1)
+#define   C_00B428_CDBG_USER                                          0xF7FFFFFF
+/*     */
+#define R_00B42C_SPI_SHADER_PGM_RSRC2_HS                                0x00B42C
+#define   S_00B42C_SCRATCH_EN(x)                                      (((x) & 0x1) << 0)
+#define   G_00B42C_SCRATCH_EN(x)                                      (((x) >> 0) & 0x1)
+#define   C_00B42C_SCRATCH_EN                                         0xFFFFFFFE
+#define   S_00B42C_USER_SGPR(x)                                       (((x) & 0x1F) << 1)
+#define   G_00B42C_USER_SGPR(x)                                       (((x) >> 1) & 0x1F)
+#define   C_00B42C_USER_SGPR                                          0xFFFFFFC1
+#define   S_00B42C_OC_LDS_EN(x)                                       (((x) & 0x1) << 7)
+#define   G_00B42C_OC_LDS_EN(x)                                       (((x) >> 7) & 0x1)
+#define   C_00B42C_OC_LDS_EN                                          0xFFFFFF7F
+#define   S_00B42C_TG_SIZE_EN(x)                                      (((x) & 0x1) << 8)
+#define   G_00B42C_TG_SIZE_EN(x)                                      (((x) >> 8) & 0x1)
+#define   C_00B42C_TG_SIZE_EN                                         0xFFFFFEFF
+#define   S_00B42C_EXCP_EN(x)                                         (((x) & 0x7F) << 9) /* mask is 0x1FF on CIK */
+#define   G_00B42C_EXCP_EN(x)                                         (((x) >> 9) & 0x7F) /* mask is 0x1FF on CIK */
+#define   C_00B42C_EXCP_EN                                            0xFFFF01FF /* mask is 0x1FF on CIK */
+#define R_00B430_SPI_SHADER_USER_DATA_HS_0                              0x00B430
+/* CIK */
+#define R_00B51C_SPI_SHADER_PGM_RSRC3_LS                                0x00B51C
+#define   S_00B51C_CU_EN(x)                                           (((x) & 0xFFFF) << 0)
+#define   G_00B51C_CU_EN(x)                                           (((x) >> 0) & 0xFFFF)
+#define   C_00B51C_CU_EN                                              0xFFFF0000
+#define   S_00B51C_WAVE_LIMIT(x)                                      (((x) & 0x3F) << 16)
+#define   G_00B51C_WAVE_LIMIT(x)                                      (((x) >> 16) & 0x3F)
+#define   C_00B51C_WAVE_LIMIT                                         0xFFC0FFFF
+#define   S_00B51C_LOCK_LOW_THRESHOLD(x)                              (((x) & 0x0F) << 22)
+#define   G_00B51C_LOCK_LOW_THRESHOLD(x)                              (((x) >> 22) & 0x0F)
+#define   C_00B51C_LOCK_LOW_THRESHOLD                                 0xFC3FFFFF
+/*     */
+#define R_00B520_SPI_SHADER_PGM_LO_LS                                   0x00B520
+#define R_00B524_SPI_SHADER_PGM_HI_LS                                   0x00B524
+#define   S_00B524_MEM_BASE(x)                                        (((x) & 0xFF) << 0)
+#define   G_00B524_MEM_BASE(x)                                        (((x) >> 0) & 0xFF)
+#define   C_00B524_MEM_BASE                                           0xFFFFFF00
+#define R_00B528_SPI_SHADER_PGM_RSRC1_LS                                0x00B528
+#define   S_00B528_VGPRS(x)                                           (((x) & 0x3F) << 0)
+#define   G_00B528_VGPRS(x)                                           (((x) >> 0) & 0x3F)
+#define   C_00B528_VGPRS                                              0xFFFFFFC0
+#define   S_00B528_SGPRS(x)                                           (((x) & 0x0F) << 6)
+#define   G_00B528_SGPRS(x)                                           (((x) >> 6) & 0x0F)
+#define   C_00B528_SGPRS                                              0xFFFFFC3F
+#define   S_00B528_PRIORITY(x)                                        (((x) & 0x03) << 10)
+#define   G_00B528_PRIORITY(x)                                        (((x) >> 10) & 0x03)
+#define   C_00B528_PRIORITY                                           0xFFFFF3FF
+#define   S_00B528_FLOAT_MODE(x)                                      (((x) & 0xFF) << 12)
+#define   G_00B528_FLOAT_MODE(x)                                      (((x) >> 12) & 0xFF)
+#define   C_00B528_FLOAT_MODE                                         0xFFF00FFF
+#define   S_00B528_PRIV(x)                                            (((x) & 0x1) << 20)
+#define   G_00B528_PRIV(x)                                            (((x) >> 20) & 0x1)
+#define   C_00B528_PRIV                                               0xFFEFFFFF
+#define   S_00B528_DX10_CLAMP(x)                                      (((x) & 0x1) << 21)
+#define   G_00B528_DX10_CLAMP(x)                                      (((x) >> 21) & 0x1)
+#define   C_00B528_DX10_CLAMP                                         0xFFDFFFFF
+#define   S_00B528_DEBUG_MODE(x)                                      (((x) & 0x1) << 22)
+#define   G_00B528_DEBUG_MODE(x)                                      (((x) >> 22) & 0x1)
+#define   C_00B528_DEBUG_MODE                                         0xFFBFFFFF
+#define   S_00B528_IEEE_MODE(x)                                       (((x) & 0x1) << 23)
+#define   G_00B528_IEEE_MODE(x)                                       (((x) >> 23) & 0x1)
+#define   C_00B528_IEEE_MODE                                          0xFF7FFFFF
+#define   S_00B528_VGPR_COMP_CNT(x)                                   (((x) & 0x03) << 24)
+#define   G_00B528_VGPR_COMP_CNT(x)                                   (((x) >> 24) & 0x03)
+#define   C_00B528_VGPR_COMP_CNT                                      0xFCFFFFFF
+/* CIK */
+#define   S_00B528_CACHE_CTL(x)                                       (((x) & 0x07) << 26)
+#define   G_00B528_CACHE_CTL(x)                                       (((x) >> 26) & 0x07)
+#define   C_00B528_CACHE_CTL                                          0xE3FFFFFF
+#define   S_00B528_CDBG_USER(x)                                       (((x) & 0x1) << 29)
+#define   G_00B528_CDBG_USER(x)                                       (((x) >> 29) & 0x1)
+#define   C_00B528_CDBG_USER                                          0xDFFFFFFF
+/*     */
+#define R_00B52C_SPI_SHADER_PGM_RSRC2_LS                                0x00B52C
+#define   S_00B52C_SCRATCH_EN(x)                                      (((x) & 0x1) << 0)
+#define   G_00B52C_SCRATCH_EN(x)                                      (((x) >> 0) & 0x1)
+#define   C_00B52C_SCRATCH_EN                                         0xFFFFFFFE
+#define   S_00B52C_USER_SGPR(x)                                       (((x) & 0x1F) << 1)
+#define   G_00B52C_USER_SGPR(x)                                       (((x) >> 1) & 0x1F)
+#define   C_00B52C_USER_SGPR                                          0xFFFFFFC1
+#define   S_00B52C_LDS_SIZE(x)                                        (((x) & 0x1FF) << 7)
+#define   G_00B52C_LDS_SIZE(x)                                        (((x) >> 7) & 0x1FF)
+#define   C_00B52C_LDS_SIZE                                           0xFFFF007F
+#define   S_00B52C_EXCP_EN(x)                                         (((x) & 0x7F) << 16) /* mask is 0x1FF on CIK */
+#define   G_00B52C_EXCP_EN(x)                                         (((x) >> 16) & 0x7F) /* mask is 0x1FF on CIK */
+#define   C_00B52C_EXCP_EN                                            0xFF80FFFF /* mask is 0x1FF on CIK */
+#define R_00B530_SPI_SHADER_USER_DATA_LS_0                              0x00B530
+#define R_00B800_COMPUTE_DISPATCH_INITIATOR                             0x00B800
+#define   S_00B800_COMPUTE_SHADER_EN(x)                               (((x) & 0x1) << 0)
+#define   G_00B800_COMPUTE_SHADER_EN(x)                               (((x) >> 0) & 0x1)
+#define   C_00B800_COMPUTE_SHADER_EN                                  0xFFFFFFFE
+#define   S_00B800_PARTIAL_TG_EN(x)                                   (((x) & 0x1) << 1)
+#define   G_00B800_PARTIAL_TG_EN(x)                                   (((x) >> 1) & 0x1)
+#define   C_00B800_PARTIAL_TG_EN                                      0xFFFFFFFD
+#define   S_00B800_FORCE_START_AT_000(x)                              (((x) & 0x1) << 2)
+#define   G_00B800_FORCE_START_AT_000(x)                              (((x) >> 2) & 0x1)
+#define   C_00B800_FORCE_START_AT_000                                 0xFFFFFFFB
+#define   S_00B800_ORDERED_APPEND_ENBL(x)                             (((x) & 0x1) << 3)
+#define   G_00B800_ORDERED_APPEND_ENBL(x)                             (((x) >> 3) & 0x1)
+#define   C_00B800_ORDERED_APPEND_ENBL                                0xFFFFFFF7
+/* CIK */
+#define   S_00B800_ORDERED_APPEND_MODE(x)                             (((x) & 0x1) << 4)
+#define   G_00B800_ORDERED_APPEND_MODE(x)                             (((x) >> 4) & 0x1)
+#define   C_00B800_ORDERED_APPEND_MODE                                0xFFFFFFEF
+#define   S_00B800_USE_THREAD_DIMENSIONS(x)                           (((x) & 0x1) << 5)
+#define   G_00B800_USE_THREAD_DIMENSIONS(x)                           (((x) >> 5) & 0x1)
+#define   C_00B800_USE_THREAD_DIMENSIONS                              0xFFFFFFDF
+#define   S_00B800_ORDER_MODE(x)                                      (((x) & 0x1) << 6)
+#define   G_00B800_ORDER_MODE(x)                                      (((x) >> 6) & 0x1)
+#define   C_00B800_ORDER_MODE                                         0xFFFFFFBF
+#define   S_00B800_DISPATCH_CACHE_CNTL(x)                             (((x) & 0x07) << 7)
+#define   G_00B800_DISPATCH_CACHE_CNTL(x)                             (((x) >> 7) & 0x07)
+#define   C_00B800_DISPATCH_CACHE_CNTL                                0xFFFFFC7F
+#define   S_00B800_SCALAR_L1_INV_VOL(x)                               (((x) & 0x1) << 10)
+#define   G_00B800_SCALAR_L1_INV_VOL(x)                               (((x) >> 10) & 0x1)
+#define   C_00B800_SCALAR_L1_INV_VOL                                  0xFFFFFBFF
+#define   S_00B800_VECTOR_L1_INV_VOL(x)                               (((x) & 0x1) << 11)
+#define   G_00B800_VECTOR_L1_INV_VOL(x)                               (((x) >> 11) & 0x1)
+#define   C_00B800_VECTOR_L1_INV_VOL                                  0xFFFFF7FF
+#define   S_00B800_DATA_ATC(x)                                        (((x) & 0x1) << 12)
+#define   G_00B800_DATA_ATC(x)                                        (((x) >> 12) & 0x1)
+#define   C_00B800_DATA_ATC                                           0xFFFFEFFF
+#define   S_00B800_RESTORE(x)                                         (((x) & 0x1) << 14)
+#define   G_00B800_RESTORE(x)                                         (((x) >> 14) & 0x1)
+#define   C_00B800_RESTORE                                            0xFFFFBFFF
+/*     */
+#define R_00B804_COMPUTE_DIM_X                                          0x00B804
+#define R_00B808_COMPUTE_DIM_Y                                          0x00B808
+#define R_00B80C_COMPUTE_DIM_Z                                          0x00B80C
+#define R_00B810_COMPUTE_START_X                                        0x00B810
+#define R_00B814_COMPUTE_START_Y                                        0x00B814
+#define R_00B818_COMPUTE_START_Z                                        0x00B818
+#define R_00B81C_COMPUTE_NUM_THREAD_X                                   0x00B81C
+#define   S_00B81C_NUM_THREAD_FULL(x)                                 (((x) & 0xFFFF) << 0)
+#define   G_00B81C_NUM_THREAD_FULL(x)                                 (((x) >> 0) & 0xFFFF)
+#define   C_00B81C_NUM_THREAD_FULL                                    0xFFFF0000
+#define   S_00B81C_NUM_THREAD_PARTIAL(x)                              (((x) & 0xFFFF) << 16)
+#define   G_00B81C_NUM_THREAD_PARTIAL(x)                              (((x) >> 16) & 0xFFFF)
+#define   C_00B81C_NUM_THREAD_PARTIAL                                 0x0000FFFF
+#define R_00B820_COMPUTE_NUM_THREAD_Y                                   0x00B820
+#define   S_00B820_NUM_THREAD_FULL(x)                                 (((x) & 0xFFFF) << 0)
+#define   G_00B820_NUM_THREAD_FULL(x)                                 (((x) >> 0) & 0xFFFF)
+#define   C_00B820_NUM_THREAD_FULL                                    0xFFFF0000
+#define   S_00B820_NUM_THREAD_PARTIAL(x)                              (((x) & 0xFFFF) << 16)
+#define   G_00B820_NUM_THREAD_PARTIAL(x)                              (((x) >> 16) & 0xFFFF)
+#define   C_00B820_NUM_THREAD_PARTIAL                                 0x0000FFFF
+#define R_00B824_COMPUTE_NUM_THREAD_Z                                   0x00B824
+#define   S_00B824_NUM_THREAD_FULL(x)                                 (((x) & 0xFFFF) << 0)
+#define   G_00B824_NUM_THREAD_FULL(x)                                 (((x) >> 0) & 0xFFFF)
+#define   C_00B824_NUM_THREAD_FULL                                    0xFFFF0000
+#define   S_00B824_NUM_THREAD_PARTIAL(x)                              (((x) & 0xFFFF) << 16)
+#define   G_00B824_NUM_THREAD_PARTIAL(x)                              (((x) >> 16) & 0xFFFF)
+#define   C_00B824_NUM_THREAD_PARTIAL                                 0x0000FFFF
+#define R_00B82C_COMPUTE_MAX_WAVE_ID                                    0x00B82C /* moved to 0xCD20 on CIK */
+#define   S_00B82C_MAX_WAVE_ID(x)                                     (((x) & 0xFFF) << 0)
+#define   G_00B82C_MAX_WAVE_ID(x)                                     (((x) >> 0) & 0xFFF)
+#define   C_00B82C_MAX_WAVE_ID                                        0xFFFFF000
+#define R_00B830_COMPUTE_PGM_LO                                         0x00B830
+#define R_00B834_COMPUTE_PGM_HI                                         0x00B834
+#define   S_00B834_DATA(x)                                            (((x) & 0xFF) << 0)
+#define   G_00B834_DATA(x)                                            (((x) >> 0) & 0xFF)
+#define   C_00B834_DATA                                               0xFFFFFF00
+/* CIK */
+#define   S_00B834_INST_ATC(x)                                        (((x) & 0x1) << 8)
+#define   G_00B834_INST_ATC(x)                                        (((x) >> 8) & 0x1)
+#define   C_00B834_INST_ATC                                           0xFFFFFEFF
+/*     */
+#define R_00B848_COMPUTE_PGM_RSRC1                                      0x00B848
+#define   S_00B848_VGPRS(x)                                           (((x) & 0x3F) << 0)
+#define   G_00B848_VGPRS(x)                                           (((x) >> 0) & 0x3F)
+#define   C_00B848_VGPRS                                              0xFFFFFFC0
+#define   S_00B848_SGPRS(x)                                           (((x) & 0x0F) << 6)
+#define   G_00B848_SGPRS(x)                                           (((x) >> 6) & 0x0F)
+#define   C_00B848_SGPRS                                              0xFFFFFC3F
+#define   S_00B848_PRIORITY(x)                                        (((x) & 0x03) << 10)
+#define   G_00B848_PRIORITY(x)                                        (((x) >> 10) & 0x03)
+#define   C_00B848_PRIORITY                                           0xFFFFF3FF
+#define   S_00B848_FLOAT_MODE(x)                                      (((x) & 0xFF) << 12)
+#define   G_00B848_FLOAT_MODE(x)                                      (((x) >> 12) & 0xFF)
+#define   C_00B848_FLOAT_MODE                                         0xFFF00FFF
+#define   S_00B848_PRIV(x)                                            (((x) & 0x1) << 20)
+#define   G_00B848_PRIV(x)                                            (((x) >> 20) & 0x1)
+#define   C_00B848_PRIV                                               0xFFEFFFFF
+#define   S_00B848_DX10_CLAMP(x)                                      (((x) & 0x1) << 21)
+#define   G_00B848_DX10_CLAMP(x)                                      (((x) >> 21) & 0x1)
+#define   C_00B848_DX10_CLAMP                                         0xFFDFFFFF
+#define   S_00B848_DEBUG_MODE(x)                                      (((x) & 0x1) << 22)
+#define   G_00B848_DEBUG_MODE(x)                                      (((x) >> 22) & 0x1)
+#define   C_00B848_DEBUG_MODE                                         0xFFBFFFFF
+#define   S_00B848_IEEE_MODE(x)                                       (((x) & 0x1) << 23)
+#define   G_00B848_IEEE_MODE(x)                                       (((x) >> 23) & 0x1)
+#define   C_00B848_IEEE_MODE                                          0xFF7FFFFF
+/* CIK */
+#define   S_00B848_BULKY(x)                                           (((x) & 0x1) << 24)
+#define   G_00B848_BULKY(x)                                           (((x) >> 24) & 0x1)
+#define   C_00B848_BULKY                                              0xFEFFFFFF
+#define   S_00B848_CDBG_USER(x)                                       (((x) & 0x1) << 25)
+#define   G_00B848_CDBG_USER(x)                                       (((x) >> 25) & 0x1)
+#define   C_00B848_CDBG_USER                                          0xFDFFFFFF
+/*     */
+#define R_00B84C_COMPUTE_PGM_RSRC2                                      0x00B84C
+#define   S_00B84C_SCRATCH_EN(x)                                      (((x) & 0x1) << 0)
+#define   G_00B84C_SCRATCH_EN(x)                                      (((x) >> 0) & 0x1)
+#define   C_00B84C_SCRATCH_EN                                         0xFFFFFFFE
+#define   S_00B84C_USER_SGPR(x)                                       (((x) & 0x1F) << 1)
+#define   G_00B84C_USER_SGPR(x)                                       (((x) >> 1) & 0x1F)
+#define   C_00B84C_USER_SGPR                                          0xFFFFFFC1
+#define   S_00B84C_TGID_X_EN(x)                                       (((x) & 0x1) << 7)
+#define   G_00B84C_TGID_X_EN(x)                                       (((x) >> 7) & 0x1)
+#define   C_00B84C_TGID_X_EN                                          0xFFFFFF7F
+#define   S_00B84C_TGID_Y_EN(x)                                       (((x) & 0x1) << 8)
+#define   G_00B84C_TGID_Y_EN(x)                                       (((x) >> 8) & 0x1)
+#define   C_00B84C_TGID_Y_EN                                          0xFFFFFEFF
+#define   S_00B84C_TGID_Z_EN(x)                                       (((x) & 0x1) << 9)
+#define   G_00B84C_TGID_Z_EN(x)                                       (((x) >> 9) & 0x1)
+#define   C_00B84C_TGID_Z_EN                                          0xFFFFFDFF
+#define   S_00B84C_TG_SIZE_EN(x)                                      (((x) & 0x1) << 10)
+#define   G_00B84C_TG_SIZE_EN(x)                                      (((x) >> 10) & 0x1)
+#define   C_00B84C_TG_SIZE_EN                                         0xFFFFFBFF
+#define   S_00B84C_TIDIG_COMP_CNT(x)                                  (((x) & 0x03) << 11)
+#define   G_00B84C_TIDIG_COMP_CNT(x)                                  (((x) >> 11) & 0x03)
+#define   C_00B84C_TIDIG_COMP_CNT                                     0xFFFFE7FF
+/* CIK */
+#define   S_00B84C_EXCP_EN_MSB(x)                                     (((x) & 0x03) << 13)
+#define   G_00B84C_EXCP_EN_MSB(x)                                     (((x) >> 13) & 0x03)
+#define   C_00B84C_EXCP_EN_MSB                                        0xFFFF9FFF
+/*     */
+#define   S_00B84C_LDS_SIZE(x)                                        (((x) & 0x1FF) << 15)
+#define   G_00B84C_LDS_SIZE(x)                                        (((x) >> 15) & 0x1FF)
+#define   C_00B84C_LDS_SIZE                                           0xFF007FFF
+#define   S_00B84C_EXCP_EN(x)                                         (((x) & 0x7F) << 24)
+#define   G_00B84C_EXCP_EN(x)                                         (((x) >> 24) & 0x7F)
+#define   C_00B84C_EXCP_EN                                            0x80FFFFFF
+#define R_00B854_COMPUTE_RESOURCE_LIMITS                                0x00B854
+#define   S_00B854_WAVES_PER_SH(x)                                    (((x) & 0x3F) << 0) /* mask is 0x3FF on CIK */
+#define   G_00B854_WAVES_PER_SH(x)                                    (((x) >> 0) & 0x3F) /* mask is 0x3FF on CIK */
+#define   C_00B854_WAVES_PER_SH                                       0xFFFFFFC0 /* mask is 0x3FF on CIK */
+#define   S_00B854_TG_PER_CU(x)                                       (((x) & 0x0F) << 12)
+#define   G_00B854_TG_PER_CU(x)                                       (((x) >> 12) & 0x0F)
+#define   C_00B854_TG_PER_CU                                          0xFFFF0FFF
+#define   S_00B854_LOCK_THRESHOLD(x)                                  (((x) & 0x3F) << 16)
+#define   G_00B854_LOCK_THRESHOLD(x)                                  (((x) >> 16) & 0x3F)
+#define   C_00B854_LOCK_THRESHOLD                                     0xFFC0FFFF
+#define   S_00B854_SIMD_DEST_CNTL(x)                                  (((x) & 0x1) << 22)
+#define   G_00B854_SIMD_DEST_CNTL(x)                                  (((x) >> 22) & 0x1)
+#define   C_00B854_SIMD_DEST_CNTL                                     0xFFBFFFFF
+/* CIK */
+#define   S_00B854_FORCE_SIMD_DIST(x)                                 (((x) & 0x1) << 23)
+#define   G_00B854_FORCE_SIMD_DIST(x)                                 (((x) >> 23) & 0x1)
+#define   C_00B854_FORCE_SIMD_DIST                                    0xFF7FFFFF
+#define   S_00B854_CU_GROUP_COUNT(x)                                  (((x) & 0x07) << 24)
+#define   G_00B854_CU_GROUP_COUNT(x)                                  (((x) >> 24) & 0x07)
+#define   C_00B854_CU_GROUP_COUNT                                     0xF8FFFFFF
+/*     */
+#define R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0                         0x00B858
+#define   S_00B858_SH0_CU_EN(x)                                       (((x) & 0xFFFF) << 0)
+#define   G_00B858_SH0_CU_EN(x)                                       (((x) >> 0) & 0xFFFF)
+#define   C_00B858_SH0_CU_EN                                          0xFFFF0000
+#define   S_00B858_SH1_CU_EN(x)                                       (((x) & 0xFFFF) << 16)
+#define   G_00B858_SH1_CU_EN(x)                                       (((x) >> 16) & 0xFFFF)
+#define   C_00B858_SH1_CU_EN                                          0x0000FFFF
+#define R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1                         0x00B85C
+#define   S_00B85C_SH0_CU_EN(x)                                       (((x) & 0xFFFF) << 0)
+#define   G_00B85C_SH0_CU_EN(x)                                       (((x) >> 0) & 0xFFFF)
+#define   C_00B85C_SH0_CU_EN                                          0xFFFF0000
+#define   S_00B85C_SH1_CU_EN(x)                                       (((x) & 0xFFFF) << 16)
+#define   G_00B85C_SH1_CU_EN(x)                                       (((x) >> 16) & 0xFFFF)
+#define   C_00B85C_SH1_CU_EN                                          0x0000FFFF
+#define R_00B860_COMPUTE_TMPRING_SIZE                                   0x00B860
+#define   S_00B860_WAVES(x)                                           (((x) & 0xFFF) << 0)
+#define   G_00B860_WAVES(x)                                           (((x) >> 0) & 0xFFF)
+#define   C_00B860_WAVES                                              0xFFFFF000
+#define   S_00B860_WAVESIZE(x)                                        (((x) & 0x1FFF) << 12)
+#define   G_00B860_WAVESIZE(x)                                        (((x) >> 12) & 0x1FFF)
+#define   C_00B860_WAVESIZE                                           0xFE000FFF
+#define R_00B900_COMPUTE_USER_DATA_0                                    0x00B900
+#define R_028000_DB_RENDER_CONTROL                                      0x028000
+#define   S_028000_DEPTH_CLEAR_ENABLE(x)                              (((x) & 0x1) << 0)
+#define   G_028000_DEPTH_CLEAR_ENABLE(x)                              (((x) >> 0) & 0x1)
+#define   C_028000_DEPTH_CLEAR_ENABLE                                 0xFFFFFFFE
+#define   S_028000_STENCIL_CLEAR_ENABLE(x)                            (((x) & 0x1) << 1)
+#define   G_028000_STENCIL_CLEAR_ENABLE(x)                            (((x) >> 1) & 0x1)
+#define   C_028000_STENCIL_CLEAR_ENABLE                               0xFFFFFFFD
+#define   S_028000_DEPTH_COPY(x)                                      (((x) & 0x1) << 2)
+#define   G_028000_DEPTH_COPY(x)                                      (((x) >> 2) & 0x1)
+#define   C_028000_DEPTH_COPY                                         0xFFFFFFFB
+#define   S_028000_STENCIL_COPY(x)                                    (((x) & 0x1) << 3)
+#define   G_028000_STENCIL_COPY(x)                                    (((x) >> 3) & 0x1)
+#define   C_028000_STENCIL_COPY                                       0xFFFFFFF7
+#define   S_028000_RESUMMARIZE_ENABLE(x)                              (((x) & 0x1) << 4)
+#define   G_028000_RESUMMARIZE_ENABLE(x)                              (((x) >> 4) & 0x1)
+#define   C_028000_RESUMMARIZE_ENABLE                                 0xFFFFFFEF
+#define   S_028000_STENCIL_COMPRESS_DISABLE(x)                        (((x) & 0x1) << 5)
+#define   G_028000_STENCIL_COMPRESS_DISABLE(x)                        (((x) >> 5) & 0x1)
+#define   C_028000_STENCIL_COMPRESS_DISABLE                           0xFFFFFFDF
+#define   S_028000_DEPTH_COMPRESS_DISABLE(x)                          (((x) & 0x1) << 6)
+#define   G_028000_DEPTH_COMPRESS_DISABLE(x)                          (((x) >> 6) & 0x1)
+#define   C_028000_DEPTH_COMPRESS_DISABLE                             0xFFFFFFBF
+#define   S_028000_COPY_CENTROID(x)                                   (((x) & 0x1) << 7)
+#define   G_028000_COPY_CENTROID(x)                                   (((x) >> 7) & 0x1)
+#define   C_028000_COPY_CENTROID                                      0xFFFFFF7F
+#define   S_028000_COPY_SAMPLE(x)                                     (((x) & 0x0F) << 8)
+#define   G_028000_COPY_SAMPLE(x)                                     (((x) >> 8) & 0x0F)
+#define   C_028000_COPY_SAMPLE                                        0xFFFFF0FF
+#define R_028004_DB_COUNT_CONTROL                                       0x028004
+#define   S_028004_ZPASS_INCREMENT_DISABLE(x)                         (((x) & 0x1) << 0)
+#define   G_028004_ZPASS_INCREMENT_DISABLE(x)                         (((x) >> 0) & 0x1)
+#define   C_028004_ZPASS_INCREMENT_DISABLE                            0xFFFFFFFE
+#define   S_028004_PERFECT_ZPASS_COUNTS(x)                            (((x) & 0x1) << 1)
+#define   G_028004_PERFECT_ZPASS_COUNTS(x)                            (((x) >> 1) & 0x1)
+#define   C_028004_PERFECT_ZPASS_COUNTS                               0xFFFFFFFD
+#define   S_028004_SAMPLE_RATE(x)                                     (((x) & 0x07) << 4)
+#define   G_028004_SAMPLE_RATE(x)                                     (((x) >> 4) & 0x07)
+#define   C_028004_SAMPLE_RATE                                        0xFFFFFF8F
+/* CIK */
+#define   S_028004_ZPASS_ENABLE(x)                                    (((x) & 0x0F) << 8)
+#define   G_028004_ZPASS_ENABLE(x)                                    (((x) >> 8) & 0x0F)
+#define   C_028004_ZPASS_ENABLE                                       0xFFFFF0FF
+#define   S_028004_ZFAIL_ENABLE(x)                                    (((x) & 0x0F) << 12)
+#define   G_028004_ZFAIL_ENABLE(x)                                    (((x) >> 12) & 0x0F)
+#define   C_028004_ZFAIL_ENABLE                                       0xFFFF0FFF
+#define   S_028004_SFAIL_ENABLE(x)                                    (((x) & 0x0F) << 16)
+#define   G_028004_SFAIL_ENABLE(x)                                    (((x) >> 16) & 0x0F)
+#define   C_028004_SFAIL_ENABLE                                       0xFFF0FFFF
+#define   S_028004_DBFAIL_ENABLE(x)                                   (((x) & 0x0F) << 20)
+#define   G_028004_DBFAIL_ENABLE(x)                                   (((x) >> 20) & 0x0F)
+#define   C_028004_DBFAIL_ENABLE                                      0xFF0FFFFF
+#define   S_028004_SLICE_EVEN_ENABLE(x)                               (((x) & 0x0F) << 24)
+#define   G_028004_SLICE_EVEN_ENABLE(x)                               (((x) >> 24) & 0x0F)
+#define   C_028004_SLICE_EVEN_ENABLE                                  0xF0FFFFFF
+#define   S_028004_SLICE_ODD_ENABLE(x)                                (((x) & 0x0F) << 28)
+#define   G_028004_SLICE_ODD_ENABLE(x)                                (((x) >> 28) & 0x0F)
+#define   C_028004_SLICE_ODD_ENABLE                                   0x0FFFFFFF
+/*     */
+#define R_028008_DB_DEPTH_VIEW                                          0x028008
+#define   S_028008_SLICE_START(x)                                     (((x) & 0x7FF) << 0)
+#define   G_028008_SLICE_START(x)                                     (((x) >> 0) & 0x7FF)
+#define   C_028008_SLICE_START                                        0xFFFFF800
+#define   S_028008_SLICE_MAX(x)                                       (((x) & 0x7FF) << 13)
+#define   G_028008_SLICE_MAX(x)                                       (((x) >> 13) & 0x7FF)
+#define   C_028008_SLICE_MAX                                          0xFF001FFF
+#define   S_028008_Z_READ_ONLY(x)                                     (((x) & 0x1) << 24)
+#define   G_028008_Z_READ_ONLY(x)                                     (((x) >> 24) & 0x1)
+#define   C_028008_Z_READ_ONLY                                        0xFEFFFFFF
+#define   S_028008_STENCIL_READ_ONLY(x)                               (((x) & 0x1) << 25)
+#define   G_028008_STENCIL_READ_ONLY(x)                               (((x) >> 25) & 0x1)
+#define   C_028008_STENCIL_READ_ONLY                                  0xFDFFFFFF
+#define R_02800C_DB_RENDER_OVERRIDE                                     0x02800C
+#define   S_02800C_FORCE_HIZ_ENABLE(x)                                (((x) & 0x03) << 0)
+#define   G_02800C_FORCE_HIZ_ENABLE(x)                                (((x) >> 0) & 0x03)
+#define   C_02800C_FORCE_HIZ_ENABLE                                   0xFFFFFFFC
+#define     V_02800C_FORCE_OFF                                      0x00
+#define     V_02800C_FORCE_ENABLE                                   0x01
+#define     V_02800C_FORCE_DISABLE                                  0x02
+#define     V_02800C_FORCE_RESERVED                                 0x03
+#define   S_02800C_FORCE_HIS_ENABLE0(x)                               (((x) & 0x03) << 2)
+#define   G_02800C_FORCE_HIS_ENABLE0(x)                               (((x) >> 2) & 0x03)
+#define   C_02800C_FORCE_HIS_ENABLE0                                  0xFFFFFFF3
+#define     V_02800C_FORCE_OFF                                      0x00
+#define     V_02800C_FORCE_ENABLE                                   0x01
+#define     V_02800C_FORCE_DISABLE                                  0x02
+#define     V_02800C_FORCE_RESERVED                                 0x03
+#define   S_02800C_FORCE_HIS_ENABLE1(x)                               (((x) & 0x03) << 4)
+#define   G_02800C_FORCE_HIS_ENABLE1(x)                               (((x) >> 4) & 0x03)
+#define   C_02800C_FORCE_HIS_ENABLE1                                  0xFFFFFFCF
+#define     V_02800C_FORCE_OFF                                      0x00
+#define     V_02800C_FORCE_ENABLE                                   0x01
+#define     V_02800C_FORCE_DISABLE                                  0x02
+#define     V_02800C_FORCE_RESERVED                                 0x03
+#define   S_02800C_FORCE_SHADER_Z_ORDER(x)                            (((x) & 0x1) << 6)
+#define   G_02800C_FORCE_SHADER_Z_ORDER(x)                            (((x) >> 6) & 0x1)
+#define   C_02800C_FORCE_SHADER_Z_ORDER                               0xFFFFFFBF
+#define   S_02800C_FAST_Z_DISABLE(x)                                  (((x) & 0x1) << 7)
+#define   G_02800C_FAST_Z_DISABLE(x)                                  (((x) >> 7) & 0x1)
+#define   C_02800C_FAST_Z_DISABLE                                     0xFFFFFF7F
+#define   S_02800C_FAST_STENCIL_DISABLE(x)                            (((x) & 0x1) << 8)
+#define   G_02800C_FAST_STENCIL_DISABLE(x)                            (((x) >> 8) & 0x1)
+#define   C_02800C_FAST_STENCIL_DISABLE                               0xFFFFFEFF
+#define   S_02800C_NOOP_CULL_DISABLE(x)                               (((x) & 0x1) << 9)
+#define   G_02800C_NOOP_CULL_DISABLE(x)                               (((x) >> 9) & 0x1)
+#define   C_02800C_NOOP_CULL_DISABLE                                  0xFFFFFDFF
+#define   S_02800C_FORCE_COLOR_KILL(x)                                (((x) & 0x1) << 10)
+#define   G_02800C_FORCE_COLOR_KILL(x)                                (((x) >> 10) & 0x1)
+#define   C_02800C_FORCE_COLOR_KILL                                   0xFFFFFBFF
+#define   S_02800C_FORCE_Z_READ(x)                                    (((x) & 0x1) << 11)
+#define   G_02800C_FORCE_Z_READ(x)                                    (((x) >> 11) & 0x1)
+#define   C_02800C_FORCE_Z_READ                                       0xFFFFF7FF
+#define   S_02800C_FORCE_STENCIL_READ(x)                              (((x) & 0x1) << 12)
+#define   G_02800C_FORCE_STENCIL_READ(x)                              (((x) >> 12) & 0x1)
+#define   C_02800C_FORCE_STENCIL_READ                                 0xFFFFEFFF
+#define   S_02800C_FORCE_FULL_Z_RANGE(x)                              (((x) & 0x03) << 13)
+#define   G_02800C_FORCE_FULL_Z_RANGE(x)                              (((x) >> 13) & 0x03)
+#define   C_02800C_FORCE_FULL_Z_RANGE                                 0xFFFF9FFF
+#define     V_02800C_FORCE_OFF                                      0x00
+#define     V_02800C_FORCE_ENABLE                                   0x01
+#define     V_02800C_FORCE_DISABLE                                  0x02
+#define     V_02800C_FORCE_RESERVED                                 0x03
+#define   S_02800C_FORCE_QC_SMASK_CONFLICT(x)                         (((x) & 0x1) << 15)
+#define   G_02800C_FORCE_QC_SMASK_CONFLICT(x)                         (((x) >> 15) & 0x1)
+#define   C_02800C_FORCE_QC_SMASK_CONFLICT                            0xFFFF7FFF
+#define   S_02800C_DISABLE_VIEWPORT_CLAMP(x)                          (((x) & 0x1) << 16)
+#define   G_02800C_DISABLE_VIEWPORT_CLAMP(x)                          (((x) >> 16) & 0x1)
+#define   C_02800C_DISABLE_VIEWPORT_CLAMP                             0xFFFEFFFF
+#define   S_02800C_IGNORE_SC_ZRANGE(x)                                (((x) & 0x1) << 17)
+#define   G_02800C_IGNORE_SC_ZRANGE(x)                                (((x) >> 17) & 0x1)
+#define   C_02800C_IGNORE_SC_ZRANGE                                   0xFFFDFFFF
+#define   S_02800C_DISABLE_FULLY_COVERED(x)                           (((x) & 0x1) << 18)
+#define   G_02800C_DISABLE_FULLY_COVERED(x)                           (((x) >> 18) & 0x1)
+#define   C_02800C_DISABLE_FULLY_COVERED                              0xFFFBFFFF
+#define   S_02800C_FORCE_Z_LIMIT_SUMM(x)                              (((x) & 0x03) << 19)
+#define   G_02800C_FORCE_Z_LIMIT_SUMM(x)                              (((x) >> 19) & 0x03)
+#define   C_02800C_FORCE_Z_LIMIT_SUMM                                 0xFFE7FFFF
+#define     V_02800C_FORCE_SUMM_OFF                                 0x00
+#define     V_02800C_FORCE_SUMM_MINZ                                0x01
+#define     V_02800C_FORCE_SUMM_MAXZ                                0x02
+#define     V_02800C_FORCE_SUMM_BOTH                                0x03
+#define   S_02800C_MAX_TILES_IN_DTT(x)                                (((x) & 0x1F) << 21)
+#define   G_02800C_MAX_TILES_IN_DTT(x)                                (((x) >> 21) & 0x1F)
+#define   C_02800C_MAX_TILES_IN_DTT                                   0xFC1FFFFF
+#define   S_02800C_DISABLE_TILE_RATE_TILES(x)                         (((x) & 0x1) << 26)
+#define   G_02800C_DISABLE_TILE_RATE_TILES(x)                         (((x) >> 26) & 0x1)
+#define   C_02800C_DISABLE_TILE_RATE_TILES                            0xFBFFFFFF
+#define   S_02800C_FORCE_Z_DIRTY(x)                                   (((x) & 0x1) << 27)
+#define   G_02800C_FORCE_Z_DIRTY(x)                                   (((x) >> 27) & 0x1)
+#define   C_02800C_FORCE_Z_DIRTY                                      0xF7FFFFFF
+#define   S_02800C_FORCE_STENCIL_DIRTY(x)                             (((x) & 0x1) << 28)
+#define   G_02800C_FORCE_STENCIL_DIRTY(x)                             (((x) >> 28) & 0x1)
+#define   C_02800C_FORCE_STENCIL_DIRTY                                0xEFFFFFFF
+#define   S_02800C_FORCE_Z_VALID(x)                                   (((x) & 0x1) << 29)
+#define   G_02800C_FORCE_Z_VALID(x)                                   (((x) >> 29) & 0x1)
+#define   C_02800C_FORCE_Z_VALID                                      0xDFFFFFFF
+#define   S_02800C_FORCE_STENCIL_VALID(x)                             (((x) & 0x1) << 30)
+#define   G_02800C_FORCE_STENCIL_VALID(x)                             (((x) >> 30) & 0x1)
+#define   C_02800C_FORCE_STENCIL_VALID                                0xBFFFFFFF
+#define   S_02800C_PRESERVE_COMPRESSION(x)                            (((x) & 0x1) << 31)
+#define   G_02800C_PRESERVE_COMPRESSION(x)                            (((x) >> 31) & 0x1)
+#define   C_02800C_PRESERVE_COMPRESSION                               0x7FFFFFFF
+#define R_028010_DB_RENDER_OVERRIDE2                                    0x028010
+#define   S_028010_PARTIAL_SQUAD_LAUNCH_CONTROL(x)                    (((x) & 0x03) << 0)
+#define   G_028010_PARTIAL_SQUAD_LAUNCH_CONTROL(x)                    (((x) >> 0) & 0x03)
+#define   C_028010_PARTIAL_SQUAD_LAUNCH_CONTROL                       0xFFFFFFFC
+#define     V_028010_PSLC_AUTO                                      0x00
+#define     V_028010_PSLC_ON_HANG_ONLY                              0x01
+#define     V_028010_PSLC_ASAP                                      0x02
+#define     V_028010_PSLC_COUNTDOWN                                 0x03
+#define   S_028010_PARTIAL_SQUAD_LAUNCH_COUNTDOWN(x)                  (((x) & 0x07) << 2)
+#define   G_028010_PARTIAL_SQUAD_LAUNCH_COUNTDOWN(x)                  (((x) >> 2) & 0x07)
+#define   C_028010_PARTIAL_SQUAD_LAUNCH_COUNTDOWN                     0xFFFFFFE3
+#define   S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(x)             (((x) & 0x1) << 5)
+#define   G_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(x)             (((x) >> 5) & 0x1)
+#define   C_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION                0xFFFFFFDF
+#define   S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(x)              (((x) & 0x1) << 6)
+#define   G_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(x)              (((x) >> 6) & 0x1)
+#define   C_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION                 0xFFFFFFBF
+#define   S_028010_DISABLE_COLOR_ON_VALIDATION(x)                     (((x) & 0x1) << 7)
+#define   G_028010_DISABLE_COLOR_ON_VALIDATION(x)                     (((x) >> 7) & 0x1)
+#define   C_028010_DISABLE_COLOR_ON_VALIDATION                        0xFFFFFF7F
+#define   S_028010_DECOMPRESS_Z_ON_FLUSH(x)                           (((x) & 0x1) << 8)
+#define   G_028010_DECOMPRESS_Z_ON_FLUSH(x)                           (((x) >> 8) & 0x1)
+#define   C_028010_DECOMPRESS_Z_ON_FLUSH                              0xFFFFFEFF
+#define   S_028010_DISABLE_REG_SNOOP(x)                               (((x) & 0x1) << 9)
+#define   G_028010_DISABLE_REG_SNOOP(x)                               (((x) >> 9) & 0x1)
+#define   C_028010_DISABLE_REG_SNOOP                                  0xFFFFFDFF
+#define   S_028010_DEPTH_BOUNDS_HIER_DEPTH_DISABLE(x)                 (((x) & 0x1) << 10)
+#define   G_028010_DEPTH_BOUNDS_HIER_DEPTH_DISABLE(x)                 (((x) >> 10) & 0x1)
+#define   C_028010_DEPTH_BOUNDS_HIER_DEPTH_DISABLE                    0xFFFFFBFF
+/* CIK */
+#define   S_028010_SEPARATE_HIZS_FUNC_ENABLE(x)                       (((x) & 0x1) << 11)
+#define   G_028010_SEPARATE_HIZS_FUNC_ENABLE(x)                       (((x) >> 11) & 0x1)
+#define   C_028010_SEPARATE_HIZS_FUNC_ENABLE                          0xFFFFF7FF
+#define   S_028010_HIZ_ZFUNC(x)                                       (((x) & 0x07) << 12)
+#define   G_028010_HIZ_ZFUNC(x)                                       (((x) >> 12) & 0x07)
+#define   C_028010_HIZ_ZFUNC                                          0xFFFF8FFF
+#define   S_028010_HIS_SFUNC_FF(x)                                    (((x) & 0x07) << 15)
+#define   G_028010_HIS_SFUNC_FF(x)                                    (((x) >> 15) & 0x07)
+#define   C_028010_HIS_SFUNC_FF                                       0xFFFC7FFF
+#define   S_028010_HIS_SFUNC_BF(x)                                    (((x) & 0x07) << 18)
+#define   G_028010_HIS_SFUNC_BF(x)                                    (((x) >> 18) & 0x07)
+#define   C_028010_HIS_SFUNC_BF                                       0xFFE3FFFF
+#define   S_028010_PRESERVE_ZRANGE(x)                                 (((x) & 0x1) << 21)
+#define   G_028010_PRESERVE_ZRANGE(x)                                 (((x) >> 21) & 0x1)
+#define   C_028010_PRESERVE_ZRANGE                                    0xFFDFFFFF
+#define   S_028010_PRESERVE_SRESULTS(x)                               (((x) & 0x1) << 22)
+#define   G_028010_PRESERVE_SRESULTS(x)                               (((x) >> 22) & 0x1)
+#define   C_028010_PRESERVE_SRESULTS                                  0xFFBFFFFF
+#define   S_028010_DISABLE_FAST_PASS(x)                               (((x) & 0x1) << 23)
+#define   G_028010_DISABLE_FAST_PASS(x)                               (((x) >> 23) & 0x1)
+#define   C_028010_DISABLE_FAST_PASS                                  0xFF7FFFFF
+/*     */
+#define R_028014_DB_HTILE_DATA_BASE                                     0x028014
+#define R_028020_DB_DEPTH_BOUNDS_MIN                                    0x028020
+#define R_028024_DB_DEPTH_BOUNDS_MAX                                    0x028024
+#define R_028028_DB_STENCIL_CLEAR                                       0x028028
+#define   S_028028_CLEAR(x)                                           (((x) & 0xFF) << 0)
+#define   G_028028_CLEAR(x)                                           (((x) >> 0) & 0xFF)
+#define   C_028028_CLEAR                                              0xFFFFFF00
+#define R_02802C_DB_DEPTH_CLEAR                                         0x02802C
+#define R_028030_PA_SC_SCREEN_SCISSOR_TL                                0x028030
+#define   S_028030_TL_X(x)                                            (((x) & 0xFFFF) << 0)
+#define   G_028030_TL_X(x)                                            (((x) >> 0) & 0xFFFF)
+#define   C_028030_TL_X                                               0xFFFF0000
+#define   S_028030_TL_Y(x)                                            (((x) & 0xFFFF) << 16)
+#define   G_028030_TL_Y(x)                                            (((x) >> 16) & 0xFFFF)
+#define   C_028030_TL_Y                                               0x0000FFFF
+#define R_028034_PA_SC_SCREEN_SCISSOR_BR                                0x028034
+#define   S_028034_BR_X(x)                                            (((x) & 0xFFFF) << 0)
+#define   G_028034_BR_X(x)                                            (((x) >> 0) & 0xFFFF)
+#define   C_028034_BR_X                                               0xFFFF0000
+#define   S_028034_BR_Y(x)                                            (((x) & 0xFFFF) << 16)
+#define   G_028034_BR_Y(x)                                            (((x) >> 16) & 0xFFFF)
+#define   C_028034_BR_Y                                               0x0000FFFF
+#define R_02803C_DB_DEPTH_INFO                                          0x02803C
+#define   S_02803C_ADDR5_SWIZZLE_MASK(x)                              (((x) & 0x0F) << 0)
+#define   G_02803C_ADDR5_SWIZZLE_MASK(x)                              (((x) >> 0) & 0x0F)
+#define   C_02803C_ADDR5_SWIZZLE_MASK                                 0xFFFFFFF0
+/* CIK */
+#define   S_02803C_ARRAY_MODE(x)                                      (((x) & 0x0F) << 4)
+#define   G_02803C_ARRAY_MODE(x)                                      (((x) >> 4) & 0x0F)
+#define   C_02803C_ARRAY_MODE                                         0xFFFFFF0F
+#define     V_02803C_ARRAY_LINEAR_GENERAL                           0x00
+#define     V_02803C_ARRAY_LINEAR_ALIGNED                           0x01
+#define     V_02803C_ARRAY_1D_TILED_THIN1                           0x02
+#define     V_02803C_ARRAY_2D_TILED_THIN1                           0x04
+#define     V_02803C_ARRAY_PRT_TILED_THIN1                          0x05
+#define     V_02803C_ARRAY_PRT_2D_TILED_THIN1                       0x06
+#define   S_02803C_PIPE_CONFIG(x)                                     (((x) & 0x1F) << 8)
+#define   G_02803C_PIPE_CONFIG(x)                                     (((x) >> 8) & 0x1F)
+#define   C_02803C_PIPE_CONFIG                                        0xFFFFE0FF
+#define     V_02803C_ADDR_SURF_P2                                   0x00
+#define     V_02803C_X_ADDR_SURF_P4_8X16                            0x04
+#define     V_02803C_X_ADDR_SURF_P4_16X16                           0x05
+#define     V_02803C_X_ADDR_SURF_P4_16X32                           0x06
+#define     V_02803C_X_ADDR_SURF_P4_32X32                           0x07
+#define     V_02803C_X_ADDR_SURF_P8_16X16_8X16                      0x08
+#define     V_02803C_X_ADDR_SURF_P8_16X32_8X16                      0x09
+#define     V_02803C_X_ADDR_SURF_P8_32X32_8X16                      0x0A
+#define     V_02803C_X_ADDR_SURF_P8_16X32_16X16                     0x0B
+#define     V_02803C_X_ADDR_SURF_P8_32X32_16X16                     0x0C
+#define     V_02803C_X_ADDR_SURF_P8_32X32_16X32                     0x0D
+#define     V_02803C_X_ADDR_SURF_P8_32X64_32X32                     0x0E
+#define   S_02803C_BANK_WIDTH(x)                                      (((x) & 0x03) << 13)
+#define   G_02803C_BANK_WIDTH(x)                                      (((x) >> 13) & 0x03)
+#define   C_02803C_BANK_WIDTH                                         0xFFFF9FFF
+#define     V_02803C_ADDR_SURF_BANK_WIDTH_1                         0x00
+#define     V_02803C_ADDR_SURF_BANK_WIDTH_2                         0x01
+#define     V_02803C_ADDR_SURF_BANK_WIDTH_4                         0x02
+#define     V_02803C_ADDR_SURF_BANK_WIDTH_8                         0x03
+#define   S_02803C_BANK_HEIGHT(x)                                     (((x) & 0x03) << 15)
+#define   G_02803C_BANK_HEIGHT(x)                                     (((x) >> 15) & 0x03)
+#define   C_02803C_BANK_HEIGHT                                        0xFFFE7FFF
+#define     V_02803C_ADDR_SURF_BANK_HEIGHT_1                        0x00
+#define     V_02803C_ADDR_SURF_BANK_HEIGHT_2                        0x01
+#define     V_02803C_ADDR_SURF_BANK_HEIGHT_4                        0x02
+#define     V_02803C_ADDR_SURF_BANK_HEIGHT_8                        0x03
+#define   S_02803C_MACRO_TILE_ASPECT(x)                               (((x) & 0x03) << 17)
+#define   G_02803C_MACRO_TILE_ASPECT(x)                               (((x) >> 17) & 0x03)
+#define   C_02803C_MACRO_TILE_ASPECT                                  0xFFF9FFFF
+#define     V_02803C_ADDR_SURF_MACRO_ASPECT_1                       0x00
+#define     V_02803C_ADDR_SURF_MACRO_ASPECT_2                       0x01
+#define     V_02803C_ADDR_SURF_MACRO_ASPECT_4                       0x02
+#define     V_02803C_ADDR_SURF_MACRO_ASPECT_8                       0x03
+#define   S_02803C_NUM_BANKS(x)                                       (((x) & 0x03) << 19)
+#define   G_02803C_NUM_BANKS(x)                                       (((x) >> 19) & 0x03)
+#define   C_02803C_NUM_BANKS                                          0xFFE7FFFF
+#define     V_02803C_ADDR_SURF_2_BANK                               0x00
+#define     V_02803C_ADDR_SURF_4_BANK                               0x01
+#define     V_02803C_ADDR_SURF_8_BANK                               0x02
+#define     V_02803C_ADDR_SURF_16_BANK                              0x03
+/*     */
+#define R_028040_DB_Z_INFO                                              0x028040
+#define   S_028040_FORMAT(x)                                          (((x) & 0x03) << 0)
+#define   G_028040_FORMAT(x)                                          (((x) >> 0) & 0x03)
+#define   C_028040_FORMAT                                             0xFFFFFFFC
+#define     V_028040_Z_INVALID                                      0x00
+#define     V_028040_Z_16                                           0x01
+#define     V_028040_Z_24                                           0x02 /* deprecated */
+#define     V_028040_Z_32_FLOAT                                     0x03
+#define   S_028040_NUM_SAMPLES(x)                                     (((x) & 0x03) << 2)
+#define   G_028040_NUM_SAMPLES(x)                                     (((x) >> 2) & 0x03)
+#define   C_028040_NUM_SAMPLES                                        0xFFFFFFF3
+#define   S_028040_TILE_MODE_INDEX(x)                                 (((x) & 0x07) << 20) /* not on CIK */
+#define   G_028040_TILE_MODE_INDEX(x)                                 (((x) >> 20) & 0x07) /* not on CIK */
+#define   C_028040_TILE_MODE_INDEX                                    0xFF8FFFFF /* not on CIK */
+/* CIK */
+#define   S_028040_TILE_SPLIT(x)                                      (((x) & 0x07) << 13)
+#define   G_028040_TILE_SPLIT(x)                                      (((x) >> 13) & 0x07)
+#define   C_028040_TILE_SPLIT                                         0xFFFF1FFF
+#define     V_028040_ADDR_SURF_TILE_SPLIT_64B                       0x00
+#define     V_028040_ADDR_SURF_TILE_SPLIT_128B                      0x01
+#define     V_028040_ADDR_SURF_TILE_SPLIT_256B                      0x02
+#define     V_028040_ADDR_SURF_TILE_SPLIT_512B                      0x03
+#define     V_028040_ADDR_SURF_TILE_SPLIT_1KB                       0x04
+#define     V_028040_ADDR_SURF_TILE_SPLIT_2KB                       0x05
+#define     V_028040_ADDR_SURF_TILE_SPLIT_4KB                       0x06
+/*     */
+#define   S_028040_ALLOW_EXPCLEAR(x)                                  (((x) & 0x1) << 27)
+#define   G_028040_ALLOW_EXPCLEAR(x)                                  (((x) >> 27) & 0x1)
+#define   C_028040_ALLOW_EXPCLEAR                                     0xF7FFFFFF
+#define   S_028040_READ_SIZE(x)                                       (((x) & 0x1) << 28)
+#define   G_028040_READ_SIZE(x)                                       (((x) >> 28) & 0x1)
+#define   C_028040_READ_SIZE                                          0xEFFFFFFF
+#define   S_028040_TILE_SURFACE_ENABLE(x)                             (((x) & 0x1) << 29)
+#define   G_028040_TILE_SURFACE_ENABLE(x)                             (((x) >> 29) & 0x1)
+#define   C_028040_TILE_SURFACE_ENABLE                                0xDFFFFFFF
+#define   S_028040_ZRANGE_PRECISION(x)                                (((x) & 0x1) << 31)
+#define   G_028040_ZRANGE_PRECISION(x)                                (((x) >> 31) & 0x1)
+#define   C_028040_ZRANGE_PRECISION                                   0x7FFFFFFF
+#define R_028044_DB_STENCIL_INFO                                        0x028044
+#define   S_028044_FORMAT(x)                                          (((x) & 0x1) << 0)
+#define   G_028044_FORMAT(x)                                          (((x) >> 0) & 0x1)
+#define   C_028044_FORMAT                                             0xFFFFFFFE
+#define     V_028044_STENCIL_INVALID                                0x00
+#define     V_028044_STENCIL_8                                      0x01
+#define   S_028044_TILE_MODE_INDEX(x)                                 (((x) & 0x07) << 20) /* not on CIK */
+#define   G_028044_TILE_MODE_INDEX(x)                                 (((x) >> 20) & 0x07) /* not on CIK */
+#define   C_028044_TILE_MODE_INDEX                                    0xFF8FFFFF /* not on CIK */
+/* CIK */
+#define   S_028044_TILE_SPLIT(x)                                      (((x) & 0x07) << 13)
+#define   G_028044_TILE_SPLIT(x)                                      (((x) >> 13) & 0x07)
+#define   C_028044_TILE_SPLIT                                         0xFFFF1FFF
+#define     V_028044_ADDR_SURF_TILE_SPLIT_64B                       0x00
+#define     V_028044_ADDR_SURF_TILE_SPLIT_128B                      0x01
+#define     V_028044_ADDR_SURF_TILE_SPLIT_256B                      0x02
+#define     V_028044_ADDR_SURF_TILE_SPLIT_512B                      0x03
+#define     V_028044_ADDR_SURF_TILE_SPLIT_1KB                       0x04
+#define     V_028044_ADDR_SURF_TILE_SPLIT_2KB                       0x05
+#define     V_028044_ADDR_SURF_TILE_SPLIT_4KB                       0x06
+/*     */
+#define   S_028044_ALLOW_EXPCLEAR(x)                                  (((x) & 0x1) << 27)
+#define   G_028044_ALLOW_EXPCLEAR(x)                                  (((x) >> 27) & 0x1)
+#define   C_028044_ALLOW_EXPCLEAR                                     0xF7FFFFFF
+#define   S_028044_TILE_STENCIL_DISABLE(x)                            (((x) & 0x1) << 29)
+#define   G_028044_TILE_STENCIL_DISABLE(x)                            (((x) >> 29) & 0x1)
+#define   C_028044_TILE_STENCIL_DISABLE                               0xDFFFFFFF
+#define R_028048_DB_Z_READ_BASE                                         0x028048
+#define R_02804C_DB_STENCIL_READ_BASE                                   0x02804C
+#define R_028050_DB_Z_WRITE_BASE                                        0x028050
+#define R_028054_DB_STENCIL_WRITE_BASE                                  0x028054
+#define R_028058_DB_DEPTH_SIZE                                          0x028058
+#define   S_028058_PITCH_TILE_MAX(x)                                  (((x) & 0x7FF) << 0)
+#define   G_028058_PITCH_TILE_MAX(x)                                  (((x) >> 0) & 0x7FF)
+#define   C_028058_PITCH_TILE_MAX                                     0xFFFFF800
+#define   S_028058_HEIGHT_TILE_MAX(x)                                 (((x) & 0x7FF) << 11)
+#define   G_028058_HEIGHT_TILE_MAX(x)                                 (((x) >> 11) & 0x7FF)
+#define   C_028058_HEIGHT_TILE_MAX                                    0xFFC007FF
+#define R_02805C_DB_DEPTH_SLICE                                         0x02805C
+#define   S_02805C_SLICE_TILE_MAX(x)                                  (((x) & 0x3FFFFF) << 0)
+#define   G_02805C_SLICE_TILE_MAX(x)                                  (((x) >> 0) & 0x3FFFFF)
+#define   C_02805C_SLICE_TILE_MAX                                     0xFFC00000
+#define R_028080_TA_BC_BASE_ADDR                                        0x028080
+/* CIK */
+#define R_028084_TA_BC_BASE_ADDR_HI                                     0x028084
+#define   S_028084_ADDRESS(x)                                         (((x) & 0xFF) << 0)
+#define   G_028084_ADDRESS(x)                                         (((x) >> 0) & 0xFF)
+#define   C_028084_ADDRESS                                            0xFFFFFF00
+/* */
+#define R_028200_PA_SC_WINDOW_OFFSET                                    0x028200
+#define   S_028200_WINDOW_X_OFFSET(x)                                 (((x) & 0xFFFF) << 0)
+#define   G_028200_WINDOW_X_OFFSET(x)                                 (((x) >> 0) & 0xFFFF)
+#define   C_028200_WINDOW_X_OFFSET                                    0xFFFF0000
+#define   S_028200_WINDOW_Y_OFFSET(x)                                 (((x) & 0xFFFF) << 16)
+#define   G_028200_WINDOW_Y_OFFSET(x)                                 (((x) >> 16) & 0xFFFF)
+#define   C_028200_WINDOW_Y_OFFSET                                    0x0000FFFF
+#define R_028204_PA_SC_WINDOW_SCISSOR_TL                                0x028204
+#define   S_028204_TL_X(x)                                            (((x) & 0x7FFF) << 0)
+#define   G_028204_TL_X(x)                                            (((x) >> 0) & 0x7FFF)
+#define   C_028204_TL_X                                               0xFFFF8000
+#define   S_028204_TL_Y(x)                                            (((x) & 0x7FFF) << 16)
+#define   G_028204_TL_Y(x)                                            (((x) >> 16) & 0x7FFF)
+#define   C_028204_TL_Y                                               0x8000FFFF
+#define   S_028204_WINDOW_OFFSET_DISABLE(x)                           (((x) & 0x1) << 31)
+#define   G_028204_WINDOW_OFFSET_DISABLE(x)                           (((x) >> 31) & 0x1)
+#define   C_028204_WINDOW_OFFSET_DISABLE                              0x7FFFFFFF
+#define R_028208_PA_SC_WINDOW_SCISSOR_BR                                0x028208
+#define   S_028208_BR_X(x)                                            (((x) & 0x7FFF) << 0)
+#define   G_028208_BR_X(x)                                            (((x) >> 0) & 0x7FFF)
+#define   C_028208_BR_X                                               0xFFFF8000
+#define   S_028208_BR_Y(x)                                            (((x) & 0x7FFF) << 16)
+#define   G_028208_BR_Y(x)                                            (((x) >> 16) & 0x7FFF)
+#define   C_028208_BR_Y                                               0x8000FFFF
+#define R_02820C_PA_SC_CLIPRECT_RULE                                    0x02820C
+#define   S_02820C_CLIP_RULE(x)                                       (((x) & 0xFFFF) << 0)
+#define   G_02820C_CLIP_RULE(x)                                       (((x) >> 0) & 0xFFFF)
+#define   C_02820C_CLIP_RULE                                          0xFFFF0000
+#define R_028210_PA_SC_CLIPRECT_0_TL                                    0x028210
+#define   S_028210_TL_X(x)                                            (((x) & 0x7FFF) << 0)
+#define   G_028210_TL_X(x)                                            (((x) >> 0) & 0x7FFF)
+#define   C_028210_TL_X                                               0xFFFF8000
+#define   S_028210_TL_Y(x)                                            (((x) & 0x7FFF) << 16)
+#define   G_028210_TL_Y(x)                                            (((x) >> 16) & 0x7FFF)
+#define   C_028210_TL_Y                                               0x8000FFFF
+#define R_028214_PA_SC_CLIPRECT_0_BR                                    0x028214
+#define   S_028214_BR_X(x)                                            (((x) & 0x7FFF) << 0)
+#define   G_028214_BR_X(x)                                            (((x) >> 0) & 0x7FFF)
+#define   C_028214_BR_X                                               0xFFFF8000
+#define   S_028214_BR_Y(x)                                            (((x) & 0x7FFF) << 16)
+#define   G_028214_BR_Y(x)                                            (((x) >> 16) & 0x7FFF)
+#define   C_028214_BR_Y                                               0x8000FFFF
+#define R_028218_PA_SC_CLIPRECT_1_TL                                    0x028218
+#define R_02821C_PA_SC_CLIPRECT_1_BR                                    0x02821C
+#define R_028220_PA_SC_CLIPRECT_2_TL                                    0x028220
+#define R_028224_PA_SC_CLIPRECT_2_BR                                    0x028224
+#define R_028228_PA_SC_CLIPRECT_3_TL                                    0x028228
+#define R_02822C_PA_SC_CLIPRECT_3_BR                                    0x02822C
+#define R_028230_PA_SC_EDGERULE                                         0x028230
+#define   S_028230_ER_TRI(x)                                          (((x) & 0x0F) << 0)
+#define   G_028230_ER_TRI(x)                                          (((x) >> 0) & 0x0F)
+#define   C_028230_ER_TRI                                             0xFFFFFFF0
+#define   S_028230_ER_POINT(x)                                        (((x) & 0x0F) << 4)
+#define   G_028230_ER_POINT(x)                                        (((x) >> 4) & 0x0F)
+#define   C_028230_ER_POINT                                           0xFFFFFF0F
+#define   S_028230_ER_RECT(x)                                         (((x) & 0x0F) << 8)
+#define   G_028230_ER_RECT(x)                                         (((x) >> 8) & 0x0F)
+#define   C_028230_ER_RECT                                            0xFFFFF0FF
+#define   S_028230_ER_LINE_LR(x)                                      (((x) & 0x3F) << 12)
+#define   G_028230_ER_LINE_LR(x)                                      (((x) >> 12) & 0x3F)
+#define   C_028230_ER_LINE_LR                                         0xFFFC0FFF
+#define   S_028230_ER_LINE_RL(x)                                      (((x) & 0x3F) << 18)
+#define   G_028230_ER_LINE_RL(x)                                      (((x) >> 18) & 0x3F)
+#define   C_028230_ER_LINE_RL                                         0xFF03FFFF
+#define   S_028230_ER_LINE_TB(x)                                      (((x) & 0x0F) << 24)
+#define   G_028230_ER_LINE_TB(x)                                      (((x) >> 24) & 0x0F)
+#define   C_028230_ER_LINE_TB                                         0xF0FFFFFF
+#define   S_028230_ER_LINE_BT(x)                                      (((x) & 0x0F) << 28)
+#define   G_028230_ER_LINE_BT(x)                                      (((x) >> 28) & 0x0F)
+#define   C_028230_ER_LINE_BT                                         0x0FFFFFFF
+#define R_028234_PA_SU_HARDWARE_SCREEN_OFFSET                           0x028234
+#define   S_028234_HW_SCREEN_OFFSET_X(x)                              (((x) & 0x1FF) << 0)
+#define   G_028234_HW_SCREEN_OFFSET_X(x)                              (((x) >> 0) & 0x1FF)
+#define   C_028234_HW_SCREEN_OFFSET_X                                 0xFFFFFE00
+#define   S_028234_HW_SCREEN_OFFSET_Y(x)                              (((x) & 0x1FF) << 16)
+#define   G_028234_HW_SCREEN_OFFSET_Y(x)                              (((x) >> 16) & 0x1FF)
+#define   C_028234_HW_SCREEN_OFFSET_Y                                 0xFE00FFFF
+#define R_028238_CB_TARGET_MASK                                         0x028238
+#define   S_028238_TARGET0_ENABLE(x)                                  (((x) & 0x0F) << 0)
+#define   G_028238_TARGET0_ENABLE(x)                                  (((x) >> 0) & 0x0F)
+#define   C_028238_TARGET0_ENABLE                                     0xFFFFFFF0
+#define   S_028238_TARGET1_ENABLE(x)                                  (((x) & 0x0F) << 4)
+#define   G_028238_TARGET1_ENABLE(x)                                  (((x) >> 4) & 0x0F)
+#define   C_028238_TARGET1_ENABLE                                     0xFFFFFF0F
+#define   S_028238_TARGET2_ENABLE(x)                                  (((x) & 0x0F) << 8)
+#define   G_028238_TARGET2_ENABLE(x)                                  (((x) >> 8) & 0x0F)
+#define   C_028238_TARGET2_ENABLE                                     0xFFFFF0FF
+#define   S_028238_TARGET3_ENABLE(x)                                  (((x) & 0x0F) << 12)
+#define   G_028238_TARGET3_ENABLE(x)                                  (((x) >> 12) & 0x0F)
+#define   C_028238_TARGET3_ENABLE                                     0xFFFF0FFF
+#define   S_028238_TARGET4_ENABLE(x)                                  (((x) & 0x0F) << 16)
+#define   G_028238_TARGET4_ENABLE(x)                                  (((x) >> 16) & 0x0F)
+#define   C_028238_TARGET4_ENABLE                                     0xFFF0FFFF
+#define   S_028238_TARGET5_ENABLE(x)                                  (((x) & 0x0F) << 20)
+#define   G_028238_TARGET5_ENABLE(x)                                  (((x) >> 20) & 0x0F)
+#define   C_028238_TARGET5_ENABLE                                     0xFF0FFFFF
+#define   S_028238_TARGET6_ENABLE(x)                                  (((x) & 0x0F) << 24)
+#define   G_028238_TARGET6_ENABLE(x)                                  (((x) >> 24) & 0x0F)
+#define   C_028238_TARGET6_ENABLE                                     0xF0FFFFFF
+#define   S_028238_TARGET7_ENABLE(x)                                  (((x) & 0x0F) << 28)
+#define   G_028238_TARGET7_ENABLE(x)                                  (((x) >> 28) & 0x0F)
+#define   C_028238_TARGET7_ENABLE                                     0x0FFFFFFF
+#define R_02823C_CB_SHADER_MASK                                         0x02823C
+#define   S_02823C_OUTPUT0_ENABLE(x)                                  (((x) & 0x0F) << 0)
+#define   G_02823C_OUTPUT0_ENABLE(x)                                  (((x) >> 0) & 0x0F)
+#define   C_02823C_OUTPUT0_ENABLE                                     0xFFFFFFF0
+#define   S_02823C_OUTPUT1_ENABLE(x)                                  (((x) & 0x0F) << 4)
+#define   G_02823C_OUTPUT1_ENABLE(x)                                  (((x) >> 4) & 0x0F)
+#define   C_02823C_OUTPUT1_ENABLE                                     0xFFFFFF0F
+#define   S_02823C_OUTPUT2_ENABLE(x)                                  (((x) & 0x0F) << 8)
+#define   G_02823C_OUTPUT2_ENABLE(x)                                  (((x) >> 8) & 0x0F)
+#define   C_02823C_OUTPUT2_ENABLE                                     0xFFFFF0FF
+#define   S_02823C_OUTPUT3_ENABLE(x)                                  (((x) & 0x0F) << 12)
+#define   G_02823C_OUTPUT3_ENABLE(x)                                  (((x) >> 12) & 0x0F)
+#define   C_02823C_OUTPUT3_ENABLE                                     0xFFFF0FFF
+#define   S_02823C_OUTPUT4_ENABLE(x)                                  (((x) & 0x0F) << 16)
+#define   G_02823C_OUTPUT4_ENABLE(x)                                  (((x) >> 16) & 0x0F)
+#define   C_02823C_OUTPUT4_ENABLE                                     0xFFF0FFFF
+#define   S_02823C_OUTPUT5_ENABLE(x)                                  (((x) & 0x0F) << 20)
+#define   G_02823C_OUTPUT5_ENABLE(x)                                  (((x) >> 20) & 0x0F)
+#define   C_02823C_OUTPUT5_ENABLE                                     0xFF0FFFFF
+#define   S_02823C_OUTPUT6_ENABLE(x)                                  (((x) & 0x0F) << 24)
+#define   G_02823C_OUTPUT6_ENABLE(x)                                  (((x) >> 24) & 0x0F)
+#define   C_02823C_OUTPUT6_ENABLE                                     0xF0FFFFFF
+#define   S_02823C_OUTPUT7_ENABLE(x)                                  (((x) & 0x0F) << 28)
+#define   G_02823C_OUTPUT7_ENABLE(x)                                  (((x) >> 28) & 0x0F)
+#define   C_02823C_OUTPUT7_ENABLE                                     0x0FFFFFFF
+#define R_028240_PA_SC_GENERIC_SCISSOR_TL                               0x028240
+#define   S_028240_TL_X(x)                                            (((x) & 0x7FFF) << 0)
+#define   G_028240_TL_X(x)                                            (((x) >> 0) & 0x7FFF)
+#define   C_028240_TL_X                                               0xFFFF8000
+#define   S_028240_TL_Y(x)                                            (((x) & 0x7FFF) << 16)
+#define   G_028240_TL_Y(x)                                            (((x) >> 16) & 0x7FFF)
+#define   C_028240_TL_Y                                               0x8000FFFF
+#define   S_028240_WINDOW_OFFSET_DISABLE(x)                           (((x) & 0x1) << 31)
+#define   G_028240_WINDOW_OFFSET_DISABLE(x)                           (((x) >> 31) & 0x1)
+#define   C_028240_WINDOW_OFFSET_DISABLE                              0x7FFFFFFF
+#define R_028244_PA_SC_GENERIC_SCISSOR_BR                               0x028244
+#define   S_028244_BR_X(x)                                            (((x) & 0x7FFF) << 0)
+#define   G_028244_BR_X(x)                                            (((x) >> 0) & 0x7FFF)
+#define   C_028244_BR_X                                               0xFFFF8000
+#define   S_028244_BR_Y(x)                                            (((x) & 0x7FFF) << 16)
+#define   G_028244_BR_Y(x)                                            (((x) >> 16) & 0x7FFF)
+#define   C_028244_BR_Y                                               0x8000FFFF
+#define R_028250_PA_SC_VPORT_SCISSOR_0_TL                               0x028250
+#define   S_028250_TL_X(x)                                            (((x) & 0x7FFF) << 0)
+#define   G_028250_TL_X(x)                                            (((x) >> 0) & 0x7FFF)
+#define   C_028250_TL_X                                               0xFFFF8000
+#define   S_028250_TL_Y(x)                                            (((x) & 0x7FFF) << 16)
+#define   G_028250_TL_Y(x)                                            (((x) >> 16) & 0x7FFF)
+#define   C_028250_TL_Y                                               0x8000FFFF
+#define   S_028250_WINDOW_OFFSET_DISABLE(x)                           (((x) & 0x1) << 31)
+#define   G_028250_WINDOW_OFFSET_DISABLE(x)                           (((x) >> 31) & 0x1)
+#define   C_028250_WINDOW_OFFSET_DISABLE                              0x7FFFFFFF
+#define R_028254_PA_SC_VPORT_SCISSOR_0_BR                               0x028254
+#define   S_028254_BR_X(x)                                            (((x) & 0x7FFF) << 0)
+#define   G_028254_BR_X(x)                                            (((x) >> 0) & 0x7FFF)
+#define   C_028254_BR_X                                               0xFFFF8000
+#define   S_028254_BR_Y(x)                                            (((x) & 0x7FFF) << 16)
+#define   G_028254_BR_Y(x)                                            (((x) >> 16) & 0x7FFF)
+#define   C_028254_BR_Y                                               0x8000FFFF
+#define R_0282D0_PA_SC_VPORT_ZMIN_0                                     0x0282D0
+#define R_0282D4_PA_SC_VPORT_ZMAX_0                                     0x0282D4
+#define R_028350_PA_SC_RASTER_CONFIG                                    0x028350
+#define   S_028350_RB_MAP_PKR0(x)                                     (((x) & 0x03) << 0)
+#define   G_028350_RB_MAP_PKR0(x)                                     (((x) >> 0) & 0x03)
+#define   C_028350_RB_MAP_PKR0                                        0xFFFFFFFC
+#define     V_028350_RASTER_CONFIG_RB_MAP_0                         0x00
+#define     V_028350_RASTER_CONFIG_RB_MAP_1                         0x01
+#define     V_028350_RASTER_CONFIG_RB_MAP_2                         0x02
+#define     V_028350_RASTER_CONFIG_RB_MAP_3                         0x03
+#define   S_028350_RB_MAP_PKR1(x)                                     (((x) & 0x03) << 2)
+#define   G_028350_RB_MAP_PKR1(x)                                     (((x) >> 2) & 0x03)
+#define   C_028350_RB_MAP_PKR1                                        0xFFFFFFF3
+#define     V_028350_RASTER_CONFIG_RB_MAP_0                         0x00
+#define     V_028350_RASTER_CONFIG_RB_MAP_1                         0x01
+#define     V_028350_RASTER_CONFIG_RB_MAP_2                         0x02
+#define     V_028350_RASTER_CONFIG_RB_MAP_3                         0x03
+#define   S_028350_RB_XSEL2(x)                                        (((x) & 0x03) << 4)
+#define   G_028350_RB_XSEL2(x)                                        (((x) >> 4) & 0x03)
+#define   C_028350_RB_XSEL2                                           0xFFFFFFCF
+#define     V_028350_RASTER_CONFIG_RB_XSEL2_0                       0x00
+#define     V_028350_RASTER_CONFIG_RB_XSEL2_1                       0x01
+#define     V_028350_RASTER_CONFIG_RB_XSEL2_2                       0x02
+#define     V_028350_RASTER_CONFIG_RB_XSEL2_3                       0x03
+#define   S_028350_RB_XSEL(x)                                         (((x) & 0x1) << 6)
+#define   G_028350_RB_XSEL(x)                                         (((x) >> 6) & 0x1)
+#define   C_028350_RB_XSEL                                            0xFFFFFFBF
+#define   S_028350_RB_YSEL(x)                                         (((x) & 0x1) << 7)
+#define   G_028350_RB_YSEL(x)                                         (((x) >> 7) & 0x1)
+#define   C_028350_RB_YSEL                                            0xFFFFFF7F
+#define   S_028350_PKR_MAP(x)                                         (((x) & 0x03) << 8)
+#define   G_028350_PKR_MAP(x)                                         (((x) >> 8) & 0x03)
+#define   C_028350_PKR_MAP                                            0xFFFFFCFF
+#define     V_028350_RASTER_CONFIG_PKR_MAP_0                        0x00
+#define     V_028350_RASTER_CONFIG_PKR_MAP_1                        0x01
+#define     V_028350_RASTER_CONFIG_PKR_MAP_2                        0x02
+#define     V_028350_RASTER_CONFIG_PKR_MAP_3                        0x03
+#define   S_028350_PKR_XSEL(x)                                        (((x) & 0x03) << 10)
+#define   G_028350_PKR_XSEL(x)                                        (((x) >> 10) & 0x03)
+#define   C_028350_PKR_XSEL                                           0xFFFFF3FF
+#define     V_028350_RASTER_CONFIG_PKR_XSEL_0                       0x00
+#define     V_028350_RASTER_CONFIG_PKR_XSEL_1                       0x01
+#define     V_028350_RASTER_CONFIG_PKR_XSEL_2                       0x02
+#define     V_028350_RASTER_CONFIG_PKR_XSEL_3                       0x03
+#define   S_028350_PKR_YSEL(x)                                        (((x) & 0x03) << 12)
+#define   G_028350_PKR_YSEL(x)                                        (((x) >> 12) & 0x03)
+#define   C_028350_PKR_YSEL                                           0xFFFFCFFF
+#define     V_028350_RASTER_CONFIG_PKR_YSEL_0                       0x00
+#define     V_028350_RASTER_CONFIG_PKR_YSEL_1                       0x01
+#define     V_028350_RASTER_CONFIG_PKR_YSEL_2                       0x02
+#define     V_028350_RASTER_CONFIG_PKR_YSEL_3                       0x03
+#define   S_028350_SC_MAP(x)                                          (((x) & 0x03) << 16)
+#define   G_028350_SC_MAP(x)                                          (((x) >> 16) & 0x03)
+#define   C_028350_SC_MAP                                             0xFFFCFFFF
+#define     V_028350_RASTER_CONFIG_SC_MAP_0                         0x00
+#define     V_028350_RASTER_CONFIG_SC_MAP_1                         0x01
+#define     V_028350_RASTER_CONFIG_SC_MAP_2                         0x02
+#define     V_028350_RASTER_CONFIG_SC_MAP_3                         0x03
+#define   S_028350_SC_XSEL(x)                                         (((x) & 0x03) << 18)
+#define   G_028350_SC_XSEL(x)                                         (((x) >> 18) & 0x03)
+#define   C_028350_SC_XSEL                                            0xFFF3FFFF
+#define     V_028350_RASTER_CONFIG_SC_XSEL_8_WIDE_TILE              0x00
+#define     V_028350_RASTER_CONFIG_SC_XSEL_16_WIDE_TILE             0x01
+#define     V_028350_RASTER_CONFIG_SC_XSEL_32_WIDE_TILE             0x02
+#define     V_028350_RASTER_CONFIG_SC_XSEL_64_WIDE_TILE             0x03
+#define   S_028350_SC_YSEL(x)                                         (((x) & 0x03) << 20)
+#define   G_028350_SC_YSEL(x)                                         (((x) >> 20) & 0x03)
+#define   C_028350_SC_YSEL                                            0xFFCFFFFF
+#define     V_028350_RASTER_CONFIG_SC_YSEL_8_WIDE_TILE              0x00
+#define     V_028350_RASTER_CONFIG_SC_YSEL_16_WIDE_TILE             0x01
+#define     V_028350_RASTER_CONFIG_SC_YSEL_32_WIDE_TILE             0x02
+#define     V_028350_RASTER_CONFIG_SC_YSEL_64_WIDE_TILE             0x03
+#define   S_028350_SE_MAP(x)                                          (((x) & 0x03) << 24)
+#define   G_028350_SE_MAP(x)                                          (((x) >> 24) & 0x03)
+#define   C_028350_SE_MAP                                             0xFCFFFFFF
+#define     V_028350_RASTER_CONFIG_SE_MAP_0                         0x00
+#define     V_028350_RASTER_CONFIG_SE_MAP_1                         0x01
+#define     V_028350_RASTER_CONFIG_SE_MAP_2                         0x02
+#define     V_028350_RASTER_CONFIG_SE_MAP_3                         0x03
+#define   S_028350_SE_XSEL(x)                                         (((x) & 0x03) << 26)
+#define   G_028350_SE_XSEL(x)                                         (((x) >> 26) & 0x03)
+#define   C_028350_SE_XSEL                                            0xF3FFFFFF
+#define     V_028350_RASTER_CONFIG_SE_XSEL_8_WIDE_TILE              0x00
+#define     V_028350_RASTER_CONFIG_SE_XSEL_16_WIDE_TILE             0x01
+#define     V_028350_RASTER_CONFIG_SE_XSEL_32_WIDE_TILE             0x02
+#define     V_028350_RASTER_CONFIG_SE_XSEL_64_WIDE_TILE             0x03
+#define   S_028350_SE_YSEL(x)                                         (((x) & 0x03) << 28)
+#define   G_028350_SE_YSEL(x)                                         (((x) >> 28) & 0x03)
+#define   C_028350_SE_YSEL                                            0xCFFFFFFF
+#define     V_028350_RASTER_CONFIG_SE_YSEL_8_WIDE_TILE              0x00
+#define     V_028350_RASTER_CONFIG_SE_YSEL_16_WIDE_TILE             0x01
+#define     V_028350_RASTER_CONFIG_SE_YSEL_32_WIDE_TILE             0x02
+#define     V_028350_RASTER_CONFIG_SE_YSEL_64_WIDE_TILE             0x03
+/* CIK */
+#define R_028354_PA_SC_RASTER_CONFIG_1                                  0x028354
+#define   S_028354_SE_PAIR_MAP(x)                                     (((x) & 0x03) << 0)
+#define   G_028354_SE_PAIR_MAP(x)                                     (((x) >> 0) & 0x03)
+#define   C_028354_SE_PAIR_MAP                                        0xFFFFFFFC
+#define     V_028354_RASTER_CONFIG_SE_PAIR_MAP_0                    0x00
+#define     V_028354_RASTER_CONFIG_SE_PAIR_MAP_1                    0x01
+#define     V_028354_RASTER_CONFIG_SE_PAIR_MAP_2                    0x02
+#define     V_028354_RASTER_CONFIG_SE_PAIR_MAP_3                    0x03
+#define   S_028354_SE_PAIR_XSEL(x)                                    (((x) & 0x03) << 2)
+#define   G_028354_SE_PAIR_XSEL(x)                                    (((x) >> 2) & 0x03)
+#define   C_028354_SE_PAIR_XSEL                                       0xFFFFFFF3
+#define     V_028354_RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE         0x00
+#define     V_028354_RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE        0x01
+#define     V_028354_RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE        0x02
+#define     V_028354_RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE        0x03
+#define   S_028354_SE_PAIR_YSEL(x)                                    (((x) & 0x03) << 4)
+#define   G_028354_SE_PAIR_YSEL(x)                                    (((x) >> 4) & 0x03)
+#define   C_028354_SE_PAIR_YSEL                                       0xFFFFFFCF
+#define     V_028354_RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE         0x00
+#define     V_028354_RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE        0x01
+#define     V_028354_RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE        0x02
+#define     V_028354_RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE        0x03
+/*     */
+#define R_028400_VGT_MAX_VTX_INDX                                       0x028400
+#define R_028404_VGT_MIN_VTX_INDX                                       0x028404
+#define R_028408_VGT_INDX_OFFSET                                        0x028408
+#define R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX                           0x02840C
+#define R_028414_CB_BLEND_RED                                           0x028414
+#define R_028418_CB_BLEND_GREEN                                         0x028418
+#define R_02841C_CB_BLEND_BLUE                                          0x02841C
+#define R_028420_CB_BLEND_ALPHA                                         0x028420
+#define R_02842C_DB_STENCIL_CONTROL                                     0x02842C
+#define   S_02842C_STENCILFAIL(x)                                     (((x) & 0x0F) << 0)
+#define   G_02842C_STENCILFAIL(x)                                     (((x) >> 0) & 0x0F)
+#define   C_02842C_STENCILFAIL                                        0xFFFFFFF0
+#define     V_02842C_STENCIL_KEEP                                   0x00
+#define     V_02842C_STENCIL_ZERO                                   0x01
+#define     V_02842C_STENCIL_ONES                                   0x02
+#define     V_02842C_STENCIL_REPLACE_TEST                           0x03
+#define     V_02842C_STENCIL_REPLACE_OP                             0x04
+#define     V_02842C_STENCIL_ADD_CLAMP                              0x05
+#define     V_02842C_STENCIL_SUB_CLAMP                              0x06
+#define     V_02842C_STENCIL_INVERT                                 0x07
+#define     V_02842C_STENCIL_ADD_WRAP                               0x08
+#define     V_02842C_STENCIL_SUB_WRAP                               0x09
+#define     V_02842C_STENCIL_AND                                    0x0A
+#define     V_02842C_STENCIL_OR                                     0x0B
+#define     V_02842C_STENCIL_XOR                                    0x0C
+#define     V_02842C_STENCIL_NAND                                   0x0D
+#define     V_02842C_STENCIL_NOR                                    0x0E
+#define     V_02842C_STENCIL_XNOR                                   0x0F
+#define   S_02842C_STENCILZPASS(x)                                    (((x) & 0x0F) << 4)
+#define   G_02842C_STENCILZPASS(x)                                    (((x) >> 4) & 0x0F)
+#define   C_02842C_STENCILZPASS                                       0xFFFFFF0F
+#define     V_02842C_STENCIL_KEEP                                   0x00
+#define     V_02842C_STENCIL_ZERO                                   0x01
+#define     V_02842C_STENCIL_ONES                                   0x02
+#define     V_02842C_STENCIL_REPLACE_TEST                           0x03
+#define     V_02842C_STENCIL_REPLACE_OP                             0x04
+#define     V_02842C_STENCIL_ADD_CLAMP                              0x05
+#define     V_02842C_STENCIL_SUB_CLAMP                              0x06
+#define     V_02842C_STENCIL_INVERT                                 0x07
+#define     V_02842C_STENCIL_ADD_WRAP                               0x08
+#define     V_02842C_STENCIL_SUB_WRAP                               0x09
+#define     V_02842C_STENCIL_AND                                    0x0A
+#define     V_02842C_STENCIL_OR                                     0x0B
+#define     V_02842C_STENCIL_XOR                                    0x0C
+#define     V_02842C_STENCIL_NAND                                   0x0D
+#define     V_02842C_STENCIL_NOR                                    0x0E
+#define     V_02842C_STENCIL_XNOR                                   0x0F
+#define   S_02842C_STENCILZFAIL(x)                                    (((x) & 0x0F) << 8)
+#define   G_02842C_STENCILZFAIL(x)                                    (((x) >> 8) & 0x0F)
+#define   C_02842C_STENCILZFAIL                                       0xFFFFF0FF
+#define     V_02842C_STENCIL_KEEP                                   0x00
+#define     V_02842C_STENCIL_ZERO                                   0x01
+#define     V_02842C_STENCIL_ONES                                   0x02
+#define     V_02842C_STENCIL_REPLACE_TEST                           0x03
+#define     V_02842C_STENCIL_REPLACE_OP                             0x04
+#define     V_02842C_STENCIL_ADD_CLAMP                              0x05
+#define     V_02842C_STENCIL_SUB_CLAMP                              0x06
+#define     V_02842C_STENCIL_INVERT                                 0x07
+#define     V_02842C_STENCIL_ADD_WRAP                               0x08
+#define     V_02842C_STENCIL_SUB_WRAP                               0x09
+#define     V_02842C_STENCIL_AND                                    0x0A
+#define     V_02842C_STENCIL_OR                                     0x0B
+#define     V_02842C_STENCIL_XOR                                    0x0C
+#define     V_02842C_STENCIL_NAND                                   0x0D
+#define     V_02842C_STENCIL_NOR                                    0x0E
+#define     V_02842C_STENCIL_XNOR                                   0x0F
+#define   S_02842C_STENCILFAIL_BF(x)                                  (((x) & 0x0F) << 12)
+#define   G_02842C_STENCILFAIL_BF(x)                                  (((x) >> 12) & 0x0F)
+#define   C_02842C_STENCILFAIL_BF                                     0xFFFF0FFF
+#define     V_02842C_STENCIL_KEEP                                   0x00
+#define     V_02842C_STENCIL_ZERO                                   0x01
+#define     V_02842C_STENCIL_ONES                                   0x02
+#define     V_02842C_STENCIL_REPLACE_TEST                           0x03
+#define     V_02842C_STENCIL_REPLACE_OP                             0x04
+#define     V_02842C_STENCIL_ADD_CLAMP                              0x05
+#define     V_02842C_STENCIL_SUB_CLAMP                              0x06
+#define     V_02842C_STENCIL_INVERT                                 0x07
+#define     V_02842C_STENCIL_ADD_WRAP                               0x08
+#define     V_02842C_STENCIL_SUB_WRAP                               0x09
+#define     V_02842C_STENCIL_AND                                    0x0A
+#define     V_02842C_STENCIL_OR                                     0x0B
+#define     V_02842C_STENCIL_XOR                                    0x0C
+#define     V_02842C_STENCIL_NAND                                   0x0D
+#define     V_02842C_STENCIL_NOR                                    0x0E
+#define     V_02842C_STENCIL_XNOR                                   0x0F
+#define   S_02842C_STENCILZPASS_BF(x)                                 (((x) & 0x0F) << 16)
+#define   G_02842C_STENCILZPASS_BF(x)                                 (((x) >> 16) & 0x0F)
+#define   C_02842C_STENCILZPASS_BF                                    0xFFF0FFFF
+#define     V_02842C_STENCIL_KEEP                                   0x00
+#define     V_02842C_STENCIL_ZERO                                   0x01
+#define     V_02842C_STENCIL_ONES                                   0x02
+#define     V_02842C_STENCIL_REPLACE_TEST                           0x03
+#define     V_02842C_STENCIL_REPLACE_OP                             0x04
+#define     V_02842C_STENCIL_ADD_CLAMP                              0x05
+#define     V_02842C_STENCIL_SUB_CLAMP                              0x06
+#define     V_02842C_STENCIL_INVERT                                 0x07
+#define     V_02842C_STENCIL_ADD_WRAP                               0x08
+#define     V_02842C_STENCIL_SUB_WRAP                               0x09
+#define     V_02842C_STENCIL_AND                                    0x0A
+#define     V_02842C_STENCIL_OR                                     0x0B
+#define     V_02842C_STENCIL_XOR                                    0x0C
+#define     V_02842C_STENCIL_NAND                                   0x0D
+#define     V_02842C_STENCIL_NOR                                    0x0E
+#define     V_02842C_STENCIL_XNOR                                   0x0F
+#define   S_02842C_STENCILZFAIL_BF(x)                                 (((x) & 0x0F) << 20)
+#define   G_02842C_STENCILZFAIL_BF(x)                                 (((x) >> 20) & 0x0F)
+#define   C_02842C_STENCILZFAIL_BF                                    0xFF0FFFFF
+#define     V_02842C_STENCIL_KEEP                                   0x00
+#define     V_02842C_STENCIL_ZERO                                   0x01
+#define     V_02842C_STENCIL_ONES                                   0x02
+#define     V_02842C_STENCIL_REPLACE_TEST                           0x03
+#define     V_02842C_STENCIL_REPLACE_OP                             0x04
+#define     V_02842C_STENCIL_ADD_CLAMP                              0x05
+#define     V_02842C_STENCIL_SUB_CLAMP                              0x06
+#define     V_02842C_STENCIL_INVERT                                 0x07
+#define     V_02842C_STENCIL_ADD_WRAP                               0x08
+#define     V_02842C_STENCIL_SUB_WRAP                               0x09
+#define     V_02842C_STENCIL_AND                                    0x0A
+#define     V_02842C_STENCIL_OR                                     0x0B
+#define     V_02842C_STENCIL_XOR                                    0x0C
+#define     V_02842C_STENCIL_NAND                                   0x0D
+#define     V_02842C_STENCIL_NOR                                    0x0E
+#define     V_02842C_STENCIL_XNOR                                   0x0F
+#define R_028430_DB_STENCILREFMASK                                      0x028430
+#define   S_028430_STENCILTESTVAL(x)                                  (((x) & 0xFF) << 0)
+#define   G_028430_STENCILTESTVAL(x)                                  (((x) >> 0) & 0xFF)
+#define   C_028430_STENCILTESTVAL                                     0xFFFFFF00
+#define   S_028430_STENCILMASK(x)                                     (((x) & 0xFF) << 8)
+#define   G_028430_STENCILMASK(x)                                     (((x) >> 8) & 0xFF)
+#define   C_028430_STENCILMASK                                        0xFFFF00FF
+#define   S_028430_STENCILWRITEMASK(x)                                (((x) & 0xFF) << 16)
+#define   G_028430_STENCILWRITEMASK(x)                                (((x) >> 16) & 0xFF)
+#define   C_028430_STENCILWRITEMASK                                   0xFF00FFFF
+#define   S_028430_STENCILOPVAL(x)                                    (((x) & 0xFF) << 24)
+#define   G_028430_STENCILOPVAL(x)                                    (((x) >> 24) & 0xFF)
+#define   C_028430_STENCILOPVAL                                       0x00FFFFFF
+#define R_028434_DB_STENCILREFMASK_BF                                   0x028434
+#define   S_028434_STENCILTESTVAL_BF(x)                               (((x) & 0xFF) << 0)
+#define   G_028434_STENCILTESTVAL_BF(x)                               (((x) >> 0) & 0xFF)
+#define   C_028434_STENCILTESTVAL_BF                                  0xFFFFFF00
+#define   S_028434_STENCILMASK_BF(x)                                  (((x) & 0xFF) << 8)
+#define   G_028434_STENCILMASK_BF(x)                                  (((x) >> 8) & 0xFF)
+#define   C_028434_STENCILMASK_BF                                     0xFFFF00FF
+#define   S_028434_STENCILWRITEMASK_BF(x)                             (((x) & 0xFF) << 16)
+#define   G_028434_STENCILWRITEMASK_BF(x)                             (((x) >> 16) & 0xFF)
+#define   C_028434_STENCILWRITEMASK_BF                                0xFF00FFFF
+#define   S_028434_STENCILOPVAL_BF(x)                                 (((x) & 0xFF) << 24)
+#define   G_028434_STENCILOPVAL_BF(x)                                 (((x) >> 24) & 0xFF)
+#define   C_028434_STENCILOPVAL_BF                                    0x00FFFFFF
+#define R_02843C_PA_CL_VPORT_XSCALE_0                                   0x02843C
+#define R_028440_PA_CL_VPORT_XOFFSET_0                                  0x028440
+#define R_028444_PA_CL_VPORT_YSCALE_0                                   0x028444
+#define R_028448_PA_CL_VPORT_YOFFSET_0                                  0x028448
+#define R_02844C_PA_CL_VPORT_ZSCALE_0                                   0x02844C
+#define R_028450_PA_CL_VPORT_ZOFFSET_0                                  0x028450
+#define R_0285BC_PA_CL_UCP_0_X                                          0x0285BC
+#define R_0285C0_PA_CL_UCP_0_Y                                          0x0285C0
+#define R_0285C4_PA_CL_UCP_0_Z                                          0x0285C4
+#define R_0285C8_PA_CL_UCP_0_W                                          0x0285C8
+#define R_0285CC_PA_CL_UCP_1_X                                          0x0285CC
+#define R_0285D0_PA_CL_UCP_1_Y                                          0x0285D0
+#define R_0285D4_PA_CL_UCP_1_Z                                          0x0285D4
+#define R_0285D8_PA_CL_UCP_1_W                                          0x0285D8
+#define R_0285DC_PA_CL_UCP_2_X                                          0x0285DC
+#define R_0285E0_PA_CL_UCP_2_Y                                          0x0285E0
+#define R_0285E4_PA_CL_UCP_2_Z                                          0x0285E4
+#define R_0285E8_PA_CL_UCP_2_W                                          0x0285E8
+#define R_0285EC_PA_CL_UCP_3_X                                          0x0285EC
+#define R_0285F0_PA_CL_UCP_3_Y                                          0x0285F0
+#define R_0285F4_PA_CL_UCP_3_Z                                          0x0285F4
+#define R_0285F8_PA_CL_UCP_3_W                                          0x0285F8
+#define R_0285FC_PA_CL_UCP_4_X                                          0x0285FC
+#define R_028600_PA_CL_UCP_4_Y                                          0x028600
+#define R_028604_PA_CL_UCP_4_Z                                          0x028604
+#define R_028608_PA_CL_UCP_4_W                                          0x028608
+#define R_02860C_PA_CL_UCP_5_X                                          0x02860C
+#define R_028610_PA_CL_UCP_5_Y                                          0x028610
+#define R_028614_PA_CL_UCP_5_Z                                          0x028614
+#define R_028618_PA_CL_UCP_5_W                                          0x028618
+#define R_028644_SPI_PS_INPUT_CNTL_0                                    0x028644
+#define   S_028644_OFFSET(x)                                          (((x) & 0x3F) << 0)
+#define   G_028644_OFFSET(x)                                          (((x) >> 0) & 0x3F)
+#define   C_028644_OFFSET                                             0xFFFFFFC0
+#define   S_028644_DEFAULT_VAL(x)                                     (((x) & 0x03) << 8)
+#define   G_028644_DEFAULT_VAL(x)                                     (((x) >> 8) & 0x03)
+#define   C_028644_DEFAULT_VAL                                        0xFFFFFCFF
+#define     V_028644_X_0_0F                                         0x00
+#define   S_028644_FLAT_SHADE(x)                                      (((x) & 0x1) << 10)
+#define   G_028644_FLAT_SHADE(x)                                      (((x) >> 10) & 0x1)
+#define   C_028644_FLAT_SHADE                                         0xFFFFFBFF
+#define   S_028644_CYL_WRAP(x)                                        (((x) & 0x0F) << 13)
+#define   G_028644_CYL_WRAP(x)                                        (((x) >> 13) & 0x0F)
+#define   C_028644_CYL_WRAP                                           0xFFFE1FFF
+#define   S_028644_PT_SPRITE_TEX(x)                                   (((x) & 0x1) << 17)
+#define   G_028644_PT_SPRITE_TEX(x)                                   (((x) >> 17) & 0x1)
+#define   C_028644_PT_SPRITE_TEX                                      0xFFFDFFFF
+/* CIK */
+#define   S_028644_DUP(x)                                             (((x) & 0x1) << 18)
+#define   G_028644_DUP(x)                                             (((x) >> 18) & 0x1)
+#define   C_028644_DUP                                                0xFFFBFFFF
+/*     */
+#define R_028648_SPI_PS_INPUT_CNTL_1                                    0x028648
+#define R_02864C_SPI_PS_INPUT_CNTL_2                                    0x02864C
+#define R_028650_SPI_PS_INPUT_CNTL_3                                    0x028650
+#define R_028654_SPI_PS_INPUT_CNTL_4                                    0x028654
+#define R_028658_SPI_PS_INPUT_CNTL_5                                    0x028658
+#define R_02865C_SPI_PS_INPUT_CNTL_6                                    0x02865C
+#define R_028660_SPI_PS_INPUT_CNTL_7                                    0x028660
+#define R_028664_SPI_PS_INPUT_CNTL_8                                    0x028664
+#define R_028668_SPI_PS_INPUT_CNTL_9                                    0x028668
+#define R_02866C_SPI_PS_INPUT_CNTL_10                                   0x02866C
+#define R_028670_SPI_PS_INPUT_CNTL_11                                   0x028670
+#define R_028674_SPI_PS_INPUT_CNTL_12                                   0x028674
+#define R_028678_SPI_PS_INPUT_CNTL_13                                   0x028678
+#define R_02867C_SPI_PS_INPUT_CNTL_14                                   0x02867C
+#define R_028680_SPI_PS_INPUT_CNTL_15                                   0x028680
+#define R_028684_SPI_PS_INPUT_CNTL_16                                   0x028684
+#define R_028688_SPI_PS_INPUT_CNTL_17                                   0x028688
+#define R_02868C_SPI_PS_INPUT_CNTL_18                                   0x02868C
+#define R_028690_SPI_PS_INPUT_CNTL_19                                   0x028690
+#define R_028694_SPI_PS_INPUT_CNTL_20                                   0x028694
+#define R_028698_SPI_PS_INPUT_CNTL_21                                   0x028698
+#define R_02869C_SPI_PS_INPUT_CNTL_22                                   0x02869C
+#define R_0286A0_SPI_PS_INPUT_CNTL_23                                   0x0286A0
+#define R_0286A4_SPI_PS_INPUT_CNTL_24                                   0x0286A4
+#define R_0286A8_SPI_PS_INPUT_CNTL_25                                   0x0286A8
+#define R_0286AC_SPI_PS_INPUT_CNTL_26                                   0x0286AC
+#define R_0286B0_SPI_PS_INPUT_CNTL_27                                   0x0286B0
+#define R_0286B4_SPI_PS_INPUT_CNTL_28                                   0x0286B4
+#define R_0286B8_SPI_PS_INPUT_CNTL_29                                   0x0286B8
+#define R_0286BC_SPI_PS_INPUT_CNTL_30                                   0x0286BC
+#define R_0286C0_SPI_PS_INPUT_CNTL_31                                   0x0286C0
+#define R_0286C4_SPI_VS_OUT_CONFIG                                      0x0286C4
+#define   S_0286C4_VS_EXPORT_COUNT(x)                                 (((x) & 0x1F) << 1)
+#define   G_0286C4_VS_EXPORT_COUNT(x)                                 (((x) >> 1) & 0x1F)
+#define   C_0286C4_VS_EXPORT_COUNT                                    0xFFFFFFC1
+#define   S_0286C4_VS_HALF_PACK(x)                                    (((x) & 0x1) << 6)
+#define   G_0286C4_VS_HALF_PACK(x)                                    (((x) >> 6) & 0x1)
+#define   C_0286C4_VS_HALF_PACK                                       0xFFFFFFBF
+#define   S_0286C4_VS_EXPORTS_FOG(x)                                  (((x) & 0x1) << 7) /* not on CIK */
+#define   G_0286C4_VS_EXPORTS_FOG(x)                                  (((x) >> 7) & 0x1) /* not on CIK */
+#define   C_0286C4_VS_EXPORTS_FOG                                     0xFFFFFF7F /* not on CIK */
+#define   S_0286C4_VS_OUT_FOG_VEC_ADDR(x)                             (((x) & 0x1F) << 8) /* not on CIK */
+#define   G_0286C4_VS_OUT_FOG_VEC_ADDR(x)                             (((x) >> 8) & 0x1F) /* not on CIK */
+#define   C_0286C4_VS_OUT_FOG_VEC_ADDR                                0xFFFFE0FF /* not on CIK */
+#define R_0286CC_SPI_PS_INPUT_ENA                                       0x0286CC
+#define   S_0286CC_PERSP_SAMPLE_ENA(x)                                (((x) & 0x1) << 0)
+#define   G_0286CC_PERSP_SAMPLE_ENA(x)                                (((x) >> 0) & 0x1)
+#define   C_0286CC_PERSP_SAMPLE_ENA                                   0xFFFFFFFE
+#define   S_0286CC_PERSP_CENTER_ENA(x)                                (((x) & 0x1) << 1)
+#define   G_0286CC_PERSP_CENTER_ENA(x)                                (((x) >> 1) & 0x1)
+#define   C_0286CC_PERSP_CENTER_ENA                                   0xFFFFFFFD
+#define   S_0286CC_PERSP_CENTROID_ENA(x)                              (((x) & 0x1) << 2)
+#define   G_0286CC_PERSP_CENTROID_ENA(x)                              (((x) >> 2) & 0x1)
+#define   C_0286CC_PERSP_CENTROID_ENA                                 0xFFFFFFFB
+#define   S_0286CC_PERSP_PULL_MODEL_ENA(x)                            (((x) & 0x1) << 3)
+#define   G_0286CC_PERSP_PULL_MODEL_ENA(x)                            (((x) >> 3) & 0x1)
+#define   C_0286CC_PERSP_PULL_MODEL_ENA                               0xFFFFFFF7
+#define   S_0286CC_LINEAR_SAMPLE_ENA(x)                               (((x) & 0x1) << 4)
+#define   G_0286CC_LINEAR_SAMPLE_ENA(x)                               (((x) >> 4) & 0x1)
+#define   C_0286CC_LINEAR_SAMPLE_ENA                                  0xFFFFFFEF
+#define   S_0286CC_LINEAR_CENTER_ENA(x)                               (((x) & 0x1) << 5)
+#define   G_0286CC_LINEAR_CENTER_ENA(x)                               (((x) >> 5) & 0x1)
+#define   C_0286CC_LINEAR_CENTER_ENA                                  0xFFFFFFDF
+#define   S_0286CC_LINEAR_CENTROID_ENA(x)                             (((x) & 0x1) << 6)
+#define   G_0286CC_LINEAR_CENTROID_ENA(x)                             (((x) >> 6) & 0x1)
+#define   C_0286CC_LINEAR_CENTROID_ENA                                0xFFFFFFBF
+#define   S_0286CC_LINE_STIPPLE_TEX_ENA(x)                            (((x) & 0x1) << 7)
+#define   G_0286CC_LINE_STIPPLE_TEX_ENA(x)                            (((x) >> 7) & 0x1)
+#define   C_0286CC_LINE_STIPPLE_TEX_ENA                               0xFFFFFF7F
+#define   S_0286CC_POS_X_FLOAT_ENA(x)                                 (((x) & 0x1) << 8)
+#define   G_0286CC_POS_X_FLOAT_ENA(x)                                 (((x) >> 8) & 0x1)
+#define   C_0286CC_POS_X_FLOAT_ENA                                    0xFFFFFEFF
+#define   S_0286CC_POS_Y_FLOAT_ENA(x)                                 (((x) & 0x1) << 9)
+#define   G_0286CC_POS_Y_FLOAT_ENA(x)                                 (((x) >> 9) & 0x1)
+#define   C_0286CC_POS_Y_FLOAT_ENA                                    0xFFFFFDFF
+#define   S_0286CC_POS_Z_FLOAT_ENA(x)                                 (((x) & 0x1) << 10)
+#define   G_0286CC_POS_Z_FLOAT_ENA(x)                                 (((x) >> 10) & 0x1)
+#define   C_0286CC_POS_Z_FLOAT_ENA                                    0xFFFFFBFF
+#define   S_0286CC_POS_W_FLOAT_ENA(x)                                 (((x) & 0x1) << 11)
+#define   G_0286CC_POS_W_FLOAT_ENA(x)                                 (((x) >> 11) & 0x1)
+#define   C_0286CC_POS_W_FLOAT_ENA                                    0xFFFFF7FF
+#define   S_0286CC_FRONT_FACE_ENA(x)                                  (((x) & 0x1) << 12)
+#define   G_0286CC_FRONT_FACE_ENA(x)                                  (((x) >> 12) & 0x1)
+#define   C_0286CC_FRONT_FACE_ENA                                     0xFFFFEFFF
+#define   S_0286CC_ANCILLARY_ENA(x)                                   (((x) & 0x1) << 13)
+#define   G_0286CC_ANCILLARY_ENA(x)                                   (((x) >> 13) & 0x1)
+#define   C_0286CC_ANCILLARY_ENA                                      0xFFFFDFFF
+#define   S_0286CC_SAMPLE_COVERAGE_ENA(x)                             (((x) & 0x1) << 14)
+#define   G_0286CC_SAMPLE_COVERAGE_ENA(x)                             (((x) >> 14) & 0x1)
+#define   C_0286CC_SAMPLE_COVERAGE_ENA                                0xFFFFBFFF
+#define   S_0286CC_POS_FIXED_PT_ENA(x)                                (((x) & 0x1) << 15)
+#define   G_0286CC_POS_FIXED_PT_ENA(x)                                (((x) >> 15) & 0x1)
+#define   C_0286CC_POS_FIXED_PT_ENA                                   0xFFFF7FFF
+#define R_0286D0_SPI_PS_INPUT_ADDR                                      0x0286D0
+#define   S_0286D0_PERSP_SAMPLE_ENA(x)                                (((x) & 0x1) << 0)
+#define   G_0286D0_PERSP_SAMPLE_ENA(x)                                (((x) >> 0) & 0x1)
+#define   C_0286D0_PERSP_SAMPLE_ENA                                   0xFFFFFFFE
+#define   S_0286D0_PERSP_CENTER_ENA(x)                                (((x) & 0x1) << 1)
+#define   G_0286D0_PERSP_CENTER_ENA(x)                                (((x) >> 1) & 0x1)
+#define   C_0286D0_PERSP_CENTER_ENA                                   0xFFFFFFFD
+#define   S_0286D0_PERSP_CENTROID_ENA(x)                              (((x) & 0x1) << 2)
+#define   G_0286D0_PERSP_CENTROID_ENA(x)                              (((x) >> 2) & 0x1)
+#define   C_0286D0_PERSP_CENTROID_ENA                                 0xFFFFFFFB
+#define   S_0286D0_PERSP_PULL_MODEL_ENA(x)                            (((x) & 0x1) << 3)
+#define   G_0286D0_PERSP_PULL_MODEL_ENA(x)                            (((x) >> 3) & 0x1)
+#define   C_0286D0_PERSP_PULL_MODEL_ENA                               0xFFFFFFF7
+#define   S_0286D0_LINEAR_SAMPLE_ENA(x)                               (((x) & 0x1) << 4)
+#define   G_0286D0_LINEAR_SAMPLE_ENA(x)                               (((x) >> 4) & 0x1)
+#define   C_0286D0_LINEAR_SAMPLE_ENA                                  0xFFFFFFEF
+#define   S_0286D0_LINEAR_CENTER_ENA(x)                               (((x) & 0x1) << 5)
+#define   G_0286D0_LINEAR_CENTER_ENA(x)                               (((x) >> 5) & 0x1)
+#define   C_0286D0_LINEAR_CENTER_ENA                                  0xFFFFFFDF
+#define   S_0286D0_LINEAR_CENTROID_ENA(x)                             (((x) & 0x1) << 6)
+#define   G_0286D0_LINEAR_CENTROID_ENA(x)                             (((x) >> 6) & 0x1)
+#define   C_0286D0_LINEAR_CENTROID_ENA                                0xFFFFFFBF
+#define   S_0286D0_LINE_STIPPLE_TEX_ENA(x)                            (((x) & 0x1) << 7)
+#define   G_0286D0_LINE_STIPPLE_TEX_ENA(x)                            (((x) >> 7) & 0x1)
+#define   C_0286D0_LINE_STIPPLE_TEX_ENA                               0xFFFFFF7F
+#define   S_0286D0_POS_X_FLOAT_ENA(x)                                 (((x) & 0x1) << 8)
+#define   G_0286D0_POS_X_FLOAT_ENA(x)                                 (((x) >> 8) & 0x1)
+#define   C_0286D0_POS_X_FLOAT_ENA                                    0xFFFFFEFF
+#define   S_0286D0_POS_Y_FLOAT_ENA(x)                                 (((x) & 0x1) << 9)
+#define   G_0286D0_POS_Y_FLOAT_ENA(x)                                 (((x) >> 9) & 0x1)
+#define   C_0286D0_POS_Y_FLOAT_ENA                                    0xFFFFFDFF
+#define   S_0286D0_POS_Z_FLOAT_ENA(x)                                 (((x) & 0x1) << 10)
+#define   G_0286D0_POS_Z_FLOAT_ENA(x)                                 (((x) >> 10) & 0x1)
+#define   C_0286D0_POS_Z_FLOAT_ENA                                    0xFFFFFBFF
+#define   S_0286D0_POS_W_FLOAT_ENA(x)                                 (((x) & 0x1) << 11)
+#define   G_0286D0_POS_W_FLOAT_ENA(x)                                 (((x) >> 11) & 0x1)
+#define   C_0286D0_POS_W_FLOAT_ENA                                    0xFFFFF7FF
+#define   S_0286D0_FRONT_FACE_ENA(x)                                  (((x) & 0x1) << 12)
+#define   G_0286D0_FRONT_FACE_ENA(x)                                  (((x) >> 12) & 0x1)
+#define   C_0286D0_FRONT_FACE_ENA                                     0xFFFFEFFF
+#define   S_0286D0_ANCILLARY_ENA(x)                                   (((x) & 0x1) << 13)
+#define   G_0286D0_ANCILLARY_ENA(x)                                   (((x) >> 13) & 0x1)
+#define   C_0286D0_ANCILLARY_ENA                                      0xFFFFDFFF
+#define   S_0286D0_SAMPLE_COVERAGE_ENA(x)                             (((x) & 0x1) << 14)
+#define   G_0286D0_SAMPLE_COVERAGE_ENA(x)                             (((x) >> 14) & 0x1)
+#define   C_0286D0_SAMPLE_COVERAGE_ENA                                0xFFFFBFFF
+#define   S_0286D0_POS_FIXED_PT_ENA(x)                                (((x) & 0x1) << 15)
+#define   G_0286D0_POS_FIXED_PT_ENA(x)                                (((x) >> 15) & 0x1)
+#define   C_0286D0_POS_FIXED_PT_ENA                                   0xFFFF7FFF
+#define R_0286D4_SPI_INTERP_CONTROL_0                                   0x0286D4
+#define   S_0286D4_FLAT_SHADE_ENA(x)                                  (((x) & 0x1) << 0)
+#define   G_0286D4_FLAT_SHADE_ENA(x)                                  (((x) >> 0) & 0x1)
+#define   C_0286D4_FLAT_SHADE_ENA                                     0xFFFFFFFE
+#define   S_0286D4_PNT_SPRITE_ENA(x)                                  (((x) & 0x1) << 1)
+#define   G_0286D4_PNT_SPRITE_ENA(x)                                  (((x) >> 1) & 0x1)
+#define   C_0286D4_PNT_SPRITE_ENA                                     0xFFFFFFFD
+#define   S_0286D4_PNT_SPRITE_OVRD_X(x)                               (((x) & 0x07) << 2)
+#define   G_0286D4_PNT_SPRITE_OVRD_X(x)                               (((x) >> 2) & 0x07)
+#define   C_0286D4_PNT_SPRITE_OVRD_X                                  0xFFFFFFE3
+#define     V_0286D4_SPI_PNT_SPRITE_SEL_0                           0x00
+#define     V_0286D4_SPI_PNT_SPRITE_SEL_1                           0x01
+#define     V_0286D4_SPI_PNT_SPRITE_SEL_S                           0x02
+#define     V_0286D4_SPI_PNT_SPRITE_SEL_T                           0x03
+#define     V_0286D4_SPI_PNT_SPRITE_SEL_NONE                        0x04
+#define   S_0286D4_PNT_SPRITE_OVRD_Y(x)                               (((x) & 0x07) << 5)
+#define   G_0286D4_PNT_SPRITE_OVRD_Y(x)                               (((x) >> 5) & 0x07)
+#define   C_0286D4_PNT_SPRITE_OVRD_Y                                  0xFFFFFF1F
+#define     V_0286D4_SPI_PNT_SPRITE_SEL_0                           0x00
+#define     V_0286D4_SPI_PNT_SPRITE_SEL_1                           0x01
+#define     V_0286D4_SPI_PNT_SPRITE_SEL_S                           0x02
+#define     V_0286D4_SPI_PNT_SPRITE_SEL_T                           0x03
+#define     V_0286D4_SPI_PNT_SPRITE_SEL_NONE                        0x04
+#define   S_0286D4_PNT_SPRITE_OVRD_Z(x)                               (((x) & 0x07) << 8)
+#define   G_0286D4_PNT_SPRITE_OVRD_Z(x)                               (((x) >> 8) & 0x07)
+#define   C_0286D4_PNT_SPRITE_OVRD_Z                                  0xFFFFF8FF
+#define     V_0286D4_SPI_PNT_SPRITE_SEL_0                           0x00
+#define     V_0286D4_SPI_PNT_SPRITE_SEL_1                           0x01
+#define     V_0286D4_SPI_PNT_SPRITE_SEL_S                           0x02
+#define     V_0286D4_SPI_PNT_SPRITE_SEL_T                           0x03
+#define     V_0286D4_SPI_PNT_SPRITE_SEL_NONE                        0x04
+#define   S_0286D4_PNT_SPRITE_OVRD_W(x)                               (((x) & 0x07) << 11)
+#define   G_0286D4_PNT_SPRITE_OVRD_W(x)                               (((x) >> 11) & 0x07)
+#define   C_0286D4_PNT_SPRITE_OVRD_W                                  0xFFFFC7FF
+#define     V_0286D4_SPI_PNT_SPRITE_SEL_0                           0x00
+#define     V_0286D4_SPI_PNT_SPRITE_SEL_1                           0x01
+#define     V_0286D4_SPI_PNT_SPRITE_SEL_S                           0x02
+#define     V_0286D4_SPI_PNT_SPRITE_SEL_T                           0x03
+#define     V_0286D4_SPI_PNT_SPRITE_SEL_NONE                        0x04
+#define   S_0286D4_PNT_SPRITE_TOP_1(x)                                (((x) & 0x1) << 14)
+#define   G_0286D4_PNT_SPRITE_TOP_1(x)                                (((x) >> 14) & 0x1)
+#define   C_0286D4_PNT_SPRITE_TOP_1                                   0xFFFFBFFF
+#define R_0286D8_SPI_PS_IN_CONTROL                                      0x0286D8
+#define   S_0286D8_NUM_INTERP(x)                                      (((x) & 0x3F) << 0)
+#define   G_0286D8_NUM_INTERP(x)                                      (((x) >> 0) & 0x3F)
+#define   C_0286D8_NUM_INTERP                                         0xFFFFFFC0
+#define   S_0286D8_PARAM_GEN(x)                                       (((x) & 0x1) << 6)
+#define   G_0286D8_PARAM_GEN(x)                                       (((x) >> 6) & 0x1)
+#define   C_0286D8_PARAM_GEN                                          0xFFFFFFBF
+#define   S_0286D8_FOG_ADDR(x)                                        (((x) & 0x7F) << 7) /* not on CIK */
+#define   G_0286D8_FOG_ADDR(x)                                        (((x) >> 7) & 0x7F) /* not on CIK */
+#define   C_0286D8_FOG_ADDR                                           0xFFFFC07F /* not on CIK */
+#define   S_0286D8_BC_OPTIMIZE_DISABLE(x)                             (((x) & 0x1) << 14)
+#define   G_0286D8_BC_OPTIMIZE_DISABLE(x)                             (((x) >> 14) & 0x1)
+#define   C_0286D8_BC_OPTIMIZE_DISABLE                                0xFFFFBFFF
+#define   S_0286D8_PASS_FOG_THROUGH_PS(x)                             (((x) & 0x1) << 15) /* not on CIK */
+#define   G_0286D8_PASS_FOG_THROUGH_PS(x)                             (((x) >> 15) & 0x1) /* not on CIK */
+#define   C_0286D8_PASS_FOG_THROUGH_PS                                0xFFFF7FFF /* not on CIK */
+#define R_0286E0_SPI_BARYC_CNTL                                         0x0286E0
+#define   S_0286E0_PERSP_CENTER_CNTL(x)                               (((x) & 0x1) << 0)
+#define   G_0286E0_PERSP_CENTER_CNTL(x)                               (((x) >> 0) & 0x1)
+#define   C_0286E0_PERSP_CENTER_CNTL                                  0xFFFFFFFE
+#define   S_0286E0_PERSP_CENTROID_CNTL(x)                             (((x) & 0x1) << 4)
+#define   G_0286E0_PERSP_CENTROID_CNTL(x)                             (((x) >> 4) & 0x1)
+#define   C_0286E0_PERSP_CENTROID_CNTL                                0xFFFFFFEF
+#define   S_0286E0_LINEAR_CENTER_CNTL(x)                              (((x) & 0x1) << 8)
+#define   G_0286E0_LINEAR_CENTER_CNTL(x)                              (((x) >> 8) & 0x1)
+#define   C_0286E0_LINEAR_CENTER_CNTL                                 0xFFFFFEFF
+#define   S_0286E0_LINEAR_CENTROID_CNTL(x)                            (((x) & 0x1) << 12)
+#define   G_0286E0_LINEAR_CENTROID_CNTL(x)                            (((x) >> 12) & 0x1)
+#define   C_0286E0_LINEAR_CENTROID_CNTL                               0xFFFFEFFF
+#define   S_0286E0_POS_FLOAT_LOCATION(x)                              (((x) & 0x03) << 16)
+#define   G_0286E0_POS_FLOAT_LOCATION(x)                              (((x) >> 16) & 0x03)
+#define   C_0286E0_POS_FLOAT_LOCATION                                 0xFFFCFFFF
+#define     V_0286E0_X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT 0x00
+#define   S_0286E0_POS_FLOAT_ULC(x)                                   (((x) & 0x1) << 20)
+#define   G_0286E0_POS_FLOAT_ULC(x)                                   (((x) >> 20) & 0x1)
+#define   C_0286E0_POS_FLOAT_ULC                                      0xFFEFFFFF
+#define   S_0286E0_FRONT_FACE_ALL_BITS(x)                             (((x) & 0x1) << 24)
+#define   G_0286E0_FRONT_FACE_ALL_BITS(x)                             (((x) >> 24) & 0x1)
+#define   C_0286E0_FRONT_FACE_ALL_BITS                                0xFEFFFFFF
+#define R_0286E8_SPI_TMPRING_SIZE                                       0x0286E8
+#define   S_0286E8_WAVES(x)                                           (((x) & 0xFFF) << 0)
+#define   G_0286E8_WAVES(x)                                           (((x) >> 0) & 0xFFF)
+#define   C_0286E8_WAVES                                              0xFFFFF000
+#define   S_0286E8_WAVESIZE(x)                                        (((x) & 0x1FFF) << 12)
+#define   G_0286E8_WAVESIZE(x)                                        (((x) >> 12) & 0x1FFF)
+#define   C_0286E8_WAVESIZE                                           0xFE000FFF
+#define R_028704_SPI_WAVE_MGMT_1                                        0x028704 /* not on CIK */
+#define   S_028704_NUM_PS_WAVES(x)                                    (((x) & 0x3F) << 0)
+#define   G_028704_NUM_PS_WAVES(x)                                    (((x) >> 0) & 0x3F)
+#define   C_028704_NUM_PS_WAVES                                       0xFFFFFFC0
+#define   S_028704_NUM_VS_WAVES(x)                                    (((x) & 0x3F) << 6)
+#define   G_028704_NUM_VS_WAVES(x)                                    (((x) >> 6) & 0x3F)
+#define   C_028704_NUM_VS_WAVES                                       0xFFFFF03F
+#define   S_028704_NUM_GS_WAVES(x)                                    (((x) & 0x3F) << 12)
+#define   G_028704_NUM_GS_WAVES(x)                                    (((x) >> 12) & 0x3F)
+#define   C_028704_NUM_GS_WAVES                                       0xFFFC0FFF
+#define   S_028704_NUM_ES_WAVES(x)                                    (((x) & 0x3F) << 18)
+#define   G_028704_NUM_ES_WAVES(x)                                    (((x) >> 18) & 0x3F)
+#define   C_028704_NUM_ES_WAVES                                       0xFF03FFFF
+#define   S_028704_NUM_HS_WAVES(x)                                    (((x) & 0x3F) << 24)
+#define   G_028704_NUM_HS_WAVES(x)                                    (((x) >> 24) & 0x3F)
+#define   C_028704_NUM_HS_WAVES                                       0xC0FFFFFF
+#define R_028708_SPI_WAVE_MGMT_2                                        0x028708 /* not on CIK */
+#define   S_028708_NUM_LS_WAVES(x)                                    (((x) & 0x3F) << 0)
+#define   G_028708_NUM_LS_WAVES(x)                                    (((x) >> 0) & 0x3F)
+#define   C_028708_NUM_LS_WAVES                                       0xFFFFFFC0
+#define R_02870C_SPI_SHADER_POS_FORMAT                                  0x02870C
+#define   S_02870C_POS0_EXPORT_FORMAT(x)                              (((x) & 0x0F) << 0)
+#define   G_02870C_POS0_EXPORT_FORMAT(x)                              (((x) >> 0) & 0x0F)
+#define   C_02870C_POS0_EXPORT_FORMAT                                 0xFFFFFFF0
+#define     V_02870C_SPI_SHADER_NONE                                0x00
+#define     V_02870C_SPI_SHADER_1COMP                               0x01
+#define     V_02870C_SPI_SHADER_2COMP                               0x02
+#define     V_02870C_SPI_SHADER_4COMPRESS                           0x03
+#define     V_02870C_SPI_SHADER_4COMP                               0x04
+#define   S_02870C_POS1_EXPORT_FORMAT(x)                              (((x) & 0x0F) << 4)
+#define   G_02870C_POS1_EXPORT_FORMAT(x)                              (((x) >> 4) & 0x0F)
+#define   C_02870C_POS1_EXPORT_FORMAT                                 0xFFFFFF0F
+#define     V_02870C_SPI_SHADER_NONE                                0x00
+#define     V_02870C_SPI_SHADER_1COMP                               0x01
+#define     V_02870C_SPI_SHADER_2COMP                               0x02
+#define     V_02870C_SPI_SHADER_4COMPRESS                           0x03
+#define     V_02870C_SPI_SHADER_4COMP                               0x04
+#define   S_02870C_POS2_EXPORT_FORMAT(x)                              (((x) & 0x0F) << 8)
+#define   G_02870C_POS2_EXPORT_FORMAT(x)                              (((x) >> 8) & 0x0F)
+#define   C_02870C_POS2_EXPORT_FORMAT                                 0xFFFFF0FF
+#define     V_02870C_SPI_SHADER_NONE                                0x00
+#define     V_02870C_SPI_SHADER_1COMP                               0x01
+#define     V_02870C_SPI_SHADER_2COMP                               0x02
+#define     V_02870C_SPI_SHADER_4COMPRESS                           0x03
+#define     V_02870C_SPI_SHADER_4COMP                               0x04
+#define   S_02870C_POS3_EXPORT_FORMAT(x)                              (((x) & 0x0F) << 12)
+#define   G_02870C_POS3_EXPORT_FORMAT(x)                              (((x) >> 12) & 0x0F)
+#define   C_02870C_POS3_EXPORT_FORMAT                                 0xFFFF0FFF
+#define     V_02870C_SPI_SHADER_NONE                                0x00
+#define     V_02870C_SPI_SHADER_1COMP                               0x01
+#define     V_02870C_SPI_SHADER_2COMP                               0x02
+#define     V_02870C_SPI_SHADER_4COMPRESS                           0x03
+#define     V_02870C_SPI_SHADER_4COMP                               0x04
+#define R_028710_SPI_SHADER_Z_FORMAT                                    0x028710
+#define   S_028710_Z_EXPORT_FORMAT(x)                                 (((x) & 0x0F) << 0)
+#define   G_028710_Z_EXPORT_FORMAT(x)                                 (((x) >> 0) & 0x0F)
+#define   C_028710_Z_EXPORT_FORMAT                                    0xFFFFFFF0
+#define     V_028710_SPI_SHADER_ZERO                                0x00
+#define     V_028710_SPI_SHADER_32_R                                0x01
+#define     V_028710_SPI_SHADER_32_GR                               0x02
+#define     V_028710_SPI_SHADER_32_AR                               0x03
+#define     V_028710_SPI_SHADER_FP16_ABGR                           0x04
+#define     V_028710_SPI_SHADER_UNORM16_ABGR                        0x05
+#define     V_028710_SPI_SHADER_SNORM16_ABGR                        0x06
+#define     V_028710_SPI_SHADER_UINT16_ABGR                         0x07
+#define     V_028710_SPI_SHADER_SINT16_ABGR                         0x08
+#define     V_028710_SPI_SHADER_32_ABGR                             0x09
+#define R_028714_SPI_SHADER_COL_FORMAT                                  0x028714
+#define   S_028714_COL0_EXPORT_FORMAT(x)                              (((x) & 0x0F) << 0)
+#define   G_028714_COL0_EXPORT_FORMAT(x)                              (((x) >> 0) & 0x0F)
+#define   C_028714_COL0_EXPORT_FORMAT                                 0xFFFFFFF0
+#define     V_028714_SPI_SHADER_ZERO                                0x00
+#define     V_028714_SPI_SHADER_32_R                                0x01
+#define     V_028714_SPI_SHADER_32_GR                               0x02
+#define     V_028714_SPI_SHADER_32_AR                               0x03
+#define     V_028714_SPI_SHADER_FP16_ABGR                           0x04
+#define     V_028714_SPI_SHADER_UNORM16_ABGR                        0x05
+#define     V_028714_SPI_SHADER_SNORM16_ABGR                        0x06
+#define     V_028714_SPI_SHADER_UINT16_ABGR                         0x07
+#define     V_028714_SPI_SHADER_SINT16_ABGR                         0x08
+#define     V_028714_SPI_SHADER_32_ABGR                             0x09
+#define   S_028714_COL1_EXPORT_FORMAT(x)                              (((x) & 0x0F) << 4)
+#define   G_028714_COL1_EXPORT_FORMAT(x)                              (((x) >> 4) & 0x0F)
+#define   C_028714_COL1_EXPORT_FORMAT                                 0xFFFFFF0F
+#define     V_028714_SPI_SHADER_ZERO                                0x00
+#define     V_028714_SPI_SHADER_32_R                                0x01
+#define     V_028714_SPI_SHADER_32_GR                               0x02
+#define     V_028714_SPI_SHADER_32_AR                               0x03
+#define     V_028714_SPI_SHADER_FP16_ABGR                           0x04
+#define     V_028714_SPI_SHADER_UNORM16_ABGR                        0x05
+#define     V_028714_SPI_SHADER_SNORM16_ABGR                        0x06
+#define     V_028714_SPI_SHADER_UINT16_ABGR                         0x07
+#define     V_028714_SPI_SHADER_SINT16_ABGR                         0x08
+#define     V_028714_SPI_SHADER_32_ABGR                             0x09
+#define   S_028714_COL2_EXPORT_FORMAT(x)                              (((x) & 0x0F) << 8)
+#define   G_028714_COL2_EXPORT_FORMAT(x)                              (((x) >> 8) & 0x0F)
+#define   C_028714_COL2_EXPORT_FORMAT                                 0xFFFFF0FF
+#define     V_028714_SPI_SHADER_ZERO                                0x00
+#define     V_028714_SPI_SHADER_32_R                                0x01
+#define     V_028714_SPI_SHADER_32_GR                               0x02
+#define     V_028714_SPI_SHADER_32_AR                               0x03
+#define     V_028714_SPI_SHADER_FP16_ABGR                           0x04
+#define     V_028714_SPI_SHADER_UNORM16_ABGR                        0x05
+#define     V_028714_SPI_SHADER_SNORM16_ABGR                        0x06
+#define     V_028714_SPI_SHADER_UINT16_ABGR                         0x07
+#define     V_028714_SPI_SHADER_SINT16_ABGR                         0x08
+#define     V_028714_SPI_SHADER_32_ABGR                             0x09
+#define   S_028714_COL3_EXPORT_FORMAT(x)                              (((x) & 0x0F) << 12)
+#define   G_028714_COL3_EXPORT_FORMAT(x)                              (((x) >> 12) & 0x0F)
+#define   C_028714_COL3_EXPORT_FORMAT                                 0xFFFF0FFF
+#define     V_028714_SPI_SHADER_ZERO                                0x00
+#define     V_028714_SPI_SHADER_32_R                                0x01
+#define     V_028714_SPI_SHADER_32_GR                               0x02
+#define     V_028714_SPI_SHADER_32_AR                               0x03
+#define     V_028714_SPI_SHADER_FP16_ABGR                           0x04
+#define     V_028714_SPI_SHADER_UNORM16_ABGR                        0x05
+#define     V_028714_SPI_SHADER_SNORM16_ABGR                        0x06
+#define     V_028714_SPI_SHADER_UINT16_ABGR                         0x07
+#define     V_028714_SPI_SHADER_SINT16_ABGR                         0x08
+#define     V_028714_SPI_SHADER_32_ABGR                             0x09
+#define   S_028714_COL4_EXPORT_FORMAT(x)                              (((x) & 0x0F) << 16)
+#define   G_028714_COL4_EXPORT_FORMAT(x)                              (((x) >> 16) & 0x0F)
+#define   C_028714_COL4_EXPORT_FORMAT                                 0xFFF0FFFF
+#define     V_028714_SPI_SHADER_ZERO                                0x00
+#define     V_028714_SPI_SHADER_32_R                                0x01
+#define     V_028714_SPI_SHADER_32_GR                               0x02
+#define     V_028714_SPI_SHADER_32_AR                               0x03
+#define     V_028714_SPI_SHADER_FP16_ABGR                           0x04
+#define     V_028714_SPI_SHADER_UNORM16_ABGR                        0x05
+#define     V_028714_SPI_SHADER_SNORM16_ABGR                        0x06
+#define     V_028714_SPI_SHADER_UINT16_ABGR                         0x07
+#define     V_028714_SPI_SHADER_SINT16_ABGR                         0x08
+#define     V_028714_SPI_SHADER_32_ABGR                             0x09
+#define   S_028714_COL5_EXPORT_FORMAT(x)                              (((x) & 0x0F) << 20)
+#define   G_028714_COL5_EXPORT_FORMAT(x)                              (((x) >> 20) & 0x0F)
+#define   C_028714_COL5_EXPORT_FORMAT                                 0xFF0FFFFF
+#define     V_028714_SPI_SHADER_ZERO                                0x00
+#define     V_028714_SPI_SHADER_32_R                                0x01
+#define     V_028714_SPI_SHADER_32_GR                               0x02
+#define     V_028714_SPI_SHADER_32_AR                               0x03
+#define     V_028714_SPI_SHADER_FP16_ABGR                           0x04
+#define     V_028714_SPI_SHADER_UNORM16_ABGR                        0x05
+#define     V_028714_SPI_SHADER_SNORM16_ABGR                        0x06
+#define     V_028714_SPI_SHADER_UINT16_ABGR                         0x07
+#define     V_028714_SPI_SHADER_SINT16_ABGR                         0x08
+#define     V_028714_SPI_SHADER_32_ABGR                             0x09
+#define   S_028714_COL6_EXPORT_FORMAT(x)                              (((x) & 0x0F) << 24)
+#define   G_028714_COL6_EXPORT_FORMAT(x)                              (((x) >> 24) & 0x0F)
+#define   C_028714_COL6_EXPORT_FORMAT                                 0xF0FFFFFF
+#define     V_028714_SPI_SHADER_ZERO                                0x00
+#define     V_028714_SPI_SHADER_32_R                                0x01
+#define     V_028714_SPI_SHADER_32_GR                               0x02
+#define     V_028714_SPI_SHADER_32_AR                               0x03
+#define     V_028714_SPI_SHADER_FP16_ABGR                           0x04
+#define     V_028714_SPI_SHADER_UNORM16_ABGR                        0x05
+#define     V_028714_SPI_SHADER_SNORM16_ABGR                        0x06
+#define     V_028714_SPI_SHADER_UINT16_ABGR                         0x07
+#define     V_028714_SPI_SHADER_SINT16_ABGR                         0x08
+#define     V_028714_SPI_SHADER_32_ABGR                             0x09
+#define   S_028714_COL7_EXPORT_FORMAT(x)                              (((x) & 0x0F) << 28)
+#define   G_028714_COL7_EXPORT_FORMAT(x)                              (((x) >> 28) & 0x0F)
+#define   C_028714_COL7_EXPORT_FORMAT                                 0x0FFFFFFF
+#define     V_028714_SPI_SHADER_ZERO                                0x00
+#define     V_028714_SPI_SHADER_32_R                                0x01
+#define     V_028714_SPI_SHADER_32_GR                               0x02
+#define     V_028714_SPI_SHADER_32_AR                               0x03
+#define     V_028714_SPI_SHADER_FP16_ABGR                           0x04
+#define     V_028714_SPI_SHADER_UNORM16_ABGR                        0x05
+#define     V_028714_SPI_SHADER_SNORM16_ABGR                        0x06
+#define     V_028714_SPI_SHADER_UINT16_ABGR                         0x07
+#define     V_028714_SPI_SHADER_SINT16_ABGR                         0x08
+#define     V_028714_SPI_SHADER_32_ABGR                             0x09
+#define R_028780_CB_BLEND0_CONTROL                                      0x028780
+#define   S_028780_COLOR_SRCBLEND(x)                                  (((x) & 0x1F) << 0)
+#define   G_028780_COLOR_SRCBLEND(x)                                  (((x) >> 0) & 0x1F)
+#define   C_028780_COLOR_SRCBLEND                                     0xFFFFFFE0
+#define     V_028780_BLEND_ZERO                                     0x00
+#define     V_028780_BLEND_ONE                                      0x01
+#define     V_028780_BLEND_SRC_COLOR                                0x02
+#define     V_028780_BLEND_ONE_MINUS_SRC_COLOR                      0x03
+#define     V_028780_BLEND_SRC_ALPHA                                0x04
+#define     V_028780_BLEND_ONE_MINUS_SRC_ALPHA                      0x05
+#define     V_028780_BLEND_DST_ALPHA                                0x06
+#define     V_028780_BLEND_ONE_MINUS_DST_ALPHA                      0x07
+#define     V_028780_BLEND_DST_COLOR                                0x08
+#define     V_028780_BLEND_ONE_MINUS_DST_COLOR                      0x09
+#define     V_028780_BLEND_SRC_ALPHA_SATURATE                       0x0A
+#define     V_028780_BLEND_CONSTANT_COLOR                           0x0D
+#define     V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR                 0x0E
+#define     V_028780_BLEND_SRC1_COLOR                               0x0F
+#define     V_028780_BLEND_INV_SRC1_COLOR                           0x10
+#define     V_028780_BLEND_SRC1_ALPHA                               0x11
+#define     V_028780_BLEND_INV_SRC1_ALPHA                           0x12
+#define     V_028780_BLEND_CONSTANT_ALPHA                           0x13
+#define     V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA                 0x14
+#define   S_028780_COLOR_COMB_FCN(x)                                  (((x) & 0x07) << 5)
+#define   G_028780_COLOR_COMB_FCN(x)                                  (((x) >> 5) & 0x07)
+#define   C_028780_COLOR_COMB_FCN                                     0xFFFFFF1F
+#define     V_028780_COMB_DST_PLUS_SRC                              0x00
+#define     V_028780_COMB_SRC_MINUS_DST                             0x01
+#define     V_028780_COMB_MIN_DST_SRC                               0x02
+#define     V_028780_COMB_MAX_DST_SRC                               0x03
+#define     V_028780_COMB_DST_MINUS_SRC                             0x04
+#define   S_028780_COLOR_DESTBLEND(x)                                 (((x) & 0x1F) << 8)
+#define   G_028780_COLOR_DESTBLEND(x)                                 (((x) >> 8) & 0x1F)
+#define   C_028780_COLOR_DESTBLEND                                    0xFFFFE0FF
+#define     V_028780_BLEND_ZERO                                     0x00
+#define     V_028780_BLEND_ONE                                      0x01
+#define     V_028780_BLEND_SRC_COLOR                                0x02
+#define     V_028780_BLEND_ONE_MINUS_SRC_COLOR                      0x03
+#define     V_028780_BLEND_SRC_ALPHA                                0x04
+#define     V_028780_BLEND_ONE_MINUS_SRC_ALPHA                      0x05
+#define     V_028780_BLEND_DST_ALPHA                                0x06
+#define     V_028780_BLEND_ONE_MINUS_DST_ALPHA                      0x07
+#define     V_028780_BLEND_DST_COLOR                                0x08
+#define     V_028780_BLEND_ONE_MINUS_DST_COLOR                      0x09
+#define     V_028780_BLEND_SRC_ALPHA_SATURATE                       0x0A
+#define     V_028780_BLEND_CONSTANT_COLOR                           0x0D
+#define     V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR                 0x0E
+#define     V_028780_BLEND_SRC1_COLOR                               0x0F
+#define     V_028780_BLEND_INV_SRC1_COLOR                           0x10
+#define     V_028780_BLEND_SRC1_ALPHA                               0x11
+#define     V_028780_BLEND_INV_SRC1_ALPHA                           0x12
+#define     V_028780_BLEND_CONSTANT_ALPHA                           0x13
+#define     V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA                 0x14
+#define   S_028780_ALPHA_SRCBLEND(x)                                  (((x) & 0x1F) << 16)
+#define   G_028780_ALPHA_SRCBLEND(x)                                  (((x) >> 16) & 0x1F)
+#define   C_028780_ALPHA_SRCBLEND                                     0xFFE0FFFF
+#define     V_028780_BLEND_ZERO                                     0x00
+#define     V_028780_BLEND_ONE                                      0x01
+#define     V_028780_BLEND_SRC_COLOR                                0x02
+#define     V_028780_BLEND_ONE_MINUS_SRC_COLOR                      0x03
+#define     V_028780_BLEND_SRC_ALPHA                                0x04
+#define     V_028780_BLEND_ONE_MINUS_SRC_ALPHA                      0x05
+#define     V_028780_BLEND_DST_ALPHA                                0x06
+#define     V_028780_BLEND_ONE_MINUS_DST_ALPHA                      0x07
+#define     V_028780_BLEND_DST_COLOR                                0x08
+#define     V_028780_BLEND_ONE_MINUS_DST_COLOR                      0x09
+#define     V_028780_BLEND_SRC_ALPHA_SATURATE                       0x0A
+#define     V_028780_BLEND_CONSTANT_COLOR                           0x0D
+#define     V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR                 0x0E
+#define     V_028780_BLEND_SRC1_COLOR                               0x0F
+#define     V_028780_BLEND_INV_SRC1_COLOR                           0x10
+#define     V_028780_BLEND_SRC1_ALPHA                               0x11
+#define     V_028780_BLEND_INV_SRC1_ALPHA                           0x12
+#define     V_028780_BLEND_CONSTANT_ALPHA                           0x13
+#define     V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA                 0x14
+#define   S_028780_ALPHA_COMB_FCN(x)                                  (((x) & 0x07) << 21)
+#define   G_028780_ALPHA_COMB_FCN(x)                                  (((x) >> 21) & 0x07)
+#define   C_028780_ALPHA_COMB_FCN                                     0xFF1FFFFF
+#define     V_028780_COMB_DST_PLUS_SRC                              0x00
+#define     V_028780_COMB_SRC_MINUS_DST                             0x01
+#define     V_028780_COMB_MIN_DST_SRC                               0x02
+#define     V_028780_COMB_MAX_DST_SRC                               0x03
+#define     V_028780_COMB_DST_MINUS_SRC                             0x04
+#define   S_028780_ALPHA_DESTBLEND(x)                                 (((x) & 0x1F) << 24)
+#define   G_028780_ALPHA_DESTBLEND(x)                                 (((x) >> 24) & 0x1F)
+#define   C_028780_ALPHA_DESTBLEND                                    0xE0FFFFFF
+#define     V_028780_BLEND_ZERO                                     0x00
+#define     V_028780_BLEND_ONE                                      0x01
+#define     V_028780_BLEND_SRC_COLOR                                0x02
+#define     V_028780_BLEND_ONE_MINUS_SRC_COLOR                      0x03
+#define     V_028780_BLEND_SRC_ALPHA                                0x04
+#define     V_028780_BLEND_ONE_MINUS_SRC_ALPHA                      0x05
+#define     V_028780_BLEND_DST_ALPHA                                0x06
+#define     V_028780_BLEND_ONE_MINUS_DST_ALPHA                      0x07
+#define     V_028780_BLEND_DST_COLOR                                0x08
+#define     V_028780_BLEND_ONE_MINUS_DST_COLOR                      0x09
+#define     V_028780_BLEND_SRC_ALPHA_SATURATE                       0x0A
+#define     V_028780_BLEND_CONSTANT_COLOR                           0x0D
+#define     V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR                 0x0E
+#define     V_028780_BLEND_SRC1_COLOR                               0x0F
+#define     V_028780_BLEND_INV_SRC1_COLOR                           0x10
+#define     V_028780_BLEND_SRC1_ALPHA                               0x11
+#define     V_028780_BLEND_INV_SRC1_ALPHA                           0x12
+#define     V_028780_BLEND_CONSTANT_ALPHA                           0x13
+#define     V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA                 0x14
+#define   S_028780_SEPARATE_ALPHA_BLEND(x)                            (((x) & 0x1) << 29)
+#define   G_028780_SEPARATE_ALPHA_BLEND(x)                            (((x) >> 29) & 0x1)
+#define   C_028780_SEPARATE_ALPHA_BLEND                               0xDFFFFFFF
+#define   S_028780_ENABLE(x)                                          (((x) & 0x1) << 30)
+#define   G_028780_ENABLE(x)                                          (((x) >> 30) & 0x1)
+#define   C_028780_ENABLE                                             0xBFFFFFFF
+#define   S_028780_DISABLE_ROP3(x)                                    (((x) & 0x1) << 31)
+#define   G_028780_DISABLE_ROP3(x)                                    (((x) >> 31) & 0x1)
+#define   C_028780_DISABLE_ROP3                                       0x7FFFFFFF
+#define R_028784_CB_BLEND1_CONTROL                                      0x028784
+#define R_028788_CB_BLEND2_CONTROL                                      0x028788
+#define R_02878C_CB_BLEND3_CONTROL                                      0x02878C
+#define R_028790_CB_BLEND4_CONTROL                                      0x028790
+#define R_028794_CB_BLEND5_CONTROL                                      0x028794
+#define R_028798_CB_BLEND6_CONTROL                                      0x028798
+#define R_02879C_CB_BLEND7_CONTROL                                      0x02879C
+#define R_0287D4_PA_CL_POINT_X_RAD                                      0x0287D4
+#define R_0287D8_PA_CL_POINT_Y_RAD                                      0x0287D8
+#define R_0287DC_PA_CL_POINT_SIZE                                       0x0287DC
+#define R_0287E0_PA_CL_POINT_CULL_RAD                                   0x0287E0
+#define R_0287E4_VGT_DMA_BASE_HI                                        0x0287E4
+#define   S_0287E4_BASE_ADDR(x)                                       (((x) & 0xFF) << 0)
+#define   G_0287E4_BASE_ADDR(x)                                       (((x) >> 0) & 0xFF)
+#define   C_0287E4_BASE_ADDR                                          0xFFFFFF00
+#define R_0287E8_VGT_DMA_BASE                                           0x0287E8
+#define R_0287F0_VGT_DRAW_INITIATOR                                     0x0287F0
+#define   S_0287F0_SOURCE_SELECT(x)                                   (((x) & 0x03) << 0)
+#define   G_0287F0_SOURCE_SELECT(x)                                   (((x) >> 0) & 0x03)
+#define   C_0287F0_SOURCE_SELECT                                      0xFFFFFFFC
+#define     V_0287F0_DI_SRC_SEL_DMA                                 0x00
+#define     V_0287F0_DI_SRC_SEL_IMMEDIATE                           0x01 /* not on CIK */
+#define     V_0287F0_DI_SRC_SEL_AUTO_INDEX                          0x02
+#define     V_0287F0_DI_SRC_SEL_RESERVED                            0x03
+#define   S_0287F0_MAJOR_MODE(x)                                      (((x) & 0x03) << 2)
+#define   G_0287F0_MAJOR_MODE(x)                                      (((x) >> 2) & 0x03)
+#define   C_0287F0_MAJOR_MODE                                         0xFFFFFFF3
+#define     V_0287F0_DI_MAJOR_MODE_0                                0x00
+#define     V_0287F0_DI_MAJOR_MODE_1                                0x01
+#define   S_0287F0_NOT_EOP(x)                                         (((x) & 0x1) << 5)
+#define   G_0287F0_NOT_EOP(x)                                         (((x) >> 5) & 0x1)
+#define   C_0287F0_NOT_EOP                                            0xFFFFFFDF
+#define   S_0287F0_USE_OPAQUE(x)                                      (((x) & 0x1) << 6)
+#define   G_0287F0_USE_OPAQUE(x)                                      (((x) >> 6) & 0x1)
+#define   C_0287F0_USE_OPAQUE                                         0xFFFFFFBF
+#define R_0287F4_VGT_IMMED_DATA                                         0x0287F4 /* not on CIK */
+#define R_028800_DB_DEPTH_CONTROL                                       0x028800
+#define   S_028800_STENCIL_ENABLE(x)                                  (((x) & 0x1) << 0)
+#define   G_028800_STENCIL_ENABLE(x)                                  (((x) >> 0) & 0x1)
+#define   C_028800_STENCIL_ENABLE                                     0xFFFFFFFE
+#define   S_028800_Z_ENABLE(x)                                        (((x) & 0x1) << 1)
+#define   G_028800_Z_ENABLE(x)                                        (((x) >> 1) & 0x1)
+#define   C_028800_Z_ENABLE                                           0xFFFFFFFD
+#define   S_028800_Z_WRITE_ENABLE(x)                                  (((x) & 0x1) << 2)
+#define   G_028800_Z_WRITE_ENABLE(x)                                  (((x) >> 2) & 0x1)
+#define   C_028800_Z_WRITE_ENABLE                                     0xFFFFFFFB
+#define   S_028800_DEPTH_BOUNDS_ENABLE(x)                             (((x) & 0x1) << 3)
+#define   G_028800_DEPTH_BOUNDS_ENABLE(x)                             (((x) >> 3) & 0x1)
+#define   C_028800_DEPTH_BOUNDS_ENABLE                                0xFFFFFFF7
+#define   S_028800_ZFUNC(x)                                           (((x) & 0x07) << 4)
+#define   G_028800_ZFUNC(x)                                           (((x) >> 4) & 0x07)
+#define   C_028800_ZFUNC                                              0xFFFFFF8F
+#define     V_028800_FRAG_NEVER                                     0x00
+#define     V_028800_FRAG_LESS                                      0x01
+#define     V_028800_FRAG_EQUAL                                     0x02
+#define     V_028800_FRAG_LEQUAL                                    0x03
+#define     V_028800_FRAG_GREATER                                   0x04
+#define     V_028800_FRAG_NOTEQUAL                                  0x05
+#define     V_028800_FRAG_GEQUAL                                    0x06
+#define     V_028800_FRAG_ALWAYS                                    0x07
+#define   S_028800_BACKFACE_ENABLE(x)                                 (((x) & 0x1) << 7)
+#define   G_028800_BACKFACE_ENABLE(x)                                 (((x) >> 7) & 0x1)
+#define   C_028800_BACKFACE_ENABLE                                    0xFFFFFF7F
+#define   S_028800_STENCILFUNC(x)                                     (((x) & 0x07) << 8)
+#define   G_028800_STENCILFUNC(x)                                     (((x) >> 8) & 0x07)
+#define   C_028800_STENCILFUNC                                        0xFFFFF8FF
+#define     V_028800_REF_NEVER                                      0x00
+#define     V_028800_REF_LESS                                       0x01
+#define     V_028800_REF_EQUAL                                      0x02
+#define     V_028800_REF_LEQUAL                                     0x03
+#define     V_028800_REF_GREATER                                    0x04
+#define     V_028800_REF_NOTEQUAL                                   0x05
+#define     V_028800_REF_GEQUAL                                     0x06
+#define     V_028800_REF_ALWAYS                                     0x07
+#define   S_028800_STENCILFUNC_BF(x)                                  (((x) & 0x07) << 20)
+#define   G_028800_STENCILFUNC_BF(x)                                  (((x) >> 20) & 0x07)
+#define   C_028800_STENCILFUNC_BF                                     0xFF8FFFFF
+#define     V_028800_REF_NEVER                                      0x00
+#define     V_028800_REF_LESS                                       0x01
+#define     V_028800_REF_EQUAL                                      0x02
+#define     V_028800_REF_LEQUAL                                     0x03
+#define     V_028800_REF_GREATER                                    0x04
+#define     V_028800_REF_NOTEQUAL                                   0x05
+#define     V_028800_REF_GEQUAL                                     0x06
+#define     V_028800_REF_ALWAYS                                     0x07
+#define   S_028800_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL(x)               (((x) & 0x1) << 30)
+#define   G_028800_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL(x)               (((x) >> 30) & 0x1)
+#define   C_028800_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL                  0xBFFFFFFF
+#define   S_028800_DISABLE_COLOR_WRITES_ON_DEPTH_PASS(x)              (((x) & 0x1) << 31)
+#define   G_028800_DISABLE_COLOR_WRITES_ON_DEPTH_PASS(x)              (((x) >> 31) & 0x1)
+#define   C_028800_DISABLE_COLOR_WRITES_ON_DEPTH_PASS                 0x7FFFFFFF
+#define R_028804_DB_EQAA                                                0x028804
+#define R_028808_CB_COLOR_CONTROL                                       0x028808
+#define   S_028808_DEGAMMA_ENABLE(x)                                  (((x) & 0x1) << 3)
+#define   G_028808_DEGAMMA_ENABLE(x)                                  (((x) >> 3) & 0x1)
+#define   C_028808_DEGAMMA_ENABLE                                     0xFFFFFFF7
+#define   S_028808_MODE(x)                                            (((x) & 0x07) << 4)
+#define   G_028808_MODE(x)                                            (((x) >> 4) & 0x07)
+#define   C_028808_MODE                                               0xFFFFFF8F
+#define     V_028808_CB_DISABLE                                     0x00
+#define     V_028808_CB_NORMAL                                      0x01
+#define     V_028808_CB_ELIMINATE_FAST_CLEAR                        0x02
+#define     V_028808_CB_RESOLVE                                     0x03
+#define     V_028808_CB_FMASK_DECOMPRESS                            0x05
+#define   S_028808_ROP3(x)                                            (((x) & 0xFF) << 16)
+#define   G_028808_ROP3(x)                                            (((x) >> 16) & 0xFF)
+#define   C_028808_ROP3                                               0xFF00FFFF
+#define     V_028808_X_0X00                                         0x00
+#define     V_028808_X_0X05                                         0x05
+#define     V_028808_X_0X0A                                         0x0A
+#define     V_028808_X_0X0F                                         0x0F
+#define     V_028808_X_0X11                                         0x11
+#define     V_028808_X_0X22                                         0x22
+#define     V_028808_X_0X33                                         0x33
+#define     V_028808_X_0X44                                         0x44
+#define     V_028808_X_0X50                                         0x50
+#define     V_028808_X_0X55                                         0x55
+#define     V_028808_X_0X5A                                         0x5A
+#define     V_028808_X_0X5F                                         0x5F
+#define     V_028808_X_0X66                                         0x66
+#define     V_028808_X_0X77                                         0x77
+#define     V_028808_X_0X88                                         0x88
+#define     V_028808_X_0X99                                         0x99
+#define     V_028808_X_0XA0                                         0xA0
+#define     V_028808_X_0XA5                                         0xA5
+#define     V_028808_X_0XAA                                         0xAA
+#define     V_028808_X_0XAF                                         0xAF
+#define     V_028808_X_0XBB                                         0xBB
+#define     V_028808_X_0XCC                                         0xCC
+#define     V_028808_X_0XDD                                         0xDD
+#define     V_028808_X_0XEE                                         0xEE
+#define     V_028808_X_0XF0                                         0xF0
+#define     V_028808_X_0XF5                                         0xF5
+#define     V_028808_X_0XFA                                         0xFA
+#define     V_028808_X_0XFF                                         0xFF
+#define R_02880C_DB_SHADER_CONTROL                                      0x02880C
+#define   S_02880C_Z_EXPORT_ENABLE(x)                                 (((x) & 0x1) << 0)
+#define   G_02880C_Z_EXPORT_ENABLE(x)                                 (((x) >> 0) & 0x1)
+#define   C_02880C_Z_EXPORT_ENABLE                                    0xFFFFFFFE
+#define   S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(x)                  (((x) & 0x1) << 1)
+#define   G_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(x)                  (((x) >> 1) & 0x1)
+#define   C_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE                     0xFFFFFFFD
+#define   S_02880C_STENCIL_OP_VAL_EXPORT_ENABLE(x)                    (((x) & 0x1) << 2)
+#define   G_02880C_STENCIL_OP_VAL_EXPORT_ENABLE(x)                    (((x) >> 2) & 0x1)
+#define   C_02880C_STENCIL_OP_VAL_EXPORT_ENABLE                       0xFFFFFFFB
+#define   S_02880C_Z_ORDER(x)                                         (((x) & 0x03) << 4)
+#define   G_02880C_Z_ORDER(x)                                         (((x) >> 4) & 0x03)
+#define   C_02880C_Z_ORDER                                            0xFFFFFFCF
+#define     V_02880C_LATE_Z                                         0x00
+#define     V_02880C_EARLY_Z_THEN_LATE_Z                            0x01
+#define     V_02880C_RE_Z                                           0x02
+#define     V_02880C_EARLY_Z_THEN_RE_Z                              0x03
+#define   S_02880C_KILL_ENABLE(x)                                     (((x) & 0x1) << 6)
+#define   G_02880C_KILL_ENABLE(x)                                     (((x) >> 6) & 0x1)
+#define   C_02880C_KILL_ENABLE                                        0xFFFFFFBF
+#define   S_02880C_COVERAGE_TO_MASK_ENABLE(x)                         (((x) & 0x1) << 7)
+#define   G_02880C_COVERAGE_TO_MASK_ENABLE(x)                         (((x) >> 7) & 0x1)
+#define   C_02880C_COVERAGE_TO_MASK_ENABLE                            0xFFFFFF7F
+#define   S_02880C_MASK_EXPORT_ENABLE(x)                              (((x) & 0x1) << 8)
+#define   G_02880C_MASK_EXPORT_ENABLE(x)                              (((x) >> 8) & 0x1)
+#define   C_02880C_MASK_EXPORT_ENABLE                                 0xFFFFFEFF
+#define   S_02880C_EXEC_ON_HIER_FAIL(x)                               (((x) & 0x1) << 9)
+#define   G_02880C_EXEC_ON_HIER_FAIL(x)                               (((x) >> 9) & 0x1)
+#define   C_02880C_EXEC_ON_HIER_FAIL                                  0xFFFFFDFF
+#define   S_02880C_EXEC_ON_NOOP(x)                                    (((x) & 0x1) << 10)
+#define   G_02880C_EXEC_ON_NOOP(x)                                    (((x) >> 10) & 0x1)
+#define   C_02880C_EXEC_ON_NOOP                                       0xFFFFFBFF
+#define   S_02880C_ALPHA_TO_MASK_DISABLE(x)                           (((x) & 0x1) << 11)
+#define   G_02880C_ALPHA_TO_MASK_DISABLE(x)                           (((x) >> 11) & 0x1)
+#define   C_02880C_ALPHA_TO_MASK_DISABLE                              0xFFFFF7FF
+#define   S_02880C_DEPTH_BEFORE_SHADER(x)                             (((x) & 0x1) << 12)
+#define   G_02880C_DEPTH_BEFORE_SHADER(x)                             (((x) >> 12) & 0x1)
+#define   C_02880C_DEPTH_BEFORE_SHADER                                0xFFFFEFFF
+/* CIK */
+#define   S_02880C_CONSERVATIVE_Z_EXPORT(x)                           (((x) & 0x03) << 13)
+#define   G_02880C_CONSERVATIVE_Z_EXPORT(x)                           (((x) >> 13) & 0x03)
+#define   C_02880C_CONSERVATIVE_Z_EXPORT                              0xFFFF9FFF
+/*     */
+#define R_028810_PA_CL_CLIP_CNTL                                        0x028810
+#define   S_028810_UCP_ENA_0(x)                                       (((x) & 0x1) << 0)
+#define   G_028810_UCP_ENA_0(x)                                       (((x) >> 0) & 0x1)
+#define   C_028810_UCP_ENA_0                                          0xFFFFFFFE
+#define   S_028810_UCP_ENA_1(x)                                       (((x) & 0x1) << 1)
+#define   G_028810_UCP_ENA_1(x)                                       (((x) >> 1) & 0x1)
+#define   C_028810_UCP_ENA_1                                          0xFFFFFFFD
+#define   S_028810_UCP_ENA_2(x)                                       (((x) & 0x1) << 2)
+#define   G_028810_UCP_ENA_2(x)                                       (((x) >> 2) & 0x1)
+#define   C_028810_UCP_ENA_2                                          0xFFFFFFFB
+#define   S_028810_UCP_ENA_3(x)                                       (((x) & 0x1) << 3)
+#define   G_028810_UCP_ENA_3(x)                                       (((x) >> 3) & 0x1)
+#define   C_028810_UCP_ENA_3                                          0xFFFFFFF7
+#define   S_028810_UCP_ENA_4(x)                                       (((x) & 0x1) << 4)
+#define   G_028810_UCP_ENA_4(x)                                       (((x) >> 4) & 0x1)
+#define   C_028810_UCP_ENA_4                                          0xFFFFFFEF
+#define   S_028810_UCP_ENA_5(x)                                       (((x) & 0x1) << 5)
+#define   G_028810_UCP_ENA_5(x)                                       (((x) >> 5) & 0x1)
+#define   C_028810_UCP_ENA_5                                          0xFFFFFFDF
+#define   S_028810_PS_UCP_Y_SCALE_NEG(x)                              (((x) & 0x1) << 13)
+#define   G_028810_PS_UCP_Y_SCALE_NEG(x)                              (((x) >> 13) & 0x1)
+#define   C_028810_PS_UCP_Y_SCALE_NEG                                 0xFFFFDFFF
+#define   S_028810_PS_UCP_MODE(x)                                     (((x) & 0x03) << 14)
+#define   G_028810_PS_UCP_MODE(x)                                     (((x) >> 14) & 0x03)
+#define   C_028810_PS_UCP_MODE                                        0xFFFF3FFF
+#define   S_028810_CLIP_DISABLE(x)                                    (((x) & 0x1) << 16)
+#define   G_028810_CLIP_DISABLE(x)                                    (((x) >> 16) & 0x1)
+#define   C_028810_CLIP_DISABLE                                       0xFFFEFFFF
+#define   S_028810_UCP_CULL_ONLY_ENA(x)                               (((x) & 0x1) << 17)
+#define   G_028810_UCP_CULL_ONLY_ENA(x)                               (((x) >> 17) & 0x1)
+#define   C_028810_UCP_CULL_ONLY_ENA                                  0xFFFDFFFF
+#define   S_028810_BOUNDARY_EDGE_FLAG_ENA(x)                          (((x) & 0x1) << 18)
+#define   G_028810_BOUNDARY_EDGE_FLAG_ENA(x)                          (((x) >> 18) & 0x1)
+#define   C_028810_BOUNDARY_EDGE_FLAG_ENA                             0xFFFBFFFF
+#define   S_028810_DX_CLIP_SPACE_DEF(x)                               (((x) & 0x1) << 19)
+#define   G_028810_DX_CLIP_SPACE_DEF(x)                               (((x) >> 19) & 0x1)
+#define   C_028810_DX_CLIP_SPACE_DEF                                  0xFFF7FFFF
+#define   S_028810_DIS_CLIP_ERR_DETECT(x)                             (((x) & 0x1) << 20)
+#define   G_028810_DIS_CLIP_ERR_DETECT(x)                             (((x) >> 20) & 0x1)
+#define   C_028810_DIS_CLIP_ERR_DETECT                                0xFFEFFFFF
+#define   S_028810_VTX_KILL_OR(x)                                     (((x) & 0x1) << 21)
+#define   G_028810_VTX_KILL_OR(x)                                     (((x) >> 21) & 0x1)
+#define   C_028810_VTX_KILL_OR                                        0xFFDFFFFF
+#define   S_028810_DX_RASTERIZATION_KILL(x)                           (((x) & 0x1) << 22)
+#define   G_028810_DX_RASTERIZATION_KILL(x)                           (((x) >> 22) & 0x1)
+#define   C_028810_DX_RASTERIZATION_KILL                              0xFFBFFFFF
+#define   S_028810_DX_LINEAR_ATTR_CLIP_ENA(x)                         (((x) & 0x1) << 24)
+#define   G_028810_DX_LINEAR_ATTR_CLIP_ENA(x)                         (((x) >> 24) & 0x1)
+#define   C_028810_DX_LINEAR_ATTR_CLIP_ENA                            0xFEFFFFFF
+#define   S_028810_VTE_VPORT_PROVOKE_DISABLE(x)                       (((x) & 0x1) << 25)
+#define   G_028810_VTE_VPORT_PROVOKE_DISABLE(x)                       (((x) >> 25) & 0x1)
+#define   C_028810_VTE_VPORT_PROVOKE_DISABLE                          0xFDFFFFFF
+#define   S_028810_ZCLIP_NEAR_DISABLE(x)                              (((x) & 0x1) << 26)
+#define   G_028810_ZCLIP_NEAR_DISABLE(x)                              (((x) >> 26) & 0x1)
+#define   C_028810_ZCLIP_NEAR_DISABLE                                 0xFBFFFFFF
+#define   S_028810_ZCLIP_FAR_DISABLE(x)                               (((x) & 0x1) << 27)
+#define   G_028810_ZCLIP_FAR_DISABLE(x)                               (((x) >> 27) & 0x1)
+#define   C_028810_ZCLIP_FAR_DISABLE                                  0xF7FFFFFF
+#define R_028814_PA_SU_SC_MODE_CNTL                                     0x028814
+#define   S_028814_CULL_FRONT(x)                                      (((x) & 0x1) << 0)
+#define   G_028814_CULL_FRONT(x)                                      (((x) >> 0) & 0x1)
+#define   C_028814_CULL_FRONT                                         0xFFFFFFFE
+#define   S_028814_CULL_BACK(x)                                       (((x) & 0x1) << 1)
+#define   G_028814_CULL_BACK(x)                                       (((x) >> 1) & 0x1)
+#define   C_028814_CULL_BACK                                          0xFFFFFFFD
+#define   S_028814_FACE(x)                                            (((x) & 0x1) << 2)
+#define   G_028814_FACE(x)                                            (((x) >> 2) & 0x1)
+#define   C_028814_FACE                                               0xFFFFFFFB
+#define   S_028814_POLY_MODE(x)                                       (((x) & 0x03) << 3)
+#define   G_028814_POLY_MODE(x)                                       (((x) >> 3) & 0x03)
+#define   C_028814_POLY_MODE                                          0xFFFFFFE7
+#define     V_028814_X_DISABLE_POLY_MODE                            0x00
+#define     V_028814_X_DUAL_MODE                                    0x01
+#define   S_028814_POLYMODE_FRONT_PTYPE(x)                            (((x) & 0x07) << 5)
+#define   G_028814_POLYMODE_FRONT_PTYPE(x)                            (((x) >> 5) & 0x07)
+#define   C_028814_POLYMODE_FRONT_PTYPE                               0xFFFFFF1F
+#define     V_028814_X_DRAW_POINTS                                  0x00
+#define     V_028814_X_DRAW_LINES                                   0x01
+#define     V_028814_X_DRAW_TRIANGLES                               0x02
+#define   S_028814_POLYMODE_BACK_PTYPE(x)                             (((x) & 0x07) << 8)
+#define   G_028814_POLYMODE_BACK_PTYPE(x)                             (((x) >> 8) & 0x07)
+#define   C_028814_POLYMODE_BACK_PTYPE                                0xFFFFF8FF
+#define     V_028814_X_DRAW_POINTS                                  0x00
+#define     V_028814_X_DRAW_LINES                                   0x01
+#define     V_028814_X_DRAW_TRIANGLES                               0x02
+#define   S_028814_POLY_OFFSET_FRONT_ENABLE(x)                        (((x) & 0x1) << 11)
+#define   G_028814_POLY_OFFSET_FRONT_ENABLE(x)                        (((x) >> 11) & 0x1)
+#define   C_028814_POLY_OFFSET_FRONT_ENABLE                           0xFFFFF7FF
+#define   S_028814_POLY_OFFSET_BACK_ENABLE(x)                         (((x) & 0x1) << 12)
+#define   G_028814_POLY_OFFSET_BACK_ENABLE(x)                         (((x) >> 12) & 0x1)
+#define   C_028814_POLY_OFFSET_BACK_ENABLE                            0xFFFFEFFF
+#define   S_028814_POLY_OFFSET_PARA_ENABLE(x)                         (((x) & 0x1) << 13)
+#define   G_028814_POLY_OFFSET_PARA_ENABLE(x)                         (((x) >> 13) & 0x1)
+#define   C_028814_POLY_OFFSET_PARA_ENABLE                            0xFFFFDFFF
+#define   S_028814_VTX_WINDOW_OFFSET_ENABLE(x)                        (((x) & 0x1) << 16)
+#define   G_028814_VTX_WINDOW_OFFSET_ENABLE(x)                        (((x) >> 16) & 0x1)
+#define   C_028814_VTX_WINDOW_OFFSET_ENABLE                           0xFFFEFFFF
+#define   S_028814_PROVOKING_VTX_LAST(x)                              (((x) & 0x1) << 19)
+#define   G_028814_PROVOKING_VTX_LAST(x)                              (((x) >> 19) & 0x1)
+#define   C_028814_PROVOKING_VTX_LAST                                 0xFFF7FFFF
+#define   S_028814_PERSP_CORR_DIS(x)                                  (((x) & 0x1) << 20)
+#define   G_028814_PERSP_CORR_DIS(x)                                  (((x) >> 20) & 0x1)
+#define   C_028814_PERSP_CORR_DIS                                     0xFFEFFFFF
+#define   S_028814_MULTI_PRIM_IB_ENA(x)                               (((x) & 0x1) << 21)
+#define   G_028814_MULTI_PRIM_IB_ENA(x)                               (((x) >> 21) & 0x1)
+#define   C_028814_MULTI_PRIM_IB_ENA                                  0xFFDFFFFF
+#define R_028818_PA_CL_VTE_CNTL                                         0x028818
+#define   S_028818_VPORT_X_SCALE_ENA(x)                               (((x) & 0x1) << 0)
+#define   G_028818_VPORT_X_SCALE_ENA(x)                               (((x) >> 0) & 0x1)
+#define   C_028818_VPORT_X_SCALE_ENA                                  0xFFFFFFFE
+#define   S_028818_VPORT_X_OFFSET_ENA(x)                              (((x) & 0x1) << 1)
+#define   G_028818_VPORT_X_OFFSET_ENA(x)                              (((x) >> 1) & 0x1)
+#define   C_028818_VPORT_X_OFFSET_ENA                                 0xFFFFFFFD
+#define   S_028818_VPORT_Y_SCALE_ENA(x)                               (((x) & 0x1) << 2)
+#define   G_028818_VPORT_Y_SCALE_ENA(x)                               (((x) >> 2) & 0x1)
+#define   C_028818_VPORT_Y_SCALE_ENA                                  0xFFFFFFFB
+#define   S_028818_VPORT_Y_OFFSET_ENA(x)                              (((x) & 0x1) << 3)
+#define   G_028818_VPORT_Y_OFFSET_ENA(x)                              (((x) >> 3) & 0x1)
+#define   C_028818_VPORT_Y_OFFSET_ENA                                 0xFFFFFFF7
+#define   S_028818_VPORT_Z_SCALE_ENA(x)                               (((x) & 0x1) << 4)
+#define   G_028818_VPORT_Z_SCALE_ENA(x)                               (((x) >> 4) & 0x1)
+#define   C_028818_VPORT_Z_SCALE_ENA                                  0xFFFFFFEF
+#define   S_028818_VPORT_Z_OFFSET_ENA(x)                              (((x) & 0x1) << 5)
+#define   G_028818_VPORT_Z_OFFSET_ENA(x)                              (((x) >> 5) & 0x1)
+#define   C_028818_VPORT_Z_OFFSET_ENA                                 0xFFFFFFDF
+#define   S_028818_VTX_XY_FMT(x)                                      (((x) & 0x1) << 8)
+#define   G_028818_VTX_XY_FMT(x)                                      (((x) >> 8) & 0x1)
+#define   C_028818_VTX_XY_FMT                                         0xFFFFFEFF
+#define   S_028818_VTX_Z_FMT(x)                                       (((x) & 0x1) << 9)
+#define   G_028818_VTX_Z_FMT(x)                                       (((x) >> 9) & 0x1)
+#define   C_028818_VTX_Z_FMT                                          0xFFFFFDFF
+#define   S_028818_VTX_W0_FMT(x)                                      (((x) & 0x1) << 10)
+#define   G_028818_VTX_W0_FMT(x)                                      (((x) >> 10) & 0x1)
+#define   C_028818_VTX_W0_FMT                                         0xFFFFFBFF
+#define R_02881C_PA_CL_VS_OUT_CNTL                                      0x02881C
+#define   S_02881C_CLIP_DIST_ENA_0(x)                                 (((x) & 0x1) << 0)
+#define   G_02881C_CLIP_DIST_ENA_0(x)                                 (((x) >> 0) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_0                                    0xFFFFFFFE
+#define   S_02881C_CLIP_DIST_ENA_1(x)                                 (((x) & 0x1) << 1)
+#define   G_02881C_CLIP_DIST_ENA_1(x)                                 (((x) >> 1) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_1                                    0xFFFFFFFD
+#define   S_02881C_CLIP_DIST_ENA_2(x)                                 (((x) & 0x1) << 2)
+#define   G_02881C_CLIP_DIST_ENA_2(x)                                 (((x) >> 2) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_2                                    0xFFFFFFFB
+#define   S_02881C_CLIP_DIST_ENA_3(x)                                 (((x) & 0x1) << 3)
+#define   G_02881C_CLIP_DIST_ENA_3(x)                                 (((x) >> 3) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_3                                    0xFFFFFFF7
+#define   S_02881C_CLIP_DIST_ENA_4(x)                                 (((x) & 0x1) << 4)
+#define   G_02881C_CLIP_DIST_ENA_4(x)                                 (((x) >> 4) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_4                                    0xFFFFFFEF
+#define   S_02881C_CLIP_DIST_ENA_5(x)                                 (((x) & 0x1) << 5)
+#define   G_02881C_CLIP_DIST_ENA_5(x)                                 (((x) >> 5) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_5                                    0xFFFFFFDF
+#define   S_02881C_CLIP_DIST_ENA_6(x)                                 (((x) & 0x1) << 6)
+#define   G_02881C_CLIP_DIST_ENA_6(x)                                 (((x) >> 6) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_6                                    0xFFFFFFBF
+#define   S_02881C_CLIP_DIST_ENA_7(x)                                 (((x) & 0x1) << 7)
+#define   G_02881C_CLIP_DIST_ENA_7(x)                                 (((x) >> 7) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_7                                    0xFFFFFF7F
+#define   S_02881C_CULL_DIST_ENA_0(x)                                 (((x) & 0x1) << 8)
+#define   G_02881C_CULL_DIST_ENA_0(x)                                 (((x) >> 8) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_0                                    0xFFFFFEFF
+#define   S_02881C_CULL_DIST_ENA_1(x)                                 (((x) & 0x1) << 9)
+#define   G_02881C_CULL_DIST_ENA_1(x)                                 (((x) >> 9) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_1                                    0xFFFFFDFF
+#define   S_02881C_CULL_DIST_ENA_2(x)                                 (((x) & 0x1) << 10)
+#define   G_02881C_CULL_DIST_ENA_2(x)                                 (((x) >> 10) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_2                                    0xFFFFFBFF
+#define   S_02881C_CULL_DIST_ENA_3(x)                                 (((x) & 0x1) << 11)
+#define   G_02881C_CULL_DIST_ENA_3(x)                                 (((x) >> 11) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_3                                    0xFFFFF7FF
+#define   S_02881C_CULL_DIST_ENA_4(x)                                 (((x) & 0x1) << 12)
+#define   G_02881C_CULL_DIST_ENA_4(x)                                 (((x) >> 12) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_4                                    0xFFFFEFFF
+#define   S_02881C_CULL_DIST_ENA_5(x)                                 (((x) & 0x1) << 13)
+#define   G_02881C_CULL_DIST_ENA_5(x)                                 (((x) >> 13) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_5                                    0xFFFFDFFF
+#define   S_02881C_CULL_DIST_ENA_6(x)                                 (((x) & 0x1) << 14)
+#define   G_02881C_CULL_DIST_ENA_6(x)                                 (((x) >> 14) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_6                                    0xFFFFBFFF
+#define   S_02881C_CULL_DIST_ENA_7(x)                                 (((x) & 0x1) << 15)
+#define   G_02881C_CULL_DIST_ENA_7(x)                                 (((x) >> 15) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_7                                    0xFFFF7FFF
+#define   S_02881C_USE_VTX_POINT_SIZE(x)                              (((x) & 0x1) << 16)
+#define   G_02881C_USE_VTX_POINT_SIZE(x)                              (((x) >> 16) & 0x1)
+#define   C_02881C_USE_VTX_POINT_SIZE                                 0xFFFEFFFF
+#define   S_02881C_USE_VTX_EDGE_FLAG(x)                               (((x) & 0x1) << 17)
+#define   G_02881C_USE_VTX_EDGE_FLAG(x)                               (((x) >> 17) & 0x1)
+#define   C_02881C_USE_VTX_EDGE_FLAG                                  0xFFFDFFFF
+#define   S_02881C_USE_VTX_RENDER_TARGET_INDX(x)                      (((x) & 0x1) << 18)
+#define   G_02881C_USE_VTX_RENDER_TARGET_INDX(x)                      (((x) >> 18) & 0x1)
+#define   C_02881C_USE_VTX_RENDER_TARGET_INDX                         0xFFFBFFFF
+#define   S_02881C_USE_VTX_VIEWPORT_INDX(x)                           (((x) & 0x1) << 19)
+#define   G_02881C_USE_VTX_VIEWPORT_INDX(x)                           (((x) >> 19) & 0x1)
+#define   C_02881C_USE_VTX_VIEWPORT_INDX                              0xFFF7FFFF
+#define   S_02881C_USE_VTX_KILL_FLAG(x)                               (((x) & 0x1) << 20)
+#define   G_02881C_USE_VTX_KILL_FLAG(x)                               (((x) >> 20) & 0x1)
+#define   C_02881C_USE_VTX_KILL_FLAG                                  0xFFEFFFFF
+#define   S_02881C_VS_OUT_MISC_VEC_ENA(x)                             (((x) & 0x1) << 21)
+#define   G_02881C_VS_OUT_MISC_VEC_ENA(x)                             (((x) >> 21) & 0x1)
+#define   C_02881C_VS_OUT_MISC_VEC_ENA                                0xFFDFFFFF
+#define   S_02881C_VS_OUT_CCDIST0_VEC_ENA(x)                          (((x) & 0x1) << 22)
+#define   G_02881C_VS_OUT_CCDIST0_VEC_ENA(x)                          (((x) >> 22) & 0x1)
+#define   C_02881C_VS_OUT_CCDIST0_VEC_ENA                             0xFFBFFFFF
+#define   S_02881C_VS_OUT_CCDIST1_VEC_ENA(x)                          (((x) & 0x1) << 23)
+#define   G_02881C_VS_OUT_CCDIST1_VEC_ENA(x)                          (((x) >> 23) & 0x1)
+#define   C_02881C_VS_OUT_CCDIST1_VEC_ENA                             0xFF7FFFFF
+#define   S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(x)                        (((x) & 0x1) << 24)
+#define   G_02881C_VS_OUT_MISC_SIDE_BUS_ENA(x)                        (((x) >> 24) & 0x1)
+#define   C_02881C_VS_OUT_MISC_SIDE_BUS_ENA                           0xFEFFFFFF
+#define   S_02881C_USE_VTX_GS_CUT_FLAG(x)                             (((x) & 0x1) << 25)
+#define   G_02881C_USE_VTX_GS_CUT_FLAG(x)                             (((x) >> 25) & 0x1)
+#define   C_02881C_USE_VTX_GS_CUT_FLAG                                0xFDFFFFFF
+#define R_028820_PA_CL_NANINF_CNTL                                      0x028820
+#define   S_028820_VTE_XY_INF_DISCARD(x)                              (((x) & 0x1) << 0)
+#define   G_028820_VTE_XY_INF_DISCARD(x)                              (((x) >> 0) & 0x1)
+#define   C_028820_VTE_XY_INF_DISCARD                                 0xFFFFFFFE
+#define   S_028820_VTE_Z_INF_DISCARD(x)                               (((x) & 0x1) << 1)
+#define   G_028820_VTE_Z_INF_DISCARD(x)                               (((x) >> 1) & 0x1)
+#define   C_028820_VTE_Z_INF_DISCARD                                  0xFFFFFFFD
+#define   S_028820_VTE_W_INF_DISCARD(x)                               (((x) & 0x1) << 2)
+#define   G_028820_VTE_W_INF_DISCARD(x)                               (((x) >> 2) & 0x1)
+#define   C_028820_VTE_W_INF_DISCARD                                  0xFFFFFFFB
+#define   S_028820_VTE_0XNANINF_IS_0(x)                               (((x) & 0x1) << 3)
+#define   G_028820_VTE_0XNANINF_IS_0(x)                               (((x) >> 3) & 0x1)
+#define   C_028820_VTE_0XNANINF_IS_0                                  0xFFFFFFF7
+#define   S_028820_VTE_XY_NAN_RETAIN(x)                               (((x) & 0x1) << 4)
+#define   G_028820_VTE_XY_NAN_RETAIN(x)                               (((x) >> 4) & 0x1)
+#define   C_028820_VTE_XY_NAN_RETAIN                                  0xFFFFFFEF
+#define   S_028820_VTE_Z_NAN_RETAIN(x)                                (((x) & 0x1) << 5)
+#define   G_028820_VTE_Z_NAN_RETAIN(x)                                (((x) >> 5) & 0x1)
+#define   C_028820_VTE_Z_NAN_RETAIN                                   0xFFFFFFDF
+#define   S_028820_VTE_W_NAN_RETAIN(x)                                (((x) & 0x1) << 6)
+#define   G_028820_VTE_W_NAN_RETAIN(x)                                (((x) >> 6) & 0x1)
+#define   C_028820_VTE_W_NAN_RETAIN                                   0xFFFFFFBF
+#define   S_028820_VTE_W_RECIP_NAN_IS_0(x)                            (((x) & 0x1) << 7)
+#define   G_028820_VTE_W_RECIP_NAN_IS_0(x)                            (((x) >> 7) & 0x1)
+#define   C_028820_VTE_W_RECIP_NAN_IS_0                               0xFFFFFF7F
+#define   S_028820_VS_XY_NAN_TO_INF(x)                                (((x) & 0x1) << 8)
+#define   G_028820_VS_XY_NAN_TO_INF(x)                                (((x) >> 8) & 0x1)
+#define   C_028820_VS_XY_NAN_TO_INF                                   0xFFFFFEFF
+#define   S_028820_VS_XY_INF_RETAIN(x)                                (((x) & 0x1) << 9)
+#define   G_028820_VS_XY_INF_RETAIN(x)                                (((x) >> 9) & 0x1)
+#define   C_028820_VS_XY_INF_RETAIN                                   0xFFFFFDFF
+#define   S_028820_VS_Z_NAN_TO_INF(x)                                 (((x) & 0x1) << 10)
+#define   G_028820_VS_Z_NAN_TO_INF(x)                                 (((x) >> 10) & 0x1)
+#define   C_028820_VS_Z_NAN_TO_INF                                    0xFFFFFBFF
+#define   S_028820_VS_Z_INF_RETAIN(x)                                 (((x) & 0x1) << 11)
+#define   G_028820_VS_Z_INF_RETAIN(x)                                 (((x) >> 11) & 0x1)
+#define   C_028820_VS_Z_INF_RETAIN                                    0xFFFFF7FF
+#define   S_028820_VS_W_NAN_TO_INF(x)                                 (((x) & 0x1) << 12)
+#define   G_028820_VS_W_NAN_TO_INF(x)                                 (((x) >> 12) & 0x1)
+#define   C_028820_VS_W_NAN_TO_INF                                    0xFFFFEFFF
+#define   S_028820_VS_W_INF_RETAIN(x)                                 (((x) & 0x1) << 13)
+#define   G_028820_VS_W_INF_RETAIN(x)                                 (((x) >> 13) & 0x1)
+#define   C_028820_VS_W_INF_RETAIN                                    0xFFFFDFFF
+#define   S_028820_VS_CLIP_DIST_INF_DISCARD(x)                        (((x) & 0x1) << 14)
+#define   G_028820_VS_CLIP_DIST_INF_DISCARD(x)                        (((x) >> 14) & 0x1)
+#define   C_028820_VS_CLIP_DIST_INF_DISCARD                           0xFFFFBFFF
+#define   S_028820_VTE_NO_OUTPUT_NEG_0(x)                             (((x) & 0x1) << 20)
+#define   G_028820_VTE_NO_OUTPUT_NEG_0(x)                             (((x) >> 20) & 0x1)
+#define   C_028820_VTE_NO_OUTPUT_NEG_0                                0xFFEFFFFF
+#define R_028824_PA_SU_LINE_STIPPLE_CNTL                                0x028824
+#define   S_028824_LINE_STIPPLE_RESET(x)                              (((x) & 0x03) << 0)
+#define   G_028824_LINE_STIPPLE_RESET(x)                              (((x) >> 0) & 0x03)
+#define   C_028824_LINE_STIPPLE_RESET                                 0xFFFFFFFC
+#define   S_028824_EXPAND_FULL_LENGTH(x)                              (((x) & 0x1) << 2)
+#define   G_028824_EXPAND_FULL_LENGTH(x)                              (((x) >> 2) & 0x1)
+#define   C_028824_EXPAND_FULL_LENGTH                                 0xFFFFFFFB
+#define   S_028824_FRACTIONAL_ACCUM(x)                                (((x) & 0x1) << 3)
+#define   G_028824_FRACTIONAL_ACCUM(x)                                (((x) >> 3) & 0x1)
+#define   C_028824_FRACTIONAL_ACCUM                                   0xFFFFFFF7
+#define   S_028824_DIAMOND_ADJUST(x)                                  (((x) & 0x1) << 4)
+#define   G_028824_DIAMOND_ADJUST(x)                                  (((x) >> 4) & 0x1)
+#define   C_028824_DIAMOND_ADJUST                                     0xFFFFFFEF
+#define R_028828_PA_SU_LINE_STIPPLE_SCALE                               0x028828
+#define R_02882C_PA_SU_PRIM_FILTER_CNTL                                 0x02882C
+#define   S_02882C_TRIANGLE_FILTER_DISABLE(x)                         (((x) & 0x1) << 0)
+#define   G_02882C_TRIANGLE_FILTER_DISABLE(x)                         (((x) >> 0) & 0x1)
+#define   C_02882C_TRIANGLE_FILTER_DISABLE                            0xFFFFFFFE
+#define   S_02882C_LINE_FILTER_DISABLE(x)                             (((x) & 0x1) << 1)
+#define   G_02882C_LINE_FILTER_DISABLE(x)                             (((x) >> 1) & 0x1)
+#define   C_02882C_LINE_FILTER_DISABLE                                0xFFFFFFFD
+#define   S_02882C_POINT_FILTER_DISABLE(x)                            (((x) & 0x1) << 2)
+#define   G_02882C_POINT_FILTER_DISABLE(x)                            (((x) >> 2) & 0x1)
+#define   C_02882C_POINT_FILTER_DISABLE                               0xFFFFFFFB
+#define   S_02882C_RECTANGLE_FILTER_DISABLE(x)                        (((x) & 0x1) << 3)
+#define   G_02882C_RECTANGLE_FILTER_DISABLE(x)                        (((x) >> 3) & 0x1)
+#define   C_02882C_RECTANGLE_FILTER_DISABLE                           0xFFFFFFF7
+#define   S_02882C_TRIANGLE_EXPAND_ENA(x)                             (((x) & 0x1) << 4)
+#define   G_02882C_TRIANGLE_EXPAND_ENA(x)                             (((x) >> 4) & 0x1)
+#define   C_02882C_TRIANGLE_EXPAND_ENA                                0xFFFFFFEF
+#define   S_02882C_LINE_EXPAND_ENA(x)                                 (((x) & 0x1) << 5)
+#define   G_02882C_LINE_EXPAND_ENA(x)                                 (((x) >> 5) & 0x1)
+#define   C_02882C_LINE_EXPAND_ENA                                    0xFFFFFFDF
+#define   S_02882C_POINT_EXPAND_ENA(x)                                (((x) & 0x1) << 6)
+#define   G_02882C_POINT_EXPAND_ENA(x)                                (((x) >> 6) & 0x1)
+#define   C_02882C_POINT_EXPAND_ENA                                   0xFFFFFFBF
+#define   S_02882C_RECTANGLE_EXPAND_ENA(x)                            (((x) & 0x1) << 7)
+#define   G_02882C_RECTANGLE_EXPAND_ENA(x)                            (((x) >> 7) & 0x1)
+#define   C_02882C_RECTANGLE_EXPAND_ENA                               0xFFFFFF7F
+#define   S_02882C_PRIM_EXPAND_CONSTANT(x)                            (((x) & 0xFF) << 8)
+#define   G_02882C_PRIM_EXPAND_CONSTANT(x)                            (((x) >> 8) & 0xFF)
+#define   C_02882C_PRIM_EXPAND_CONSTANT                               0xFFFF00FF
+/* CIK */
+#define   S_02882C_XMAX_RIGHT_EXCLUSION(x)                            (((x) & 0x1) << 30)
+#define   G_02882C_XMAX_RIGHT_EXCLUSION(x)                            (((x) >> 30) & 0x1)
+#define   C_02882C_XMAX_RIGHT_EXCLUSION                               0xBFFFFFFF
+#define   S_02882C_YMAX_BOTTOM_EXCLUSION(x)                           (((x) & 0x1) << 31)
+#define   G_02882C_YMAX_BOTTOM_EXCLUSION(x)                           (((x) >> 31) & 0x1)
+#define   C_02882C_YMAX_BOTTOM_EXCLUSION                              0x7FFFFFFF
+/*     */
+#define R_028A00_PA_SU_POINT_SIZE                                       0x028A00
+#define   S_028A00_HEIGHT(x)                                          (((x) & 0xFFFF) << 0)
+#define   G_028A00_HEIGHT(x)                                          (((x) >> 0) & 0xFFFF)
+#define   C_028A00_HEIGHT                                             0xFFFF0000
+#define   S_028A00_WIDTH(x)                                           (((x) & 0xFFFF) << 16)
+#define   G_028A00_WIDTH(x)                                           (((x) >> 16) & 0xFFFF)
+#define   C_028A00_WIDTH                                              0x0000FFFF
+#define R_028A04_PA_SU_POINT_MINMAX                                     0x028A04
+#define   S_028A04_MIN_SIZE(x)                                        (((x) & 0xFFFF) << 0)
+#define   G_028A04_MIN_SIZE(x)                                        (((x) >> 0) & 0xFFFF)
+#define   C_028A04_MIN_SIZE                                           0xFFFF0000
+#define   S_028A04_MAX_SIZE(x)                                        (((x) & 0xFFFF) << 16)
+#define   G_028A04_MAX_SIZE(x)                                        (((x) >> 16) & 0xFFFF)
+#define   C_028A04_MAX_SIZE                                           0x0000FFFF
+#define R_028A08_PA_SU_LINE_CNTL                                        0x028A08
+#define   S_028A08_WIDTH(x)                                           (((x) & 0xFFFF) << 0)
+#define   G_028A08_WIDTH(x)                                           (((x) >> 0) & 0xFFFF)
+#define   C_028A08_WIDTH                                              0xFFFF0000
+#define R_028A0C_PA_SC_LINE_STIPPLE                                     0x028A0C
+#define   S_028A0C_LINE_PATTERN(x)                                    (((x) & 0xFFFF) << 0)
+#define   G_028A0C_LINE_PATTERN(x)                                    (((x) >> 0) & 0xFFFF)
+#define   C_028A0C_LINE_PATTERN                                       0xFFFF0000
+#define   S_028A0C_REPEAT_COUNT(x)                                    (((x) & 0xFF) << 16)
+#define   G_028A0C_REPEAT_COUNT(x)                                    (((x) >> 16) & 0xFF)
+#define   C_028A0C_REPEAT_COUNT                                       0xFF00FFFF
+#define   S_028A0C_PATTERN_BIT_ORDER(x)                               (((x) & 0x1) << 28)
+#define   G_028A0C_PATTERN_BIT_ORDER(x)                               (((x) >> 28) & 0x1)
+#define   C_028A0C_PATTERN_BIT_ORDER                                  0xEFFFFFFF
+#define   S_028A0C_AUTO_RESET_CNTL(x)                                 (((x) & 0x03) << 29)
+#define   G_028A0C_AUTO_RESET_CNTL(x)                                 (((x) >> 29) & 0x03)
+#define   C_028A0C_AUTO_RESET_CNTL                                    0x9FFFFFFF
+#define R_028A10_VGT_OUTPUT_PATH_CNTL                                   0x028A10
+#define   S_028A10_PATH_SELECT(x)                                     (((x) & 0x07) << 0)
+#define   G_028A10_PATH_SELECT(x)                                     (((x) >> 0) & 0x07)
+#define   C_028A10_PATH_SELECT                                        0xFFFFFFF8
+#define     V_028A10_VGT_OUTPATH_VTX_REUSE                          0x00
+#define     V_028A10_VGT_OUTPATH_TESS_EN                            0x01
+#define     V_028A10_VGT_OUTPATH_PASSTHRU                           0x02
+#define     V_028A10_VGT_OUTPATH_GS_BLOCK                           0x03
+#define     V_028A10_VGT_OUTPATH_HS_BLOCK                           0x04
+#define R_028A14_VGT_HOS_CNTL                                           0x028A14
+#define   S_028A14_TESS_MODE(x)                                       (((x) & 0x03) << 0)
+#define   G_028A14_TESS_MODE(x)                                       (((x) >> 0) & 0x03)
+#define   C_028A14_TESS_MODE                                          0xFFFFFFFC
+#define R_028A18_VGT_HOS_MAX_TESS_LEVEL                                 0x028A18
+#define R_028A1C_VGT_HOS_MIN_TESS_LEVEL                                 0x028A1C
+#define R_028A20_VGT_HOS_REUSE_DEPTH                                    0x028A20
+#define   S_028A20_REUSE_DEPTH(x)                                     (((x) & 0xFF) << 0)
+#define   G_028A20_REUSE_DEPTH(x)                                     (((x) >> 0) & 0xFF)
+#define   C_028A20_REUSE_DEPTH                                        0xFFFFFF00
+#define R_028A24_VGT_GROUP_PRIM_TYPE                                    0x028A24
+#define   S_028A24_PRIM_TYPE(x)                                       (((x) & 0x1F) << 0)
+#define   G_028A24_PRIM_TYPE(x)                                       (((x) >> 0) & 0x1F)
+#define   C_028A24_PRIM_TYPE                                          0xFFFFFFE0
+#define     V_028A24_VGT_GRP_3D_POINT                               0x00
+#define     V_028A24_VGT_GRP_3D_LINE                                0x01
+#define     V_028A24_VGT_GRP_3D_TRI                                 0x02
+#define     V_028A24_VGT_GRP_3D_RECT                                0x03
+#define     V_028A24_VGT_GRP_3D_QUAD                                0x04
+#define     V_028A24_VGT_GRP_2D_COPY_RECT_V0                        0x05
+#define     V_028A24_VGT_GRP_2D_COPY_RECT_V1                        0x06
+#define     V_028A24_VGT_GRP_2D_COPY_RECT_V2                        0x07
+#define     V_028A24_VGT_GRP_2D_COPY_RECT_V3                        0x08
+#define     V_028A24_VGT_GRP_2D_FILL_RECT                           0x09
+#define     V_028A24_VGT_GRP_2D_LINE                                0x0A
+#define     V_028A24_VGT_GRP_2D_TRI                                 0x0B
+#define     V_028A24_VGT_GRP_PRIM_INDEX_LINE                        0x0C
+#define     V_028A24_VGT_GRP_PRIM_INDEX_TRI                         0x0D
+#define     V_028A24_VGT_GRP_PRIM_INDEX_QUAD                        0x0E
+#define     V_028A24_VGT_GRP_3D_LINE_ADJ                            0x0F
+#define     V_028A24_VGT_GRP_3D_TRI_ADJ                             0x10
+#define     V_028A24_VGT_GRP_3D_PATCH                               0x11
+#define   S_028A24_RETAIN_ORDER(x)                                    (((x) & 0x1) << 14)
+#define   G_028A24_RETAIN_ORDER(x)                                    (((x) >> 14) & 0x1)
+#define   C_028A24_RETAIN_ORDER                                       0xFFFFBFFF
+#define   S_028A24_RETAIN_QUADS(x)                                    (((x) & 0x1) << 15)
+#define   G_028A24_RETAIN_QUADS(x)                                    (((x) >> 15) & 0x1)
+#define   C_028A24_RETAIN_QUADS                                       0xFFFF7FFF
+#define   S_028A24_PRIM_ORDER(x)                                      (((x) & 0x07) << 16)
+#define   G_028A24_PRIM_ORDER(x)                                      (((x) >> 16) & 0x07)
+#define   C_028A24_PRIM_ORDER                                         0xFFF8FFFF
+#define     V_028A24_VGT_GRP_LIST                                   0x00
+#define     V_028A24_VGT_GRP_STRIP                                  0x01
+#define     V_028A24_VGT_GRP_FAN                                    0x02
+#define     V_028A24_VGT_GRP_LOOP                                   0x03
+#define     V_028A24_VGT_GRP_POLYGON                                0x04
+#define R_028A28_VGT_GROUP_FIRST_DECR                                   0x028A28
+#define   S_028A28_FIRST_DECR(x)                                      (((x) & 0x0F) << 0)
+#define   G_028A28_FIRST_DECR(x)                                      (((x) >> 0) & 0x0F)
+#define   C_028A28_FIRST_DECR                                         0xFFFFFFF0
+#define R_028A2C_VGT_GROUP_DECR                                         0x028A2C
+#define   S_028A2C_DECR(x)                                            (((x) & 0x0F) << 0)
+#define   G_028A2C_DECR(x)                                            (((x) >> 0) & 0x0F)
+#define   C_028A2C_DECR                                               0xFFFFFFF0
+#define R_028A30_VGT_GROUP_VECT_0_CNTL                                  0x028A30
+#define   S_028A30_COMP_X_EN(x)                                       (((x) & 0x1) << 0)
+#define   G_028A30_COMP_X_EN(x)                                       (((x) >> 0) & 0x1)
+#define   C_028A30_COMP_X_EN                                          0xFFFFFFFE
+#define   S_028A30_COMP_Y_EN(x)                                       (((x) & 0x1) << 1)
+#define   G_028A30_COMP_Y_EN(x)                                       (((x) >> 1) & 0x1)
+#define   C_028A30_COMP_Y_EN                                          0xFFFFFFFD
+#define   S_028A30_COMP_Z_EN(x)                                       (((x) & 0x1) << 2)
+#define   G_028A30_COMP_Z_EN(x)                                       (((x) >> 2) & 0x1)
+#define   C_028A30_COMP_Z_EN                                          0xFFFFFFFB
+#define   S_028A30_COMP_W_EN(x)                                       (((x) & 0x1) << 3)
+#define   G_028A30_COMP_W_EN(x)                                       (((x) >> 3) & 0x1)
+#define   C_028A30_COMP_W_EN                                          0xFFFFFFF7
+#define   S_028A30_STRIDE(x)                                          (((x) & 0xFF) << 8)
+#define   G_028A30_STRIDE(x)                                          (((x) >> 8) & 0xFF)
+#define   C_028A30_STRIDE                                             0xFFFF00FF
+#define   S_028A30_SHIFT(x)                                           (((x) & 0xFF) << 16)
+#define   G_028A30_SHIFT(x)                                           (((x) >> 16) & 0xFF)
+#define   C_028A30_SHIFT                                              0xFF00FFFF
+#define R_028A34_VGT_GROUP_VECT_1_CNTL                                  0x028A34
+#define   S_028A34_COMP_X_EN(x)                                       (((x) & 0x1) << 0)
+#define   G_028A34_COMP_X_EN(x)                                       (((x) >> 0) & 0x1)
+#define   C_028A34_COMP_X_EN                                          0xFFFFFFFE
+#define   S_028A34_COMP_Y_EN(x)                                       (((x) & 0x1) << 1)
+#define   G_028A34_COMP_Y_EN(x)                                       (((x) >> 1) & 0x1)
+#define   C_028A34_COMP_Y_EN                                          0xFFFFFFFD
+#define   S_028A34_COMP_Z_EN(x)                                       (((x) & 0x1) << 2)
+#define   G_028A34_COMP_Z_EN(x)                                       (((x) >> 2) & 0x1)
+#define   C_028A34_COMP_Z_EN                                          0xFFFFFFFB
+#define   S_028A34_COMP_W_EN(x)                                       (((x) & 0x1) << 3)
+#define   G_028A34_COMP_W_EN(x)                                       (((x) >> 3) & 0x1)
+#define   C_028A34_COMP_W_EN                                          0xFFFFFFF7
+#define   S_028A34_STRIDE(x)                                          (((x) & 0xFF) << 8)
+#define   G_028A34_STRIDE(x)                                          (((x) >> 8) & 0xFF)
+#define   C_028A34_STRIDE                                             0xFFFF00FF
+#define   S_028A34_SHIFT(x)                                           (((x) & 0xFF) << 16)
+#define   G_028A34_SHIFT(x)                                           (((x) >> 16) & 0xFF)
+#define   C_028A34_SHIFT                                              0xFF00FFFF
+#define R_028A38_VGT_GROUP_VECT_0_FMT_CNTL                              0x028A38
+#define   S_028A38_X_CONV(x)                                          (((x) & 0x0F) << 0)
+#define   G_028A38_X_CONV(x)                                          (((x) >> 0) & 0x0F)
+#define   C_028A38_X_CONV                                             0xFFFFFFF0
+#define     V_028A38_VGT_GRP_INDEX_16                               0x00
+#define     V_028A38_VGT_GRP_INDEX_32                               0x01
+#define     V_028A38_VGT_GRP_UINT_16                                0x02
+#define     V_028A38_VGT_GRP_UINT_32                                0x03
+#define     V_028A38_VGT_GRP_SINT_16                                0x04
+#define     V_028A38_VGT_GRP_SINT_32                                0x05
+#define     V_028A38_VGT_GRP_FLOAT_32                               0x06
+#define     V_028A38_VGT_GRP_AUTO_PRIM                              0x07
+#define     V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT                      0x08
+#define   S_028A38_X_OFFSET(x)                                        (((x) & 0x0F) << 4)
+#define   G_028A38_X_OFFSET(x)                                        (((x) >> 4) & 0x0F)
+#define   C_028A38_X_OFFSET                                           0xFFFFFF0F
+#define   S_028A38_Y_CONV(x)                                          (((x) & 0x0F) << 8)
+#define   G_028A38_Y_CONV(x)                                          (((x) >> 8) & 0x0F)
+#define   C_028A38_Y_CONV                                             0xFFFFF0FF
+#define     V_028A38_VGT_GRP_INDEX_16                               0x00
+#define     V_028A38_VGT_GRP_INDEX_32                               0x01
+#define     V_028A38_VGT_GRP_UINT_16                                0x02
+#define     V_028A38_VGT_GRP_UINT_32                                0x03
+#define     V_028A38_VGT_GRP_SINT_16                                0x04
+#define     V_028A38_VGT_GRP_SINT_32                                0x05
+#define     V_028A38_VGT_GRP_FLOAT_32                               0x06
+#define     V_028A38_VGT_GRP_AUTO_PRIM                              0x07
+#define     V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT                      0x08
+#define   S_028A38_Y_OFFSET(x)                                        (((x) & 0x0F) << 12)
+#define   G_028A38_Y_OFFSET(x)                                        (((x) >> 12) & 0x0F)
+#define   C_028A38_Y_OFFSET                                           0xFFFF0FFF
+#define   S_028A38_Z_CONV(x)                                          (((x) & 0x0F) << 16)
+#define   G_028A38_Z_CONV(x)                                          (((x) >> 16) & 0x0F)
+#define   C_028A38_Z_CONV                                             0xFFF0FFFF
+#define     V_028A38_VGT_GRP_INDEX_16                               0x00
+#define     V_028A38_VGT_GRP_INDEX_32                               0x01
+#define     V_028A38_VGT_GRP_UINT_16                                0x02
+#define     V_028A38_VGT_GRP_UINT_32                                0x03
+#define     V_028A38_VGT_GRP_SINT_16                                0x04
+#define     V_028A38_VGT_GRP_SINT_32                                0x05
+#define     V_028A38_VGT_GRP_FLOAT_32                               0x06
+#define     V_028A38_VGT_GRP_AUTO_PRIM                              0x07
+#define     V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT                      0x08
+#define   S_028A38_Z_OFFSET(x)                                        (((x) & 0x0F) << 20)
+#define   G_028A38_Z_OFFSET(x)                                        (((x) >> 20) & 0x0F)
+#define   C_028A38_Z_OFFSET                                           0xFF0FFFFF
+#define   S_028A38_W_CONV(x)                                          (((x) & 0x0F) << 24)
+#define   G_028A38_W_CONV(x)                                          (((x) >> 24) & 0x0F)
+#define   C_028A38_W_CONV                                             0xF0FFFFFF
+#define     V_028A38_VGT_GRP_INDEX_16                               0x00
+#define     V_028A38_VGT_GRP_INDEX_32                               0x01
+#define     V_028A38_VGT_GRP_UINT_16                                0x02
+#define     V_028A38_VGT_GRP_UINT_32                                0x03
+#define     V_028A38_VGT_GRP_SINT_16                                0x04
+#define     V_028A38_VGT_GRP_SINT_32                                0x05
+#define     V_028A38_VGT_GRP_FLOAT_32                               0x06
+#define     V_028A38_VGT_GRP_AUTO_PRIM                              0x07
+#define     V_028A38_VGT_GRP_FIX_1_23_TO_FLOAT                      0x08
+#define   S_028A38_W_OFFSET(x)                                        (((x) & 0x0F) << 28)
+#define   G_028A38_W_OFFSET(x)                                        (((x) >> 28) & 0x0F)
+#define   C_028A38_W_OFFSET                                           0x0FFFFFFF
+#define R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL                              0x028A3C
+#define   S_028A3C_X_CONV(x)                                          (((x) & 0x0F) << 0)
+#define   G_028A3C_X_CONV(x)                                          (((x) >> 0) & 0x0F)
+#define   C_028A3C_X_CONV                                             0xFFFFFFF0
+#define     V_028A3C_VGT_GRP_INDEX_16                               0x00
+#define     V_028A3C_VGT_GRP_INDEX_32                               0x01
+#define     V_028A3C_VGT_GRP_UINT_16                                0x02
+#define     V_028A3C_VGT_GRP_UINT_32                                0x03
+#define     V_028A3C_VGT_GRP_SINT_16                                0x04
+#define     V_028A3C_VGT_GRP_SINT_32                                0x05
+#define     V_028A3C_VGT_GRP_FLOAT_32                               0x06
+#define     V_028A3C_VGT_GRP_AUTO_PRIM                              0x07
+#define     V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT                      0x08
+#define   S_028A3C_X_OFFSET(x)                                        (((x) & 0x0F) << 4)
+#define   G_028A3C_X_OFFSET(x)                                        (((x) >> 4) & 0x0F)
+#define   C_028A3C_X_OFFSET                                           0xFFFFFF0F
+#define   S_028A3C_Y_CONV(x)                                          (((x) & 0x0F) << 8)
+#define   G_028A3C_Y_CONV(x)                                          (((x) >> 8) & 0x0F)
+#define   C_028A3C_Y_CONV                                             0xFFFFF0FF
+#define     V_028A3C_VGT_GRP_INDEX_16                               0x00
+#define     V_028A3C_VGT_GRP_INDEX_32                               0x01
+#define     V_028A3C_VGT_GRP_UINT_16                                0x02
+#define     V_028A3C_VGT_GRP_UINT_32                                0x03
+#define     V_028A3C_VGT_GRP_SINT_16                                0x04
+#define     V_028A3C_VGT_GRP_SINT_32                                0x05
+#define     V_028A3C_VGT_GRP_FLOAT_32                               0x06
+#define     V_028A3C_VGT_GRP_AUTO_PRIM                              0x07
+#define     V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT                      0x08
+#define   S_028A3C_Y_OFFSET(x)                                        (((x) & 0x0F) << 12)
+#define   G_028A3C_Y_OFFSET(x)                                        (((x) >> 12) & 0x0F)
+#define   C_028A3C_Y_OFFSET                                           0xFFFF0FFF
+#define   S_028A3C_Z_CONV(x)                                          (((x) & 0x0F) << 16)
+#define   G_028A3C_Z_CONV(x)                                          (((x) >> 16) & 0x0F)
+#define   C_028A3C_Z_CONV                                             0xFFF0FFFF
+#define     V_028A3C_VGT_GRP_INDEX_16                               0x00
+#define     V_028A3C_VGT_GRP_INDEX_32                               0x01
+#define     V_028A3C_VGT_GRP_UINT_16                                0x02
+#define     V_028A3C_VGT_GRP_UINT_32                                0x03
+#define     V_028A3C_VGT_GRP_SINT_16                                0x04
+#define     V_028A3C_VGT_GRP_SINT_32                                0x05
+#define     V_028A3C_VGT_GRP_FLOAT_32                               0x06
+#define     V_028A3C_VGT_GRP_AUTO_PRIM                              0x07
+#define     V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT                      0x08
+#define   S_028A3C_Z_OFFSET(x)                                        (((x) & 0x0F) << 20)
+#define   G_028A3C_Z_OFFSET(x)                                        (((x) >> 20) & 0x0F)
+#define   C_028A3C_Z_OFFSET                                           0xFF0FFFFF
+#define   S_028A3C_W_CONV(x)                                          (((x) & 0x0F) << 24)
+#define   G_028A3C_W_CONV(x)                                          (((x) >> 24) & 0x0F)
+#define   C_028A3C_W_CONV                                             0xF0FFFFFF
+#define     V_028A3C_VGT_GRP_INDEX_16                               0x00
+#define     V_028A3C_VGT_GRP_INDEX_32                               0x01
+#define     V_028A3C_VGT_GRP_UINT_16                                0x02
+#define     V_028A3C_VGT_GRP_UINT_32                                0x03
+#define     V_028A3C_VGT_GRP_SINT_16                                0x04
+#define     V_028A3C_VGT_GRP_SINT_32                                0x05
+#define     V_028A3C_VGT_GRP_FLOAT_32                               0x06
+#define     V_028A3C_VGT_GRP_AUTO_PRIM                              0x07
+#define     V_028A3C_VGT_GRP_FIX_1_23_TO_FLOAT                      0x08
+#define   S_028A3C_W_OFFSET(x)                                        (((x) & 0x0F) << 28)
+#define   G_028A3C_W_OFFSET(x)                                        (((x) >> 28) & 0x0F)
+#define   C_028A3C_W_OFFSET                                           0x0FFFFFFF
+#define R_028A40_VGT_GS_MODE                                            0x028A40
+#define   S_028A40_MODE(x)                                            (((x) & 0x07) << 0)
+#define   G_028A40_MODE(x)                                            (((x) >> 0) & 0x07)
+#define   C_028A40_MODE                                               0xFFFFFFF8
+#define     V_028A40_GS_OFF                                         0x00
+#define     V_028A40_GS_SCENARIO_A                                  0x01
+#define     V_028A40_GS_SCENARIO_B                                  0x02
+#define     V_028A40_GS_SCENARIO_G                                  0x03
+#define     V_028A40_GS_SCENARIO_C                                  0x04
+#define     V_028A40_SPRITE_EN                                      0x05
+#define   S_028A40_CUT_MODE(x)                                        (((x) & 0x03) << 4)
+#define   G_028A40_CUT_MODE(x)                                        (((x) >> 4) & 0x03)
+#define   C_028A40_CUT_MODE                                           0xFFFFFFCF
+#define     V_028A40_GS_CUT_1024                                    0x00
+#define     V_028A40_GS_CUT_512                                     0x01
+#define     V_028A40_GS_CUT_256                                     0x02
+#define     V_028A40_GS_CUT_128                                     0x03
+#define   S_028A40_GS_C_PACK_EN(x)                                    (((x) & 0x1) << 11)
+#define   G_028A40_GS_C_PACK_EN(x)                                    (((x) >> 11) & 0x1)
+#define   C_028A40_GS_C_PACK_EN                                       0xFFFFF7FF
+#define   S_028A40_ES_PASSTHRU(x)                                     (((x) & 0x1) << 13)
+#define   G_028A40_ES_PASSTHRU(x)                                     (((x) >> 13) & 0x1)
+#define   C_028A40_ES_PASSTHRU                                        0xFFFFDFFF
+#define   S_028A40_COMPUTE_MODE(x)                                    (((x) & 0x1) << 14)
+#define   G_028A40_COMPUTE_MODE(x)                                    (((x) >> 14) & 0x1)
+#define   C_028A40_COMPUTE_MODE                                       0xFFFFBFFF
+#define   S_028A40_FAST_COMPUTE_MODE(x)                               (((x) & 0x1) << 15)
+#define   G_028A40_FAST_COMPUTE_MODE(x)                               (((x) >> 15) & 0x1)
+#define   C_028A40_FAST_COMPUTE_MODE                                  0xFFFF7FFF
+#define   S_028A40_ELEMENT_INFO_EN(x)                                 (((x) & 0x1) << 16)
+#define   G_028A40_ELEMENT_INFO_EN(x)                                 (((x) >> 16) & 0x1)
+#define   C_028A40_ELEMENT_INFO_EN                                    0xFFFEFFFF
+#define   S_028A40_PARTIAL_THD_AT_EOI(x)                              (((x) & 0x1) << 17)
+#define   G_028A40_PARTIAL_THD_AT_EOI(x)                              (((x) >> 17) & 0x1)
+#define   C_028A40_PARTIAL_THD_AT_EOI                                 0xFFFDFFFF
+#define   S_028A40_SUPPRESS_CUTS(x)                                   (((x) & 0x1) << 18)
+#define   G_028A40_SUPPRESS_CUTS(x)                                   (((x) >> 18) & 0x1)
+#define   C_028A40_SUPPRESS_CUTS                                      0xFFFBFFFF
+#define   S_028A40_ES_WRITE_OPTIMIZE(x)                               (((x) & 0x1) << 19)
+#define   G_028A40_ES_WRITE_OPTIMIZE(x)                               (((x) >> 19) & 0x1)
+#define   C_028A40_ES_WRITE_OPTIMIZE                                  0xFFF7FFFF
+#define   S_028A40_GS_WRITE_OPTIMIZE(x)                               (((x) & 0x1) << 20)
+#define   G_028A40_GS_WRITE_OPTIMIZE(x)                               (((x) >> 20) & 0x1)
+#define   C_028A40_GS_WRITE_OPTIMIZE                                  0xFFEFFFFF
+/* CIK */
+#define   S_028A40_ONCHIP(x)                                          (((x) & 0x03) << 21)
+#define   G_028A40_ONCHIP(x)                                          (((x) >> 21) & 0x03)
+#define   C_028A40_ONCHIP                                             0xFF9FFFFF
+#define     V_028A40_X_0_OFFCHIP_GS                                 0x00
+#define     V_028A40_X_3_ES_AND_GS_ARE_ONCHIP                       0x03
+#define R_028A44_VGT_GS_ONCHIP_CNTL                                     0x028A44
+#define   S_028A44_ES_VERTS_PER_SUBGRP(x)                             (((x) & 0x7FF) << 0)
+#define   G_028A44_ES_VERTS_PER_SUBGRP(x)                             (((x) >> 0) & 0x7FF)
+#define   C_028A44_ES_VERTS_PER_SUBGRP                                0xFFFFF800
+#define   S_028A44_GS_PRIMS_PER_SUBGRP(x)                             (((x) & 0x7FF) << 11)
+#define   G_028A44_GS_PRIMS_PER_SUBGRP(x)                             (((x) >> 11) & 0x7FF)
+#define   C_028A44_GS_PRIMS_PER_SUBGRP                                0xFFC007FF
+/*     */
+#define R_028A48_PA_SC_MODE_CNTL_0                                      0x028A48
+#define   S_028A48_MSAA_ENABLE(x)                                     (((x) & 0x1) << 0)
+#define   G_028A48_MSAA_ENABLE(x)                                     (((x) >> 0) & 0x1)
+#define   C_028A48_MSAA_ENABLE                                        0xFFFFFFFE
+#define   S_028A48_VPORT_SCISSOR_ENABLE(x)                            (((x) & 0x1) << 1)
+#define   G_028A48_VPORT_SCISSOR_ENABLE(x)                            (((x) >> 1) & 0x1)
+#define   C_028A48_VPORT_SCISSOR_ENABLE                               0xFFFFFFFD
+#define   S_028A48_LINE_STIPPLE_ENABLE(x)                             (((x) & 0x1) << 2)
+#define   G_028A48_LINE_STIPPLE_ENABLE(x)                             (((x) >> 2) & 0x1)
+#define   C_028A48_LINE_STIPPLE_ENABLE                                0xFFFFFFFB
+#define   S_028A48_SEND_UNLIT_STILES_TO_PKR(x)                        (((x) & 0x1) << 3)
+#define   G_028A48_SEND_UNLIT_STILES_TO_PKR(x)                        (((x) >> 3) & 0x1)
+#define   C_028A48_SEND_UNLIT_STILES_TO_PKR                           0xFFFFFFF7
+#define R_028A4C_PA_SC_MODE_CNTL_1                                      0x028A4C
+#define   S_028A4C_WALK_SIZE(x)                                       (((x) & 0x1) << 0)
+#define   G_028A4C_WALK_SIZE(x)                                       (((x) >> 0) & 0x1)
+#define   C_028A4C_WALK_SIZE                                          0xFFFFFFFE
+#define   S_028A4C_WALK_ALIGNMENT(x)                                  (((x) & 0x1) << 1)
+#define   G_028A4C_WALK_ALIGNMENT(x)                                  (((x) >> 1) & 0x1)
+#define   C_028A4C_WALK_ALIGNMENT                                     0xFFFFFFFD
+#define   S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(x)                        (((x) & 0x1) << 2)
+#define   G_028A4C_WALK_ALIGN8_PRIM_FITS_ST(x)                        (((x) >> 2) & 0x1)
+#define   C_028A4C_WALK_ALIGN8_PRIM_FITS_ST                           0xFFFFFFFB
+#define   S_028A4C_WALK_FENCE_ENABLE(x)                               (((x) & 0x1) << 3)
+#define   G_028A4C_WALK_FENCE_ENABLE(x)                               (((x) >> 3) & 0x1)
+#define   C_028A4C_WALK_FENCE_ENABLE                                  0xFFFFFFF7
+#define   S_028A4C_WALK_FENCE_SIZE(x)                                 (((x) & 0x07) << 4)
+#define   G_028A4C_WALK_FENCE_SIZE(x)                                 (((x) >> 4) & 0x07)
+#define   C_028A4C_WALK_FENCE_SIZE                                    0xFFFFFF8F
+#define   S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(x)                     (((x) & 0x1) << 7)
+#define   G_028A4C_SUPERTILE_WALK_ORDER_ENABLE(x)                     (((x) >> 7) & 0x1)
+#define   C_028A4C_SUPERTILE_WALK_ORDER_ENABLE                        0xFFFFFF7F
+#define   S_028A4C_TILE_WALK_ORDER_ENABLE(x)                          (((x) & 0x1) << 8)
+#define   G_028A4C_TILE_WALK_ORDER_ENABLE(x)                          (((x) >> 8) & 0x1)
+#define   C_028A4C_TILE_WALK_ORDER_ENABLE                             0xFFFFFEFF
+#define   S_028A4C_TILE_COVER_DISABLE(x)                              (((x) & 0x1) << 9)
+#define   G_028A4C_TILE_COVER_DISABLE(x)                              (((x) >> 9) & 0x1)
+#define   C_028A4C_TILE_COVER_DISABLE                                 0xFFFFFDFF
+#define   S_028A4C_TILE_COVER_NO_SCISSOR(x)                           (((x) & 0x1) << 10)
+#define   G_028A4C_TILE_COVER_NO_SCISSOR(x)                           (((x) >> 10) & 0x1)
+#define   C_028A4C_TILE_COVER_NO_SCISSOR                              0xFFFFFBFF
+#define   S_028A4C_ZMM_LINE_EXTENT(x)                                 (((x) & 0x1) << 11)
+#define   G_028A4C_ZMM_LINE_EXTENT(x)                                 (((x) >> 11) & 0x1)
+#define   C_028A4C_ZMM_LINE_EXTENT                                    0xFFFFF7FF
+#define   S_028A4C_ZMM_LINE_OFFSET(x)                                 (((x) & 0x1) << 12)
+#define   G_028A4C_ZMM_LINE_OFFSET(x)                                 (((x) >> 12) & 0x1)
+#define   C_028A4C_ZMM_LINE_OFFSET                                    0xFFFFEFFF
+#define   S_028A4C_ZMM_RECT_EXTENT(x)                                 (((x) & 0x1) << 13)
+#define   G_028A4C_ZMM_RECT_EXTENT(x)                                 (((x) >> 13) & 0x1)
+#define   C_028A4C_ZMM_RECT_EXTENT                                    0xFFFFDFFF
+#define   S_028A4C_KILL_PIX_POST_HI_Z(x)                              (((x) & 0x1) << 14)
+#define   G_028A4C_KILL_PIX_POST_HI_Z(x)                              (((x) >> 14) & 0x1)
+#define   C_028A4C_KILL_PIX_POST_HI_Z                                 0xFFFFBFFF
+#define   S_028A4C_KILL_PIX_POST_DETAIL_MASK(x)                       (((x) & 0x1) << 15)
+#define   G_028A4C_KILL_PIX_POST_DETAIL_MASK(x)                       (((x) >> 15) & 0x1)
+#define   C_028A4C_KILL_PIX_POST_DETAIL_MASK                          0xFFFF7FFF
+#define   S_028A4C_PS_ITER_SAMPLE(x)                                  (((x) & 0x1) << 16)
+#define   G_028A4C_PS_ITER_SAMPLE(x)                                  (((x) >> 16) & 0x1)
+#define   C_028A4C_PS_ITER_SAMPLE                                     0xFFFEFFFF
+#define   S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISC(x)                   (((x) & 0x1) << 17)
+#define   G_028A4C_MULTI_SHADER_ENGINE_PRIM_DISC(x)                   (((x) >> 17) & 0x1)
+#define   C_028A4C_MULTI_SHADER_ENGINE_PRIM_DISC                      0xFFFDFFFF
+#define   S_028A4C_FORCE_EOV_CNTDWN_ENABLE(x)                         (((x) & 0x1) << 25)
+#define   G_028A4C_FORCE_EOV_CNTDWN_ENABLE(x)                         (((x) >> 25) & 0x1)
+#define   C_028A4C_FORCE_EOV_CNTDWN_ENABLE                            0xFDFFFFFF
+#define   S_028A4C_FORCE_EOV_REZ_ENABLE(x)                            (((x) & 0x1) << 26)
+#define   G_028A4C_FORCE_EOV_REZ_ENABLE(x)                            (((x) >> 26) & 0x1)
+#define   C_028A4C_FORCE_EOV_REZ_ENABLE                               0xFBFFFFFF
+#define   S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(x)                   (((x) & 0x1) << 27)
+#define   G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(x)                   (((x) >> 27) & 0x1)
+#define   C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE                      0xF7FFFFFF
+#define   S_028A4C_OUT_OF_ORDER_WATER_MARK(x)                         (((x) & 0x07) << 28)
+#define   G_028A4C_OUT_OF_ORDER_WATER_MARK(x)                         (((x) >> 28) & 0x07)
+#define   C_028A4C_OUT_OF_ORDER_WATER_MARK                            0x8FFFFFFF
+#define R_028A50_VGT_ENHANCE                                            0x028A50
+#define R_028A54_VGT_GS_PER_ES                                          0x028A54
+#define   S_028A54_GS_PER_ES(x)                                       (((x) & 0x7FF) << 0)
+#define   G_028A54_GS_PER_ES(x)                                       (((x) >> 0) & 0x7FF)
+#define   C_028A54_GS_PER_ES                                          0xFFFFF800
+#define R_028A58_VGT_ES_PER_GS                                          0x028A58
+#define   S_028A58_ES_PER_GS(x)                                       (((x) & 0x7FF) << 0)
+#define   G_028A58_ES_PER_GS(x)                                       (((x) >> 0) & 0x7FF)
+#define   C_028A58_ES_PER_GS                                          0xFFFFF800
+#define R_028A5C_VGT_GS_PER_VS                                          0x028A5C
+#define   S_028A5C_GS_PER_VS(x)                                       (((x) & 0x0F) << 0)
+#define   G_028A5C_GS_PER_VS(x)                                       (((x) >> 0) & 0x0F)
+#define   C_028A5C_GS_PER_VS                                          0xFFFFFFF0
+#define R_028A60_VGT_GSVS_RING_OFFSET_1                                 0x028A60
+#define   S_028A60_OFFSET(x)                                          (((x) & 0x7FFF) << 0)
+#define   G_028A60_OFFSET(x)                                          (((x) >> 0) & 0x7FFF)
+#define   C_028A60_OFFSET                                             0xFFFF8000
+#define R_028A64_VGT_GSVS_RING_OFFSET_2                                 0x028A64
+#define   S_028A64_OFFSET(x)                                          (((x) & 0x7FFF) << 0)
+#define   G_028A64_OFFSET(x)                                          (((x) >> 0) & 0x7FFF)
+#define   C_028A64_OFFSET                                             0xFFFF8000
+#define R_028A68_VGT_GSVS_RING_OFFSET_3                                 0x028A68
+#define   S_028A68_OFFSET(x)                                          (((x) & 0x7FFF) << 0)
+#define   G_028A68_OFFSET(x)                                          (((x) >> 0) & 0x7FFF)
+#define   C_028A68_OFFSET                                             0xFFFF8000
+#define R_028A6C_VGT_GS_OUT_PRIM_TYPE                                   0x028A6C
+#define   S_028A6C_OUTPRIM_TYPE(x)                                    (((x) & 0x3F) << 0)
+#define   G_028A6C_OUTPRIM_TYPE(x)                                    (((x) >> 0) & 0x3F)
+#define   C_028A6C_OUTPRIM_TYPE                                       0xFFFFFFC0
+#define   S_028A6C_OUTPRIM_TYPE_1(x)                                  (((x) & 0x3F) << 8)
+#define   G_028A6C_OUTPRIM_TYPE_1(x)                                  (((x) >> 8) & 0x3F)
+#define   C_028A6C_OUTPRIM_TYPE_1                                     0xFFFFC0FF
+#define   S_028A6C_OUTPRIM_TYPE_2(x)                                  (((x) & 0x3F) << 16)
+#define   G_028A6C_OUTPRIM_TYPE_2(x)                                  (((x) >> 16) & 0x3F)
+#define   C_028A6C_OUTPRIM_TYPE_2                                     0xFFC0FFFF
+#define   S_028A6C_OUTPRIM_TYPE_3(x)                                  (((x) & 0x3F) << 22)
+#define   G_028A6C_OUTPRIM_TYPE_3(x)                                  (((x) >> 22) & 0x3F)
+#define   C_028A6C_OUTPRIM_TYPE_3                                     0xF03FFFFF
+#define   S_028A6C_UNIQUE_TYPE_PER_STREAM(x)                          (((x) & 0x1) << 31)
+#define   G_028A6C_UNIQUE_TYPE_PER_STREAM(x)                          (((x) >> 31) & 0x1)
+#define   C_028A6C_UNIQUE_TYPE_PER_STREAM                             0x7FFFFFFF
+#define R_028A70_IA_ENHANCE                                             0x028A70
+#define R_028A74_VGT_DMA_SIZE                                           0x028A74
+#define R_028A78_VGT_DMA_MAX_SIZE                                       0x028A78
+#define R_028A7C_VGT_DMA_INDEX_TYPE                                     0x028A7C
+#define   S_028A7C_INDEX_TYPE(x)                                      (((x) & 0x03) << 0)
+#define   G_028A7C_INDEX_TYPE(x)                                      (((x) >> 0) & 0x03)
+#define   C_028A7C_INDEX_TYPE                                         0xFFFFFFFC
+#define     V_028A7C_VGT_INDEX_16                                   0x00
+#define     V_028A7C_VGT_INDEX_32                                   0x01
+#define   S_028A7C_SWAP_MODE(x)                                       (((x) & 0x03) << 2)
+#define   G_028A7C_SWAP_MODE(x)                                       (((x) >> 2) & 0x03)
+#define   C_028A7C_SWAP_MODE                                          0xFFFFFFF3
+#define     V_028A7C_VGT_DMA_SWAP_NONE                              0x00
+#define     V_028A7C_VGT_DMA_SWAP_16_BIT                            0x01
+#define     V_028A7C_VGT_DMA_SWAP_32_BIT                            0x02
+#define     V_028A7C_VGT_DMA_SWAP_WORD                              0x03
+/* CIK */
+#define   S_028A7C_BUF_TYPE(x)                                        (((x) & 0x03) << 4)
+#define   G_028A7C_BUF_TYPE(x)                                        (((x) >> 4) & 0x03)
+#define   C_028A7C_BUF_TYPE                                           0xFFFFFFCF
+#define     V_028A7C_VGT_DMA_BUF_MEM                                0x00
+#define     V_028A7C_VGT_DMA_BUF_RING                               0x01
+#define     V_028A7C_VGT_DMA_BUF_SETUP                              0x02
+#define   S_028A7C_RDREQ_POLICY(x)                                    (((x) & 0x03) << 6)
+#define   G_028A7C_RDREQ_POLICY(x)                                    (((x) >> 6) & 0x03)
+#define   C_028A7C_RDREQ_POLICY                                       0xFFFFFF3F
+#define     V_028A7C_VGT_POLICY_LRU                                 0x00
+#define     V_028A7C_VGT_POLICY_STREAM                              0x01
+#define   S_028A7C_ATC(x)                                             (((x) & 0x1) << 8)
+#define   G_028A7C_ATC(x)                                             (((x) >> 8) & 0x1)
+#define   C_028A7C_ATC                                                0xFFFFFEFF
+#define   S_028A7C_NOT_EOP(x)                                         (((x) & 0x1) << 9)
+#define   G_028A7C_NOT_EOP(x)                                         (((x) >> 9) & 0x1)
+#define   C_028A7C_NOT_EOP                                            0xFFFFFDFF
+#define   S_028A7C_REQ_PATH(x)                                        (((x) & 0x1) << 10)
+#define   G_028A7C_REQ_PATH(x)                                        (((x) >> 10) & 0x1)
+#define   C_028A7C_REQ_PATH                                           0xFFFFFBFF
+/*     */
+#define R_028A84_VGT_PRIMITIVEID_EN                                     0x028A84
+#define   S_028A84_PRIMITIVEID_EN(x)                                  (((x) & 0x1) << 0)
+#define   G_028A84_PRIMITIVEID_EN(x)                                  (((x) >> 0) & 0x1)
+#define   C_028A84_PRIMITIVEID_EN                                     0xFFFFFFFE
+#define   S_028A84_DISABLE_RESET_ON_EOI(x)                            (((x) & 0x1) << 1) /* not on CIK */
+#define   G_028A84_DISABLE_RESET_ON_EOI(x)                            (((x) >> 1) & 0x1) /* not on CIK */
+#define   C_028A84_DISABLE_RESET_ON_EOI                               0xFFFFFFFD /* not on CIK */
+#define R_028A88_VGT_DMA_NUM_INSTANCES                                  0x028A88
+#define R_028A8C_VGT_PRIMITIVEID_RESET                                  0x028A8C
+#define R_028A90_VGT_EVENT_INITIATOR                                    0x028A90
+#define   S_028A90_EVENT_TYPE(x)                                      (((x) & 0x3F) << 0)
+#define   G_028A90_EVENT_TYPE(x)                                      (((x) >> 0) & 0x3F)
+#define   C_028A90_EVENT_TYPE                                         0xFFFFFFC0
+#define     V_028A90_SAMPLE_STREAMOUTSTATS1                         0x01
+#define     V_028A90_SAMPLE_STREAMOUTSTATS2                         0x02
+#define     V_028A90_SAMPLE_STREAMOUTSTATS3                         0x03
+#define     V_028A90_CACHE_FLUSH_TS                                 0x04
+#define     V_028A90_CONTEXT_DONE                                   0x05
+#define     V_028A90_CACHE_FLUSH                                    0x06
+#define     V_028A90_CS_PARTIAL_FLUSH                               0x07
+#define     V_028A90_VGT_STREAMOUT_SYNC                             0x08
+#define     V_028A90_VGT_STREAMOUT_RESET                            0x0A
+#define     V_028A90_END_OF_PIPE_INCR_DE                            0x0B
+#define     V_028A90_END_OF_PIPE_IB_END                             0x0C
+#define     V_028A90_RST_PIX_CNT                                    0x0D
+#define     V_028A90_VS_PARTIAL_FLUSH                               0x0F
+#define     V_028A90_PS_PARTIAL_FLUSH                               0x10
+#define     V_028A90_FLUSH_HS_OUTPUT                                0x11
+#define     V_028A90_FLUSH_LS_OUTPUT                                0x12
+#define     V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT                   0x14
+#define     V_028A90_ZPASS_DONE                                     0x15 /* not on CIK */
+#define     V_028A90_CACHE_FLUSH_AND_INV_EVENT                      0x16
+#define     V_028A90_PERFCOUNTER_START                              0x17
+#define     V_028A90_PERFCOUNTER_STOP                               0x18
+#define     V_028A90_PIPELINESTAT_START                             0x19
+#define     V_028A90_PIPELINESTAT_STOP                              0x1A
+#define     V_028A90_PERFCOUNTER_SAMPLE                             0x1B
+#define     V_028A90_FLUSH_ES_OUTPUT                                0x1C
+#define     V_028A90_FLUSH_GS_OUTPUT                                0x1D
+#define     V_028A90_SAMPLE_PIPELINESTAT                            0x1E
+#define     V_028A90_SO_VGTSTREAMOUT_FLUSH                          0x1F
+#define     V_028A90_SAMPLE_STREAMOUTSTATS                          0x20
+#define     V_028A90_RESET_VTX_CNT                                  0x21
+#define     V_028A90_BLOCK_CONTEXT_DONE                             0x22
+#define     V_028A90_CS_CONTEXT_DONE                                0x23
+#define     V_028A90_VGT_FLUSH                                      0x24
+#define     V_028A90_SC_SEND_DB_VPZ                                 0x27
+#define     V_028A90_BOTTOM_OF_PIPE_TS                              0x28
+#define     V_028A90_DB_CACHE_FLUSH_AND_INV                         0x2A
+#define     V_028A90_FLUSH_AND_INV_DB_DATA_TS                       0x2B
+#define     V_028A90_FLUSH_AND_INV_DB_META                          0x2C
+#define     V_028A90_FLUSH_AND_INV_CB_DATA_TS                       0x2D
+#define     V_028A90_FLUSH_AND_INV_CB_META                          0x2E
+#define     V_028A90_CS_DONE                                        0x2F
+#define     V_028A90_PS_DONE                                        0x30
+#define     V_028A90_FLUSH_AND_INV_CB_PIXEL_DATA                    0x31
+#define     V_028A90_THREAD_TRACE_START                             0x33
+#define     V_028A90_THREAD_TRACE_STOP                              0x34
+#define     V_028A90_THREAD_TRACE_MARKER                            0x35
+#define     V_028A90_THREAD_TRACE_FLUSH                             0x36
+#define     V_028A90_THREAD_TRACE_FINISH                            0x37
+/* CIK */
+#define     V_028A90_PIXEL_PIPE_STAT_CONTROL                        0x38
+#define     V_028A90_PIXEL_PIPE_STAT_DUMP                           0x39
+#define     V_028A90_PIXEL_PIPE_STAT_RESET                          0x40
+/*     */
+#define   S_028A90_ADDRESS_HI(x)                                      (((x) & 0x1FF) << 18)
+#define   G_028A90_ADDRESS_HI(x)                                      (((x) >> 18) & 0x1FF)
+#define   C_028A90_ADDRESS_HI                                         0xF803FFFF
+#define   S_028A90_EXTENDED_EVENT(x)                                  (((x) & 0x1) << 27)
+#define   G_028A90_EXTENDED_EVENT(x)                                  (((x) >> 27) & 0x1)
+#define   C_028A90_EXTENDED_EVENT                                     0xF7FFFFFF
+#define R_028A94_VGT_MULTI_PRIM_IB_RESET_EN                             0x028A94
+#define   S_028A94_RESET_EN(x)                                        (((x) & 0x1) << 0)
+#define   G_028A94_RESET_EN(x)                                        (((x) >> 0) & 0x1)
+#define   C_028A94_RESET_EN                                           0xFFFFFFFE
+#define R_028AA0_VGT_INSTANCE_STEP_RATE_0                               0x028AA0
+#define R_028AA4_VGT_INSTANCE_STEP_RATE_1                               0x028AA4
+#define R_028AA8_IA_MULTI_VGT_PARAM                                     0x028AA8
+#define   S_028AA8_PRIMGROUP_SIZE(x)                                  (((x) & 0xFFFF) << 0)
+#define   G_028AA8_PRIMGROUP_SIZE(x)                                  (((x) >> 0) & 0xFFFF)
+#define   C_028AA8_PRIMGROUP_SIZE                                     0xFFFF0000
+#define   S_028AA8_PARTIAL_VS_WAVE_ON(x)                              (((x) & 0x1) << 16)
+#define   G_028AA8_PARTIAL_VS_WAVE_ON(x)                              (((x) >> 16) & 0x1)
+#define   C_028AA8_PARTIAL_VS_WAVE_ON                                 0xFFFEFFFF
+#define   S_028AA8_SWITCH_ON_EOP(x)                                   (((x) & 0x1) << 17)
+#define   G_028AA8_SWITCH_ON_EOP(x)                                   (((x) >> 17) & 0x1)
+#define   C_028AA8_SWITCH_ON_EOP                                      0xFFFDFFFF
+#define   S_028AA8_PARTIAL_ES_WAVE_ON(x)                              (((x) & 0x1) << 18)
+#define   G_028AA8_PARTIAL_ES_WAVE_ON(x)                              (((x) >> 18) & 0x1)
+#define   C_028AA8_PARTIAL_ES_WAVE_ON                                 0xFFFBFFFF
+#define   S_028AA8_SWITCH_ON_EOI(x)                                   (((x) & 0x1) << 19)
+#define   G_028AA8_SWITCH_ON_EOI(x)                                   (((x) >> 19) & 0x1)
+#define   C_028AA8_SWITCH_ON_EOI                                      0xFFF7FFFF
+/* CIK */
+#define   S_028AA8_WD_SWITCH_ON_EOP(x)                                (((x) & 0x1) << 20)
+#define   G_028AA8_WD_SWITCH_ON_EOP(x)                                (((x) >> 20) & 0x1)
+#define   C_028AA8_WD_SWITCH_ON_EOP                                   0xFFEFFFFF
+/*     */
+#define R_028AAC_VGT_ESGS_RING_ITEMSIZE                                 0x028AAC
+#define   S_028AAC_ITEMSIZE(x)                                        (((x) & 0x7FFF) << 0)
+#define   G_028AAC_ITEMSIZE(x)                                        (((x) >> 0) & 0x7FFF)
+#define   C_028AAC_ITEMSIZE                                           0xFFFF8000
+#define R_028AB0_VGT_GSVS_RING_ITEMSIZE                                 0x028AB0
+#define   S_028AB0_ITEMSIZE(x)                                        (((x) & 0x7FFF) << 0)
+#define   G_028AB0_ITEMSIZE(x)                                        (((x) >> 0) & 0x7FFF)
+#define   C_028AB0_ITEMSIZE                                           0xFFFF8000
+#define R_028AB4_VGT_REUSE_OFF                                          0x028AB4
+#define   S_028AB4_REUSE_OFF(x)                                       (((x) & 0x1) << 0)
+#define   G_028AB4_REUSE_OFF(x)                                       (((x) >> 0) & 0x1)
+#define   C_028AB4_REUSE_OFF                                          0xFFFFFFFE
+#define R_028AB8_VGT_VTX_CNT_EN                                         0x028AB8
+#define   S_028AB8_VTX_CNT_EN(x)                                      (((x) & 0x1) << 0)
+#define   G_028AB8_VTX_CNT_EN(x)                                      (((x) >> 0) & 0x1)
+#define   C_028AB8_VTX_CNT_EN                                         0xFFFFFFFE
+#define R_028ABC_DB_HTILE_SURFACE                                       0x028ABC
+#define   S_028ABC_LINEAR(x)                                          (((x) & 0x1) << 0)
+#define   G_028ABC_LINEAR(x)                                          (((x) >> 0) & 0x1)
+#define   C_028ABC_LINEAR                                             0xFFFFFFFE
+#define   S_028ABC_FULL_CACHE(x)                                      (((x) & 0x1) << 1)
+#define   G_028ABC_FULL_CACHE(x)                                      (((x) >> 1) & 0x1)
+#define   C_028ABC_FULL_CACHE                                         0xFFFFFFFD
+#define   S_028ABC_HTILE_USES_PRELOAD_WIN(x)                          (((x) & 0x1) << 2)
+#define   G_028ABC_HTILE_USES_PRELOAD_WIN(x)                          (((x) >> 2) & 0x1)
+#define   C_028ABC_HTILE_USES_PRELOAD_WIN                             0xFFFFFFFB
+#define   S_028ABC_PRELOAD(x)                                         (((x) & 0x1) << 3)
+#define   G_028ABC_PRELOAD(x)                                         (((x) >> 3) & 0x1)
+#define   C_028ABC_PRELOAD                                            0xFFFFFFF7
+#define   S_028ABC_PREFETCH_WIDTH(x)                                  (((x) & 0x3F) << 4)
+#define   G_028ABC_PREFETCH_WIDTH(x)                                  (((x) >> 4) & 0x3F)
+#define   C_028ABC_PREFETCH_WIDTH                                     0xFFFFFC0F
+#define   S_028ABC_PREFETCH_HEIGHT(x)                                 (((x) & 0x3F) << 10)
+#define   G_028ABC_PREFETCH_HEIGHT(x)                                 (((x) >> 10) & 0x3F)
+#define   C_028ABC_PREFETCH_HEIGHT                                    0xFFFF03FF
+#define   S_028ABC_DST_OUTSIDE_ZERO_TO_ONE(x)                         (((x) & 0x1) << 16)
+#define   G_028ABC_DST_OUTSIDE_ZERO_TO_ONE(x)                         (((x) >> 16) & 0x1)
+#define   C_028ABC_DST_OUTSIDE_ZERO_TO_ONE                            0xFFFEFFFF
+#define R_028AC0_DB_SRESULTS_COMPARE_STATE0                             0x028AC0
+#define   S_028AC0_COMPAREFUNC0(x)                                    (((x) & 0x07) << 0)
+#define   G_028AC0_COMPAREFUNC0(x)                                    (((x) >> 0) & 0x07)
+#define   C_028AC0_COMPAREFUNC0                                       0xFFFFFFF8
+#define     V_028AC0_REF_NEVER                                      0x00
+#define     V_028AC0_REF_LESS                                       0x01
+#define     V_028AC0_REF_EQUAL                                      0x02
+#define     V_028AC0_REF_LEQUAL                                     0x03
+#define     V_028AC0_REF_GREATER                                    0x04
+#define     V_028AC0_REF_NOTEQUAL                                   0x05
+#define     V_028AC0_REF_GEQUAL                                     0x06
+#define     V_028AC0_REF_ALWAYS                                     0x07
+#define   S_028AC0_COMPAREVALUE0(x)                                   (((x) & 0xFF) << 4)
+#define   G_028AC0_COMPAREVALUE0(x)                                   (((x) >> 4) & 0xFF)
+#define   C_028AC0_COMPAREVALUE0                                      0xFFFFF00F
+#define   S_028AC0_COMPAREMASK0(x)                                    (((x) & 0xFF) << 12)
+#define   G_028AC0_COMPAREMASK0(x)                                    (((x) >> 12) & 0xFF)
+#define   C_028AC0_COMPAREMASK0                                       0xFFF00FFF
+#define   S_028AC0_ENABLE0(x)                                         (((x) & 0x1) << 24)
+#define   G_028AC0_ENABLE0(x)                                         (((x) >> 24) & 0x1)
+#define   C_028AC0_ENABLE0                                            0xFEFFFFFF
+#define R_028AC4_DB_SRESULTS_COMPARE_STATE1                             0x028AC4
+#define   S_028AC4_COMPAREFUNC1(x)                                    (((x) & 0x07) << 0)
+#define   G_028AC4_COMPAREFUNC1(x)                                    (((x) >> 0) & 0x07)
+#define   C_028AC4_COMPAREFUNC1                                       0xFFFFFFF8
+#define     V_028AC4_REF_NEVER                                      0x00
+#define     V_028AC4_REF_LESS                                       0x01
+#define     V_028AC4_REF_EQUAL                                      0x02
+#define     V_028AC4_REF_LEQUAL                                     0x03
+#define     V_028AC4_REF_GREATER                                    0x04
+#define     V_028AC4_REF_NOTEQUAL                                   0x05
+#define     V_028AC4_REF_GEQUAL                                     0x06
+#define     V_028AC4_REF_ALWAYS                                     0x07
+#define   S_028AC4_COMPAREVALUE1(x)                                   (((x) & 0xFF) << 4)
+#define   G_028AC4_COMPAREVALUE1(x)                                   (((x) >> 4) & 0xFF)
+#define   C_028AC4_COMPAREVALUE1                                      0xFFFFF00F
+#define   S_028AC4_COMPAREMASK1(x)                                    (((x) & 0xFF) << 12)
+#define   G_028AC4_COMPAREMASK1(x)                                    (((x) >> 12) & 0xFF)
+#define   C_028AC4_COMPAREMASK1                                       0xFFF00FFF
+#define   S_028AC4_ENABLE1(x)                                         (((x) & 0x1) << 24)
+#define   G_028AC4_ENABLE1(x)                                         (((x) >> 24) & 0x1)
+#define   C_028AC4_ENABLE1                                            0xFEFFFFFF
+#define R_028AC8_DB_PRELOAD_CONTROL                                     0x028AC8
+#define   S_028AC8_START_X(x)                                         (((x) & 0xFF) << 0)
+#define   G_028AC8_START_X(x)                                         (((x) >> 0) & 0xFF)
+#define   C_028AC8_START_X                                            0xFFFFFF00
+#define   S_028AC8_START_Y(x)                                         (((x) & 0xFF) << 8)
+#define   G_028AC8_START_Y(x)                                         (((x) >> 8) & 0xFF)
+#define   C_028AC8_START_Y                                            0xFFFF00FF
+#define   S_028AC8_MAX_X(x)                                           (((x) & 0xFF) << 16)
+#define   G_028AC8_MAX_X(x)                                           (((x) >> 16) & 0xFF)
+#define   C_028AC8_MAX_X                                              0xFF00FFFF
+#define   S_028AC8_MAX_Y(x)                                           (((x) & 0xFF) << 24)
+#define   G_028AC8_MAX_Y(x)                                           (((x) >> 24) & 0xFF)
+#define   C_028AC8_MAX_Y                                              0x00FFFFFF
+#define R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0                              0x028AD0
+#define R_028AD4_VGT_STRMOUT_VTX_STRIDE_0                               0x028AD4
+#define   S_028AD4_STRIDE(x)                                          (((x) & 0x3FF) << 0)
+#define   G_028AD4_STRIDE(x)                                          (((x) >> 0) & 0x3FF)
+#define   C_028AD4_STRIDE                                             0xFFFFFC00
+#define R_028ADC_VGT_STRMOUT_BUFFER_OFFSET_0                            0x028ADC
+#define R_028AE0_VGT_STRMOUT_BUFFER_SIZE_1                              0x028AE0
+#define R_028AE4_VGT_STRMOUT_VTX_STRIDE_1                               0x028AE4
+#define   S_028AE4_STRIDE(x)                                          (((x) & 0x3FF) << 0)
+#define   G_028AE4_STRIDE(x)                                          (((x) >> 0) & 0x3FF)
+#define   C_028AE4_STRIDE                                             0xFFFFFC00
+#define R_028AEC_VGT_STRMOUT_BUFFER_OFFSET_1                            0x028AEC
+#define R_028AF0_VGT_STRMOUT_BUFFER_SIZE_2                              0x028AF0
+#define R_028AF4_VGT_STRMOUT_VTX_STRIDE_2                               0x028AF4
+#define   S_028AF4_STRIDE(x)                                          (((x) & 0x3FF) << 0)
+#define   G_028AF4_STRIDE(x)                                          (((x) >> 0) & 0x3FF)
+#define   C_028AF4_STRIDE                                             0xFFFFFC00
+#define R_028AFC_VGT_STRMOUT_BUFFER_OFFSET_2                            0x028AFC
+#define R_028B00_VGT_STRMOUT_BUFFER_SIZE_3                              0x028B00
+#define R_028B04_VGT_STRMOUT_VTX_STRIDE_3                               0x028B04
+#define   S_028B04_STRIDE(x)                                          (((x) & 0x3FF) << 0)
+#define   G_028B04_STRIDE(x)                                          (((x) >> 0) & 0x3FF)
+#define   C_028B04_STRIDE                                             0xFFFFFC00
+#define R_028B0C_VGT_STRMOUT_BUFFER_OFFSET_3                            0x028B0C
+#define R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET                         0x028B28
+#define R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE             0x028B2C
+#define R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE                  0x028B30
+#define   S_028B30_VERTEX_STRIDE(x)                                   (((x) & 0x1FF) << 0)
+#define   G_028B30_VERTEX_STRIDE(x)                                   (((x) >> 0) & 0x1FF)
+#define   C_028B30_VERTEX_STRIDE                                      0xFFFFFE00
+#define R_028B38_VGT_GS_MAX_VERT_OUT                                    0x028B38
+#define   S_028B38_MAX_VERT_OUT(x)                                    (((x) & 0x7FF) << 0)
+#define   G_028B38_MAX_VERT_OUT(x)                                    (((x) >> 0) & 0x7FF)
+#define   C_028B38_MAX_VERT_OUT                                       0xFFFFF800
+#define R_028B54_VGT_SHADER_STAGES_EN                                   0x028B54
+#define   S_028B54_LS_EN(x)                                           (((x) & 0x03) << 0)
+#define   G_028B54_LS_EN(x)                                           (((x) >> 0) & 0x03)
+#define   C_028B54_LS_EN                                              0xFFFFFFFC
+#define     V_028B54_LS_STAGE_OFF                                   0x00
+#define     V_028B54_LS_STAGE_ON                                    0x01
+#define     V_028B54_CS_STAGE_ON                                    0x02
+#define   S_028B54_HS_EN(x)                                           (((x) & 0x1) << 2)
+#define   G_028B54_HS_EN(x)                                           (((x) >> 2) & 0x1)
+#define   C_028B54_HS_EN                                              0xFFFFFFFB
+#define   S_028B54_ES_EN(x)                                           (((x) & 0x03) << 3)
+#define   G_028B54_ES_EN(x)                                           (((x) >> 3) & 0x03)
+#define   C_028B54_ES_EN                                              0xFFFFFFE7
+#define     V_028B54_ES_STAGE_OFF                                   0x00
+#define     V_028B54_ES_STAGE_DS                                    0x01
+#define     V_028B54_ES_STAGE_REAL                                  0x02
+#define   S_028B54_GS_EN(x)                                           (((x) & 0x1) << 5)
+#define   G_028B54_GS_EN(x)                                           (((x) >> 5) & 0x1)
+#define   C_028B54_GS_EN                                              0xFFFFFFDF
+#define   S_028B54_VS_EN(x)                                           (((x) & 0x03) << 6)
+#define   G_028B54_VS_EN(x)                                           (((x) >> 6) & 0x03)
+#define   C_028B54_VS_EN                                              0xFFFFFF3F
+#define     V_028B54_VS_STAGE_REAL                                  0x00
+#define     V_028B54_VS_STAGE_DS                                    0x01
+#define     V_028B54_VS_STAGE_COPY_SHADER                           0x02
+#define   S_028B54_DYNAMIC_HS(x)                                      (((x) & 0x1) << 8)
+#define   G_028B54_DYNAMIC_HS(x)                                      (((x) >> 8) & 0x1)
+#define   C_028B54_DYNAMIC_HS                                         0xFFFFFEFF
+#define R_028B58_VGT_LS_HS_CONFIG                                       0x028B58
+#define   S_028B58_NUM_PATCHES(x)                                     (((x) & 0xFF) << 0)
+#define   G_028B58_NUM_PATCHES(x)                                     (((x) >> 0) & 0xFF)
+#define   C_028B58_NUM_PATCHES                                        0xFFFFFF00
+#define   S_028B58_HS_NUM_INPUT_CP(x)                                 (((x) & 0x3F) << 8)
+#define   G_028B58_HS_NUM_INPUT_CP(x)                                 (((x) >> 8) & 0x3F)
+#define   C_028B58_HS_NUM_INPUT_CP                                    0xFFFFC0FF
+#define   S_028B58_HS_NUM_OUTPUT_CP(x)                                (((x) & 0x3F) << 14)
+#define   G_028B58_HS_NUM_OUTPUT_CP(x)                                (((x) >> 14) & 0x3F)
+#define   C_028B58_HS_NUM_OUTPUT_CP                                   0xFFF03FFF
+#define R_028B5C_VGT_GS_VERT_ITEMSIZE                                   0x028B5C
+#define   S_028B5C_ITEMSIZE(x)                                        (((x) & 0x7FFF) << 0)
+#define   G_028B5C_ITEMSIZE(x)                                        (((x) >> 0) & 0x7FFF)
+#define   C_028B5C_ITEMSIZE                                           0xFFFF8000
+#define R_028B60_VGT_GS_VERT_ITEMSIZE_1                                 0x028B60
+#define   S_028B60_ITEMSIZE(x)                                        (((x) & 0x7FFF) << 0)
+#define   G_028B60_ITEMSIZE(x)                                        (((x) >> 0) & 0x7FFF)
+#define   C_028B60_ITEMSIZE                                           0xFFFF8000
+#define R_028B64_VGT_GS_VERT_ITEMSIZE_2                                 0x028B64
+#define   S_028B64_ITEMSIZE(x)                                        (((x) & 0x7FFF) << 0)
+#define   G_028B64_ITEMSIZE(x)                                        (((x) >> 0) & 0x7FFF)
+#define   C_028B64_ITEMSIZE                                           0xFFFF8000
+#define R_028B68_VGT_GS_VERT_ITEMSIZE_3                                 0x028B68
+#define   S_028B68_ITEMSIZE(x)                                        (((x) & 0x7FFF) << 0)
+#define   G_028B68_ITEMSIZE(x)                                        (((x) >> 0) & 0x7FFF)
+#define   C_028B68_ITEMSIZE                                           0xFFFF8000
+#define R_028B6C_VGT_TF_PARAM                                           0x028B6C
+#define   S_028B6C_TYPE(x)                                            (((x) & 0x03) << 0)
+#define   G_028B6C_TYPE(x)                                            (((x) >> 0) & 0x03)
+#define   C_028B6C_TYPE                                               0xFFFFFFFC
+#define     V_028B6C_TESS_ISOLINE                                   0x00
+#define     V_028B6C_TESS_TRIANGLE                                  0x01
+#define     V_028B6C_TESS_QUAD                                      0x02
+#define   S_028B6C_PARTITIONING(x)                                    (((x) & 0x07) << 2)
+#define   G_028B6C_PARTITIONING(x)                                    (((x) >> 2) & 0x07)
+#define   C_028B6C_PARTITIONING                                       0xFFFFFFE3
+#define     V_028B6C_PART_INTEGER                                   0x00
+#define     V_028B6C_PART_POW2                                      0x01
+#define     V_028B6C_PART_FRAC_ODD                                  0x02
+#define     V_028B6C_PART_FRAC_EVEN                                 0x03
+#define   S_028B6C_TOPOLOGY(x)                                        (((x) & 0x07) << 5)
+#define   G_028B6C_TOPOLOGY(x)                                        (((x) >> 5) & 0x07)
+#define   C_028B6C_TOPOLOGY                                           0xFFFFFF1F
+#define     V_028B6C_OUTPUT_POINT                                   0x00
+#define     V_028B6C_OUTPUT_LINE                                    0x01
+#define     V_028B6C_OUTPUT_TRIANGLE_CW                             0x02
+#define     V_028B6C_OUTPUT_TRIANGLE_CCW                            0x03
+#define   S_028B6C_RESERVED_REDUC_AXIS(x)                             (((x) & 0x1) << 8) /* not on CIK */
+#define   G_028B6C_RESERVED_REDUC_AXIS(x)                             (((x) >> 8) & 0x1) /* not on CIK */
+#define   C_028B6C_RESERVED_REDUC_AXIS                                0xFFFFFEFF /* not on CIK */
+#define   S_028B6C_NUM_DS_WAVES_PER_SIMD(x)                           (((x) & 0x0F) << 10)
+#define   G_028B6C_NUM_DS_WAVES_PER_SIMD(x)                           (((x) >> 10) & 0x0F)
+#define   C_028B6C_NUM_DS_WAVES_PER_SIMD                              0xFFFFC3FF
+#define   S_028B6C_DISABLE_DONUTS(x)                                  (((x) & 0x1) << 14)
+#define   G_028B6C_DISABLE_DONUTS(x)                                  (((x) >> 14) & 0x1)
+#define   C_028B6C_DISABLE_DONUTS                                     0xFFFFBFFF
+/* CIK */
+#define   S_028B6C_RDREQ_POLICY(x)                                    (((x) & 0x03) << 15)
+#define   G_028B6C_RDREQ_POLICY(x)                                    (((x) >> 15) & 0x03)
+#define   C_028B6C_RDREQ_POLICY                                       0xFFFE7FFF
+#define     V_028B6C_VGT_POLICY_LRU                                 0x00
+#define     V_028B6C_VGT_POLICY_STREAM                              0x01
+#define     V_028B6C_VGT_POLICY_BYPASS                              0x02
+/*     */
+#define R_028B70_DB_ALPHA_TO_MASK                                       0x028B70
+#define   S_028B70_ALPHA_TO_MASK_ENABLE(x)                            (((x) & 0x1) << 0)
+#define   G_028B70_ALPHA_TO_MASK_ENABLE(x)                            (((x) >> 0) & 0x1)
+#define   C_028B70_ALPHA_TO_MASK_ENABLE                               0xFFFFFFFE
+#define   S_028B70_ALPHA_TO_MASK_OFFSET0(x)                           (((x) & 0x03) << 8)
+#define   G_028B70_ALPHA_TO_MASK_OFFSET0(x)                           (((x) >> 8) & 0x03)
+#define   C_028B70_ALPHA_TO_MASK_OFFSET0                              0xFFFFFCFF
+#define   S_028B70_ALPHA_TO_MASK_OFFSET1(x)                           (((x) & 0x03) << 10)
+#define   G_028B70_ALPHA_TO_MASK_OFFSET1(x)                           (((x) >> 10) & 0x03)
+#define   C_028B70_ALPHA_TO_MASK_OFFSET1                              0xFFFFF3FF
+#define   S_028B70_ALPHA_TO_MASK_OFFSET2(x)                           (((x) & 0x03) << 12)
+#define   G_028B70_ALPHA_TO_MASK_OFFSET2(x)                           (((x) >> 12) & 0x03)
+#define   C_028B70_ALPHA_TO_MASK_OFFSET2                              0xFFFFCFFF
+#define   S_028B70_ALPHA_TO_MASK_OFFSET3(x)                           (((x) & 0x03) << 14)
+#define   G_028B70_ALPHA_TO_MASK_OFFSET3(x)                           (((x) >> 14) & 0x03)
+#define   C_028B70_ALPHA_TO_MASK_OFFSET3                              0xFFFF3FFF
+#define   S_028B70_OFFSET_ROUND(x)                                    (((x) & 0x1) << 16)
+#define   G_028B70_OFFSET_ROUND(x)                                    (((x) >> 16) & 0x1)
+#define   C_028B70_OFFSET_ROUND                                       0xFFFEFFFF
+/* CIK */
+#define R_028B74_VGT_DISPATCH_DRAW_INDEX                                0x028B74
+/*     */
+#define R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL                          0x028B78
+#define   S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(x)                     (((x) & 0xFF) << 0)
+#define   G_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(x)                     (((x) >> 0) & 0xFF)
+#define   C_028B78_POLY_OFFSET_NEG_NUM_DB_BITS                        0xFFFFFF00
+#define   S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(x)                     (((x) & 0x1) << 8)
+#define   G_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(x)                     (((x) >> 8) & 0x1)
+#define   C_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT                        0xFFFFFEFF
+#define R_028B7C_PA_SU_POLY_OFFSET_CLAMP                                0x028B7C
+#define R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE                          0x028B80
+#define R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET                         0x028B84
+#define R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE                           0x028B88
+#define R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET                          0x028B8C
+#define R_028B90_VGT_GS_INSTANCE_CNT                                    0x028B90
+#define   S_028B90_ENABLE(x)                                          (((x) & 0x1) << 0)
+#define   G_028B90_ENABLE(x)                                          (((x) >> 0) & 0x1)
+#define   C_028B90_ENABLE                                             0xFFFFFFFE
+#define   S_028B90_CNT(x)                                             (((x) & 0x7F) << 2)
+#define   G_028B90_CNT(x)                                             (((x) >> 2) & 0x7F)
+#define   C_028B90_CNT                                                0xFFFFFE03
+#define R_028B94_VGT_STRMOUT_CONFIG                                     0x028B94
+#define   S_028B94_STREAMOUT_0_EN(x)                                  (((x) & 0x1) << 0)
+#define   G_028B94_STREAMOUT_0_EN(x)                                  (((x) >> 0) & 0x1)
+#define   C_028B94_STREAMOUT_0_EN                                     0xFFFFFFFE
+#define   S_028B94_STREAMOUT_1_EN(x)                                  (((x) & 0x1) << 1)
+#define   G_028B94_STREAMOUT_1_EN(x)                                  (((x) >> 1) & 0x1)
+#define   C_028B94_STREAMOUT_1_EN                                     0xFFFFFFFD
+#define   S_028B94_STREAMOUT_2_EN(x)                                  (((x) & 0x1) << 2)
+#define   G_028B94_STREAMOUT_2_EN(x)                                  (((x) >> 2) & 0x1)
+#define   C_028B94_STREAMOUT_2_EN                                     0xFFFFFFFB
+#define   S_028B94_STREAMOUT_3_EN(x)                                  (((x) & 0x1) << 3)
+#define   G_028B94_STREAMOUT_3_EN(x)                                  (((x) >> 3) & 0x1)
+#define   C_028B94_STREAMOUT_3_EN                                     0xFFFFFFF7
+#define   S_028B94_RAST_STREAM(x)                                     (((x) & 0x07) << 4)
+#define   G_028B94_RAST_STREAM(x)                                     (((x) >> 4) & 0x07)
+#define   C_028B94_RAST_STREAM                                        0xFFFFFF8F
+#define   S_028B94_RAST_STREAM_MASK(x)                                (((x) & 0x0F) << 8)
+#define   G_028B94_RAST_STREAM_MASK(x)                                (((x) >> 8) & 0x0F)
+#define   C_028B94_RAST_STREAM_MASK                                   0xFFFFF0FF
+#define   S_028B94_USE_RAST_STREAM_MASK(x)                            (((x) & 0x1) << 31)
+#define   G_028B94_USE_RAST_STREAM_MASK(x)                            (((x) >> 31) & 0x1)
+#define   C_028B94_USE_RAST_STREAM_MASK                               0x7FFFFFFF
+#define R_028B98_VGT_STRMOUT_BUFFER_CONFIG                              0x028B98
+#define   S_028B98_STREAM_0_BUFFER_EN(x)                              (((x) & 0x0F) << 0)
+#define   G_028B98_STREAM_0_BUFFER_EN(x)                              (((x) >> 0) & 0x0F)
+#define   C_028B98_STREAM_0_BUFFER_EN                                 0xFFFFFFF0
+#define   S_028B98_STREAM_1_BUFFER_EN(x)                              (((x) & 0x0F) << 4)
+#define   G_028B98_STREAM_1_BUFFER_EN(x)                              (((x) >> 4) & 0x0F)
+#define   C_028B98_STREAM_1_BUFFER_EN                                 0xFFFFFF0F
+#define   S_028B98_STREAM_2_BUFFER_EN(x)                              (((x) & 0x0F) << 8)
+#define   G_028B98_STREAM_2_BUFFER_EN(x)                              (((x) >> 8) & 0x0F)
+#define   C_028B98_STREAM_2_BUFFER_EN                                 0xFFFFF0FF
+#define   S_028B98_STREAM_3_BUFFER_EN(x)                              (((x) & 0x0F) << 12)
+#define   G_028B98_STREAM_3_BUFFER_EN(x)                              (((x) >> 12) & 0x0F)
+#define   C_028B98_STREAM_3_BUFFER_EN                                 0xFFFF0FFF
+#define R_028BD4_PA_SC_CENTROID_PRIORITY_0                              0x028BD4
+#define   S_028BD4_DISTANCE_0(x)                                      (((x) & 0x0F) << 0)
+#define   G_028BD4_DISTANCE_0(x)                                      (((x) >> 0) & 0x0F)
+#define   C_028BD4_DISTANCE_0                                         0xFFFFFFF0
+#define   S_028BD4_DISTANCE_1(x)                                      (((x) & 0x0F) << 4)
+#define   G_028BD4_DISTANCE_1(x)                                      (((x) >> 4) & 0x0F)
+#define   C_028BD4_DISTANCE_1                                         0xFFFFFF0F
+#define   S_028BD4_DISTANCE_2(x)                                      (((x) & 0x0F) << 8)
+#define   G_028BD4_DISTANCE_2(x)                                      (((x) >> 8) & 0x0F)
+#define   C_028BD4_DISTANCE_2                                         0xFFFFF0FF
+#define   S_028BD4_DISTANCE_3(x)                                      (((x) & 0x0F) << 12)
+#define   G_028BD4_DISTANCE_3(x)                                      (((x) >> 12) & 0x0F)
+#define   C_028BD4_DISTANCE_3                                         0xFFFF0FFF
+#define   S_028BD4_DISTANCE_4(x)                                      (((x) & 0x0F) << 16)
+#define   G_028BD4_DISTANCE_4(x)                                      (((x) >> 16) & 0x0F)
+#define   C_028BD4_DISTANCE_4                                         0xFFF0FFFF
+#define   S_028BD4_DISTANCE_5(x)                                      (((x) & 0x0F) << 20)
+#define   G_028BD4_DISTANCE_5(x)                                      (((x) >> 20) & 0x0F)
+#define   C_028BD4_DISTANCE_5                                         0xFF0FFFFF
+#define   S_028BD4_DISTANCE_6(x)                                      (((x) & 0x0F) << 24)
+#define   G_028BD4_DISTANCE_6(x)                                      (((x) >> 24) & 0x0F)
+#define   C_028BD4_DISTANCE_6                                         0xF0FFFFFF
+#define   S_028BD4_DISTANCE_7(x)                                      (((x) & 0x0F) << 28)
+#define   G_028BD4_DISTANCE_7(x)                                      (((x) >> 28) & 0x0F)
+#define   C_028BD4_DISTANCE_7                                         0x0FFFFFFF
+#define R_028BD8_PA_SC_CENTROID_PRIORITY_1                              0x028BD8
+#define   S_028BD8_DISTANCE_8(x)                                      (((x) & 0x0F) << 0)
+#define   G_028BD8_DISTANCE_8(x)                                      (((x) >> 0) & 0x0F)
+#define   C_028BD8_DISTANCE_8                                         0xFFFFFFF0
+#define   S_028BD8_DISTANCE_9(x)                                      (((x) & 0x0F) << 4)
+#define   G_028BD8_DISTANCE_9(x)                                      (((x) >> 4) & 0x0F)
+#define   C_028BD8_DISTANCE_9                                         0xFFFFFF0F
+#define   S_028BD8_DISTANCE_10(x)                                     (((x) & 0x0F) << 8)
+#define   G_028BD8_DISTANCE_10(x)                                     (((x) >> 8) & 0x0F)
+#define   C_028BD8_DISTANCE_10                                        0xFFFFF0FF
+#define   S_028BD8_DISTANCE_11(x)                                     (((x) & 0x0F) << 12)
+#define   G_028BD8_DISTANCE_11(x)                                     (((x) >> 12) & 0x0F)
+#define   C_028BD8_DISTANCE_11                                        0xFFFF0FFF
+#define   S_028BD8_DISTANCE_12(x)                                     (((x) & 0x0F) << 16)
+#define   G_028BD8_DISTANCE_12(x)                                     (((x) >> 16) & 0x0F)
+#define   C_028BD8_DISTANCE_12                                        0xFFF0FFFF
+#define   S_028BD8_DISTANCE_13(x)                                     (((x) & 0x0F) << 20)
+#define   G_028BD8_DISTANCE_13(x)                                     (((x) >> 20) & 0x0F)
+#define   C_028BD8_DISTANCE_13                                        0xFF0FFFFF
+#define   S_028BD8_DISTANCE_14(x)                                     (((x) & 0x0F) << 24)
+#define   G_028BD8_DISTANCE_14(x)                                     (((x) >> 24) & 0x0F)
+#define   C_028BD8_DISTANCE_14                                        0xF0FFFFFF
+#define   S_028BD8_DISTANCE_15(x)                                     (((x) & 0x0F) << 28)
+#define   G_028BD8_DISTANCE_15(x)                                     (((x) >> 28) & 0x0F)
+#define   C_028BD8_DISTANCE_15                                        0x0FFFFFFF
+#define R_028BDC_PA_SC_LINE_CNTL                                        0x028BDC
+#define   S_028BDC_EXPAND_LINE_WIDTH(x)                               (((x) & 0x1) << 9)
+#define   G_028BDC_EXPAND_LINE_WIDTH(x)                               (((x) >> 9) & 0x1)
+#define   C_028BDC_EXPAND_LINE_WIDTH                                  0xFFFFFDFF
+#define   S_028BDC_LAST_PIXEL(x)                                      (((x) & 0x1) << 10)
+#define   G_028BDC_LAST_PIXEL(x)                                      (((x) >> 10) & 0x1)
+#define   C_028BDC_LAST_PIXEL                                         0xFFFFFBFF
+#define   S_028BDC_PERPENDICULAR_ENDCAP_ENA(x)                        (((x) & 0x1) << 11)
+#define   G_028BDC_PERPENDICULAR_ENDCAP_ENA(x)                        (((x) >> 11) & 0x1)
+#define   C_028BDC_PERPENDICULAR_ENDCAP_ENA                           0xFFFFF7FF
+#define   S_028BDC_DX10_DIAMOND_TEST_ENA(x)                           (((x) & 0x1) << 12)
+#define   G_028BDC_DX10_DIAMOND_TEST_ENA(x)                           (((x) >> 12) & 0x1)
+#define   C_028BDC_DX10_DIAMOND_TEST_ENA                              0xFFFFEFFF
+#define R_028BE0_PA_SC_AA_CONFIG                                        0x028BE0
+#define   S_028BE0_MSAA_NUM_SAMPLES(x)                                (((x) & 0x07) << 0)
+#define   G_028BE0_MSAA_NUM_SAMPLES(x)                                (((x) >> 0) & 0x07)
+#define   C_028BE0_MSAA_NUM_SAMPLES                                   0xFFFFFFF8
+#define   S_028BE0_AA_MASK_CENTROID_DTMN(x)                           (((x) & 0x1) << 4)
+#define   G_028BE0_AA_MASK_CENTROID_DTMN(x)                           (((x) >> 4) & 0x1)
+#define   C_028BE0_AA_MASK_CENTROID_DTMN                              0xFFFFFFEF
+#define   S_028BE0_MAX_SAMPLE_DIST(x)                                 (((x) & 0x0F) << 13)
+#define   G_028BE0_MAX_SAMPLE_DIST(x)                                 (((x) >> 13) & 0x0F)
+#define   C_028BE0_MAX_SAMPLE_DIST                                    0xFFFE1FFF
+#define   S_028BE0_MSAA_EXPOSED_SAMPLES(x)                            (((x) & 0x07) << 20)
+#define   G_028BE0_MSAA_EXPOSED_SAMPLES(x)                            (((x) >> 20) & 0x07)
+#define   C_028BE0_MSAA_EXPOSED_SAMPLES                               0xFF8FFFFF
+#define   S_028BE0_DETAIL_TO_EXPOSED_MODE(x)                          (((x) & 0x03) << 24)
+#define   G_028BE0_DETAIL_TO_EXPOSED_MODE(x)                          (((x) >> 24) & 0x03)
+#define   C_028BE0_DETAIL_TO_EXPOSED_MODE                             0xFCFFFFFF
+#define R_028BE4_PA_SU_VTX_CNTL                                         0x028BE4
+#define   S_028BE4_PIX_CENTER(x)                                      (((x) & 0x1) << 0)
+#define   G_028BE4_PIX_CENTER(x)                                      (((x) >> 0) & 0x1)
+#define   C_028BE4_PIX_CENTER                                         0xFFFFFFFE
+#define   S_028BE4_ROUND_MODE(x)                                      (((x) & 0x03) << 1)
+#define   G_028BE4_ROUND_MODE(x)                                      (((x) >> 1) & 0x03)
+#define   C_028BE4_ROUND_MODE                                         0xFFFFFFF9
+#define     V_028BE4_X_TRUNCATE                                     0x00
+#define     V_028BE4_X_ROUND                                        0x01
+#define     V_028BE4_X_ROUND_TO_EVEN                                0x02
+#define     V_028BE4_X_ROUND_TO_ODD                                 0x03
+#define   S_028BE4_QUANT_MODE(x)                                      (((x) & 0x07) << 3)
+#define   G_028BE4_QUANT_MODE(x)                                      (((x) >> 3) & 0x07)
+#define   C_028BE4_QUANT_MODE                                         0xFFFFFFC7
+#define     V_028BE4_X_16_8_FIXED_POINT_1_16TH                      0x00
+#define     V_028BE4_X_16_8_FIXED_POINT_1_8TH                       0x01
+#define     V_028BE4_X_16_8_FIXED_POINT_1_4TH                       0x02
+#define     V_028BE4_X_16_8_FIXED_POINT_1_2                         0x03
+#define     V_028BE4_X_16_8_FIXED_POINT_1                           0x04
+#define     V_028BE4_X_16_8_FIXED_POINT_1_256TH                     0x05
+#define     V_028BE4_X_14_10_FIXED_POINT_1_1024TH                   0x06
+#define     V_028BE4_X_12_12_FIXED_POINT_1_4096TH                   0x07
+#define R_028BE8_PA_CL_GB_VERT_CLIP_ADJ                                 0x028BE8
+#define R_028BEC_PA_CL_GB_VERT_DISC_ADJ                                 0x028BEC
+#define R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ                                 0x028BF0
+#define R_028BF4_PA_CL_GB_HORZ_DISC_ADJ                                 0x028BF4
+#define R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0                      0x028BF8
+#define   S_028BF8_S0_X(x)                                            (((x) & 0x0F) << 0)
+#define   G_028BF8_S0_X(x)                                            (((x) >> 0) & 0x0F)
+#define   C_028BF8_S0_X                                               0xFFFFFFF0
+#define   S_028BF8_S0_Y(x)                                            (((x) & 0x0F) << 4)
+#define   G_028BF8_S0_Y(x)                                            (((x) >> 4) & 0x0F)
+#define   C_028BF8_S0_Y                                               0xFFFFFF0F
+#define   S_028BF8_S1_X(x)                                            (((x) & 0x0F) << 8)
+#define   G_028BF8_S1_X(x)                                            (((x) >> 8) & 0x0F)
+#define   C_028BF8_S1_X                                               0xFFFFF0FF
+#define   S_028BF8_S1_Y(x)                                            (((x) & 0x0F) << 12)
+#define   G_028BF8_S1_Y(x)                                            (((x) >> 12) & 0x0F)
+#define   C_028BF8_S1_Y                                               0xFFFF0FFF
+#define   S_028BF8_S2_X(x)                                            (((x) & 0x0F) << 16)
+#define   G_028BF8_S2_X(x)                                            (((x) >> 16) & 0x0F)
+#define   C_028BF8_S2_X                                               0xFFF0FFFF
+#define   S_028BF8_S2_Y(x)                                            (((x) & 0x0F) << 20)
+#define   G_028BF8_S2_Y(x)                                            (((x) >> 20) & 0x0F)
+#define   C_028BF8_S2_Y                                               0xFF0FFFFF
+#define   S_028BF8_S3_X(x)                                            (((x) & 0x0F) << 24)
+#define   G_028BF8_S3_X(x)                                            (((x) >> 24) & 0x0F)
+#define   C_028BF8_S3_X                                               0xF0FFFFFF
+#define   S_028BF8_S3_Y(x)                                            (((x) & 0x0F) << 28)
+#define   G_028BF8_S3_Y(x)                                            (((x) >> 28) & 0x0F)
+#define   C_028BF8_S3_Y                                               0x0FFFFFFF
+#define R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1                      0x028BFC
+#define   S_028BFC_S4_X(x)                                            (((x) & 0x0F) << 0)
+#define   G_028BFC_S4_X(x)                                            (((x) >> 0) & 0x0F)
+#define   C_028BFC_S4_X                                               0xFFFFFFF0
+#define   S_028BFC_S4_Y(x)                                            (((x) & 0x0F) << 4)
+#define   G_028BFC_S4_Y(x)                                            (((x) >> 4) & 0x0F)
+#define   C_028BFC_S4_Y                                               0xFFFFFF0F
+#define   S_028BFC_S5_X(x)                                            (((x) & 0x0F) << 8)
+#define   G_028BFC_S5_X(x)                                            (((x) >> 8) & 0x0F)
+#define   C_028BFC_S5_X                                               0xFFFFF0FF
+#define   S_028BFC_S5_Y(x)                                            (((x) & 0x0F) << 12)
+#define   G_028BFC_S5_Y(x)                                            (((x) >> 12) & 0x0F)
+#define   C_028BFC_S5_Y                                               0xFFFF0FFF
+#define   S_028BFC_S6_X(x)                                            (((x) & 0x0F) << 16)
+#define   G_028BFC_S6_X(x)                                            (((x) >> 16) & 0x0F)
+#define   C_028BFC_S6_X                                               0xFFF0FFFF
+#define   S_028BFC_S6_Y(x)                                            (((x) & 0x0F) << 20)
+#define   G_028BFC_S6_Y(x)                                            (((x) >> 20) & 0x0F)
+#define   C_028BFC_S6_Y                                               0xFF0FFFFF
+#define   S_028BFC_S7_X(x)                                            (((x) & 0x0F) << 24)
+#define   G_028BFC_S7_X(x)                                            (((x) >> 24) & 0x0F)
+#define   C_028BFC_S7_X                                               0xF0FFFFFF
+#define   S_028BFC_S7_Y(x)                                            (((x) & 0x0F) << 28)
+#define   G_028BFC_S7_Y(x)                                            (((x) >> 28) & 0x0F)
+#define   C_028BFC_S7_Y                                               0x0FFFFFFF
+#define R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2                      0x028C00
+#define   S_028C00_S8_X(x)                                            (((x) & 0x0F) << 0)
+#define   G_028C00_S8_X(x)                                            (((x) >> 0) & 0x0F)
+#define   C_028C00_S8_X                                               0xFFFFFFF0
+#define   S_028C00_S8_Y(x)                                            (((x) & 0x0F) << 4)
+#define   G_028C00_S8_Y(x)                                            (((x) >> 4) & 0x0F)
+#define   C_028C00_S8_Y                                               0xFFFFFF0F
+#define   S_028C00_S9_X(x)                                            (((x) & 0x0F) << 8)
+#define   G_028C00_S9_X(x)                                            (((x) >> 8) & 0x0F)
+#define   C_028C00_S9_X                                               0xFFFFF0FF
+#define   S_028C00_S9_Y(x)                                            (((x) & 0x0F) << 12)
+#define   G_028C00_S9_Y(x)                                            (((x) >> 12) & 0x0F)
+#define   C_028C00_S9_Y                                               0xFFFF0FFF
+#define   S_028C00_S10_X(x)                                           (((x) & 0x0F) << 16)
+#define   G_028C00_S10_X(x)                                           (((x) >> 16) & 0x0F)
+#define   C_028C00_S10_X                                              0xFFF0FFFF
+#define   S_028C00_S10_Y(x)                                           (((x) & 0x0F) << 20)
+#define   G_028C00_S10_Y(x)                                           (((x) >> 20) & 0x0F)
+#define   C_028C00_S10_Y                                              0xFF0FFFFF
+#define   S_028C00_S11_X(x)                                           (((x) & 0x0F) << 24)
+#define   G_028C00_S11_X(x)                                           (((x) >> 24) & 0x0F)
+#define   C_028C00_S11_X                                              0xF0FFFFFF
+#define   S_028C00_S11_Y(x)                                           (((x) & 0x0F) << 28)
+#define   G_028C00_S11_Y(x)                                           (((x) >> 28) & 0x0F)
+#define   C_028C00_S11_Y                                              0x0FFFFFFF
+#define R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3                      0x028C04
+#define   S_028C04_S12_X(x)                                           (((x) & 0x0F) << 0)
+#define   G_028C04_S12_X(x)                                           (((x) >> 0) & 0x0F)
+#define   C_028C04_S12_X                                              0xFFFFFFF0
+#define   S_028C04_S12_Y(x)                                           (((x) & 0x0F) << 4)
+#define   G_028C04_S12_Y(x)                                           (((x) >> 4) & 0x0F)
+#define   C_028C04_S12_Y                                              0xFFFFFF0F
+#define   S_028C04_S13_X(x)                                           (((x) & 0x0F) << 8)
+#define   G_028C04_S13_X(x)                                           (((x) >> 8) & 0x0F)
+#define   C_028C04_S13_X                                              0xFFFFF0FF
+#define   S_028C04_S13_Y(x)                                           (((x) & 0x0F) << 12)
+#define   G_028C04_S13_Y(x)                                           (((x) >> 12) & 0x0F)
+#define   C_028C04_S13_Y                                              0xFFFF0FFF
+#define   S_028C04_S14_X(x)                                           (((x) & 0x0F) << 16)
+#define   G_028C04_S14_X(x)                                           (((x) >> 16) & 0x0F)
+#define   C_028C04_S14_X                                              0xFFF0FFFF
+#define   S_028C04_S14_Y(x)                                           (((x) & 0x0F) << 20)
+#define   G_028C04_S14_Y(x)                                           (((x) >> 20) & 0x0F)
+#define   C_028C04_S14_Y                                              0xFF0FFFFF
+#define   S_028C04_S15_X(x)                                           (((x) & 0x0F) << 24)
+#define   G_028C04_S15_X(x)                                           (((x) >> 24) & 0x0F)
+#define   C_028C04_S15_X                                              0xF0FFFFFF
+#define   S_028C04_S15_Y(x)                                           (((x) & 0x0F) << 28)
+#define   G_028C04_S15_Y(x)                                           (((x) >> 28) & 0x0F)
+#define   C_028C04_S15_Y                                              0x0FFFFFFF
+#define R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0                      0x028C08
+#define   S_028C08_S0_X(x)                                            (((x) & 0x0F) << 0)
+#define   G_028C08_S0_X(x)                                            (((x) >> 0) & 0x0F)
+#define   C_028C08_S0_X                                               0xFFFFFFF0
+#define   S_028C08_S0_Y(x)                                            (((x) & 0x0F) << 4)
+#define   G_028C08_S0_Y(x)                                            (((x) >> 4) & 0x0F)
+#define   C_028C08_S0_Y                                               0xFFFFFF0F
+#define   S_028C08_S1_X(x)                                            (((x) & 0x0F) << 8)
+#define   G_028C08_S1_X(x)                                            (((x) >> 8) & 0x0F)
+#define   C_028C08_S1_X                                               0xFFFFF0FF
+#define   S_028C08_S1_Y(x)                                            (((x) & 0x0F) << 12)
+#define   G_028C08_S1_Y(x)                                            (((x) >> 12) & 0x0F)
+#define   C_028C08_S1_Y                                               0xFFFF0FFF
+#define   S_028C08_S2_X(x)                                            (((x) & 0x0F) << 16)
+#define   G_028C08_S2_X(x)                                            (((x) >> 16) & 0x0F)
+#define   C_028C08_S2_X                                               0xFFF0FFFF
+#define   S_028C08_S2_Y(x)                                            (((x) & 0x0F) << 20)
+#define   G_028C08_S2_Y(x)                                            (((x) >> 20) & 0x0F)
+#define   C_028C08_S2_Y                                               0xFF0FFFFF
+#define   S_028C08_S3_X(x)                                            (((x) & 0x0F) << 24)
+#define   G_028C08_S3_X(x)                                            (((x) >> 24) & 0x0F)
+#define   C_028C08_S3_X                                               0xF0FFFFFF
+#define   S_028C08_S3_Y(x)                                            (((x) & 0x0F) << 28)
+#define   G_028C08_S3_Y(x)                                            (((x) >> 28) & 0x0F)
+#define   C_028C08_S3_Y                                               0x0FFFFFFF
+#define R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1                      0x028C0C
+#define   S_028C0C_S4_X(x)                                            (((x) & 0x0F) << 0)
+#define   G_028C0C_S4_X(x)                                            (((x) >> 0) & 0x0F)
+#define   C_028C0C_S4_X                                               0xFFFFFFF0
+#define   S_028C0C_S4_Y(x)                                            (((x) & 0x0F) << 4)
+#define   G_028C0C_S4_Y(x)                                            (((x) >> 4) & 0x0F)
+#define   C_028C0C_S4_Y                                               0xFFFFFF0F
+#define   S_028C0C_S5_X(x)                                            (((x) & 0x0F) << 8)
+#define   G_028C0C_S5_X(x)                                            (((x) >> 8) & 0x0F)
+#define   C_028C0C_S5_X                                               0xFFFFF0FF
+#define   S_028C0C_S5_Y(x)                                            (((x) & 0x0F) << 12)
+#define   G_028C0C_S5_Y(x)                                            (((x) >> 12) & 0x0F)
+#define   C_028C0C_S5_Y                                               0xFFFF0FFF
+#define   S_028C0C_S6_X(x)                                            (((x) & 0x0F) << 16)
+#define   G_028C0C_S6_X(x)                                            (((x) >> 16) & 0x0F)
+#define   C_028C0C_S6_X                                               0xFFF0FFFF
+#define   S_028C0C_S6_Y(x)                                            (((x) & 0x0F) << 20)
+#define   G_028C0C_S6_Y(x)                                            (((x) >> 20) & 0x0F)
+#define   C_028C0C_S6_Y                                               0xFF0FFFFF
+#define   S_028C0C_S7_X(x)                                            (((x) & 0x0F) << 24)
+#define   G_028C0C_S7_X(x)                                            (((x) >> 24) & 0x0F)
+#define   C_028C0C_S7_X                                               0xF0FFFFFF
+#define   S_028C0C_S7_Y(x)                                            (((x) & 0x0F) << 28)
+#define   G_028C0C_S7_Y(x)                                            (((x) >> 28) & 0x0F)
+#define   C_028C0C_S7_Y                                               0x0FFFFFFF
+#define R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2                      0x028C10
+#define   S_028C10_S8_X(x)                                            (((x) & 0x0F) << 0)
+#define   G_028C10_S8_X(x)                                            (((x) >> 0) & 0x0F)
+#define   C_028C10_S8_X                                               0xFFFFFFF0
+#define   S_028C10_S8_Y(x)                                            (((x) & 0x0F) << 4)
+#define   G_028C10_S8_Y(x)                                            (((x) >> 4) & 0x0F)
+#define   C_028C10_S8_Y                                               0xFFFFFF0F
+#define   S_028C10_S9_X(x)                                            (((x) & 0x0F) << 8)
+#define   G_028C10_S9_X(x)                                            (((x) >> 8) & 0x0F)
+#define   C_028C10_S9_X                                               0xFFFFF0FF
+#define   S_028C10_S9_Y(x)                                            (((x) & 0x0F) << 12)
+#define   G_028C10_S9_Y(x)                                            (((x) >> 12) & 0x0F)
+#define   C_028C10_S9_Y                                               0xFFFF0FFF
+#define   S_028C10_S10_X(x)                                           (((x) & 0x0F) << 16)
+#define   G_028C10_S10_X(x)                                           (((x) >> 16) & 0x0F)
+#define   C_028C10_S10_X                                              0xFFF0FFFF
+#define   S_028C10_S10_Y(x)                                           (((x) & 0x0F) << 20)
+#define   G_028C10_S10_Y(x)                                           (((x) >> 20) & 0x0F)
+#define   C_028C10_S10_Y                                              0xFF0FFFFF
+#define   S_028C10_S11_X(x)                                           (((x) & 0x0F) << 24)
+#define   G_028C10_S11_X(x)                                           (((x) >> 24) & 0x0F)
+#define   C_028C10_S11_X                                              0xF0FFFFFF
+#define   S_028C10_S11_Y(x)                                           (((x) & 0x0F) << 28)
+#define   G_028C10_S11_Y(x)                                           (((x) >> 28) & 0x0F)
+#define   C_028C10_S11_Y                                              0x0FFFFFFF
+#define R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3                      0x028C14
+#define   S_028C14_S12_X(x)                                           (((x) & 0x0F) << 0)
+#define   G_028C14_S12_X(x)                                           (((x) >> 0) & 0x0F)
+#define   C_028C14_S12_X                                              0xFFFFFFF0
+#define   S_028C14_S12_Y(x)                                           (((x) & 0x0F) << 4)
+#define   G_028C14_S12_Y(x)                                           (((x) >> 4) & 0x0F)
+#define   C_028C14_S12_Y                                              0xFFFFFF0F
+#define   S_028C14_S13_X(x)                                           (((x) & 0x0F) << 8)
+#define   G_028C14_S13_X(x)                                           (((x) >> 8) & 0x0F)
+#define   C_028C14_S13_X                                              0xFFFFF0FF
+#define   S_028C14_S13_Y(x)                                           (((x) & 0x0F) << 12)
+#define   G_028C14_S13_Y(x)                                           (((x) >> 12) & 0x0F)
+#define   C_028C14_S13_Y                                              0xFFFF0FFF
+#define   S_028C14_S14_X(x)                                           (((x) & 0x0F) << 16)
+#define   G_028C14_S14_X(x)                                           (((x) >> 16) & 0x0F)
+#define   C_028C14_S14_X                                              0xFFF0FFFF
+#define   S_028C14_S14_Y(x)                                           (((x) & 0x0F) << 20)
+#define   G_028C14_S14_Y(x)                                           (((x) >> 20) & 0x0F)
+#define   C_028C14_S14_Y                                              0xFF0FFFFF
+#define   S_028C14_S15_X(x)                                           (((x) & 0x0F) << 24)
+#define   G_028C14_S15_X(x)                                           (((x) >> 24) & 0x0F)
+#define   C_028C14_S15_X                                              0xF0FFFFFF
+#define   S_028C14_S15_Y(x)                                           (((x) & 0x0F) << 28)
+#define   G_028C14_S15_Y(x)                                           (((x) >> 28) & 0x0F)
+#define   C_028C14_S15_Y                                              0x0FFFFFFF
+#define R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0                      0x028C18
+#define   S_028C18_S0_X(x)                                            (((x) & 0x0F) << 0)
+#define   G_028C18_S0_X(x)                                            (((x) >> 0) & 0x0F)
+#define   C_028C18_S0_X                                               0xFFFFFFF0
+#define   S_028C18_S0_Y(x)                                            (((x) & 0x0F) << 4)
+#define   G_028C18_S0_Y(x)                                            (((x) >> 4) & 0x0F)
+#define   C_028C18_S0_Y                                               0xFFFFFF0F
+#define   S_028C18_S1_X(x)                                            (((x) & 0x0F) << 8)
+#define   G_028C18_S1_X(x)                                            (((x) >> 8) & 0x0F)
+#define   C_028C18_S1_X                                               0xFFFFF0FF
+#define   S_028C18_S1_Y(x)                                            (((x) & 0x0F) << 12)
+#define   G_028C18_S1_Y(x)                                            (((x) >> 12) & 0x0F)
+#define   C_028C18_S1_Y                                               0xFFFF0FFF
+#define   S_028C18_S2_X(x)                                            (((x) & 0x0F) << 16)
+#define   G_028C18_S2_X(x)                                            (((x) >> 16) & 0x0F)
+#define   C_028C18_S2_X                                               0xFFF0FFFF
+#define   S_028C18_S2_Y(x)                                            (((x) & 0x0F) << 20)
+#define   G_028C18_S2_Y(x)                                            (((x) >> 20) & 0x0F)
+#define   C_028C18_S2_Y                                               0xFF0FFFFF
+#define   S_028C18_S3_X(x)                                            (((x) & 0x0F) << 24)
+#define   G_028C18_S3_X(x)                                            (((x) >> 24) & 0x0F)
+#define   C_028C18_S3_X                                               0xF0FFFFFF
+#define   S_028C18_S3_Y(x)                                            (((x) & 0x0F) << 28)
+#define   G_028C18_S3_Y(x)                                            (((x) >> 28) & 0x0F)
+#define   C_028C18_S3_Y                                               0x0FFFFFFF
+#define R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1                      0x028C1C
+#define   S_028C1C_S4_X(x)                                            (((x) & 0x0F) << 0)
+#define   G_028C1C_S4_X(x)                                            (((x) >> 0) & 0x0F)
+#define   C_028C1C_S4_X                                               0xFFFFFFF0
+#define   S_028C1C_S4_Y(x)                                            (((x) & 0x0F) << 4)
+#define   G_028C1C_S4_Y(x)                                            (((x) >> 4) & 0x0F)
+#define   C_028C1C_S4_Y                                               0xFFFFFF0F
+#define   S_028C1C_S5_X(x)                                            (((x) & 0x0F) << 8)
+#define   G_028C1C_S5_X(x)                                            (((x) >> 8) & 0x0F)
+#define   C_028C1C_S5_X                                               0xFFFFF0FF
+#define   S_028C1C_S5_Y(x)                                            (((x) & 0x0F) << 12)
+#define   G_028C1C_S5_Y(x)                                            (((x) >> 12) & 0x0F)
+#define   C_028C1C_S5_Y                                               0xFFFF0FFF
+#define   S_028C1C_S6_X(x)                                            (((x) & 0x0F) << 16)
+#define   G_028C1C_S6_X(x)                                            (((x) >> 16) & 0x0F)
+#define   C_028C1C_S6_X                                               0xFFF0FFFF
+#define   S_028C1C_S6_Y(x)                                            (((x) & 0x0F) << 20)
+#define   G_028C1C_S6_Y(x)                                            (((x) >> 20) & 0x0F)
+#define   C_028C1C_S6_Y                                               0xFF0FFFFF
+#define   S_028C1C_S7_X(x)                                            (((x) & 0x0F) << 24)
+#define   G_028C1C_S7_X(x)                                            (((x) >> 24) & 0x0F)
+#define   C_028C1C_S7_X                                               0xF0FFFFFF
+#define   S_028C1C_S7_Y(x)                                            (((x) & 0x0F) << 28)
+#define   G_028C1C_S7_Y(x)                                            (((x) >> 28) & 0x0F)
+#define   C_028C1C_S7_Y                                               0x0FFFFFFF
+#define R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2                      0x028C20
+#define   S_028C20_S8_X(x)                                            (((x) & 0x0F) << 0)
+#define   G_028C20_S8_X(x)                                            (((x) >> 0) & 0x0F)
+#define   C_028C20_S8_X                                               0xFFFFFFF0
+#define   S_028C20_S8_Y(x)                                            (((x) & 0x0F) << 4)
+#define   G_028C20_S8_Y(x)                                            (((x) >> 4) & 0x0F)
+#define   C_028C20_S8_Y                                               0xFFFFFF0F
+#define   S_028C20_S9_X(x)                                            (((x) & 0x0F) << 8)
+#define   G_028C20_S9_X(x)                                            (((x) >> 8) & 0x0F)
+#define   C_028C20_S9_X                                               0xFFFFF0FF
+#define   S_028C20_S9_Y(x)                                            (((x) & 0x0F) << 12)
+#define   G_028C20_S9_Y(x)                                            (((x) >> 12) & 0x0F)
+#define   C_028C20_S9_Y                                               0xFFFF0FFF
+#define   S_028C20_S10_X(x)                                           (((x) & 0x0F) << 16)
+#define   G_028C20_S10_X(x)                                           (((x) >> 16) & 0x0F)
+#define   C_028C20_S10_X                                              0xFFF0FFFF
+#define   S_028C20_S10_Y(x)                                           (((x) & 0x0F) << 20)
+#define   G_028C20_S10_Y(x)                                           (((x) >> 20) & 0x0F)
+#define   C_028C20_S10_Y                                              0xFF0FFFFF
+#define   S_028C20_S11_X(x)                                           (((x) & 0x0F) << 24)
+#define   G_028C20_S11_X(x)                                           (((x) >> 24) & 0x0F)
+#define   C_028C20_S11_X                                              0xF0FFFFFF
+#define   S_028C20_S11_Y(x)                                           (((x) & 0x0F) << 28)
+#define   G_028C20_S11_Y(x)                                           (((x) >> 28) & 0x0F)
+#define   C_028C20_S11_Y                                              0x0FFFFFFF
+#define R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3                      0x028C24
+#define   S_028C24_S12_X(x)                                           (((x) & 0x0F) << 0)
+#define   G_028C24_S12_X(x)                                           (((x) >> 0) & 0x0F)
+#define   C_028C24_S12_X                                              0xFFFFFFF0
+#define   S_028C24_S12_Y(x)                                           (((x) & 0x0F) << 4)
+#define   G_028C24_S12_Y(x)                                           (((x) >> 4) & 0x0F)
+#define   C_028C24_S12_Y                                              0xFFFFFF0F
+#define   S_028C24_S13_X(x)                                           (((x) & 0x0F) << 8)
+#define   G_028C24_S13_X(x)                                           (((x) >> 8) & 0x0F)
+#define   C_028C24_S13_X                                              0xFFFFF0FF
+#define   S_028C24_S13_Y(x)                                           (((x) & 0x0F) << 12)
+#define   G_028C24_S13_Y(x)                                           (((x) >> 12) & 0x0F)
+#define   C_028C24_S13_Y                                              0xFFFF0FFF
+#define   S_028C24_S14_X(x)                                           (((x) & 0x0F) << 16)
+#define   G_028C24_S14_X(x)                                           (((x) >> 16) & 0x0F)
+#define   C_028C24_S14_X                                              0xFFF0FFFF
+#define   S_028C24_S14_Y(x)                                           (((x) & 0x0F) << 20)
+#define   G_028C24_S14_Y(x)                                           (((x) >> 20) & 0x0F)
+#define   C_028C24_S14_Y                                              0xFF0FFFFF
+#define   S_028C24_S15_X(x)                                           (((x) & 0x0F) << 24)
+#define   G_028C24_S15_X(x)                                           (((x) >> 24) & 0x0F)
+#define   C_028C24_S15_X                                              0xF0FFFFFF
+#define   S_028C24_S15_Y(x)                                           (((x) & 0x0F) << 28)
+#define   G_028C24_S15_Y(x)                                           (((x) >> 28) & 0x0F)
+#define   C_028C24_S15_Y                                              0x0FFFFFFF
+#define R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0                      0x028C28
+#define   S_028C28_S0_X(x)                                            (((x) & 0x0F) << 0)
+#define   G_028C28_S0_X(x)                                            (((x) >> 0) & 0x0F)
+#define   C_028C28_S0_X                                               0xFFFFFFF0
+#define   S_028C28_S0_Y(x)                                            (((x) & 0x0F) << 4)
+#define   G_028C28_S0_Y(x)                                            (((x) >> 4) & 0x0F)
+#define   C_028C28_S0_Y                                               0xFFFFFF0F
+#define   S_028C28_S1_X(x)                                            (((x) & 0x0F) << 8)
+#define   G_028C28_S1_X(x)                                            (((x) >> 8) & 0x0F)
+#define   C_028C28_S1_X                                               0xFFFFF0FF
+#define   S_028C28_S1_Y(x)                                            (((x) & 0x0F) << 12)
+#define   G_028C28_S1_Y(x)                                            (((x) >> 12) & 0x0F)
+#define   C_028C28_S1_Y                                               0xFFFF0FFF
+#define   S_028C28_S2_X(x)                                            (((x) & 0x0F) << 16)
+#define   G_028C28_S2_X(x)                                            (((x) >> 16) & 0x0F)
+#define   C_028C28_S2_X                                               0xFFF0FFFF
+#define   S_028C28_S2_Y(x)                                            (((x) & 0x0F) << 20)
+#define   G_028C28_S2_Y(x)                                            (((x) >> 20) & 0x0F)
+#define   C_028C28_S2_Y                                               0xFF0FFFFF
+#define   S_028C28_S3_X(x)                                            (((x) & 0x0F) << 24)
+#define   G_028C28_S3_X(x)                                            (((x) >> 24) & 0x0F)
+#define   C_028C28_S3_X                                               0xF0FFFFFF
+#define   S_028C28_S3_Y(x)                                            (((x) & 0x0F) << 28)
+#define   G_028C28_S3_Y(x)                                            (((x) >> 28) & 0x0F)
+#define   C_028C28_S3_Y                                               0x0FFFFFFF
+#define R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1                      0x028C2C
+#define   S_028C2C_S4_X(x)                                            (((x) & 0x0F) << 0)
+#define   G_028C2C_S4_X(x)                                            (((x) >> 0) & 0x0F)
+#define   C_028C2C_S4_X                                               0xFFFFFFF0
+#define   S_028C2C_S4_Y(x)                                            (((x) & 0x0F) << 4)
+#define   G_028C2C_S4_Y(x)                                            (((x) >> 4) & 0x0F)
+#define   C_028C2C_S4_Y                                               0xFFFFFF0F
+#define   S_028C2C_S5_X(x)                                            (((x) & 0x0F) << 8)
+#define   G_028C2C_S5_X(x)                                            (((x) >> 8) & 0x0F)
+#define   C_028C2C_S5_X                                               0xFFFFF0FF
+#define   S_028C2C_S5_Y(x)                                            (((x) & 0x0F) << 12)
+#define   G_028C2C_S5_Y(x)                                            (((x) >> 12) & 0x0F)
+#define   C_028C2C_S5_Y                                               0xFFFF0FFF
+#define   S_028C2C_S6_X(x)                                            (((x) & 0x0F) << 16)
+#define   G_028C2C_S6_X(x)                                            (((x) >> 16) & 0x0F)
+#define   C_028C2C_S6_X                                               0xFFF0FFFF
+#define   S_028C2C_S6_Y(x)                                            (((x) & 0x0F) << 20)
+#define   G_028C2C_S6_Y(x)                                            (((x) >> 20) & 0x0F)
+#define   C_028C2C_S6_Y                                               0xFF0FFFFF
+#define   S_028C2C_S7_X(x)                                            (((x) & 0x0F) << 24)
+#define   G_028C2C_S7_X(x)                                            (((x) >> 24) & 0x0F)
+#define   C_028C2C_S7_X                                               0xF0FFFFFF
+#define   S_028C2C_S7_Y(x)                                            (((x) & 0x0F) << 28)
+#define   G_028C2C_S7_Y(x)                                            (((x) >> 28) & 0x0F)
+#define   C_028C2C_S7_Y                                               0x0FFFFFFF
+#define R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2                      0x028C30
+#define   S_028C30_S8_X(x)                                            (((x) & 0x0F) << 0)
+#define   G_028C30_S8_X(x)                                            (((x) >> 0) & 0x0F)
+#define   C_028C30_S8_X                                               0xFFFFFFF0
+#define   S_028C30_S8_Y(x)                                            (((x) & 0x0F) << 4)
+#define   G_028C30_S8_Y(x)                                            (((x) >> 4) & 0x0F)
+#define   C_028C30_S8_Y                                               0xFFFFFF0F
+#define   S_028C30_S9_X(x)                                            (((x) & 0x0F) << 8)
+#define   G_028C30_S9_X(x)                                            (((x) >> 8) & 0x0F)
+#define   C_028C30_S9_X                                               0xFFFFF0FF
+#define   S_028C30_S9_Y(x)                                            (((x) & 0x0F) << 12)
+#define   G_028C30_S9_Y(x)                                            (((x) >> 12) & 0x0F)
+#define   C_028C30_S9_Y                                               0xFFFF0FFF
+#define   S_028C30_S10_X(x)                                           (((x) & 0x0F) << 16)
+#define   G_028C30_S10_X(x)                                           (((x) >> 16) & 0x0F)
+#define   C_028C30_S10_X                                              0xFFF0FFFF
+#define   S_028C30_S10_Y(x)                                           (((x) & 0x0F) << 20)
+#define   G_028C30_S10_Y(x)                                           (((x) >> 20) & 0x0F)
+#define   C_028C30_S10_Y                                              0xFF0FFFFF
+#define   S_028C30_S11_X(x)                                           (((x) & 0x0F) << 24)
+#define   G_028C30_S11_X(x)                                           (((x) >> 24) & 0x0F)
+#define   C_028C30_S11_X                                              0xF0FFFFFF
+#define   S_028C30_S11_Y(x)                                           (((x) & 0x0F) << 28)
+#define   G_028C30_S11_Y(x)                                           (((x) >> 28) & 0x0F)
+#define   C_028C30_S11_Y                                              0x0FFFFFFF
+#define R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3                      0x028C34
+#define   S_028C34_S12_X(x)                                           (((x) & 0x0F) << 0)
+#define   G_028C34_S12_X(x)                                           (((x) >> 0) & 0x0F)
+#define   C_028C34_S12_X                                              0xFFFFFFF0
+#define   S_028C34_S12_Y(x)                                           (((x) & 0x0F) << 4)
+#define   G_028C34_S12_Y(x)                                           (((x) >> 4) & 0x0F)
+#define   C_028C34_S12_Y                                              0xFFFFFF0F
+#define   S_028C34_S13_X(x)                                           (((x) & 0x0F) << 8)
+#define   G_028C34_S13_X(x)                                           (((x) >> 8) & 0x0F)
+#define   C_028C34_S13_X                                              0xFFFFF0FF
+#define   S_028C34_S13_Y(x)                                           (((x) & 0x0F) << 12)
+#define   G_028C34_S13_Y(x)                                           (((x) >> 12) & 0x0F)
+#define   C_028C34_S13_Y                                              0xFFFF0FFF
+#define   S_028C34_S14_X(x)                                           (((x) & 0x0F) << 16)
+#define   G_028C34_S14_X(x)                                           (((x) >> 16) & 0x0F)
+#define   C_028C34_S14_X                                              0xFFF0FFFF
+#define   S_028C34_S14_Y(x)                                           (((x) & 0x0F) << 20)
+#define   G_028C34_S14_Y(x)                                           (((x) >> 20) & 0x0F)
+#define   C_028C34_S14_Y                                              0xFF0FFFFF
+#define   S_028C34_S15_X(x)                                           (((x) & 0x0F) << 24)
+#define   G_028C34_S15_X(x)                                           (((x) >> 24) & 0x0F)
+#define   C_028C34_S15_X                                              0xF0FFFFFF
+#define   S_028C34_S15_Y(x)                                           (((x) & 0x0F) << 28)
+#define   G_028C34_S15_Y(x)                                           (((x) >> 28) & 0x0F)
+#define   C_028C34_S15_Y                                              0x0FFFFFFF
+#define R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0                                0x028C38
+#define   S_028C38_AA_MASK_X0Y0(x)                                    (((x) & 0xFFFF) << 0)
+#define   G_028C38_AA_MASK_X0Y0(x)                                    (((x) >> 0) & 0xFFFF)
+#define   C_028C38_AA_MASK_X0Y0                                       0xFFFF0000
+#define   S_028C38_AA_MASK_X1Y0(x)                                    (((x) & 0xFFFF) << 16)
+#define   G_028C38_AA_MASK_X1Y0(x)                                    (((x) >> 16) & 0xFFFF)
+#define   C_028C38_AA_MASK_X1Y0                                       0x0000FFFF
+#define R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1                                0x028C3C
+#define   S_028C3C_AA_MASK_X0Y1(x)                                    (((x) & 0xFFFF) << 0)
+#define   G_028C3C_AA_MASK_X0Y1(x)                                    (((x) >> 0) & 0xFFFF)
+#define   C_028C3C_AA_MASK_X0Y1                                       0xFFFF0000
+#define   S_028C3C_AA_MASK_X1Y1(x)                                    (((x) & 0xFFFF) << 16)
+#define   G_028C3C_AA_MASK_X1Y1(x)                                    (((x) >> 16) & 0xFFFF)
+#define   C_028C3C_AA_MASK_X1Y1                                       0x0000FFFF
+#define R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL                            0x028C58
+#define   S_028C58_VTX_REUSE_DEPTH(x)                                 (((x) & 0xFF) << 0)
+#define   G_028C58_VTX_REUSE_DEPTH(x)                                 (((x) >> 0) & 0xFF)
+#define   C_028C58_VTX_REUSE_DEPTH                                    0xFFFFFF00
+#define R_028C5C_VGT_OUT_DEALLOC_CNTL                                   0x028C5C
+#define   S_028C5C_DEALLOC_DIST(x)                                    (((x) & 0x7F) << 0)
+#define   G_028C5C_DEALLOC_DIST(x)                                    (((x) >> 0) & 0x7F)
+#define   C_028C5C_DEALLOC_DIST                                       0xFFFFFF80
+#define R_028C60_CB_COLOR0_BASE                                         0x028C60
+#define R_028C64_CB_COLOR0_PITCH                                        0x028C64
+#define   S_028C64_TILE_MAX(x)                                        (((x) & 0x7FF) << 0)
+#define   G_028C64_TILE_MAX(x)                                        (((x) >> 0) & 0x7FF)
+#define   C_028C64_TILE_MAX                                           0xFFFFF800
+/* CIK */
+#define   S_028C64_FMASK_TILE_MAX(x)                                  (((x) & 0x7FF) << 20)
+#define   G_028C64_FMASK_TILE_MAX(x)                                  (((x) >> 20) & 0x7FF)
+#define   C_028C64_FMASK_TILE_MAX                                     0x800FFFFF
+/*     */
+#define R_028C68_CB_COLOR0_SLICE                                        0x028C68
+#define   S_028C68_TILE_MAX(x)                                        (((x) & 0x3FFFFF) << 0)
+#define   G_028C68_TILE_MAX(x)                                        (((x) >> 0) & 0x3FFFFF)
+#define   C_028C68_TILE_MAX                                           0xFFC00000
+#define R_028C6C_CB_COLOR0_VIEW                                         0x028C6C
+#define   S_028C6C_SLICE_START(x)                                     (((x) & 0x7FF) << 0)
+#define   G_028C6C_SLICE_START(x)                                     (((x) >> 0) & 0x7FF)
+#define   C_028C6C_SLICE_START                                        0xFFFFF800
+#define   S_028C6C_SLICE_MAX(x)                                       (((x) & 0x7FF) << 13)
+#define   G_028C6C_SLICE_MAX(x)                                       (((x) >> 13) & 0x7FF)
+#define   C_028C6C_SLICE_MAX                                          0xFF001FFF
+#define R_028C70_CB_COLOR0_INFO                                         0x028C70
+#define   S_028C70_ENDIAN(x)                                          (((x) & 0x03) << 0)
+#define   G_028C70_ENDIAN(x)                                          (((x) >> 0) & 0x03)
+#define   C_028C70_ENDIAN                                             0xFFFFFFFC
+#define     V_028C70_ENDIAN_NONE                                    0x00
+#define     V_028C70_ENDIAN_8IN16                                   0x01
+#define     V_028C70_ENDIAN_8IN32                                   0x02
+#define     V_028C70_ENDIAN_8IN64                                   0x03
+#define   S_028C70_FORMAT(x)                                          (((x) & 0x1F) << 2)
+#define   G_028C70_FORMAT(x)                                          (((x) >> 2) & 0x1F)
+#define   C_028C70_FORMAT                                             0xFFFFFF83
+#define     V_028C70_COLOR_INVALID                                  0x00
+#define     V_028C70_COLOR_8                                        0x01
+#define     V_028C70_COLOR_16                                       0x02
+#define     V_028C70_COLOR_8_8                                      0x03
+#define     V_028C70_COLOR_32                                       0x04
+#define     V_028C70_COLOR_16_16                                    0x05
+#define     V_028C70_COLOR_10_11_11                                 0x06
+#define     V_028C70_COLOR_11_11_10                                 0x07
+#define     V_028C70_COLOR_10_10_10_2                               0x08
+#define     V_028C70_COLOR_2_10_10_10                               0x09
+#define     V_028C70_COLOR_8_8_8_8                                  0x0A
+#define     V_028C70_COLOR_32_32                                    0x0B
+#define     V_028C70_COLOR_16_16_16_16                              0x0C
+#define     V_028C70_COLOR_32_32_32_32                              0x0E
+#define     V_028C70_COLOR_5_6_5                                    0x10
+#define     V_028C70_COLOR_1_5_5_5                                  0x11
+#define     V_028C70_COLOR_5_5_5_1                                  0x12
+#define     V_028C70_COLOR_4_4_4_4                                  0x13
+#define     V_028C70_COLOR_8_24                                     0x14
+#define     V_028C70_COLOR_24_8                                     0x15
+#define     V_028C70_COLOR_X24_8_32_FLOAT                           0x16
+#define   S_028C70_LINEAR_GENERAL(x)                                  (((x) & 0x1) << 7)
+#define   G_028C70_LINEAR_GENERAL(x)                                  (((x) >> 7) & 0x1)
+#define   C_028C70_LINEAR_GENERAL                                     0xFFFFFF7F
+#define   S_028C70_NUMBER_TYPE(x)                                     (((x) & 0x07) << 8)
+#define   G_028C70_NUMBER_TYPE(x)                                     (((x) >> 8) & 0x07)
+#define   C_028C70_NUMBER_TYPE                                        0xFFFFF8FF
+#define     V_028C70_NUMBER_UNORM                                   0x00
+#define     V_028C70_NUMBER_SNORM                                   0x01
+#define     V_028C70_NUMBER_UINT                                    0x04
+#define     V_028C70_NUMBER_SINT                                    0x05
+#define     V_028C70_NUMBER_SRGB                                    0x06
+#define     V_028C70_NUMBER_FLOAT                                   0x07
+#define   S_028C70_COMP_SWAP(x)                                       (((x) & 0x03) << 11)
+#define   G_028C70_COMP_SWAP(x)                                       (((x) >> 11) & 0x03)
+#define   C_028C70_COMP_SWAP                                          0xFFFFE7FF
+#define     V_028C70_SWAP_STD                                       0x00
+#define     V_028C70_SWAP_ALT                                       0x01
+#define     V_028C70_SWAP_STD_REV                                   0x02
+#define     V_028C70_SWAP_ALT_REV                                   0x03
+#define   S_028C70_FAST_CLEAR(x)                                      (((x) & 0x1) << 13)
+#define   G_028C70_FAST_CLEAR(x)                                      (((x) >> 13) & 0x1)
+#define   C_028C70_FAST_CLEAR                                         0xFFFFDFFF
+#define   S_028C70_COMPRESSION(x)                                     (((x) & 0x1) << 14)
+#define   G_028C70_COMPRESSION(x)                                     (((x) >> 14) & 0x1)
+#define   C_028C70_COMPRESSION                                        0xFFFFBFFF
+#define   S_028C70_BLEND_CLAMP(x)                                     (((x) & 0x1) << 15)
+#define   G_028C70_BLEND_CLAMP(x)                                     (((x) >> 15) & 0x1)
+#define   C_028C70_BLEND_CLAMP                                        0xFFFF7FFF
+#define   S_028C70_BLEND_BYPASS(x)                                    (((x) & 0x1) << 16)
+#define   G_028C70_BLEND_BYPASS(x)                                    (((x) >> 16) & 0x1)
+#define   C_028C70_BLEND_BYPASS                                       0xFFFEFFFF
+#define   S_028C70_SIMPLE_FLOAT(x)                                    (((x) & 0x1) << 17)
+#define   G_028C70_SIMPLE_FLOAT(x)                                    (((x) >> 17) & 0x1)
+#define   C_028C70_SIMPLE_FLOAT                                       0xFFFDFFFF
+#define   S_028C70_ROUND_MODE(x)                                      (((x) & 0x1) << 18)
+#define   G_028C70_ROUND_MODE(x)                                      (((x) >> 18) & 0x1)
+#define   C_028C70_ROUND_MODE                                         0xFFFBFFFF
+#define   S_028C70_CMASK_IS_LINEAR(x)                                 (((x) & 0x1) << 19)
+#define   G_028C70_CMASK_IS_LINEAR(x)                                 (((x) >> 19) & 0x1)
+#define   C_028C70_CMASK_IS_LINEAR                                    0xFFF7FFFF
+#define   S_028C70_BLEND_OPT_DONT_RD_DST(x)                           (((x) & 0x07) << 20)
+#define   G_028C70_BLEND_OPT_DONT_RD_DST(x)                           (((x) >> 20) & 0x07)
+#define   C_028C70_BLEND_OPT_DONT_RD_DST                              0xFF8FFFFF
+#define     V_028C70_FORCE_OPT_AUTO                                 0x00
+#define     V_028C70_FORCE_OPT_DISABLE                              0x01
+#define     V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_0                    0x02
+#define     V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_0                  0x03
+#define     V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_0                 0x04
+#define     V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_1                    0x05
+#define     V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_1                  0x06
+#define     V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_1                 0x07
+#define   S_028C70_BLEND_OPT_DISCARD_PIXEL(x)                         (((x) & 0x07) << 23)
+#define   G_028C70_BLEND_OPT_DISCARD_PIXEL(x)                         (((x) >> 23) & 0x07)
+#define   C_028C70_BLEND_OPT_DISCARD_PIXEL                            0xFC7FFFFF
+#define     V_028C70_FORCE_OPT_AUTO                                 0x00
+#define     V_028C70_FORCE_OPT_DISABLE                              0x01
+#define     V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_0                    0x02
+#define     V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_0                  0x03
+#define     V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_0                 0x04
+#define     V_028C70_FORCE_OPT_ENABLE_IF_SRC_A_1                    0x05
+#define     V_028C70_FORCE_OPT_ENABLE_IF_SRC_RGB_1                  0x06
+#define     V_028C70_FORCE_OPT_ENABLE_IF_SRC_ARGB_1                 0x07
+/* CIK */
+#define   S_028C70_FMASK_COMPRESSION_DISABLE(x)                       (((x) & 0x1) << 26)
+#define   G_028C70_FMASK_COMPRESSION_DISABLE(x)                       (((x) >> 26) & 0x1)
+#define   C_028C70_FMASK_COMPRESSION_DISABLE                          0xFBFFFFFF
+/*     */
+#define R_028C74_CB_COLOR0_ATTRIB                                       0x028C74
+#define   S_028C74_TILE_MODE_INDEX(x)                                 (((x) & 0x1F) << 0)
+#define   G_028C74_TILE_MODE_INDEX(x)                                 (((x) >> 0) & 0x1F)
+#define   C_028C74_TILE_MODE_INDEX                                    0xFFFFFFE0
+#define   S_028C74_FMASK_TILE_MODE_INDEX(x)                           (((x) & 0x1F) << 5)
+#define   G_028C74_FMASK_TILE_MODE_INDEX(x)                           (((x) >> 5) & 0x1F)
+#define   C_028C74_FMASK_TILE_MODE_INDEX                              0xFFFFFC1F
+#define   S_028C74_NUM_SAMPLES(x)                                     (((x) & 0x07) << 12)
+#define   G_028C74_NUM_SAMPLES(x)                                     (((x) >> 12) & 0x07)
+#define   C_028C74_NUM_SAMPLES                                        0xFFFF8FFF
+#define   S_028C74_NUM_FRAGMENTS(x)                                   (((x) & 0x03) << 15)
+#define   G_028C74_NUM_FRAGMENTS(x)                                   (((x) >> 15) & 0x03)
+#define   C_028C74_NUM_FRAGMENTS                                      0xFFFE7FFF
+#define   S_028C74_FORCE_DST_ALPHA_1(x)                               (((x) & 0x1) << 17)
+#define   G_028C74_FORCE_DST_ALPHA_1(x)                               (((x) >> 17) & 0x1)
+#define   C_028C74_FORCE_DST_ALPHA_1                                  0xFFFDFFFF
+#define R_028C7C_CB_COLOR0_CMASK                                        0x028C7C
+#define R_028C80_CB_COLOR0_CMASK_SLICE                                  0x028C80
+#define   S_028C80_TILE_MAX(x)                                        (((x) & 0x3FFF) << 0)
+#define   G_028C80_TILE_MAX(x)                                        (((x) >> 0) & 0x3FFF)
+#define   C_028C80_TILE_MAX                                           0xFFFFC000
+#define R_028C84_CB_COLOR0_FMASK                                        0x028C84
+#define R_028C88_CB_COLOR0_FMASK_SLICE                                  0x028C88
+#define   S_028C88_TILE_MAX(x)                                        (((x) & 0x3FFFFF) << 0)
+#define   G_028C88_TILE_MAX(x)                                        (((x) >> 0) & 0x3FFFFF)
+#define   C_028C88_TILE_MAX                                           0xFFC00000
+#define R_028C8C_CB_COLOR0_CLEAR_WORD0                                  0x028C8C
+#define R_028C90_CB_COLOR0_CLEAR_WORD1                                  0x028C90
+#define R_028C9C_CB_COLOR1_BASE                                         0x028C9C
+#define R_028CA0_CB_COLOR1_PITCH                                        0x028CA0
+#define R_028CA4_CB_COLOR1_SLICE                                        0x028CA4
+#define R_028CA8_CB_COLOR1_VIEW                                         0x028CA8
+#define R_028CAC_CB_COLOR1_INFO                                         0x028CAC
+#define R_028CB0_CB_COLOR1_ATTRIB                                       0x028CB0
+#define R_028CD4_CB_COLOR1_CMASK                                        0x028CB8
+#define R_028CBC_CB_COLOR1_CMASK_SLICE                                  0x028CBC
+#define R_028CC0_CB_COLOR1_FMASK                                        0x028CC0
+#define R_028CC4_CB_COLOR1_FMASK_SLICE                                  0x028CC4
+#define R_028CC8_CB_COLOR1_CLEAR_WORD0                                  0x028CC8
+#define R_028CCC_CB_COLOR1_CLEAR_WORD1                                  0x028CCC
+#define R_028CD8_CB_COLOR2_BASE                                         0x028CD8
+#define R_028CDC_CB_COLOR2_PITCH                                        0x028CDC
+#define R_028CE0_CB_COLOR2_SLICE                                        0x028CE0
+#define R_028CE4_CB_COLOR2_VIEW                                         0x028CE4
+#define R_028CE8_CB_COLOR2_INFO                                         0x028CE8
+#define R_028CEC_CB_COLOR2_ATTRIB                                       0x028CEC
+#define R_028CF4_CB_COLOR2_CMASK                                        0x028CF4
+#define R_028CF8_CB_COLOR2_CMASK_SLICE                                  0x028CF8
+#define R_028CFC_CB_COLOR2_FMASK                                        0x028CFC
+#define R_028D00_CB_COLOR2_FMASK_SLICE                                  0x028D00
+#define R_028D04_CB_COLOR2_CLEAR_WORD0                                  0x028D04
+#define R_028D08_CB_COLOR2_CLEAR_WORD1                                  0x028D08
+#define R_028D14_CB_COLOR3_BASE                                         0x028D14
+#define R_028D18_CB_COLOR3_PITCH                                        0x028D18
+#define R_028D1C_CB_COLOR3_SLICE                                        0x028D1C
+#define R_028D20_CB_COLOR3_VIEW                                         0x028D20
+#define R_028D24_CB_COLOR3_INFO                                         0x028D24
+#define R_028D28_CB_COLOR3_ATTRIB                                       0x028D28
+#define R_028D30_CB_COLOR3_CMASK                                        0x028D30
+#define R_028D34_CB_COLOR3_CMASK_SLICE                                  0x028D34
+#define R_028D38_CB_COLOR3_FMASK                                        0x028D38
+#define R_028D3C_CB_COLOR3_FMASK_SLICE                                  0x028D3C
+#define R_028D40_CB_COLOR3_CLEAR_WORD0                                  0x028D40
+#define R_028D44_CB_COLOR3_CLEAR_WORD1                                  0x028D44
+#define R_028D50_CB_COLOR4_BASE                                         0x028D50
+#define R_028D54_CB_COLOR4_PITCH                                        0x028D54
+#define R_028D58_CB_COLOR4_SLICE                                        0x028D58
+#define R_028D5C_CB_COLOR4_VIEW                                         0x028D5C
+#define R_028D60_CB_COLOR4_INFO                                         0x028D60
+#define R_028D64_CB_COLOR4_ATTRIB                                       0x028D64
+#define R_028D6C_CB_COLOR4_CMASK                                        0x028D6C
+#define R_028D70_CB_COLOR4_CMASK_SLICE                                  0x028D70
+#define R_028D74_CB_COLOR4_FMASK                                        0x028D74
+#define R_028D78_CB_COLOR4_FMASK_SLICE                                  0x028D78
+#define R_028D7C_CB_COLOR4_CLEAR_WORD0                                  0x028D7C
+#define R_028D80_CB_COLOR4_CLEAR_WORD1                                  0x028D80
+#define R_028D8C_CB_COLOR5_BASE                                         0x028D8C
+#define R_028D90_CB_COLOR5_PITCH                                        0x028D90
+#define R_028D94_CB_COLOR5_SLICE                                        0x028D94
+#define R_028D98_CB_COLOR5_VIEW                                         0x028D98
+#define R_028D9C_CB_COLOR5_INFO                                         0x028D9C
+#define R_028DA0_CB_COLOR5_ATTRIB                                       0x028DA0
+#define R_028DA8_CB_COLOR5_CMASK                                        0x028DA8
+#define R_028DAC_CB_COLOR5_CMASK_SLICE                                  0x028DAC
+#define R_028DB0_CB_COLOR5_FMASK                                        0x028DB0
+#define R_028DB4_CB_COLOR5_FMASK_SLICE                                  0x028DB4
+#define R_028DB8_CB_COLOR5_CLEAR_WORD0                                  0x028DB8
+#define R_028DBC_CB_COLOR5_CLEAR_WORD1                                  0x028DBC
+#define R_028DC8_CB_COLOR6_BASE                                         0x028DC8
+#define R_028DCC_CB_COLOR6_PITCH                                        0x028DCC
+#define R_028DD0_CB_COLOR6_SLICE                                        0x028DD0
+#define R_028DD4_CB_COLOR6_VIEW                                         0x028DD4
+#define R_028DD8_CB_COLOR6_INFO                                         0x028DD8
+#define R_028DDC_CB_COLOR6_ATTRIB                                       0x028DDC
+#define R_028DE4_CB_COLOR6_CMASK                                        0x028DE4
+#define R_028DE8_CB_COLOR6_CMASK_SLICE                                  0x028DE8
+#define R_028DEC_CB_COLOR6_FMASK                                        0x028DEC
+#define R_028DF0_CB_COLOR6_FMASK_SLICE                                  0x028DF0
+#define R_028DF4_CB_COLOR6_CLEAR_WORD0                                  0x028DF4
+#define R_028DF8_CB_COLOR6_CLEAR_WORD1                                  0x028DF8
+#define R_028E04_CB_COLOR7_BASE                                         0x028E04
+#define R_028E08_CB_COLOR7_PITCH                                        0x028E08
+#define R_028E0C_CB_COLOR7_SLICE                                        0x028E0C
+#define R_028E10_CB_COLOR7_VIEW                                         0x028E10
+#define R_028E14_CB_COLOR7_INFO                                         0x028E14
+#define R_028E18_CB_COLOR7_ATTRIB                                       0x028E18
+#define R_028E20_CB_COLOR7_CMASK                                        0x028E20
+#define R_028E24_CB_COLOR7_CMASK_SLICE                                  0x028E24
+#define R_028E28_CB_COLOR7_FMASK                                        0x028E28
+#define R_028E2C_CB_COLOR7_FMASK_SLICE                                  0x028E2C
+#define R_028E30_CB_COLOR7_CLEAR_WORD0                                  0x028E30
+#define R_028E34_CB_COLOR7_CLEAR_WORD1                                  0x028E34
+#endif /* _SID_H */

Subversion Repositories Kolibri OS

Compare Revisions

Regard whitespace Rev 4357 → Rev 4358