| /contrib/sdk/sources/Mesa/mesa-9.2.5/src/gallium/drivers/radeon/LLVM_REVISION.txt |
|---|
| 0,0 → 1,0 |
| @181269 |
| /contrib/sdk/sources/Mesa/mesa-9.2.5/src/gallium/drivers/radeon/Makefile.am |
|---|
| 0,0 → 1,38 |
| include Makefile.sources |
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| $(C_SOURCES) |
| if NEED_RADEON_LLVM |
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| $(LLVM_LDFLAGS) |
| noinst_LTLIBRARIES += libllvmradeon.la |
| libllvmradeon_la_CXXFLAGS = \ |
| $(GALLIUM_CFLAGS) \ |
| $(DEFINES) |
| libllvmradeon_la_CFLAGS = \ |
| $(GALLIUM_CFLAGS) \ |
| $(LLVM_CFLAGS) |
| libllvmradeon_la_SOURCES = \ |
| $(LLVM_CPP_FILES) \ |
| $(LLVM_C_FILES) |
| libllvmradeon_la_LIBADD = \ |
| $(LIBGALLIUM_LIBS) \ |
| $(CLOCK_LIB) \ |
| $(LLVM_LIBS) \ |
| $(ELF_LIB) |
| endif |
| /contrib/sdk/sources/Mesa/mesa-9.2.5/src/gallium/drivers/radeon/Makefile.in |
|---|
| 0,0 → 1,832 |
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| # Copyright (C) 1994-2013 Free Software Foundation, Inc. |
| # This Makefile.in is free software; the Free Software Foundation |
| # gives unlimited permission to copy and/or distribute it, |
| # with or without modifications, as long as this notice is preserved. |
| # This program is distributed in the hope that it will be useful, |
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| ac_ct_DUMPBIN = @ac_ct_DUMPBIN@ |
| am__include = @am__include@ |
| am__leading_dot = @am__leading_dot@ |
| am__quote = @am__quote@ |
| am__tar = @am__tar@ |
| am__untar = @am__untar@ |
| ax_pthread_config = @ax_pthread_config@ |
| bindir = @bindir@ |
| build = @build@ |
| build_alias = @build_alias@ |
| build_cpu = @build_cpu@ |
| build_os = @build_os@ |
| build_vendor = @build_vendor@ |
| builddir = @builddir@ |
| datadir = @datadir@ |
| datarootdir = @datarootdir@ |
| docdir = @docdir@ |
| dvidir = @dvidir@ |
| exec_prefix = @exec_prefix@ |
| host = @host@ |
| host_alias = @host_alias@ |
| host_cpu = @host_cpu@ |
| host_os = @host_os@ |
| host_vendor = @host_vendor@ |
| htmldir = @htmldir@ |
| includedir = @includedir@ |
| infodir = @infodir@ |
| install_sh = @install_sh@ |
| libdir = @libdir@ |
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| top_srcdir = @top_srcdir@ |
| C_SOURCES := \ |
| radeon_uvd.c |
| LLVM_C_FILES := \ |
| radeon_setup_tgsi_llvm.c \ |
| radeon_llvm_emit.c \ |
| radeon_llvm_util.c |
| GALLIUM_CFLAGS = \ |
| -I$(top_srcdir)/include \ |
| -I$(top_srcdir)/src/gallium/include \ |
| -I$(top_srcdir)/src/gallium/auxiliary \ |
| $(DEFINES) |
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| @NEED_RADEON_LLVM_TRUE@ $(LLVM_LDFLAGS) |
| @NEED_RADEON_LLVM_TRUE@libllvmradeon_la_CXXFLAGS = \ |
| @NEED_RADEON_LLVM_TRUE@ $(GALLIUM_CFLAGS) \ |
| @NEED_RADEON_LLVM_TRUE@ $(DEFINES) |
| @NEED_RADEON_LLVM_TRUE@libllvmradeon_la_CFLAGS = \ |
| @NEED_RADEON_LLVM_TRUE@ $(GALLIUM_CFLAGS) \ |
| @NEED_RADEON_LLVM_TRUE@ $(LLVM_CFLAGS) |
| @NEED_RADEON_LLVM_TRUE@libllvmradeon_la_SOURCES = \ |
| @NEED_RADEON_LLVM_TRUE@ $(LLVM_CPP_FILES) \ |
| @NEED_RADEON_LLVM_TRUE@ $(LLVM_C_FILES) |
| @NEED_RADEON_LLVM_TRUE@libllvmradeon_la_LIBADD = \ |
| @NEED_RADEON_LLVM_TRUE@ $(LIBGALLIUM_LIBS) \ |
| @NEED_RADEON_LLVM_TRUE@ $(CLOCK_LIB) \ |
| @NEED_RADEON_LLVM_TRUE@ $(LLVM_LIBS) \ |
| @NEED_RADEON_LLVM_TRUE@ $(ELF_LIB) |
| all: all-am |
| .SUFFIXES: |
| .SUFFIXES: .c .lo .o .obj |
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| @for dep in $?; do \ |
| case '$(am__configure_deps)' in \ |
| *$$dep*) \ |
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| exit 1;; \ |
| esac; \ |
| done; \ |
| echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign src/gallium/drivers/radeon/Makefile'; \ |
| $(am__cd) $(top_srcdir) && \ |
| $(AUTOMAKE) --foreign src/gallium/drivers/radeon/Makefile |
| .PRECIOUS: Makefile |
| Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status |
| @case '$?' in \ |
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| /contrib/sdk/sources/Mesa/mesa-9.2.5/src/gallium/drivers/radeon/Makefile.sources |
|---|
| 0,0 → 1,7 |
| C_SOURCES := \ |
| radeon_uvd.c |
| LLVM_C_FILES := \ |
| radeon_setup_tgsi_llvm.c \ |
| radeon_llvm_emit.c \ |
| radeon_llvm_util.c |
| /contrib/sdk/sources/Mesa/mesa-9.2.5/src/gallium/drivers/radeon/radeon_llvm.h |
|---|
| 0,0 → 1,201 |
| /* |
| * Copyright 2011 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| * SOFTWARE. |
| * |
| * Authors: Tom Stellard <thomas.stellard@amd.com> |
| * |
| */ |
| #ifndef RADEON_LLVM_H |
| #define RADEON_LLVM_H |
| #include <llvm-c/Core.h> |
| #include "gallivm/lp_bld_init.h" |
| #include "gallivm/lp_bld_tgsi.h" |
| #define RADEON_LLVM_MAX_INPUTS 32 * 4 |
| #define RADEON_LLVM_MAX_OUTPUTS 32 * 4 |
| #define RADEON_LLVM_MAX_BRANCH_DEPTH 16 |
| #define RADEON_LLVM_MAX_LOOP_DEPTH 16 |
| #define RADEON_LLVM_MAX_ARRAYS 16 |
| #define RADEON_LLVM_MAX_SYSTEM_VALUES 4 |
| struct radeon_llvm_branch { |
| LLVMBasicBlockRef endif_block; |
| LLVMBasicBlockRef if_block; |
| LLVMBasicBlockRef else_block; |
| unsigned has_else; |
| }; |
| struct radeon_llvm_loop { |
| LLVMBasicBlockRef loop_block; |
| LLVMBasicBlockRef endloop_block; |
| }; |
| struct radeon_llvm_context { |
| struct lp_build_tgsi_soa_context soa; |
| unsigned chip_class; |
| unsigned type; |
| unsigned face_gpr; |
| unsigned two_side; |
| unsigned clip_vertex; |
| struct r600_shader_io * r600_inputs; |
| struct r600_shader_io * r600_outputs; |
| struct pipe_stream_output_info *stream_outputs; |
| unsigned color_buffer_count; |
| unsigned fs_color_all; |
| unsigned alpha_to_one; |
| unsigned has_txq_cube_array_z_comp; |
| /*=== Front end configuration ===*/ |
| /* Special Intrinsics */ |
| /** Write to an output register: float store_output(float, i32) */ |
| const char * store_output_intr; |
| /** Swizzle a vector value: <4 x float> swizzle(<4 x float>, i32) |
| * The swizzle is an unsigned integer that encodes a TGSI_SWIZZLE_* value |
| * in 2-bits. |
| * Swizzle{0-1} = X Channel |
| * Swizzle{2-3} = Y Channel |
| * Swizzle{4-5} = Z Channel |
| * Swizzle{6-7} = W Channel |
| */ |
| const char * swizzle_intr; |
| /* Instructions that are not described by any of the TGSI opcodes. */ |
| /** This function is responsible for initilizing the inputs array and will be |
| * called once for each input declared in the TGSI shader. |
| */ |
| void (*load_input)(struct radeon_llvm_context *, |
| unsigned input_index, |
| const struct tgsi_full_declaration *decl); |
| void (*load_system_value)(struct radeon_llvm_context *, |
| unsigned index, |
| const struct tgsi_full_declaration *decl); |
| /** User data to use with the callbacks */ |
| void * userdata; |
| /** This array contains the input values for the shader. Typically these |
| * values will be in the form of a target intrinsic that will inform the |
| * backend how to load the actual inputs to the shader. |
| */ |
| LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS]; |
| LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS][TGSI_NUM_CHANNELS]; |
| unsigned output_reg_count; |
| LLVMValueRef system_values[RADEON_LLVM_MAX_SYSTEM_VALUES]; |
| /*=== Private Members ===*/ |
| struct radeon_llvm_branch branch[RADEON_LLVM_MAX_BRANCH_DEPTH]; |
| struct radeon_llvm_loop loop[RADEON_LLVM_MAX_LOOP_DEPTH]; |
| unsigned branch_depth; |
| unsigned loop_depth; |
| struct tgsi_declaration_range arrays[RADEON_LLVM_MAX_ARRAYS]; |
| unsigned num_arrays; |
| LLVMValueRef main_fn; |
| struct gallivm_state gallivm; |
| }; |
| static inline LLVMTypeRef tgsi2llvmtype( |
| struct lp_build_tgsi_context * bld_base, |
| enum tgsi_opcode_type type) |
| { |
| LLVMContextRef ctx = bld_base->base.gallivm->context; |
| switch (type) { |
| case TGSI_TYPE_UNSIGNED: |
| case TGSI_TYPE_SIGNED: |
| return LLVMInt32TypeInContext(ctx); |
| case TGSI_TYPE_UNTYPED: |
| case TGSI_TYPE_FLOAT: |
| return LLVMFloatTypeInContext(ctx); |
| default: break; |
| } |
| return 0; |
| } |
| static inline LLVMValueRef bitcast( |
| struct lp_build_tgsi_context * bld_base, |
| enum tgsi_opcode_type type, |
| LLVMValueRef value |
| ) |
| { |
| LLVMBuilderRef builder = bld_base->base.gallivm->builder; |
| LLVMTypeRef dst_type = tgsi2llvmtype(bld_base, type); |
| if (dst_type) |
| return LLVMBuildBitCast(builder, value, dst_type, ""); |
| else |
| return value; |
| } |
| void radeon_llvm_emit_prepare_cube_coords(struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data, |
| LLVMValueRef *coords_arg); |
| void radeon_llvm_context_init(struct radeon_llvm_context * ctx); |
| void radeon_llvm_create_func(struct radeon_llvm_context * ctx, |
| LLVMTypeRef *ParamTypes, unsigned ParamCount); |
| void radeon_llvm_dispose(struct radeon_llvm_context * ctx); |
| inline static struct radeon_llvm_context * radeon_llvm_context( |
| struct lp_build_tgsi_context * bld_base) |
| { |
| return (struct radeon_llvm_context*)bld_base; |
| } |
| unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan); |
| void radeon_llvm_finalize_module(struct radeon_llvm_context * ctx); |
| LLVMValueRef |
| build_intrinsic(LLVMBuilderRef builder, |
| const char *name, |
| LLVMTypeRef ret_type, |
| LLVMValueRef *args, |
| unsigned num_args, |
| LLVMAttribute attr); |
| void |
| build_tgsi_intrinsic_nomem( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data); |
| #endif /* RADEON_LLVM_H */ |
| /contrib/sdk/sources/Mesa/mesa-9.2.5/src/gallium/drivers/radeon/radeon_llvm_emit.c |
|---|
| 0,0 → 1,172 |
| /* |
| * Copyright 2011 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| * SOFTWARE. |
| * |
| * Authors: Tom Stellard <thomas.stellard@amd.com> |
| * |
| */ |
| #include "radeon_llvm_emit.h" |
| #include "util/u_memory.h" |
| #include <llvm-c/Target.h> |
| #include <llvm-c/TargetMachine.h> |
| #include <stdlib.h> |
| #include <stdio.h> |
| #include <string.h> |
| #include <libelf.h> |
| #include <gelf.h> |
| #define CPU_STRING_LEN 30 |
| #define FS_STRING_LEN 30 |
| #define TRIPLE_STRING_LEN 7 |
| /** |
| * Set the shader type we want to compile |
| * |
| * @param type shader type to set |
| */ |
| void radeon_llvm_shader_type(LLVMValueRef F, unsigned type) |
| { |
| char Str[2]; |
| sprintf(Str, "%1d", type); |
| LLVMAddTargetDependentFunctionAttr(F, "ShaderType", Str); |
| } |
| static void init_r600_target() { |
| static unsigned initialized = 0; |
| if (!initialized) { |
| LLVMInitializeR600TargetInfo(); |
| LLVMInitializeR600Target(); |
| LLVMInitializeR600TargetMC(); |
| LLVMInitializeR600AsmPrinter(); |
| initialized = 1; |
| } |
| } |
| static LLVMTargetRef get_r600_target() { |
| LLVMTargetRef target = NULL; |
| for (target = LLVMGetFirstTarget(); target; |
| target = LLVMGetNextTarget(target)) { |
| if (!strncmp(LLVMGetTargetName(target), "r600", 4)) { |
| break; |
| } |
| } |
| if (!target) { |
| fprintf(stderr, "Can't find target r600\n"); |
| return NULL; |
| } |
| return target; |
| } |
| /** |
| * Compile an LLVM module to machine code. |
| * |
| * @returns 0 for success, 1 for failure |
| */ |
| unsigned radeon_llvm_compile(LLVMModuleRef M, struct radeon_llvm_binary *binary, |
| const char * gpu_family, unsigned dump) { |
| LLVMTargetRef target; |
| LLVMTargetMachineRef tm; |
| char cpu[CPU_STRING_LEN]; |
| char fs[FS_STRING_LEN]; |
| char *err; |
| LLVMMemoryBufferRef out_buffer; |
| unsigned buffer_size; |
| const char *buffer_data; |
| char triple[TRIPLE_STRING_LEN]; |
| char *elf_buffer; |
| Elf *elf; |
| Elf_Scn *section = NULL; |
| size_t section_str_index; |
| LLVMBool r; |
| init_r600_target(); |
| target = get_r600_target(); |
| if (!target) { |
| return 1; |
| } |
| strncpy(cpu, gpu_family, CPU_STRING_LEN); |
| memset(fs, 0, sizeof(fs)); |
| if (dump) { |
| LLVMDumpModule(M); |
| strncpy(fs, "+DumpCode", FS_STRING_LEN); |
| } |
| strncpy(triple, "r600--", TRIPLE_STRING_LEN); |
| tm = LLVMCreateTargetMachine(target, triple, cpu, fs, |
| LLVMCodeGenLevelDefault, LLVMRelocDefault, |
| LLVMCodeModelDefault); |
| r = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile, &err, |
| &out_buffer); |
| if (r) { |
| fprintf(stderr, "%s", err); |
| FREE(err); |
| return 1; |
| } |
| buffer_size = LLVMGetBufferSize(out_buffer); |
| buffer_data = LLVMGetBufferStart(out_buffer); |
| /* One of the libelf implementations |
| * (http://www.mr511.de/software/english.htm) requires calling |
| * elf_version() before elf_memory(). |
| */ |
| elf_version(EV_CURRENT); |
| elf_buffer = MALLOC(buffer_size); |
| memcpy(elf_buffer, buffer_data, buffer_size); |
| elf = elf_memory(elf_buffer, buffer_size); |
| elf_getshdrstrndx(elf, §ion_str_index); |
| while ((section = elf_nextscn(elf, section))) { |
| const char *name; |
| Elf_Data *section_data = NULL; |
| GElf_Shdr section_header; |
| if (gelf_getshdr(section, §ion_header) != §ion_header) { |
| fprintf(stderr, "Failed to read ELF section header\n"); |
| return 1; |
| } |
| name = elf_strptr(elf, section_str_index, section_header.sh_name); |
| if (!strcmp(name, ".text")) { |
| section_data = elf_getdata(section, section_data); |
| binary->code_size = section_data->d_size; |
| binary->code = MALLOC(binary->code_size * sizeof(unsigned char)); |
| memcpy(binary->code, section_data->d_buf, binary->code_size); |
| } else if (!strcmp(name, ".AMDGPU.config")) { |
| section_data = elf_getdata(section, section_data); |
| binary->config_size = section_data->d_size; |
| binary->config = MALLOC(binary->config_size * sizeof(unsigned char)); |
| memcpy(binary->config, section_data->d_buf, binary->config_size); |
| } |
| } |
| LLVMDisposeMemoryBuffer(out_buffer); |
| LLVMDisposeTargetMachine(tm); |
| return 0; |
| } |
| /contrib/sdk/sources/Mesa/mesa-9.2.5/src/gallium/drivers/radeon/radeon_llvm_emit.h |
|---|
| 0,0 → 1,47 |
| /* |
| * Copyright 2012 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| * SOFTWARE. |
| * |
| * Authors: Tom Stellard <thomas.stellard@amd.com> |
| * |
| */ |
| #ifndef RADEON_LLVM_EMIT_H |
| #define RADEON_LLVM_EMIT_H |
| #include <llvm-c/Core.h> |
| struct radeon_llvm_binary { |
| unsigned char *code; |
| unsigned code_size; |
| unsigned char *config; |
| unsigned config_size; |
| }; |
| void radeon_llvm_shader_type(LLVMValueRef F, unsigned type); |
| unsigned radeon_llvm_compile( |
| LLVMModuleRef M, |
| struct radeon_llvm_binary *binary, |
| const char * gpu_family, |
| unsigned dump); |
| #endif /* RADEON_LLVM_EMIT_H */ |
| /contrib/sdk/sources/Mesa/mesa-9.2.5/src/gallium/drivers/radeon/radeon_llvm_util.c |
|---|
| 0,0 → 1,91 |
| /* |
| * Copyright 2012, 2013 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| * SOFTWARE. |
| * |
| * Authors: Tom Stellard <thomas.stellard@amd.com> |
| * |
| */ |
| #include "radeon_llvm_util.h" |
| #include "util/u_memory.h" |
| #include <llvm-c/BitReader.h> |
| #include <llvm-c/Core.h> |
| #include <llvm-c/Transforms/PassManagerBuilder.h> |
| LLVMModuleRef radeon_llvm_parse_bitcode(const unsigned char * bitcode, |
| unsigned bitcode_len) |
| { |
| LLVMMemoryBufferRef buf; |
| LLVMContextRef ctx = LLVMContextCreate(); |
| LLVMModuleRef module; |
| buf = LLVMCreateMemoryBufferWithMemoryRangeCopy((const char*)bitcode, |
| bitcode_len, "radeon"); |
| LLVMParseBitcodeInContext(ctx, buf, &module, NULL); |
| return module; |
| } |
| unsigned radeon_llvm_get_num_kernels(const unsigned char *bitcode, |
| unsigned bitcode_len) |
| { |
| LLVMModuleRef mod = radeon_llvm_parse_bitcode(bitcode, bitcode_len); |
| return LLVMGetNamedMetadataNumOperands(mod, "opencl.kernels"); |
| } |
| static void radeon_llvm_optimize(LLVMModuleRef mod) |
| { |
| LLVMPassManagerBuilderRef builder = LLVMPassManagerBuilderCreate(); |
| LLVMPassManagerRef pass_manager = LLVMCreatePassManager(); |
| LLVMPassManagerBuilderUseInlinerWithThreshold(builder, 1000000000); |
| LLVMPassManagerBuilderPopulateModulePassManager(builder, pass_manager); |
| LLVMRunPassManager(pass_manager, mod); |
| LLVMPassManagerBuilderDispose(builder); |
| LLVMDisposePassManager(pass_manager); |
| } |
| LLVMModuleRef radeon_llvm_get_kernel_module(unsigned index, |
| const unsigned char *bitcode, unsigned bitcode_len) |
| { |
| LLVMModuleRef mod; |
| unsigned num_kernels; |
| LLVMValueRef *kernel_metadata; |
| unsigned i; |
| mod = radeon_llvm_parse_bitcode(bitcode, bitcode_len); |
| num_kernels = LLVMGetNamedMetadataNumOperands(mod, "opencl.kernels"); |
| kernel_metadata = MALLOC(num_kernels * sizeof(LLVMValueRef)); |
| LLVMGetNamedMetadataOperands(mod, "opencl.kernels", kernel_metadata); |
| for (i = 0; i < num_kernels; i++) { |
| LLVMValueRef kernel_signature, kernel_function; |
| if (i == index) { |
| continue; |
| } |
| kernel_signature = kernel_metadata[i]; |
| LLVMGetMDNodeOperands(kernel_signature, &kernel_function); |
| LLVMDeleteFunction(kernel_function); |
| } |
| FREE(kernel_metadata); |
| radeon_llvm_optimize(mod); |
| return mod; |
| } |
| /contrib/sdk/sources/Mesa/mesa-9.2.5/src/gallium/drivers/radeon/radeon_llvm_util.h |
|---|
| 0,0 → 1,38 |
| /* |
| * Copyright 2012, 2013 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| * SOFTWARE. |
| * |
| * Authors: Tom Stellard <thomas.stellard@amd.com> |
| * |
| */ |
| #ifndef RADEON_LLVM_UTIL_H |
| #define RADEON_LLVM_UTIL_H |
| #include <llvm-c/Core.h> |
| LLVMModuleRef radeon_llvm_parse_bitcode(const unsigned char * bitcode, |
| unsigned bitcode_len); |
| unsigned radeon_llvm_get_num_kernels(const unsigned char *bitcode, unsigned bitcode_len); |
| LLVMModuleRef radeon_llvm_get_kernel_module(unsigned index, |
| const unsigned char *bitcode, unsigned bitcode_len); |
| #endif |
| /contrib/sdk/sources/Mesa/mesa-9.2.5/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c |
|---|
| 0,0 → 1,1367 |
| /* |
| * Copyright 2011 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| * SOFTWARE. |
| * |
| * Authors: Tom Stellard <thomas.stellard@amd.com> |
| * |
| */ |
| #include "radeon_llvm.h" |
| #include "gallivm/lp_bld_const.h" |
| #include "gallivm/lp_bld_gather.h" |
| #include "gallivm/lp_bld_flow.h" |
| #include "gallivm/lp_bld_init.h" |
| #include "gallivm/lp_bld_intr.h" |
| #include "gallivm/lp_bld_swizzle.h" |
| #include "tgsi/tgsi_info.h" |
| #include "tgsi/tgsi_parse.h" |
| #include "util/u_math.h" |
| #include "util/u_memory.h" |
| #include "util/u_debug.h" |
| #include <llvm-c/Core.h> |
| #include <llvm-c/Transforms/Scalar.h> |
| static struct radeon_llvm_loop * get_current_loop(struct radeon_llvm_context * ctx) |
| { |
| return ctx->loop_depth > 0 ? ctx->loop + (ctx->loop_depth - 1) : NULL; |
| } |
| static struct radeon_llvm_branch * get_current_branch( |
| struct radeon_llvm_context * ctx) |
| { |
| return ctx->branch_depth > 0 ? |
| ctx->branch + (ctx->branch_depth - 1) : NULL; |
| } |
| unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan) |
| { |
| return (index * 4) + chan; |
| } |
| static LLVMValueRef emit_swizzle( |
| struct lp_build_tgsi_context * bld_base, |
| LLVMValueRef value, |
| unsigned swizzle_x, |
| unsigned swizzle_y, |
| unsigned swizzle_z, |
| unsigned swizzle_w) |
| { |
| LLVMValueRef swizzles[4]; |
| LLVMTypeRef i32t = |
| LLVMInt32TypeInContext(bld_base->base.gallivm->context); |
| swizzles[0] = LLVMConstInt(i32t, swizzle_x, 0); |
| swizzles[1] = LLVMConstInt(i32t, swizzle_y, 0); |
| swizzles[2] = LLVMConstInt(i32t, swizzle_z, 0); |
| swizzles[3] = LLVMConstInt(i32t, swizzle_w, 0); |
| return LLVMBuildShuffleVector(bld_base->base.gallivm->builder, |
| value, |
| LLVMGetUndef(LLVMTypeOf(value)), |
| LLVMConstVector(swizzles, 4), ""); |
| } |
| static struct tgsi_declaration_range |
| get_array_range(struct lp_build_tgsi_context *bld_base, |
| unsigned File, const struct tgsi_ind_register *reg) |
| { |
| struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); |
| if (File != TGSI_FILE_TEMPORARY || reg->ArrayID == 0 || |
| reg->ArrayID > RADEON_LLVM_MAX_ARRAYS) { |
| struct tgsi_declaration_range range; |
| range.First = 0; |
| range.Last = bld_base->info->file_max[File]; |
| return range; |
| } |
| return ctx->arrays[reg->ArrayID - 1]; |
| } |
| static LLVMValueRef |
| emit_array_index( |
| struct lp_build_tgsi_soa_context *bld, |
| const struct tgsi_ind_register *reg, |
| unsigned offset) |
| { |
| struct gallivm_state * gallivm = bld->bld_base.base.gallivm; |
| LLVMValueRef addr = LLVMBuildLoad(gallivm->builder, bld->addr[reg->Index][reg->Swizzle], ""); |
| return LLVMBuildAdd(gallivm->builder, addr, lp_build_const_int32(gallivm, offset), ""); |
| } |
| static LLVMValueRef |
| emit_fetch( |
| struct lp_build_tgsi_context *bld_base, |
| const struct tgsi_full_src_register *reg, |
| enum tgsi_opcode_type type, |
| unsigned swizzle); |
| static LLVMValueRef |
| emit_array_fetch( |
| struct lp_build_tgsi_context *bld_base, |
| unsigned File, enum tgsi_opcode_type type, |
| struct tgsi_declaration_range range, |
| unsigned swizzle) |
| { |
| struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base); |
| struct gallivm_state * gallivm = bld->bld_base.base.gallivm; |
| LLVMBuilderRef builder = bld_base->base.gallivm->builder; |
| unsigned i, size = range.Last - range.First + 1; |
| LLVMTypeRef vec = LLVMVectorType(tgsi2llvmtype(bld_base, type), size); |
| LLVMValueRef result = LLVMGetUndef(vec); |
| struct tgsi_full_src_register tmp_reg = {}; |
| tmp_reg.Register.File = File; |
| for (i = 0; i < size; ++i) { |
| tmp_reg.Register.Index = i + range.First; |
| LLVMValueRef temp = emit_fetch(bld_base, &tmp_reg, type, swizzle); |
| result = LLVMBuildInsertElement(builder, result, temp, |
| lp_build_const_int32(gallivm, i), ""); |
| } |
| return result; |
| } |
| static LLVMValueRef |
| emit_fetch( |
| struct lp_build_tgsi_context *bld_base, |
| const struct tgsi_full_src_register *reg, |
| enum tgsi_opcode_type type, |
| unsigned swizzle) |
| { |
| struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); |
| struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base); |
| LLVMBuilderRef builder = bld_base->base.gallivm->builder; |
| LLVMValueRef result, ptr; |
| if (swizzle == ~0) { |
| LLVMValueRef values[TGSI_NUM_CHANNELS]; |
| unsigned chan; |
| for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) { |
| values[chan] = emit_fetch(bld_base, reg, type, chan); |
| } |
| return lp_build_gather_values(bld_base->base.gallivm, values, |
| TGSI_NUM_CHANNELS); |
| } |
| if (reg->Register.Indirect) { |
| struct tgsi_declaration_range range = get_array_range(bld_base, |
| reg->Register.File, ®->Indirect); |
| return LLVMBuildExtractElement(builder, |
| emit_array_fetch(bld_base, reg->Register.File, type, range, swizzle), |
| emit_array_index(bld, ®->Indirect, reg->Register.Index - range.First), |
| ""); |
| } |
| switch(reg->Register.File) { |
| case TGSI_FILE_IMMEDIATE: { |
| LLVMTypeRef ctype = tgsi2llvmtype(bld_base, type); |
| return LLVMConstBitCast(bld->immediates[reg->Register.Index][swizzle], ctype); |
| } |
| case TGSI_FILE_INPUT: |
| result = ctx->inputs[radeon_llvm_reg_index_soa(reg->Register.Index, swizzle)]; |
| break; |
| case TGSI_FILE_TEMPORARY: |
| ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index, swizzle); |
| result = LLVMBuildLoad(builder, ptr, ""); |
| break; |
| case TGSI_FILE_OUTPUT: |
| ptr = lp_get_output_ptr(bld, reg->Register.Index, swizzle); |
| result = LLVMBuildLoad(builder, ptr, ""); |
| break; |
| default: |
| return LLVMGetUndef(tgsi2llvmtype(bld_base, type)); |
| } |
| return bitcast(bld_base, type, result); |
| } |
| static LLVMValueRef fetch_system_value( |
| struct lp_build_tgsi_context * bld_base, |
| const struct tgsi_full_src_register *reg, |
| enum tgsi_opcode_type type, |
| unsigned swizzle) |
| { |
| struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); |
| LLVMValueRef cval = ctx->system_values[reg->Register.Index]; |
| return bitcast(bld_base, type, cval); |
| } |
| static void emit_declaration( |
| struct lp_build_tgsi_context * bld_base, |
| const struct tgsi_full_declaration *decl) |
| { |
| struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); |
| switch(decl->Declaration.File) { |
| case TGSI_FILE_ADDRESS: |
| { |
| unsigned idx; |
| for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) { |
| unsigned chan; |
| for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) { |
| ctx->soa.addr[idx][chan] = lp_build_alloca( |
| &ctx->gallivm, |
| ctx->soa.bld_base.uint_bld.elem_type, ""); |
| } |
| } |
| break; |
| } |
| case TGSI_FILE_TEMPORARY: |
| if (decl->Declaration.Array && decl->Array.ArrayID <= RADEON_LLVM_MAX_ARRAYS) |
| ctx->arrays[decl->Array.ArrayID - 1] = decl->Range; |
| lp_emit_declaration_soa(bld_base, decl); |
| break; |
| case TGSI_FILE_INPUT: |
| { |
| unsigned idx; |
| for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) { |
| ctx->load_input(ctx, idx, decl); |
| } |
| } |
| break; |
| case TGSI_FILE_SYSTEM_VALUE: |
| { |
| unsigned idx; |
| for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) { |
| ctx->load_system_value(ctx, idx, decl); |
| } |
| } |
| break; |
| case TGSI_FILE_OUTPUT: |
| { |
| unsigned idx; |
| for (idx = decl->Range.First; idx <= decl->Range.Last; idx++) { |
| unsigned chan; |
| assert(idx < RADEON_LLVM_MAX_OUTPUTS); |
| for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) { |
| ctx->soa.outputs[idx][chan] = lp_build_alloca(&ctx->gallivm, |
| ctx->soa.bld_base.base.elem_type, ""); |
| } |
| } |
| ctx->output_reg_count = MAX2(ctx->output_reg_count, |
| decl->Range.Last + 1); |
| break; |
| } |
| default: |
| break; |
| } |
| } |
| static void |
| emit_store( |
| struct lp_build_tgsi_context * bld_base, |
| const struct tgsi_full_instruction * inst, |
| const struct tgsi_opcode_info * info, |
| LLVMValueRef dst[4]) |
| { |
| struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base); |
| struct gallivm_state *gallivm = bld->bld_base.base.gallivm; |
| struct lp_build_context base = bld->bld_base.base; |
| const struct tgsi_full_dst_register *reg = &inst->Dst[0]; |
| LLVMBuilderRef builder = bld->bld_base.base.gallivm->builder; |
| LLVMValueRef temp_ptr; |
| unsigned chan, chan_index; |
| boolean is_vec_store = FALSE; |
| if (dst[0]) { |
| LLVMTypeKind k = LLVMGetTypeKind(LLVMTypeOf(dst[0])); |
| is_vec_store = (k == LLVMVectorTypeKind); |
| } |
| if (is_vec_store) { |
| LLVMValueRef values[4] = {}; |
| TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan) { |
| LLVMValueRef index = lp_build_const_int32(gallivm, chan); |
| values[chan] = LLVMBuildExtractElement(gallivm->builder, |
| dst[0], index, ""); |
| } |
| bld_base->emit_store(bld_base, inst, info, values); |
| return; |
| } |
| TGSI_FOR_EACH_DST0_ENABLED_CHANNEL( inst, chan_index ) { |
| LLVMValueRef value = dst[chan_index]; |
| if (inst->Instruction.Saturate != TGSI_SAT_NONE) { |
| struct lp_build_emit_data clamp_emit_data; |
| memset(&clamp_emit_data, 0, sizeof(clamp_emit_data)); |
| clamp_emit_data.arg_count = 3; |
| clamp_emit_data.args[0] = value; |
| clamp_emit_data.args[2] = base.one; |
| switch(inst->Instruction.Saturate) { |
| case TGSI_SAT_ZERO_ONE: |
| clamp_emit_data.args[1] = base.zero; |
| break; |
| case TGSI_SAT_MINUS_PLUS_ONE: |
| clamp_emit_data.args[1] = LLVMConstReal( |
| base.elem_type, -1.0f); |
| break; |
| default: |
| assert(0); |
| } |
| value = lp_build_emit_llvm(bld_base, TGSI_OPCODE_CLAMP, |
| &clamp_emit_data); |
| } |
| if (reg->Register.File == TGSI_FILE_ADDRESS) { |
| temp_ptr = bld->addr[reg->Register.Index][chan_index]; |
| LLVMBuildStore(builder, value, temp_ptr); |
| continue; |
| } |
| value = bitcast(bld_base, TGSI_TYPE_FLOAT, value); |
| if (reg->Register.Indirect) { |
| struct tgsi_declaration_range range = get_array_range(bld_base, |
| reg->Register.File, ®->Indirect); |
| unsigned i, size = range.Last - range.First + 1; |
| LLVMValueRef array = LLVMBuildInsertElement(builder, |
| emit_array_fetch(bld_base, reg->Register.File, TGSI_TYPE_FLOAT, range, chan_index), |
| value, emit_array_index(bld, ®->Indirect, reg->Register.Index - range.First), ""); |
| for (i = 0; i < size; ++i) { |
| switch(reg->Register.File) { |
| case TGSI_FILE_OUTPUT: |
| temp_ptr = bld->outputs[i + range.First][chan_index]; |
| break; |
| case TGSI_FILE_TEMPORARY: |
| temp_ptr = lp_get_temp_ptr_soa(bld, i + range.First, chan_index); |
| break; |
| default: |
| return; |
| } |
| value = LLVMBuildExtractElement(builder, array, |
| lp_build_const_int32(gallivm, i), ""); |
| LLVMBuildStore(builder, value, temp_ptr); |
| } |
| } else { |
| switch(reg->Register.File) { |
| case TGSI_FILE_OUTPUT: |
| temp_ptr = bld->outputs[reg->Register.Index][chan_index]; |
| break; |
| case TGSI_FILE_TEMPORARY: |
| temp_ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index, chan_index); |
| break; |
| default: |
| return; |
| } |
| LLVMBuildStore(builder, value, temp_ptr); |
| } |
| } |
| } |
| static void bgnloop_emit( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); |
| struct gallivm_state * gallivm = bld_base->base.gallivm; |
| LLVMBasicBlockRef loop_block; |
| LLVMBasicBlockRef endloop_block; |
| endloop_block = LLVMAppendBasicBlockInContext(gallivm->context, |
| ctx->main_fn, "ENDLOOP"); |
| loop_block = LLVMInsertBasicBlockInContext(gallivm->context, |
| endloop_block, "LOOP"); |
| LLVMBuildBr(gallivm->builder, loop_block); |
| LLVMPositionBuilderAtEnd(gallivm->builder, loop_block); |
| ctx->loop_depth++; |
| ctx->loop[ctx->loop_depth - 1].loop_block = loop_block; |
| ctx->loop[ctx->loop_depth - 1].endloop_block = endloop_block; |
| } |
| static void brk_emit( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); |
| struct gallivm_state * gallivm = bld_base->base.gallivm; |
| struct radeon_llvm_loop * current_loop = get_current_loop(ctx); |
| LLVMBuildBr(gallivm->builder, current_loop->endloop_block); |
| } |
| static void cont_emit( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); |
| struct gallivm_state * gallivm = bld_base->base.gallivm; |
| struct radeon_llvm_loop * current_loop = get_current_loop(ctx); |
| LLVMBuildBr(gallivm->builder, current_loop->loop_block); |
| } |
| static void else_emit( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); |
| struct gallivm_state * gallivm = bld_base->base.gallivm; |
| struct radeon_llvm_branch * current_branch = get_current_branch(ctx); |
| LLVMBasicBlockRef current_block = LLVMGetInsertBlock(gallivm->builder); |
| /* We need to add a terminator to the current block if the previous |
| * instruction was an ENDIF.Example: |
| * IF |
| * [code] |
| * IF |
| * [code] |
| * ELSE |
| * [code] |
| * ENDIF <-- |
| * ELSE<-- |
| * [code] |
| * ENDIF |
| */ |
| if (current_block != current_branch->if_block) { |
| LLVMBuildBr(gallivm->builder, current_branch->endif_block); |
| } |
| if (!LLVMGetBasicBlockTerminator(current_branch->if_block)) { |
| LLVMBuildBr(gallivm->builder, current_branch->endif_block); |
| } |
| current_branch->has_else = 1; |
| LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->else_block); |
| } |
| static void endif_emit( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); |
| struct gallivm_state * gallivm = bld_base->base.gallivm; |
| struct radeon_llvm_branch * current_branch = get_current_branch(ctx); |
| LLVMBasicBlockRef current_block = LLVMGetInsertBlock(gallivm->builder); |
| /* If we have consecutive ENDIF instructions, then the first ENDIF |
| * will not have a terminator, so we need to add one. */ |
| if (current_block != current_branch->if_block |
| && current_block != current_branch->else_block |
| && !LLVMGetBasicBlockTerminator(current_block)) { |
| LLVMBuildBr(gallivm->builder, current_branch->endif_block); |
| } |
| if (!LLVMGetBasicBlockTerminator(current_branch->else_block)) { |
| LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->else_block); |
| LLVMBuildBr(gallivm->builder, current_branch->endif_block); |
| } |
| if (!LLVMGetBasicBlockTerminator(current_branch->if_block)) { |
| LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->if_block); |
| LLVMBuildBr(gallivm->builder, current_branch->endif_block); |
| } |
| LLVMPositionBuilderAtEnd(gallivm->builder, current_branch->endif_block); |
| ctx->branch_depth--; |
| } |
| static void endloop_emit( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); |
| struct gallivm_state * gallivm = bld_base->base.gallivm; |
| struct radeon_llvm_loop * current_loop = get_current_loop(ctx); |
| if (!LLVMGetBasicBlockTerminator(LLVMGetInsertBlock(gallivm->builder))) { |
| LLVMBuildBr(gallivm->builder, current_loop->loop_block); |
| } |
| LLVMPositionBuilderAtEnd(gallivm->builder, current_loop->endloop_block); |
| ctx->loop_depth--; |
| } |
| static void if_cond_emit( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data, |
| LLVMValueRef cond) |
| { |
| struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); |
| struct gallivm_state * gallivm = bld_base->base.gallivm; |
| LLVMBasicBlockRef if_block, else_block, endif_block; |
| endif_block = LLVMAppendBasicBlockInContext(gallivm->context, |
| ctx->main_fn, "ENDIF"); |
| if_block = LLVMInsertBasicBlockInContext(gallivm->context, |
| endif_block, "IF"); |
| else_block = LLVMInsertBasicBlockInContext(gallivm->context, |
| endif_block, "ELSE"); |
| LLVMBuildCondBr(gallivm->builder, cond, if_block, else_block); |
| LLVMPositionBuilderAtEnd(gallivm->builder, if_block); |
| ctx->branch_depth++; |
| ctx->branch[ctx->branch_depth - 1].endif_block = endif_block; |
| ctx->branch[ctx->branch_depth - 1].if_block = if_block; |
| ctx->branch[ctx->branch_depth - 1].else_block = else_block; |
| ctx->branch[ctx->branch_depth - 1].has_else = 0; |
| } |
| static void if_emit( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| struct gallivm_state * gallivm = bld_base->base.gallivm; |
| LLVMValueRef cond; |
| cond = LLVMBuildFCmp(gallivm->builder, LLVMRealUNE, |
| emit_data->args[0], |
| bld_base->base.zero, ""); |
| if_cond_emit(action, bld_base, emit_data, cond); |
| } |
| static void uif_emit( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| struct gallivm_state * gallivm = bld_base->base.gallivm; |
| LLVMValueRef cond; |
| cond = LLVMBuildICmp(gallivm->builder, LLVMIntNE, |
| bitcast(bld_base, TGSI_TYPE_UNSIGNED, emit_data->args[0]), |
| bld_base->int_bld.zero, ""); |
| if_cond_emit(action, bld_base, emit_data, cond); |
| } |
| static void kil_emit( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| unsigned i; |
| for (i = 0; i < emit_data->arg_count; i++) { |
| emit_data->output[i] = lp_build_intrinsic_unary( |
| bld_base->base.gallivm->builder, |
| action->intr_name, |
| emit_data->dst_type, emit_data->args[i]); |
| } |
| } |
| void radeon_llvm_emit_prepare_cube_coords( |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data, |
| LLVMValueRef *coords_arg) |
| { |
| unsigned target = emit_data->inst->Texture.Texture; |
| unsigned opcode = emit_data->inst->Instruction.Opcode; |
| struct gallivm_state * gallivm = bld_base->base.gallivm; |
| LLVMBuilderRef builder = gallivm->builder; |
| LLVMTypeRef type = bld_base->base.elem_type; |
| LLVMValueRef coords[4]; |
| LLVMValueRef mad_args[3]; |
| LLVMValueRef idx; |
| struct LLVMOpaqueValue *cube_vec; |
| LLVMValueRef v; |
| unsigned i; |
| cube_vec = lp_build_gather_values(bld_base->base.gallivm, coords_arg, 4); |
| v = build_intrinsic(builder, "llvm.AMDGPU.cube", LLVMVectorType(type, 4), |
| &cube_vec, 1, LLVMReadNoneAttribute); |
| for (i = 0; i < 4; ++i) { |
| idx = lp_build_const_int32(gallivm, i); |
| coords[i] = LLVMBuildExtractElement(builder, v, idx, ""); |
| } |
| coords[2] = build_intrinsic(builder, "fabs", |
| type, &coords[2], 1, LLVMReadNoneAttribute); |
| coords[2] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_RCP, coords[2]); |
| mad_args[1] = coords[2]; |
| mad_args[2] = LLVMConstReal(type, 1.5); |
| mad_args[0] = coords[0]; |
| coords[0] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD, |
| mad_args[0], mad_args[1], mad_args[2]); |
| mad_args[0] = coords[1]; |
| coords[1] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD, |
| mad_args[0], mad_args[1], mad_args[2]); |
| /* apply xyz = yxw swizzle to cooords */ |
| coords[2] = coords[3]; |
| coords[3] = coords[1]; |
| coords[1] = coords[0]; |
| coords[0] = coords[3]; |
| /* all cases except simple cube map sampling require special handling |
| * for coord vector */ |
| if (target != TGSI_TEXTURE_CUBE || |
| opcode != TGSI_OPCODE_TEX) { |
| /* for cube arrays coord.z = coord.w(array_index) * 8 + face */ |
| if (target == TGSI_TEXTURE_CUBE_ARRAY || |
| target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) { |
| /* coords_arg.w component - array_index for cube arrays or |
| * compare value for SHADOWCUBE */ |
| coords[2] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD, |
| coords_arg[3], lp_build_const_float(gallivm, 8.0), coords[2]); |
| } |
| /* for instructions that need additional src (compare/lod/bias), |
| * put it in coord.w */ |
| if (opcode == TGSI_OPCODE_TEX2 || |
| opcode == TGSI_OPCODE_TXB2 || |
| opcode == TGSI_OPCODE_TXL2) { |
| coords[3] = coords_arg[4]; |
| } else if (opcode == TGSI_OPCODE_TXB || |
| opcode == TGSI_OPCODE_TXL) { |
| coords[3] = coords_arg[3]; |
| } |
| } |
| memcpy(coords_arg, coords, sizeof(coords)); |
| } |
| static void txd_fetch_args( |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| const struct tgsi_full_instruction * inst = emit_data->inst; |
| LLVMValueRef coords[4]; |
| unsigned chan, src; |
| for (src = 0; src < 3; src++) { |
| for (chan = 0; chan < 4; chan++) |
| coords[chan] = lp_build_emit_fetch(bld_base, inst, src, chan); |
| emit_data->args[src] = lp_build_gather_values(bld_base->base.gallivm, |
| coords, 4); |
| } |
| emit_data->arg_count = 3; |
| emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4); |
| } |
| static void txp_fetch_args( |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| const struct tgsi_full_instruction * inst = emit_data->inst; |
| LLVMValueRef src_w; |
| unsigned chan; |
| LLVMValueRef coords[4]; |
| emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4); |
| src_w = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W); |
| for (chan = 0; chan < 3; chan++ ) { |
| LLVMValueRef arg = lp_build_emit_fetch(bld_base, |
| emit_data->inst, 0, chan); |
| coords[chan] = lp_build_emit_llvm_binary(bld_base, |
| TGSI_OPCODE_DIV, arg, src_w); |
| } |
| coords[3] = bld_base->base.one; |
| if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE || |
| inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY || |
| inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE || |
| inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) && |
| inst->Instruction.Opcode != TGSI_OPCODE_TXQ && |
| inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) { |
| radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords); |
| } |
| emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm, |
| coords, 4); |
| emit_data->arg_count = 1; |
| } |
| static void tex_fetch_args( |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| /* XXX: lp_build_swizzle_aos() was failing with wrong arg types, |
| * when we used CHAN_ALL. We should be able to get this to work, |
| * but for now we will swizzle it ourselves |
| emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst, |
| 0, CHAN_ALL); |
| */ |
| const struct tgsi_full_instruction * inst = emit_data->inst; |
| LLVMValueRef coords[5]; |
| unsigned chan; |
| for (chan = 0; chan < 4; chan++) { |
| coords[chan] = lp_build_emit_fetch(bld_base, inst, 0, chan); |
| } |
| if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 || |
| inst->Instruction.Opcode == TGSI_OPCODE_TXB2 || |
| inst->Instruction.Opcode == TGSI_OPCODE_TXL2) { |
| /* These instructions have additional operand that should be packed |
| * into the cube coord vector by radeon_llvm_emit_prepare_cube_coords. |
| * That operand should be passed as a float value in the args array |
| * right after the coord vector. After packing it's not used anymore, |
| * that's why arg_count is not increased */ |
| coords[4] = lp_build_emit_fetch(bld_base, inst, 1, 0); |
| } |
| if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE || |
| inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY || |
| inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE || |
| inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) && |
| inst->Instruction.Opcode != TGSI_OPCODE_TXQ && |
| inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) { |
| radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords); |
| } |
| emit_data->arg_count = 1; |
| emit_data->args[0] = lp_build_gather_values(bld_base->base.gallivm, |
| coords, 4); |
| emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4); |
| } |
| static void txf_fetch_args( |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| const struct tgsi_full_instruction * inst = emit_data->inst; |
| struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base); |
| const struct tgsi_texture_offset * off = inst->TexOffsets; |
| LLVMTypeRef offset_type = bld_base->int_bld.elem_type; |
| /* fetch tex coords */ |
| tex_fetch_args(bld_base, emit_data); |
| /* fetch tex offsets */ |
| if (inst->Texture.NumOffsets) { |
| assert(inst->Texture.NumOffsets == 1); |
| emit_data->args[1] = LLVMConstBitCast( |
| bld->immediates[off->Index][off->SwizzleX], |
| offset_type); |
| emit_data->args[2] = LLVMConstBitCast( |
| bld->immediates[off->Index][off->SwizzleY], |
| offset_type); |
| emit_data->args[3] = LLVMConstBitCast( |
| bld->immediates[off->Index][off->SwizzleZ], |
| offset_type); |
| } else { |
| emit_data->args[1] = bld_base->int_bld.zero; |
| emit_data->args[2] = bld_base->int_bld.zero; |
| emit_data->args[3] = bld_base->int_bld.zero; |
| } |
| emit_data->arg_count = 4; |
| } |
| static void emit_icmp( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| unsigned pred; |
| LLVMBuilderRef builder = bld_base->base.gallivm->builder; |
| LLVMContextRef context = bld_base->base.gallivm->context; |
| switch (emit_data->inst->Instruction.Opcode) { |
| case TGSI_OPCODE_USEQ: pred = LLVMIntEQ; break; |
| case TGSI_OPCODE_USNE: pred = LLVMIntNE; break; |
| case TGSI_OPCODE_USGE: pred = LLVMIntUGE; break; |
| case TGSI_OPCODE_USLT: pred = LLVMIntULT; break; |
| case TGSI_OPCODE_ISGE: pred = LLVMIntSGE; break; |
| case TGSI_OPCODE_ISLT: pred = LLVMIntSLT; break; |
| default: |
| assert(!"unknown instruction"); |
| pred = 0; |
| break; |
| } |
| LLVMValueRef v = LLVMBuildICmp(builder, pred, |
| emit_data->args[0], emit_data->args[1],""); |
| v = LLVMBuildSExtOrBitCast(builder, v, |
| LLVMInt32TypeInContext(context), ""); |
| emit_data->output[emit_data->chan] = v; |
| } |
| static void emit_ucmp( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| LLVMBuilderRef builder = bld_base->base.gallivm->builder; |
| LLVMValueRef v = LLVMBuildFCmp(builder, LLVMRealUGE, |
| emit_data->args[0], lp_build_const_float(bld_base->base.gallivm, 0.), ""); |
| emit_data->output[emit_data->chan] = LLVMBuildSelect(builder, v, emit_data->args[2], emit_data->args[1], ""); |
| } |
| static void emit_cmp( |
| const struct lp_build_tgsi_action *action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| LLVMBuilderRef builder = bld_base->base.gallivm->builder; |
| LLVMRealPredicate pred; |
| LLVMValueRef cond; |
| /* XXX I'm not sure whether to do unordered or ordered comparisons, |
| * but llvmpipe uses unordered comparisons, so for consistency we use |
| * unordered. (The authors of llvmpipe aren't sure about using |
| * unordered vs ordered comparisons either. |
| */ |
| switch (emit_data->inst->Instruction.Opcode) { |
| case TGSI_OPCODE_SGE: pred = LLVMRealUGE; break; |
| case TGSI_OPCODE_SEQ: pred = LLVMRealUEQ; break; |
| case TGSI_OPCODE_SLE: pred = LLVMRealULE; break; |
| case TGSI_OPCODE_SLT: pred = LLVMRealULT; break; |
| case TGSI_OPCODE_SNE: pred = LLVMRealUNE; break; |
| case TGSI_OPCODE_SGT: pred = LLVMRealUGT; break; |
| default: assert(!"unknown instruction"); pred = 0; break; |
| } |
| cond = LLVMBuildFCmp(builder, |
| pred, emit_data->args[0], emit_data->args[1], ""); |
| emit_data->output[emit_data->chan] = LLVMBuildSelect(builder, |
| cond, bld_base->base.one, bld_base->base.zero, ""); |
| } |
| static void emit_not( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| LLVMBuilderRef builder = bld_base->base.gallivm->builder; |
| LLVMValueRef v = bitcast(bld_base, TGSI_TYPE_UNSIGNED, |
| emit_data->args[0]); |
| emit_data->output[emit_data->chan] = LLVMBuildNot(builder, v, ""); |
| } |
| static void emit_arl( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| LLVMBuilderRef builder = bld_base->base.gallivm->builder; |
| LLVMValueRef floor_index = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_FLR, emit_data->args[0]); |
| emit_data->output[emit_data->chan] = LLVMBuildFPToSI(builder, |
| floor_index, bld_base->base.int_elem_type , ""); |
| } |
| static void emit_and( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| LLVMBuilderRef builder = bld_base->base.gallivm->builder; |
| emit_data->output[emit_data->chan] = LLVMBuildAnd(builder, |
| emit_data->args[0], emit_data->args[1], ""); |
| } |
| static void emit_or( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| LLVMBuilderRef builder = bld_base->base.gallivm->builder; |
| emit_data->output[emit_data->chan] = LLVMBuildOr(builder, |
| emit_data->args[0], emit_data->args[1], ""); |
| } |
| static void emit_uadd( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| LLVMBuilderRef builder = bld_base->base.gallivm->builder; |
| emit_data->output[emit_data->chan] = LLVMBuildAdd(builder, |
| emit_data->args[0], emit_data->args[1], ""); |
| } |
| static void emit_udiv( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| LLVMBuilderRef builder = bld_base->base.gallivm->builder; |
| emit_data->output[emit_data->chan] = LLVMBuildUDiv(builder, |
| emit_data->args[0], emit_data->args[1], ""); |
| } |
| static void emit_idiv( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| LLVMBuilderRef builder = bld_base->base.gallivm->builder; |
| emit_data->output[emit_data->chan] = LLVMBuildSDiv(builder, |
| emit_data->args[0], emit_data->args[1], ""); |
| } |
| static void emit_mod( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| LLVMBuilderRef builder = bld_base->base.gallivm->builder; |
| emit_data->output[emit_data->chan] = LLVMBuildSRem(builder, |
| emit_data->args[0], emit_data->args[1], ""); |
| } |
| static void emit_umod( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| LLVMBuilderRef builder = bld_base->base.gallivm->builder; |
| emit_data->output[emit_data->chan] = LLVMBuildURem(builder, |
| emit_data->args[0], emit_data->args[1], ""); |
| } |
| static void emit_shl( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| LLVMBuilderRef builder = bld_base->base.gallivm->builder; |
| emit_data->output[emit_data->chan] = LLVMBuildShl(builder, |
| emit_data->args[0], emit_data->args[1], ""); |
| } |
| static void emit_ushr( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| LLVMBuilderRef builder = bld_base->base.gallivm->builder; |
| emit_data->output[emit_data->chan] = LLVMBuildLShr(builder, |
| emit_data->args[0], emit_data->args[1], ""); |
| } |
| static void emit_ishr( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| LLVMBuilderRef builder = bld_base->base.gallivm->builder; |
| emit_data->output[emit_data->chan] = LLVMBuildAShr(builder, |
| emit_data->args[0], emit_data->args[1], ""); |
| } |
| static void emit_xor( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| LLVMBuilderRef builder = bld_base->base.gallivm->builder; |
| emit_data->output[emit_data->chan] = LLVMBuildXor(builder, |
| emit_data->args[0], emit_data->args[1], ""); |
| } |
| static void emit_ssg( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| LLVMBuilderRef builder = bld_base->base.gallivm->builder; |
| LLVMValueRef cmp, val; |
| if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_ISSG) { |
| cmp = LLVMBuildICmp(builder, LLVMIntSGT, emit_data->args[0], bld_base->int_bld.zero, ""); |
| val = LLVMBuildSelect(builder, cmp, bld_base->int_bld.one, emit_data->args[0], ""); |
| cmp = LLVMBuildICmp(builder, LLVMIntSGE, val, bld_base->int_bld.zero, ""); |
| val = LLVMBuildSelect(builder, cmp, val, LLVMConstInt(bld_base->int_bld.elem_type, -1, true), ""); |
| } else { // float SSG |
| cmp = LLVMBuildFCmp(builder, LLVMRealUGT, emit_data->args[0], bld_base->base.zero, ""); |
| val = LLVMBuildSelect(builder, cmp, bld_base->base.one, emit_data->args[0], ""); |
| cmp = LLVMBuildFCmp(builder, LLVMRealUGE, val, bld_base->base.zero, ""); |
| val = LLVMBuildSelect(builder, cmp, val, LLVMConstReal(bld_base->base.elem_type, -1), ""); |
| } |
| emit_data->output[emit_data->chan] = val; |
| } |
| static void emit_ineg( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| LLVMBuilderRef builder = bld_base->base.gallivm->builder; |
| emit_data->output[emit_data->chan] = LLVMBuildNeg(builder, |
| emit_data->args[0], ""); |
| } |
| static void emit_f2i( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| LLVMBuilderRef builder = bld_base->base.gallivm->builder; |
| emit_data->output[emit_data->chan] = LLVMBuildFPToSI(builder, |
| emit_data->args[0], bld_base->int_bld.elem_type, ""); |
| } |
| static void emit_f2u( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| LLVMBuilderRef builder = bld_base->base.gallivm->builder; |
| emit_data->output[emit_data->chan] = LLVMBuildFPToUI(builder, |
| emit_data->args[0], bld_base->uint_bld.elem_type, ""); |
| } |
| static void emit_i2f( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| LLVMBuilderRef builder = bld_base->base.gallivm->builder; |
| emit_data->output[emit_data->chan] = LLVMBuildSIToFP(builder, |
| emit_data->args[0], bld_base->base.elem_type, ""); |
| } |
| static void emit_u2f( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| LLVMBuilderRef builder = bld_base->base.gallivm->builder; |
| emit_data->output[emit_data->chan] = LLVMBuildUIToFP(builder, |
| emit_data->args[0], bld_base->base.elem_type, ""); |
| } |
| static void emit_immediate(struct lp_build_tgsi_context * bld_base, |
| const struct tgsi_full_immediate *imm) |
| { |
| unsigned i; |
| struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base); |
| for (i = 0; i < 4; ++i) { |
| ctx->soa.immediates[ctx->soa.num_immediates][i] = |
| LLVMConstInt(bld_base->uint_bld.elem_type, imm->u[i].Uint, false ); |
| } |
| ctx->soa.num_immediates++; |
| } |
| LLVMValueRef |
| build_intrinsic(LLVMBuilderRef builder, |
| const char *name, |
| LLVMTypeRef ret_type, |
| LLVMValueRef *args, |
| unsigned num_args, |
| LLVMAttribute attr) |
| { |
| LLVMModuleRef module = LLVMGetGlobalParent(LLVMGetBasicBlockParent(LLVMGetInsertBlock(builder))); |
| LLVMValueRef function; |
| function = LLVMGetNamedFunction(module, name); |
| if(!function) { |
| LLVMTypeRef arg_types[LP_MAX_FUNC_ARGS]; |
| unsigned i; |
| assert(num_args <= LP_MAX_FUNC_ARGS); |
| for(i = 0; i < num_args; ++i) { |
| assert(args[i]); |
| arg_types[i] = LLVMTypeOf(args[i]); |
| } |
| function = lp_declare_intrinsic(module, name, ret_type, arg_types, num_args); |
| if (attr) |
| LLVMAddFunctionAttr(function, attr); |
| } |
| return LLVMBuildCall(builder, function, args, num_args, ""); |
| } |
| static void build_tgsi_intrinsic( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data, |
| LLVMAttribute attr) |
| { |
| struct lp_build_context * base = &bld_base->base; |
| emit_data->output[emit_data->chan] = build_intrinsic( |
| base->gallivm->builder, action->intr_name, |
| emit_data->dst_type, emit_data->args, |
| emit_data->arg_count, attr); |
| } |
| void |
| build_tgsi_intrinsic_nomem( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| build_tgsi_intrinsic(action, bld_base, emit_data, LLVMReadNoneAttribute); |
| } |
| static void build_tgsi_intrinsic_readonly( |
| const struct lp_build_tgsi_action * action, |
| struct lp_build_tgsi_context * bld_base, |
| struct lp_build_emit_data * emit_data) |
| { |
| build_tgsi_intrinsic(action, bld_base, emit_data, LLVMReadOnlyAttribute); |
| } |
| void radeon_llvm_context_init(struct radeon_llvm_context * ctx) |
| { |
| struct lp_type type; |
| /* Initialize the gallivm object: |
| * We are only using the module, context, and builder fields of this struct. |
| * This should be enough for us to be able to pass our gallivm struct to the |
| * helper functions in the gallivm module. |
| */ |
| memset(&ctx->gallivm, 0, sizeof (ctx->gallivm)); |
| memset(&ctx->soa, 0, sizeof(ctx->soa)); |
| ctx->gallivm.context = LLVMContextCreate(); |
| ctx->gallivm.module = LLVMModuleCreateWithNameInContext("tgsi", |
| ctx->gallivm.context); |
| ctx->gallivm.builder = LLVMCreateBuilderInContext(ctx->gallivm.context); |
| ctx->store_output_intr = "llvm.AMDGPU.store.output."; |
| ctx->swizzle_intr = "llvm.AMDGPU.swizzle"; |
| struct lp_build_tgsi_context * bld_base = &ctx->soa.bld_base; |
| /* XXX: We need to revisit this.I think the correct way to do this is |
| * to use length = 4 here and use the elem_bld for everything. */ |
| type.floating = TRUE; |
| type.fixed = FALSE; |
| type.sign = TRUE; |
| type.norm = FALSE; |
| type.width = 32; |
| type.length = 1; |
| lp_build_context_init(&bld_base->base, &ctx->gallivm, type); |
| lp_build_context_init(&ctx->soa.bld_base.uint_bld, &ctx->gallivm, lp_uint_type(type)); |
| lp_build_context_init(&ctx->soa.bld_base.int_bld, &ctx->gallivm, lp_int_type(type)); |
| bld_base->soa = 1; |
| bld_base->emit_store = emit_store; |
| bld_base->emit_swizzle = emit_swizzle; |
| bld_base->emit_declaration = emit_declaration; |
| bld_base->emit_immediate = emit_immediate; |
| bld_base->emit_fetch_funcs[TGSI_FILE_IMMEDIATE] = emit_fetch; |
| bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = emit_fetch; |
| bld_base->emit_fetch_funcs[TGSI_FILE_TEMPORARY] = emit_fetch; |
| bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = emit_fetch; |
| bld_base->emit_fetch_funcs[TGSI_FILE_SYSTEM_VALUE] = fetch_system_value; |
| /* Allocate outputs */ |
| ctx->soa.outputs = ctx->outputs; |
| ctx->num_arrays = 0; |
| /* XXX: Is there a better way to initialize all this ? */ |
| lp_set_default_actions(bld_base); |
| bld_base->op_actions[TGSI_OPCODE_ABS].emit = build_tgsi_intrinsic_readonly; |
| bld_base->op_actions[TGSI_OPCODE_ABS].intr_name = "fabs"; |
| bld_base->op_actions[TGSI_OPCODE_ARL].emit = emit_arl; |
| bld_base->op_actions[TGSI_OPCODE_AND].emit = emit_and; |
| bld_base->op_actions[TGSI_OPCODE_BGNLOOP].emit = bgnloop_emit; |
| bld_base->op_actions[TGSI_OPCODE_BRK].emit = brk_emit; |
| bld_base->op_actions[TGSI_OPCODE_CEIL].emit = build_tgsi_intrinsic_readonly; |
| bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "ceil"; |
| bld_base->op_actions[TGSI_OPCODE_CLAMP].emit = build_tgsi_intrinsic_nomem; |
| bld_base->op_actions[TGSI_OPCODE_CLAMP].intr_name = "llvm.AMDIL.clamp."; |
| bld_base->op_actions[TGSI_OPCODE_CMP].emit = build_tgsi_intrinsic_nomem; |
| bld_base->op_actions[TGSI_OPCODE_CMP].intr_name = "llvm.AMDGPU.cndlt"; |
| bld_base->op_actions[TGSI_OPCODE_CONT].emit = cont_emit; |
| bld_base->op_actions[TGSI_OPCODE_COS].emit = build_tgsi_intrinsic_readonly; |
| bld_base->op_actions[TGSI_OPCODE_COS].intr_name = "llvm.cos.f32"; |
| bld_base->op_actions[TGSI_OPCODE_DDX].intr_name = "llvm.AMDGPU.ddx"; |
| bld_base->op_actions[TGSI_OPCODE_DDX].fetch_args = tex_fetch_args; |
| bld_base->op_actions[TGSI_OPCODE_DDY].intr_name = "llvm.AMDGPU.ddy"; |
| bld_base->op_actions[TGSI_OPCODE_DDY].fetch_args = tex_fetch_args; |
| bld_base->op_actions[TGSI_OPCODE_ELSE].emit = else_emit; |
| bld_base->op_actions[TGSI_OPCODE_ENDIF].emit = endif_emit; |
| bld_base->op_actions[TGSI_OPCODE_ENDLOOP].emit = endloop_emit; |
| bld_base->op_actions[TGSI_OPCODE_EX2].emit = build_tgsi_intrinsic_nomem; |
| bld_base->op_actions[TGSI_OPCODE_EX2].intr_name = "llvm.AMDIL.exp."; |
| bld_base->op_actions[TGSI_OPCODE_FLR].emit = build_tgsi_intrinsic_readonly; |
| bld_base->op_actions[TGSI_OPCODE_FLR].intr_name = "floor"; |
| bld_base->op_actions[TGSI_OPCODE_FRC].emit = build_tgsi_intrinsic_nomem; |
| bld_base->op_actions[TGSI_OPCODE_FRC].intr_name = "llvm.AMDIL.fraction."; |
| bld_base->op_actions[TGSI_OPCODE_F2I].emit = emit_f2i; |
| bld_base->op_actions[TGSI_OPCODE_F2U].emit = emit_f2u; |
| bld_base->op_actions[TGSI_OPCODE_IABS].emit = build_tgsi_intrinsic_nomem; |
| bld_base->op_actions[TGSI_OPCODE_IABS].intr_name = "llvm.AMDIL.abs."; |
| bld_base->op_actions[TGSI_OPCODE_IDIV].emit = emit_idiv; |
| bld_base->op_actions[TGSI_OPCODE_IF].emit = if_emit; |
| bld_base->op_actions[TGSI_OPCODE_UIF].emit = uif_emit; |
| bld_base->op_actions[TGSI_OPCODE_IMAX].emit = build_tgsi_intrinsic_nomem; |
| bld_base->op_actions[TGSI_OPCODE_IMAX].intr_name = "llvm.AMDGPU.imax"; |
| bld_base->op_actions[TGSI_OPCODE_IMIN].emit = build_tgsi_intrinsic_nomem; |
| bld_base->op_actions[TGSI_OPCODE_IMIN].intr_name = "llvm.AMDGPU.imin"; |
| bld_base->op_actions[TGSI_OPCODE_INEG].emit = emit_ineg; |
| bld_base->op_actions[TGSI_OPCODE_ISHR].emit = emit_ishr; |
| bld_base->op_actions[TGSI_OPCODE_ISGE].emit = emit_icmp; |
| bld_base->op_actions[TGSI_OPCODE_ISLT].emit = emit_icmp; |
| bld_base->op_actions[TGSI_OPCODE_ISSG].emit = emit_ssg; |
| bld_base->op_actions[TGSI_OPCODE_I2F].emit = emit_i2f; |
| bld_base->op_actions[TGSI_OPCODE_KILL_IF].emit = kil_emit; |
| bld_base->op_actions[TGSI_OPCODE_KILL_IF].intr_name = "llvm.AMDGPU.kill"; |
| bld_base->op_actions[TGSI_OPCODE_KILL].emit = lp_build_tgsi_intrinsic; |
| bld_base->op_actions[TGSI_OPCODE_KILL].intr_name = "llvm.AMDGPU.kilp"; |
| bld_base->op_actions[TGSI_OPCODE_LG2].emit = build_tgsi_intrinsic_readonly; |
| bld_base->op_actions[TGSI_OPCODE_LG2].intr_name = "llvm.log2.f32"; |
| bld_base->op_actions[TGSI_OPCODE_LRP].emit = build_tgsi_intrinsic_nomem; |
| bld_base->op_actions[TGSI_OPCODE_LRP].intr_name = "llvm.AMDGPU.lrp"; |
| bld_base->op_actions[TGSI_OPCODE_MOD].emit = emit_mod; |
| bld_base->op_actions[TGSI_OPCODE_NOT].emit = emit_not; |
| bld_base->op_actions[TGSI_OPCODE_OR].emit = emit_or; |
| bld_base->op_actions[TGSI_OPCODE_POW].emit = build_tgsi_intrinsic_readonly; |
| bld_base->op_actions[TGSI_OPCODE_POW].intr_name = "llvm.pow.f32"; |
| bld_base->op_actions[TGSI_OPCODE_ROUND].emit = build_tgsi_intrinsic_nomem; |
| bld_base->op_actions[TGSI_OPCODE_ROUND].intr_name = "llvm.AMDIL.round.nearest."; |
| bld_base->op_actions[TGSI_OPCODE_SGE].emit = emit_cmp; |
| bld_base->op_actions[TGSI_OPCODE_SEQ].emit = emit_cmp; |
| bld_base->op_actions[TGSI_OPCODE_SHL].emit = emit_shl; |
| bld_base->op_actions[TGSI_OPCODE_SLE].emit = emit_cmp; |
| bld_base->op_actions[TGSI_OPCODE_SLT].emit = emit_cmp; |
| bld_base->op_actions[TGSI_OPCODE_SNE].emit = emit_cmp; |
| bld_base->op_actions[TGSI_OPCODE_SGT].emit = emit_cmp; |
| bld_base->op_actions[TGSI_OPCODE_SIN].emit = build_tgsi_intrinsic_readonly; |
| bld_base->op_actions[TGSI_OPCODE_SIN].intr_name = "llvm.sin.f32"; |
| bld_base->op_actions[TGSI_OPCODE_SSG].emit = emit_ssg; |
| bld_base->op_actions[TGSI_OPCODE_TEX].fetch_args = tex_fetch_args; |
| bld_base->op_actions[TGSI_OPCODE_TEX].intr_name = "llvm.AMDGPU.tex"; |
| bld_base->op_actions[TGSI_OPCODE_TEX2].fetch_args = tex_fetch_args; |
| bld_base->op_actions[TGSI_OPCODE_TEX2].intr_name = "llvm.AMDGPU.tex"; |
| bld_base->op_actions[TGSI_OPCODE_TXB].fetch_args = tex_fetch_args; |
| bld_base->op_actions[TGSI_OPCODE_TXB].intr_name = "llvm.AMDGPU.txb"; |
| bld_base->op_actions[TGSI_OPCODE_TXB2].fetch_args = tex_fetch_args; |
| bld_base->op_actions[TGSI_OPCODE_TXB2].intr_name = "llvm.AMDGPU.txb"; |
| bld_base->op_actions[TGSI_OPCODE_TXD].fetch_args = txd_fetch_args; |
| bld_base->op_actions[TGSI_OPCODE_TXD].intr_name = "llvm.AMDGPU.txd"; |
| bld_base->op_actions[TGSI_OPCODE_TXF].fetch_args = txf_fetch_args; |
| bld_base->op_actions[TGSI_OPCODE_TXF].intr_name = "llvm.AMDGPU.txf"; |
| bld_base->op_actions[TGSI_OPCODE_TXL].fetch_args = tex_fetch_args; |
| bld_base->op_actions[TGSI_OPCODE_TXL].intr_name = "llvm.AMDGPU.txl"; |
| bld_base->op_actions[TGSI_OPCODE_TXL2].fetch_args = tex_fetch_args; |
| bld_base->op_actions[TGSI_OPCODE_TXL2].intr_name = "llvm.AMDGPU.txl"; |
| bld_base->op_actions[TGSI_OPCODE_TXP].fetch_args = txp_fetch_args; |
| bld_base->op_actions[TGSI_OPCODE_TXP].intr_name = "llvm.AMDGPU.tex"; |
| bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = tex_fetch_args; |
| bld_base->op_actions[TGSI_OPCODE_TXQ].intr_name = "llvm.AMDGPU.txq"; |
| bld_base->op_actions[TGSI_OPCODE_TRUNC].emit = build_tgsi_intrinsic_nomem; |
| bld_base->op_actions[TGSI_OPCODE_TRUNC].intr_name = "llvm.AMDGPU.trunc"; |
| bld_base->op_actions[TGSI_OPCODE_UADD].emit = emit_uadd; |
| bld_base->op_actions[TGSI_OPCODE_UDIV].emit = emit_udiv; |
| bld_base->op_actions[TGSI_OPCODE_UMAX].emit = build_tgsi_intrinsic_nomem; |
| bld_base->op_actions[TGSI_OPCODE_UMAX].intr_name = "llvm.AMDGPU.umax"; |
| bld_base->op_actions[TGSI_OPCODE_UMIN].emit = build_tgsi_intrinsic_nomem; |
| bld_base->op_actions[TGSI_OPCODE_UMIN].intr_name = "llvm.AMDGPU.umin"; |
| bld_base->op_actions[TGSI_OPCODE_UMOD].emit = emit_umod; |
| bld_base->op_actions[TGSI_OPCODE_USEQ].emit = emit_icmp; |
| bld_base->op_actions[TGSI_OPCODE_USGE].emit = emit_icmp; |
| bld_base->op_actions[TGSI_OPCODE_USHR].emit = emit_ushr; |
| bld_base->op_actions[TGSI_OPCODE_USLT].emit = emit_icmp; |
| bld_base->op_actions[TGSI_OPCODE_USNE].emit = emit_icmp; |
| bld_base->op_actions[TGSI_OPCODE_U2F].emit = emit_u2f; |
| bld_base->op_actions[TGSI_OPCODE_XOR].emit = emit_xor; |
| bld_base->op_actions[TGSI_OPCODE_UCMP].emit = emit_ucmp; |
| bld_base->rsq_action.emit = build_tgsi_intrinsic_nomem; |
| bld_base->rsq_action.intr_name = "llvm.AMDGPU.rsq"; |
| } |
| void radeon_llvm_create_func(struct radeon_llvm_context * ctx, |
| LLVMTypeRef *ParamTypes, unsigned ParamCount) |
| { |
| LLVMTypeRef main_fn_type; |
| LLVMBasicBlockRef main_fn_body; |
| /* Setup the function */ |
| main_fn_type = LLVMFunctionType(LLVMVoidTypeInContext(ctx->gallivm.context), |
| ParamTypes, ParamCount, 0); |
| ctx->main_fn = LLVMAddFunction(ctx->gallivm.module, "main", main_fn_type); |
| main_fn_body = LLVMAppendBasicBlockInContext(ctx->gallivm.context, |
| ctx->main_fn, "main_body"); |
| LLVMPositionBuilderAtEnd(ctx->gallivm.builder, main_fn_body); |
| } |
| void radeon_llvm_finalize_module(struct radeon_llvm_context * ctx) |
| { |
| struct gallivm_state * gallivm = ctx->soa.bld_base.base.gallivm; |
| /* End the main function with Return*/ |
| LLVMBuildRetVoid(gallivm->builder); |
| /* Create the pass manager */ |
| ctx->gallivm.passmgr = LLVMCreateFunctionPassManagerForModule( |
| gallivm->module); |
| /* This pass should eliminate all the load and store instructions */ |
| LLVMAddPromoteMemoryToRegisterPass(gallivm->passmgr); |
| /* Add some optimization passes */ |
| LLVMAddScalarReplAggregatesPass(gallivm->passmgr); |
| LLVMAddLICMPass(gallivm->passmgr); |
| LLVMAddAggressiveDCEPass(gallivm->passmgr); |
| LLVMAddCFGSimplificationPass(gallivm->passmgr); |
| /* Run the passs */ |
| LLVMRunFunctionPassManager(gallivm->passmgr, ctx->main_fn); |
| LLVMDisposeBuilder(gallivm->builder); |
| LLVMDisposePassManager(gallivm->passmgr); |
| } |
| void radeon_llvm_dispose(struct radeon_llvm_context * ctx) |
| { |
| LLVMDisposeModule(ctx->soa.bld_base.base.gallivm->module); |
| LLVMContextDispose(ctx->soa.bld_base.base.gallivm->context); |
| } |
| /contrib/sdk/sources/Mesa/mesa-9.2.5/src/gallium/drivers/radeon/radeon_uvd.c |
|---|
| 0,0 → 1,1127 |
| /************************************************************************** |
| * |
| * Copyright 2011 Advanced Micro Devices, Inc. |
| * All Rights Reserved. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the |
| * "Software"), to deal in the Software without restriction, including |
| * without limitation the rights to use, copy, modify, merge, publish, |
| * distribute, sub license, and/or sell copies of the Software, and to |
| * permit persons to whom the Software is furnished to do so, subject to |
| * the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the |
| * next paragraph) shall be included in all copies or substantial portions |
| * of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR |
| * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| * |
| **************************************************************************/ |
| /* |
| * Authors: |
| * Christian König <christian.koenig@amd.com> |
| * |
| */ |
| #include <sys/types.h> |
| #include <assert.h> |
| #include <errno.h> |
| #include <unistd.h> |
| #include <stdio.h> |
| #include "pipe/p_video_decoder.h" |
| #include "util/u_memory.h" |
| #include "util/u_video.h" |
| #include "vl/vl_defines.h" |
| #include "vl/vl_mpeg12_decoder.h" |
| #include "../../winsys/radeon/drm/radeon_winsys.h" |
| #include "radeon_uvd.h" |
| #define RUVD_ERR(fmt, args...) \ |
| fprintf(stderr, "EE %s:%d %s UVD - "fmt, __FILE__, __LINE__, __func__, ##args) |
| #define NUM_BUFFERS 4 |
| #define NUM_MPEG2_REFS 6 |
| #define NUM_H264_REFS 17 |
| /* UVD buffer representation */ |
| struct ruvd_buffer |
| { |
| struct pb_buffer* buf; |
| struct radeon_winsys_cs_handle* cs_handle; |
| }; |
| /* UVD decoder representation */ |
| struct ruvd_decoder { |
| struct pipe_video_decoder base; |
| ruvd_set_dtb set_dtb; |
| unsigned stream_handle; |
| unsigned frame_number; |
| struct radeon_winsys* ws; |
| struct radeon_winsys_cs* cs; |
| unsigned cur_buffer; |
| struct ruvd_buffer msg_fb_buffers[NUM_BUFFERS]; |
| struct ruvd_buffer bs_buffers[NUM_BUFFERS]; |
| void* bs_ptr; |
| unsigned bs_size; |
| struct ruvd_buffer dpb; |
| }; |
| /* generate an UVD stream handle */ |
| static unsigned alloc_stream_handle() |
| { |
| static unsigned counter = 0; |
| unsigned stream_handle = 0; |
| unsigned pid = getpid(); |
| int i; |
| for (i = 0; i < 32; ++i) |
| stream_handle |= ((pid >> i) & 1) << (31 - i); |
| stream_handle ^= ++counter; |
| return stream_handle; |
| } |
| /* flush IB to the hardware */ |
| static void flush(struct ruvd_decoder *dec) |
| { |
| uint32_t *pm4 = dec->cs->buf; |
| // align IB |
| while(dec->cs->cdw % 16) |
| pm4[dec->cs->cdw++] = RUVD_PKT2(); |
| dec->ws->cs_flush(dec->cs, 0, 0); |
| } |
| /* add a new set register command to the IB */ |
| static void set_reg(struct ruvd_decoder *dec, unsigned reg, uint32_t val) |
| { |
| uint32_t *pm4 = dec->cs->buf; |
| pm4[dec->cs->cdw++] = RUVD_PKT0(reg >> 2, 0); |
| pm4[dec->cs->cdw++] = val; |
| } |
| /* send a command to the VCPU through the GPCOM registers */ |
| static void send_cmd(struct ruvd_decoder *dec, unsigned cmd, |
| struct radeon_winsys_cs_handle* cs_buf, uint32_t off, |
| enum radeon_bo_usage usage, enum radeon_bo_domain domain) |
| { |
| int reloc_idx; |
| reloc_idx = dec->ws->cs_add_reloc(dec->cs, cs_buf, usage, domain); |
| set_reg(dec, RUVD_GPCOM_VCPU_DATA0, off); |
| set_reg(dec, RUVD_GPCOM_VCPU_DATA1, reloc_idx * 4); |
| set_reg(dec, RUVD_GPCOM_VCPU_CMD, cmd << 1); |
| } |
| /* send a message command to the VCPU */ |
| static void send_msg(struct ruvd_decoder *dec, struct ruvd_msg *msg) |
| { |
| struct ruvd_buffer* buf; |
| void *ptr; |
| /* grap a message buffer */ |
| buf = &dec->msg_fb_buffers[dec->cur_buffer]; |
| /* copy the message into it */ |
| ptr = dec->ws->buffer_map(buf->cs_handle, dec->cs, PIPE_TRANSFER_WRITE); |
| if (!ptr) |
| return; |
| memcpy(ptr, msg, sizeof(*msg)); |
| memset(ptr + sizeof(*msg), 0, buf->buf->size - sizeof(*msg)); |
| dec->ws->buffer_unmap(buf->cs_handle); |
| /* and send it to the hardware */ |
| send_cmd(dec, RUVD_CMD_MSG_BUFFER, buf->cs_handle, 0, |
| RADEON_USAGE_READ, RADEON_DOMAIN_VRAM); |
| } |
| /* create a buffer in the winsys */ |
| static bool create_buffer(struct ruvd_decoder *dec, |
| struct ruvd_buffer *buffer, |
| unsigned size) |
| { |
| buffer->buf = dec->ws->buffer_create(dec->ws, size, 4096, false, |
| RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM); |
| if (!buffer->buf) |
| return false; |
| buffer->cs_handle = dec->ws->buffer_get_cs_handle(buffer->buf); |
| if (!buffer->cs_handle) |
| return false; |
| return true; |
| } |
| /* destroy a buffer */ |
| static void destroy_buffer(struct ruvd_buffer *buffer) |
| { |
| pb_reference(&buffer->buf, NULL); |
| buffer->cs_handle = NULL; |
| } |
| /* reallocate a buffer, preserving its content */ |
| static bool resize_buffer(struct ruvd_decoder *dec, |
| struct ruvd_buffer *new_buf, |
| unsigned new_size) |
| { |
| unsigned bytes = MIN2(new_buf->buf->size, new_size); |
| struct ruvd_buffer old_buf = *new_buf; |
| void *src = NULL, *dst = NULL; |
| if (!create_buffer(dec, new_buf, new_size)) |
| goto error; |
| src = dec->ws->buffer_map(old_buf.cs_handle, dec->cs, PIPE_TRANSFER_READ); |
| if (!src) |
| goto error; |
| dst = dec->ws->buffer_map(new_buf->cs_handle, dec->cs, PIPE_TRANSFER_WRITE); |
| if (!dst) |
| goto error; |
| memcpy(dst, src, bytes); |
| if (new_size > bytes) { |
| new_size -= bytes; |
| dst += bytes; |
| memset(dst, 0, new_size); |
| } |
| dec->ws->buffer_unmap(new_buf->cs_handle); |
| dec->ws->buffer_unmap(old_buf.cs_handle); |
| destroy_buffer(&old_buf); |
| return true; |
| error: |
| if (src) dec->ws->buffer_unmap(old_buf.cs_handle); |
| destroy_buffer(new_buf); |
| *new_buf = old_buf; |
| return false; |
| } |
| /* clear the buffer with zeros */ |
| static void clear_buffer(struct ruvd_decoder *dec, |
| struct ruvd_buffer* buffer) |
| { |
| //TODO: let the GPU do the job |
| void *ptr = dec->ws->buffer_map(buffer->cs_handle, dec->cs, |
| PIPE_TRANSFER_WRITE); |
| if (!ptr) |
| return; |
| memset(ptr, 0, buffer->buf->size); |
| dec->ws->buffer_unmap(buffer->cs_handle); |
| } |
| /* cycle to the next set of buffers */ |
| static void next_buffer(struct ruvd_decoder *dec) |
| { |
| ++dec->cur_buffer; |
| dec->cur_buffer %= NUM_BUFFERS; |
| } |
| /* convert the profile into something UVD understands */ |
| static uint32_t profile2stream_type(enum pipe_video_profile profile) |
| { |
| switch (u_reduce_video_profile(profile)) { |
| case PIPE_VIDEO_CODEC_MPEG4_AVC: |
| return RUVD_CODEC_H264; |
| case PIPE_VIDEO_CODEC_VC1: |
| return RUVD_CODEC_VC1; |
| case PIPE_VIDEO_CODEC_MPEG12: |
| return RUVD_CODEC_MPEG2; |
| case PIPE_VIDEO_CODEC_MPEG4: |
| return RUVD_CODEC_MPEG4; |
| default: |
| assert(0); |
| return 0; |
| } |
| } |
| /* calculate size of reference picture buffer */ |
| static unsigned calc_dpb_size(enum pipe_video_profile profile, |
| unsigned width, unsigned height, |
| unsigned max_references) |
| { |
| unsigned width_in_mb, height_in_mb, image_size, dpb_size; |
| // always align them to MB size for dpb calculation |
| width = align(width, VL_MACROBLOCK_WIDTH); |
| height = align(height, VL_MACROBLOCK_HEIGHT); |
| // always one more for currently decoded picture |
| max_references += 1; |
| // aligned size of a single frame |
| image_size = width * height; |
| image_size += image_size / 2; |
| image_size = align(image_size, 1024); |
| // picture width & height in 16 pixel units |
| width_in_mb = width / VL_MACROBLOCK_WIDTH; |
| height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2); |
| switch (u_reduce_video_profile(profile)) { |
| case PIPE_VIDEO_CODEC_MPEG4_AVC: |
| // the firmware seems to allways assume a minimum of ref frames |
| max_references = MAX2(NUM_H264_REFS, max_references); |
| // reference picture buffer |
| dpb_size = image_size * max_references; |
| // macroblock context buffer |
| dpb_size += width_in_mb * height_in_mb * max_references * 192; |
| // IT surface buffer |
| dpb_size += width_in_mb * height_in_mb * 32; |
| break; |
| case PIPE_VIDEO_CODEC_VC1: |
| // reference picture buffer |
| dpb_size = image_size * max_references; |
| // CONTEXT_BUFFER |
| dpb_size += width_in_mb * height_in_mb * 128; |
| // IT surface buffer |
| dpb_size += width_in_mb * 64; |
| // DB surface buffer |
| dpb_size += width_in_mb * 128; |
| // BP |
| dpb_size += align(MAX2(width_in_mb, height_in_mb) * 7 * 16, 64); |
| break; |
| case PIPE_VIDEO_CODEC_MPEG12: |
| // reference picture buffer, must be big enough for all frames |
| dpb_size = image_size * NUM_MPEG2_REFS; |
| break; |
| case PIPE_VIDEO_CODEC_MPEG4: |
| // reference picture buffer |
| dpb_size = image_size * max_references; |
| // CM |
| dpb_size += width_in_mb * height_in_mb * 64; |
| // IT surface buffer |
| dpb_size += align(width_in_mb * height_in_mb * 32, 64); |
| break; |
| default: |
| // something is missing here |
| assert(0); |
| // at least use a sane default value |
| dpb_size = 32 * 1024 * 1024; |
| break; |
| } |
| return dpb_size; |
| } |
| /* get h264 specific message bits */ |
| static struct ruvd_h264 get_h264_msg(struct ruvd_decoder *dec, struct pipe_h264_picture_desc *pic) |
| { |
| struct ruvd_h264 result; |
| memset(&result, 0, sizeof(result)); |
| switch (pic->base.profile) { |
| case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE: |
| result.profile = RUVD_H264_PROFILE_BASELINE; |
| break; |
| case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN: |
| result.profile = RUVD_H264_PROFILE_MAIN; |
| break; |
| case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH: |
| result.profile = RUVD_H264_PROFILE_HIGH; |
| break; |
| default: |
| assert(0); |
| break; |
| } |
| if (((dec->base.width * dec->base.height) >> 8) <= 1620) |
| result.level = 30; |
| else |
| result.level = 41; |
| result.sps_info_flags = 0; |
| result.sps_info_flags |= pic->direct_8x8_inference_flag << 0; |
| result.sps_info_flags |= pic->mb_adaptive_frame_field_flag << 1; |
| result.sps_info_flags |= pic->frame_mbs_only_flag << 2; |
| result.sps_info_flags |= pic->delta_pic_order_always_zero_flag << 3; |
| result.pps_info_flags = 0; |
| result.pps_info_flags |= pic->transform_8x8_mode_flag << 0; |
| result.pps_info_flags |= pic->redundant_pic_cnt_present_flag << 1; |
| result.pps_info_flags |= pic->constrained_intra_pred_flag << 2; |
| result.pps_info_flags |= pic->deblocking_filter_control_present_flag << 3; |
| result.pps_info_flags |= pic->weighted_bipred_idc << 4; |
| result.pps_info_flags |= pic->weighted_pred_flag << 6; |
| result.pps_info_flags |= pic->pic_order_present_flag << 7; |
| result.pps_info_flags |= pic->entropy_coding_mode_flag << 8; |
| result.chroma_format = 0x1; |
| result.bit_depth_luma_minus8 = 0; |
| result.bit_depth_chroma_minus8 = 0; |
| result.log2_max_frame_num_minus4 = pic->log2_max_frame_num_minus4; |
| result.pic_order_cnt_type = pic->pic_order_cnt_type; |
| result.log2_max_pic_order_cnt_lsb_minus4 = pic->log2_max_pic_order_cnt_lsb_minus4; |
| result.num_ref_frames = pic->num_ref_frames; |
| result.pic_init_qp_minus26 = pic->pic_init_qp_minus26; |
| result.chroma_qp_index_offset = pic->chroma_qp_index_offset; |
| result.second_chroma_qp_index_offset = pic->second_chroma_qp_index_offset; |
| result.num_slice_groups_minus1 = 0; |
| result.slice_group_map_type = 0; |
| result.num_ref_idx_l0_active_minus1 = pic->num_ref_idx_l0_active_minus1; |
| result.num_ref_idx_l1_active_minus1 = pic->num_ref_idx_l1_active_minus1; |
| result.slice_group_change_rate_minus1 = 0; |
| memcpy(result.scaling_list_4x4, pic->scaling_lists_4x4, 6*64); |
| memcpy(result.scaling_list_8x8, pic->scaling_lists_8x8, 2*64); |
| result.frame_num = pic->frame_num; |
| memcpy(result.frame_num_list, pic->frame_num_list, 4*16); |
| result.curr_field_order_cnt_list[0] = pic->field_order_cnt[0]; |
| result.curr_field_order_cnt_list[1] = pic->field_order_cnt[1]; |
| memcpy(result.field_order_cnt_list, pic->field_order_cnt_list, 4*16*2); |
| result.decoded_pic_idx = pic->frame_num; |
| return result; |
| } |
| /* get vc1 specific message bits */ |
| static struct ruvd_vc1 get_vc1_msg(struct pipe_vc1_picture_desc *pic) |
| { |
| struct ruvd_vc1 result; |
| memset(&result, 0, sizeof(result)); |
| switch(pic->base.profile) { |
| case PIPE_VIDEO_PROFILE_VC1_SIMPLE: |
| result.profile = RUVD_VC1_PROFILE_SIMPLE; |
| break; |
| case PIPE_VIDEO_PROFILE_VC1_MAIN: |
| result.profile = RUVD_VC1_PROFILE_MAIN; |
| break; |
| case PIPE_VIDEO_PROFILE_VC1_ADVANCED: |
| result.profile = RUVD_VC1_PROFILE_ADVANCED; |
| break; |
| default: |
| assert(0); |
| } |
| if (pic->base.profile == PIPE_VIDEO_PROFILE_VC1_ADVANCED) { |
| result.level = 0; |
| result.sps_info_flags |= pic->postprocflag << 7; |
| result.sps_info_flags |= pic->pulldown << 6; |
| result.sps_info_flags |= pic->interlace << 5; |
| result.sps_info_flags |= pic->tfcntrflag << 4; |
| result.sps_info_flags |= pic->psf << 1; |
| result.pps_info_flags |= pic->panscan_flag << 7; |
| result.pps_info_flags |= pic->refdist_flag << 6; |
| result.pps_info_flags |= pic->extended_dmv << 8; |
| result.pps_info_flags |= pic->range_mapy_flag << 31; |
| result.pps_info_flags |= pic->range_mapy << 28; |
| result.pps_info_flags |= pic->range_mapuv_flag << 27; |
| result.pps_info_flags |= pic->range_mapuv << 24; |
| } else { |
| result.level = 0; |
| result.pps_info_flags |= pic->multires << 21; |
| result.pps_info_flags |= pic->syncmarker << 20; |
| result.pps_info_flags |= pic->rangered << 19; |
| result.pps_info_flags |= pic->maxbframes << 16; |
| } |
| result.sps_info_flags |= pic->finterpflag << 3; |
| //(((unsigned int)(pPicParams->advance.reserved1)) << SPS_INFO_VC1_RESERVED_SHIFT) |
| result.pps_info_flags |= pic->loopfilter << 5; |
| result.pps_info_flags |= pic->fastuvmc << 4; |
| result.pps_info_flags |= pic->extended_mv << 3; |
| result.pps_info_flags |= pic->dquant << 1; |
| result.pps_info_flags |= pic->vstransform << 0; |
| result.pps_info_flags |= pic->overlap << 11; |
| result.pps_info_flags |= pic->quantizer << 9; |
| #if 0 |
| uint32_t slice_count |
| uint8_t picture_type |
| uint8_t frame_coding_mode |
| uint8_t deblockEnable |
| uint8_t pquant |
| #endif |
| result.chroma_format = 1; |
| return result; |
| } |
| /* extract the frame number from a referenced video buffer */ |
| static uint32_t get_ref_pic_idx(struct ruvd_decoder *dec, struct pipe_video_buffer *ref) |
| { |
| uint32_t min = dec->frame_number - NUM_MPEG2_REFS; |
| uint32_t max = dec->frame_number - 1; |
| uintptr_t frame; |
| /* seems to be the most sane fallback */ |
| if (!ref) |
| return max; |
| /* get the frame number from the associated data */ |
| frame = (uintptr_t)vl_video_buffer_get_associated_data(ref, &dec->base); |
| /* limit the frame number to a valid range */ |
| return MAX2(MIN2(frame, max), min); |
| } |
| /* get mpeg2 specific msg bits */ |
| static struct ruvd_mpeg2 get_mpeg2_msg(struct ruvd_decoder *dec, |
| struct pipe_mpeg12_picture_desc *pic) |
| { |
| const int *zscan = pic->alternate_scan ? vl_zscan_alternate : vl_zscan_normal; |
| struct ruvd_mpeg2 result; |
| unsigned i; |
| memset(&result, 0, sizeof(result)); |
| result.decoded_pic_idx = dec->frame_number; |
| for (i = 0; i < 2; ++i) |
| result.ref_pic_idx[i] = get_ref_pic_idx(dec, pic->ref[i]); |
| result.load_intra_quantiser_matrix = 1; |
| result.load_nonintra_quantiser_matrix = 1; |
| for (i = 0; i < 64; ++i) { |
| result.intra_quantiser_matrix[i] = pic->intra_matrix[zscan[i]]; |
| result.nonintra_quantiser_matrix[i] = pic->non_intra_matrix[zscan[i]]; |
| } |
| result.profile_and_level_indication = 0; |
| result.chroma_format = 0x1; |
| result.picture_coding_type = pic->picture_coding_type; |
| result.f_code[0][0] = pic->f_code[0][0] + 1; |
| result.f_code[0][1] = pic->f_code[0][1] + 1; |
| result.f_code[1][0] = pic->f_code[1][0] + 1; |
| result.f_code[1][1] = pic->f_code[1][1] + 1; |
| result.intra_dc_precision = pic->intra_dc_precision; |
| result.pic_structure = pic->picture_structure; |
| result.top_field_first = pic->top_field_first; |
| result.frame_pred_frame_dct = pic->frame_pred_frame_dct; |
| result.concealment_motion_vectors = pic->concealment_motion_vectors; |
| result.q_scale_type = pic->q_scale_type; |
| result.intra_vlc_format = pic->intra_vlc_format; |
| result.alternate_scan = pic->alternate_scan; |
| return result; |
| } |
| /* get mpeg4 specific msg bits */ |
| static struct ruvd_mpeg4 get_mpeg4_msg(struct ruvd_decoder *dec, |
| struct pipe_mpeg4_picture_desc *pic) |
| { |
| struct ruvd_mpeg4 result; |
| unsigned i; |
| memset(&result, 0, sizeof(result)); |
| result.decoded_pic_idx = dec->frame_number; |
| for (i = 0; i < 2; ++i) |
| result.ref_pic_idx[i] = get_ref_pic_idx(dec, pic->ref[i]); |
| result.variant_type = 0; |
| result.profile_and_level_indication = 0xF0; // ASP Level0 |
| result.video_object_layer_verid = 0x5; // advanced simple |
| result.video_object_layer_shape = 0x0; // rectangular |
| result.video_object_layer_width = dec->base.width; |
| result.video_object_layer_height = dec->base.height; |
| result.vop_time_increment_resolution = pic->vop_time_increment_resolution; |
| result.flags |= pic->short_video_header << 0; |
| //result.flags |= obmc_disable << 1; |
| result.flags |= pic->interlaced << 2; |
| result.flags |= 1 << 3; // load_intra_quant_mat |
| result.flags |= 1 << 4; // load_nonintra_quant_mat |
| result.flags |= pic->quarter_sample << 5; |
| result.flags |= 1 << 6; // complexity_estimation_disable |
| result.flags |= pic->resync_marker_disable << 7; |
| //result.flags |= data_partitioned << 8; |
| //result.flags |= reversible_vlc << 9; |
| result.flags |= 0 << 10; // newpred_enable |
| result.flags |= 0 << 11; // reduced_resolution_vop_enable |
| //result.flags |= scalability << 12; |
| //result.flags |= is_object_layer_identifier << 13; |
| //result.flags |= fixed_vop_rate << 14; |
| //result.flags |= newpred_segment_type << 15; |
| result.quant_type = pic->quant_type; |
| for (i = 0; i < 64; ++i) { |
| result.intra_quant_mat[i] = pic->intra_matrix[vl_zscan_normal[i]]; |
| result.nonintra_quant_mat[i] = pic->non_intra_matrix[vl_zscan_normal[i]]; |
| } |
| /* |
| int32_t trd [2] |
| int32_t trb [2] |
| uint8_t vop_coding_type |
| uint8_t vop_fcode_forward |
| uint8_t vop_fcode_backward |
| uint8_t rounding_control |
| uint8_t alternate_vertical_scan_flag |
| uint8_t top_field_first |
| */ |
| return result; |
| } |
| /** |
| * destroy this video decoder |
| */ |
| static void ruvd_destroy(struct pipe_video_decoder *decoder) |
| { |
| struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder; |
| struct ruvd_msg msg; |
| unsigned i; |
| assert(decoder); |
| memset(&msg, 0, sizeof(msg)); |
| msg.size = sizeof(msg); |
| msg.msg_type = RUVD_MSG_DESTROY; |
| msg.stream_handle = dec->stream_handle; |
| send_msg(dec, &msg); |
| flush(dec); |
| dec->ws->cs_destroy(dec->cs); |
| for (i = 0; i < NUM_BUFFERS; ++i) { |
| destroy_buffer(&dec->msg_fb_buffers[i]); |
| destroy_buffer(&dec->bs_buffers[i]); |
| } |
| destroy_buffer(&dec->dpb); |
| FREE(dec); |
| } |
| /* free associated data in the video buffer callback */ |
| static void ruvd_destroy_associated_data(void *data) |
| { |
| /* NOOP, since we only use an intptr */ |
| } |
| /** |
| * start decoding of a new frame |
| */ |
| static void ruvd_begin_frame(struct pipe_video_decoder *decoder, |
| struct pipe_video_buffer *target, |
| struct pipe_picture_desc *picture) |
| { |
| struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder; |
| uintptr_t frame; |
| assert(decoder); |
| frame = ++dec->frame_number; |
| vl_video_buffer_set_associated_data(target, decoder, (void *)frame, |
| &ruvd_destroy_associated_data); |
| dec->bs_size = 0; |
| dec->bs_ptr = dec->ws->buffer_map( |
| dec->bs_buffers[dec->cur_buffer].cs_handle, |
| dec->cs, PIPE_TRANSFER_WRITE); |
| } |
| /** |
| * decode a macroblock |
| */ |
| static void ruvd_decode_macroblock(struct pipe_video_decoder *decoder, |
| struct pipe_video_buffer *target, |
| struct pipe_picture_desc *picture, |
| const struct pipe_macroblock *macroblocks, |
| unsigned num_macroblocks) |
| { |
| /* not supported (yet) */ |
| assert(0); |
| } |
| /** |
| * decode a bitstream |
| */ |
| static void ruvd_decode_bitstream(struct pipe_video_decoder *decoder, |
| struct pipe_video_buffer *target, |
| struct pipe_picture_desc *picture, |
| unsigned num_buffers, |
| const void * const *buffers, |
| const unsigned *sizes) |
| { |
| struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder; |
| unsigned i; |
| assert(decoder); |
| if (!dec->bs_ptr) |
| return; |
| for (i = 0; i < num_buffers; ++i) { |
| struct ruvd_buffer *buf = &dec->bs_buffers[dec->cur_buffer]; |
| unsigned new_size = dec->bs_size + sizes[i]; |
| if (new_size > buf->buf->size) { |
| dec->ws->buffer_unmap(buf->cs_handle); |
| if (!resize_buffer(dec, buf, new_size)) { |
| RUVD_ERR("Can't resize bitstream buffer!"); |
| return; |
| } |
| dec->bs_ptr = dec->ws->buffer_map(buf->cs_handle, dec->cs, |
| PIPE_TRANSFER_WRITE); |
| if (!dec->bs_ptr) |
| return; |
| dec->bs_ptr += dec->bs_size; |
| } |
| memcpy(dec->bs_ptr, buffers[i], sizes[i]); |
| dec->bs_size += sizes[i]; |
| dec->bs_ptr += sizes[i]; |
| } |
| } |
| /** |
| * end decoding of the current frame |
| */ |
| static void ruvd_end_frame(struct pipe_video_decoder *decoder, |
| struct pipe_video_buffer *target, |
| struct pipe_picture_desc *picture) |
| { |
| struct ruvd_decoder *dec = (struct ruvd_decoder*)decoder; |
| struct radeon_winsys_cs_handle *dt; |
| struct ruvd_buffer *msg_fb_buf, *bs_buf; |
| struct ruvd_msg msg; |
| unsigned bs_size; |
| assert(decoder); |
| if (!dec->bs_ptr) |
| return; |
| msg_fb_buf = &dec->msg_fb_buffers[dec->cur_buffer]; |
| bs_buf = &dec->bs_buffers[dec->cur_buffer]; |
| bs_size = align(dec->bs_size, 128); |
| memset(dec->bs_ptr, 0, bs_size - dec->bs_size); |
| dec->ws->buffer_unmap(bs_buf->cs_handle); |
| memset(&msg, 0, sizeof(msg)); |
| msg.size = sizeof(msg); |
| msg.msg_type = RUVD_MSG_DECODE; |
| msg.stream_handle = dec->stream_handle; |
| msg.status_report_feedback_number = dec->frame_number; |
| msg.body.decode.stream_type = profile2stream_type(dec->base.profile); |
| msg.body.decode.decode_flags = 0x1; |
| msg.body.decode.width_in_samples = dec->base.width; |
| msg.body.decode.height_in_samples = dec->base.height; |
| msg.body.decode.dpb_size = dec->dpb.buf->size; |
| msg.body.decode.bsd_size = bs_size; |
| dt = dec->set_dtb(&msg, (struct vl_video_buffer *)target); |
| switch (u_reduce_video_profile(picture->profile)) { |
| case PIPE_VIDEO_CODEC_MPEG4_AVC: |
| msg.body.decode.codec.h264 = get_h264_msg(dec, (struct pipe_h264_picture_desc*)picture); |
| break; |
| case PIPE_VIDEO_CODEC_VC1: |
| msg.body.decode.codec.vc1 = get_vc1_msg((struct pipe_vc1_picture_desc*)picture); |
| break; |
| case PIPE_VIDEO_CODEC_MPEG12: |
| msg.body.decode.codec.mpeg2 = get_mpeg2_msg(dec, (struct pipe_mpeg12_picture_desc*)picture); |
| break; |
| case PIPE_VIDEO_CODEC_MPEG4: |
| msg.body.decode.codec.mpeg4 = get_mpeg4_msg(dec, (struct pipe_mpeg4_picture_desc*)picture); |
| break; |
| default: |
| assert(0); |
| return; |
| } |
| msg.body.decode.db_surf_tile_config = msg.body.decode.dt_surf_tile_config; |
| msg.body.decode.extension_support = 0x1; |
| send_msg(dec, &msg); |
| send_cmd(dec, RUVD_CMD_DPB_BUFFER, dec->dpb.cs_handle, 0, |
| RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM); |
| send_cmd(dec, RUVD_CMD_BITSTREAM_BUFFER, bs_buf->cs_handle, |
| 0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT); |
| send_cmd(dec, RUVD_CMD_DECODING_TARGET_BUFFER, dt, 0, |
| RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM); |
| send_cmd(dec, RUVD_CMD_FEEDBACK_BUFFER, msg_fb_buf->cs_handle, |
| 0x1000, RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM); |
| set_reg(dec, RUVD_ENGINE_CNTL, 1); |
| flush(dec); |
| next_buffer(dec); |
| } |
| /** |
| * flush any outstanding command buffers to the hardware |
| */ |
| static void ruvd_flush(struct pipe_video_decoder *decoder) |
| { |
| } |
| /** |
| * create and UVD decoder |
| */ |
| struct pipe_video_decoder *ruvd_create_decoder(struct pipe_context *context, |
| enum pipe_video_profile profile, |
| enum pipe_video_entrypoint entrypoint, |
| enum pipe_video_chroma_format chroma_format, |
| unsigned width, unsigned height, |
| unsigned max_references, bool expect_chunked_decode, |
| struct radeon_winsys* ws, |
| ruvd_set_dtb set_dtb) |
| { |
| unsigned dpb_size = calc_dpb_size(profile, width, height, max_references); |
| struct radeon_info info; |
| struct ruvd_decoder *dec; |
| struct ruvd_msg msg; |
| int i; |
| ws->query_info(ws, &info); |
| switch(u_reduce_video_profile(profile)) { |
| case PIPE_VIDEO_CODEC_MPEG12: |
| if (entrypoint > PIPE_VIDEO_ENTRYPOINT_BITSTREAM || info.family < CHIP_PALM) |
| return vl_create_mpeg12_decoder(context, profile, entrypoint, |
| chroma_format, width, |
| height, max_references, expect_chunked_decode); |
| /* fall through */ |
| case PIPE_VIDEO_CODEC_MPEG4: |
| case PIPE_VIDEO_CODEC_MPEG4_AVC: |
| width = align(width, VL_MACROBLOCK_WIDTH); |
| height = align(height, VL_MACROBLOCK_HEIGHT); |
| break; |
| default: |
| break; |
| } |
| dec = CALLOC_STRUCT(ruvd_decoder); |
| if (!dec) |
| return NULL; |
| dec->base.context = context; |
| dec->base.profile = profile; |
| dec->base.entrypoint = entrypoint; |
| dec->base.chroma_format = chroma_format; |
| dec->base.width = width; |
| dec->base.height = height; |
| dec->base.destroy = ruvd_destroy; |
| dec->base.begin_frame = ruvd_begin_frame; |
| dec->base.decode_macroblock = ruvd_decode_macroblock; |
| dec->base.decode_bitstream = ruvd_decode_bitstream; |
| dec->base.end_frame = ruvd_end_frame; |
| dec->base.flush = ruvd_flush; |
| dec->set_dtb = set_dtb; |
| dec->stream_handle = alloc_stream_handle(); |
| dec->ws = ws; |
| dec->cs = ws->cs_create(ws, RING_UVD, NULL); |
| if (!dec->cs) { |
| RUVD_ERR("Can't get command submission context.\n"); |
| goto error; |
| } |
| for (i = 0; i < NUM_BUFFERS; ++i) { |
| unsigned msg_fb_size = align(sizeof(struct ruvd_msg), 0x1000) + 0x1000; |
| if (!create_buffer(dec, &dec->msg_fb_buffers[i], msg_fb_size)) { |
| RUVD_ERR("Can't allocated message buffers.\n"); |
| goto error; |
| } |
| if (!create_buffer(dec, &dec->bs_buffers[i], 4096)) { |
| RUVD_ERR("Can't allocated bitstream buffers.\n"); |
| goto error; |
| } |
| clear_buffer(dec, &dec->msg_fb_buffers[i]); |
| clear_buffer(dec, &dec->bs_buffers[i]); |
| } |
| if (!create_buffer(dec, &dec->dpb, dpb_size)) { |
| RUVD_ERR("Can't allocated dpb.\n"); |
| goto error; |
| } |
| clear_buffer(dec, &dec->dpb); |
| memset(&msg, 0, sizeof(msg)); |
| msg.size = sizeof(msg); |
| msg.msg_type = RUVD_MSG_CREATE; |
| msg.stream_handle = dec->stream_handle; |
| msg.body.create.stream_type = profile2stream_type(dec->base.profile); |
| msg.body.create.width_in_samples = dec->base.width; |
| msg.body.create.height_in_samples = dec->base.height; |
| msg.body.create.dpb_size = dec->dpb.buf->size; |
| send_msg(dec, &msg); |
| flush(dec); |
| next_buffer(dec); |
| return &dec->base; |
| error: |
| if (dec->cs) dec->ws->cs_destroy(dec->cs); |
| for (i = 0; i < NUM_BUFFERS; ++i) { |
| destroy_buffer(&dec->msg_fb_buffers[i]); |
| destroy_buffer(&dec->bs_buffers[i]); |
| } |
| destroy_buffer(&dec->dpb); |
| FREE(dec); |
| return NULL; |
| } |
| /** |
| * join surfaces into the same buffer with identical tiling params |
| * sumup their sizes and replace the backend buffers with a single bo |
| */ |
| void ruvd_join_surfaces(struct radeon_winsys* ws, unsigned bind, |
| struct pb_buffer** buffers[VL_NUM_COMPONENTS], |
| struct radeon_surface *surfaces[VL_NUM_COMPONENTS]) |
| { |
| unsigned best_tiling, best_wh, off; |
| unsigned size, alignment; |
| struct pb_buffer *pb; |
| unsigned i, j; |
| for (i = 0, best_tiling = 0, best_wh = ~0; i < VL_NUM_COMPONENTS; ++i) { |
| unsigned wh; |
| if (!surfaces[i]) |
| continue; |
| /* choose the smallest bank w/h for now */ |
| wh = surfaces[i]->bankw * surfaces[i]->bankh; |
| if (wh < best_wh) { |
| best_wh = wh; |
| best_tiling = i; |
| } |
| } |
| for (i = 0, off = 0; i < VL_NUM_COMPONENTS; ++i) { |
| if (!surfaces[i]) |
| continue; |
| /* copy the tiling parameters */ |
| surfaces[i]->bankw = surfaces[best_tiling]->bankw; |
| surfaces[i]->bankh = surfaces[best_tiling]->bankh; |
| surfaces[i]->mtilea = surfaces[best_tiling]->mtilea; |
| surfaces[i]->tile_split = surfaces[best_tiling]->tile_split; |
| /* adjust the texture layer offsets */ |
| off = align(off, surfaces[i]->bo_alignment); |
| for (j = 0; j < Elements(surfaces[i]->level); ++j) |
| surfaces[i]->level[j].offset += off; |
| off += surfaces[i]->bo_size; |
| } |
| for (i = 0, size = 0, alignment = 0; i < VL_NUM_COMPONENTS; ++i) { |
| if (!buffers[i] || !*buffers[i]) |
| continue; |
| size = align(size, (*buffers[i])->alignment); |
| size += (*buffers[i])->size; |
| alignment = MAX2(alignment, (*buffers[i])->alignment * 1); |
| } |
| if (!size) |
| return; |
| /* TODO: 2D tiling workaround */ |
| alignment *= 2; |
| pb = ws->buffer_create(ws, size, alignment, bind, RADEON_DOMAIN_VRAM); |
| if (!pb) |
| return; |
| for (i = 0; i < VL_NUM_COMPONENTS; ++i) { |
| if (!buffers[i] || !*buffers[i]) |
| continue; |
| pb_reference(buffers[i], pb); |
| } |
| pb_reference(&pb, NULL); |
| } |
| /* calculate top/bottom offset */ |
| static unsigned texture_offset(struct radeon_surface *surface, unsigned layer) |
| { |
| return surface->level[0].offset + |
| layer * surface->level[0].slice_size; |
| } |
| /* hw encode the aspect of macro tiles */ |
| static unsigned macro_tile_aspect(unsigned macro_tile_aspect) |
| { |
| switch (macro_tile_aspect) { |
| default: |
| case 1: macro_tile_aspect = 0; break; |
| case 2: macro_tile_aspect = 1; break; |
| case 4: macro_tile_aspect = 2; break; |
| case 8: macro_tile_aspect = 3; break; |
| } |
| return macro_tile_aspect; |
| } |
| /* hw encode the bank width and height */ |
| static unsigned bank_wh(unsigned bankwh) |
| { |
| switch (bankwh) { |
| default: |
| case 1: bankwh = 0; break; |
| case 2: bankwh = 1; break; |
| case 4: bankwh = 2; break; |
| case 8: bankwh = 3; break; |
| } |
| return bankwh; |
| } |
| /** |
| * fill decoding target field from the luma and chroma surfaces |
| */ |
| void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surface *luma, |
| struct radeon_surface *chroma) |
| { |
| msg->body.decode.dt_pitch = luma->level[0].pitch_bytes; |
| switch (luma->level[0].mode) { |
| case RADEON_SURF_MODE_LINEAR_ALIGNED: |
| msg->body.decode.dt_tiling_mode = RUVD_TILE_LINEAR; |
| msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_LINEAR; |
| break; |
| case RADEON_SURF_MODE_1D: |
| msg->body.decode.dt_tiling_mode = RUVD_TILE_8X8; |
| msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_1D_THIN; |
| break; |
| case RADEON_SURF_MODE_2D: |
| msg->body.decode.dt_tiling_mode = RUVD_TILE_8X8; |
| msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_2D_THIN; |
| break; |
| default: |
| assert(0); |
| break; |
| } |
| msg->body.decode.dt_luma_top_offset = texture_offset(luma, 0); |
| msg->body.decode.dt_chroma_top_offset = texture_offset(chroma, 0); |
| if (msg->body.decode.dt_field_mode) { |
| msg->body.decode.dt_luma_bottom_offset = texture_offset(luma, 1); |
| msg->body.decode.dt_chroma_bottom_offset = texture_offset(chroma, 1); |
| } else { |
| msg->body.decode.dt_luma_bottom_offset = msg->body.decode.dt_luma_top_offset; |
| msg->body.decode.dt_chroma_bottom_offset = msg->body.decode.dt_chroma_top_offset; |
| } |
| assert(luma->bankw == chroma->bankw); |
| assert(luma->bankh == chroma->bankh); |
| assert(luma->mtilea == chroma->mtilea); |
| msg->body.decode.dt_surf_tile_config |= RUVD_BANK_WIDTH(bank_wh(luma->bankw)); |
| msg->body.decode.dt_surf_tile_config |= RUVD_BANK_HEIGHT(bank_wh(luma->bankh)); |
| msg->body.decode.dt_surf_tile_config |= RUVD_MACRO_TILE_ASPECT_RATIO(macro_tile_aspect(luma->mtilea)); |
| } |
| int ruvd_get_video_param(struct pipe_screen *screen, |
| enum pipe_video_profile profile, |
| enum pipe_video_cap param) |
| { |
| switch (param) { |
| case PIPE_VIDEO_CAP_SUPPORTED: |
| switch (u_reduce_video_profile(profile)) { |
| case PIPE_VIDEO_CODEC_MPEG12: |
| case PIPE_VIDEO_CODEC_MPEG4: |
| case PIPE_VIDEO_CODEC_MPEG4_AVC: |
| case PIPE_VIDEO_CODEC_VC1: |
| return true; |
| default: |
| return false; |
| } |
| case PIPE_VIDEO_CAP_NPOT_TEXTURES: |
| return 1; |
| case PIPE_VIDEO_CAP_MAX_WIDTH: |
| return 2048; |
| case PIPE_VIDEO_CAP_MAX_HEIGHT: |
| return 1152; |
| case PIPE_VIDEO_CAP_PREFERED_FORMAT: |
| return PIPE_FORMAT_NV12; |
| case PIPE_VIDEO_CAP_PREFERS_INTERLACED: |
| return true; |
| case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: |
| return true; |
| case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE: |
| return true; |
| default: |
| return 0; |
| } |
| } |
| boolean ruvd_is_format_supported(struct pipe_screen *screen, |
| enum pipe_format format, |
| enum pipe_video_profile profile) |
| { |
| /* we can only handle this one anyway */ |
| return format == PIPE_FORMAT_NV12; |
| } |
| /contrib/sdk/sources/Mesa/mesa-9.2.5/src/gallium/drivers/radeon/radeon_uvd.h |
|---|
| 0,0 → 1,377 |
| /************************************************************************** |
| * |
| * Copyright 2011 Advanced Micro Devices, Inc. |
| * All Rights Reserved. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the |
| * "Software"), to deal in the Software without restriction, including |
| * without limitation the rights to use, copy, modify, merge, publish, |
| * distribute, sub license, and/or sell copies of the Software, and to |
| * permit persons to whom the Software is furnished to do so, subject to |
| * the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the |
| * next paragraph) shall be included in all copies or substantial portions |
| * of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR |
| * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| * |
| **************************************************************************/ |
| /* |
| * Authors: |
| * Christian König <christian.koenig@amd.com> |
| * |
| */ |
| #ifndef RADEON_UVD_H |
| #define RADEON_UVD_H |
| /* UVD uses PM4 packet type 0 and 2 */ |
| #define RUVD_PKT_TYPE_S(x) (((x) & 0x3) << 30) |
| #define RUVD_PKT_TYPE_G(x) (((x) >> 30) & 0x3) |
| #define RUVD_PKT_TYPE_C 0x3FFFFFFF |
| #define RUVD_PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) |
| #define RUVD_PKT_COUNT_G(x) (((x) >> 16) & 0x3FFF) |
| #define RUVD_PKT_COUNT_C 0xC000FFFF |
| #define RUVD_PKT0_BASE_INDEX_S(x) (((x) & 0xFFFF) << 0) |
| #define RUVD_PKT0_BASE_INDEX_G(x) (((x) >> 0) & 0xFFFF) |
| #define RUVD_PKT0_BASE_INDEX_C 0xFFFF0000 |
| #define RUVD_PKT0(index, count) (RUVD_PKT_TYPE_S(0) | RUVD_PKT0_BASE_INDEX_S(index) | RUVD_PKT_COUNT_S(count)) |
| #define RUVD_PKT2() (RUVD_PKT_TYPE_S(2)) |
| /* registers involved with UVD */ |
| #define RUVD_GPCOM_VCPU_CMD 0xEF0C |
| #define RUVD_GPCOM_VCPU_DATA0 0xEF10 |
| #define RUVD_GPCOM_VCPU_DATA1 0xEF14 |
| #define RUVD_ENGINE_CNTL 0xEF18 |
| /* UVD commands to VCPU */ |
| #define RUVD_CMD_MSG_BUFFER 0x00000000 |
| #define RUVD_CMD_DPB_BUFFER 0x00000001 |
| #define RUVD_CMD_DECODING_TARGET_BUFFER 0x00000002 |
| #define RUVD_CMD_FEEDBACK_BUFFER 0x00000003 |
| #define RUVD_CMD_BITSTREAM_BUFFER 0x00000100 |
| /* UVD message types */ |
| #define RUVD_MSG_CREATE 0 |
| #define RUVD_MSG_DECODE 1 |
| #define RUVD_MSG_DESTROY 2 |
| /* UVD stream types */ |
| #define RUVD_CODEC_H264 0x00000000 |
| #define RUVD_CODEC_VC1 0x00000001 |
| #define RUVD_CODEC_MPEG2 0x00000003 |
| #define RUVD_CODEC_MPEG4 0x00000004 |
| /* UVD decode target buffer tiling mode */ |
| #define RUVD_TILE_LINEAR 0x00000000 |
| #define RUVD_TILE_8X4 0x00000001 |
| #define RUVD_TILE_8X8 0x00000002 |
| #define RUVD_TILE_32AS8 0x00000003 |
| /* UVD decode target buffer array mode */ |
| #define RUVD_ARRAY_MODE_LINEAR 0x00000000 |
| #define RUVD_ARRAY_MODE_MACRO_LINEAR_MICRO_TILED 0x00000001 |
| #define RUVD_ARRAY_MODE_1D_THIN 0x00000002 |
| #define RUVD_ARRAY_MODE_2D_THIN 0x00000004 |
| #define RUVD_ARRAY_MODE_MACRO_TILED_MICRO_LINEAR 0x00000004 |
| #define RUVD_ARRAY_MODE_MACRO_TILED_MICRO_TILED 0x00000005 |
| /* UVD tile config */ |
| #define RUVD_BANK_WIDTH(x) ((x) << 0) |
| #define RUVD_BANK_HEIGHT(x) ((x) << 3) |
| #define RUVD_MACRO_TILE_ASPECT_RATIO(x) ((x) << 6) |
| #define RUVD_NUM_BANKS(x) ((x) << 9) |
| /* H.264 profile definitions */ |
| #define RUVD_H264_PROFILE_BASELINE 0x00000000 |
| #define RUVD_H264_PROFILE_MAIN 0x00000001 |
| #define RUVD_H264_PROFILE_HIGH 0x00000002 |
| #define RUVD_H264_PROFILE_STEREO_HIGH 0x00000003 |
| #define RUVD_H264_PROFILE_MVC 0x00000004 |
| /* VC-1 profile definitions */ |
| #define RUVD_VC1_PROFILE_SIMPLE 0x00000000 |
| #define RUVD_VC1_PROFILE_MAIN 0x00000001 |
| #define RUVD_VC1_PROFILE_ADVANCED 0x00000002 |
| struct ruvd_mvc_element { |
| uint16_t viewOrderIndex; |
| uint16_t viewId; |
| uint16_t numOfAnchorRefsInL0; |
| uint16_t viewIdOfAnchorRefsInL0[15]; |
| uint16_t numOfAnchorRefsInL1; |
| uint16_t viewIdOfAnchorRefsInL1[15]; |
| uint16_t numOfNonAnchorRefsInL0; |
| uint16_t viewIdOfNonAnchorRefsInL0[15]; |
| uint16_t numOfNonAnchorRefsInL1; |
| uint16_t viewIdOfNonAnchorRefsInL1[15]; |
| }; |
| struct ruvd_h264 { |
| uint32_t profile; |
| uint32_t level; |
| uint32_t sps_info_flags; |
| uint32_t pps_info_flags; |
| uint8_t chroma_format; |
| uint8_t bit_depth_luma_minus8; |
| uint8_t bit_depth_chroma_minus8; |
| uint8_t log2_max_frame_num_minus4; |
| uint8_t pic_order_cnt_type; |
| uint8_t log2_max_pic_order_cnt_lsb_minus4; |
| uint8_t num_ref_frames; |
| uint8_t reserved_8bit; |
| int8_t pic_init_qp_minus26; |
| int8_t pic_init_qs_minus26; |
| int8_t chroma_qp_index_offset; |
| int8_t second_chroma_qp_index_offset; |
| uint8_t num_slice_groups_minus1; |
| uint8_t slice_group_map_type; |
| uint8_t num_ref_idx_l0_active_minus1; |
| uint8_t num_ref_idx_l1_active_minus1; |
| uint16_t slice_group_change_rate_minus1; |
| uint16_t reserved_16bit_1; |
| uint8_t scaling_list_4x4[6][16]; |
| uint8_t scaling_list_8x8[2][64]; |
| uint32_t frame_num; |
| uint32_t frame_num_list[16]; |
| int32_t curr_field_order_cnt_list[2]; |
| int32_t field_order_cnt_list[16][2]; |
| uint32_t decoded_pic_idx; |
| uint32_t curr_pic_ref_frame_num; |
| uint8_t ref_frame_list[16]; |
| uint32_t reserved[122]; |
| struct { |
| uint32_t numViews; |
| uint32_t viewId0; |
| struct ruvd_mvc_element mvcElements[1]; |
| } mvc; |
| }; |
| struct ruvd_vc1 { |
| uint32_t profile; |
| uint32_t level; |
| uint32_t sps_info_flags; |
| uint32_t pps_info_flags; |
| uint32_t pic_structure; |
| uint32_t chroma_format; |
| }; |
| struct ruvd_mpeg2 { |
| uint32_t decoded_pic_idx; |
| uint32_t ref_pic_idx[2]; |
| uint8_t load_intra_quantiser_matrix; |
| uint8_t load_nonintra_quantiser_matrix; |
| uint8_t reserved_quantiser_alignement[2]; |
| uint8_t intra_quantiser_matrix[64]; |
| uint8_t nonintra_quantiser_matrix[64]; |
| uint8_t profile_and_level_indication; |
| uint8_t chroma_format; |
| uint8_t picture_coding_type; |
| uint8_t reserved_1; |
| uint8_t f_code[2][2]; |
| uint8_t intra_dc_precision; |
| uint8_t pic_structure; |
| uint8_t top_field_first; |
| uint8_t frame_pred_frame_dct; |
| uint8_t concealment_motion_vectors; |
| uint8_t q_scale_type; |
| uint8_t intra_vlc_format; |
| uint8_t alternate_scan; |
| }; |
| struct ruvd_mpeg4 |
| { |
| uint32_t decoded_pic_idx; |
| uint32_t ref_pic_idx[2]; |
| uint32_t variant_type; |
| uint8_t profile_and_level_indication; |
| uint8_t video_object_layer_verid; |
| uint8_t video_object_layer_shape; |
| uint8_t reserved_1; |
| uint16_t video_object_layer_width; |
| uint16_t video_object_layer_height; |
| uint16_t vop_time_increment_resolution; |
| uint16_t reserved_2; |
| uint32_t flags; |
| uint8_t quant_type; |
| uint8_t reserved_3[3]; |
| uint8_t intra_quant_mat[64]; |
| uint8_t nonintra_quant_mat[64]; |
| struct { |
| uint8_t sprite_enable; |
| uint8_t reserved_4[3]; |
| uint16_t sprite_width; |
| uint16_t sprite_height; |
| int16_t sprite_left_coordinate; |
| int16_t sprite_top_coordinate; |
| uint8_t no_of_sprite_warping_points; |
| uint8_t sprite_warping_accuracy; |
| uint8_t sprite_brightness_change; |
| uint8_t low_latency_sprite_enable; |
| } sprite_config; |
| struct { |
| uint32_t flags; |
| uint8_t vol_mode; |
| uint8_t reserved_5[3]; |
| } divx_311_config; |
| }; |
| /* message between driver and hardware */ |
| struct ruvd_msg { |
| uint32_t size; |
| uint32_t msg_type; |
| uint32_t stream_handle; |
| uint32_t status_report_feedback_number; |
| union { |
| struct { |
| uint32_t stream_type; |
| uint32_t session_flags; |
| uint32_t asic_id; |
| uint32_t width_in_samples; |
| uint32_t height_in_samples; |
| uint32_t dpb_buffer; |
| uint32_t dpb_size; |
| uint32_t dpb_model; |
| uint32_t version_info; |
| } create; |
| struct { |
| uint32_t stream_type; |
| uint32_t decode_flags; |
| uint32_t width_in_samples; |
| uint32_t height_in_samples; |
| uint32_t dpb_buffer; |
| uint32_t dpb_size; |
| uint32_t dpb_model; |
| uint32_t dpb_reserved; |
| uint32_t db_offset_alignment; |
| uint32_t db_pitch; |
| uint32_t db_tiling_mode; |
| uint32_t db_array_mode; |
| uint32_t db_field_mode; |
| uint32_t db_surf_tile_config; |
| uint32_t db_aligned_height; |
| uint32_t db_reserved; |
| uint32_t use_addr_macro; |
| uint32_t bsd_buffer; |
| uint32_t bsd_size; |
| uint32_t pic_param_buffer; |
| uint32_t pic_param_size; |
| uint32_t mb_cntl_buffer; |
| uint32_t mb_cntl_size; |
| uint32_t dt_buffer; |
| uint32_t dt_pitch; |
| uint32_t dt_tiling_mode; |
| uint32_t dt_array_mode; |
| uint32_t dt_field_mode; |
| uint32_t dt_luma_top_offset; |
| uint32_t dt_luma_bottom_offset; |
| uint32_t dt_chroma_top_offset; |
| uint32_t dt_chroma_bottom_offset; |
| uint32_t dt_surf_tile_config; |
| uint32_t dt_reserved[3]; |
| uint32_t reserved[16]; |
| union { |
| struct ruvd_h264 h264; |
| struct ruvd_vc1 vc1; |
| struct ruvd_mpeg2 mpeg2; |
| struct ruvd_mpeg4 mpeg4; |
| uint32_t info[768]; |
| } codec; |
| uint8_t extension_support; |
| uint8_t reserved_8bit_1; |
| uint8_t reserved_8bit_2; |
| uint8_t reserved_8bit_3; |
| uint32_t extension_reserved[64]; |
| } decode; |
| } body; |
| }; |
| /* driver dependent callback */ |
| typedef struct radeon_winsys_cs_handle* (*ruvd_set_dtb) |
| (struct ruvd_msg* msg, struct vl_video_buffer *vb); |
| /* create an UVD decode */ |
| struct pipe_video_decoder *ruvd_create_decoder(struct pipe_context *context, |
| enum pipe_video_profile profile, |
| enum pipe_video_entrypoint entrypoint, |
| enum pipe_video_chroma_format chroma_format, |
| unsigned width, unsigned height, |
| unsigned max_references, bool expect_chunked_decode, |
| struct radeon_winsys* ws, |
| ruvd_set_dtb set_dtb); |
| /* join surfaces into the same buffer with identical tiling params |
| sumup their sizes and replace the backend buffers with a single bo */ |
| void ruvd_join_surfaces(struct radeon_winsys* ws, unsigned bind, |
| struct pb_buffer** buffers[VL_NUM_COMPONENTS], |
| struct radeon_surface *surfaces[VL_NUM_COMPONENTS]); |
| /* fill decoding target field from the luma and chroma surfaces */ |
| void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surface *luma, |
| struct radeon_surface *chroma); |
| /* returns supported codecs and other parameters */ |
| int ruvd_get_video_param(struct pipe_screen *screen, |
| enum pipe_video_profile profile, |
| enum pipe_video_cap param); |
| /* the hardware only supports NV12 */ |
| boolean ruvd_is_format_supported(struct pipe_screen *screen, |
| enum pipe_format format, |
| enum pipe_video_profile profile); |
| #endif |