Rev 877 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
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811 | serge | 1 | |
2 | |||
3 | |||
4 | //#define FINISH_ACCEL() ADVANCE_RING() |
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5 | #define FINISH_ACCEL() COMMIT_RING() |
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6 | |||
7 | |||
8 | |||
9 | |||
813 | serge | 10 | do { \ |
11 | u32_t wait_until = 0; \ |
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12 | BEGIN_ACCEL(1); \ |
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13 | wait_until |= RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN; \ |
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14 | OUT_ACCEL_REG(RADEON_WAIT_UNTIL, wait_until); \ |
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15 | FINISH_ACCEL(); \ |
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16 | } while (0); |
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17 | |||
811 | serge | 18 | |
19 | |||
813 | serge | 20 | Bool dst_alpha; |
21 | Bool src_alpha; |
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22 | u32_t blend_cntl; |
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23 | }; |
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24 | |||
25 | |||
26 | /* 0 - Clear */ |
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27 | {0, 0, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ZERO}, |
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28 | /* 1 - Src */ |
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29 | {0, 0, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO}, |
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30 | /* 2 - Dst */ |
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31 | {0, 0, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ONE}, |
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32 | /* 3 - Over */ |
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33 | {0, 1, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
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34 | /* 4 - OverReverse */ |
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35 | {1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ONE}, |
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36 | /* 5 - In */ |
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37 | {1, 0, RADEON_SRC_BLEND_GL_DST_ALPHA | RADEON_DST_BLEND_GL_ZERO}, |
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38 | /* 6 - InReverse */ |
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39 | {0, 1, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_SRC_ALPHA}, |
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40 | /* 7 - Out */ |
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41 | {1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ZERO}, |
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42 | /* 8 - OutReverse */ |
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43 | {0, 1, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
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44 | /* 9 - Atop */ |
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45 | {1, 1, RADEON_SRC_BLEND_GL_DST_ALPHA | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
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46 | /* 10- AtopReverse */ |
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47 | {1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_SRC_ALPHA}, |
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48 | /* 11 - Xor */ |
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49 | {1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
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50 | /* 12 - Add */ |
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51 | {0, 0, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ONE}, |
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52 | }; |
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53 | |||
54 | |||
55 | |||
811 | serge | 56 | { |
57 | // RADEONInfoPtr info = RADEONPTR(pScrn); |
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58 | u32_t gb_tile_config, su_reg_dest, vap_cntl; |
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59 | // ACCEL_PREAMBLE(); |
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60 | |||
61 | |||
877 | serge | 62 | |
811 | serge | 63 | |
64 | |||
65 | |||
813 | serge | 66 | { |
67 | |||
811 | serge | 68 | |
69 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
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70 | OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
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71 | OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
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72 | FINISH_ACCEL(); |
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73 | |||
74 | |||
813 | serge | 75 | { |
76 | u32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT); |
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77 | |||
78 | |||
79 | RADEONOUTPLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); |
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80 | } |
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81 | |||
82 | |||
83 | |||
84 | |||
811 | serge | 85 | |
86 | |||
87 | case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; |
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88 | case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; |
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89 | case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; |
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90 | default: |
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91 | case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; |
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92 | } |
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93 | |||
94 | |||
95 | OUT_ACCEL_REG(R300_GB_TILE_CONFIG, gb_tile_config); |
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96 | OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
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97 | OUT_ACCEL_REG(R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG); |
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98 | OUT_ACCEL_REG(R300_GB_SELECT, 0); |
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99 | OUT_ACCEL_REG(R300_GB_ENABLE, 0); |
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100 | FINISH_ACCEL(); |
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101 | |||
102 | |||
103 | su_reg_dest = ((1 << rhdPtr->num_gb_pipes) - 1); |
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104 | BEGIN_ACCEL(2); |
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105 | OUT_ACCEL_REG(R500_SU_REG_DEST, su_reg_dest); |
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106 | OUT_ACCEL_REG(R500_VAP_INDEX_OFFSET, 0); |
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107 | FINISH_ACCEL(); |
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108 | } |
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109 | |||
110 | |||
111 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
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112 | OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
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113 | OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
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114 | FINISH_ACCEL(); |
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115 | |||
116 | |||
117 | OUT_ACCEL_REG(R300_GB_AA_CONFIG, 0); |
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118 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
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119 | OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
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120 | OUT_ACCEL_REG(R300_GB_MSPOS0, ((8 << R300_MS_X0_SHIFT) | |
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121 | (8 << R300_MS_Y0_SHIFT) | |
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122 | (8 << R300_MS_X1_SHIFT) | |
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123 | (8 << R300_MS_Y1_SHIFT) | |
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124 | (8 << R300_MS_X2_SHIFT) | |
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125 | (8 << R300_MS_Y2_SHIFT) | |
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126 | (8 << R300_MSBD0_Y_SHIFT) | |
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127 | (7 << R300_MSBD0_X_SHIFT))); |
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128 | OUT_ACCEL_REG(R300_GB_MSPOS1, ((8 << R300_MS_X3_SHIFT) | |
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129 | (8 << R300_MS_Y3_SHIFT) | |
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130 | (8 << R300_MS_X4_SHIFT) | |
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131 | (8 << R300_MS_Y4_SHIFT) | |
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132 | (8 << R300_MS_X5_SHIFT) | |
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133 | (8 << R300_MS_Y5_SHIFT) | |
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134 | (8 << R300_MSBD1_SHIFT))); |
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135 | FINISH_ACCEL(); |
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136 | |||
137 | |||
138 | OUT_ACCEL_REG(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); |
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139 | OUT_ACCEL_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); |
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140 | OUT_ACCEL_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST | |
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141 | R300_COLOR_ROUND_NEAREST)); |
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142 | OUT_ACCEL_REG(R300_GA_COLOR_CONTROL, (R300_RGB0_SHADING_GOURAUD | |
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143 | R300_ALPHA0_SHADING_GOURAUD | |
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144 | R300_RGB1_SHADING_GOURAUD | |
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145 | R300_ALPHA1_SHADING_GOURAUD | |
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146 | R300_RGB2_SHADING_GOURAUD | |
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147 | R300_ALPHA2_SHADING_GOURAUD | |
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148 | R300_RGB3_SHADING_GOURAUD | |
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149 | R300_ALPHA3_SHADING_GOURAUD)); |
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150 | OUT_ACCEL_REG(R300_GA_OFFSET, 0); |
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151 | FINISH_ACCEL(); |
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152 | |||
153 | |||
154 | OUT_ACCEL_REG(R300_SU_TEX_WRAP, 0); |
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155 | OUT_ACCEL_REG(R300_SU_POLY_OFFSET_ENABLE, 0); |
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156 | OUT_ACCEL_REG(R300_SU_CULL_MODE, R300_FACE_NEG); |
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157 | OUT_ACCEL_REG(R300_SU_DEPTH_SCALE, 0x4b7fffff); |
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158 | OUT_ACCEL_REG(R300_SU_DEPTH_OFFSET, 0); |
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159 | FINISH_ACCEL(); |
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160 | |||
161 | |||
162 | if (rhdPtr->has_tcl) |
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163 | vap_cntl = ((5 << R300_PVS_NUM_SLOTS_SHIFT) | |
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164 | (5 << R300_PVS_NUM_CNTLRS_SHIFT) | |
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165 | (9 << R300_VF_MAX_VTX_NUM_SHIFT)); |
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166 | else |
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167 | vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) | |
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168 | (5 << R300_PVS_NUM_CNTLRS_SHIFT) | |
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169 | (5 << R300_VF_MAX_VTX_NUM_SHIFT)); |
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170 | |||
171 | |||
812 | serge | 172 | vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT); |
811 | serge | 173 | else if ((rhdPtr->ChipSet == RHD_FAMILY_RV530) || |
812 | serge | 174 | (rhdPtr->ChipSet == RHD_FAMILY_RV560)) |
175 | vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT); |
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811 | serge | 176 | else if (rhdPtr->ChipSet == RHD_FAMILY_R420) |
812 | serge | 177 | vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT); |
811 | serge | 178 | else if ((rhdPtr->ChipSet == RHD_FAMILY_R520) || |
812 | serge | 179 | (rhdPtr->ChipSet == RHD_FAMILY_R580) || |
180 | (rhdPtr->ChipSet == RHD_FAMILY_RV570)) |
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181 | vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT); |
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811 | serge | 182 | else |
183 | vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT); |
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184 | |||
185 | |||
186 | BEGIN_ACCEL(15); |
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187 | else |
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188 | BEGIN_ACCEL(9); |
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189 | OUT_ACCEL_REG(R300_VAP_VTX_STATE_CNTL, 0); |
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190 | OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); |
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191 | |||
192 | |||
193 | OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0); |
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194 | else |
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195 | OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS); |
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196 | OUT_ACCEL_REG(R300_VAP_CNTL, vap_cntl); |
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197 | OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); |
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198 | OUT_ACCEL_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT); |
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199 | OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0); |
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200 | |||
201 | |||
202 | ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) | |
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203 | (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) | |
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204 | (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) | |
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205 | (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) | |
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206 | ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) |
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207 | << R300_WRITE_ENA_0_SHIFT) | |
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208 | (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) | |
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209 | (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) | |
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210 | (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) | |
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211 | (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) | |
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212 | ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) |
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213 | << R300_WRITE_ENA_1_SHIFT))); |
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214 | OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, |
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215 | ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) | |
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216 | (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) | |
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217 | (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_2_SHIFT) | |
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218 | (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_2_SHIFT) | |
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219 | ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) |
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220 | << R300_WRITE_ENA_2_SHIFT))); |
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221 | |||
222 | |||
223 | OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0); |
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224 | OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000); |
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225 | OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000); |
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226 | OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000); |
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227 | OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000); |
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228 | OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE); |
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229 | } |
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230 | FINISH_ACCEL(); |
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231 | |||
232 | |||
233 | if (rhdPtr->has_tcl) { |
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234 | /* exa mask shader program */ |
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235 | BEGIN_ACCEL(13); |
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236 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0); |
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237 | /* PVS inst 0 */ |
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238 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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239 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
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240 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
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241 | R300_PVS_DST_OFFSET(0) | |
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242 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
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243 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
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244 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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245 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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246 | R300_PVS_SRC_OFFSET(0) | |
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247 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
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248 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
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249 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
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250 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
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251 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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252 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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253 | R300_PVS_SRC_OFFSET(0) | |
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254 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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255 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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256 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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257 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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258 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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259 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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260 | R300_PVS_SRC_OFFSET(0) | |
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261 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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262 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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263 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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264 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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265 | |||
266 | |||
267 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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268 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
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269 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
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270 | R300_PVS_DST_OFFSET(1) | |
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271 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
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272 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
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273 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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274 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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275 | R300_PVS_SRC_OFFSET(6) | |
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276 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
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277 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
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278 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
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279 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
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280 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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281 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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282 | R300_PVS_SRC_OFFSET(6) | |
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283 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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284 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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285 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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286 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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287 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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288 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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289 | R300_PVS_SRC_OFFSET(6) | |
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290 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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291 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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292 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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293 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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294 | |||
295 | |||
296 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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297 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
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298 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
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299 | R300_PVS_DST_OFFSET(2) | |
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300 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
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301 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
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302 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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303 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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304 | R300_PVS_SRC_OFFSET(7) | |
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305 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
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306 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
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307 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
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308 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
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309 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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310 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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311 | R300_PVS_SRC_OFFSET(7) | |
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312 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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313 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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314 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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315 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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316 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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317 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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318 | R300_PVS_SRC_OFFSET(7) | |
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319 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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320 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
321 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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322 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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323 | FINISH_ACCEL(); |
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324 | |||
325 | |||
326 | /* exa no mask instruction */ |
||
327 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 3); |
||
328 | /* PVS inst 0 */ |
||
329 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
330 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
||
331 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
||
332 | R300_PVS_DST_OFFSET(0) | |
||
333 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
||
334 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
||
335 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
336 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
337 | R300_PVS_SRC_OFFSET(0) | |
||
338 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
||
339 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
||
340 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
||
341 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
||
342 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
343 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
344 | R300_PVS_SRC_OFFSET(0) | |
||
345 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
346 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
347 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
348 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
349 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
350 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
351 | R300_PVS_SRC_OFFSET(0) | |
||
352 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
353 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
354 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
355 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
356 | |||
357 | |||
358 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
359 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
||
360 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
||
361 | R300_PVS_DST_OFFSET(1) | |
||
362 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
||
363 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
||
364 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
365 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
366 | R300_PVS_SRC_OFFSET(6) | |
||
367 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
||
368 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
||
369 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
||
370 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
||
371 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
372 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
373 | R300_PVS_SRC_OFFSET(6) | |
||
374 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
375 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
376 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
377 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
378 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
379 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
380 | R300_PVS_SRC_OFFSET(6) | |
||
381 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
382 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
383 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
384 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
385 | FINISH_ACCEL(); |
||
386 | |||
387 | |||
388 | BEGIN_ACCEL(9); |
||
389 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 5); |
||
390 | |||
391 | |||
392 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
||
393 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
||
394 | R300_PVS_DST_OFFSET(0) | |
||
395 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
||
396 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
||
397 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
398 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
399 | R300_PVS_SRC_OFFSET(0) | |
||
400 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
||
401 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
||
402 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
||
403 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
||
404 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
405 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
406 | R300_PVS_SRC_OFFSET(0) | |
||
407 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
408 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
409 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
410 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
411 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
412 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
413 | R300_PVS_SRC_OFFSET(0) | |
||
414 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
415 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
416 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
417 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
418 | |||
419 | |||
420 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
||
421 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
||
422 | R300_PVS_DST_OFFSET(1) | |
||
423 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
||
424 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
||
425 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
426 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
427 | R300_PVS_SRC_OFFSET(6) | |
||
428 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
||
429 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
||
430 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
||
431 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
||
432 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
433 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
434 | R300_PVS_SRC_OFFSET(6) | |
||
435 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
436 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
437 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
438 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
439 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
440 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
441 | R300_PVS_SRC_OFFSET(6) | |
||
442 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
443 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
444 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
445 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
446 | FINISH_ACCEL(); |
||
447 | } |
||
448 | |||
449 | |||
450 | BEGIN_ACCEL(4); |
||
451 | if (IS_R300_3D) { |
||
452 | /* rasterizer source table |
||
453 | * R300_RS_TEX_PTR is the offset into the input RS stream |
||
454 | * 0,1 are tex0 |
||
455 | * 2,3 are tex1 |
||
456 | */ |
||
457 | OUT_ACCEL_REG(R300_RS_IP_0, |
||
458 | (R300_RS_TEX_PTR(0) | |
||
459 | R300_RS_SEL_S(R300_RS_SEL_C0) | |
||
460 | R300_RS_SEL_T(R300_RS_SEL_C1) | |
||
461 | R300_RS_SEL_R(R300_RS_SEL_K0) | |
||
462 | R300_RS_SEL_Q(R300_RS_SEL_K1))); |
||
463 | OUT_ACCEL_REG(R300_RS_IP_1, |
||
464 | (R300_RS_TEX_PTR(2) | |
||
465 | R300_RS_SEL_S(R300_RS_SEL_C0) | |
||
466 | R300_RS_SEL_T(R300_RS_SEL_C1) | |
||
467 | R300_RS_SEL_R(R300_RS_SEL_K0) | |
||
468 | R300_RS_SEL_Q(R300_RS_SEL_K1))); |
||
469 | /* src tex */ |
||
470 | /* R300_INST_TEX_ID - select the RS source table entry |
||
471 | * R300_INST_TEX_ADDR - the FS temp register for the texture data |
||
472 | */ |
||
473 | OUT_ACCEL_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) | |
||
474 | R300_RS_INST_TEX_CN_WRITE | |
||
475 | R300_INST_TEX_ADDR(0))); |
||
476 | /* mask tex */ |
||
477 | OUT_ACCEL_REG(R300_RS_INST_1, (R300_INST_TEX_ID(1) | |
||
478 | R300_RS_INST_TEX_CN_WRITE | |
||
479 | R300_INST_TEX_ADDR(1))); |
||
480 | |||
481 | |||
482 | /* rasterizer source table |
||
483 | * R300_RS_TEX_PTR is the offset into the input RS stream |
||
484 | * 0,1 are tex0 |
||
485 | * 2,3 are tex1 |
||
486 | */ |
||
487 | OUT_ACCEL_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) | |
||
488 | (1 << R500_RS_IP_TEX_PTR_T_SHIFT) | |
||
489 | (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | |
||
490 | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); |
||
491 | |||
492 | |||
493 | (3 << R500_RS_IP_TEX_PTR_T_SHIFT) | |
||
494 | (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | |
||
495 | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); |
||
496 | /* src tex */ |
||
497 | /* R500_RS_INST_TEX_ID_SHIFT - select the RS source table entry |
||
498 | * R500_RS_INST_TEX_ADDR_SHIFT - the FS temp register for the texture data |
||
499 | */ |
||
500 | OUT_ACCEL_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) | |
||
501 | R500_RS_INST_TEX_CN_WRITE | |
||
502 | (0 << R500_RS_INST_TEX_ADDR_SHIFT))); |
||
503 | /* mask tex */ |
||
504 | OUT_ACCEL_REG(R500_RS_INST_1, ((1 << R500_RS_INST_TEX_ID_SHIFT) | |
||
505 | R500_RS_INST_TEX_CN_WRITE | |
||
506 | (1 << R500_RS_INST_TEX_ADDR_SHIFT))); |
||
507 | } |
||
508 | FINISH_ACCEL(); |
||
509 | |||
510 | |||
511 | if (IS_R300_3D) { |
||
512 | BEGIN_ACCEL(2); |
||
513 | /* tex inst for src texture */ |
||
514 | OUT_ACCEL_REG(R300_US_TEX_INST_0, |
||
515 | (R300_TEX_SRC_ADDR(0) | |
||
516 | R300_TEX_DST_ADDR(0) | |
||
517 | R300_TEX_ID(0) | |
||
518 | R300_TEX_INST(R300_TEX_INST_LD))); |
||
519 | |||
520 | |||
521 | OUT_ACCEL_REG(R300_US_TEX_INST_1, |
||
522 | (R300_TEX_SRC_ADDR(1) | |
||
523 | R300_TEX_DST_ADDR(1) | |
||
524 | R300_TEX_ID(1) | |
||
525 | R300_TEX_INST(R300_TEX_INST_LD))); |
||
526 | FINISH_ACCEL(); |
||
527 | } |
||
528 | |||
529 | |||
530 | BEGIN_ACCEL(9); |
||
531 | OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX); |
||
532 | OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */ |
||
533 | OUT_ACCEL_REG(R300_US_CODE_ADDR_0, |
||
534 | (R300_ALU_START(0) | |
||
535 | R300_ALU_SIZE(0) | |
||
536 | R300_TEX_START(0) | |
||
537 | R300_TEX_SIZE(0))); |
||
538 | OUT_ACCEL_REG(R300_US_CODE_ADDR_1, |
||
539 | (R300_ALU_START(0) | |
||
540 | R300_ALU_SIZE(0) | |
||
541 | R300_TEX_START(0) | |
||
542 | R300_TEX_SIZE(0))); |
||
543 | OUT_ACCEL_REG(R300_US_CODE_ADDR_2, |
||
544 | (R300_ALU_START(0) | |
||
545 | R300_ALU_SIZE(0) | |
||
546 | R300_TEX_START(0) | |
||
547 | R300_TEX_SIZE(0))); |
||
548 | } else { |
||
549 | BEGIN_ACCEL(7); |
||
550 | OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); |
||
551 | OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */ |
||
552 | OUT_ACCEL_REG(R500_US_FC_CTRL, 0); |
||
553 | } |
||
554 | OUT_ACCEL_REG(R300_US_W_FMT, 0); |
||
555 | OUT_ACCEL_REG(R300_US_OUT_FMT_1, (R300_OUT_FMT_UNUSED | |
||
556 | R300_OUT_FMT_C0_SEL_BLUE | |
||
557 | R300_OUT_FMT_C1_SEL_GREEN | |
||
558 | R300_OUT_FMT_C2_SEL_RED | |
||
559 | R300_OUT_FMT_C3_SEL_ALPHA)); |
||
560 | OUT_ACCEL_REG(R300_US_OUT_FMT_2, (R300_OUT_FMT_UNUSED | |
||
561 | R300_OUT_FMT_C0_SEL_BLUE | |
||
562 | R300_OUT_FMT_C1_SEL_GREEN | |
||
563 | R300_OUT_FMT_C2_SEL_RED | |
||
564 | R300_OUT_FMT_C3_SEL_ALPHA)); |
||
565 | OUT_ACCEL_REG(R300_US_OUT_FMT_3, (R300_OUT_FMT_UNUSED | |
||
566 | R300_OUT_FMT_C0_SEL_BLUE | |
||
567 | R300_OUT_FMT_C1_SEL_GREEN | |
||
568 | R300_OUT_FMT_C2_SEL_RED | |
||
569 | R300_OUT_FMT_C3_SEL_ALPHA)); |
||
570 | FINISH_ACCEL(); |
||
571 | |||
572 | |||
573 | |||
574 | OUT_ACCEL_REG(R300_FG_DEPTH_SRC, 0); |
||
575 | OUT_ACCEL_REG(R300_FG_FOG_BLEND, 0); |
||
576 | OUT_ACCEL_REG(R300_FG_ALPHA_FUNC, 0); |
||
577 | FINISH_ACCEL(); |
||
578 | |||
579 | |||
580 | OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0); |
||
581 | OUT_ACCEL_REG(R300_RB3D_ZSTENCILCNTL, 0); |
||
582 | OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
||
583 | OUT_ACCEL_REG(R300_RB3D_BW_CNTL, 0); |
||
584 | OUT_ACCEL_REG(R300_RB3D_ZCNTL, 0); |
||
585 | OUT_ACCEL_REG(R300_RB3D_ZTOP, 0); |
||
586 | OUT_ACCEL_REG(R300_RB3D_ROPCNTL, 0); |
||
587 | |||
588 | |||
589 | OUT_ACCEL_REG(R300_RB3D_COLOR_CHANNEL_MASK, (R300_BLUE_MASK_EN | |
||
590 | R300_GREEN_MASK_EN | |
||
591 | R300_RED_MASK_EN | |
||
592 | R300_ALPHA_MASK_EN)); |
||
593 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
||
594 | OUT_ACCEL_REG(R300_RB3D_CCTL, 0); |
||
595 | OUT_ACCEL_REG(R300_RB3D_DITHER_CTL, 0); |
||
596 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
||
597 | FINISH_ACCEL(); |
||
598 | |||
599 | |||
600 | OUT_ACCEL_REG(R300_SC_EDGERULE, 0xA5294A5); |
||
601 | OUT_ACCEL_REG(R300_SC_SCISSOR0, ((0 << R300_SCISSOR_X_SHIFT) | |
||
602 | (0 << R300_SCISSOR_Y_SHIFT))); |
||
603 | OUT_ACCEL_REG(R300_SC_SCISSOR1, ((8191 << R300_SCISSOR_X_SHIFT) | |
||
604 | (8191 << R300_SCISSOR_Y_SHIFT))); |
||
605 | |||
606 | |||
607 | /* clip has offset 1440 */ |
||
608 | OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1088 << R300_CLIP_X_SHIFT) | |
||
609 | (1088 << R300_CLIP_Y_SHIFT))); |
||
610 | OUT_ACCEL_REG(R300_SC_CLIP_0_B, (((1080 + 2920) << R300_CLIP_X_SHIFT) | |
||
611 | ((1080 + 2920) << R300_CLIP_Y_SHIFT))); |
||
612 | } else { |
||
613 | OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((0 << R300_CLIP_X_SHIFT) | |
||
614 | (0 << R300_CLIP_Y_SHIFT))); |
||
615 | OUT_ACCEL_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) | |
||
616 | (4080 << R300_CLIP_Y_SHIFT))); |
||
617 | } |
||
618 | OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA); |
||
619 | OUT_ACCEL_REG(R300_SC_SCREENDOOR, 0xffffff); |
||
620 | FINISH_ACCEL(); |
||
621 | } else if ((rhdPtr->ChipSet == RHD_FAMILY_RV250) || |
||
812 | serge | 622 | (rhdPtr->ChipSet == RHD_FAMILY_RV280) || |
623 | (rhdPtr->ChipSet == RHD_FAMILY_RS300) || |
||
624 | (rhdPtr->ChipSet == RHD_FAMILY_R200)) { |
||
625 | |||
811 | serge | 626 | |
627 | if (rhdPtr->ChipSet == RHD_FAMILY_RS300) { |
||
812 | serge | 628 | OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS); |
811 | serge | 629 | } else { |
630 | OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, 0); |
||
631 | } |
||
632 | OUT_ACCEL_REG(R200_PP_CNTL_X, 0); |
||
633 | OUT_ACCEL_REG(R200_PP_TXMULTI_CTL_0, 0); |
||
634 | OUT_ACCEL_REG(R200_SE_VTX_STATE_CNTL, 0); |
||
635 | OUT_ACCEL_REG(R200_RE_CNTL, 0x0); |
||
636 | OUT_ACCEL_REG(R200_SE_VTE_CNTL, 0); |
||
637 | OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE | |
||
638 | R200_VAP_VF_MAX_VTX_NUM); |
||
639 | FINISH_ACCEL(); |
||
640 | |||
641 | |||
642 | OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0); |
||
643 | OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); |
||
644 | OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0); |
||
645 | OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); |
||
646 | OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | |
||
647 | RADEON_BFACE_SOLID | |
||
648 | RADEON_FFACE_SOLID | |
||
649 | RADEON_VTX_PIX_CENTER_OGL | |
||
650 | RADEON_ROUND_MODE_ROUND | |
||
651 | RADEON_ROUND_PREC_4TH_PIX)); |
||
652 | FINISH_ACCEL(); |
||
653 | } else { |
||
654 | BEGIN_ACCEL(2); |
||
655 | if ((rhdPtr->ChipSet == RHD_FAMILY_RADEON) || |
||
812 | serge | 656 | (rhdPtr->ChipSet == RHD_FAMILY_RV200)) |
657 | OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, 0); |
||
811 | serge | 658 | else |
659 | OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS); |
||
660 | OUT_ACCEL_REG(RADEON_SE_COORD_FMT, |
||
661 | RADEON_VTX_XY_PRE_MULT_1_OVER_W0 | |
||
662 | RADEON_VTX_ST0_NONPARAMETRIC | |
||
663 | RADEON_VTX_ST1_NONPARAMETRIC | |
||
664 | RADEON_TEX1_W_ROUTING_USE_W0); |
||
665 | FINISH_ACCEL(); |
||
666 | |||
667 | |||
668 | OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0); |
||
669 | OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); |
||
670 | OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0); |
||
671 | OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); |
||
672 | OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | |
||
673 | RADEON_BFACE_SOLID | |
||
674 | RADEON_FFACE_SOLID | |
||
675 | RADEON_VTX_PIX_CENTER_OGL | |
||
676 | RADEON_ROUND_MODE_ROUND | |
||
677 | RADEON_ROUND_PREC_4TH_PIX)); |
||
678 | FINISH_ACCEL(); |
||
679 | } |
||
680 | |||
681 | |||
682 | |||
683 | |||
813 | serge | 684 | { |
685 | //RINFO_FROM_SCREEN(pPix->drawable.pScreen); |
||
686 | u32_t txfilter, txformat0, txformat1, txoffset, txpitch; |
||
687 | // int w = pPict->pDrawable->width; |
||
688 | // int h = pPict->pDrawable->height; |
||
689 | int i, pixel_shift; |
||
690 | |||
811 | serge | 691 | |
813 | serge | 692 | |
811 | serge | 693 | |
813 | serge | 694 | |
695 | |||
696 | txpitch = rhd.displayWidth * 4; |
||
697 | |||
698 | |||
699 | txoffset = rhd.FbIntAddress + rhd.FbScanoutStart; |
||
700 | |||
701 | |||
702 | dbgprintf("Bad texture offset 0x%x\n", (int)txoffset); |
||
703 | if ((txpitch & 0x1f) != 0) |
||
704 | dbgprintf("Bad texture pitch 0x%x\n", (int)txpitch); |
||
705 | |||
706 | |||
707 | pixel_shift = 32 >> 4; |
||
708 | txpitch >>= pixel_shift; |
||
709 | txpitch -= 1; |
||
710 | |||
711 | |||
712 | // txoffset |= R300_MACRO_TILE; |
||
713 | |||
714 | |||
715 | // { |
||
716 | // if (R300TexFormats[i].fmt == pPict->format) |
||
717 | // break; |
||
718 | // } |
||
719 | |||
720 | |||
721 | txformat1 = R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8); |
||
722 | |||
723 | |||
724 | (((h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT)); |
||
725 | |||
726 | |||
727 | txpitch |= R500_TXWIDTH_11; |
||
728 | |||
729 | |||
730 | txpitch |= R500_TXHEIGHT_11; |
||
731 | |||
732 | |||
733 | * omit this if there is no padding, but there is no apparent advantage |
||
734 | * in doing so. |
||
735 | */ |
||
736 | txformat0 |= R300_TXPITCH_EN; |
||
737 | |||
738 | |||
739 | // info->texH[unit] = h; |
||
740 | |||
741 | |||
742 | // txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_WRAP); |
||
743 | // else |
||
744 | txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_GL); |
||
745 | |||
746 | |||
747 | // txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_WRAP); |
||
748 | // else |
||
749 | txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_GL); |
||
750 | |||
751 | |||
752 | |||
753 | |||
754 | // case PictFilterNearest: |
||
755 | txfilter |= (R300_TX_MAG_FILTER_NEAREST | R300_TX_MIN_FILTER_NEAREST); |
||
756 | // break; |
||
757 | // case PictFilterBilinear: |
||
758 | // txfilter |= (R300_TX_MAG_FILTER_LINEAR | R300_TX_MIN_FILTER_LINEAR); |
||
759 | // break; |
||
760 | // default: |
||
761 | // RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter)); |
||
762 | // } |
||
763 | |||
764 | |||
765 | u32_t *ring, write; |
||
766 | |||
767 | |||
768 | OUT_ACCEL_REG(R300_TX_FILTER0_0 + (unit * 4), txfilter); |
||
769 | OUT_ACCEL_REG(R300_TX_FILTER1_0 + (unit * 4), 0); |
||
770 | OUT_ACCEL_REG(R300_TX_FORMAT0_0 + (unit * 4), txformat0); |
||
771 | OUT_ACCEL_REG(R300_TX_FORMAT1_0 + (unit * 4), txformat1); |
||
772 | OUT_ACCEL_REG(R300_TX_FORMAT2_0 + (unit * 4), txpitch); |
||
773 | OUT_ACCEL_REG(R300_TX_OFFSET_0 + (unit * 4), txoffset); |
||
774 | // if (!pPict->repeat) |
||
775 | OUT_ACCEL_REG(R300_TX_BORDER_COLOR_0 + (unit * 4), 0); |
||
776 | FINISH_ACCEL(); |
||
777 | } |
||
778 | // if (pPict->transform != 0) { |
||
779 | // is_transform[unit] = TRUE; |
||
780 | // transform[unit] = pPict->transform; |
||
781 | // } else { |
||
782 | // is_transform[unit] = FALSE; |
||
783 | // } |
||
784 | |||
785 | |||
786 | } |
||
787 | |||
788 | |||
789 | { |
||
790 | u32_t sblend, dblend; |
||
791 | |||
792 | |||
793 | dblend = RadeonBlendOp[op].blend_cntl & RADEON_DST_BLEND_MASK; |
||
794 | |||
795 | |||
796 | * it as always 1. |
||
797 | */ |
||
798 | if (PICT_FORMAT_A(dst_format) == 0 && RadeonBlendOp[op].dst_alpha) { |
||
799 | if (sblend == RADEON_SRC_BLEND_GL_DST_ALPHA) |
||
800 | sblend = RADEON_SRC_BLEND_GL_ONE; |
||
801 | else if (sblend == RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA) |
||
802 | sblend = RADEON_SRC_BLEND_GL_ZERO; |
||
803 | } |
||
804 | |||
805 | |||
806 | } |
||
807 | |||
808 | |||
809 | int dstX, int dstY, |
||
810 | int w, int h) |
||
811 | { |
||
812 | // RINFO_FROM_SCREEN(pDst->drawable.pScreen); |
||
813 | u32_t dst_format, dst_offset, dst_pitch; |
||
814 | u32_t txenable, colorpitch; |
||
815 | u32_t blendcntl; |
||
816 | int pixel_shift; |
||
817 | u32_t *ring, write; |
||
818 | |||
819 | |||
820 | |||
821 | |||
822 | |||
823 | |||
824 | // RADEONInit3DEngine(pScrn); |
||
825 | |||
826 | |||
827 | // return FALSE; |
||
828 | dst_format = R300_COLORFORMAT_ARGB8888; |
||
829 | |||
830 | |||
831 | |||
832 | |||
833 | dst_offset = rhd.FbIntAddress + rhd.FbScanoutStart; |
||
834 | |||
835 | |||
836 | dst_pitch = rhd.displayWidth * 4; |
||
837 | colorpitch = dst_pitch >> pixel_shift; |
||
838 | |||
839 | |||
840 | // colorpitch |= R300_COLORTILE; |
||
841 | |||
842 | |||
843 | |||
844 | |||
845 | dbgprintf("Bad destination offset 0x%x\n", (int)dst_offset); |
||
846 | if (((dst_pitch >> pixel_shift) & 0x7) != 0) |
||
847 | dbgprintf("Bad destination pitch 0x%x\n", (int)dst_pitch); |
||
848 | |||
849 | |||
850 | // return FALSE; |
||
851 | |||
852 | |||
853 | return FALSE; |
||
854 | |||
855 | |||
856 | |||
857 | |||
858 | |||
859 | |||
860 | BEGIN_ACCEL(7); |
||
861 | |||
862 | |||
863 | * to the PVS unit of GA input (when PVS is disabled) |
||
864 | * DST_VEC_LOC is the slot in the PVS input vector memory when PVS/TCL is |
||
865 | * enabled. This memory provides the imputs to the vertex shader program |
||
866 | * and ordering is not important. When PVS/TCL is disabled, this field maps |
||
867 | * directly to the GA input memory and the order is signifigant. In |
||
868 | * PVS_BYPASS mode the order is as follows: |
||
869 | * Position |
||
870 | * Point Size |
||
871 | * Color 0-3 |
||
872 | * Textures 0-7 |
||
873 | * Fog |
||
874 | */ |
||
875 | |||
876 | |||
877 | ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | |
||
878 | (0 << R300_SKIP_DWORDS_0_SHIFT) | |
||
879 | (0 << R300_DST_VEC_LOC_0_SHIFT) | |
||
880 | R300_SIGNED_0 | |
||
881 | (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | |
||
882 | (0 << R300_SKIP_DWORDS_1_SHIFT) | |
||
883 | (6 << R300_DST_VEC_LOC_1_SHIFT) | |
||
884 | R300_LAST_VEC_1 | |
||
885 | R300_SIGNED_1)); |
||
886 | |||
887 | |||
888 | * We pre-load vertex programs in RADEONInit3DEngine(): |
||
889 | * - exa no mask |
||
890 | * - exa mask |
||
891 | * - Xv |
||
892 | * Here we select the offset of the vertex program we want to use |
||
893 | */ |
||
894 | OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0, |
||
895 | ((3 << R300_PVS_FIRST_INST_SHIFT) | |
||
896 | (4 << R300_PVS_XYZW_VALID_INST_SHIFT) | |
||
897 | (4 << R300_PVS_LAST_INST_SHIFT))); |
||
898 | OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1, |
||
899 | (4 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); |
||
900 | |||
901 | |||
902 | OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT); |
||
903 | OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT)); |
||
904 | |||
905 | |||
906 | OUT_ACCEL_REG(R300_TX_ENABLE, txenable); |
||
907 | FINISH_ACCEL(); |
||
908 | |||
909 | |||
910 | if (IS_R300_3D) { |
||
911 | } else { |
||
912 | u32_t output_fmt; |
||
913 | u32_t src_color, src_alpha; |
||
914 | u32_t mask_color, mask_alpha; |
||
915 | |||
916 | |||
917 | src_color = (R500_ALU_RGB_R_SWIZ_A_0 | |
||
918 | R500_ALU_RGB_G_SWIZ_A_0 | |
||
919 | R500_ALU_RGB_B_SWIZ_A_0); |
||
920 | else |
||
921 | src_color = (R500_ALU_RGB_R_SWIZ_A_R | |
||
922 | R500_ALU_RGB_G_SWIZ_A_G | |
||
923 | R500_ALU_RGB_B_SWIZ_A_B); |
||
924 | |||
925 | |||
926 | src_alpha = R500_ALPHA_SWIZ_A_1; |
||
927 | else |
||
928 | src_alpha = R500_ALPHA_SWIZ_A_A; |
||
929 | |||
930 | |||
931 | R500_ALU_RGB_G_SWIZ_B_1 | |
||
932 | R500_ALU_RGB_B_SWIZ_B_1); |
||
933 | mask_alpha = R500_ALPHA_SWIZ_B_1; |
||
934 | |||
935 | |||
936 | output_fmt = (R300_OUT_FMT_C4_8 | |
||
937 | R300_OUT_FMT_C0_SEL_BLUE | |
||
938 | R300_OUT_FMT_C1_SEL_GREEN | |
||
939 | R300_OUT_FMT_C2_SEL_RED | |
||
940 | R300_OUT_FMT_C3_SEL_ALPHA); |
||
941 | |||
942 | |||
943 | OUT_ACCEL_REG(R300_RS_COUNT, |
||
944 | ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | |
||
945 | R300_RS_COUNT_HIRES_EN)); |
||
946 | |||
947 | |||
948 | |||
949 | |||
950 | R500_US_CODE_END_ADDR(1))); |
||
951 | OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) | |
||
952 | R500_US_CODE_RANGE_SIZE(1))); |
||
953 | OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0); |
||
954 | |||
955 | |||
956 | FINISH_ACCEL(); |
||
957 | |||
958 | |||
959 | OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0); |
||
960 | /* tex inst for src texture */ |
||
961 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | |
||
962 | R500_INST_TEX_SEM_WAIT | |
||
963 | R500_INST_RGB_WMASK_R | |
||
964 | R500_INST_RGB_WMASK_G | |
||
965 | R500_INST_RGB_WMASK_B | |
||
966 | R500_INST_ALPHA_WMASK | |
||
967 | R500_INST_RGB_CLAMP | |
||
968 | R500_INST_ALPHA_CLAMP)); |
||
969 | |||
970 | |||
971 | R500_TEX_INST_LD | |
||
972 | R500_TEX_SEM_ACQUIRE | |
||
973 | R500_TEX_IGNORE_UNCOVERED)); |
||
974 | |||
975 | |||
976 | R500_TEX_SRC_S_SWIZ_R | |
||
977 | R500_TEX_SRC_T_SWIZ_G | |
||
978 | R500_TEX_DST_ADDR(0) | |
||
979 | R500_TEX_DST_R_SWIZ_R | |
||
980 | R500_TEX_DST_G_SWIZ_G | |
||
981 | R500_TEX_DST_B_SWIZ_B | |
||
982 | R500_TEX_DST_A_SWIZ_A)); |
||
983 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) | |
||
984 | R500_DX_S_SWIZ_R | |
||
985 | R500_DX_T_SWIZ_R | |
||
986 | R500_DX_R_SWIZ_R | |
||
987 | R500_DX_Q_SWIZ_R | |
||
988 | R500_DY_ADDR(0) | |
||
989 | R500_DY_S_SWIZ_R | |
||
990 | R500_DY_T_SWIZ_R | |
||
991 | R500_DY_R_SWIZ_R | |
||
992 | R500_DY_Q_SWIZ_R)); |
||
993 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); |
||
994 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); |
||
995 | |||
996 | |||
997 | /* *_OMASK* - output component write mask */ |
||
998 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT | |
||
999 | R500_INST_TEX_SEM_WAIT | |
||
1000 | R500_INST_LAST | |
||
1001 | R500_INST_RGB_OMASK_R | |
||
1002 | R500_INST_RGB_OMASK_G | |
||
1003 | R500_INST_RGB_OMASK_B | |
||
1004 | R500_INST_ALPHA_OMASK | |
||
1005 | R500_INST_RGB_CLAMP | |
||
1006 | R500_INST_ALPHA_CLAMP)); |
||
1007 | /* ALU inst |
||
1008 | * temp addresses for texture inputs |
||
1009 | * RGB_ADDR0 is src tex (temp 0) |
||
1010 | * RGB_ADDR1 is mask tex (temp 1) |
||
1011 | */ |
||
1012 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | |
||
1013 | R500_RGB_ADDR1(1) | |
||
1014 | R500_RGB_ADDR2(0))); |
||
1015 | /* ALU inst |
||
1016 | * temp addresses for texture inputs |
||
1017 | * ALPHA_ADDR0 is src tex (temp 0) |
||
1018 | * ALPHA_ADDR1 is mask tex (temp 1) |
||
1019 | */ |
||
1020 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | |
||
1021 | R500_ALPHA_ADDR1(1) | |
||
1022 | R500_ALPHA_ADDR2(0))); |
||
1023 | |||
1024 | |||
1025 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | |
||
1026 | src_color | |
||
1027 | R500_ALU_RGB_SEL_B_SRC1 | |
||
1028 | mask_color | |
||
1029 | R500_ALU_RGB_TARGET(0))); |
||
1030 | |||
1031 | |||
1032 | OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD | |
||
1033 | R500_ALPHA_ADDRD(0) | |
||
1034 | R500_ALPHA_SEL_A_SRC0 | |
||
1035 | src_alpha | |
||
1036 | R500_ALPHA_SEL_B_SRC1 | |
||
1037 | mask_alpha | |
||
1038 | R500_ALPHA_TARGET(0))); |
||
1039 | |||
1040 | |||
1041 | R500_ALU_RGBA_ADDRD(0) | |
||
1042 | R500_ALU_RGBA_R_SWIZ_0 | |
||
1043 | R500_ALU_RGBA_G_SWIZ_0 | |
||
1044 | R500_ALU_RGBA_B_SWIZ_0 | |
||
1045 | R500_ALU_RGBA_A_SWIZ_0)); |
||
1046 | FINISH_ACCEL(); |
||
1047 | } |
||
1048 | |||
1049 | |||
1050 | |||
1051 | |||
1052 | OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch); |
||
1053 | |||
1054 | |||
1055 | OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, blendcntl | R300_ALPHA_BLEND_ENABLE | R300_READ_ENABLE); |
||
1056 | |||
1057 | |||
1058 | |||
1059 | |||
1060 | } |
||
1061 | |||
1062 | |||
1063 | |||
1064 | |||
1065 | |||
1066 | |||
1067 | |||
1068 | |||
1069 | |||
1070 | { |
||
1071 | union { |
||
1072 | float f; |
||
1073 | u32_t l; |
||
1074 | } tmp; |
||
1075 | tmp.f = val; |
||
1076 | return tmp.l; |
||
1077 | } |
||
1078 | |||
1079 | |||
1080 | |||
1081 | |||
1082 | do { \ |
||
1083 | OUT_RING_F(_dstX); \ |
||
1084 | OUT_RING_F(_dstY); \ |
||
1085 | OUT_RING_F(_srcX); \ |
||
1086 | OUT_RING_F(_srcY); \ |
||
1087 | } while (0) |
||
1088 | |||
1089 | |||
1090 | |||
1091 | |||
1092 | int dstX, int dstY, |
||
1093 | int w, int h) |
||
1094 | { |
||
1095 | // RINFO_FROM_SCREEN(pDst->drawable.pScreen); |
||
1096 | int vtx_count; |
||
1097 | xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight; |
||
1098 | xPointFixed maskTopLeft, maskTopRight, maskBottomLeft, maskBottomRight; |
||
1099 | |||
1100 | |||
877 | serge | 1101 | |
813 | serge | 1102 | |
1103 | |||
1104 | |||
1105 | |||
1106 | |||
1107 | |||
1108 | srcX, srcY, maskX, maskY,dstX, dstY, w, h); */ |
||
1109 | |||
1110 | |||
1111 | srcTopLeft.y = IntToxFixed(srcY); |
||
1112 | srcTopRight.x = IntToxFixed(srcX + w); |
||
1113 | srcTopRight.y = IntToxFixed(srcY); |
||
1114 | srcBottomLeft.x = IntToxFixed(srcX); |
||
1115 | srcBottomLeft.y = IntToxFixed(srcY + h); |
||
1116 | srcBottomRight.x = IntToxFixed(srcX + w); |
||
1117 | srcBottomRight.y = IntToxFixed(srcY + h); |
||
1118 | |||
1119 | |||
1120 | if (is_transform[0]) { |
||
1121 | transformPoint(transform[0], &srcTopLeft); |
||
1122 | transformPoint(transform[0], &srcTopRight); |
||
1123 | transformPoint(transform[0], &srcBottomLeft); |
||
1124 | transformPoint(transform[0], &srcBottomRight); |
||
1125 | } |
||
1126 | if (is_transform[1]) { |
||
1127 | transformPoint(transform[1], &maskTopLeft); |
||
1128 | transformPoint(transform[1], &maskTopRight); |
||
1129 | transformPoint(transform[1], &maskBottomLeft); |
||
1130 | transformPoint(transform[1], &maskBottomRight); |
||
1131 | } |
||
1132 | */ |
||
1133 | vtx_count = VTX_COUNT; |
||
1134 | |||
1135 | |||
1136 | OUT_ACCEL_REG(R300_VAP_VTX_SIZE, vtx_count); |
||
1137 | FINISH_ACCEL(); |
||
1138 | |||
1139 | |||
1140 | |||
1141 | |||
1142 | 4 * vtx_count)); |
||
1143 | OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN | |
||
1144 | RADEON_CP_VC_CNTL_PRIM_WALK_RING | |
||
1145 | (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); |
||
1146 | |||
1147 | |||
1148 | |||
1149 | xFixedToFloat(srcTopLeft.x) / w, // info->texW[0], |
||
1150 | xFixedToFloat(srcTopLeft.y) / h); // info->texH[0]); |
||
1151 | |||
1152 | |||
1153 | xFixedToFloat(srcBottomLeft.x) / w, // info->texW[0], |
||
1154 | xFixedToFloat(srcBottomLeft.y) / h); // info->texH[0]); |
||
1155 | |||
1156 | |||
1157 | xFixedToFloat(srcBottomRight.x) / w, // info->texW[0], |
||
1158 | xFixedToFloat(srcBottomRight.y) / h); // info->texH[0]); |
||
1159 | |||
1160 | |||
1161 | xFixedToFloat(srcTopRight.x) / w, // info->texW[0], |
||
1162 | xFixedToFloat(srcTopRight.y) / h); // info->texH[0]); |
||
1163 | |||
1164 | |||
1165 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D); |
||
1166 | |||
1167 | |||
1168 | |||
1169 | |||
1170 | |||
1171 | |||
1172 | } |
||
1173 | #undef VTX_OUT |
||
1174 | #undef VTX_OUT_MASK |
||
1175 | |||
1176 | |||
879 | serge | 1177 | |
813 | serge | 1178 | |
1179 | { |
||
1180 | int tileSrcY, tileMaskY, tileDstY; |
||
1181 | int remainingHeight; |
||
1182 | |||
1183 | |||
1184 | blit->dst_x, blit->dst_y, |
||
1185 | blit->w, blit->h); |
||
1186 | |||
1187 | |||
1188 | RadeonCompositeTile( blit->src_x, blit->src_y, |
||
1189 | blit->dst_x, blit->dst_y, |
||
1190 | blit->w, blit->h); |
||
1191 | return 0; |
||
1192 | // } |
||
1193 | |||
1194 | |||
1195 | |||
1196 | |||
1197 | modulus(srcY, src_tile_height, tileSrcY); |
||
1198 | tileMaskY = maskY; |
||
1199 | tileDstY = dstY; |
||
1200 | |||
1201 | |||
1202 | while (remainingHeight > 0) { |
||
1203 | int remainingWidth = width; |
||
1204 | int tileSrcX, tileMaskX, tileDstX; |
||
1205 | int h = src_tile_height - tileSrcY; |
||
1206 | |||
1207 | |||
1208 | h = remainingHeight; |
||
1209 | remainingHeight -= h; |
||
1210 | |||
1211 | |||
1212 | tileMaskX = maskX; |
||
1213 | tileDstX = dstX; |
||
1214 | |||
1215 | |||
1216 | int w = src_tile_width - tileSrcX; |
||
1217 | if (w > remainingWidth) |
||
1218 | w = remainingWidth; |
||
1219 | remainingWidth -= w; |
||
1220 | |||
1221 | |||
1222 | tileSrcX, tileSrcY, |
||
1223 | tileMaskX, tileMaskY, |
||
1224 | tileDstX, tileDstY, |
||
1225 | w, h); |
||
1226 | |||
1227 | |||
1228 | tileMaskX += w; |
||
1229 | tileDstX += w; |
||
1230 | } |
||
1231 | tileSrcY = 0; |
||
1232 | tileMaskY += h; |
||
1233 | tileDstY += h; |
||
1234 | } |
||
1235 | #endif |
||
1236 | } |
||
1237 | |||
1238 | |||
879 | serge | 1239 |