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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 811 | serge | 1 | |
| 2 | |||
| 3 | |||
| 4 | //#define FINISH_ACCEL() ADVANCE_RING() |
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| 5 | #define FINISH_ACCEL() COMMIT_RING() |
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| 6 | |||
| 7 | |||
| 8 | |||
| 9 | |||
| 10 | #define IS_R500_3D 1 |
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| 11 | |||
| 12 | |||
| 13 | CHIP_FAMILY_UNKNOW, |
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| 14 | CHIP_FAMILY_LEGACY, |
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| 15 | CHIP_FAMILY_RADEON, |
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| 16 | CHIP_FAMILY_RV100, |
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| 17 | CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/ |
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| 18 | CHIP_FAMILY_RV200, |
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| 19 | CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */ |
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| 20 | CHIP_FAMILY_R200, |
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| 21 | CHIP_FAMILY_RV250, |
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| 22 | CHIP_FAMILY_RS300, /* RS300/RS350 */ |
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| 23 | CHIP_FAMILY_RV280, |
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| 24 | CHIP_FAMILY_R300, |
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| 25 | CHIP_FAMILY_R350, |
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| 26 | CHIP_FAMILY_RV350, |
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| 27 | CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ |
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| 28 | CHIP_FAMILY_R420, /* R420/R423/M18 */ |
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| 29 | CHIP_FAMILY_RV410, /* RV410, M26 */ |
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| 30 | CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400) Intel */ |
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| 31 | CHIP_FAMILY_RS480, /* xpress 200, 200m (RS410/480/482/485) AMD */ |
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| 32 | CHIP_FAMILY_RV515, /* rv515 */ |
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| 33 | CHIP_FAMILY_R520, /* r520 */ |
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| 34 | CHIP_FAMILY_RV530, /* rv530 */ |
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| 35 | CHIP_FAMILY_R580, /* r580 */ |
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| 36 | CHIP_FAMILY_RV560, /* rv560 */ |
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| 37 | CHIP_FAMILY_RV570, /* rv570 */ |
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| 38 | CHIP_FAMILY_RS600, |
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| 39 | CHIP_FAMILY_RS690, |
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| 40 | CHIP_FAMILY_RS740, |
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| 41 | CHIP_FAMILY_R600, /* r600 */ |
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| 42 | CHIP_FAMILY_R630, |
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| 43 | CHIP_FAMILY_RV610, |
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| 44 | CHIP_FAMILY_RV630, |
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| 45 | CHIP_FAMILY_RV670, |
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| 46 | CHIP_FAMILY_RV620, |
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| 47 | CHIP_FAMILY_RV635, |
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| 48 | CHIP_FAMILY_RS780, |
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| 49 | CHIP_FAMILY_LAST |
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| 50 | } RADEONChipFamily; |
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| 51 | |||
| 52 | |||
| 53 | { |
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| 54 | // RADEONInfoPtr info = RADEONPTR(pScrn); |
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| 55 | u32_t gb_tile_config, su_reg_dest, vap_cntl; |
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| 56 | // ACCEL_PREAMBLE(); |
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| 57 | |||
| 58 | |||
| 59 | |||
| 60 | |||
| 61 | |||
| 62 | |||
| 63 | |||
| 64 | |||
| 65 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
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| 66 | OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
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| 67 | OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
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| 68 | FINISH_ACCEL(); |
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| 69 | |||
| 70 | |||
| 71 | |||
| 72 | |||
| 73 | case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; |
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| 74 | case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; |
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| 75 | case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; |
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| 76 | default: |
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| 77 | case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; |
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| 78 | } |
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| 79 | |||
| 80 | |||
| 81 | OUT_ACCEL_REG(R300_GB_TILE_CONFIG, gb_tile_config); |
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| 82 | OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
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| 83 | OUT_ACCEL_REG(R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG); |
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| 84 | OUT_ACCEL_REG(R300_GB_SELECT, 0); |
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| 85 | OUT_ACCEL_REG(R300_GB_ENABLE, 0); |
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| 86 | FINISH_ACCEL(); |
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| 87 | |||
| 88 | |||
| 89 | su_reg_dest = ((1 << rhdPtr->num_gb_pipes) - 1); |
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| 90 | BEGIN_ACCEL(2); |
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| 91 | OUT_ACCEL_REG(R500_SU_REG_DEST, su_reg_dest); |
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| 92 | OUT_ACCEL_REG(R500_VAP_INDEX_OFFSET, 0); |
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| 93 | FINISH_ACCEL(); |
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| 94 | } |
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| 95 | |||
| 96 | |||
| 97 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
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| 98 | OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
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| 99 | OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
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| 100 | FINISH_ACCEL(); |
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| 101 | |||
| 102 | |||
| 103 | OUT_ACCEL_REG(R300_GB_AA_CONFIG, 0); |
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| 104 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
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| 105 | OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
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| 106 | OUT_ACCEL_REG(R300_GB_MSPOS0, ((8 << R300_MS_X0_SHIFT) | |
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| 107 | (8 << R300_MS_Y0_SHIFT) | |
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| 108 | (8 << R300_MS_X1_SHIFT) | |
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| 109 | (8 << R300_MS_Y1_SHIFT) | |
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| 110 | (8 << R300_MS_X2_SHIFT) | |
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| 111 | (8 << R300_MS_Y2_SHIFT) | |
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| 112 | (8 << R300_MSBD0_Y_SHIFT) | |
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| 113 | (7 << R300_MSBD0_X_SHIFT))); |
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| 114 | OUT_ACCEL_REG(R300_GB_MSPOS1, ((8 << R300_MS_X3_SHIFT) | |
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| 115 | (8 << R300_MS_Y3_SHIFT) | |
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| 116 | (8 << R300_MS_X4_SHIFT) | |
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| 117 | (8 << R300_MS_Y4_SHIFT) | |
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| 118 | (8 << R300_MS_X5_SHIFT) | |
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| 119 | (8 << R300_MS_Y5_SHIFT) | |
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| 120 | (8 << R300_MSBD1_SHIFT))); |
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| 121 | FINISH_ACCEL(); |
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| 122 | |||
| 123 | |||
| 124 | OUT_ACCEL_REG(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); |
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| 125 | OUT_ACCEL_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); |
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| 126 | OUT_ACCEL_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST | |
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| 127 | R300_COLOR_ROUND_NEAREST)); |
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| 128 | OUT_ACCEL_REG(R300_GA_COLOR_CONTROL, (R300_RGB0_SHADING_GOURAUD | |
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| 129 | R300_ALPHA0_SHADING_GOURAUD | |
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| 130 | R300_RGB1_SHADING_GOURAUD | |
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| 131 | R300_ALPHA1_SHADING_GOURAUD | |
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| 132 | R300_RGB2_SHADING_GOURAUD | |
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| 133 | R300_ALPHA2_SHADING_GOURAUD | |
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| 134 | R300_RGB3_SHADING_GOURAUD | |
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| 135 | R300_ALPHA3_SHADING_GOURAUD)); |
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| 136 | OUT_ACCEL_REG(R300_GA_OFFSET, 0); |
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| 137 | FINISH_ACCEL(); |
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| 138 | |||
| 139 | |||
| 140 | OUT_ACCEL_REG(R300_SU_TEX_WRAP, 0); |
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| 141 | OUT_ACCEL_REG(R300_SU_POLY_OFFSET_ENABLE, 0); |
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| 142 | OUT_ACCEL_REG(R300_SU_CULL_MODE, R300_FACE_NEG); |
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| 143 | OUT_ACCEL_REG(R300_SU_DEPTH_SCALE, 0x4b7fffff); |
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| 144 | OUT_ACCEL_REG(R300_SU_DEPTH_OFFSET, 0); |
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| 145 | FINISH_ACCEL(); |
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| 146 | |||
| 147 | |||
| 148 | if (rhdPtr->has_tcl) |
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| 149 | vap_cntl = ((5 << R300_PVS_NUM_SLOTS_SHIFT) | |
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| 150 | (5 << R300_PVS_NUM_CNTLRS_SHIFT) | |
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| 151 | (9 << R300_VF_MAX_VTX_NUM_SHIFT)); |
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| 152 | else |
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| 153 | vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) | |
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| 154 | (5 << R300_PVS_NUM_CNTLRS_SHIFT) | |
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| 155 | (5 << R300_VF_MAX_VTX_NUM_SHIFT)); |
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| 156 | |||
| 157 | |||
| 158 | vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT); |
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| 159 | else if ((rhdPtr->ChipSet == CHIP_FAMILY_RV530) || |
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| 160 | (rhdPtr->ChipSet == CHIP_FAMILY_RV560)) |
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| 161 | vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT); |
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| 162 | else if (rhdPtr->ChipSet == CHIP_FAMILY_R420) |
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| 163 | vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT); |
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| 164 | else if ((rhdPtr->ChipSet == CHIP_FAMILY_R520) || |
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| 165 | (rhdPtr->ChipSet == CHIP_FAMILY_R580) || |
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| 166 | (rhdPtr->ChipSet == CHIP_FAMILY_RV570)) |
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| 167 | vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT); |
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| 168 | else |
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| 169 | vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT); |
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| 170 | |||
| 171 | |||
| 172 | BEGIN_ACCEL(15); |
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| 173 | else |
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| 174 | BEGIN_ACCEL(9); |
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| 175 | OUT_ACCEL_REG(R300_VAP_VTX_STATE_CNTL, 0); |
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| 176 | OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); |
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| 177 | |||
| 178 | |||
| 179 | OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0); |
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| 180 | else |
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| 181 | OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS); |
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| 182 | OUT_ACCEL_REG(R300_VAP_CNTL, vap_cntl); |
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| 183 | OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); |
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| 184 | OUT_ACCEL_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT); |
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| 185 | OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0); |
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| 186 | |||
| 187 | |||
| 188 | ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) | |
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| 189 | (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) | |
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| 190 | (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) | |
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| 191 | (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) | |
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| 192 | ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) |
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| 193 | << R300_WRITE_ENA_0_SHIFT) | |
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| 194 | (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) | |
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| 195 | (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) | |
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| 196 | (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) | |
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| 197 | (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) | |
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| 198 | ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) |
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| 199 | << R300_WRITE_ENA_1_SHIFT))); |
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| 200 | OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, |
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| 201 | ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) | |
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| 202 | (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) | |
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| 203 | (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_2_SHIFT) | |
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| 204 | (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_2_SHIFT) | |
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| 205 | ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) |
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| 206 | << R300_WRITE_ENA_2_SHIFT))); |
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| 207 | |||
| 208 | |||
| 209 | OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0); |
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| 210 | OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000); |
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| 211 | OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000); |
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| 212 | OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000); |
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| 213 | OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000); |
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| 214 | OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE); |
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| 215 | } |
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| 216 | FINISH_ACCEL(); |
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| 217 | |||
| 218 | |||
| 219 | if (rhdPtr->has_tcl) { |
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| 220 | /* exa mask shader program */ |
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| 221 | BEGIN_ACCEL(13); |
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| 222 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0); |
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| 223 | /* PVS inst 0 */ |
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| 224 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 225 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
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| 226 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
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| 227 | R300_PVS_DST_OFFSET(0) | |
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| 228 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
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| 229 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
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| 230 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 231 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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| 232 | R300_PVS_SRC_OFFSET(0) | |
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| 233 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
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| 234 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
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| 235 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
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| 236 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
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| 237 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 238 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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| 239 | R300_PVS_SRC_OFFSET(0) | |
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| 240 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 241 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 242 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 243 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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| 244 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 245 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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| 246 | R300_PVS_SRC_OFFSET(0) | |
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| 247 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 248 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 249 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 250 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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| 251 | |||
| 252 | |||
| 253 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 254 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
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| 255 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
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| 256 | R300_PVS_DST_OFFSET(1) | |
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| 257 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
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| 258 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
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| 259 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 260 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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| 261 | R300_PVS_SRC_OFFSET(6) | |
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| 262 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
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| 263 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
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| 264 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
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| 265 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
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| 266 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 267 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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| 268 | R300_PVS_SRC_OFFSET(6) | |
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| 269 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 270 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 271 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 272 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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| 273 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 274 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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| 275 | R300_PVS_SRC_OFFSET(6) | |
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| 276 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 277 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 278 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 279 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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| 280 | |||
| 281 | |||
| 282 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 283 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
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| 284 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
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| 285 | R300_PVS_DST_OFFSET(2) | |
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| 286 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
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| 287 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
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| 288 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 289 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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| 290 | R300_PVS_SRC_OFFSET(7) | |
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| 291 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
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| 292 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
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| 293 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
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| 294 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
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| 295 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 296 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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| 297 | R300_PVS_SRC_OFFSET(7) | |
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| 298 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 299 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 300 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 301 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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| 302 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
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| 303 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
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| 304 | R300_PVS_SRC_OFFSET(7) | |
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| 305 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 306 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 307 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
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| 308 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
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| 309 | FINISH_ACCEL(); |
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| 310 | |||
| 311 | |||
| 312 | /* exa no mask instruction */ |
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| 313 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 3); |
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| 314 | /* PVS inst 0 */ |
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| 315 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 316 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
||
| 317 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
||
| 318 | R300_PVS_DST_OFFSET(0) | |
||
| 319 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
||
| 320 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
||
| 321 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 322 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 323 | R300_PVS_SRC_OFFSET(0) | |
||
| 324 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
||
| 325 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
||
| 326 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
||
| 327 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
||
| 328 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 329 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 330 | R300_PVS_SRC_OFFSET(0) | |
||
| 331 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 332 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 333 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 334 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
| 335 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 336 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 337 | R300_PVS_SRC_OFFSET(0) | |
||
| 338 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 339 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 340 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 341 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
| 342 | |||
| 343 | |||
| 344 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 345 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
||
| 346 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
||
| 347 | R300_PVS_DST_OFFSET(1) | |
||
| 348 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
||
| 349 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
||
| 350 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 351 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 352 | R300_PVS_SRC_OFFSET(6) | |
||
| 353 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
||
| 354 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
||
| 355 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
||
| 356 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
||
| 357 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 358 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 359 | R300_PVS_SRC_OFFSET(6) | |
||
| 360 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 361 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 362 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 363 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
| 364 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 365 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 366 | R300_PVS_SRC_OFFSET(6) | |
||
| 367 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 368 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 369 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 370 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
| 371 | FINISH_ACCEL(); |
||
| 372 | |||
| 373 | |||
| 374 | BEGIN_ACCEL(9); |
||
| 375 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 5); |
||
| 376 | |||
| 377 | |||
| 378 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
||
| 379 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
||
| 380 | R300_PVS_DST_OFFSET(0) | |
||
| 381 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
||
| 382 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
||
| 383 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 384 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 385 | R300_PVS_SRC_OFFSET(0) | |
||
| 386 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
||
| 387 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
||
| 388 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
||
| 389 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
||
| 390 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 391 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 392 | R300_PVS_SRC_OFFSET(0) | |
||
| 393 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 394 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 395 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 396 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
| 397 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 398 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 399 | R300_PVS_SRC_OFFSET(0) | |
||
| 400 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 401 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 402 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 403 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
| 404 | |||
| 405 | |||
| 406 | (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
||
| 407 | R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
||
| 408 | R300_PVS_DST_OFFSET(1) | |
||
| 409 | R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
||
| 410 | R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
||
| 411 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 412 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 413 | R300_PVS_SRC_OFFSET(6) | |
||
| 414 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
||
| 415 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
||
| 416 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
||
| 417 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
||
| 418 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 419 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 420 | R300_PVS_SRC_OFFSET(6) | |
||
| 421 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 422 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 423 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 424 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
| 425 | OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
||
| 426 | (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
||
| 427 | R300_PVS_SRC_OFFSET(6) | |
||
| 428 | R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 429 | R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 430 | R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
||
| 431 | R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
||
| 432 | FINISH_ACCEL(); |
||
| 433 | } |
||
| 434 | |||
| 435 | |||
| 436 | BEGIN_ACCEL(4); |
||
| 437 | if (IS_R300_3D) { |
||
| 438 | /* rasterizer source table |
||
| 439 | * R300_RS_TEX_PTR is the offset into the input RS stream |
||
| 440 | * 0,1 are tex0 |
||
| 441 | * 2,3 are tex1 |
||
| 442 | */ |
||
| 443 | OUT_ACCEL_REG(R300_RS_IP_0, |
||
| 444 | (R300_RS_TEX_PTR(0) | |
||
| 445 | R300_RS_SEL_S(R300_RS_SEL_C0) | |
||
| 446 | R300_RS_SEL_T(R300_RS_SEL_C1) | |
||
| 447 | R300_RS_SEL_R(R300_RS_SEL_K0) | |
||
| 448 | R300_RS_SEL_Q(R300_RS_SEL_K1))); |
||
| 449 | OUT_ACCEL_REG(R300_RS_IP_1, |
||
| 450 | (R300_RS_TEX_PTR(2) | |
||
| 451 | R300_RS_SEL_S(R300_RS_SEL_C0) | |
||
| 452 | R300_RS_SEL_T(R300_RS_SEL_C1) | |
||
| 453 | R300_RS_SEL_R(R300_RS_SEL_K0) | |
||
| 454 | R300_RS_SEL_Q(R300_RS_SEL_K1))); |
||
| 455 | /* src tex */ |
||
| 456 | /* R300_INST_TEX_ID - select the RS source table entry |
||
| 457 | * R300_INST_TEX_ADDR - the FS temp register for the texture data |
||
| 458 | */ |
||
| 459 | OUT_ACCEL_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) | |
||
| 460 | R300_RS_INST_TEX_CN_WRITE | |
||
| 461 | R300_INST_TEX_ADDR(0))); |
||
| 462 | /* mask tex */ |
||
| 463 | OUT_ACCEL_REG(R300_RS_INST_1, (R300_INST_TEX_ID(1) | |
||
| 464 | R300_RS_INST_TEX_CN_WRITE | |
||
| 465 | R300_INST_TEX_ADDR(1))); |
||
| 466 | |||
| 467 | |||
| 468 | /* rasterizer source table |
||
| 469 | * R300_RS_TEX_PTR is the offset into the input RS stream |
||
| 470 | * 0,1 are tex0 |
||
| 471 | * 2,3 are tex1 |
||
| 472 | */ |
||
| 473 | OUT_ACCEL_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) | |
||
| 474 | (1 << R500_RS_IP_TEX_PTR_T_SHIFT) | |
||
| 475 | (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | |
||
| 476 | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); |
||
| 477 | |||
| 478 | |||
| 479 | (3 << R500_RS_IP_TEX_PTR_T_SHIFT) | |
||
| 480 | (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | |
||
| 481 | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); |
||
| 482 | /* src tex */ |
||
| 483 | /* R500_RS_INST_TEX_ID_SHIFT - select the RS source table entry |
||
| 484 | * R500_RS_INST_TEX_ADDR_SHIFT - the FS temp register for the texture data |
||
| 485 | */ |
||
| 486 | OUT_ACCEL_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) | |
||
| 487 | R500_RS_INST_TEX_CN_WRITE | |
||
| 488 | (0 << R500_RS_INST_TEX_ADDR_SHIFT))); |
||
| 489 | /* mask tex */ |
||
| 490 | OUT_ACCEL_REG(R500_RS_INST_1, ((1 << R500_RS_INST_TEX_ID_SHIFT) | |
||
| 491 | R500_RS_INST_TEX_CN_WRITE | |
||
| 492 | (1 << R500_RS_INST_TEX_ADDR_SHIFT))); |
||
| 493 | } |
||
| 494 | FINISH_ACCEL(); |
||
| 495 | |||
| 496 | |||
| 497 | if (IS_R300_3D) { |
||
| 498 | BEGIN_ACCEL(2); |
||
| 499 | /* tex inst for src texture */ |
||
| 500 | OUT_ACCEL_REG(R300_US_TEX_INST_0, |
||
| 501 | (R300_TEX_SRC_ADDR(0) | |
||
| 502 | R300_TEX_DST_ADDR(0) | |
||
| 503 | R300_TEX_ID(0) | |
||
| 504 | R300_TEX_INST(R300_TEX_INST_LD))); |
||
| 505 | |||
| 506 | |||
| 507 | OUT_ACCEL_REG(R300_US_TEX_INST_1, |
||
| 508 | (R300_TEX_SRC_ADDR(1) | |
||
| 509 | R300_TEX_DST_ADDR(1) | |
||
| 510 | R300_TEX_ID(1) | |
||
| 511 | R300_TEX_INST(R300_TEX_INST_LD))); |
||
| 512 | FINISH_ACCEL(); |
||
| 513 | } |
||
| 514 | |||
| 515 | |||
| 516 | BEGIN_ACCEL(9); |
||
| 517 | OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX); |
||
| 518 | OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */ |
||
| 519 | OUT_ACCEL_REG(R300_US_CODE_ADDR_0, |
||
| 520 | (R300_ALU_START(0) | |
||
| 521 | R300_ALU_SIZE(0) | |
||
| 522 | R300_TEX_START(0) | |
||
| 523 | R300_TEX_SIZE(0))); |
||
| 524 | OUT_ACCEL_REG(R300_US_CODE_ADDR_1, |
||
| 525 | (R300_ALU_START(0) | |
||
| 526 | R300_ALU_SIZE(0) | |
||
| 527 | R300_TEX_START(0) | |
||
| 528 | R300_TEX_SIZE(0))); |
||
| 529 | OUT_ACCEL_REG(R300_US_CODE_ADDR_2, |
||
| 530 | (R300_ALU_START(0) | |
||
| 531 | R300_ALU_SIZE(0) | |
||
| 532 | R300_TEX_START(0) | |
||
| 533 | R300_TEX_SIZE(0))); |
||
| 534 | } else { |
||
| 535 | BEGIN_ACCEL(7); |
||
| 536 | OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); |
||
| 537 | OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */ |
||
| 538 | OUT_ACCEL_REG(R500_US_FC_CTRL, 0); |
||
| 539 | } |
||
| 540 | OUT_ACCEL_REG(R300_US_W_FMT, 0); |
||
| 541 | OUT_ACCEL_REG(R300_US_OUT_FMT_1, (R300_OUT_FMT_UNUSED | |
||
| 542 | R300_OUT_FMT_C0_SEL_BLUE | |
||
| 543 | R300_OUT_FMT_C1_SEL_GREEN | |
||
| 544 | R300_OUT_FMT_C2_SEL_RED | |
||
| 545 | R300_OUT_FMT_C3_SEL_ALPHA)); |
||
| 546 | OUT_ACCEL_REG(R300_US_OUT_FMT_2, (R300_OUT_FMT_UNUSED | |
||
| 547 | R300_OUT_FMT_C0_SEL_BLUE | |
||
| 548 | R300_OUT_FMT_C1_SEL_GREEN | |
||
| 549 | R300_OUT_FMT_C2_SEL_RED | |
||
| 550 | R300_OUT_FMT_C3_SEL_ALPHA)); |
||
| 551 | OUT_ACCEL_REG(R300_US_OUT_FMT_3, (R300_OUT_FMT_UNUSED | |
||
| 552 | R300_OUT_FMT_C0_SEL_BLUE | |
||
| 553 | R300_OUT_FMT_C1_SEL_GREEN | |
||
| 554 | R300_OUT_FMT_C2_SEL_RED | |
||
| 555 | R300_OUT_FMT_C3_SEL_ALPHA)); |
||
| 556 | FINISH_ACCEL(); |
||
| 557 | |||
| 558 | |||
| 559 | |||
| 560 | OUT_ACCEL_REG(R300_FG_DEPTH_SRC, 0); |
||
| 561 | OUT_ACCEL_REG(R300_FG_FOG_BLEND, 0); |
||
| 562 | OUT_ACCEL_REG(R300_FG_ALPHA_FUNC, 0); |
||
| 563 | FINISH_ACCEL(); |
||
| 564 | |||
| 565 | |||
| 566 | OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0); |
||
| 567 | OUT_ACCEL_REG(R300_RB3D_ZSTENCILCNTL, 0); |
||
| 568 | OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
||
| 569 | OUT_ACCEL_REG(R300_RB3D_BW_CNTL, 0); |
||
| 570 | OUT_ACCEL_REG(R300_RB3D_ZCNTL, 0); |
||
| 571 | OUT_ACCEL_REG(R300_RB3D_ZTOP, 0); |
||
| 572 | OUT_ACCEL_REG(R300_RB3D_ROPCNTL, 0); |
||
| 573 | |||
| 574 | |||
| 575 | OUT_ACCEL_REG(R300_RB3D_COLOR_CHANNEL_MASK, (R300_BLUE_MASK_EN | |
||
| 576 | R300_GREEN_MASK_EN | |
||
| 577 | R300_RED_MASK_EN | |
||
| 578 | R300_ALPHA_MASK_EN)); |
||
| 579 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
||
| 580 | OUT_ACCEL_REG(R300_RB3D_CCTL, 0); |
||
| 581 | OUT_ACCEL_REG(R300_RB3D_DITHER_CTL, 0); |
||
| 582 | OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
||
| 583 | FINISH_ACCEL(); |
||
| 584 | |||
| 585 | |||
| 586 | OUT_ACCEL_REG(R300_SC_EDGERULE, 0xA5294A5); |
||
| 587 | OUT_ACCEL_REG(R300_SC_SCISSOR0, ((0 << R300_SCISSOR_X_SHIFT) | |
||
| 588 | (0 << R300_SCISSOR_Y_SHIFT))); |
||
| 589 | OUT_ACCEL_REG(R300_SC_SCISSOR1, ((8191 << R300_SCISSOR_X_SHIFT) | |
||
| 590 | (8191 << R300_SCISSOR_Y_SHIFT))); |
||
| 591 | |||
| 592 | |||
| 593 | /* clip has offset 1440 */ |
||
| 594 | OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1088 << R300_CLIP_X_SHIFT) | |
||
| 595 | (1088 << R300_CLIP_Y_SHIFT))); |
||
| 596 | OUT_ACCEL_REG(R300_SC_CLIP_0_B, (((1080 + 2920) << R300_CLIP_X_SHIFT) | |
||
| 597 | ((1080 + 2920) << R300_CLIP_Y_SHIFT))); |
||
| 598 | } else { |
||
| 599 | OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((0 << R300_CLIP_X_SHIFT) | |
||
| 600 | (0 << R300_CLIP_Y_SHIFT))); |
||
| 601 | OUT_ACCEL_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) | |
||
| 602 | (4080 << R300_CLIP_Y_SHIFT))); |
||
| 603 | } |
||
| 604 | OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA); |
||
| 605 | OUT_ACCEL_REG(R300_SC_SCREENDOOR, 0xffffff); |
||
| 606 | FINISH_ACCEL(); |
||
| 607 | } else if ((rhdPtr->ChipSet == CHIP_FAMILY_RV250) || |
||
| 608 | (rhdPtr->ChipSet == CHIP_FAMILY_RV280) || |
||
| 609 | (rhdPtr->ChipSet == CHIP_FAMILY_RS300) || |
||
| 610 | (rhdPtr->ChipSet == CHIP_FAMILY_R200)) { |
||
| 611 | |||
| 612 | |||
| 613 | if (rhdPtr->ChipSet == CHIP_FAMILY_RS300) { |
||
| 614 | OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS); |
||
| 615 | } else { |
||
| 616 | OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, 0); |
||
| 617 | } |
||
| 618 | OUT_ACCEL_REG(R200_PP_CNTL_X, 0); |
||
| 619 | OUT_ACCEL_REG(R200_PP_TXMULTI_CTL_0, 0); |
||
| 620 | OUT_ACCEL_REG(R200_SE_VTX_STATE_CNTL, 0); |
||
| 621 | OUT_ACCEL_REG(R200_RE_CNTL, 0x0); |
||
| 622 | OUT_ACCEL_REG(R200_SE_VTE_CNTL, 0); |
||
| 623 | OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE | |
||
| 624 | R200_VAP_VF_MAX_VTX_NUM); |
||
| 625 | FINISH_ACCEL(); |
||
| 626 | |||
| 627 | |||
| 628 | OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0); |
||
| 629 | OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); |
||
| 630 | OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0); |
||
| 631 | OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); |
||
| 632 | OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | |
||
| 633 | RADEON_BFACE_SOLID | |
||
| 634 | RADEON_FFACE_SOLID | |
||
| 635 | RADEON_VTX_PIX_CENTER_OGL | |
||
| 636 | RADEON_ROUND_MODE_ROUND | |
||
| 637 | RADEON_ROUND_PREC_4TH_PIX)); |
||
| 638 | FINISH_ACCEL(); |
||
| 639 | } else { |
||
| 640 | BEGIN_ACCEL(2); |
||
| 641 | if ((rhdPtr->ChipSet == CHIP_FAMILY_RADEON) || |
||
| 642 | (rhdPtr->ChipSet == CHIP_FAMILY_RV200)) |
||
| 643 | OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, 0); |
||
| 644 | else |
||
| 645 | OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS); |
||
| 646 | OUT_ACCEL_REG(RADEON_SE_COORD_FMT, |
||
| 647 | RADEON_VTX_XY_PRE_MULT_1_OVER_W0 | |
||
| 648 | RADEON_VTX_ST0_NONPARAMETRIC | |
||
| 649 | RADEON_VTX_ST1_NONPARAMETRIC | |
||
| 650 | RADEON_TEX1_W_ROUTING_USE_W0); |
||
| 651 | FINISH_ACCEL(); |
||
| 652 | |||
| 653 | |||
| 654 | OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0); |
||
| 655 | OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); |
||
| 656 | OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0); |
||
| 657 | OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); |
||
| 658 | OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | |
||
| 659 | RADEON_BFACE_SOLID | |
||
| 660 | RADEON_FFACE_SOLID | |
||
| 661 | RADEON_VTX_PIX_CENTER_OGL | |
||
| 662 | RADEON_ROUND_MODE_ROUND | |
||
| 663 | RADEON_ROUND_PREC_4TH_PIX)); |
||
| 664 | FINISH_ACCEL(); |
||
| 665 | } |
||
| 666 | |||
| 667 | |||
| 668 |