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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1814 | yogev_ezra | 1 | /*===================================================================== |
| 2 | Macros.c -> Macros used on the opcode execution. |
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| 3 | |||
| 4 | This program is free software; you can redistribute it and/or modify |
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| 5 | it under the terms of the GNU General Public License as published by |
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| 6 | the Free Software Foundation; either version 2 of the License, or |
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| 7 | (at your option) any later version. |
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| 8 | |||
| 9 | This program is distributed in the hope that it will be useful, |
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| 10 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 12 | GNU General Public License for more details. |
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| 13 | |||
| 14 | You should have received a copy of the GNU General Public License |
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| 15 | along with this program; if not, write to the Free Software |
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| 16 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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| 17 | |||
| 18 | Copyright (c) 2000 Santiago Romero Iglesias. |
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| 19 | Email: sromero@escomposlinux.org |
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| 20 | ======================================================================*/ |
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| 21 | |||
| 22 | /* defines for the registers: faster access to them when coding... */ |
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| 23 | |||
| 24 | #define r_PC regs->PC.W |
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| 25 | #define r_PCl regs->PC.B.l |
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| 26 | #define r_PCh regs->PC.B.h |
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| 27 | #define r_SP regs->SP.W |
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| 28 | #define r_IFF1 regs->IFF1 |
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| 29 | #define r_IFF2 regs->IFF2 |
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| 30 | #define r_R regs->R.W |
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| 31 | |||
| 32 | #define r_AF regs->AF.W |
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| 33 | #define r_A regs->AF.B.h |
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| 34 | #define r_F regs->AF.B.l |
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| 35 | #define r_BC regs->BC.W |
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| 36 | #define r_B regs->BC.B.h |
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| 37 | #define r_C regs->BC.B.l |
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| 38 | #define r_DE regs->DE.W |
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| 39 | #define r_D regs->DE.B.h |
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| 40 | #define r_E regs->DE.B.l |
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| 41 | #define r_HL regs->HL.W |
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| 42 | #define r_H regs->HL.B.h |
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| 43 | #define r_L regs->HL.B.l |
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| 44 | #define r_IX regs->IX.W |
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| 45 | #define r_IXh regs->IX.B.h |
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| 46 | #define r_IXl regs->IX.B.l |
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| 47 | #define r_IY regs->IY.W |
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| 48 | #define r_IYh regs->IY.B.h |
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| 49 | #define r_IYl regs->IY.B.l |
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| 50 | |||
| 51 | #define r_AFs regs->AFs.W |
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| 52 | #define r_As regs->AFs.B.h |
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| 53 | #define r_Fs regs->AFs.B.l |
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| 54 | #define r_BCs regs->BCs.W |
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| 55 | #define r_Bs regs->BCs.B.h |
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| 56 | #define r_Cs regs->BCs.B.l |
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| 57 | #define r_DEs regs->DEs.W |
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| 58 | #define r_Ds regs->DEs.B.h |
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| 59 | #define r_Es regs->DEs.B.l |
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| 60 | #define r_HLs regs->HLs.W |
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| 61 | #define r_Hs regs->HLs.B.h |
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| 62 | #define r_Ls regs->HLs.B.l |
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| 63 | #define r_IXs regs->IX.W |
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| 64 | #define r_IXhs regs->IX.B.h |
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| 65 | #define r_IXls regs->IX.B.l |
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| 66 | #define r_IYs regs->IY.W |
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| 67 | #define r_IYhs regs->IY.B.h |
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| 68 | #define r_IYls regs->IY.B.l |
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| 69 | |||
| 70 | #define r_op ops.W |
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| 71 | #define r_oph ops.B.h |
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| 72 | #define r_opl ops.B.l |
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| 73 | #define r_tmp tmpreg2.W |
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| 74 | #define r_tmph tmpreg2.B.h |
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| 75 | #define r_tmpl tmpreg2.B.l |
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| 76 | #define r_mem mread.W |
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| 77 | #define r_memh mread.B.h |
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| 78 | #define r_meml mread.B.l |
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| 79 | |||
| 80 | #ifndef _DISASM_ |
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| 81 | /*--- Flag tables by Philip Kendall, taken from it's fuse emulator -*/ |
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| 82 | /*--- I was having headache trying to emulate correctly the FLAGS, |
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| 83 | so I finished using the FLAG tables used by P. Kendall. ------*/ |
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| 84 | #define FLAG_C 0x01 |
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| 85 | #define FLAG_N 0x02 |
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| 86 | #define FLAG_P 0x04 |
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| 87 | #define FLAG_V FLAG_P |
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| 88 | #define FLAG_3 0x08 |
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| 89 | #define FLAG_H 0x10 |
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| 90 | #define FLAG_5 0x20 |
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| 91 | #define FLAG_Z 0x40 |
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| 92 | #define FLAG_S 0x80 |
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| 93 | |||
| 94 | /* Whether a half carry occured or not can be determined by looking at |
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| 95 | the 3rd bit of the two arguments and the result; these are hashed |
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| 96 | into this table in the form r12, where r is the 3rd bit of the |
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| 97 | result, 1 is the 3rd bit of the 1st argument and 2 is the |
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| 98 | third bit of the 2nd argument; the tables differ for add and subtract |
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| 99 | operations */ |
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| 100 | |||
| 101 | /* Whether a half carry occured or not can be determined by looking at |
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| 102 | the 3rd bit of the two arguments and the result; these are hashed |
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| 103 | into this table in the form r12, where r is the 3rd bit of the |
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| 104 | result, 1 is the 3rd bit of the 1st argument and 2 is the |
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| 105 | third bit of the 2nd argument; the tables differ for add and subtract |
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| 106 | operations */ |
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| 107 | byte halfcarry_add_table[] = { 0, FLAG_H, FLAG_H, FLAG_H, 0, 0, 0, FLAG_H }; |
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| 108 | byte halfcarry_sub_table[] = { 0, 0, FLAG_H, 0, FLAG_H, 0, FLAG_H, FLAG_H }; |
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| 109 | |||
| 110 | /* Similarly, overflow can be determined by looking at the 7th bits; again |
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| 111 | the hash into this table is r12 */ |
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| 112 | byte overflow_add_table[] = { 0, 0, 0, FLAG_V, FLAG_V, 0, 0, 0 }; |
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| 113 | byte overflow_sub_table[] = { 0, FLAG_V, 0, 0, 0, 0, FLAG_V, 0 }; |
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| 114 | |||
| 115 | /* Some more tables; initialised in z80_init_tables() */ |
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| 116 | byte sz53_table[0x100]; /* The S, Z, 5 and 3 bits of the temp value */ |
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| 117 | byte parity_table[0x100]; /* The parity of the temp value */ |
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| 118 | byte sz53p_table[0x100]; /* OR the above two tables together */ |
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| 119 | /*------------------------------------------------------------------*/ |
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| 120 | |||
| 121 | // Contributed by Metalbrain to implement OUTI, etc. |
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| 122 | byte ioblock_inc1_table[64]; |
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| 123 | byte ioblock_dec1_table[64]; |
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| 124 | byte ioblock_2_table[0x100]; |
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| 125 | |||
| 126 | /*--- Memory Write on the A address on no bank machines -------------*/ |
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| 127 | void Z80WriteMem( word where, word A, Z80Regs *regs) |
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| 128 | { |
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| 129 | if( where >= 16384 ) |
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| 130 | regs->RAM[where] = A; |
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| 131 | } |
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| 132 | |||
| 133 | #endif |
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| 134 | |||
| 135 | |||
| 136 | /*--- Memory Read from the A address on no bank machines -------------*/ |
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| 137 | #define Z80ReadMem(A) ((regs->RAM[(A)])) |
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| 138 | |||
| 139 | // return( regs->RAM[A] ); |
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| 140 | |||
| 141 | |||
| 142 | /* macros to change the ICount register */ |
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| 143 | #define AddCycles(n) regs->ICount-=(n) |
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| 144 | |||
| 145 | #define SubCycles(n) regs->ICount+=(n) |
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| 146 | |||
| 147 | //#define AddR(n) r_R = (r_R+(n)) |
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| 148 | #define AddR(n) r_R = ((r_R & 0x80) | ((r_R+(n)) & 0x7f )) |
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| 149 | #define SubR(n) r_R = ((r_R & 0x80) | ((r_R-(n)) & 0x7f )) |
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| 150 | |||
| 151 | |||
| 152 | /* setting and resetting the flag bits: */ |
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| 153 | #define SET_FLAG(flag) (r_F |= (flag)) |
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| 154 | |||
| 155 | #define RESET_FLAG(flag) (r_F &= ~(flag)) |
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| 156 | |||
| 157 | #define TEST_FLAG(flag) (r_F & (flag)) |
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| 158 | |||
| 159 | |||
| 160 | /* store a given register in the stack (hi and lo bytes) */ |
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| 161 | #define PUSH(rreg) \ |
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| 162 | Z80WriteMem( --(r_SP), regs->rreg.B.h, regs); \ |
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| 163 | Z80WriteMem( --(r_SP), regs->rreg.B.l, regs) |
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| 164 | |||
| 165 | #define POP(rreg)\ |
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| 166 | regs->rreg.B.l = Z80ReadMem(r_SP); r_SP++;\ |
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| 167 | regs->rreg.B.h = Z80ReadMem(r_SP); r_SP++ |
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| 168 | |||
| 169 | #define PUSH_IXYr() \ |
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| 170 | Z80WriteMem( --(r_SP), REGH, regs); \ |
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| 171 | Z80WriteMem( --(r_SP), REGL, regs) |
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| 172 | |||
| 173 | #define POP_IXYr()\ |
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| 174 | REGL = Z80ReadMem(r_SP); r_SP++; \ |
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| 175 | REGH = Z80ReadMem(r_SP); r_SP++ |
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| 176 | |||
| 177 | #define RST(rstval) PUSH(PC); r_PC=(rstval) |
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| 178 | |||
| 179 | |||
| 180 | /*--- Move data to mem or regs --------------------------------------*/ |
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| 181 | #define LD_r_r(dreg, sreg) (dreg) = (sreg) |
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| 182 | |||
| 183 | #define STORE_r(daddreg, sreg) Z80WriteMem((daddreg), (sreg), regs) |
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| 184 | |||
| 185 | #define STORE_nn_rr(dreg) \ |
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| 186 | r_opl = Z80ReadMem(r_PC); r_PC++;\ |
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| 187 | r_oph = Z80ReadMem(r_PC); r_PC++; \ |
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| 188 | r_tmp = dreg; \ |
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| 189 | Z80WriteMem((r_op),r_tmpl, regs); \ |
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| 190 | Z80WriteMem((r_op+1),r_tmph, regs) |
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| 191 | |||
| 192 | #define STORE_nn_r(sreg) \ |
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| 193 | r_opl = Z80ReadMem(r_PC); r_PC++; \ |
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| 194 | r_oph = Z80ReadMem(r_PC); r_PC++; \ |
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| 195 | Z80WriteMem((r_op),(sreg), regs) |
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| 196 | |||
| 197 | #define LOAD_r(dreg, saddreg) (dreg)=Z80ReadMem((saddreg)) |
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| 198 | |||
| 199 | #define LOAD_rr_nn(dreg) r_opl = Z80ReadMem(r_PC); r_PC++; \ |
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| 200 | r_oph = Z80ReadMem(r_PC); r_PC++; \ |
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| 201 | r_tmpl = Z80ReadMem(r_op); \ |
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| 202 | r_tmph = Z80ReadMem((r_op)+1); \ |
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| 203 | dreg=r_tmp |
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| 204 | |||
| 205 | |||
| 206 | #define LOAD_r_nn(dreg) r_opl = Z80ReadMem(r_PC); r_PC++; \ |
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| 207 | r_oph = Z80ReadMem(r_PC); r_PC++; \ |
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| 208 | dreg = Z80ReadMem(r_op) |
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| 209 | |||
| 210 | #define LD_r_n(reg) (reg) = Z80ReadMem(r_PC++) |
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| 211 | |||
| 212 | #define LD_rr_nn(reg) r_opl = Z80ReadMem(r_PC); r_PC++; \ |
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| 213 | r_oph = Z80ReadMem(r_PC); r_PC++; \ |
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| 214 | reg = r_op |
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| 215 | |||
| 216 | #define EX(reg1,reg2) r_opl=(reg1); (reg1)=(reg2); (reg2)=r_opl |
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| 217 | |||
| 218 | #define EX_WORD(reg1,reg2) r_op=(reg1); (reg1)=(reg2); (reg2)=r_op |
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| 219 | |||
| 220 | /*--- Increments/Decrements -----------------------------------------*/ |
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| 221 | #define INC(reg) (reg)++; \ |
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| 222 | r_F = ( r_F & FLAG_C ) | ( (reg)==0x80 ? FLAG_V : 0 ) | \ |
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| 223 | ( (reg)&0x0f ? 0 : FLAG_H ) | ( (reg) ? 0 : FLAG_Z ) | \ |
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| 224 | sz53_table[(reg)] |
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| 225 | |||
| 226 | #define DEC(reg) \ |
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| 227 | r_F = ( r_F & FLAG_C ) | ( (reg)&0x0f ? 0 : FLAG_H ) | FLAG_N; \ |
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| 228 | (reg)--; \ |
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| 229 | r_F |= ( (reg)==0x7f ? FLAG_V : 0 ) | sz53_table[(reg)] |
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| 230 | |||
| 231 | // it was: |
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| 232 | // r_F |= ( (reg)==0x79 ? FLAG_V : 0 ) | sz53_table[(reg)] |
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| 233 | // But Kak pointed my was not 0x79 -> 0x7F, changed 7-3-2001 |
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| 234 | |||
| 235 | |||
| 236 | /*--- Bit operations ------------------------------------------------*/ |
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| 237 | #define BIT_RES(b,reg) reg &= ~(0x1< |
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| 238 | |||
| 239 | #define BIT_SET(b,reg) reg |= (0x1< |
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| 240 | |||
| 241 | #define BIT_mem_RES(b,addr) r_opl = Z80ReadMem(addr); \ |
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| 242 | r_opl &= ~(0x1< |
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| 243 | Z80WriteMem(addr, r_opl, regs) |
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| 244 | |||
| 245 | #define BIT_mem_SET(b,addr) r_opl = Z80ReadMem(addr); \ |
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| 246 | r_opl |= (0x1< |
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| 247 | Z80WriteMem(addr, r_opl, regs) |
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| 248 | |||
| 249 | #define BIT_RES_mem(b,addr,reg) reg &= ~(0x1< |
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| 250 | Z80WriteMem((addr), (reg), regs) |
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| 251 | |||
| 252 | #define BIT_SET_mem(b,addr,reg) reg |= (0x1< |
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| 253 | Z80WriteMem((addr), (reg), regs) |
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| 254 | |||
| 255 | #define BIT_BIT(b,reg) r_F = ( r_F & FLAG_C ) | \ |
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| 256 | ( (reg) & ( FLAG_3 | FLAG_5 ) ) |\ |
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| 257 | (((reg) & ( 0x01 << b ) ) ? FLAG_H : \ |
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| 258 | (FLAG_P|FLAG_H|FLAG_Z ) ) |
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| 259 | |||
| 260 | #define BIT_mem_BIT(b,reg) r_opl = Z80ReadMem(reg); \ |
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| 261 | r_F = ( r_F & FLAG_C ) | \ |
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| 262 | ( (r_opl) & ( FLAG_3 | FLAG_5 ) ) |\ |
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| 263 | (((r_opl) & ( 0x01 << b ) ) ? FLAG_H : \ |
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| 264 | (FLAG_P|FLAG_H|FLAG_Z ) ) |
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| 265 | |||
| 266 | #define BIT_BIT7(reg) r_F = ( r_F & FLAG_C ) | ( (reg) & \ |
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| 267 | ( FLAG_3 | FLAG_5 ) ) |\ |
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| 268 | (((reg) & 0x80 ) ? ( FLAG_H | FLAG_S ) :\ |
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| 269 | ( FLAG_P | FLAG_H | FLAG_Z ) ) |
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| 270 | |||
| 271 | #define BIT_mem_BIT7(reg) r_opl = Z80ReadMem(reg); \ |
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| 272 | r_F = ( r_F & FLAG_C ) | ( (r_opl) & \ |
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| 273 | ( FLAG_3 | FLAG_5 ) ) |\ |
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| 274 | (((r_opl) & 0x80 ) ? ( FLAG_H | FLAG_S ) :\ |
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| 275 | ( FLAG_P | FLAG_H | FLAG_Z ) ) |
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| 276 | |||
| 277 | |||
| 278 | #define RLC(reg) (reg) = ( (reg)<<1 ) | ( (reg)>>7 ); \ |
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| 279 | r_F = ( (reg) & FLAG_C ) | sz53p_table[(reg)] |
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| 280 | |||
| 281 | #define RRC(reg) r_F = (reg) & FLAG_C; \ |
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| 282 | (reg) = ( (reg)>>1 ) | ( (reg)<<7 );\ |
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| 283 | r_F |= sz53p_table[(reg)] |
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| 284 | |||
| 285 | #define RL(reg) r_opl = (reg); \ |
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| 286 | (reg) = ( (reg)<<1 ) | ( r_F & FLAG_C ); \ |
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| 287 | r_F = ( r_opl >> 7 ) | sz53p_table[(reg)] |
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| 288 | |||
| 289 | #define RR(reg) r_opl = (reg); \ |
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| 290 | (reg) = ( (reg)>>1 ) | ( r_F << 7 );\ |
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| 291 | r_F = ( r_opl & FLAG_C ) | sz53p_table[(reg)] |
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| 292 | |||
| 293 | #define SLA(reg) r_F = (reg) >> 7;\ |
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| 294 | (reg) <<= 1;\ |
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| 295 | r_F |= sz53p_table[(reg)] |
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| 296 | |||
| 297 | #define SRA(reg) r_F = (reg) & FLAG_C; \ |
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| 298 | (reg) = ( (reg) & 0x80 ) | ( (reg) >> 1 );\ |
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| 299 | r_F |= sz53p_table[(reg)] |
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| 300 | |||
| 301 | #define SLL(reg) r_F = (reg) >> 7;\ |
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| 302 | (reg) = ( (reg) << 1 ) | 0x01;\ |
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| 303 | r_F |= sz53p_table[(reg)] |
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| 304 | |||
| 305 | #define SRL(reg) r_F = (reg) & FLAG_C;\ |
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| 306 | (reg) >>= 1;\ |
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| 307 | r_F |= sz53p_table[(reg)] |
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| 308 | |||
| 309 | |||
| 310 | |||
| 311 | /*--- JP operations -------------------------------------------------*/ |
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| 312 | #define JP_nn() r_opl = Z80ReadMem(r_PC); \ |
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| 313 | r_PC++; \ |
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| 314 | r_oph = Z80ReadMem(r_PC); \ |
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| 315 | r_PC = r_op |
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| 316 | |||
| 317 | #define JR_n() r_PC += (offset) (Z80ReadMem(r_PC)); r_PC++ |
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| 318 | |||
| 319 | #define RET_nn() r_PCl = Z80ReadMem (r_SP); r_SP++; \ |
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| 320 | r_PCh = Z80ReadMem (r_SP); r_SP++; |
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| 321 | |||
| 322 | #define CALL_nn() r_opl = Z80ReadMem (r_PC); r_PC++; \ |
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| 323 | r_oph = Z80ReadMem (r_PC); r_PC++; \ |
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| 324 | Z80WriteMem( --(r_SP), r_PCh, regs ); \ |
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| 325 | Z80WriteMem( --(r_SP), r_PCl, regs ); \ |
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| 326 | r_PC = r_op |
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| 327 | |||
| 328 | |||
| 329 | /*--- ALU operations ------------------------------------------------*/ |
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| 330 | #define AND(reg) r_A &= (reg); \ |
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| 331 | r_F = FLAG_H | sz53p_table[r_A] |
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| 332 | |||
| 333 | #define OR(reg) r_A |= (reg); \ |
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| 334 | r_F = sz53p_table[r_A] |
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| 335 | |||
| 336 | #define XOR(reg) r_A ^= (reg); \ |
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| 337 | r_F = sz53p_table[r_A] |
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| 338 | |||
| 339 | #define AND_mem(raddress) r_opl = Z80ReadMem(raddress); \ |
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| 340 | r_A &= (r_opl); \ |
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| 341 | r_F = FLAG_H | sz53p_table[r_A] |
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| 342 | |||
| 343 | #define OR_mem(raddress) r_opl = Z80ReadMem(raddress); \ |
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| 344 | r_A |= (r_opl); \ |
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| 345 | r_F = sz53p_table[r_A] |
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| 346 | |||
| 347 | #define XOR_mem(raddress) r_opl = Z80ReadMem(raddress); \ |
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| 348 | r_A ^= (r_opl); \ |
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| 349 | r_F = sz53p_table[r_A] |
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| 350 | |||
| 351 | #define ADD(val) tempword = r_A + (val); \ |
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| 352 | r_oph = ((r_A&0x88)>>3)|(((val)&0x88)>>2) | \ |
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| 353 | ( (tempword & 0x88) >> 1 ); \ |
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| 354 | r_A = tempword; \ |
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| 355 | r_F = ( tempword & 0x100 ? FLAG_C : 0 ) | \ |
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| 356 | halfcarry_add_table[ r_oph & 0x07] | \ |
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| 357 | overflow_add_table[ r_oph >> 4] | \ |
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| 358 | sz53_table[r_A] |
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| 359 | |||
| 360 | #define ADD_WORD(value1,value2) \ |
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| 361 | tempdword = (value1) + (value2); \ |
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| 362 | r_oph = ( ( (value1) & 0x0800 ) >> 11 ) | \ |
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| 363 | ( ( (value2) & 0x0800 ) >> 10 ) | \ |
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| 364 | ( ( tempdword & 0x0800 ) >> 9 ); \ |
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| 365 | (value1) = tempdword; \ |
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| 366 | r_F = ( r_F & ( FLAG_V | FLAG_Z | FLAG_S ) ) | \ |
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| 367 | ( tempdword & 0x10000 ? FLAG_C : 0 ) | \ |
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| 368 | (( tempdword >> 8 ) & ( FLAG_3 | FLAG_5 ) ) | \ |
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| 369 | halfcarry_add_table[r_oph] |
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| 370 | |||
| 371 | #define ADC(value) \ |
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| 372 | tempword = r_A + (value) + ( r_F & FLAG_C ); \ |
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| 373 | r_oph = ( (r_A & 0x88) >> 3 ) | ( ( (value) & 0x88 ) >> 2 ) |\ |
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| 374 | ( (tempword & 0x88) >> 1 ); \ |
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| 375 | r_A = tempword; \ |
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| 376 | r_F = ( tempword & 0x100 ? FLAG_C : 0 ) | \ |
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| 377 | halfcarry_add_table[r_oph & 0x07] | \ |
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| 378 | overflow_add_table[r_oph >> 4] | \ |
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| 379 | sz53_table[r_A] |
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| 380 | |||
| 381 | #define ADC_WORD(value) \ |
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| 382 | tempdword= r_HL + (value) + ( r_F & FLAG_C ); \ |
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| 383 | r_oph = ( ( r_HL & 0x8800 ) >> 11 ) | \ |
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| 384 | ( ( (value) & 0x8800 ) >> 10 ) | \ |
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| 385 | ( ( tempdword & 0x8800 ) >> 9 ); \ |
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| 386 | r_HL = tempdword; \ |
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| 387 | r_F = ( tempdword & 0x10000 ? FLAG_C : 0 )| \ |
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| 388 | overflow_add_table[r_oph >> 4] | \ |
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| 389 | ( r_H & ( FLAG_3 | FLAG_5 | FLAG_S ) ) | \ |
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| 390 | halfcarry_add_table[ r_oph & 0x0f ]| \ |
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| 391 | ( r_HL ? 0 : FLAG_Z ) |
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| 392 | |||
| 393 | #define SUB(value) \ |
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| 394 | tempword = r_A - (value);\ |
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| 395 | r_opl = ( (r_A & 0x88) >> 3 ) | \ |
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| 396 | ( ( (value) & 0x88 ) >> 2 ) | \ |
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| 397 | ( (tempword & 0x88) >> 1 ); \ |
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| 398 | r_A = tempword; \ |
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| 399 | r_F = ( tempword & 0x100 ? FLAG_C : 0 ) | FLAG_N | \ |
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| 400 | halfcarry_sub_table[r_opl & 0x07] | \ |
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| 401 | overflow_sub_table[r_opl >> 4] | \ |
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| 402 | sz53_table[r_A] |
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| 403 | |||
| 404 | #define SBC(value) \ |
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| 405 | tempword = r_A - (value) - ( r_F & FLAG_C ); \ |
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| 406 | r_opl = ( (r_A & 0x88) >> 3 ) | \ |
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| 407 | ( ( (value) & 0x88 ) >> 2 ) | \ |
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| 408 | ( (tempword & 0x88) >> 1 ); \ |
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| 409 | r_A = tempword; \ |
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| 410 | r_F = ( tempword & 0x100 ? FLAG_C : 0 ) | FLAG_N | \ |
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| 411 | halfcarry_sub_table[r_opl & 0x07] | \ |
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| 412 | overflow_sub_table[r_opl >> 4] | \ |
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| 413 | sz53_table[r_A] |
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| 414 | |||
| 415 | |||
| 416 | #define SBC_WORD(Rg) \ |
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| 417 | tempword=r_F & C_FLAG; r_op=(r_HL-Rg-tempword)&0xFFFF; \ |
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| 418 | r_F= \ |
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| 419 | N_FLAG| \ |
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| 420 | (((long)r_HL-(long)Rg-(long)tempword)&0x10000? C_FLAG:0)| \ |
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| 421 | ((r_HL^Rg)&(r_HL^r_op)&0x8000? O_FLAG:0)| \ |
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| 422 | ((r_HL^Rg^r_op)&0x1000? H_FLAG:0)| \ |
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| 423 | (r_op? 0:Z_FLAG)|(r_oph&S_FLAG); \ |
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| 424 | r_HL=r_op |
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| 425 | |||
| 426 | #define CP(value) \ |
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| 427 | tempword = r_A - (value);\ |
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| 428 | r_opl = ( (r_A & 0x88) >> 3 ) | ( ( (value) & 0x88 ) >> 2 ) | \ |
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| 429 | ( (tempword & 0x88) >> 1 ); \ |
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| 430 | r_F = ( tempword & 0x100 ? FLAG_C : ( tempword ? 0 : FLAG_Z ) ) | FLAG_N |\ |
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| 431 | halfcarry_sub_table[r_opl & 0x07] | \ |
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| 432 | overflow_sub_table[r_opl >> 4] | \ |
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| 433 | ( value & ( FLAG_3 | FLAG_5 ) ) | \ |
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| 434 | ( tempword & FLAG_S ) |
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| 435 | |||
| 436 | #define NEG_A() r_opl = r_A; r_A=0; SUB(r_opl) |
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| 437 | |||
| 438 | /*--- MISC operations -----------------------------------------------*/ |
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| 439 | #define IN(reg,port) (reg)=Z80InPort((port)); \ |
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| 440 | r_F = ( r_F & FLAG_C) | sz53p_table[(reg)] |
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| 441 | |||
| 442 | |||
| 443 | |||
| 444 | |||
| 445 | |||
| 446 | |||
| 447 |