WebSVN – Kolibri OS – Blame – /kernel/trunk/network/eth_drv/drivers/rtl8139.inc

Rev	Author	Line No.	Line
261	hidnplayr	1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		2	;; ;;
		3	;; RTL8139.INC ;;
		4	;; ;;
		5	;; Ethernet driver for Menuet OS ;;
		6	;; ;;
		7	;; Version 0.2 11 August 2003 ;;
		8	;; ;;
		9	;; Driver for chips of RealTek 8139 family ;;
		10	;; References: ;;
		11	;; www.realtek.com.hw - data sheets ;;
		12	;; rtl8139.c - linux driver ;;
		13	;; 8139too.c - linux driver ;;
		14	;; ethernet driver template by Mike Hibbett ;;
		15	;; ;;
		16	;; The copyright statement is ;;
		17	;; ;;
		18	;; GNU GENERAL PUBLIC LICENSE ;;
		19	;; Version 2, June 1991 ;;
		20	;; ;;
		21	;; Copyright 2003 Endre Kozma, ;;
		22	;; endre.kozma@axelero.hu ;;
		23	;; ;;
		24	;; See file COPYING for details ;;
		25	;; ;;
		26	;; ;;
		27	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		28	ETH_ALEN equ 6
		29	ETH_HLEN equ (2 * ETH_ALEN + 2)
		30	ETH_ZLEN equ 60 ; 60 + 4bytes auto payload for
		31	; mininmum 64bytes frame length
		32
		33	PCI_REG_COMMAND equ 0x04 ; command register
		34	PCI_BIT_PIO equ 0 ; bit0: io space control
		35	PCI_BIT_MMIO equ 1 ; bit1: memory space control
		36	PCI_BIT_MASTER equ 2 ; bit2: device acts as a PCI master
		37
		38	RTL8139_REG_MAR0 equ 0x08 ; multicast filter register 0
		39	RTL8139_REG_MAR4 equ 0x0c ; multicast filter register 4
		40	RTL8139_REG_TSD0 equ 0x10 ; transmit status of descriptor
		41	RTL8139_REG_TSAD0 equ 0x20 ; transmit start address of descriptor
		42	RTL8139_REG_RBSTART equ 0x30 ; RxBuffer start address
		43	RTL8139_REG_COMMAND equ 0x37 ; command register
		44	RTL8139_REG_CAPR equ 0x38 ; current address of packet read
		45	RTL8139_REG_IMR equ 0x3c ; interrupt mask register
		46	RTL8139_REG_ISR equ 0x3e ; interrupt status register
		47	RTL8139_REG_TXCONFIG equ 0x40 ; transmit configuration register
		48	RTL8139_REG_TXCONFIG_0 equ 0x40 ; transmit configuration register 0
		49	RTL8139_REG_TXCONFIG_1 equ 0x41 ; transmit configuration register 1
		50	RTL8139_REG_TXCONFIG_2 equ 0x42 ; transmit configuration register 2
		51	RTL8139_REG_TXCONFIG_3 equ 0x43 ; transmit configuration register 3
		52	RTL8139_REG_RXCONFIG equ 0x44 ; receive configuration register 0
		53	RTL8139_REG_RXCONFIG_0 equ 0x44 ; receive configuration register 0
		54	RTL8139_REG_RXCONFIG_1 equ 0x45 ; receive configuration register 1
		55	RTL8139_REG_RXCONFIG_2 equ 0x46 ; receive configuration register 2
		56	RTL8139_REG_RXCONFIG_3 equ 0x47 ; receive configuration register 3
		57	RTL8139_REG_MPC equ 0x4c ; missed packet counter
		58	RTL8139_REG_9346CR equ 0x50 ; serial eeprom 93C46 command register
		59	RTL8139_REG_CONFIG1 equ 0x52 ; configuration register 1
		60	RTL8139_REG_CONFIG4 equ 0x5a ; configuration register 4
		61	RTL8139_REG_HLTCLK equ 0x5b ; undocumented halt clock register
		62	RTL8139_REG_BMCR equ 0x62 ; basic mode control register
		63	RTL8139_REG_ANAR equ 0x66 ; auto negotiation advertisement register
		64
		65	; 5.1 packet header
		66	RTL8139_BIT_RUNT equ 4 ; total packet length < 64 bytes
		67	RTL8139_BIT_LONG equ 3 ; total packet length > 4k
		68	RTL8139_BIT_CRC equ 2 ; crc error occured
		69	RTL8139_BIT_FAE equ 1 ; frame alignment error occured
		70	RTL8139_BIT_ROK equ 0 ; received packet is ok
		71	; 5.4 command register
		72	RTL8139_BIT_RST equ 4 ; reset bit
		73	RTL8139_BIT_RE equ 3 ; receiver enabled
		74	RTL8139_BIT_TE equ 2 ; transmitter enabled
		75	RTL8139_BIT_BUFE equ 0 ; rx buffer is empty, no packet stored
		76	; 5.6 interrupt status register
		77	RTL8139_BIT_ISR_TOK equ 2 ; transmit ok
		78	RTL8139_BIT_ISR_RER equ 1 ; receive error interrupt
		79	RTL8139_BIT_ISR_ROK equ 0 ; receive ok
		80	; 5.7 transmit configyration register
		81	RTL8139_BIT_TX_MXDMA equ 8 ; Max DMA burst size per Tx DMA burst
		82	RTL8139_BIT_TXRR equ 4 ; Tx Retry count 16+(TXRR*16)
		83	; 5.8 receive configuration register
		84	RTL8139_BIT_RXFTH equ 13 ; Rx fifo threshold
		85	RTL8139_BIT_RBLEN equ 11 ; Ring buffer length indicator
		86	RTL8139_BIT_RX_MXDMA equ 8 ; Max DMA burst size per Rx DMA burst
		87	RTL8139_BIT_NOWRAP equ 7 ; transfered data wrapping
		88	RTL8139_BIT_9356SEL equ 6 ; eeprom selector 9346/9356
		89	RTL8139_BIT_AER equ 5 ; accept error packets
		90	RTL8139_BIT_AR equ 4 ; accept runt packets
		91	RTL8139_BIT_AB equ 3 ; accept broadcast packets
		92	RTL8139_BIT_AM equ 2 ; accept multicast packets
		93	RTL8139_BIT_APM equ 1 ; accept physical match packets
		94	RTL8139_BIT_AAP equ 0 ; accept all packets
		95	; 5.9 93C46/93C56 command register
		96	RTL8139_BIT_93C46_EEM1 equ 7 ; RTL8139 eeprom operating mode1
		97	RTL8139_BIT_93C46_EEM0 equ 6 ; RTL8139 eeprom operating mode0
		98	RTL8139_BIT_93C46_EECS equ 3 ; chip select
		99	RTL8139_BIT_93C46_EESK equ 2 ; serial data clock
		100	RTL8139_BIT_93C46_EEDI equ 1 ; serial data input
		101	RTL8139_BIT_93C46_EEDO equ 0 ; serial data output
		102	; 5.11 configuration register 1
		103	RTL8139_BIT_LWACT equ 4 ; see RTL8139_REG_CONFIG1
		104	RTL8139_BIT_SLEEP equ 1 ; sleep bit at older chips
		105	RTL8139_BIT_PWRDWN equ 0 ; power down bit at older chips
		106	RTL8139_BIT_PMEn equ 0 ; power management enabled
		107	; 5.14 configuration register 4
		108	RTL8139_BIT_LWPTN equ 2 ; see RTL8139_REG_CONFIG4
		109	; 6.2 transmit status register
		110	RTL8139_BIT_ERTXTH equ 16 ; early TX threshold
		111	RTL8139_BIT_TOK equ 15 ; transmit ok
		112	RTL8139_BIT_OWN equ 13 ; tx DMA operation is completed
		113	; 6.18 basic mode control register
		114	RTL8139_BIT_ANE equ 12 ; auto negotiation enable
		115	; 6.20 auto negotiation advertisement register
		116	RTL8139_BIT_TXFD equ 8 ; 100base-T full duplex
		117	RTL8139_BIT_TX equ 7 ; 100base-T
		118	RTL8139_BIT_10FD equ 6 ; 10base-T full duplex
		119	RTL8139_BIT_10 equ 5 ; 10base-T
		120	RTL8139_BIT_SELECTOR equ 0 ; binary encoded selector CSMA/CD=00001
		121	; RX/TX buffer size
		122	RTL8139_RBLEN equ 0 ; 0==8K 1==16k 2==32k 3==64k
		123	RTL8139_RX_BUFFER_SIZE equ (8192 shl RTL8139_RBLEN)
		124	MAX_ETH_FRAME_SIZE equ 1516 ; exactly 1514 wthout CRC
		125	RTL8139_NUM_TX_DESC equ 4
		126	RTL8139_TX_BUFFER_SIZE equ (MAX_ETH_FRAME_SIZE * RTL8139_NUM_TX_DESC)
		127	RTL8139_TXRR equ 8 ; total retries = 16+(TXRR*16)
		128	RTL8139_TX_MXDMA equ 6 ; 0==16 1==32 2==64 3==128
		129	; 4==256 5==512 6==1024 7==2048
		130	RTL8139_ERTXTH equ 8 ; in unit of 32 bytes e.g:(8*32)=256
		131	RTL8139_RX_MXDMA equ 7 ; 0==16 1==32 2==64 3==128
		132	; 4==256 5==512 6==1024 7==unlimited
		133	RTL8139_RXFTH equ 7 ; 0==16 1==32 2==64 3==128
		134	; 4==256 5==512 6==1024 7==no threshold
		135	RTL8139_RX_CONFIG equ ((RTL8139_RBLEN shl RTL8139_BIT_RBLEN) \
		136	or (RTL8139_RX_MXDMA shl RTL8139_BIT_RX_MXDMA) \
		137	or (1 shl RTL8139_BIT_NOWRAP) \
		138	or (RTL8139_RXFTH shl RTL8139_BIT_RXFTH) \
		139	or (1 shl RTL8139_BIT_AB) or (1 shl RTL8139_BIT_APM) \
		140	or (1 shl RTL8139_BIT_AER) or (1 shl RTL8139_BIT_AR) \
		141	or (1 shl RTL8139_BIT_AM))
		142	RTL8139_TX_TIMEOUT equ 30 ; 300 milliseconds timeout
		143
		144	EE_93C46_REG_ETH_ID equ 7 ; MAC offset
		145	EE_93C46_READ_CMD equ (6 shl 6) ; 110b + 6bit address
		146	EE_93C56_READ_CMD equ (6 shl 8) ; 110b + 8bit address
		147	EE_93C46_CMD_LENGTH equ 9 ; start bit + cmd + 6bit address
		148	EE_93C56_CMD_LENGTH equ 11 ; start bit + cmd + 8bit ddress
		149
		150	VER_RTL8139 equ 1100000b
		151	VER_RTL8139A equ 1110000b
		152	; VER_RTL8139AG equ 1110100b
		153	VER_RTL8139B equ 1111000b
		154	VER_RTL8130 equ VER_RTL8139B
		155	VER_RTL8139C equ 1110100b
		156	VER_RTL8100 equ 1111010b
		157	VER_RTL8100B equ 1110101b
		158	VER_RTL8139D equ VER_RTL8100B
		159	VER_RTL8139CP equ 1110110b
		160	VER_RTL8101 equ 1110111b
		161
		162	IDX_RTL8139 equ 0
		163	IDX_RTL8139A equ 1
		164	IDX_RTL8139B equ 2
		165	IDX_RTL8139C equ 3
		166	IDX_RTL8100 equ 4
		167	IDX_RTL8139D equ 5
		168	IDX_RTL8139D equ 6
		169	IDX_RTL8101 equ 7
		170
		171
		172	; These two must be 4 byte aligned ( which they are )
		173	rtl8139_rx_buff equ eth_data_start
		174	rtl8139_tx_buff equ rtl8139_rx_buff + (RTL8139_RX_BUFFER_SIZE + MAX_ETH_FRAME_SIZE)
		175
		176	uglobal
		177	align 4
		178	rtl8139_rx_buff_offset: dd 0
		179	curr_tx_desc: dd 0
		180	endg
		181
		182	iglobal
		183	hw_ver_array: db VER_RTL8139, VER_RTL8139A, VER_RTL8139B, VER_RTL8139C
		184	db VER_RTL8100, VER_RTL8139D, VER_RTL8139CP, VER_RTL8101
		185	HW_VER_ARRAY_SIZE = $-hw_ver_array
		186	endg
		187
		188	uglobal
		189	hw_ver_id: db 0
		190	endg
		191
		192	;***************************************************************************
		193	; Function
		194	; rtl8139_probe
		195	; Description
		196	; Searches for an ethernet card, enables it and clears the rx buffer
		197	; If a card was found, it enables the ethernet -> TCPIP link
		198	; Destroyed registers
		199	; eax, ebx, ecx, edx
		200	;
		201	;***************************************************************************
		202	rtl8139_probe:
		203	; enable the device
		204	mov al, 2
		205	mov ah, [pci_bus]
		206	mov bh, [pci_dev]
		207	mov bl, PCI_REG_COMMAND
		208	call pci_read_reg
		209	mov cx, ax
		210	or cl, (1 shl PCI_BIT_MASTER) or (1 shl PCI_BIT_PIO)
		211	and cl, not (1 shl PCI_BIT_MMIO)
		212	mov al, 2
		213	mov ah, [pci_bus]
		214	mov bh, [pci_dev]
		215	mov bl, PCI_REG_COMMAND
		216	call pci_write_reg
		217	; get chip version
		218	mov edx, [io_addr]
		219	add edx, RTL8139_REG_TXCONFIG_2
		220	in ax, dx
		221	shr ah, 2
		222	shr ax, 6
		223	and al, 01111111b
		224	mov ecx, HW_VER_ARRAY_SIZE-1
		225	.chip_ver_loop:
		226	cmp al, [hw_ver_array+ecx]
		227	je .chip_ver_found
		228	dec ecx
		229	jns .chip_ver_loop
		230	xor cl, cl ; default RTL8139
		231	.chip_ver_found:
		232	mov [hw_ver_id], cl
		233	; wake up the chip
		234	mov edx, [io_addr]
		235	add edx, RTL8139_REG_HLTCLK
		236	mov al, 'R' ; run the clock
		237	out dx, al
		238	; unlock config and BMCR registers
		239	add edx, RTL8139_REG_9346CR - RTL8139_REG_HLTCLK
		240	mov al, (1 shl RTL8139_BIT_93C46_EEM1) or (1 shl RTL8139_BIT_93C46_EEM0)
		241	out dx, al
		242	; enable power management
		243	add edx, RTL8139_REG_CONFIG1 - RTL8139_REG_9346CR
		244	in al, dx
		245	cmp byte [hw_ver_id], IDX_RTL8139B
		246	jl .old_chip
		247	; set LWAKE pin to active high (default value).
		248	; it is for Wake-On-LAN functionality of some motherboards.
		249	; this signal is used to inform the motherboard to execute a wake-up process.
		250	; only at newer chips.
		251	or al, (1 shl RTL8139_BIT_PMEn)
		252	and al, not (1 shl RTL8139_BIT_LWACT)
		253	out dx, al
		254	add edx, RTL8139_REG_CONFIG4 - RTL8139_REG_CONFIG1
		255	in al, dx
		256	and al, not (1 shl RTL8139_BIT_LWPTN)
		257	out dx, al
		258	jmp .finish_wake_up
		259	.old_chip:
		260	; wake up older chips
		261	and al, not ((1 shl RTL8139_BIT_SLEEP) or (1 shl RTL8139_BIT_PWRDWN))
		262	out dx, al
		263	.finish_wake_up:
		264	; lock config and BMCR registers
		265	xor al, al
		266	mov edx, [io_addr]
		267	add edx, RTL8139_REG_9346CR
		268	out dx, al
		269	;***************************************************************************
		270	; Function
		271	; rt8139_reset
		272	; Description
		273	; Place the chip (ie, the ethernet card) into a virgin state
		274	; Destroyed registers
		275	; eax, ebx, ecx, edx
		276	;
		277	;***************************************************************************
		278	rtl8139_reset:
		279	mov edx, [io_addr]
		280	add edx, RTL8139_REG_COMMAND
		281	mov al, 1 shl RTL8139_BIT_RST
		282	out dx, al
		283	mov cx, 1000 ; wait no longer for the reset
		284	.wait_for_reset:
		285	in al, dx
		286	test al, 1 shl RTL8139_BIT_RST
		287	jz .reset_completed ; RST remains 1 during reset
		288	dec cx
		289	jns .wait_for_reset
		290	.reset_completed:
		291	; get MAC (hardware address)
		292	mov ecx, 2
		293	.mac_read_loop:
		294	lea eax, [EE_93C46_REG_ETH_ID+ecx]
		295	push ecx
		296	call rtl8139_read_eeprom
		297	pop ecx
		298	mov [node_addr+ecx*2], ax
		299	dec ecx
		300	jns .mac_read_loop
		301	; unlock config and BMCR registers
		302	mov edx, [io_addr]
		303	add edx, RTL8139_REG_9346CR
		304	mov al, (1 shl RTL8139_BIT_93C46_EEM1) or (1 shl RTL8139_BIT_93C46_EEM0)
		305	out dx, al
		306	; initialize multicast registers (no filtering)
		307	mov eax, 0xffffffff
		308	add edx, RTL8139_REG_MAR0 - RTL8139_REG_9346CR
		309	out dx, eax
		310	add edx, RTL8139_REG_MAR4 - RTL8139_REG_MAR0
		311	out dx, eax
		312	; enable Rx/Tx
		313	mov al, (1 shl RTL8139_BIT_RE) or (1 shl RTL8139_BIT_TE)
		314	add edx, RTL8139_REG_COMMAND - RTL8139_REG_MAR4
		315	out dx, al
		316	; 32k Rxbuffer, unlimited dma burst, no wrapping, no rx threshold
		317	; accept broadcast packets, accept physical match packets
		318	mov ax, RTL8139_RX_CONFIG
		319	add edx, RTL8139_REG_RXCONFIG - RTL8139_REG_COMMAND
		320	out dx, ax
		321	; 1024 bytes DMA burst, total retries = 16 + 8 * 16 = 144
		322	mov ax, (RTL8139_TX_MXDMA shl RTL8139_BIT_TX_MXDMA) \
		323	or (RTL8139_TXRR shl RTL8139_BIT_TXRR)
		324	add edx, RTL8139_REG_TXCONFIG - RTL8139_REG_RXCONFIG
		325	out dx, ax
		326	; enable auto negotiation
		327	add edx, RTL8139_REG_BMCR - RTL8139_REG_TXCONFIG
		328	in ax, dx
		329	or ax, (1 shl RTL8139_BIT_ANE)
		330	out dx, ax
		331	; set auto negotiation advertisement
		332	add edx, RTL8139_REG_ANAR - RTL8139_REG_BMCR
		333	in ax, dx
		334	or ax, (1 shl RTL8139_BIT_SELECTOR) or (1 shl RTL8139_BIT_10) \
		335	or (1 shl RTL8139_BIT_10FD) or (1 shl RTL8139_BIT_TX) \
		336	or (1 shl RTL8139_BIT_TXFD)
		337	out dx, ax
		338	; lock config and BMCR registers
		339	xor eax, eax
		340	add edx, RTL8139_REG_9346CR - RTL8139_REG_ANAR
		341	out dx, al
		342	; init RX/TX pointers
		343	mov [rtl8139_rx_buff_offset], eax
		344	mov [curr_tx_desc], eax
		345	; clear missing packet counter
		346	add edx, RTL8139_REG_MPC - RTL8139_REG_9346CR
		347	out dx, eax
		348	; disable all interrupts
		349	add edx, RTL8139_REG_IMR - RTL8139_REG_MPC
		350	out dx, ax
		351	; set RxBuffer address, init RX buffer offset, init TX ring
		352	mov eax, rtl8139_rx_buff
		353	add edx, RTL8139_REG_RBSTART - RTL8139_REG_IMR
		354	out dx, eax
		355	; Indicate that we have successfully reset the card
		356	mov eax, [pci_data]
		357	mov [eth_status], eax
		358	ret
		359
		360	;***************************************************************************
		361	; Function
		362	; rtl8139_read_eeprom
		363	; Description
		364	; reads eeprom type 93c46 and 93c56
		365	; Parameters
		366	; al - word to be read (6bit in case of 93c46 and 8bit otherwise)
		367	; Return value
		368	; ax - word read in
		369	; Destroyed register(s)
		370	; eax, cx, ebx, edx
		371	;
		372	;***************************************************************************
		373	rtl8139_read_eeprom:
		374	movzx ebx, al
		375	mov edx, [io_addr]
		376	add edx, RTL8139_REG_RXCONFIG
		377	in al, dx
		378	test al, (1 shl RTL8139_BIT_9356SEL)
		379	jz .type_93c46
		380	; and bl, 01111111b ; don't care first bit
		381	or bx, EE_93C56_READ_CMD ; it contains start bit
		382	mov cx, EE_93C56_CMD_LENGTH-1 ; cmd_loop counter
		383	jmp .read_eeprom
		384	.type_93c46:
		385	and bl, 00111111b
		386	or bx, EE_93C46_READ_CMD ; it contains start bit
		387	mov cx, EE_93C46_CMD_LENGTH-1 ; cmd_loop counter
		388	.read_eeprom:
		389	add edx, RTL8139_REG_9346CR - RTL8139_REG_RXCONFIG_0
		390	; mov al, (1 shl RTL8139_BIT_93C46_EEM1)
		391	; out dx, al
		392	mov al, (1 shl RTL8139_BIT_93C46_EEM1) \
		393	or (1 shl RTL8139_BIT_93C46_EECS) ; wake up the eeprom
		394	out dx, al
		395	.cmd_loop:
		396	mov al, (1 shl RTL8139_BIT_93C46_EEM1) or (1 shl RTL8139_BIT_93C46_EECS)
		397	bt bx, cx
		398	jnc .zero_bit
		399	or al, (1 shl RTL8139_BIT_93C46_EEDI)
		400	.zero_bit:
		401	out dx, al
		402	; push eax
		403	; in eax, dx ; eeprom delay
		404	; pop eax
		405	or al, (1 shl RTL8139_BIT_93C46_EESK)
		406	out dx, al
		407	; in eax, dx ; eeprom delay
		408	dec cx
		409	jns .cmd_loop
		410	; in eax, dx ; eeprom delay
		411	mov al, (1 shl RTL8139_BIT_93C46_EEM1) or (1 shl RTL8139_BIT_93C46_EECS)
		412	out dx, al
		413	mov cl, 0xf
		414	.read_loop:
		415	shl ebx, 1
		416	mov al, (1 shl RTL8139_BIT_93C46_EEM1) \
		417	or (1 shl RTL8139_BIT_93C46_EECS) \
		418	or (1 shl RTL8139_BIT_93C46_EESK)
		419	out dx, al
		420	; in eax, dx ; eeprom delay
		421	in al, dx
		422	and al, (1 shl RTL8139_BIT_93C46_EEDO)
		423	jz .dont_set
		424	inc ebx
		425	.dont_set:
		426	mov al, (1 shl RTL8139_BIT_93C46_EEM1) \
		427	or (1 shl RTL8139_BIT_93C46_EECS)
		428	out dx, al
		429	; in eax, dx ; eeprom delay
		430	dec cl
		431	jns .read_loop
		432	xor al, al
		433	out dx, al
		434	mov ax, bx
		435	ret
		436
		437	;***************************************************************************
		438	; Function
		439	; rtl8139_transmit
		440	; Description
		441	; Transmits a packet of data via the ethernet card
		442	; Pointer to 48 bit destination address in edi
		443	; Type of packet in bx
		444	; size of packet in ecx
		445	; pointer to packet data in esi
		446	; Destroyed registers
		447	; eax, edx, esi, edi
		448	; ToDo
		449	; for waiting of timeout the rtl8139 internal timer
		450	; should be used
		451	;
		452	;***************************************************************************
		453	rtl8139_transmit:
		454	cmp ecx, MAX_ETH_FRAME_SIZE
		455	jg .finish ; packet is too long
		456	push ecx
		457	; check descriptor
		458	mov ecx, [curr_tx_desc]
		459	mov edx, [io_addr]
		460	lea edx, [edx+ecx*4+RTL8139_REG_TSD0]
		461	push edx ebx
		462	in ax, dx
		463	and ax, (1 shl RTL8139_BIT_TOK) or (1 shl RTL8139_BIT_OWN)
		464	cmp ax, (1 shl RTL8139_BIT_TOK) or (1 shl RTL8139_BIT_OWN)
		465	jz .send_packet
		466	test ax, 0x1fff ; or no size given
		467	jz .send_packet
		468	; wait for timeout
		469	mov ebx, RTL8139_TX_TIMEOUT
		470	mov eax, 0x5 ; delay x/100 secs
		471	int 0x40
		472	in ax, dx
		473	and ax, (1 shl RTL8139_BIT_TOK) or (1 shl RTL8139_BIT_OWN)
		474	cmp ax, (1 shl RTL8139_BIT_TOK) or (1 shl RTL8139_BIT_OWN)
		475	jz .send_packet
		476	; chip hung, reset it
		477	call rtl8139_reset
		478	; reset the card
		479	.send_packet:
		480	; calculate tx_buffer address
		481	pop ebx
		482	push esi
		483	mov eax, MAX_ETH_FRAME_SIZE
		484	mul dword [curr_tx_desc]
		485	mov esi, edi
		486	lea edi, [rtl8139_tx_buff+eax]
		487	mov eax, edi
		488	cld
		489	; copy destination address
		490	movsd
		491	movsw
		492	; copy source address
		493	mov esi, node_addr
		494	movsd
		495	movsw
		496	; copy packet type
		497	mov [edi], bx
		498	add edi, 2
		499	; copy the packet data
		500	pop esi edx ecx
		501	push ecx
		502	shr ecx, 2
		503	rep movsd
		504	pop ecx
		505	push ecx
		506	and ecx, 3
		507	rep movsb
		508	; set address
		509	add edx, RTL8139_REG_TSAD0 - RTL8139_REG_TSD0
		510	out dx, eax
		511	; set size and early threshold
		512	pop eax ; pick up the size
		513	add eax, ETH_HLEN
		514	cmp eax, ETH_ZLEN
		515	jnc .no_pad
		516	mov eax, ETH_ZLEN
		517	.no_pad:
		518	or eax, (RTL8139_ERTXTH shl RTL8139_BIT_ERTXTH)
		519	add edx, RTL8139_REG_TSD0 - RTL8139_REG_TSAD0
		520	out dx, eax
		521	; get next descriptor 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, ...
		522	inc dword [curr_tx_desc]
		523	and dword [curr_tx_desc], 3
		524	.finish:
		525	ret
		526
		527	;***************************************************************************
		528	; Function
		529	; rtl8139_poll
		530	;
		531	; Description
		532	; Polls the ethernet card for a received packet
		533	; Received data, if any, ends up in Ether_buffer
		534	; Destroyed register(s)
		535	; eax, edx, ecx
		536	;
		537	;***************************************************************************
		538	rtl8139_poll:
		539	mov word [eth_rx_data_len], 0
		540	mov edx, [io_addr]
		541	add edx, RTL8139_REG_COMMAND
		542	in al, dx
		543	test al, (1 shl RTL8139_BIT_BUFE)
		544	jnz .finish
		545	; new packet received copy it from rx_buffer into Ether_buffer
		546	mov eax, rtl8139_rx_buff
		547	add eax, [rtl8139_rx_buff_offset]
		548	; check if packet is ok
		549	test byte [eax], (1 shl RTL8139_BIT_ROK)
		550	jz .reset_rx
		551	; packet is ok copy it into the Ether_buffer
		552	movzx ecx, word [eax+2] ; packet length
		553	sub ecx, 4 ; don't copy CRC
		554	mov word [eth_rx_data_len], cx
		555	push ecx
		556	shr ecx, 2 ; first copy dword-wise
		557	lea esi, [eax+4] ; don't copy the packet header
		558	mov edi, Ether_buffer
		559	cld
		560	rep movsd ; copy the dwords
		561	pop ecx
		562	and ecx, 3
		563	rep movsb ; copy the rest bytes
		564	; update rtl8139_rx_buff_offset
		565	movzx eax, word [eax+2] ; packet length
		566	add eax, [rtl8139_rx_buff_offset]
		567	add eax, 4+3 ; packet header is 4 bytes long + dword alignment
		568	and eax, not 3 ; dword alignment
		569	cmp eax, RTL8139_RX_BUFFER_SIZE
		570	jl .no_wrap
		571	sub eax, RTL8139_RX_BUFFER_SIZE
		572	.no_wrap:
		573	mov [rtl8139_rx_buff_offset], eax
		574	; update CAPR register
		575	sub eax, 0x10 ; value 0x10 is a constant for CAPR
		576	add edx, RTL8139_REG_CAPR - RTL8139_REG_COMMAND
		577	out dx, ax
		578	.finish:
		579	; clear active interrupt sources
		580	mov edx, [io_addr]
		581	add edx, RTL8139_REG_ISR
		582	in ax, dx
		583	out dx, ax
		584	ret
		585	.reset_rx:
		586	in al, dx ; read command register
		587	push eax
		588	and al, not (1 shl RTL8139_BIT_RE)
		589	out dx, al
		590	pop eax
		591	out dx, al
		592	add edx, RTL8139_REG_RXCONFIG - RTL8139_REG_COMMAND
		593	mov ax, RTL8139_RX_CONFIG
		594	out dx, ax
		595	ret

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(root)/kernel/trunk/network/eth_drv/drivers/rtl8139.inc @ 1644 – Rev 261