WebSVN – Kolibri OS – Blame – /kernel/trunk/drivers/r500hw.inc

Rev	Author	Line No.	Line
729	serge	1	if 0
		2
		3	Copyright 2008 Serge
		4
		5	The below code is a rework from code in
		6	xf86-video-radeonhd/src/r5xx_accel.c, xf86-video-radeonhd/src/r5xx_xaa.c
		7
		8	Copyright 2008 Luc Verhaegen
		9	Copyright 2008 Matthias Hopf
		10	Copyright 2008 Egbert Eich
		11	Copyright 2008 Advanced Micro Devices, Inc.
		12
		13	Permission is hereby granted, free of charge, to any person obtaining a
		14	copy of this software and associated documentation files (the "Software"),
		15	to deal in the Software without restriction, including without limitation
		16	the rights to use, copy, modify, merge, publish, distribute, sublicense,
		17	and/or sell copies of the Software, and to permit persons to whom the
		18	Software is furnished to do so, subject to the following conditions:
		19
		20	The above copyright notice and this permission notice shall be included in
		21	all copies or substantial portions of the Software.
		22
		23	THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		24	IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		25	FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		26	THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		27	OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		28	ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		29	OTHER DEALINGS IN THE SOFTWARE.
		30
		31	The below code is a rework from code in xf86-video-ati/src/radeon_accel.c
		32	The original license is included below, it has the messed up disclaimer and
		33	an all rights reserved statement.
		34
		35
		36	Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
		37	VA Linux Systems Inc., Fremont, California.
		38
		39	All Rights Reserved.
		40
		41	Permission is hereby granted, free of charge, to any person obtaining
		42	a copy of this software and associated documentation files (the
		43	"Software"), to deal in the Software without restriction, including
		44	without limitation on the rights to use, copy, modify, merge,
		45	publish, distribute, sublicense, and/or sell copies of the Software,
		46	and to permit persons to whom the Software is furnished to do so,
		47	subject to the following conditions:
		48
		49	The above copyright notice and this permission notice (including the
		50	next paragraph) shall be included in all copies or substantial
		51	portions of the Software.
		52
		53	THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
		54	EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
		55	MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
		56	NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
		57	THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
		58	WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
		59	OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
		60	DEALINGS IN THE SOFTWARE.
		61
		62	Authors:
		63	Kevin E. Martin
		64	Rickard E. Faith
		65	Alan Hourihane
		66
		67	end if
		68
791	serge	69	RADEON_CP_ME_RAM_ADDR equ 0x07d4
		70	RADEON_CP_ME_RAM_RADDR equ 0x07d8
		71	RADEON_CP_ME_RAM_DATAH equ 0x07dc
		72	RADEON_CP_ME_RAM_DATAL equ 0x07e0
		73
		74	RADEON_CP_RB_BASE equ 0x0700
		75	RADEON_CP_RB_CNTL equ 0x0704
		76	RADEON_RB_NO_UPDATE equ (1 shl 27)
		77	RADEON_CP_RB_RPTR_ADDR equ 0x070c
		78	RADEON_CP_RB_RPTR equ 0x0710
		79	RADEON_CP_RB_WPTR equ 0x0714
		80
		81	RADEON_CP_CSQ_CNTL equ 0x0740
		82	RADEON_CSQ_CNT_PRIMARY_MASK equ (0xff shl 0)
		83	RADEON_CSQ_PRIDIS_INDDIS equ (0 shl 28)
		84	RADEON_CSQ_PRIPIO_INDDIS equ (1 shl 28)
		85	RADEON_CSQ_PRIBM_INDDIS equ (2 shl 28)
		86	RADEON_CSQ_PRIPIO_INDBM equ (3 shl 28)
		87	RADEON_CSQ_PRIBM_INDBM equ (4 shl 28)
		88	RADEON_CSQ_PRIPIO_INDPIO equ (15 shl 28)
		89
		90	RADEON_CP_RB_WPTR_DELAY equ 0x0718
		91
		92	RADEON_SCRATCH_UMSK equ 0x0770
		93	RADEON_SCRATCH_ADDR equ 0x0774
		94
		95	RADEON_ISYNC_CNTL equ 0x1724
		96	RADEON_ISYNC_ANY2D_IDLE3D equ (1 shl 0)
		97	RADEON_ISYNC_ANY3D_IDLE2D equ (1 shl 1)
		98	RADEON_ISYNC_TRIG2D_IDLE3D equ (1 shl 2)
		99	RADEON_ISYNC_TRIG3D_IDLE2D equ (1 shl 3)
		100	RADEON_ISYNC_WAIT_IDLEGUI equ (1 shl 4)
		101	RADEON_ISYNC_CPSCRATCH_IDLEGUI equ (1 shl 5)
		102
		103	RADEON_AIC_CNTL equ 0x01d0
		104	RADEON_PCIGART_TRANSLATE_EN equ (1 shl 0)
		105	RADEON_AIC_STAT equ 0x01d4
		106	RADEON_AIC_PT_BASE equ 0x01d8
		107	RADEON_AIC_LO_ADDR equ 0x01dc
		108	RADEON_AIC_HI_ADDR equ 0x01e0
		109	RADEON_AIC_TLB_ADDR equ 0x01e4
		110	RADEON_AIC_TLB_DATA equ 0x01e8
		111
		112	RADEON_WAIT_UNTIL equ 0x1720
		113	RADEON_WAIT_CRTC_PFLIP equ (1 shl 0)
		114	RADEON_WAIT_2D_IDLE equ (1 shl 14)
		115	RADEON_WAIT_3D_IDLE equ (1 shl 15)
		116	RADEON_WAIT_2D_IDLECLEAN equ (1 shl 16)
		117	RADEON_WAIT_3D_IDLECLEAN equ (1 shl 17)
		118	RADEON_WAIT_HOST_IDLECLEAN equ (1 shl 18)
		119
732	serge	120	D1GRPH_PITCH equ 0x6120
734	serge	121	D1GRPH_X_END equ 0x6134
		122	D1GRPH_Y_END equ 0x6138
729	serge	123
734	serge	124
729	serge	125	R5XX_DATATYPE_ARGB8888 equ 6
		126
		127	R5XX_RB3D_CNTL equ 0x1c3c
		128
		129	R5XX_RBBM_STATUS equ 0x0e40
		130	R5XX_RBBM_FIFOCNT_MASK equ 0x007f
		131	R5XX_RBBM_ACTIVE equ (1 shl 31)
		132
		133	R5XX_RBBM_SOFT_RESET equ 0x00f0
		134	R5XX_SOFT_RESET_CP equ (1 shl 0)
		135	R5XX_SOFT_RESET_HI equ (1 shl 1)
		136	R5XX_SOFT_RESET_SE equ (1 shl 2)
		137	R5XX_SOFT_RESET_RE equ (1 shl 3)
		138	R5XX_SOFT_RESET_PP equ (1 shl 4)
		139	R5XX_SOFT_RESET_E2 equ (1 shl 5)
		140	R5XX_SOFT_RESET_RB equ (1 shl 6)
		141	R5XX_SOFT_RESET_HDP equ (1 shl 7)
		142
		143	R5XX_SRC_PITCH_OFFSET equ 0x1428
		144	R5XX_DST_PITCH_OFFSET equ 0x142c
		145
		146	R5XX_DP_DATATYPE equ 0x16c4
		147	R5XX_HOST_BIG_ENDIAN_EN equ (1 shl 29)
		148
		149	R5XX_DP_CNTL equ 0x16c0
		150	R5XX_DST_X_LEFT_TO_RIGHT equ (1 shl 0)
		151	R5XX_DST_Y_TOP_TO_BOTTOM equ (1 shl 1)
		152	R5XX_DP_DST_TILE_LINEAR equ (0 shl 3)
		153	R5XX_DP_DST_TILE_MACRO equ (1 shl 3)
		154	R5XX_DP_DST_TILE_MICRO equ (2 shl 3)
		155	R5XX_DP_DST_TILE_BOTH equ (3 shl 3)
		156
791	serge	157	RADEON_RB3D_ZCACHE_CTLSTAT equ 0x3254
		158	RADEON_RB3D_ZC_FLUSH equ (1 shl 0)
		159	RADEON_RB3D_ZC_FREE equ (1 shl 2)
		160	RADEON_RB3D_ZC_FLUSH_ALL equ 0x5
		161	RADEON_RB3D_ZC_BUSY equ (1 shl 31)
729	serge	162
		163	R5XX_RB3D_DSTCACHE_CTLSTAT equ 0x325C
		164	R5XX_RB3D_DC_FLUSH equ (3 shl 0)
		165	R5XX_RB3D_DC_FREE equ (3 shl 2)
		166	R5XX_RB3D_DC_FLUSH_ALL equ 0xf
		167	R5XX_RB3D_DC_BUSY equ (1 shl 31)
		168
		169	R5XX_SURFACE_CNTL equ 0x0b00
		170	R5XX_SURF_TRANSLATION_DIS equ (1 shl 8)
		171	R5XX_NONSURF_AP0_SWP_16BPP equ (1 shl 20)
		172	R5XX_NONSURF_AP0_SWP_32BPP equ (1 shl 21)
		173	R5XX_NONSURF_AP1_SWP_16BPP equ (1 shl 22)
		174	R5XX_NONSURF_AP1_SWP_32BPP equ (1 shl 23)
		175
		176	R5XX_DEFAULT_SC_BOTTOM_RIGHT equ 0x16e8
		177	R5XX_DEFAULT_SC_RIGHT_MAX equ (0x1fff shl 0)
		178	R5XX_DEFAULT_SC_BOTTOM_MAX equ (0x1fff shl 16)
		179
		180	R5XX_SC_TOP_LEFT equ 0x16ec
		181	R5XX_SC_BOTTOM_RIGHT equ 0x16f0
		182	R5XX_SC_SIGN_MASK_LO equ 0x8000
		183	R5XX_SC_SIGN_MASK_HI equ 0x80000000
		184
		185	R5XX_DP_GUI_MASTER_CNTL equ 0x146c
		186	R5XX_GMC_SRC_PITCH_OFFSET_CNTL equ (1 shl 0)
		187	R5XX_GMC_DST_PITCH_OFFSET_CNTL equ (1 shl 1)
		188	R5XX_GMC_SRC_CLIPPING equ (1 shl 2)
		189	R5XX_GMC_DST_CLIPPING equ (1 shl 3)
		190	R5XX_GMC_BRUSH_DATATYPE_MASK equ (0x0f shl 4)
		191	R5XX_GMC_BRUSH_8X8_MONO_FG_BG equ (0 shl 4)
		192	R5XX_GMC_BRUSH_8X8_MONO_FG_LA equ (1 shl 4)
		193	R5XX_GMC_BRUSH_1X8_MONO_FG_BG equ (4 shl 4)
		194	R5XX_GMC_BRUSH_1X8_MONO_FG_LA equ (5 shl 4)
		195	R5XX_GMC_BRUSH_32x1_MONO_FG_BG equ (6 shl 4)
		196	R5XX_GMC_BRUSH_32x1_MONO_FG_LA equ (7 shl 4)
		197	R5XX_GMC_BRUSH_32x32_MONO_FG_BG equ (8 shl 4)
		198	R5XX_GMC_BRUSH_32x32_MONO_FG_LA equ (9 shl 4)
		199	R5XX_GMC_BRUSH_8x8_COLOR equ (10 shl 4)
		200	R5XX_GMC_BRUSH_1X8_COLOR equ (12 shl 4)
		201	R5XX_GMC_BRUSH_SOLID_COLOR equ (13 shl 4)
		202	R5XX_GMC_BRUSH_NONE equ (15 shl 4)
		203	R5XX_GMC_DST_8BPP_CI equ (2 shl 8)
		204	R5XX_GMC_DST_15BPP equ (3 shl 8)
		205	R5XX_GMC_DST_16BPP equ (4 shl 8)
		206	R5XX_GMC_DST_24BPP equ (5 shl 8)
		207	R5XX_GMC_DST_32BPP equ (6 shl 8)
		208	R5XX_GMC_DST_8BPP_RGB equ (7 shl 8)
		209	R5XX_GMC_DST_Y8 equ (8 shl 8)
		210	R5XX_GMC_DST_RGB8 equ (9 shl 8)
		211	R5XX_GMC_DST_VYUY equ (11 shl 8)
		212	R5XX_GMC_DST_YVYU equ (12 shl 8)
		213	R5XX_GMC_DST_AYUV444 equ (14 shl 8)
		214	R5XX_GMC_DST_ARGB4444 equ (15 shl 8)
		215	R5XX_GMC_DST_DATATYPE_MASK equ (0x0f shl 8)
		216	R5XX_GMC_DST_DATATYPE_SHIFT equ 8
		217	R5XX_GMC_SRC_DATATYPE_MASK equ (3 shl 12)
		218	R5XX_GMC_SRC_DATATYPE_MONO_FG_BG equ (0 shl 12)
		219	R5XX_GMC_SRC_DATATYPE_MONO_FG_LA equ (1 shl 12)
		220	R5XX_GMC_SRC_DATATYPE_COLOR equ (3 shl 12)
		221	R5XX_GMC_BYTE_PIX_ORDER equ (1 shl 14)
		222	R5XX_GMC_BYTE_MSB_TO_LSB equ (0 shl 14)
		223	R5XX_GMC_BYTE_LSB_TO_MSB equ (1 shl 14)
		224	R5XX_GMC_CONVERSION_TEMP equ (1 shl 15)
		225	R5XX_GMC_CONVERSION_TEMP_6500 equ (0 shl 15)
		226	R5XX_GMC_CONVERSION_TEMP_9300 equ (1 shl 15)
		227	R5XX_GMC_ROP3_MASK equ (0xff shl 16)
		228	R5XX_DP_SRC_SOURCE_MASK equ (7 shl 24)
		229	R5XX_DP_SRC_SOURCE_MEMORY equ (2 shl 24)
		230	R5XX_DP_SRC_SOURCE_HOST_DATA equ (3 shl 24)
		231	R5XX_GMC_3D_FCN_EN equ (1 shl 27)
		232	R5XX_GMC_CLR_CMP_CNTL_DIS equ (1 shl 28)
		233	R5XX_GMC_AUX_CLIP_DIS equ (1 shl 29)
		234	R5XX_GMC_WR_MSK_DIS equ (1 shl 30)
		235	R5XX_GMC_LD_BRUSH_Y_X equ (1 shl 31)
		236	R5XX_ROP3_ZERO equ 0x00000000
		237	R5XX_ROP3_DSa equ 0x00880000
		238	R5XX_ROP3_SDna equ 0x00440000
		239	R5XX_ROP3_S equ 0x00cc0000
		240	R5XX_ROP3_DSna equ 0x00220000
		241	R5XX_ROP3_D equ 0x00aa0000
		242	R5XX_ROP3_DSx equ 0x00660000
		243	R5XX_ROP3_DSo equ 0x00ee0000
		244	R5XX_ROP3_DSon equ 0x00110000
		245	R5XX_ROP3_DSxn equ 0x00990000
		246	R5XX_ROP3_Dn equ 0x00550000
		247	R5XX_ROP3_SDno equ 0x00dd0000
		248	R5XX_ROP3_Sn equ 0x00330000
		249	R5XX_ROP3_DSno equ 0x00bb0000
		250	R5XX_ROP3_DSan equ 0x00770000
		251	R5XX_ROP3_ONE equ 0x00ff0000
		252	R5XX_ROP3_DPa equ 0x00a00000
		253	R5XX_ROP3_PDna equ 0x00500000
		254	R5XX_ROP3_P equ 0x00f00000
		255	R5XX_ROP3_DPna equ 0x000a0000
		256	R5XX_ROP3_D equ 0x00aa0000
		257	R5XX_ROP3_DPx equ 0x005a0000
		258	R5XX_ROP3_DPo equ 0x00fa0000
		259	R5XX_ROP3_DPon equ 0x00050000
		260	R5XX_ROP3_PDxn equ 0x00a50000
		261	R5XX_ROP3_PDno equ 0x00f50000
		262	R5XX_ROP3_Pn equ 0x000f0000
		263	R5XX_ROP3_DPno equ 0x00af0000
		264	R5XX_ROP3_DPan equ 0x005f0000
		265
		266	R5XX_HOST_PATH_CNTL equ 0x0130
		267	R5XX_HDP_SOFT_RESET equ (1 shl 26)
		268	R5XX_HDP_APER_CNTL equ (1 shl 23)
		269
		270	R5XX_RB3D_DSTCACHE_MODE equ 0x3258
		271	R5XX_RB3D_DC_CACHE_ENABLE equ (0)
		272	R5XX_RB3D_DC_2D_CACHE_DISABLE equ (1)
		273	R5XX_RB3D_DC_3D_CACHE_DISABLE equ (2)
		274	R5XX_RB3D_DC_CACHE_DISABLE equ (3)
		275	R5XX_RB3D_DC_2D_CACHE_LINESIZE_128 equ (1 shl 2)
		276	R5XX_RB3D_DC_3D_CACHE_LINESIZE_128 equ (2 shl 2)
		277	R5XX_RB3D_DC_2D_CACHE_AUTOFLUSH equ (1 shl 8)
		278	R5XX_RB3D_DC_3D_CACHE_AUTOFLUSH equ (2 shl 8)
		279	R200_RB3D_DC_2D_CACHE_AUTOFREE equ (1 shl 10)
		280	R200_RB3D_DC_3D_CACHE_AUTOFREE equ (2 shl 10)
		281	R5XX_RB3D_DC_FORCE_RMW equ (1 shl 16)
		282	R5XX_RB3D_DC_DISABLE_RI_FILL equ (1 shl 24)
		283	R5XX_RB3D_DC_DISABLE_RI_READ equ (1 shl 25)
		284
		285	R5XX_BRUSH_Y_X equ 0x1474
		286	R5XX_DP_BRUSH_BKGD_CLR equ 0x1478
		287	R5XX_DP_BRUSH_FRGD_CLR equ 0x147c
		288	R5XX_BRUSH_DATA0 equ 0x1480
		289	R5XX_BRUSH_DATA1 equ 0x1484
		290
732	serge	291	R5XX_SRC_Y_X equ 0x1434
		292
		293	R5XX_DST_Y_X equ 0x1438
		294	R5XX_DST_HEIGHT_WIDTH equ 0x143c
729	serge	295	R5XX_DST_WIDTH_HEIGHT equ 0x1598
		296
732	serge	297	R5XX_DST_LINE_START equ 0x1600
		298	R5XX_DST_LINE_END equ 0x1604
		299	R5XX_DST_LINE_PATCOUNT equ 0x1608
		300	R5XX_BRES_CNTL_SHIFT equ 8
		301
		302
729	serge	303	R5XX_DP_SRC_BKGD_CLR equ 0x15dc
		304	R5XX_DP_SRC_FRGD_CLR equ 0x15d8
		305
		306	R5XX_DP_WRITE_MASK equ 0x16cc
		307
791	serge	308
		309	RADEON_CP_PACKET0 equ 0x00000000
		310
729	serge	311	struc RHD
		312	{
		313	.control rd 1
		314	.control_saved rd 1
		315	.datatype rd 1
		316	.surface_cntl rd 1
		317	.dst_pitch_offset rd 1
791	serge	318	.ring_base rd 1
		319	.ring_rp rd 1
		320	.ring_wp rd 1
729	serge	321	};
		322
		323	R5XX_LOOP_COUNT equ 2000000
		324
791	serge	325
		326
729	serge	327	align 4
		328	R5xxFIFOWaitLocal:
		329
		330	mov ecx, R5XX_LOOP_COUNT
		331	@@:
		332	rdr ebx, R5XX_RBBM_STATUS
		333	and ebx, R5XX_RBBM_FIFOCNT_MASK
		334
		335	cmp eax, ebx
		336	jbe .done
		337	loop @B
		338
		339	mov esi, msgR5xxFIFOWaitLocaltimeout
		340	call SysMsgBoardStr
		341	xor eax, eax
		342	ret
		343	.done:
		344	mov eax, 1
		345	ret
		346
		347	align 4
		348	R5xxFIFOWait:
		349	call R5xxFIFOWaitLocal
		350	test eax, eax
		351	jz .reset
		352
		353	ret
		354	.reset:
		355	call R5xx2DReset
		356	call R5xx2DSetup
		357
		358	ret
		359
		360
		361	; Wait for the graphics engine to be completely idle: the FIFO has
		362	; drained, the Pixel Cache is flushed, and the engine is idle. This is
		363	; a standard "sync" function that will make the hardware "quiescent".
		364
		365	align 4
		366	R5xx2DIdleLocal:
		367
		368	mov ecx, R5XX_LOOP_COUNT
		369	@@:
		370	rdr eax, R5XX_RBBM_STATUS
		371	and eax, R5XX_RBBM_FIFOCNT_MASK
		372	cmp eax, 0x40
		373	je @F
		374	loop @B
		375
		376	mov esi, msgR5xx2DIdleLocaltimeout
		377	call SysMsgBoardStr
		378	xor eax, eax
		379	ret
		380	@@:
		381	mov ecx, R5XX_LOOP_COUNT
		382	@@:
		383	rdr eax, R5XX_RBBM_STATUS
		384	test eax, R5XX_RBBM_ACTIVE
		385	jz .done
		386	loop @B
		387
		388	mov esi, msgR5xx2DIdleLocaltimeout
		389	call SysMsgBoardStr
		390	xor eax, eax
		391	ret
		392	.done:
		393	call R5xx2DFlush
		394	ret
		395
		396	align 4
		397	R5xx2DFlush:
		398	rmask R5XX_RB3D_DSTCACHE_CTLSTAT, R5XX_RB3D_DC_FLUSH_ALL, R5XX_RB3D_DC_FLUSH_ALL
		399
		400	mov ecx, R5XX_LOOP_COUNT
		401	@@:
		402	rdr eax, R5XX_RB3D_DSTCACHE_CTLSTAT
		403	test eax, R5XX_RB3D_DC_BUSY
		404	jz .done
		405	loop @B
		406	.fail:
		407	mov esi, msgR5xx2DFlushtimeout
		408	call SysMsgBoardStr
		409	xor eax, eax
		410	ret
		411	.done:
		412	mov eax, 1
		413	ret
		414
		415	align 4
		416	proc R5xx2DReset
		417	locals
		418	save rd 1
		419	tmp rd 1
		420	endl
		421
		422	; The following RBBM_SOFT_RESET sequence can help un-wedge
		423	; an R300 after the command processor got stuck.
		424
		425	rdr eax, R5XX_RBBM_SOFT_RESET
		426	mov [save], eax
		427
		428	or eax, R5XX_SOFT_RESET_CP or \
		429	R5XX_SOFT_RESET_HI or R5XX_SOFT_RESET_SE or \
		430	R5XX_SOFT_RESET_RE or R5XX_SOFT_RESET_PP or \
		431	R5XX_SOFT_RESET_E2 or R5XX_SOFT_RESET_RB
		432	mov [tmp], eax
		433
		434	wrr R5XX_RBBM_SOFT_RESET, eax
		435
		436	rdr ebx, R5XX_RBBM_SOFT_RESET
		437	and eax, not (R5XX_SOFT_RESET_CP or R5XX_SOFT_RESET_HI or \
		438	R5XX_SOFT_RESET_SE or R5XX_SOFT_RESET_RE or \
		439	R5XX_SOFT_RESET_PP or R5XX_SOFT_RESET_E2 or \
		440	R5XX_SOFT_RESET_RB)
		441	wrr R5XX_RBBM_SOFT_RESET, eax
		442	rdr ebx, R5XX_RBBM_SOFT_RESET
		443	mov eax, [save]
		444	wrr R5XX_RBBM_SOFT_RESET, eax
		445	rdr ebx, R5XX_RBBM_SOFT_RESET
		446	call R5xx2DFlush
		447
		448	; Soft resetting HDP thru RBBM_SOFT_RESET register can cause some
		449	; unexpected behaviour on some machines. Here we use
		450	; R5XX_HOST_PATH_CNTL to reset it.
		451
		452	rdr edx, R5XX_HOST_PATH_CNTL
		453
		454	rdr ebx, R5XX_RBBM_SOFT_RESET
		455
		456	or ebx, R5XX_SOFT_RESET_CP or R5XX_SOFT_RESET_HI or R5XX_SOFT_RESET_E2
		457
		458	wrr R5XX_RBBM_SOFT_RESET, ebx
		459
		460	rdr eax, R5XX_RBBM_SOFT_RESET
		461
		462	wrr R5XX_RBBM_SOFT_RESET, 0
		463
		464	rdr ebx, R5XX_RB3D_DSTCACHE_MODE
		465
		466	or ebx, (1 shl 17)
		467	wrr R5XX_RB3D_DSTCACHE_MODE, ebx
		468
		469	lea eax, [edx+R5XX_HDP_SOFT_RESET]
		470	wrr R5XX_HOST_PATH_CNTL, eax
		471
		472	rdr ebx, R5XX_HOST_PATH_CNTL
		473
		474	wrr R5XX_HOST_PATH_CNTL, edx
		475
		476	ret
		477	endp
		478
		479	align 4
		480	R5xx2DSetup:
		481
		482	; Setup engine location. This shouldn't be necessary since we
		483	; set them appropriately before any accel ops, but let's avoid
		484	; random bogus DMA in case we inadvertently trigger the engine
		485	; in the wrong place (happened).
		486
		487	mov eax, 2
		488	call R5xxFIFOWaitLocal
		489
		490	mov eax, [rhd.dst_pitch_offset]
		491	wrr R5XX_DST_PITCH_OFFSET, eax
		492
		493	wrr R5XX_SRC_PITCH_OFFSET, eax
		494
		495	mov eax, 1
		496	call R5xxFIFOWaitLocal
		497
		498	rmask R5XX_DP_DATATYPE, 0, R5XX_HOST_BIG_ENDIAN_EN
		499
		500	mov eax, [rhd.surface_cntl]
		501	wrr R5XX_SURFACE_CNTL, eax
		502
		503	mov eax, 1
		504	call R5xxFIFOWaitLocal
		505
		506	wrr R5XX_DEFAULT_SC_BOTTOM_RIGHT,\
		507	(R5XX_DEFAULT_SC_RIGHT_MAX or R5XX_DEFAULT_SC_BOTTOM_MAX)
		508
		509	mov eax, 1
		510	call R5xxFIFOWaitLocal
		511
		512	mov eax, [rhd.control]
		513	or eax, (R5XX_GMC_BRUSH_SOLID_COLOR or R5XX_GMC_SRC_DATATYPE_COLOR)
		514	wrr R5XX_DP_GUI_MASTER_CNTL, eax
		515
		516	mov eax, 5
		517	call R5xxFIFOWaitLocal
		518
		519	wrr R5XX_DP_BRUSH_FRGD_CLR, 0xFFFFFFFF
		520
		521	wrr R5XX_DP_BRUSH_BKGD_CLR, 0x00000000
		522
		523	wrr R5XX_DP_SRC_FRGD_CLR, 0xFFFFFFFF
		524	wrr R5XX_DP_SRC_BKGD_CLR, 0x00000000
		525	wrr R5XX_DP_WRITE_MASK, 0xFFFFFFFF
		526
		527	call R5xx2DIdleLocal
		528	ret
		529
		530	align 4
		531	R5xx2DPreInit:
		532
734	serge	533	mov [rhd.control],\
		534	(R5XX_DATATYPE_ARGB8888 shl R5XX_GMC_DST_DATATYPE_SHIFT) or\
		535	R5XX_GMC_CLR_CMP_CNTL_DIS or R5XX_GMC_DST_PITCH_OFFSET_CNTL
729	serge	536
		537	mov [rhd.datatype], R5XX_DATATYPE_ARGB8888
		538	mov [rhd.surface_cntl],0
		539
732	serge	540	rdr eax, D1GRPH_PITCH
		541	shl eax, 18
		542
		543	mov ebx, [r500_LFB]
		544	shr ebx, 10
		545	or eax, ebx
		546
729	serge	547	mov [rhd.dst_pitch_offset], eax
		548
		549	ret
		550
791	serge	551	RADEON_BUS_CNTL equ 0x0030
		552	RADEON_BUS_MASTER_DIS equ (1 shl 6)
		553
729	serge	554	align 4
791	serge	555	R5xxCpInit:
		556	stdcall CreateRingBuffer, 0x8000, PG_SW+PG_NOCACHE
		557	test eax, eax
		558	jz .fail
		559
		560	mov [rhd.ring_base], eax
		561	call GetPgAddr
		562
		563	wrr RADEON_CP_RB_BASE, eax
		564
		565	wrr RADEON_CP_RB_WPTR_DELAY, 0
		566
		567	rdr ebx, RADEON_CP_RB_RPTR
		568	wrr RADEON_CP_RB_WPTR, ebx
		569
		570	mov [rhd.ring_rp], ebx
		571	mov [rhd.ring_wp], ebx
		572
		573	wrr RADEON_CP_RB_RPTR_ADDR, 0 ;ring buffer read pointer
		574	;no update
		575
		576	wrr RADEON_CP_RB_CNTL, RADEON_RB_NO_UPDATE + 12
		577	wrr RADEON_SCRATCH_UMSK, 0 ;no scratch update
		578
		579	rdr ebx, RADEON_BUS_CNTL
		580	and ebx, not RADEON_BUS_MASTER_DIS
		581
		582	wrr RADEON_BUS_CNTL, ebx
		583
		584	; wrr RADEON_LAST_FRAME_REG, 0
		585	; wrr RADEON_LAST_DISPATCH_REG, 0
		586	; wrr RADEON_LAST_CLEAR_REG, 0
		587
		588	call R5xx2DIdleLocal
		589
		590	wrr RADEON_ISYNC_CNTL, RADEON_ISYNC_ANY2D_IDLE3D + \
		591	RADEON_ISYNC_ANY3D_IDLE2D + \
		592	RADEON_ISYNC_WAIT_IDLEGUI + \
		593	RADEON_ISYNC_CPSCRATCH_IDLEGUI
		594	.fail:
		595	ret
		596
		597	align 4
		598	load_microcode:
		599
		600	pushfd
		601	cli
		602
		603	call R5xx2DIdleLocal
		604
		605	wrr RADEON_CP_ME_RAM_ADDR, 0
		606
		607	lea esi, [R520_cp_microcode]
		608	mov ecx, 256
		609	@@:
		610	mov eax, [esi]
		611	mov ebx, [esi+4]
		612	wrr RADEON_CP_ME_RAM_DATAH, ebx
		613	wrr RADEON_CP_ME_RAM_DATAL, eax
		614	add esi, 8
		615	loop @B
		616
		617	popfd
		618	ret
		619
		620
		621	align 4
729	serge	622	R5xx2DInit:
		623
		624	call R5xx2DPreInit
		625	wrr R5XX_RB3D_CNTL, 0
791	serge	626
729	serge	627	call R5xx2DReset
		628	call R5xx2DSetup
734	serge	629
791	serge	630	rdr eax, RADEON_AIC_CNTL ;disable GART
		631	and eax, not RADEON_PCIGART_TRANSLATE_EN
		632	wrr RADEON_AIC_CNTL, eax
		633
		634	call load_microcode
		635
		636	call R5xxCpInit
		637
734	serge	638	rdr eax, D1GRPH_X_END
		639	rdr ebx, D1GRPH_Y_END
		640	dec eax
		641	dec ebx
		642
		643	mov [__xmin], 0 ;set clip
		644	mov [__ymin], 0
		645	mov [__xmax], eax
		646	mov [__ymax], ebx
		647
791	serge	648	wrr RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM
		649
		650	; BEGIN_RING
		651	; RADEON_PURGE_CACHE
		652	; RADEON_PURGE_ZCACHE
		653	; RADEON_WAIT_UNTIL_IDLE
		654	; COMMIT_RING
		655
729	serge	656	ret
		657
		658	proc R5xxSetupForSolidFill stdcall,color:dword, rop:dword, planemask:dword
		659
		660	mov edx, [rop]
		661	mov edx, [R5xxRops+4+edx*8]
		662	or edx, [rhd.control]
		663	or edx, (R5XX_GMC_BRUSH_SOLID_COLOR or R5XX_GMC_SRC_DATATYPE_COLOR)
		664
		665	; Save for later clipping */
		666	mov [rhd.control_saved], edx
		667
		668	mov eax, 4
		669	call R5xxFIFOWait
		670
		671	wrr R5XX_DP_GUI_MASTER_CNTL, edx
		672
		673	mov eax, [color]
		674	wrr R5XX_DP_BRUSH_FRGD_CLR, eax
		675
		676	mov ebx, [planemask]
		677	wrr R5XX_DP_WRITE_MASK, ebx
		678
		679	wrr R5XX_DP_CNTL, (R5XX_DST_X_LEFT_TO_RIGHT or R5XX_DST_Y_TOP_TO_BOTTOM)
		680
		681	ret
		682	endp
		683
		684	align 4
		685	proc R5xxSolidFillRect stdcall, x:dword, y:dword, w:dword, h:dword
		686
		687	mov eax, 3
		688	call R5xxFIFOWait
		689
		690	mov eax, [rhd.dst_pitch_offset]
		691	wrr R5XX_DST_PITCH_OFFSET, eax
		692
		693	mov ebx, [y]
		694	shl ebx, 16
		695	mov bx, word [x]
		696	wrr R5XX_DST_Y_X, ebx
		697
		698	mov ecx, [w]
		699	shl ecx, 16
		700	mov cx, word [h]
		701	wrr R5XX_DST_WIDTH_HEIGHT, ecx
		702
		703	ret
		704	endp
		705
732	serge	706	handle equ IOCTL.handle
		707	io_code equ IOCTL.io_code
		708	input equ IOCTL.input
		709	inp_size equ IOCTL.inp_size
		710	output equ IOCTL.output
		711	out_size equ IOCTL.out_size
729	serge	712
732	serge	713	SRV_GETVERSION equ 0
		714	SOLID_FILL equ 1
		715	LINE_2P equ 2
		716
		717	align 4
		718	proc r500_entry stdcall, state:dword
		719
		720	.close:
		721	; call r500_close
		722
		723	xor eax, eax
		724	ret
		725	endp
		726
736	serge	727	CURRENT_TASK equ (OS_BASE+0x0003000)
		728	TASK_COUNT equ (OS_BASE+0x0003004)
		729	WIN_STACK equ (OS_BASE+0x000C000)
		730
		731
732	serge	732	align 4
		733	proc r500_HDraw stdcall, ioctl:dword
		734
		735	mov ebx, [ioctl]
		736	mov eax, [ebx+io_code]
		737	cmp eax, LINE_2P
		738	ja .fail
		739
		740	cmp eax, SRV_GETVERSION
		741	jne @F
		742
		743	mov eax, [ebx+output]
		744	cmp [ebx+out_size], 4
		745	jne .fail
		746	mov [eax], dword API_VERSION
		747	xor eax, eax
		748	ret
		749	@@:
736	serge	750	mov edx, [CURRENT_TASK]
		751	movzx edx, word [WIN_STACK+edx*2]
		752	cmp edx, [TASK_COUNT]
		753	jne .skip ;skip if window inactive
		754
732	serge	755	cmp eax, SOLID_FILL
		756	jne @F
		757
		758	cmp [ebx+inp_size], 5
		759	jne .fail
		760
		761	mov esi, [ebx+input]
		762	call solid_fill
736	serge	763	.skip:
732	serge	764	xor eax, eax
		765	ret
		766	@@:
		767	cmp eax, LINE_2P
		768	jne @F
		769
		770	cmp [ebx+inp_size], 5
		771	jne .fail
		772
		773	mov esi, [ebx+input]
		774	call solid_line
		775	xor eax, eax
		776	ret
		777	@@:
		778
		779	.fail:
		780	or eax, -1
		781	ret
		782	endp
		783
		784	restore handle
		785	restore io_code
		786	restore input
		787	restore inp_size
		788	restore output
		789	restore out_size
		790
		791	struc FILL
		792	{
		793	.color rd 1
		794	.x rd 1
		795	.y rd 1
		796	.w rd 1
		797	.h rd 1
		798	}
		799
		800	virtual at 0
		801	FILL FILL
		802	end virtual
		803
		804	struc LINE2P
		805	{
		806	.color rd 1
		807	.x1 rd 1
		808	.y1 rd 1
		809	.x2 rd 1
		810	.y2 rd 1
		811	}
		812
		813	virtual at 0
		814	LINE2P LINE2P
		815	end virtual
		816
		817	GXcopy equ 3
		818
791	serge	819	RADEON_CP_PACKET3 equ 0xC0000000
		820
		821	PAINT_MULTI equ 0xC0009A00
		822
		823	DST_PITCH_OFFSET_CNTL equ ( 1 shl 1)
		824	BRUSH_SOLID_COLOR equ ( 13 shl 4)
		825	COLOR_ARGB equ ( 6 shl 8)
		826	SRC_DATATYPE_COLOR equ ( 3 shl 12)
		827
		828	;RADEON_ROP3_P equ
		829
732	serge	830	; esi= input params
		831	align 4
		832	solid_fill:
		833
734	serge	834	mov ebx, [esi+FILL.x]
		835	mov ecx, [esi+FILL.y]
		836	mov eax, [esi+FILL.w]
		837	mov edx, [esi+FILL.h]
		838
		839	lea eax, [eax+ebx-1] ;x2
		840	lea edx, [edx+ecx-1] ;y2
		841
		842	push edx ;y2
		843	push eax ;x2
		844
		845	mov eax, esp ;&x2
		846	lea ebx, [esp+4] ;&y2
		847
		848	lea ecx, [esi+FILL.x]
		849	lea edx, [esi+FILL.y]
		850
		851	push ebx ;&y2
		852	push eax ;&x2
		853	push edx ;&y1
		854	push ecx ;&x1
		855
		856	call _BlockClip
		857	add esp, 16
		858	test eax, eax
		859	jnz .exit
		860
791	serge	861	;mov edx, [R5xxRops+4+GXcopy*8]
		862	;or edx, [rhd.control]
		863	;or edx, (R5XX_GMC_BRUSH_SOLID_COLOR or R5XX_GMC_SRC_DATATYPE_COLOR)
732	serge	864
736	serge	865	pushfd
		866	cli
		867
732	serge	868
791	serge	869	BEGIN_RING
		870	OUT_PACKET3 PAINT_MULTI, 4
		871	OUT_RING (DST_PITCH_OFFSET_CNTL + \
		872	BRUSH_SOLID_COLOR + \
		873	COLOR_ARGB + \
		874	SRC_DATATYPE_COLOR + \
		875	(1 shl 28)+(1 shl 30) + \
		876	R5XX_ROP3_P)
732	serge	877
791	serge	878	OUT_RING [rhd.dst_pitch_offset]
		879	OUT_RING [esi+FILL.color]
732	serge	880
		881	mov ebx, [esi+FILL.y]
		882	shl ebx, 16
		883	mov bx, word [esi+FILL.x]
791	serge	884	OUT_RING ebx
732	serge	885
736	serge	886	mov ecx, [esp+4] ;x2
734	serge	887	sub ecx, [esi+FILL.x]
		888	inc ecx ;w
		889
736	serge	890	mov eax, [esp+8] ;y2
734	serge	891	sub eax, [esi+FILL.y]
		892	inc eax ;h
		893
732	serge	894	shl ecx, 16
791	serge	895	mov cx, ax ;w\|h
		896
		897	OUT_RING ecx
		898	COMMIT_RING
		899
		900	if 0
		901	; mov eax, 7
		902	; call R5xxFIFOWait
		903
		904	; wrr R5XX_DP_GUI_MASTER_CNTL, edx
		905
		906	; mov eax, [esi+FILL.color]
		907	; wrr R5XX_DP_BRUSH_FRGD_CLR, eax
		908
		909	; wrr R5XX_DP_WRITE_MASK, 0xFFFFFFFF
		910
		911	; wrr R5XX_DP_CNTL, (R5XX_DST_X_LEFT_TO_RIGHT or R5XX_DST_Y_TOP_TO_BOTTOM)
		912
		913	; mov eax, [rhd.dst_pitch_offset]
		914	; wrr R5XX_DST_PITCH_OFFSET, eax
		915
		916	; mov ebx, [esi+FILL.y]
		917	; shl ebx, 16
		918	; mov bx, word [esi+FILL.x]
		919	; wrr R5XX_DST_Y_X, ebx
		920
		921	; mov ecx, [esp+4] ;x2
		922	; sub ecx, [esi+FILL.x]
		923	; inc ecx ;w
		924
		925	; mov eax, [esp+8] ;y2
		926	; sub eax, [esi+FILL.y]
		927	; inc eax ;h
		928
		929	; shl ecx, 16
		930	; mov cx, ax ;w\|h
		931	; wrr R5XX_DST_WIDTH_HEIGHT, ecx
		932	end if
736	serge	933	popfd
734	serge	934	.exit:
		935	add esp, 8
732	serge	936	ret
		937
		938	align 4
		939	solid_line:
		940
734	serge	941	lea eax, [esi+LINE2P.y2]
		942	lea ebx, [esi+LINE2P.x2]
		943	lea ecx, [esi+LINE2P.y1]
		944	lea edx, [esi+LINE2P.x1]
		945
		946	push eax
		947	push ebx
		948	push ecx
		949	push edx
		950
		951	call _LineClip
		952	add esp, 16
		953	test eax, eax
		954	jnz .exit
		955
732	serge	956	mov edx, [R5xxRops+4+GXcopy*8]
		957	or edx, [rhd.control]
		958	or edx, (R5XX_GMC_BRUSH_SOLID_COLOR or R5XX_GMC_SRC_DATATYPE_COLOR)
		959
736	serge	960	pushfd
		961	cli
		962
		963	mov eax, 7
		964	call R5xxFIFOWait
		965
732	serge	966	wrr R5XX_DST_LINE_PATCOUNT, (0x55 shl R5XX_BRES_CNTL_SHIFT)
		967	wrr R5XX_DP_GUI_MASTER_CNTL, edx
		968
		969	mov eax, [esi+FILL.color]
		970	wrr R5XX_DP_BRUSH_FRGD_CLR, eax
		971
		972	wrr R5XX_DP_WRITE_MASK, 0xFFFFFFFF
		973
		974	mov eax, [rhd.dst_pitch_offset]
		975	wrr R5XX_DST_PITCH_OFFSET, eax
		976
		977	mov ebx, [esi+LINE2P.y1]
		978	shl ebx, 16
		979	mov bx, word [esi+LINE2P.x1]
		980	wrr R5XX_DST_LINE_START, ebx
		981
		982	mov ecx, [esi+LINE2P.y2]
		983	shl ecx, 16
		984	mov cx, word [esi+LINE2P.x2]
		985	wrr R5XX_DST_LINE_END, ecx
736	serge	986	popfd
734	serge	987	.exit:
		988	ret
732	serge	989
734	serge	990	align 4
		991	__L1OutCode:
		992	cmp eax, [__xmin]
		993	mov ecx, edx
		994	setl dl
		995	sal edx, 3
		996	cmp eax, [__xmax]
		997	jle L9
		998	or edx, 4
		999	L9:
		1000	cmp ecx, [__ymin]
		1001	jge L11
		1002	or edx, 1
		1003	L11:
		1004	cmp ecx, [__ymax]
		1005	jle L13
		1006	or edx, 2
		1007	L13:
		1008	movzx eax, dl
732	serge	1009	ret
734	serge	1010
		1011	align 4
		1012	_line_inter:
		1013	push ebp
		1014	mov ebp, edx
		1015	push edi
		1016	push esi
		1017	push ebx
		1018	sub esp, 4
		1019	mov ebx, [eax]
		1020	mov [esp], eax
		1021	mov edx, [esp+24]
		1022	mov edi, [ebp]
		1023	sub ecx, ebx
		1024	mov eax, ecx
		1025	sar eax, 31
		1026	sub edx, edi
		1027	mov esi, eax
		1028	xor esi, ecx
		1029	sub esi, eax
		1030	mov eax, [esp+28]
		1031	lea ecx, [edx+edx]
		1032	sub eax, ebx
		1033	cdq
		1034	xor eax, edx
		1035	sub eax, edx
		1036	imul ecx, eax
		1037	test ecx, ecx
		1038	jle L17
		1039	add ecx, esi
		1040	jmp L19
		1041	L17:
		1042	sub ecx, esi
		1043	L19:
		1044	lea edx, [esi+esi]
		1045	mov eax, ecx
		1046	mov ebx, edx
		1047	cdq
		1048	idiv ebx
		1049	lea eax, [eax+edi]
		1050	mov [ebp], eax
		1051	mov eax, [esp]
		1052	mov edx, [esp+28]
		1053	mov [eax], edx
		1054	pop eax
		1055	pop ebx
		1056	pop esi
		1057	pop edi
		1058	pop ebp
		1059	ret
		1060
		1061	_LineClip:
		1062	push ebp
		1063	push edi
		1064	push esi
		1065	push ebx
		1066	mov eax, [esp+24]
		1067	mov ecx, [esp+20]
		1068	mov ebp, [esp+28]
		1069	mov edi, [esp+32]
		1070	mov edx, [eax]
		1071	mov eax, [ecx]
		1072	call __L1OutCode
		1073	mov edx, [edi]
		1074	mov bl, al
		1075	mov eax, [ebp]
		1076	call __L1OutCode
		1077	L48:
		1078	mov esi, eax
		1079	L47:
		1080	mov eax, esi
		1081	and al, bl
		1082	jne L23
		1083	mov edx, esi
		1084	cmp bl, dl
		1085	je L23
		1086	test bl, bl
		1087	jne L26
		1088	movsx eax, dl
		1089	test al, 1
		1090	je L28
		1091	push [__ymin]
		1092	mov ecx, [esp+24]
		1093	push dword [ecx]
		1094	jmp L51
		1095	L28:
		1096	test al, 2
		1097	je L31
		1098	push [__ymax]
		1099	mov edx, [esp+24]
		1100	push dword [edx]
		1101	L51:
		1102	mov eax, [esp+32]
		1103	mov edx, ebp
		1104	mov ecx, [eax]
		1105	mov eax, edi
		1106	jmp L49
		1107	L31:
		1108	test al, 4
		1109	je L33
		1110	push [__xmax]
		1111	jmp L52
		1112	L33:
		1113	test al, 8
		1114	je L30
		1115	push [__xmin]
		1116	L52:
		1117	mov edx, [esp+28]
		1118	push dword [edx]
		1119	mov edx, edi
		1120	mov eax, [esp+28]
		1121	mov ecx, [eax]
		1122	mov eax, ebp
		1123	L49:
		1124	call _line_inter
		1125	pop esi
		1126	pop eax
		1127	L30:
		1128	mov edx, [edi]
		1129	mov eax, [ebp]
		1130	call __L1OutCode
		1131	jmp L48
		1132	L26:
		1133	movsx eax, bl
		1134	test al, 1
		1135	je L36
		1136	push [__ymin]
		1137	jmp L53
		1138	L36:
		1139	test al, 2
		1140	je L39
		1141	push [__ymax]
		1142	L53:
		1143	push dword [ebp]
		1144	mov ecx, [edi]
		1145	mov edx, [esp+28]
		1146	mov eax, [esp+32]
		1147	jmp L50
		1148	L39:
		1149	test al, 4
		1150	je L41
		1151	push [__xmax]
		1152	jmp L54
		1153	L41:
		1154	test al, 8
		1155	je L38
		1156	push [__xmin]
		1157	L54:
		1158	push dword [edi]
		1159	mov ecx, [ebp]
		1160	mov edx, [esp+32]
		1161	mov eax, [esp+28]
		1162	L50:
		1163	call _line_inter
		1164	pop edx
		1165	pop ecx
		1166	L38:
		1167	mov ecx, [esp+24]
		1168	mov edx, [ecx]
		1169	mov ecx, [esp+20]
		1170	mov eax, [ecx]
		1171	call __L1OutCode
		1172	mov bl, al
		1173	jmp L47
		1174	L23:
		1175	pop ebx
		1176	movsx eax, al
		1177	pop esi
		1178	pop edi
		1179	pop ebp
		1180	ret
		1181
		1182	align 4
		1183	_block_inter:
		1184	test cl, 1
		1185	push ebx
		1186	mov ebx, eax
		1187	je L57
		1188	mov eax, [__ymin]
		1189	jmp L66
		1190	L57:
		1191	test cl, 2
		1192	je L60
		1193	mov eax, [__ymax]
		1194	L66:
		1195	mov [edx], eax
		1196	jmp L65
		1197	L60:
		1198	test cl, 4
		1199	je L62
		1200	mov eax, [__xmax]
		1201	jmp L67
		1202	L62:
		1203	and cl, 8
		1204	je L65
		1205	mov eax, [__xmin]
		1206	L67:
		1207	mov [ebx], eax
		1208	L65:
		1209	pop ebx
		1210	ret
		1211
		1212	align 4
		1213	_BlockClip:
		1214	push ebp
		1215	push edi
		1216	push esi
		1217	push ebx
		1218	mov eax, [esp+24]
		1219	mov ecx, [esp+20]
		1220	mov ebp, [esp+28]
		1221	mov edi, [esp+32]
		1222	mov edx, [eax]
		1223	mov eax, [ecx]
		1224	call __L1OutCode
		1225	mov edx, [edi]
		1226	mov ebx, eax
		1227	mov eax, [ebp]
		1228	call __L1OutCode
		1229	L80:
		1230	mov esi, eax
		1231	L79:
		1232	test esi, ebx
		1233	jne L70
		1234	cmp ebx, esi
		1235	je L72
		1236	test ebx, ebx
		1237	jne L74
		1238	mov edx, edi
		1239	mov eax, ebp
		1240	mov ecx, esi
		1241	call _block_inter
		1242	mov edx, [edi]
		1243	mov eax, [ebp]
		1244	call __L1OutCode
		1245	jmp L80
		1246	L74:
		1247	mov edx, [esp+24]
		1248	mov ecx, ebx
		1249	mov eax, [esp+20]
		1250	call _block_inter
		1251	mov eax, [esp+24]
		1252	mov ecx, [esp+20]
		1253	mov edx, [eax]
		1254	mov eax, [ecx]
		1255	call __L1OutCode
		1256	mov ebx, eax
		1257	jmp L79
		1258	L72:
		1259	mov esi, ebx
		1260	L70:
		1261	mov eax, esi
		1262	and eax, ebx
		1263	pop ebx
		1264	cwde
		1265	pop esi
		1266	pop edi
		1267	pop ebp
		1268	ret

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(root)/kernel/trunk/drivers/r500hw.inc @ 874 – Rev 791