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Rev | Author | Line No. | Line |
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2886 | hidnplayr | 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
2 | ;; ;; |
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3 | ;; Copyright (C) KolibriOS team 2004-2012. All rights reserved. ;; |
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4 | ;; Distributed under terms of the GNU General Public License ;; |
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5 | ;; ;; |
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6 | ;; GNU GENERAL PUBLIC LICENSE ;; |
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7 | ;; Version 2, June 1991 ;; |
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8 | ;; ;; |
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9 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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10 | |||
11 | |||
12 | ; PCI Bus defines |
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13 | |||
14 | PCI_HEADER_TYPE = 0x0e ; 8 bit |
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15 | PCI_BASE_ADDRESS_0 = 0x10 ; 32 bit |
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16 | PCI_BASE_ADDRESS_5 = 0x24 ; 32 bits |
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17 | PCI_BASE_ADDRESS_SPACE_IO = 0x01 |
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18 | PCI_VENDOR_ID = 0x00 ; 16 bit |
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19 | PCI_BASE_ADDRESS_IO_MASK = 0xFFFFFFFC |
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20 | |||
21 | ; PCI programming |
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22 | |||
23 | PCI_REG_COMMAND = 0x4 ; command register |
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24 | PCI_REG_STATUS = 0x6 ; status register |
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25 | PCI_REG_LATENCY = 0xd ; latency timer register |
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26 | PCI_REG_CAP_PTR = 0x34 ; capabilities pointer |
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27 | PCI_REG_CAPABILITY_ID = 0x0 ; capapility ID in pm register block |
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28 | PCI_REG_PM_STATUS = 0x4 ; power management status register |
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29 | PCI_REG_PM_CTRL = 0x4 ; power management control register |
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30 | PCI_BIT_PIO = 1 ; bit0: io space control |
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31 | PCI_BIT_MMIO = 2 ; bit1: memory space control |
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32 | PCI_BIT_MASTER = 4 ; bit2: device acts as a PCI master |
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33 | |||
34 | |||
35 | macro find_io bus, dev, io { |
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36 | |||
37 | local .check, .inc, .got |
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38 | |||
39 | xor eax, eax |
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40 | mov esi, PCI_BASE_ADDRESS_0 |
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41 | movzx ecx, bus |
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42 | movzx edx, dev |
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43 | .check: |
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44 | stdcall PciRead32, ecx ,edx ,esi |
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45 | |||
46 | test eax, PCI_BASE_ADDRESS_IO_MASK |
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47 | jz .inc |
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48 | |||
49 | test eax, PCI_BASE_ADDRESS_SPACE_IO |
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50 | jz .inc |
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51 | |||
52 | and eax, PCI_BASE_ADDRESS_IO_MASK |
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53 | mov io , eax |
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54 | jmp .got |
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55 | |||
56 | .inc: |
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57 | add esi, 4 |
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58 | cmp esi, PCI_BASE_ADDRESS_5 |
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59 | jle .check |
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60 | |||
61 | .got: |
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62 | |||
63 | } |
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64 | |||
65 | |||
66 | macro find_mmio32 bus, dev, mmio32 { |
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67 | |||
68 | local .check, .got |
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69 | |||
70 | xor eax, eax |
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71 | mov esi, PCI_BASE_ADDRESS_0 |
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72 | movzx ecx, bus |
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73 | movzx edx, dev |
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74 | .check: |
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75 | stdcall PciRead32, ecx ,edx ,esi |
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76 | |||
77 | test eax, not PCI_BASE_ADDRESS_IO_MASK |
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78 | jz .got |
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79 | |||
80 | add esi, 4 |
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81 | cmp esi, PCI_BASE_ADDRESS_5 |
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82 | jle .check |
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83 | |||
84 | xor eax, eax |
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85 | .got: |
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86 | mov mmio32, eax |
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87 | |||
88 | } |
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89 | |||
90 | macro find_irq bus, dev, irq { |
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91 | |||
92 | push eax edx ecx |
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93 | movzx ecx, bus |
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94 | movzx edx, dev |
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95 | stdcall PciRead8, ecx ,edx ,0x3c ; 0x3c is the offset where irq can be found |
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96 | mov irq, al |
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97 | pop ecx edx eax |
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98 | |||
99 | } |
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100 | |||
101 | macro find_rev bus, dev, rev { |
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102 | |||
103 | push eax edx ecx |
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104 | movzx ecx, bus |
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105 | movzx edx, dev |
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106 | stdcall PciRead8, ecx ,edx ,0x8 |
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107 | mov rev, al |
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108 | pop ecx edx eax |
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109 | |||
110 | } |
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111 | |||
112 | macro make_bus_master bus, dev { |
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113 | |||
114 | movzx ecx, bus |
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115 | movzx edx, dev |
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116 | stdcall PciRead32, ecx ,edx, PCI_REG_COMMAND |
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2911 | hidnplayr | 117 | or al, PCI_BIT_MASTER |
2886 | hidnplayr | 118 | stdcall PciWrite32, ecx, edx, PCI_REG_COMMAND, eax |
119 | |||
2911 | hidnplayr | 120 | } |
2886 | hidnplayr | 121 | |
2911 | hidnplayr | 122 | macro adjust_latency bus, dev, min { |
123 | |||
124 | movzx ecx, bus |
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125 | movzx edx, dev |
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126 | stdcall PciRead8, ecx ,edx, PCI_REG_LATENCY |
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127 | cmp al, min |
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128 | ja @f |
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129 | mov al, min |
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130 | stdcall PciWrite8, ecx, edx, PCI_REG_LATENCY, eax |
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131 | @@: |
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132 | |||
133 | } |