Rev 854 | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
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| 854 | serge | 1 | /* |
| 2 | * Copyright (c) 2006 Jakub Jermar |
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| 3 | * All rights reserved. |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * |
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| 9 | * - Redistributions of source code must retain the above copyright |
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| 10 | * notice, this list of conditions and the following disclaimer. |
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| 11 | * - Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * - The name of the author may not be used to endorse or promote products |
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| 15 | * derived from this software without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 27 | */ |
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| 28 | |||
| 29 | |||
| 30 | #ifndef KERN_ATOMIC_H_ |
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| 31 | #define KERN_ATOMIC_H_ |
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| 32 | |||
| 33 | typedef struct atomic { |
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| 34 | volatile long count; |
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| 35 | } atomic_t; |
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| 36 | |||
| 37 | static inline void atomic_inc(atomic_t *val) { |
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| 38 | #ifdef USE_SMP |
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| 886 | serge | 39 | asm volatile ("lock incl %0\n" : "+m" (val->count)); |
| 854 | serge | 40 | #else |
| 886 | serge | 41 | asm volatile ("incl %0\n" : "+m" (val->count)); |
| 854 | serge | 42 | #endif /* USE_SMP */ |
| 43 | } |
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| 44 | |||
| 45 | static inline void atomic_dec(atomic_t *val) { |
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| 46 | #ifdef USE_SMP |
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| 886 | serge | 47 | asm volatile ("lock decl %0\n" : "+m" (val->count)); |
| 854 | serge | 48 | #else |
| 886 | serge | 49 | asm volatile ("decl %0\n" : "+m" (val->count)); |
| 854 | serge | 50 | #endif /* USE_SMP */ |
| 51 | } |
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| 52 | |||
| 53 | /* |
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| 54 | static inline long atomic_postinc(atomic_t *val) |
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| 55 | { |
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| 56 | long r = 1; |
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| 57 | |||
| 58 | asm volatile ( |
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| 59 | "lock xadd %1, %0\n" |
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| 60 | : "+m" (val->count), "+r" (r) |
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| 61 | ); |
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| 62 | |||
| 63 | return r; |
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| 64 | } |
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| 65 | |||
| 66 | static inline long atomic_postdec(atomic_t *val) |
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| 67 | { |
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| 68 | long r = -1; |
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| 69 | |||
| 70 | asm volatile ( |
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| 71 | "lock xadd %1, %0\n" |
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| 72 | : "+m" (val->count), "+r"(r) |
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| 73 | ); |
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| 74 | |||
| 75 | return r; |
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| 76 | } |
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| 77 | |||
| 78 | #define atomic_preinc(val) (atomic_postinc(val) + 1) |
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| 79 | #define atomic_predec(val) (atomic_postdec(val) - 1) |
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| 80 | |||
| 81 | static inline u32_t test_and_set(atomic_t *val) { |
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| 82 | uint32_t v; |
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| 83 | |||
| 84 | asm volatile ( |
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| 85 | "movl $1, %0\n" |
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| 86 | "xchgl %0, %1\n" |
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| 87 | : "=r" (v),"+m" (val->count) |
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| 88 | ); |
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| 89 | |||
| 90 | return v; |
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| 91 | } |
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| 92 | */ |
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| 93 | |||
| 94 | /* ia32 specific fast spinlock */ |
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| 95 | |||
| 96 | static inline void atomic_lock_arch(atomic_t *val) |
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| 97 | { |
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| 98 | u32_t tmp; |
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| 99 | |||
| 100 | // preemption_disable(); |
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| 101 | |||
| 886 | serge | 102 | asm volatile ( |
| 103 | "0:\n" |
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| 104 | "pause\n" /* Pentium 4's HT love this instruction */ |
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| 105 | "mov %0, %1\n" |
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| 106 | "testl %1, %1\n" |
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| 107 | "jnz 0b\n" /* lightweight looping on locked spinlock */ |
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| 108 | |||
| 109 | "incl %1\n" /* now use the atomic operation */ |
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| 110 | "xchgl %0, %1\n" |
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| 111 | "testl %1, %1\n" |
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| 112 | "jnz 0b\n" |
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| 113 | : "+m" (val->count), "=&r"(tmp) |
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| 114 | ); |
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| 854 | serge | 115 | // CS_ENTER_BARRIER(); |
| 116 | } |
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| 117 | |||
| 118 | static inline void atomic_set(atomic_t *val, long i) |
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| 119 | { |
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| 120 | val->count = i; |
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| 121 | } |
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| 122 | |||
| 123 | static inline long atomic_get(atomic_t *val) |
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| 124 | { |
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| 125 | return val->count; |
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| 126 | } |
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| 127 | |||
| 128 | #endif /* KERN_ATOMIC_H_ */ |
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| 129 |