WebSVN – Kolibri OS – Blame – /kernel/branches/kolibri-ahci/blkdev/ahci.inc

Rev	Author	Line No.	Line
9020	rgimad	1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		2	;; ;;
		3	;; Copyright (C) KolibriOS team 2004-2021. All rights reserved. ;;
		4	;; Distributed under terms of the GNU General Public License ;;
		5	;; ;;
		6	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		7
		8	$Revision$
		9
		10	PCI_REG_STATUS_COMMAND = 0x0004
		11	PCI_REG_BAR5 = 0x0024
		12
9162	rgimad	13	AHCI_DBGLVL = 0 ; debug output verbosity level. 0 - less verbose, 1 - more verbose
		14
9134	rgimad	15	; different SATA device signatures
9184	rgimad	16	SATA_SIG_ATA = 0x00000101 ; SATA drive
		17	SATA_SIG_ATAPI = 0xEB140101 ; SATAPI drive
		18	SATA_SIG_SEMB = 0xC33C0101 ; Enclosure management bridge
		19	SATA_SIG_PM = 0x96690101 ; Port multiplier
9134	rgimad	20
		21	; Device type constants
		22	AHCI_DEV_NULL = 0
		23	AHCI_DEV_SATA = 1
		24	AHCI_DEV_SEMB = 2
		25	AHCI_DEV_PM = 3
		26	AHCI_DEV_SATAPI = 4
		27
		28	; ATA commands
9162	rgimad	29	ATA_IDENTIFY = 0xEC
		30	ATA_CMD_READ_DMA_EX = 0x25
		31	ATA_CMD_WRITE_DMA_EX = 0x35
9134	rgimad	32
9139	rgimad	33	; ATA constants
		34	ATA_DEV_BUSY = 0x80
		35	ATA_DEV_DRQ = 0x08
		36
9134	rgimad	37	; ATAPI commands
		38	ATAPI_IDENTIFY = 0xA1
		39
9162	rgimad	40	PRDT_MAX_ENTRIES = 16 ;65535
		41
9023	rgimad	42	; bit_ prefix means that its index of bit
		43	; format: bit_AHCI_STR_REG_BIT
		44	bit_AHCI_HBA_CAP2_BOH = 0 ; Supports BIOS/OS Handoff
9020	rgimad	45
9023	rgimad	46	bit_AHCI_HBA_BOHC_BOS = 0 ; BIOS-Owned Semaphore (BIOS owns controller)
		47	bit_AHCI_HBA_BOHC_OOS = 1 ; OS-Owned Semaphore (OS owns controller)
		48	bit_AHCI_HBA_BOHC_BB = 4 ; BIOS Busy (polling bit while BIOS cleans up
9020	rgimad	49
9023	rgimad	50	bit_AHCI_HBA_GHC_AHCI_ENABLE = 31 ; Enable AHCI mode
		51	bit_AHCI_HBA_GHC_RESET = 0 ; Reset HBA
		52	bit_AHCI_HBA_GHC_INTERRUPT_ENABLE = 1 ; Enable interrupts from the HBA
		53
9065	rgimad	54	bit_AHCI_HBA_PxCMD_ST = 0
		55	bit_AHCI_HBA_PxCMD_FRE = 4
		56	bit_AHCI_HBA_PxCMD_FR = 14
		57	bit_AHCI_HBA_PxCMD_CR = 15
9139	rgimad	58	bit_AHCI_HBA_PxIS_TFES = 30
9065	rgimad	59
9130	rgimad	60	AHCI_HBA_PxCMD_ST = 1 shl 0
		61	AHCI_HBA_PxCMD_FRE = 1 shl 4
		62	AHCI_HBA_PxCMD_FR = 1 shl 14
		63	AHCI_HBA_PxCMD_CR = 1 shl 15
		64
9074	rgimad	65	bit_AHCI_H2D_FLAG_CMD = 7
		66
9037	rgimad	67	AHCI_HBA_PxSSTS_DET = 0xF
		68	AHCI_HBA_PORT_IPM_ACTIVE = 1
		69	AHCI_HBA_PxSSTS_DET_PRESENT = 3
		70
9023	rgimad	71	AHCI_MAX_PORTS = 32 ;
9064	rgimad	72	;HBA_MEMORY_SIZE = 0x1100
9020	rgimad	73
9139	rgimad	74	AHCI_PORT_TIMEOUT = 1000000
		75
9064	rgimad	76	; Frame Information Structure Types
		77	FIS_TYPE_REG_H2D = 0x27 ; Register FIS - host to device
		78	FIS_TYPE_REG_D2H = 0x34 ; Register FIS - device to host
		79	FIS_TYPE_DMA_ACT = 0x39 ; DMA activate FIS - device to host
		80	FIS_TYPE_DMA_SETUP = 0x41 ; DMA setup FIS - bidirectional
		81	FIS_TYPE_DATA = 0x46 ; Data FIS - bidirectional
		82	FIS_TYPE_BIST = 0x58 ; BIST activate FIS - bidirectional
		83	FIS_TYPE_PIO_SETUP = 0x5F ; PIO setup FIS - device to host
		84	FIS_TYPE_DEV_BITS = 0xA1 ; Set device bits FIS - device to host
		85
9020	rgimad	86	; Generic Host Control registers
		87	struct HBA_MEM
9064	rgimad	88	cap dd ? ; 0x00, Host capabilities
		89	ghc dd ? ; 0x04, Global host control
		90	is dd ? ; 0x08, Interrupt status
		91	pi dd ? ; 0x0C, Port implemented
		92	version dd ? ; 0x10, Version
9020	rgimad	93	ccc_ctl dd ? ; 0x14, Command completion coalescing control
		94	ccc_pts dd ? ; 0x18, Command completion coalescing ports
		95	em_loc dd ? ; 0x1C, Enclosure management location
		96	em_ctl dd ? ; 0x20, Enclosure management control
9064	rgimad	97	cap2 dd ? ; 0x24, Host capabilities extended
9020	rgimad	98	bohc dd ? ; 0x28, BIOS/OS handoff control and status
9072	rgimad	99	reserved rb (0xA0-HBA_MEM.reserved) ; 0x2C - 0x9F, Reserved
		100	vendor rb (0x100-HBA_MEM.vendor) ; 0xA0 - 0xFF, Vendor specific
9023	rgimad	101	ports rb (sizeof.HBA_PORT*AHCI_MAX_PORTS) ; 0x100 - 0x10FF, Port control registers, max AHCI_MAX_PORTS
9020	rgimad	102	ends
		103
		104	; Port Control registers
		105	struct HBA_PORT
9064	rgimad	106	command_list_base_l dd ? ; 0x00, command list base address, 1K-byte aligned
		107	command_list_base_h dd ? ; 0x04, command list base address upper 32 bits, used on 64 bit systems
		108	fis_base_l dd ? ; 0x08, FIS base address, 256-byte aligned
		109	fis_base_h dd ? ; 0x0C, FIS base address upper 32 bits, used on 64 bit systems
		110	interrupt_status dd ? ; 0x10
		111	interrupt_enable dd ? ; 0x14
		112	command dd ? ; 0x18, command and status
		113	reserved0 dd ? ; 0x1C
		114	task_file_data dd ? ; 0x20
		115	signature dd ? ; 0x24
		116	sata_status dd ? ; 0x28, SATA status (SCR0:SStatus)
		117	sata_control dd ? ; 0x2C, SATA control (SCR2:SControl)
		118	sata_error dd ? ; 0x30, SATA error (SCR1:SError)
		119	sata_active dd ? ; 0x34, SATA active (SCR3:SActive)
		120	command_issue dd ? ; 0x38
		121	sata_notification dd ? ; 0x3C, SATA notification (SCR4:SNotification)
		122	fis_based_switch_control dd ? ; 0x40
		123	reserved1 rd 11 ; 0x44 - 0x6F
		124	vendor rd 4 ; 0x70 - 0x7F, vendor specific
9020	rgimad	125	ends
		126
9074	rgimad	127	; Command header structure, size = 32 bytes
9068	rgimad	128	struct HBA_CMD_HDR
9131	rgimad	129	flags1 db ? ; 0bPWACCCCC, P - Prefetchable, W - Write (1: H2D, 0: D2H)
9068	rgimad	130	; A - ATAPI, C - Command FIS length in DWORDS, 2 ~ 16
		131
9131	rgimad	132	flags2 db ? ; 0bPPPPRCB(Re), P - Port multiplier port, R - Reserved,
9068	rgimad	133	; C - Clear busy upon R_OK, B - BIST, Re - Reset
		134
		135	prdtl dw ? ; Physical region descriptor table length in entries
		136	prdbc dd ? ; Physical region descriptor byte count transferred
		137	ctba dd ? ; Command table descriptor base address
		138	ctbau dd ? ; Command table descriptor base address upper 32 bits
9072	rgimad	139	rd 4 ; Reserved
9068	rgimad	140	ends
		141
9074	rgimad	142	; Physical region descriptor table entry, size = 16 bytes
9069	rgimad	143	struct HBA_PRDT_ENTRY
		144	dba dd ? ; Data base address
		145	dbau dd ? ; Data base address upper 32 bits
9072	rgimad	146	dd ? ; Reserved
9131	rgimad	147	flags dd ? ; 0bIR..RD..D, I (1 bit) - Interrupt on completion,
9069	rgimad	148	; R (9 bits) - Reserved, D (22 bits) - Byte count, 4M max
		149	ends
		150
		151	struct HBA_CMD_TBL
		152	cfis rb 64 ; 0x00, Command FIS
		153	acmd rb 16 ; 0x40, ATAPI command, 12 or 16 bytes
9072	rgimad	154	rb 48 ; 0x50, Reserved
9069	rgimad	155	prdt_entry HBA_PRDT_ENTRY ; 0x80, Physical region descriptor table entries, 0 ~ 65535
		156	; so, this structure is variable-length
		157	ends
		158
9068	rgimad	159	; Contains virtual mappings for port phys memory regions
		160	struct PORT_DATA
		161	clb dd ? ; Command list base
		162	fb dd ? ; FIS base
		163	ctba_arr rd 32 ; ctba_arr[0] = clb[0].ctba, ... and so on.
		164	port dd ? ; address of correspoding HBA_PORT structure
9074	rgimad	165	portno dd ? ; port index, 0..31
9134	rgimad	166	drive_type db ? ; drive type
9140	rgimad	167	sector_count dq ? ; number of sectors
9068	rgimad	168	ends
		169
9064	rgimad	170	; Register FIS – Host to Device
		171	struct FIS_REG_H2D
		172	fis_type db ? ; FIS_TYPE_REG_H2D
9131	rgimad	173	flags db ? ; 0bCRRRPPPP, C - 1: Command, 0: Control
9064	rgimad	174	; R - Reserved, P - Port multiplier
		175
		176	command db ? ; Command register
		177	featurel db ? ; Feature register, 7:0
		178
		179	lba0 db ? ; LBA low register, 7:0
		180	lba1 db ? ; LBA mid register, 15:8
		181	lba2 db ? ; LBA high register, 23:16
		182	device db ? ; Device register
		183
		184	lba3 db ? ; LBA register, 31:24
		185	lba4 db ? ; LBA register, 39:32
		186	lba5 db ? ; LBA register, 47:40
		187	featureh db ? ; Feature register, 15:8
		188
		189	countl db ? ; Count register, 7:0
		190	counth db ? ; Count register, 15:8
		191	icc db ? ; Isochronous command completion
		192	control db ? ; Control register
		193
9072	rgimad	194	rb 4 ; Reserved
9064	rgimad	195	ends
		196
		197	; Register FIS – Device to Host
		198	struct FIS_REG_D2H
		199	fis_type db ? ; FIS_TYPE_REG_D2H
		200
9131	rgimad	201	flags db ? ; 0bRIRPPPP, P - Port multiplier, R - Reserved
9064	rgimad	202	; I - Interrupt bit
		203
		204	status db ? ; Status register
		205	error db ? ; Error register
		206
		207	lba0 db ? ; LBA low register, 7:0
		208	lba1 db ? ; LBA mid register, 15:8
		209	lba2 db ? ; LBA high register, 23:16
		210	device db ? ; Device register
		211
		212	lba3 db ? ; LBA register, 31:24
		213	lba4 db ? ; LBA register, 39:32
		214	lba5 db ? ; LBA register, 47:40
9072	rgimad	215	db ? ; Reserved
9064	rgimad	216
		217	countl db ? ; Count register, 7:0
		218	counth db ? ; Count register, 15:8
9072	rgimad	219	rb 2 ; Reserved
9064	rgimad	220
9072	rgimad	221	rb 4 ; Reserved
9064	rgimad	222	ends
		223
		224	; Data FIS – Bidirectional
		225	struct FIS_DATA
		226	fis_type db ? ; FIS_TYPE_DATA
9131	rgimad	227	flags db ? ; 0bRRRRPPPP, R - Reserved, P - Port multiplier
9072	rgimad	228	rb 2 ; Reserved
9064	rgimad	229	; DWORD 1 ~ N (?)
		230	data rd 1 ; Payload
		231	ends
		232
		233	; PIO Setup – Device to Host
		234	struct FIS_PIO_SETUP
		235	fis_type db ? ; FIS_TYPE_PIO_SETUP
		236
9131	rgimad	237	flags db ? ; 0bRIDRPPPP, P - Port multiplier, R - Reserved
9064	rgimad	238	; I - Interrupt bit, D - Data transfer direction, 1 - device to host
		239
		240	status db ? ; Status register
		241	error db ? ; Error register
		242
		243	lba0 db ? ; LBA low register, 7:0
		244	lba1 db ? ; LBA mid register, 15:8
		245	lba2 db ? ; LBA high register, 23:16
		246	device db ? ; Device register
		247
		248	lba3 db ? ; LBA register, 31:24
		249	lba4 db ? ; LBA register, 39:32
		250	lba5 db ? ; LBA register, 47:40
9072	rgimad	251	db ? ; Reserved
9064	rgimad	252
		253	countl db ? ; Count register, 7:0
		254	counth db ? ; Count register, 15:8
9072	rgimad	255	db ? ; Reserved
9064	rgimad	256	e_status db ? ; New value of status register
		257
		258	tc dw ? ; Transfer count
9072	rgimad	259	rb 2 ; Reserved
9064	rgimad	260	ends
		261
		262	; DMA Setup – Device to Host
		263	struct FIS_DMA_SETUP
		264	fis_type db ? ; FIS_TYPE_DMA_SETUP
9131	rgimad	265	flags db ? ; 0bAIDRPPPP, A - Auto-activate. Specifies if DMA Activate FIS is needed,
9064	rgimad	266	; I - Interrupt bit, D - Data transfer direction, 1 - device to host,
		267	; R - Reserved, P - Port multiplier
		268
9072	rgimad	269	rb 2 ; Reserved
9064	rgimad	270	DMAbufferID dq ? ; DMA Buffer Identifier.
		271	; Used to Identify DMA buffer in host memory.
		272	; SATA Spec says host specific and not in Spec.
		273	; Trying AHCI spec might work.
		274
9072	rgimad	275	dd ? ; Reserved
		276	DMAbufOffset dd ? ; Byte offset into buffer. First 2 bits must be 0
9064	rgimad	277	TransferCount dd ? ; Number of bytes to transfer. Bit 0 must be 0
9072	rgimad	278	dd ? ; Reserved
9064	rgimad	279	ends
		280
		281	; Set device bits FIS - device to host
		282	struct FIS_DEV_BITS
		283	fis_type db ? ; FIS_TYPE_DEV_BITS
9131	rgimad	284	flags db ? ; 0bNIRRPPPP, N - Notification, I - Interrupt,
9064	rgimad	285	; R - Reserved, P - Port multiplier
		286
		287	status db ? ; Status register
		288	error db ? ; Error register
		289
		290	protocol dd ? ; Protocol
		291	ends
		292
9069	rgimad	293	struct HBA_FIS
		294	dsfis FIS_DMA_SETUP ; 0x00, DMA Setup FIS
9072	rgimad	295	rb 4 ; padding
9069	rgimad	296
		297	psfis FIS_PIO_SETUP ; 0x20, PIO Setup FIS
9072	rgimad	298	rb 12 ; padding
9069	rgimad	299
		300	rfis FIS_REG_D2H ; 0x40, Register - Device to Host FIS
9072	rgimad	301	rb 4 ; padding
9069	rgimad	302
		303	sdbfis FIS_DEV_BITS ; 0x58, Set Device Bit FIS
		304
		305	ufis rb 64 ; 0x60
		306
9072	rgimad	307	rb (0x100 - 0xA0) ; 0xA0, Reserved
9069	rgimad	308	ends
		309
9064	rgimad	310	; --------------------------------------------------
9020	rgimad	311	uglobal
9264	rgimad	312
9020	rgimad	313	align 4
9264	rgimad	314
9271	rgimad	315	; AHCI controller structure
		316	struct AHCI_CTR
		317	abar dd ? ; pointer to HBA Memory (BAR5) mapped to virtual kernelspace memory
		318	pcidev dd ? ; pointer to corresponding PCIDEV structure
9264	rgimad	319	port_data_arr rb (sizeof.PORT_DATA*AHCI_MAX_PORTS)
9271	rgimad	320	mutex MUTEX
9264	rgimad	321	ends
		322
9271	rgimad	323	ctr1_data AHCI_CTR
		324	ctr2_data AHCI_CTR
		325	ctr3_data AHCI_CTR
		326	ctr4_data AHCI_CTR
		327	ctr5_data AHCI_CTR
		328	ctr6_data AHCI_CTR
		329	ctr7_data AHCI_CTR
		330	ctr8_data AHCI_CTR
9264	rgimad	331
9271	rgimad	332	ctr_ptr dd ?
9020	rgimad	333	endg
		334
9140	rgimad	335	iglobal
		336	align 4
		337	ahci_callbacks:
		338	dd ahci_callbacks.end - ahci_callbacks
		339	dd 0 ; no close function
		340	dd 0 ; no closemedia function
		341	dd ahci_querymedia
9143	rgimad	342	dd ahci_read
9166	rgimad	343	dd ahci_write
9140	rgimad	344	dd 0 ; no flush function
		345	dd 0 ; use default cache size
		346	.end:
9264	rgimad	347	hd_name db 'sd', 0, 0, 0
9271	rgimad	348	sata_dev_counter dd 0 ; sata devices counter
		349	; TODO: satapi_dev_counter dd 0 ; satapi devices (optical drives) counter
		350	ctr_counter dd 0 ; controllers counter
9140	rgimad	351	endg
		352
9064	rgimad	353	; -----------------------------------------------------------------------
9020	rgimad	354	; detect ahci controller and initialize
		355	align 4
9068	rgimad	356	ahci_init:
9020	rgimad	357	mov esi, pcidev_list
9271	rgimad	358	mov [ctr_ptr], ctr1_data
		359	mov [sata_dev_counter], 0
9020	rgimad	360	.find_ahci_ctr:
		361	mov esi, [esi + PCIDEV.fd]
		362	cmp esi, pcidev_list
		363	jz .ahci_ctr_not_found
		364	mov eax, [esi + PCIDEV.class]
		365	;DEBUGF 1, "K: device class = %x\n", eax
		366	shr eax, 8 ; shift right because lowest 8 bits if ProgIf field
		367	cmp eax, 0x0106 ; 0x01 - Mass Storage Controller class, 0x06 - Serial ATA Controller subclass
		368	jz .ahci_ctr_found
		369	jmp .find_ahci_ctr
		370
		371	.ahci_ctr_not_found:
		372	DEBUGF 1, "K: AHCI controller not found\n"
		373	ret
		374
		375	.ahci_ctr_found:
9264	rgimad	376	push esi
9020	rgimad	377
9271	rgimad	378	mov ecx, [ctr_ptr]
		379	add ecx, AHCI_CTR.mutex
9264	rgimad	380	call mutex_init
		381
9271	rgimad	382	mov ecx, [ctr_ptr]
		383	mov [ecx + AHCI_CTR.pcidev], esi
9264	rgimad	384
9020	rgimad	385	mov eax, [esi+PCIDEV.class]
		386	movzx ebx, byte [esi+PCIDEV.bus]
		387	movzx ecx, byte [esi+PCIDEV.devfn]
		388	shr ecx, 3 ; get rid of 3 lowest bits (function code), the rest bits is device code
		389	movzx edx, byte [esi+PCIDEV.devfn]
		390	and edx, 00000111b ; get only 3 lowest bits (function code)
		391	DEBUGF 1, "K: found AHCI controller, (class, subcl, progif) = %x, bus = %x, device = %x, function = %x\n", eax, ebx, ecx, edx
		392
9023	rgimad	393	; get BAR5 value, it is physical address
9037	rgimad	394	movzx ebx, [esi + PCIDEV.bus]
		395	movzx ebp, [esi + PCIDEV.devfn]
		396	stdcall pci_read32, ebx, ebp, PCI_REG_BAR5
		397	DEBUGF 1, "K: AHCI controller MMIO = %x\n", eax
		398	mov edi, eax
9020	rgimad	399
9037	rgimad	400	; get the size of MMIO region
		401	stdcall pci_write32, ebx, ebp, PCI_REG_BAR5, 0xFFFFFFFF
		402	stdcall pci_read32, ebx, ebp, PCI_REG_BAR5
		403	not eax
		404	inc eax
		405	DEBUGF 1, "K: AHCI: MMIO region size = 0x%x bytes\n", eax
		406
		407	; Map MMIO region to virtual memory
		408	stdcall map_io_mem, edi, eax, PG_SWR + PG_NOCACHE
9264	rgimad	409	push ecx
9271	rgimad	410	mov ecx, [ctr_ptr]
		411	mov [ecx + AHCI_CTR.abar], eax
9264	rgimad	412	pop ecx
9020	rgimad	413	DEBUGF 1, "K: AHCI controller BAR5 mapped to virtual addr %x\n", eax
		414
9037	rgimad	415	; Restore the original BAR5 value
		416	stdcall pci_write32, ebx, ebp, PCI_REG_BAR5, edi
		417
9023	rgimad	418	; Enable dma bus mastering, memory space access, clear the "disable interrupts" bit
		419	; Usually, it is already done before us
9024	rgimad	420	movzx ebx, [esi + PCIDEV.bus]
		421	movzx ebp, [esi + PCIDEV.devfn]
		422	stdcall pci_read32, ebx, ebp, PCI_REG_STATUS_COMMAND
9020	rgimad	423	DEBUGF 1, "K: AHCI: pci_status_command = %x\nEnabling interrupts, DMA bus mastering and memory space access\n", eax
		424	or eax, 0x06 ; pci.command \|= 0x06 (dma bus mastering + memory space access)
		425	btr eax, 10 ; clear the "disable interrupts" bit
		426	DEBUGF 1, "K: AHCI: pci_status_command = %x\n", eax
9024	rgimad	427	stdcall pci_write32, ebx, ebp, PCI_REG_STATUS_COMMAND, eax
9020	rgimad	428
9271	rgimad	429	mov esi, [ctr_ptr]
		430	mov esi, [esi + AHCI_CTR.abar]
		431
9023	rgimad	432	; ; Print some register values to debug board
9064	rgimad	433	; DEBUGF 1, "K: AHCI: HBA.cap = %x, HBA.ghc = %x, HBA_MEM.version = %x\n", [esi + HBA_MEM.cap], [esi + HBA_MEM.ghc], [esi + HBA_MEM.version]
9020	rgimad	434
9023	rgimad	435	;-------------------------------------------------------
		436	; Request BIOS/OS ownership handoff, if supported. (TODO check correctness)
9064	rgimad	437	;mov ebx, [esi + HBA_MEM.cap2]
9023	rgimad	438	;DEBUGF 1, "K: AHCI: HBA_MEM.cap2 = %x\n", ebx
9064	rgimad	439	bt [esi + HBA_MEM.cap2], bit_AHCI_HBA_CAP2_BOH
9020	rgimad	440	jnc .end_handoff
9023	rgimad	441	DEBUGF 1, "K: AHCI: requesting AHCI ownership change...\n"
9024	rgimad	442	bts [esi + HBA_MEM.bohc], bit_AHCI_HBA_BOHC_OOS
9020	rgimad	443
		444	.wait_not_bos:
9024	rgimad	445	bt [esi + HBA_MEM.bohc], bit_AHCI_HBA_BOHC_BOS
9020	rgimad	446	jc .wait_not_bos
		447
		448	mov ebx, 3
		449	call delay_hs
		450
9023	rgimad	451	; if Bios Busy is still set after 30 mS, wait 2 seconds.
9024	rgimad	452	bt [esi + HBA_MEM.bohc], bit_AHCI_HBA_BOHC_BB
9020	rgimad	453	jnc @f
		454
		455	mov ebx, 200
		456	call delay_hs
		457	@@:
9023	rgimad	458	DEBUGF 1, "K: AHCI: ownership change completed.\n"
9020	rgimad	459
		460	.end_handoff:
9023	rgimad	461	;-------------------------------------------------------
9020	rgimad	462
9023	rgimad	463	; enable the AHCI and reset it
9064	rgimad	464	bts [esi + HBA_MEM.ghc], bit_AHCI_HBA_GHC_AHCI_ENABLE
		465	bts [esi + HBA_MEM.ghc], bit_AHCI_HBA_GHC_RESET
9020	rgimad	466
9023	rgimad	467	; wait for reset to complete
		468	.wait_reset:
9064	rgimad	469	bt [esi + HBA_MEM.ghc], bit_AHCI_HBA_GHC_RESET
9023	rgimad	470	jc .wait_reset
9020	rgimad	471
9023	rgimad	472	; enable the AHCI and interrupts
9064	rgimad	473	bts [esi + HBA_MEM.ghc], bit_AHCI_HBA_GHC_AHCI_ENABLE
		474	bts [esi + HBA_MEM.ghc], bit_AHCI_HBA_GHC_INTERRUPT_ENABLE
9023	rgimad	475	mov ebx, 2
		476	call delay_hs
		477
9064	rgimad	478	DEBUGF 1, "K: AHCI: caps: %x %x, ver: %x, ghc: %x, pi: %x\n", [esi + HBA_MEM.cap], [esi + HBA_MEM.cap2], [esi + HBA_MEM.version], [esi + HBA_MEM.ghc], [esi + HBA_MEM.pi]
9020	rgimad	479
9037	rgimad	480	; TODO:
		481	; calculate irq line
		482	; ahciHBA->ghc \|= AHCI_GHC_IE;
		483	; IDT::RegisterInterruptHandler(irq, InterruptHandler);
9064	rgimad	484	; ahciHBA->is = 0xffffffff;
9037	rgimad	485
		486	xor ebx, ebx
		487	.detect_drives:
		488	cmp ebx, AHCI_MAX_PORTS
		489	jae .end_detect_drives
		490
		491	; if port with index ebx is not implemented then go to next
9064	rgimad	492	mov ecx, [esi + HBA_MEM.pi]
9037	rgimad	493	bt ecx, ebx
		494	jnc .continue_detect_drives
		495
		496	mov edi, ebx
9074	rgimad	497	imul edi, sizeof.HBA_PORT
9037	rgimad	498	add edi, HBA_MEM.ports
		499	add edi, esi
		500	; now edi - base of HBA_MEM.ports[ebx]
		501
9130	rgimad	502	DEBUGF 1, "K: AHCI: port %d, cmd = %x, ssts = %x\n", ebx, [edi + HBA_PORT.command], [edi + HBA_PORT.sata_status]
9037	rgimad	503
9130	rgimad	504	; If port is not idle force it to be idle
		505	mov eax, [edi + HBA_PORT.command]
		506	and eax, (AHCI_HBA_PxCMD_ST or AHCI_HBA_PxCMD_CR or AHCI_HBA_PxCMD_FRE or AHCI_HBA_PxCMD_FR)
		507	test eax, eax
		508	jz @f
		509
		510	mov eax, edi
		511	DEBUGF 1, "ahci_stop_cmd..\n"
		512	call ahci_stop_cmd
		513	@@:
		514	; TODO: what is purpose of this block of code ?
		515	; Reset port, disable slumber and partial state
		516	; mov [edi + HBA_PORT.sata_control], 0x301
		517	; push ebx
		518	; mov ebx, 5 ; wait 50 ms
		519	; call delay_hs
		520	; pop ebx
		521	; mov [edi + HBA_PORT.sata_control], 0x300
		522
		523	; if(abar->cap & HBA_MEM_CAP_SSS)
		524	; {
		525	; abar->ports[i].cmd \|= (HBA_PxCMD_SUD \| HBA_PxCMD_POD \| HBA_PxCMD_ICC);
		526	; Sleep(10);
		527	; }
		528	; rewritten to:
		529	bt [esi + HBA_MEM.cap], 27 ; check Supports Staggered Spin-up bit in capabilities
		530	jnc @f
9134	rgimad	531	DEBUGF 1, "Supports Staggered Spin-up, spinning up the port..\n"
9130	rgimad	532	or [edi + HBA_PORT.command], (0x0002 or 0x0004 or 0x10000000)
		533	push ebx
9162	rgimad	534	mov ebx, 10 ; wait 100 ms
9130	rgimad	535	call delay_hs
		536	pop ebx
		537	@@:
		538	; Clear interrupt status and error status
		539	mov [edi + HBA_PORT.sata_error], 0xFFFFFFFF
		540	mov [edi + HBA_PORT.interrupt_status], 0xFFFFFFFF
		541
		542	; ------------------------------------------
		543
9037	rgimad	544	mov ecx, [edi + HBA_PORT.sata_status]
		545	shr ecx, 8
		546	and ecx, 0x0F
		547	cmp ecx, AHCI_HBA_PORT_IPM_ACTIVE
		548	jne .continue_detect_drives
		549
		550	mov ecx, [edi + HBA_PORT.sata_status]
		551	and ecx, AHCI_HBA_PxSSTS_DET
		552	cmp ecx, AHCI_HBA_PxSSTS_DET_PRESENT
9068	rgimad	553	jne .continue_detect_drives
9037	rgimad	554
9134	rgimad	555	; DEBUGF 1, "K: AHCI: found drive at port %d, cmd = 0x%x, ssts = 0x%x, signature = 0x%x\n", ebx, [edi + HBA_PORT.command], [edi + HBA_PORT.sata_status], [edi + HBA_PORT.signature]
9037	rgimad	556
9068	rgimad	557	mov ecx, ebx
9074	rgimad	558	imul ecx, sizeof.PORT_DATA
9271	rgimad	559	add ecx, AHCI_CTR.port_data_arr
		560	add ecx, [ctr_ptr]
9068	rgimad	561	stdcall ahci_port_rebase, edi, ebx, ecx
		562
9134	rgimad	563	; DEBUGF 1, "K: AHCI: After REBASING, signature = 0x%x\n", [edi + HBA_PORT.signature]
		564
9135	rgimad	565	; Determine drive type by checking port signature
9134	rgimad	566	.switch_sig:
		567	cmp [edi + HBA_PORT.signature], SATA_SIG_ATA
9135	rgimad	568	mov eax, AHCI_DEV_SATA
		569	jz .end_switch_sig
		570
9134	rgimad	571	cmp [edi + HBA_PORT.signature], SATA_SIG_ATAPI
9135	rgimad	572	mov eax, AHCI_DEV_SATAPI
		573	jz .end_switch_sig
		574
9134	rgimad	575	cmp [edi + HBA_PORT.signature], SATA_SIG_SEMB
9135	rgimad	576	mov eax, AHCI_DEV_SEMB
		577	jz .end_switch_sig
		578
9134	rgimad	579	cmp [edi + HBA_PORT.signature], SATA_SIG_PM
9135	rgimad	580	mov eax, AHCI_DEV_PM
		581	jz .end_switch_sig
		582
9134	rgimad	583	DEBUGF 1, "Unknown device signature\n"
9135	rgimad	584	mov eax, AHCI_DEV_NULL
9134	rgimad	585	.end_switch_sig:
9136	rgimad	586	mov [ecx + PORT_DATA.drive_type], al
9134	rgimad	587
		588	DEBUGF 1, "K: AHCI: found drive on port %u: TYPE = %u\n", ebx, [ecx + PORT_DATA.drive_type]
		589
9074	rgimad	590	stdcall ahci_port_identify, ecx
		591
9140	rgimad	592	cmp [ecx + PORT_DATA.drive_type], AHCI_DEV_SATA
		593	jne .after_add_disk ; skip adding disk code
		594	; register disk in system:
9143	rgimad	595
		596	;stdcall ahci_read_first_sector, ecx
9141	rgimad	597
9142	rgimad	598	push ecx
9271	rgimad	599	mov eax, [sata_dev_counter]
		600	inc [sata_dev_counter]
9140	rgimad	601	xor edx, edx
		602	mov ecx, 10
9271	rgimad	603	div ecx ; eax = sata_dev_counter / 10, edx = sata_dev_counter % 10
9140	rgimad	604	test eax, eax
		605	jz .concat_one
		606	add al, '0'
		607	mov byte [hd_name + 2], al
		608	add dl, '0'
		609	mov byte [hd_name + 3], dl
		610	jmp .endif1
		611	.concat_one:
		612	add dl, '0'
		613	mov byte [hd_name + 2], dl
		614	.endif1:
9142	rgimad	615	pop ecx
9140	rgimad	616
		617	DEBUGF 1, "adding '%s'\n", hd_name
		618
9142	rgimad	619	push ecx
9140	rgimad	620	stdcall disk_add, ahci_callbacks, hd_name, ecx, 0
9142	rgimad	621	pop ecx
9140	rgimad	622	test eax, eax
		623	jz .disk_add_fail
9142	rgimad	624	push ecx
9140	rgimad	625	stdcall disk_media_changed, eax, 1 ; system will scan for partitions on disk
9142	rgimad	626	pop ecx
9141	rgimad	627
9140	rgimad	628	jmp .after_add_disk
		629
		630	.disk_add_fail:
		631	DEBUGF 1, "Failed to add disk\n"
		632	.after_add_disk:
		633
9037	rgimad	634	.continue_detect_drives:
		635	inc ebx
		636	jmp .detect_drives
		637
9064	rgimad	638
9037	rgimad	639
		640	.end_detect_drives:
9264	rgimad	641	pop esi
9271	rgimad	642	add [ctr_ptr], sizeof.AHCI_CTR
		643	inc [ctr_counter]
		644	cmp [ctr_counter], 8
9264	rgimad	645	jnz .find_ahci_ctr
		646	DEBUGF 1, "AHCI: reached controllers number limit\n"
9020	rgimad	647	ret
9065	rgimad	648	; -------------------------------------------------
9020	rgimad	649
9074	rgimad	650	modelstr rb 42
		651	; Identify drive on port ; TODO check
		652	; in: pdata - address of PORT_DATA structure
		653	proc ahci_port_identify stdcall, pdata: dword
		654	locals
		655	cmdslot dd ?
		656	cmdheader dd ?
		657	cmdtable dd ?
		658	buf_phys dd ?
		659	buf_virt dd ?
		660	endl
		661
		662	pushad
		663
		664	mov esi, [pdata] ; esi - address of PORT_DATA struct of port
		665	mov edi, [esi + PORT_DATA.port] ; edi - address of HBA_PORT struct of port
		666
		667	mov eax, edi
		668	call ahci_find_cmdslot
		669
		670	cmp eax, -1
9184	rgimad	671	jne .cmdslot_found
9074	rgimad	672
		673	DEBUGF 1, "No free cmdslot on port %u\n", [esi + PORT_DATA.portno]
9140	rgimad	674	jmp .ret
9074	rgimad	675
		676	.cmdslot_found:
		677	mov [cmdslot], eax
9134	rgimad	678	; DEBUGF 1, "Found free cmdslot %u on port %u\n", [cmdslot], [esi + PORT_DATA.portno]
9074	rgimad	679
		680	shl eax, BSF sizeof.HBA_CMD_HDR
		681	add eax, [esi + PORT_DATA.clb]
		682	mov [cmdheader], eax ; address of virtual mapping of command header
		683	mov eax, [cmdslot]
		684	mov eax, [esi + eax*4 + PORT_DATA.ctba_arr]
		685	mov [cmdtable], eax ; address of virtual mapping of command table of command header
		686
		687	stdcall _memset, eax, 0, sizeof.HBA_CMD_TBL
		688
		689	call alloc_page
		690	mov [buf_phys], eax
		691
		692	stdcall map_io_mem, eax, 4096, PG_NOCACHE + PG_SWR ; map to virt memory so we can work with it
		693	mov [buf_virt], eax
		694
		695	mov eax, [cmdtable]
		696	mov ebx, [buf_phys]
		697	mov dword [eax + HBA_CMD_TBL.prdt_entry + HBA_PRDT_ENTRY.dba], ebx
		698	mov dword [eax + HBA_CMD_TBL.prdt_entry + HBA_PRDT_ENTRY.dbau], 0
9131	rgimad	699	and [eax + HBA_CMD_TBL.prdt_entry + HBA_PRDT_ENTRY.flags], not 0x3FFFFF ; zero out lower 22 bits, they used for byte count
		700	or [eax + HBA_CMD_TBL.prdt_entry + HBA_PRDT_ENTRY.flags], 512 - 1 ; reason why -1 see in spec on this field
		701	; or [eax + HBA_CMD_TBL.prdt_entry + HBA_PRDT_ENTRY.flags], 1 shl 31 ; enable interrupt on completion
		702
9074	rgimad	703	mov eax, [cmdheader]
9131	rgimad	704	and [eax + HBA_CMD_HDR.flags1], not 0x1F ; zero out lower 5 bits, they will be used for cfl
		705	or [eax + HBA_CMD_HDR.flags1], (sizeof.FIS_REG_H2D / 4) ; set command fis length in dwords
		706	movzx bx, [eax + HBA_CMD_HDR.flags1]
		707	btr bx, 6 ; flag W = 0
		708	mov [eax + HBA_CMD_HDR.flags1], bl
		709	movzx bx, [eax + HBA_CMD_HDR.flags2]
		710	btr bx, 2 ; flag C = 0
		711	mov [eax + HBA_CMD_HDR.flags2], bl
9074	rgimad	712	mov [eax + HBA_CMD_HDR.prdtl], 1
		713
		714	mov eax, [cmdtable]
		715	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.fis_type], FIS_TYPE_REG_H2D
9131	rgimad	716	movzx ebx, byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.flags]
9074	rgimad	717	bts ebx, bit_AHCI_H2D_FLAG_CMD ; Set Command bit in H2D FIS.
9131	rgimad	718	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.flags], bl
9134	rgimad	719
		720	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.command], ATA_IDENTIFY
		721	cmp [esi + PORT_DATA.drive_type], AHCI_DEV_SATAPI
		722	jne @f
		723	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.command], ATAPI_IDENTIFY
		724	@@:
9074	rgimad	725	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.device], 0
		726
9139	rgimad	727	; Wait on previous command to complete, before issuing new command.
		728	stdcall ahci_port_wait, edi, AHCI_PORT_TIMEOUT
		729	; DEBUGF 1, "eax = %x\n", eax
		730	; TODO check eax error value
9074	rgimad	731
		732	mov eax, [cmdslot]
		733	bts [edi + HBA_PORT.command_issue], eax ; Issue the command
		734
9139	rgimad	735	; Wait for command completion
		736	stdcall ahci_port_cmd_wait, edi, eax;, AHCI_PORT_CMD_TIMEOUT
		737	; DEBUGF 1, " eax = %x\n", eax
		738	; TODO check eax error value
9074	rgimad	739
9134	rgimad	740	; DEBUGF 1, "sata_error register = 0x%x\n", [edi + HBA_PORT.sata_error]
9130	rgimad	741
		742	mov esi, [buf_virt]
9074	rgimad	743	add esi, 27*2
		744	mov edi, modelstr
		745	mov ecx, ((46-27)+1)*2
		746	cld
		747	rep movsb
		748	mov byte [edi], 0
		749
9138	rgimad	750	stdcall swap_bytes_in_words, modelstr, (46-27)+1
9131	rgimad	751	DEBUGF 1, "IDENTIFICATION RESULT: MODEL = %s\n", modelstr
9074	rgimad	752
9138	rgimad	753	mov esi, [buf_virt]
		754	mov eax, [esi + 200]
		755	mov edx, [esi + 200 + 4]
		756	DEBUGF 1, "lba48 mode sector count = 0x%x:%x\n", edx, eax
		757
9145	rgimad	758	mov ebx, [pdata]
		759	mov dword [ebx + PORT_DATA.sector_count], eax
		760	mov dword [ebx + PORT_DATA.sector_count + 4], edx
		761
9138	rgimad	762	shrd eax, edx, 11 ; i.e *512 / 1024 / 1024, 512 - sector size
		763	DEBUGF 1, "disk capacity = %u MiB ", eax
		764	shrd eax, edx, 10 ; / 1024
		765	DEBUGF 1, "= %u GiB\n", eax
9074	rgimad	766	.ret:
		767	popad
		768	ret
		769	endp
		770
9140	rgimad	771	proc ahci_querymedia stdcall, pdata, mediainfo
		772	push ecx edx
		773	mov eax, [mediainfo]
		774	mov edx, [pdata]
		775	mov [eax + DISKMEDIAINFO.Flags], 0
		776	mov [eax + DISKMEDIAINFO.SectorSize], 512
		777	mov ecx, dword[edx + PORT_DATA.sector_count]
		778	mov dword [eax + DISKMEDIAINFO.Capacity], ecx
		779	mov ecx, dword[edx + PORT_DATA.sector_count + 4]
		780	mov dword [eax + DISKMEDIAINFO.Capacity + 4], ecx
		781	pop edx ecx
		782	xor eax, eax
		783	ret
		784	endp
9134	rgimad	785
9271	rgimad	786	; Read/write sectors, note: currently work for SATA, not SATAPI
9143	rgimad	787	; return value: 0 = success, otherwise = error
9162	rgimad	788	proc ahci_rw_sectors stdcall pdata: dword, vbuf: dword, startsector: qword, numsectors: dword, is_write: dword
9143	rgimad	789	locals
		790	cmdslot dd ?
		791	cmdheader dd ?
		792	cmdtable dd ?
9162	rgimad	793	vbuf_orig dd ?
		794	vbuf_len dd ?
		795	phys_region_start dd ?
		796	new_phys_region_start dd ?
		797	cur_prd dd ?
		798	cur_phys dd ?
		799	dbc dd ?
		800	cur_phys_page dd ?
		801	next_phys_page dd ?
		802	cur_antioffset dd ?
		803	prdt_bytes_total dd ?
9143	rgimad	804	endl
		805
		806	pushad
		807
9162	rgimad	808	DEBUGF AHCI_DBGLVL, " ahci_rw_sectors: buffer = 0x%x, startsector = 0x%x:%x, numsectors = %u, is_write = %u\n", [vbuf], [startsector], [startsector + 4], [numsectors], [is_write]:1
9143	rgimad	809
		810	mov esi, [pdata] ; esi - address of PORT_DATA struct of port
		811	mov edi, [esi + PORT_DATA.port] ; edi - address of HBA_PORT struct of port
		812	mov eax, edi
		813	call ahci_find_cmdslot
		814	cmp eax, -1
9184	rgimad	815	jne .cmdslot_found
9143	rgimad	816
9162	rgimad	817	DEBUGF AHCI_DBGLVL, "No free cmdslot on port %u\n", [esi + PORT_DATA.portno]
		818	jmp .fail
9143	rgimad	819
		820	.cmdslot_found:
		821	mov [cmdslot], eax
9162	rgimad	822	DEBUGF AHCI_DBGLVL, "Found free cmdslot %u on port %u\n", [cmdslot], [esi + PORT_DATA.portno]
9143	rgimad	823
		824	shl eax, BSF sizeof.HBA_CMD_HDR
		825	add eax, [esi + PORT_DATA.clb]
		826	mov [cmdheader], eax ; address of virtual mapping of command header
		827	mov eax, [cmdslot]
		828	mov eax, [esi + eax*4 + PORT_DATA.ctba_arr]
		829	mov [cmdtable], eax ; address of virtual mapping of command table of command header
		830
		831	mov eax, [cmdheader]
		832	and [eax + HBA_CMD_HDR.flags1], not 0x1F ; zero out lower 5 bits, they will be used for cfl
		833	or [eax + HBA_CMD_HDR.flags1], (sizeof.FIS_REG_H2D / 4) ; set command fis length in dwords
		834	movzx bx, [eax + HBA_CMD_HDR.flags1]
		835	btr bx, 6 ; flag W = 0
9162	rgimad	836	cmp [is_write], 1 ; if is_write then set W flag
		837	jne @f
		838	bts bx, 6
		839	@@:
9143	rgimad	840	mov [eax + HBA_CMD_HDR.flags1], bl
		841	movzx bx, [eax + HBA_CMD_HDR.flags2]
		842	btr bx, 2 ; flag C = 0
		843	mov [eax + HBA_CMD_HDR.flags2], bl
		844
9162	rgimad	845	mov eax, [vbuf]
		846	mov [vbuf_orig], eax
9143	rgimad	847	mov ebx, [numsectors]
		848	shl ebx, 9 ; *= 512
9162	rgimad	849	mov [vbuf_len], ebx
		850	DEBUGF AHCI_DBGLVL, "vbuf_len = %u bytes\n", ebx
9143	rgimad	851
9162	rgimad	852	mov ebx, [vbuf]
		853	and ebx, 0xFFF
		854	mov eax, [vbuf]
		855	call get_pg_addr
		856	add eax, ebx
		857	mov [phys_region_start], eax
		858	mov [prdt_bytes_total], 0
		859	mov [cur_prd], 0
		860	.fill_prdt:
		861	cmp [vbuf_len], 0
		862	jbe .fill_prdt_end
9143	rgimad	863
9162	rgimad	864	mov eax, [vbuf]
		865	call get_pg_addr
		866	mov [cur_phys_page], eax
		867	mov eax, [vbuf]
		868	add eax, 4096
		869	call get_pg_addr
		870	mov [next_phys_page], eax
		871	mov eax, 4096
		872	mov ebx, [vbuf]
9143	rgimad	873	and ebx, 0xFFF
9162	rgimad	874	sub eax, ebx
		875	mov [cur_antioffset], eax
		876	mov eax, [cur_phys_page]
9143	rgimad	877	add eax, ebx
9162	rgimad	878	mov [cur_phys], eax
9143	rgimad	879
9162	rgimad	880	.check_if1:
		881	mov eax, [vbuf_len]
		882	cmp eax, [cur_antioffset]
		883	ja .check_if2
9143	rgimad	884
9162	rgimad	885	mov eax, [cur_phys]
		886	sub eax, [phys_region_start]
		887	add eax, [vbuf_len]
		888	dec eax
		889	mov [dbc], eax
		890	mov eax, [next_phys_page]
		891	mov [new_phys_region_start], eax
		892	jmp .add_prd
9143	rgimad	893
9162	rgimad	894	.check_if2:
		895	mov eax, [cur_phys]
		896	add eax, [cur_antioffset]
		897	cmp eax, [next_phys_page]
		898	je .check_if3
		899
		900	mov eax, [cur_phys]
		901	add eax, [cur_antioffset]
		902	sub eax, [phys_region_start]
		903	dec eax
		904	mov [dbc], eax
		905	mov eax, [next_phys_page]
		906	mov [new_phys_region_start], eax
		907	jmp .add_prd
		908
		909	.check_if3:
		910	mov eax, [cur_phys]
		911	add eax, [cur_antioffset]
		912	sub eax, [phys_region_start]
		913	cmp eax, 410241024
		914	jb .after_ifs
		915
		916	mov [dbc], 410241024 - 1
		917	mov eax, [phys_region_start]
		918	add eax, 410241024
		919	jmp .add_prd
		920
		921	.after_ifs:
		922	jmp .step_next
		923
		924	.add_prd:
		925	mov ebx, [cur_prd]
9143	rgimad	926	shl ebx, BSF sizeof.HBA_PRDT_ENTRY
		927	add ebx, [cmdtable]
9162	rgimad	928	add ebx, HBA_CMD_TBL.prdt_entry ; now ebx - address of 'th prdt_entry
		929
		930	DEBUGF AHCI_DBGLVL, "Added PRDT entry: dba = 0x%x, dbc = %u\n", [phys_region_start], [dbc]
		931	mov eax, [phys_region_start]
9143	rgimad	932	mov [ebx + HBA_PRDT_ENTRY.dba], eax
		933	mov [ebx + HBA_PRDT_ENTRY.dbau], 0
		934	and [ebx + HBA_PRDT_ENTRY.flags], not 0x3FFFFF ; zero out lower 22 bits, they used for byte count
9162	rgimad	935	mov eax, [dbc]
		936	or [ebx + HBA_PRDT_ENTRY.flags], eax
		937
		938	inc [cur_prd]
		939	mov eax, [dbc]
		940	inc eax
		941	add [prdt_bytes_total], eax
		942	mov eax, [new_phys_region_start]
		943	mov [phys_region_start], eax
		944	cmp [cur_prd], PRDT_MAX_ENTRIES
		945	jne @f
		946	jmp .fill_prdt_end
		947	@@:
		948
		949	.step_next:
		950	mov eax, [vbuf_len]
		951	cmp eax, [cur_antioffset]
		952	jbe @f
		953	mov eax, [cur_antioffset]
		954	@@:
		955	add [vbuf], eax
		956	sub [vbuf_len], eax
		957	jmp .fill_prdt
9143	rgimad	958
9162	rgimad	959	.fill_prdt_end:
		960
		961	mov eax, [cmdheader]
		962	mov ebx, [cur_prd]
		963	DEBUGF AHCI_DBGLVL, " PRDTL = %u\n", ebx
		964	mov [eax + HBA_CMD_HDR.prdtl], bx
		965
		966	mov eax, [prdt_bytes_total]
		967	DEBUGF AHCI_DBGLVL, " prdt_bytes_total = %u\n", eax
		968	shr eax, 9 ; /= 512
		969	mov [numsectors], eax
		970
9143	rgimad	971	mov eax, [cmdtable]
		972	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.fis_type], FIS_TYPE_REG_H2D
		973	movzx ebx, byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.flags]
		974	bts ebx, bit_AHCI_H2D_FLAG_CMD ; Set Command bit in H2D FIS.
		975	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.flags], bl
		976
		977	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.command], ATA_CMD_READ_DMA_EX
9162	rgimad	978	cmp [is_write], 1
		979	jne @f
		980	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.command], ATA_CMD_WRITE_DMA_EX
		981	@@:
9143	rgimad	982	mov ebx, dword [startsector]
		983	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.lba0], bl
		984	shr ebx, 8
		985	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.lba1], bl
		986	shr ebx, 8
		987	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.lba2], bl
		988	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.device], 1 shl 6 ; LBA mode
		989	shr ebx, 8
		990	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.lba3], bl
		991	mov ebx, dword [startsector + 4]
		992	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.lba4], bl
		993	shr ebx, 8
		994	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.lba5], bl
		995
		996	mov ebx, [numsectors]
		997	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.countl], bl
		998	shr ebx, 8
		999	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.counth], bl
		1000
		1001	; Wait on previous command to complete, before issuing new command.
		1002	stdcall ahci_port_wait, edi, AHCI_PORT_TIMEOUT
		1003
		1004	mov eax, [cmdslot]
		1005	bts [edi + HBA_PORT.command_issue], eax ; Issue the command
		1006
		1007	; Wait for command completion
		1008	stdcall ahci_port_cmd_wait, edi, eax;, AHCI_PORT_CMD_TIMEOUT
		1009
9162	rgimad	1010	DEBUGF AHCI_DBGLVL, "sata_error register = 0x%x\n", [edi + HBA_PORT.sata_error]
9143	rgimad	1011
9166	rgimad	1012	DEBUGF AHCI_DBGLVL, "R/W completed\n"
9143	rgimad	1013
9145	rgimad	1014	; xor ecx, ecx
9162	rgimad	1015	; mov esi, [vbuf_orig]
9145	rgimad	1016	; .print_data:
		1017	; cmp ecx, 512
		1018	; jae .end_print_data
9143	rgimad	1019
9145	rgimad	1020	; mov al, byte [esi + ecx]
		1021	; mov byte [tmpstr], al
		1022	; mov byte [tmpstr + 1], 0
		1023	; DEBUGF 1, "0x%x(%s) ", al:2, tmpstr
9143	rgimad	1024
9145	rgimad	1025	; inc ecx
		1026	; jmp .print_data
		1027	; .end_print_data:
		1028	; DEBUGF 1, "\n"
9143	rgimad	1029
9162	rgimad	1030	popad
		1031	;mov eax, [cmdheader]
		1032	;mov eax, [eax + HBA_CMD_HDR.prdbc]
		1033	mov eax, [numsectors]
		1034	shl eax, 9 ; *= 512
		1035	ret
9143	rgimad	1036
9162	rgimad	1037	.fail:
9143	rgimad	1038	popad
		1039	xor eax, eax
		1040	ret
		1041	endp
		1042	tmpstr rb 16
		1043
9162	rgimad	1044	; Read sectors
		1045	; return value: 0 = success, otherwise = error
		1046	proc ahci_read stdcall pdata: dword, buffer: dword, startsector: qword, numsectors_ptr:dword
		1047	locals
		1048	numsectors dd ?
		1049	endl
		1050
		1051	pushad
		1052
9271	rgimad	1053	mov ecx, ctr1_data.mutex ; why ctr1 ? TODO: make for corresponding controller
9162	rgimad	1054	call mutex_lock
		1055
		1056	mov eax, [numsectors_ptr]
		1057	mov eax, [eax]
		1058	mov [numsectors], eax
		1059	DEBUGF AHCI_DBGLVL, " ahci_read: buffer = 0x%x, startsector = 0x%x:%x, numsectors = %u\n", [buffer], [startsector], [startsector + 4], eax
		1060
		1061	xor ecx, ecx ; how many sectors have been read
		1062	.read_loop:
		1063	cmp ecx, [numsectors]
		1064	jae .read_loop_end
		1065
		1066	; mov eax, [buffer]
		1067	; call get_pg_addr
		1068	; DEBUGF 1, "buf phys = 0x%x\n", eax
		1069	; mov eax, [buffer]
		1070	; add eax, 4096
		1071	; call get_pg_addr
		1072	; DEBUGF 1, "buf + 4096 phys = 0x%x\n", eax
		1073
		1074	mov ebx, [numsectors]
		1075	sub ebx, ecx
		1076	; DEBUGF 1, "buffer = 0x%x\n", [buffer]
		1077	stdcall ahci_rw_sectors, [pdata], [buffer], dword [startsector], dword [startsector + 4], ebx, 0
		1078	;; TODO check if eax == 0 ?
		1079
		1080	DEBUGF AHCI_DBGLVL, " EAX = 0x%x\n", eax
		1081
		1082	add [buffer], eax
		1083	shr eax, 9 ; /= 512
		1084	add ecx, eax
		1085	add dword [startsector], eax
		1086	adc dword [startsector + 4], 0
		1087
		1088	jmp .read_loop
		1089	.read_loop_end:
		1090
9271	rgimad	1091	mov ecx, ctr1_data.mutex ; why ctr1 ? TODO: make for corresponding controller
9162	rgimad	1092	call mutex_unlock
		1093
		1094	popad
		1095	xor eax, eax
		1096	ret
		1097	endp
		1098
9166	rgimad	1099	; Write sectors
		1100	; return value: 0 = success, otherwise = error
		1101	proc ahci_write stdcall pdata: dword, buffer: dword, startsector: qword, numsectors_ptr:dword
		1102	locals
		1103	numsectors dd ?
		1104	endl
		1105
		1106	pushad
		1107
9271	rgimad	1108	mov ecx, ctr1_data.mutex ; why ctr1 ? TODO: make for corresponding controller
9166	rgimad	1109	call mutex_lock
		1110
		1111	mov eax, [numsectors_ptr]
		1112	mov eax, [eax]
		1113	mov [numsectors], eax
		1114	DEBUGF AHCI_DBGLVL, " ahci_write: buffer = 0x%x, startsector = 0x%x:%x, numsectors = %u\n", [buffer], [startsector], [startsector + 4], eax
		1115
		1116	xor ecx, ecx ; how many sectors have been read
		1117	.write_loop:
		1118	cmp ecx, [numsectors]
		1119	jae .write_loop_end
		1120
		1121	mov ebx, [numsectors]
		1122	sub ebx, ecx
		1123	stdcall ahci_rw_sectors, [pdata], [buffer], dword [startsector], dword [startsector + 4], ebx, 1
		1124	;; TODO check if eax == 0 ?
		1125
		1126	DEBUGF AHCI_DBGLVL, " EAX = 0x%x\n", eax
		1127
		1128	add [buffer], eax
		1129	shr eax, 9 ; /= 512
		1130	add ecx, eax
		1131	add dword [startsector], eax
		1132	adc dword [startsector + 4], 0
		1133
		1134	jmp .write_loop
		1135	.write_loop_end:
		1136
9271	rgimad	1137	mov ecx, ctr1_data.mutex ; why ctr1 ? TODO: make for corresponding controller
9166	rgimad	1138	call mutex_unlock
		1139
		1140	popad
		1141	xor eax, eax
		1142	ret
		1143	endp
		1144
9065	rgimad	1145	; Start command engine
		1146	; in: eax - address of HBA_PORT structure
9068	rgimad	1147	ahci_start_cmd:
9065	rgimad	1148	.wait_cr: ; Wait until CR (bit15) is cleared
		1149	bt [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_CR
		1150	jc .wait_cr
		1151
		1152	; Set FRE (bit4) and ST (bit0)
		1153	bts [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_FRE
		1154	bts [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_ST
9068	rgimad	1155	; maybe here call ahci flush cmd ? TODO (see seakernel)
9065	rgimad	1156	ret
		1157
		1158	; Stop command engine
		1159	; in: eax - address of HBA_PORT structure
9068	rgimad	1160	ahci_stop_cmd:
9065	rgimad	1161	btr [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_ST ; Clear ST (bit0)
		1162	btr [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_FRE ; Clear FRE (bit4)
		1163	.wait_fr_cr: ; Wait until FR (bit14), CR (bit15) are cleared
		1164	bt [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_FR
		1165	jc .wait_fr_cr
		1166	bt [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_CR
		1167	jc .wait_fr_cr
		1168
		1169	ret
		1170
9139	rgimad	1171	; waits until the port is no longer busy before issuing a new command
		1172	; in: [port] - address of HBA_PORT structure
		1173	; [timeout] - timeout (in iterations)
		1174	; out: eax = 0 if success, 1 if timeout expired
		1175	proc ahci_port_wait stdcall, port: dword, timeout: dword
		1176	push ebx ecx
		1177	mov ebx, [port]
		1178	xor ecx, ecx
		1179	.wait:
		1180	cmp ecx, [timeout]
		1181	jae .wait_end
		1182	mov eax, [ebx + HBA_PORT.task_file_data]
		1183	and eax, ATA_DEV_BUSY or ATA_DEV_DRQ
		1184	test eax, eax
		1185	jz .wait_end
		1186	inc ecx
		1187	jmp .wait
		1188	.wait_end:
		1189	xor eax, eax
9162	rgimad	1190	DEBUGF AHCI_DBGLVL, "port wait counter = %u\n", ecx
9139	rgimad	1191	cmp ecx, [timeout] ; if they equal it means port is hung
		1192	setz al
		1193	pop ecx ebx
9068	rgimad	1194	ret
9139	rgimad	1195	endp
9065	rgimad	1196
		1197
9139	rgimad	1198	; Wait for command completion
		1199	; in: [port] - address of HBA_PORT structure
		1200	; [cmdslot] - number of command slot
		1201	; out: eax = 0 if success, 1 if error
		1202	proc ahci_port_cmd_wait stdcall, port: dword, cmdslot: dword ;, timeout: dword
		1203	push ebx ecx edx
		1204	mov ebx, [port]
		1205	mov edx, [cmdslot]
		1206	xor eax, eax
		1207	xor ecx, ecx
		1208	.wait:
		1209	bt [ebx + HBA_PORT.command_issue], edx
		1210	jnc .wait_end
		1211	bt [ebx + HBA_PORT.interrupt_status], bit_AHCI_HBA_PxIS_TFES ; check for Task File Error
		1212	jc .error
		1213	inc ecx
		1214	jmp .wait
		1215	.wait_end:
9162	rgimad	1216	DEBUGF AHCI_DBGLVL, "port cmd wait counter = %u\n", ecx
9139	rgimad	1217	bt [ebx + HBA_PORT.interrupt_status], bit_AHCI_HBA_PxIS_TFES ; check for Task File Error
		1218	jc .error
		1219	jmp .ret
		1220	.error:
		1221	mov eax, 1
		1222	.ret:
		1223	pop edx ecx ebx
9068	rgimad	1224	ret
9139	rgimad	1225	endp
9065	rgimad	1226
9139	rgimad	1227	; ; The commands may not take effect until the command
		1228	; ; register is read again by software, because reasons.
		1229	; ; in: eax - address of HBA_PORT structure
		1230	; ; out: eax - command register value
		1231	; ahci_flush_cmd:
		1232	; mov eax, [eax + HBA_PORT.command]
		1233	; ret
		1234
		1235	; ; Send command to port
		1236	; ; in: eax - address of HBA_PORT structure
		1237	; ; ebx - index of command slot
		1238	; ahci_send_cmd:
		1239	; push ecx
		1240	; mov [eax + HBA_PORT.interrupt_status], 0xFFFFFFFF
		1241
		1242	; mov cl, bl
		1243	; mov [eax + HBA_PORT.command_issue], 1
		1244	; shl [eax + HBA_PORT.command_issue], cl
		1245
		1246	; call ahci_flush_cmd
		1247	; pop ecx
		1248	; ret
		1249
9068	rgimad	1250	; ---------------------------------------------------------------------------
		1251	; in: port - address of HBA_PORT structure
		1252	; portno - port index (0..31)
		1253	; pdata - address of PORT_DATA structure
		1254	proc ahci_port_rebase stdcall, port: dword, portno: dword, pdata: dword
		1255	locals
		1256	phys_page1 dd ?
		1257	virt_page1 dd ?
		1258	phys_page23 dd ?
		1259	virt_page23 dd ?
		1260	tmp dd ?
		1261	endl
		1262
		1263	pushad
		1264
		1265	DEBUGF 1, "Rebasing port %u\n", [portno]
		1266
		1267	mov eax, [port]
		1268	call ahci_stop_cmd
		1269
		1270	; Command list entry size = 32
		1271	; Command list entry maxim count = 32
		1272	; Command list maxim size = 32*32 = 1K per port
		1273	call alloc_page
		1274	mov [phys_page1], eax
		1275
		1276	stdcall map_io_mem, eax, 4096, PG_NOCACHE + PG_SWR ; map to virt memory so we can work with it
		1277	mov [virt_page1], eax
		1278
		1279	mov esi, [port]
		1280	mov ebx, [phys_page1]
		1281	mov [esi + HBA_PORT.command_list_base_l], ebx ; set the command list base
		1282	mov [esi + HBA_PORT.command_list_base_h], 0 ; zero upper 32 bits of addr cause we are 32 bit os
		1283
		1284	mov edi, [pdata]
		1285	mov ebx, [virt_page1]
		1286	mov [edi + PORT_DATA.clb], ebx ; set pdata->clb
		1287
		1288	mov eax, [port]
		1289	mov [edi + PORT_DATA.port], eax ; set pdata->port
9074	rgimad	1290	mov eax, [portno] ; set pdata->portno
		1291	mov [edi + PORT_DATA.portno], eax
9068	rgimad	1292
		1293	stdcall _memset, ebx, 0, 1024 ; zero out the command list
		1294
		1295	; FIS entry size = 256 bytes per port
		1296	mov eax, [phys_page1]
		1297	add eax, 1024
		1298	mov [esi + HBA_PORT.fis_base_l], eax
		1299	mov [esi + HBA_PORT.fis_base_h], 0
		1300
		1301	mov eax, [virt_page1]
		1302	add eax, 1024
		1303	mov [edi + PORT_DATA.fb], eax ; set pdata->fb
		1304	stdcall _memset, eax, 0, 256 ; zero out
		1305
9162	rgimad	1306	stdcall alloc_pages, 32(64 + 16 + 48 + PRDT_MAX_ENTRIES16)/4096
9068	rgimad	1307	mov [phys_page23], eax
9162	rgimad	1308	stdcall map_io_mem, eax, 32(64 + 16 + 48 + PRDT_MAX_ENTRIES16), PG_NOCACHE + PG_SWR
9068	rgimad	1309	mov [virt_page23], eax
		1310
9162	rgimad	1311	; Command table size = N*32 per port
9068	rgimad	1312	mov edx, [edi + PORT_DATA.clb] ; cmdheader array base
		1313	xor ecx, ecx
		1314
		1315	.for1:
		1316	cmp ecx, 32
		1317	jae .for1_end
		1318
		1319	mov ebx, ecx
		1320	shl ebx, BSF sizeof.HBA_CMD_HDR
		1321	add ebx, edx ; ebx = cmdheader[ecx]
		1322
9162	rgimad	1323	mov [ebx + HBA_CMD_HDR.prdtl], PRDT_MAX_ENTRIES ; prdt entries per command table
9068	rgimad	1324
9162	rgimad	1325	; bytes per command table = 64+16+48+PRDT_MAX_ENTRIES*16 = N
9068	rgimad	1326
		1327	push edx
		1328
9162	rgimad	1329	; cmdheader[ecx].ctba = phys_page23 + ecx*N
9068	rgimad	1330	mov [ebx + HBA_CMD_HDR.ctba], ecx
9162	rgimad	1331	mov edx, [ebx + HBA_CMD_HDR.ctba]
		1332	imul edx, (64+16+48+PRDT_MAX_ENTRIES16) ; = N
		1333	mov [ebx + HBA_CMD_HDR.ctba], edx
9068	rgimad	1334	mov eax, [ebx + HBA_CMD_HDR.ctba]
		1335	mov edx, [phys_page23]
		1336	add [ebx + HBA_CMD_HDR.ctba], edx
		1337
		1338	add eax, [virt_page23]
9162	rgimad	1339	mov [tmp], eax ; tmp = virt_page23 + ecx*N
9069	rgimad	1340	lea eax, [ecx*4 + edi + PORT_DATA.ctba_arr] ; eax = pdata->ctba_arr[ecx]
9068	rgimad	1341	mov edx, [tmp]
9162	rgimad	1342	mov [eax], edx ; pdata->ctba_arr[ecx] = virt_page23 + ecx*N
9068	rgimad	1343
		1344	pop edx
		1345
		1346	mov [ebx + HBA_CMD_HDR.ctbau], 0
9162	rgimad	1347	stdcall _memset, [eax], 0, 64+16+48+PRDT_MAX_ENTRIES*16 ; zero out
9068	rgimad	1348
		1349	inc ecx
		1350	jmp .for1
		1351	.for1_end:
		1352
		1353	mov eax, [port]
		1354	call ahci_start_cmd
		1355
		1356	DEBUGF 1, "End rebasing port %u\n", [portno]
		1357	popad
		1358	ret
		1359	endp
		1360
9069	rgimad	1361	; ----------------------------------------------------------- ; TODO check
		1362	; Find a free command list slot
		1363	; in: eax - address of HBA_PORT structure
		1364	; out: eax - if not found -1, else slot index
		1365	ahci_find_cmdslot:
		1366	push ebx ecx edx esi
		1367	; If not set in SACT and CI, the slot is free
		1368	mov ebx, [eax + HBA_PORT.sata_active]
		1369	or ebx, [eax + HBA_PORT.command_issue] ; ebx = slots
9068	rgimad	1370
9271	rgimad	1371	mov esi, [ctr1_data.abar] ; why ctr1 ? TODO: make for corresponding controller
9069	rgimad	1372	mov edx, [esi + HBA_MEM.cap]
		1373	shr edx, 8
		1374	and edx, 0xf
9134	rgimad	1375	; DEBUGF 1, "Number of Command Slots on each port = %u\n", edx
9069	rgimad	1376	xor ecx, ecx
		1377	.for1:
		1378	cmp ecx, edx
		1379	jae .for1_end
9068	rgimad	1380
9069	rgimad	1381	; if ((slots&1) == 0) return i;
		1382	bt ebx, 0
		1383	jc .cont1
		1384
		1385	mov eax, ecx
		1386	jmp .ret
		1387
		1388	.cont1:
		1389	shr ebx, 1
		1390	inc ecx
		1391	jmp .for1
		1392	.for1_end:
		1393	DEBUGF 1, "Cannot find free command list entry\n"
		1394	mov eax, -1
		1395	.ret:
		1396	pop esi edx ecx ebx
		1397	ret
		1398
		1399
9068	rgimad	1400	proc _memset stdcall, dest:dword, val:byte, cnt:dword ; doesnt clobber any registers
		1401	;DEBUGF DBG_INFO, "memset(%x, %u, %u)\n", [dest], [val], [cnt]
		1402	push eax ecx edi
		1403	mov edi, dword [dest]
9184	rgimad	1404	mov al, byte [val]
9068	rgimad	1405	mov ecx, dword [cnt]
9069	rgimad	1406	rep stosb
9068	rgimad	1407	pop edi ecx eax
		1408	ret
		1409	endp
9138	rgimad	1410
		1411	; Swaps byte order in words
		1412	; base - address of first word
		1413	; len - how many words to swap bytes in
		1414	; doesnt clobber any registers
		1415	proc swap_bytes_in_words stdcall, base: dword, len: dword
		1416	push eax ebx ecx
		1417	xor ecx, ecx
		1418	mov ebx, [base]
		1419	.loop:
		1420	cmp ecx, [len]
		1421	jae .loop_end
		1422	mov ax, word [ebx + ecx*2]
		1423	xchg ah, al
		1424	mov word [ebx + ecx*2], ax
		1425	inc ecx
		1426	jmp .loop
		1427	.loop_end:
		1428	pop ecx ebx eax
		1429	ret
		1430	endp

Subversion Repositories Kolibri OS

(root)/kernel/branches/kolibri-ahci/blkdev/ahci.inc @ 9417 – Rev 9271