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Rev | Author | Line No. | Line |
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9020 | rgimad | 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
2 | ;; ;; |
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3 | ;; Copyright (C) KolibriOS team 2004-2021. All rights reserved. ;; |
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4 | ;; Distributed under terms of the GNU General Public License ;; |
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5 | ;; ;; |
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6 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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7 | |||
8 | $Revision$ |
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9 | |||
10 | PCI_REG_STATUS_COMMAND = 0x0004 |
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11 | PCI_REG_BAR5 = 0x0024 |
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12 | |||
9134 | rgimad | 13 | ; different SATA device signatures |
14 | SATA_SIG_ATA = 0x00000101 ; SATA drive |
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15 | SATA_SIG_ATAPI = 0xEB140101 ; SATAPI drive |
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16 | SATA_SIG_SEMB = 0xC33C0101 ; Enclosure management bridge |
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17 | SATA_SIG_PM = 0x96690101 ; Port multiplier |
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18 | |||
19 | ; Device type constants |
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20 | AHCI_DEV_NULL = 0 |
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21 | AHCI_DEV_SATA = 1 |
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22 | AHCI_DEV_SEMB = 2 |
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23 | AHCI_DEV_PM = 3 |
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24 | AHCI_DEV_SATAPI = 4 |
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25 | |||
26 | ; ATA commands |
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9140 | rgimad | 27 | ATA_IDENTIFY = 0xEC |
28 | ATA_CMD_READ_DMA_EX = 0x25 |
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9134 | rgimad | 29 | |
9139 | rgimad | 30 | ; ATA constants |
31 | ATA_DEV_BUSY = 0x80 |
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32 | ATA_DEV_DRQ = 0x08 |
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33 | |||
9134 | rgimad | 34 | ; ATAPI commands |
35 | ATAPI_IDENTIFY = 0xA1 |
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36 | |||
9023 | rgimad | 37 | ; bit_ prefix means that its index of bit |
38 | ; format: bit_AHCI_STR_REG_BIT |
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39 | bit_AHCI_HBA_CAP2_BOH = 0 ; Supports BIOS/OS Handoff |
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9020 | rgimad | 40 | |
9023 | rgimad | 41 | bit_AHCI_HBA_BOHC_BOS = 0 ; BIOS-Owned Semaphore (BIOS owns controller) |
42 | bit_AHCI_HBA_BOHC_OOS = 1 ; OS-Owned Semaphore (OS owns controller) |
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43 | bit_AHCI_HBA_BOHC_BB = 4 ; BIOS Busy (polling bit while BIOS cleans up |
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9020 | rgimad | 44 | |
9023 | rgimad | 45 | bit_AHCI_HBA_GHC_AHCI_ENABLE = 31 ; Enable AHCI mode |
46 | bit_AHCI_HBA_GHC_RESET = 0 ; Reset HBA |
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47 | bit_AHCI_HBA_GHC_INTERRUPT_ENABLE = 1 ; Enable interrupts from the HBA |
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48 | |||
9065 | rgimad | 49 | bit_AHCI_HBA_PxCMD_ST = 0 |
50 | bit_AHCI_HBA_PxCMD_FRE = 4 |
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51 | bit_AHCI_HBA_PxCMD_FR = 14 |
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52 | bit_AHCI_HBA_PxCMD_CR = 15 |
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9139 | rgimad | 53 | bit_AHCI_HBA_PxIS_TFES = 30 |
9065 | rgimad | 54 | |
9130 | rgimad | 55 | AHCI_HBA_PxCMD_ST = 1 shl 0 |
56 | AHCI_HBA_PxCMD_FRE = 1 shl 4 |
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57 | AHCI_HBA_PxCMD_FR = 1 shl 14 |
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58 | AHCI_HBA_PxCMD_CR = 1 shl 15 |
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59 | |||
9074 | rgimad | 60 | bit_AHCI_H2D_FLAG_CMD = 7 |
61 | |||
9037 | rgimad | 62 | AHCI_HBA_PxSSTS_DET = 0xF |
63 | AHCI_HBA_PORT_IPM_ACTIVE = 1 |
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64 | AHCI_HBA_PxSSTS_DET_PRESENT = 3 |
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65 | |||
9023 | rgimad | 66 | AHCI_MAX_PORTS = 32 ; |
9064 | rgimad | 67 | ;HBA_MEMORY_SIZE = 0x1100 |
9020 | rgimad | 68 | |
9139 | rgimad | 69 | AHCI_PORT_TIMEOUT = 1000000 |
70 | |||
9064 | rgimad | 71 | ; Frame Information Structure Types |
72 | FIS_TYPE_REG_H2D = 0x27 ; Register FIS - host to device |
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73 | FIS_TYPE_REG_D2H = 0x34 ; Register FIS - device to host |
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74 | FIS_TYPE_DMA_ACT = 0x39 ; DMA activate FIS - device to host |
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75 | FIS_TYPE_DMA_SETUP = 0x41 ; DMA setup FIS - bidirectional |
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76 | FIS_TYPE_DATA = 0x46 ; Data FIS - bidirectional |
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77 | FIS_TYPE_BIST = 0x58 ; BIST activate FIS - bidirectional |
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78 | FIS_TYPE_PIO_SETUP = 0x5F ; PIO setup FIS - device to host |
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79 | FIS_TYPE_DEV_BITS = 0xA1 ; Set device bits FIS - device to host |
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80 | |||
9020 | rgimad | 81 | struct AHCI_DATA |
82 | abar dd ? ; pointer to HBA Memory (BAR5) mapped to virtual kernelspace memory |
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83 | pcidev dd ? ; pointer to corresponding PCIDEV structure |
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84 | ends |
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85 | |||
86 | ; Generic Host Control registers |
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87 | struct HBA_MEM |
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9064 | rgimad | 88 | cap dd ? ; 0x00, Host capabilities |
89 | ghc dd ? ; 0x04, Global host control |
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90 | is dd ? ; 0x08, Interrupt status |
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91 | pi dd ? ; 0x0C, Port implemented |
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92 | version dd ? ; 0x10, Version |
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9020 | rgimad | 93 | ccc_ctl dd ? ; 0x14, Command completion coalescing control |
94 | ccc_pts dd ? ; 0x18, Command completion coalescing ports |
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95 | em_loc dd ? ; 0x1C, Enclosure management location |
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96 | em_ctl dd ? ; 0x20, Enclosure management control |
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9064 | rgimad | 97 | cap2 dd ? ; 0x24, Host capabilities extended |
9020 | rgimad | 98 | bohc dd ? ; 0x28, BIOS/OS handoff control and status |
9072 | rgimad | 99 | reserved rb (0xA0-HBA_MEM.reserved) ; 0x2C - 0x9F, Reserved |
100 | vendor rb (0x100-HBA_MEM.vendor) ; 0xA0 - 0xFF, Vendor specific |
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9023 | rgimad | 101 | ports rb (sizeof.HBA_PORT*AHCI_MAX_PORTS) ; 0x100 - 0x10FF, Port control registers, max AHCI_MAX_PORTS |
9020 | rgimad | 102 | ends |
103 | |||
104 | ; Port Control registers |
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105 | struct HBA_PORT |
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9064 | rgimad | 106 | command_list_base_l dd ? ; 0x00, command list base address, 1K-byte aligned |
107 | command_list_base_h dd ? ; 0x04, command list base address upper 32 bits, used on 64 bit systems |
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108 | fis_base_l dd ? ; 0x08, FIS base address, 256-byte aligned |
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109 | fis_base_h dd ? ; 0x0C, FIS base address upper 32 bits, used on 64 bit systems |
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110 | interrupt_status dd ? ; 0x10 |
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111 | interrupt_enable dd ? ; 0x14 |
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112 | command dd ? ; 0x18, command and status |
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113 | reserved0 dd ? ; 0x1C |
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114 | task_file_data dd ? ; 0x20 |
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115 | signature dd ? ; 0x24 |
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116 | sata_status dd ? ; 0x28, SATA status (SCR0:SStatus) |
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117 | sata_control dd ? ; 0x2C, SATA control (SCR2:SControl) |
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118 | sata_error dd ? ; 0x30, SATA error (SCR1:SError) |
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119 | sata_active dd ? ; 0x34, SATA active (SCR3:SActive) |
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120 | command_issue dd ? ; 0x38 |
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121 | sata_notification dd ? ; 0x3C, SATA notification (SCR4:SNotification) |
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122 | fis_based_switch_control dd ? ; 0x40 |
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123 | reserved1 rd 11 ; 0x44 - 0x6F |
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124 | vendor rd 4 ; 0x70 - 0x7F, vendor specific |
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9020 | rgimad | 125 | ends |
126 | |||
9074 | rgimad | 127 | ; Command header structure, size = 32 bytes |
9068 | rgimad | 128 | struct HBA_CMD_HDR |
9131 | rgimad | 129 | flags1 db ? ; 0bPWACCCCC, P - Prefetchable, W - Write (1: H2D, 0: D2H) |
9068 | rgimad | 130 | ; A - ATAPI, C - Command FIS length in DWORDS, 2 ~ 16 |
131 | |||
9131 | rgimad | 132 | flags2 db ? ; 0bPPPPRCB(Re), P - Port multiplier port, R - Reserved, |
9068 | rgimad | 133 | ; C - Clear busy upon R_OK, B - BIST, Re - Reset |
134 | |||
135 | prdtl dw ? ; Physical region descriptor table length in entries |
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136 | prdbc dd ? ; Physical region descriptor byte count transferred |
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137 | ctba dd ? ; Command table descriptor base address |
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138 | ctbau dd ? ; Command table descriptor base address upper 32 bits |
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9072 | rgimad | 139 | rd 4 ; Reserved |
9068 | rgimad | 140 | ends |
141 | |||
9074 | rgimad | 142 | ; Physical region descriptor table entry, size = 16 bytes |
9069 | rgimad | 143 | struct HBA_PRDT_ENTRY |
144 | dba dd ? ; Data base address |
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145 | dbau dd ? ; Data base address upper 32 bits |
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9072 | rgimad | 146 | dd ? ; Reserved |
9131 | rgimad | 147 | flags dd ? ; 0bIR..RD..D, I (1 bit) - Interrupt on completion, |
9069 | rgimad | 148 | ; R (9 bits) - Reserved, D (22 bits) - Byte count, 4M max |
149 | ends |
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150 | |||
151 | struct HBA_CMD_TBL |
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152 | cfis rb 64 ; 0x00, Command FIS |
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153 | acmd rb 16 ; 0x40, ATAPI command, 12 or 16 bytes |
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9072 | rgimad | 154 | rb 48 ; 0x50, Reserved |
9069 | rgimad | 155 | prdt_entry HBA_PRDT_ENTRY ; 0x80, Physical region descriptor table entries, 0 ~ 65535 |
156 | ; so, this structure is variable-length |
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157 | ends |
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158 | |||
9068 | rgimad | 159 | ; Contains virtual mappings for port phys memory regions |
160 | struct PORT_DATA |
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161 | clb dd ? ; Command list base |
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162 | fb dd ? ; FIS base |
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163 | ctba_arr rd 32 ; ctba_arr[0] = clb[0].ctba, ... and so on. |
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164 | port dd ? ; address of correspoding HBA_PORT structure |
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9074 | rgimad | 165 | portno dd ? ; port index, 0..31 |
9134 | rgimad | 166 | drive_type db ? ; drive type |
9140 | rgimad | 167 | sector_count dq ? ; number of sectors |
9068 | rgimad | 168 | ends |
169 | |||
9064 | rgimad | 170 | ; Register FIS – Host to Device |
171 | struct FIS_REG_H2D |
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172 | fis_type db ? ; FIS_TYPE_REG_H2D |
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9131 | rgimad | 173 | flags db ? ; 0bCRRRPPPP, C - 1: Command, 0: Control |
9064 | rgimad | 174 | ; R - Reserved, P - Port multiplier |
175 | |||
176 | command db ? ; Command register |
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177 | featurel db ? ; Feature register, 7:0 |
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178 | |||
179 | lba0 db ? ; LBA low register, 7:0 |
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180 | lba1 db ? ; LBA mid register, 15:8 |
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181 | lba2 db ? ; LBA high register, 23:16 |
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182 | device db ? ; Device register |
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183 | |||
184 | lba3 db ? ; LBA register, 31:24 |
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185 | lba4 db ? ; LBA register, 39:32 |
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186 | lba5 db ? ; LBA register, 47:40 |
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187 | featureh db ? ; Feature register, 15:8 |
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188 | |||
189 | countl db ? ; Count register, 7:0 |
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190 | counth db ? ; Count register, 15:8 |
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191 | icc db ? ; Isochronous command completion |
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192 | control db ? ; Control register |
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193 | |||
9072 | rgimad | 194 | rb 4 ; Reserved |
9064 | rgimad | 195 | ends |
196 | |||
197 | ; Register FIS – Device to Host |
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198 | struct FIS_REG_D2H |
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199 | fis_type db ? ; FIS_TYPE_REG_D2H |
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200 | |||
9131 | rgimad | 201 | flags db ? ; 0bRIRPPPP, P - Port multiplier, R - Reserved |
9064 | rgimad | 202 | ; I - Interrupt bit |
203 | |||
204 | status db ? ; Status register |
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205 | error db ? ; Error register |
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206 | |||
207 | lba0 db ? ; LBA low register, 7:0 |
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208 | lba1 db ? ; LBA mid register, 15:8 |
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209 | lba2 db ? ; LBA high register, 23:16 |
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210 | device db ? ; Device register |
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211 | |||
212 | lba3 db ? ; LBA register, 31:24 |
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213 | lba4 db ? ; LBA register, 39:32 |
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214 | lba5 db ? ; LBA register, 47:40 |
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9072 | rgimad | 215 | db ? ; Reserved |
9064 | rgimad | 216 | |
217 | countl db ? ; Count register, 7:0 |
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218 | counth db ? ; Count register, 15:8 |
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9072 | rgimad | 219 | rb 2 ; Reserved |
9064 | rgimad | 220 | |
9072 | rgimad | 221 | rb 4 ; Reserved |
9064 | rgimad | 222 | ends |
223 | |||
224 | ; Data FIS – Bidirectional |
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225 | struct FIS_DATA |
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226 | fis_type db ? ; FIS_TYPE_DATA |
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9131 | rgimad | 227 | flags db ? ; 0bRRRRPPPP, R - Reserved, P - Port multiplier |
9072 | rgimad | 228 | rb 2 ; Reserved |
9064 | rgimad | 229 | ; DWORD 1 ~ N (?) |
230 | data rd 1 ; Payload |
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231 | ends |
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232 | |||
233 | ; PIO Setup – Device to Host |
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234 | struct FIS_PIO_SETUP |
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235 | fis_type db ? ; FIS_TYPE_PIO_SETUP |
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236 | |||
9131 | rgimad | 237 | flags db ? ; 0bRIDRPPPP, P - Port multiplier, R - Reserved |
9064 | rgimad | 238 | ; I - Interrupt bit, D - Data transfer direction, 1 - device to host |
239 | |||
240 | status db ? ; Status register |
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241 | error db ? ; Error register |
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242 | |||
243 | lba0 db ? ; LBA low register, 7:0 |
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244 | lba1 db ? ; LBA mid register, 15:8 |
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245 | lba2 db ? ; LBA high register, 23:16 |
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246 | device db ? ; Device register |
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247 | |||
248 | lba3 db ? ; LBA register, 31:24 |
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249 | lba4 db ? ; LBA register, 39:32 |
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250 | lba5 db ? ; LBA register, 47:40 |
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9072 | rgimad | 251 | db ? ; Reserved |
9064 | rgimad | 252 | |
253 | countl db ? ; Count register, 7:0 |
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254 | counth db ? ; Count register, 15:8 |
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9072 | rgimad | 255 | db ? ; Reserved |
9064 | rgimad | 256 | e_status db ? ; New value of status register |
257 | |||
258 | tc dw ? ; Transfer count |
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9072 | rgimad | 259 | rb 2 ; Reserved |
9064 | rgimad | 260 | ends |
261 | |||
262 | ; DMA Setup – Device to Host |
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263 | struct FIS_DMA_SETUP |
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264 | fis_type db ? ; FIS_TYPE_DMA_SETUP |
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9131 | rgimad | 265 | flags db ? ; 0bAIDRPPPP, A - Auto-activate. Specifies if DMA Activate FIS is needed, |
9064 | rgimad | 266 | ; I - Interrupt bit, D - Data transfer direction, 1 - device to host, |
267 | ; R - Reserved, P - Port multiplier |
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268 | |||
9072 | rgimad | 269 | rb 2 ; Reserved |
9064 | rgimad | 270 | DMAbufferID dq ? ; DMA Buffer Identifier. |
271 | ; Used to Identify DMA buffer in host memory. |
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272 | ; SATA Spec says host specific and not in Spec. |
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273 | ; Trying AHCI spec might work. |
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274 | |||
9072 | rgimad | 275 | dd ? ; Reserved |
276 | DMAbufOffset dd ? ; Byte offset into buffer. First 2 bits must be 0 |
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9064 | rgimad | 277 | TransferCount dd ? ; Number of bytes to transfer. Bit 0 must be 0 |
9072 | rgimad | 278 | dd ? ; Reserved |
9064 | rgimad | 279 | ends |
280 | |||
281 | ; Set device bits FIS - device to host |
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282 | struct FIS_DEV_BITS |
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283 | fis_type db ? ; FIS_TYPE_DEV_BITS |
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9131 | rgimad | 284 | flags db ? ; 0bNIRRPPPP, N - Notification, I - Interrupt, |
9064 | rgimad | 285 | ; R - Reserved, P - Port multiplier |
286 | |||
287 | status db ? ; Status register |
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288 | error db ? ; Error register |
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289 | |||
290 | protocol dd ? ; Protocol |
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291 | ends |
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292 | |||
9069 | rgimad | 293 | struct HBA_FIS |
294 | dsfis FIS_DMA_SETUP ; 0x00, DMA Setup FIS |
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9072 | rgimad | 295 | rb 4 ; padding |
9069 | rgimad | 296 | |
297 | psfis FIS_PIO_SETUP ; 0x20, PIO Setup FIS |
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9072 | rgimad | 298 | rb 12 ; padding |
9069 | rgimad | 299 | |
300 | rfis FIS_REG_D2H ; 0x40, Register - Device to Host FIS |
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9072 | rgimad | 301 | rb 4 ; padding |
9069 | rgimad | 302 | |
303 | sdbfis FIS_DEV_BITS ; 0x58, Set Device Bit FIS |
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304 | |||
305 | ufis rb 64 ; 0x60 |
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306 | |||
9072 | rgimad | 307 | rb (0x100 - 0xA0) ; 0xA0, Reserved |
9069 | rgimad | 308 | ends |
309 | |||
9064 | rgimad | 310 | ; -------------------------------------------------- |
9020 | rgimad | 311 | uglobal |
312 | align 4 |
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313 | ahci_controller AHCI_DATA |
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9068 | rgimad | 314 | port_data_arr rb (sizeof.PORT_DATA*AHCI_MAX_PORTS) |
9140 | rgimad | 315 | ahci_mutex MUTEX |
9020 | rgimad | 316 | endg |
317 | |||
9140 | rgimad | 318 | iglobal |
319 | align 4 |
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320 | ahci_callbacks: |
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321 | dd ahci_callbacks.end - ahci_callbacks |
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322 | dd 0 ; no close function |
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323 | dd 0 ; no closemedia function |
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324 | dd ahci_querymedia |
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9141 | rgimad | 325 | dd 0;ahci_read |
9140 | rgimad | 326 | dd 0;ahci_write |
327 | dd 0 ; no flush function |
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328 | dd 0 ; use default cache size |
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329 | .end: |
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330 | hd_name db 'hd', 0, 0, 0 |
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331 | hd_counter dd 0 |
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332 | endg |
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333 | |||
9064 | rgimad | 334 | ; ----------------------------------------------------------------------- |
9020 | rgimad | 335 | ; detect ahci controller and initialize |
336 | align 4 |
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9068 | rgimad | 337 | ahci_init: |
9140 | rgimad | 338 | mov ecx, ahci_mutex |
339 | call mutex_init |
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340 | |||
9020 | rgimad | 341 | mov ecx, ahci_controller |
342 | mov esi, pcidev_list |
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343 | .find_ahci_ctr: |
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344 | mov esi, [esi + PCIDEV.fd] |
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345 | cmp esi, pcidev_list |
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346 | jz .ahci_ctr_not_found |
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347 | mov eax, [esi + PCIDEV.class] |
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348 | ;DEBUGF 1, "K: device class = %x\n", eax |
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349 | shr eax, 8 ; shift right because lowest 8 bits if ProgIf field |
||
350 | cmp eax, 0x0106 ; 0x01 - Mass Storage Controller class, 0x06 - Serial ATA Controller subclass |
||
351 | jz .ahci_ctr_found |
||
352 | jmp .find_ahci_ctr |
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353 | |||
354 | .ahci_ctr_not_found: |
||
355 | DEBUGF 1, "K: AHCI controller not found\n" |
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356 | ret |
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357 | |||
358 | .ahci_ctr_found: |
||
359 | mov [ahci_controller + AHCI_DATA.pcidev], esi |
||
360 | |||
361 | mov eax, [esi+PCIDEV.class] |
||
362 | movzx ebx, byte [esi+PCIDEV.bus] |
||
363 | movzx ecx, byte [esi+PCIDEV.devfn] |
||
364 | shr ecx, 3 ; get rid of 3 lowest bits (function code), the rest bits is device code |
||
365 | movzx edx, byte [esi+PCIDEV.devfn] |
||
366 | and edx, 00000111b ; get only 3 lowest bits (function code) |
||
367 | DEBUGF 1, "K: found AHCI controller, (class, subcl, progif) = %x, bus = %x, device = %x, function = %x\n", eax, ebx, ecx, edx |
||
368 | |||
9023 | rgimad | 369 | ; get BAR5 value, it is physical address |
9037 | rgimad | 370 | movzx ebx, [esi + PCIDEV.bus] |
371 | movzx ebp, [esi + PCIDEV.devfn] |
||
372 | stdcall pci_read32, ebx, ebp, PCI_REG_BAR5 |
||
373 | DEBUGF 1, "K: AHCI controller MMIO = %x\n", eax |
||
374 | mov edi, eax |
||
9020 | rgimad | 375 | |
9037 | rgimad | 376 | ; get the size of MMIO region |
377 | stdcall pci_write32, ebx, ebp, PCI_REG_BAR5, 0xFFFFFFFF |
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378 | stdcall pci_read32, ebx, ebp, PCI_REG_BAR5 |
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379 | not eax |
||
380 | inc eax |
||
381 | DEBUGF 1, "K: AHCI: MMIO region size = 0x%x bytes\n", eax |
||
382 | |||
383 | ; Map MMIO region to virtual memory |
||
384 | stdcall map_io_mem, edi, eax, PG_SWR + PG_NOCACHE |
||
9020 | rgimad | 385 | mov [ahci_controller + AHCI_DATA.abar], eax |
386 | DEBUGF 1, "K: AHCI controller BAR5 mapped to virtual addr %x\n", eax |
||
387 | |||
9037 | rgimad | 388 | ; Restore the original BAR5 value |
389 | stdcall pci_write32, ebx, ebp, PCI_REG_BAR5, edi |
||
390 | |||
9023 | rgimad | 391 | ; Enable dma bus mastering, memory space access, clear the "disable interrupts" bit |
392 | ; Usually, it is already done before us |
||
9024 | rgimad | 393 | movzx ebx, [esi + PCIDEV.bus] |
394 | movzx ebp, [esi + PCIDEV.devfn] |
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395 | stdcall pci_read32, ebx, ebp, PCI_REG_STATUS_COMMAND |
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9020 | rgimad | 396 | DEBUGF 1, "K: AHCI: pci_status_command = %x\nEnabling interrupts, DMA bus mastering and memory space access\n", eax |
397 | or eax, 0x06 ; pci.command |= 0x06 (dma bus mastering + memory space access) |
||
398 | btr eax, 10 ; clear the "disable interrupts" bit |
||
399 | DEBUGF 1, "K: AHCI: pci_status_command = %x\n", eax |
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9024 | rgimad | 400 | stdcall pci_write32, ebx, ebp, PCI_REG_STATUS_COMMAND, eax |
9020 | rgimad | 401 | |
9023 | rgimad | 402 | ; ; Print some register values to debug board |
403 | ; mov esi, [ahci_controller + AHCI_DATA.abar] |
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9064 | rgimad | 404 | ; DEBUGF 1, "K: AHCI: HBA.cap = %x, HBA.ghc = %x, HBA_MEM.version = %x\n", [esi + HBA_MEM.cap], [esi + HBA_MEM.ghc], [esi + HBA_MEM.version] |
9020 | rgimad | 405 | |
9023 | rgimad | 406 | ;------------------------------------------------------- |
407 | ; Request BIOS/OS ownership handoff, if supported. (TODO check correctness) |
||
408 | mov esi, [ahci_controller + AHCI_DATA.abar] |
||
9064 | rgimad | 409 | ;mov ebx, [esi + HBA_MEM.cap2] |
9023 | rgimad | 410 | ;DEBUGF 1, "K: AHCI: HBA_MEM.cap2 = %x\n", ebx |
9064 | rgimad | 411 | bt [esi + HBA_MEM.cap2], bit_AHCI_HBA_CAP2_BOH |
9020 | rgimad | 412 | jnc .end_handoff |
9023 | rgimad | 413 | DEBUGF 1, "K: AHCI: requesting AHCI ownership change...\n" |
9024 | rgimad | 414 | bts [esi + HBA_MEM.bohc], bit_AHCI_HBA_BOHC_OOS |
9020 | rgimad | 415 | |
416 | .wait_not_bos: |
||
9024 | rgimad | 417 | bt [esi + HBA_MEM.bohc], bit_AHCI_HBA_BOHC_BOS |
9020 | rgimad | 418 | jc .wait_not_bos |
419 | |||
420 | mov ebx, 3 |
||
421 | call delay_hs |
||
422 | |||
9023 | rgimad | 423 | ; if Bios Busy is still set after 30 mS, wait 2 seconds. |
9024 | rgimad | 424 | bt [esi + HBA_MEM.bohc], bit_AHCI_HBA_BOHC_BB |
9020 | rgimad | 425 | jnc @f |
426 | |||
427 | mov ebx, 200 |
||
428 | call delay_hs |
||
429 | @@: |
||
9023 | rgimad | 430 | DEBUGF 1, "K: AHCI: ownership change completed.\n" |
9020 | rgimad | 431 | |
432 | .end_handoff: |
||
9023 | rgimad | 433 | ;------------------------------------------------------- |
9020 | rgimad | 434 | |
9023 | rgimad | 435 | ; enable the AHCI and reset it |
9064 | rgimad | 436 | bts [esi + HBA_MEM.ghc], bit_AHCI_HBA_GHC_AHCI_ENABLE |
437 | bts [esi + HBA_MEM.ghc], bit_AHCI_HBA_GHC_RESET |
||
9020 | rgimad | 438 | |
9023 | rgimad | 439 | ; wait for reset to complete |
440 | .wait_reset: |
||
9064 | rgimad | 441 | bt [esi + HBA_MEM.ghc], bit_AHCI_HBA_GHC_RESET |
9023 | rgimad | 442 | jc .wait_reset |
9020 | rgimad | 443 | |
9023 | rgimad | 444 | ; enable the AHCI and interrupts |
9064 | rgimad | 445 | bts [esi + HBA_MEM.ghc], bit_AHCI_HBA_GHC_AHCI_ENABLE |
446 | bts [esi + HBA_MEM.ghc], bit_AHCI_HBA_GHC_INTERRUPT_ENABLE |
||
9023 | rgimad | 447 | mov ebx, 2 |
448 | call delay_hs |
||
449 | |||
9064 | rgimad | 450 | DEBUGF 1, "K: AHCI: caps: %x %x, ver: %x, ghc: %x, pi: %x\n", [esi + HBA_MEM.cap], [esi + HBA_MEM.cap2], [esi + HBA_MEM.version], [esi + HBA_MEM.ghc], [esi + HBA_MEM.pi] |
9020 | rgimad | 451 | |
9037 | rgimad | 452 | ; TODO: |
453 | ; calculate irq line |
||
454 | ; ahciHBA->ghc |= AHCI_GHC_IE; |
||
455 | ; IDT::RegisterInterruptHandler(irq, InterruptHandler); |
||
9064 | rgimad | 456 | ; ahciHBA->is = 0xffffffff; |
9037 | rgimad | 457 | |
9140 | rgimad | 458 | mov [hd_counter], 0 |
9037 | rgimad | 459 | xor ebx, ebx |
460 | .detect_drives: |
||
461 | cmp ebx, AHCI_MAX_PORTS |
||
462 | jae .end_detect_drives |
||
463 | |||
464 | ; if port with index ebx is not implemented then go to next |
||
9064 | rgimad | 465 | mov ecx, [esi + HBA_MEM.pi] |
9037 | rgimad | 466 | bt ecx, ebx |
467 | jnc .continue_detect_drives |
||
468 | |||
469 | mov edi, ebx |
||
9074 | rgimad | 470 | imul edi, sizeof.HBA_PORT |
9037 | rgimad | 471 | add edi, HBA_MEM.ports |
472 | add edi, esi |
||
473 | ; now edi - base of HBA_MEM.ports[ebx] |
||
474 | |||
9130 | rgimad | 475 | DEBUGF 1, "K: AHCI: port %d, cmd = %x, ssts = %x\n", ebx, [edi + HBA_PORT.command], [edi + HBA_PORT.sata_status] |
9037 | rgimad | 476 | |
9130 | rgimad | 477 | ; If port is not idle force it to be idle |
478 | mov eax, [edi + HBA_PORT.command] |
||
479 | and eax, (AHCI_HBA_PxCMD_ST or AHCI_HBA_PxCMD_CR or AHCI_HBA_PxCMD_FRE or AHCI_HBA_PxCMD_FR) |
||
480 | test eax, eax |
||
481 | jz @f |
||
482 | |||
483 | mov eax, edi |
||
484 | DEBUGF 1, "ahci_stop_cmd..\n" |
||
485 | call ahci_stop_cmd |
||
486 | @@: |
||
487 | ; TODO: what is purpose of this block of code ? |
||
488 | ; Reset port, disable slumber and partial state |
||
489 | ; mov [edi + HBA_PORT.sata_control], 0x301 |
||
490 | ; push ebx |
||
491 | ; mov ebx, 5 ; wait 50 ms |
||
492 | ; call delay_hs |
||
493 | ; pop ebx |
||
494 | ; mov [edi + HBA_PORT.sata_control], 0x300 |
||
495 | |||
496 | ; if(abar->cap & HBA_MEM_CAP_SSS) |
||
497 | ; { |
||
498 | ; abar->ports[i].cmd |= (HBA_PxCMD_SUD | HBA_PxCMD_POD | HBA_PxCMD_ICC); |
||
499 | ; Sleep(10); |
||
500 | ; } |
||
501 | ; rewritten to: |
||
502 | bt [esi + HBA_MEM.cap], 27 ; check Supports Staggered Spin-up bit in capabilities |
||
503 | jnc @f |
||
9134 | rgimad | 504 | DEBUGF 1, "Supports Staggered Spin-up, spinning up the port..\n" |
9130 | rgimad | 505 | or [edi + HBA_PORT.command], (0x0002 or 0x0004 or 0x10000000) |
506 | push ebx |
||
507 | mov ebx, 1 ; wait 10 ms |
||
508 | call delay_hs |
||
509 | pop ebx |
||
510 | @@: |
||
511 | ; Clear interrupt status and error status |
||
512 | mov [edi + HBA_PORT.sata_error], 0xFFFFFFFF |
||
513 | mov [edi + HBA_PORT.interrupt_status], 0xFFFFFFFF |
||
514 | |||
515 | ; ------------------------------------------ |
||
516 | |||
9037 | rgimad | 517 | mov ecx, [edi + HBA_PORT.sata_status] |
518 | shr ecx, 8 |
||
519 | and ecx, 0x0F |
||
520 | cmp ecx, AHCI_HBA_PORT_IPM_ACTIVE |
||
521 | jne .continue_detect_drives |
||
522 | |||
523 | mov ecx, [edi + HBA_PORT.sata_status] |
||
524 | and ecx, AHCI_HBA_PxSSTS_DET |
||
525 | cmp ecx, AHCI_HBA_PxSSTS_DET_PRESENT |
||
9068 | rgimad | 526 | jne .continue_detect_drives |
9037 | rgimad | 527 | |
9134 | rgimad | 528 | ; DEBUGF 1, "K: AHCI: found drive at port %d, cmd = 0x%x, ssts = 0x%x, signature = 0x%x\n", ebx, [edi + HBA_PORT.command], [edi + HBA_PORT.sata_status], [edi + HBA_PORT.signature] |
9037 | rgimad | 529 | |
9068 | rgimad | 530 | mov ecx, ebx |
9074 | rgimad | 531 | imul ecx, sizeof.PORT_DATA |
9068 | rgimad | 532 | add ecx, port_data_arr |
533 | stdcall ahci_port_rebase, edi, ebx, ecx |
||
534 | |||
9134 | rgimad | 535 | ; DEBUGF 1, "K: AHCI: After REBASING, signature = 0x%x\n", [edi + HBA_PORT.signature] |
536 | |||
9135 | rgimad | 537 | ; Determine drive type by checking port signature |
9134 | rgimad | 538 | .switch_sig: |
539 | cmp [edi + HBA_PORT.signature], SATA_SIG_ATA |
||
9135 | rgimad | 540 | mov eax, AHCI_DEV_SATA |
541 | jz .end_switch_sig |
||
542 | |||
9134 | rgimad | 543 | cmp [edi + HBA_PORT.signature], SATA_SIG_ATAPI |
9135 | rgimad | 544 | mov eax, AHCI_DEV_SATAPI |
545 | jz .end_switch_sig |
||
546 | |||
9134 | rgimad | 547 | cmp [edi + HBA_PORT.signature], SATA_SIG_SEMB |
9135 | rgimad | 548 | mov eax, AHCI_DEV_SEMB |
549 | jz .end_switch_sig |
||
550 | |||
9134 | rgimad | 551 | cmp [edi + HBA_PORT.signature], SATA_SIG_PM |
9135 | rgimad | 552 | mov eax, AHCI_DEV_PM |
553 | jz .end_switch_sig |
||
554 | |||
9134 | rgimad | 555 | DEBUGF 1, "Unknown device signature\n" |
9135 | rgimad | 556 | mov eax, AHCI_DEV_NULL |
9134 | rgimad | 557 | .end_switch_sig: |
9136 | rgimad | 558 | mov [ecx + PORT_DATA.drive_type], al |
9134 | rgimad | 559 | |
560 | DEBUGF 1, "K: AHCI: found drive on port %u: TYPE = %u\n", ebx, [ecx + PORT_DATA.drive_type] |
||
561 | |||
9074 | rgimad | 562 | stdcall ahci_port_identify, ecx |
563 | |||
9140 | rgimad | 564 | cmp [ecx + PORT_DATA.drive_type], AHCI_DEV_SATA |
565 | jne .after_add_disk ; skip adding disk code |
||
566 | ; register disk in system: |
||
9141 | rgimad | 567 | stdcall ahci_read_first_sector, ecx |
568 | |||
9140 | rgimad | 569 | push ecx edx |
570 | mov eax, [hd_counter] |
||
571 | xor edx, edx |
||
572 | mov ecx, 10 |
||
573 | div ecx ; eax = hd_counter / 10, edx = hd_counter % 10 |
||
574 | test eax, eax |
||
575 | jz .concat_one |
||
576 | add al, '0' |
||
577 | mov byte [hd_name + 2], al |
||
578 | add dl, '0' |
||
579 | mov byte [hd_name + 3], dl |
||
580 | jmp .endif1 |
||
581 | .concat_one: |
||
582 | add dl, '0' |
||
583 | mov byte [hd_name + 2], dl |
||
584 | .endif1: |
||
585 | pop edx ecx |
||
586 | |||
587 | DEBUGF 1, "adding '%s'\n", hd_name |
||
588 | |||
589 | stdcall disk_add, ahci_callbacks, hd_name, ecx, 0 |
||
590 | test eax, eax |
||
591 | jz .disk_add_fail |
||
592 | stdcall disk_media_changed, eax, 1 ; system will scan for partitions on disk |
||
9141 | rgimad | 593 | |
9140 | rgimad | 594 | jmp .after_add_disk |
595 | |||
596 | .disk_add_fail: |
||
597 | DEBUGF 1, "Failed to add disk\n" |
||
598 | .after_add_disk: |
||
599 | |||
9037 | rgimad | 600 | .continue_detect_drives: |
601 | inc ebx |
||
602 | jmp .detect_drives |
||
603 | |||
9064 | rgimad | 604 | |
9037 | rgimad | 605 | |
606 | .end_detect_drives: |
||
607 | |||
608 | |||
9020 | rgimad | 609 | ret |
9065 | rgimad | 610 | ; ------------------------------------------------- |
9020 | rgimad | 611 | |
9074 | rgimad | 612 | modelstr rb 42 |
613 | ; Identify drive on port ; TODO check |
||
614 | ; in: pdata - address of PORT_DATA structure |
||
615 | proc ahci_port_identify stdcall, pdata: dword |
||
616 | locals |
||
617 | cmdslot dd ? |
||
618 | cmdheader dd ? |
||
619 | cmdtable dd ? |
||
620 | buf_phys dd ? |
||
621 | buf_virt dd ? |
||
622 | endl |
||
623 | |||
624 | pushad |
||
625 | |||
626 | mov esi, [pdata] ; esi - address of PORT_DATA struct of port |
||
627 | mov edi, [esi + PORT_DATA.port] ; edi - address of HBA_PORT struct of port |
||
628 | |||
629 | mov eax, edi |
||
630 | call ahci_find_cmdslot |
||
631 | |||
632 | cmp eax, -1 |
||
633 | jne .cmdslot_found |
||
634 | |||
635 | DEBUGF 1, "No free cmdslot on port %u\n", [esi + PORT_DATA.portno] |
||
9140 | rgimad | 636 | jmp .ret |
9074 | rgimad | 637 | |
638 | .cmdslot_found: |
||
639 | mov [cmdslot], eax |
||
9134 | rgimad | 640 | ; DEBUGF 1, "Found free cmdslot %u on port %u\n", [cmdslot], [esi + PORT_DATA.portno] |
9074 | rgimad | 641 | |
642 | shl eax, BSF sizeof.HBA_CMD_HDR |
||
643 | add eax, [esi + PORT_DATA.clb] |
||
644 | mov [cmdheader], eax ; address of virtual mapping of command header |
||
645 | mov eax, [cmdslot] |
||
646 | mov eax, [esi + eax*4 + PORT_DATA.ctba_arr] |
||
647 | mov [cmdtable], eax ; address of virtual mapping of command table of command header |
||
648 | |||
649 | stdcall _memset, eax, 0, sizeof.HBA_CMD_TBL |
||
650 | |||
651 | call alloc_page |
||
652 | mov [buf_phys], eax |
||
653 | |||
654 | stdcall map_io_mem, eax, 4096, PG_NOCACHE + PG_SWR ; map to virt memory so we can work with it |
||
655 | mov [buf_virt], eax |
||
656 | |||
657 | mov eax, [cmdtable] |
||
658 | mov ebx, [buf_phys] |
||
659 | mov dword [eax + HBA_CMD_TBL.prdt_entry + HBA_PRDT_ENTRY.dba], ebx |
||
660 | mov dword [eax + HBA_CMD_TBL.prdt_entry + HBA_PRDT_ENTRY.dbau], 0 |
||
9131 | rgimad | 661 | and [eax + HBA_CMD_TBL.prdt_entry + HBA_PRDT_ENTRY.flags], not 0x3FFFFF ; zero out lower 22 bits, they used for byte count |
662 | or [eax + HBA_CMD_TBL.prdt_entry + HBA_PRDT_ENTRY.flags], 512 - 1 ; reason why -1 see in spec on this field |
||
663 | ; or [eax + HBA_CMD_TBL.prdt_entry + HBA_PRDT_ENTRY.flags], 1 shl 31 ; enable interrupt on completion |
||
664 | |||
9074 | rgimad | 665 | mov eax, [cmdheader] |
9131 | rgimad | 666 | and [eax + HBA_CMD_HDR.flags1], not 0x1F ; zero out lower 5 bits, they will be used for cfl |
667 | or [eax + HBA_CMD_HDR.flags1], (sizeof.FIS_REG_H2D / 4) ; set command fis length in dwords |
||
668 | movzx bx, [eax + HBA_CMD_HDR.flags1] |
||
669 | btr bx, 6 ; flag W = 0 |
||
670 | mov [eax + HBA_CMD_HDR.flags1], bl |
||
671 | movzx bx, [eax + HBA_CMD_HDR.flags2] |
||
672 | btr bx, 2 ; flag C = 0 |
||
673 | mov [eax + HBA_CMD_HDR.flags2], bl |
||
9074 | rgimad | 674 | mov [eax + HBA_CMD_HDR.prdtl], 1 |
675 | |||
676 | mov eax, [cmdtable] |
||
677 | mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.fis_type], FIS_TYPE_REG_H2D |
||
9131 | rgimad | 678 | movzx ebx, byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.flags] |
9074 | rgimad | 679 | bts ebx, bit_AHCI_H2D_FLAG_CMD ; Set Command bit in H2D FIS. |
9131 | rgimad | 680 | mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.flags], bl |
9134 | rgimad | 681 | |
682 | mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.command], ATA_IDENTIFY |
||
683 | cmp [esi + PORT_DATA.drive_type], AHCI_DEV_SATAPI |
||
684 | jne @f |
||
685 | mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.command], ATAPI_IDENTIFY |
||
686 | @@: |
||
9074 | rgimad | 687 | mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.device], 0 |
688 | |||
9139 | rgimad | 689 | ; Wait on previous command to complete, before issuing new command. |
690 | stdcall ahci_port_wait, edi, AHCI_PORT_TIMEOUT |
||
691 | ; DEBUGF 1, "eax = %x\n", eax |
||
692 | ; TODO check eax error value |
||
9074 | rgimad | 693 | |
694 | mov eax, [cmdslot] |
||
695 | bts [edi + HBA_PORT.command_issue], eax ; Issue the command |
||
696 | |||
9139 | rgimad | 697 | ; Wait for command completion |
698 | stdcall ahci_port_cmd_wait, edi, eax;, AHCI_PORT_CMD_TIMEOUT |
||
699 | ; DEBUGF 1, " eax = %x\n", eax |
||
700 | ; TODO check eax error value |
||
9074 | rgimad | 701 | |
9134 | rgimad | 702 | ; DEBUGF 1, "sata_error register = 0x%x\n", [edi + HBA_PORT.sata_error] |
9130 | rgimad | 703 | |
704 | mov esi, [buf_virt] |
||
9074 | rgimad | 705 | add esi, 27*2 |
706 | mov edi, modelstr |
||
707 | mov ecx, ((46-27)+1)*2 |
||
708 | cld |
||
709 | rep movsb |
||
710 | mov byte [edi], 0 |
||
711 | |||
9138 | rgimad | 712 | stdcall swap_bytes_in_words, modelstr, (46-27)+1 |
9131 | rgimad | 713 | DEBUGF 1, "IDENTIFICATION RESULT: MODEL = %s\n", modelstr |
9074 | rgimad | 714 | |
9138 | rgimad | 715 | mov esi, [buf_virt] |
716 | mov eax, [esi + 200] |
||
717 | mov edx, [esi + 200 + 4] |
||
718 | DEBUGF 1, "lba48 mode sector count = 0x%x:%x\n", edx, eax |
||
719 | |||
720 | shrd eax, edx, 11 ; i.e *512 / 1024 / 1024, 512 - sector size |
||
721 | DEBUGF 1, "disk capacity = %u MiB ", eax |
||
722 | shrd eax, edx, 10 ; / 1024 |
||
723 | DEBUGF 1, "= %u GiB\n", eax |
||
9074 | rgimad | 724 | .ret: |
725 | popad |
||
726 | ret |
||
727 | endp |
||
728 | |||
9140 | rgimad | 729 | proc ahci_querymedia stdcall, pdata, mediainfo |
730 | push ecx edx |
||
731 | mov eax, [mediainfo] |
||
732 | mov edx, [pdata] |
||
733 | mov [eax + DISKMEDIAINFO.Flags], 0 |
||
734 | mov [eax + DISKMEDIAINFO.SectorSize], 512 |
||
735 | mov ecx, dword[edx + PORT_DATA.sector_count] |
||
736 | mov dword [eax + DISKMEDIAINFO.Capacity], ecx |
||
737 | mov ecx, dword[edx + PORT_DATA.sector_count + 4] |
||
738 | mov dword [eax + DISKMEDIAINFO.Capacity + 4], ecx |
||
739 | pop edx ecx |
||
740 | xor eax, eax |
||
741 | ret |
||
742 | endp |
||
9134 | rgimad | 743 | |
9141 | rgimad | 744 | ;------------------------TEST------------------------------- |
745 | |||
746 | proc ahci_read_first_sector stdcall pdata: dword |
||
9140 | rgimad | 747 | locals |
748 | cmdslot dd ? |
||
749 | cmdheader dd ? |
||
750 | cmdtable dd ? |
||
9141 | rgimad | 751 | buf_phys dd ? |
752 | buf_virt dd ? |
||
753 | ;numsectors dd ? |
||
9140 | rgimad | 754 | endl |
755 | |||
756 | pushad |
||
757 | mov ecx, ahci_mutex |
||
758 | call mutex_lock |
||
759 | |||
760 | mov esi, [pdata] ; esi - address of PORT_DATA struct of port |
||
761 | mov edi, [esi + PORT_DATA.port] ; edi - address of HBA_PORT struct of port |
||
762 | mov eax, edi |
||
763 | call ahci_find_cmdslot |
||
764 | cmp eax, -1 |
||
765 | jne .cmdslot_found |
||
766 | |||
767 | DEBUGF 1, "No free cmdslot on port %u\n", [esi + PORT_DATA.portno] |
||
768 | jmp .ret |
||
769 | |||
770 | .cmdslot_found: |
||
771 | mov [cmdslot], eax |
||
9141 | rgimad | 772 | DEBUGF 1, "Found free cmdslot %u on port %u\n", [cmdslot], [esi + PORT_DATA.portno] |
9140 | rgimad | 773 | |
774 | shl eax, BSF sizeof.HBA_CMD_HDR |
||
775 | add eax, [esi + PORT_DATA.clb] |
||
776 | mov [cmdheader], eax ; address of virtual mapping of command header |
||
777 | mov eax, [cmdslot] |
||
778 | mov eax, [esi + eax*4 + PORT_DATA.ctba_arr] |
||
779 | mov [cmdtable], eax ; address of virtual mapping of command table of command header |
||
780 | |||
781 | mov eax, [cmdheader] |
||
782 | and [eax + HBA_CMD_HDR.flags1], not 0x1F ; zero out lower 5 bits, they will be used for cfl |
||
783 | or [eax + HBA_CMD_HDR.flags1], (sizeof.FIS_REG_H2D / 4) ; set command fis length in dwords |
||
784 | movzx bx, [eax + HBA_CMD_HDR.flags1] |
||
785 | btr bx, 6 ; flag W = 0 |
||
786 | mov [eax + HBA_CMD_HDR.flags1], bl |
||
787 | movzx bx, [eax + HBA_CMD_HDR.flags2] |
||
788 | btr bx, 2 ; flag C = 0 |
||
789 | mov [eax + HBA_CMD_HDR.flags2], bl |
||
790 | |||
9141 | rgimad | 791 | mov [eax + HBA_CMD_HDR.prdtl], 1 |
9140 | rgimad | 792 | |
9141 | rgimad | 793 | ; zero out the command table |
794 | stdcall _memset, [cmdtable], 0, sizeof.HBA_CMD_TBL |
||
9140 | rgimad | 795 | |
796 | DEBUGF 1, " prdtl = %u\n", [eax + HBA_CMD_HDR.prdtl]:2 |
||
797 | |||
9141 | rgimad | 798 | call alloc_page |
799 | mov [buf_phys], eax |
||
9140 | rgimad | 800 | |
9141 | rgimad | 801 | stdcall map_io_mem, eax, 4096, PG_NOCACHE + PG_SWR ; map to virt memory so we can work with it |
802 | mov [buf_virt], eax |
||
9140 | rgimad | 803 | |
9141 | rgimad | 804 | mov eax, [cmdtable] |
805 | mov ebx, [buf_phys] |
||
806 | DEBUGF 1, "DBA = 0x%x\n", ebx |
||
807 | mov [eax + HBA_CMD_TBL.prdt_entry + HBA_PRDT_ENTRY.dba], ebx |
||
808 | mov [eax + HBA_CMD_TBL.prdt_entry + HBA_PRDT_ENTRY.dbau], 0 |
||
809 | and [eax + HBA_CMD_TBL.prdt_entry + HBA_PRDT_ENTRY.flags], not 0x3FFFFF ; zero out lower 22 bits, they used for byte count |
||
810 | or [eax + HBA_CMD_TBL.prdt_entry + HBA_PRDT_ENTRY.flags], 512 - 1 ; reason why -1 see in spec on this field |
||
9140 | rgimad | 811 | ; or [eax + HBA_CMD_TBL.prdt_entry + HBA_PRDT_ENTRY.flags], 1 shl 31 ; enable interrupt on completion |
812 | |||
813 | mov eax, [cmdtable] |
||
814 | mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.fis_type], FIS_TYPE_REG_H2D |
||
815 | movzx ebx, byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.flags] |
||
816 | bts ebx, bit_AHCI_H2D_FLAG_CMD ; Set Command bit in H2D FIS. |
||
817 | mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.flags], bl |
||
818 | |||
819 | mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.command], ATA_CMD_READ_DMA_EX |
||
820 | |||
9141 | rgimad | 821 | mov ebx, 0 ; start sector is 0 |
9140 | rgimad | 822 | mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.lba0], bl |
823 | mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.lba1], bl |
||
824 | mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.lba2], bl |
||
825 | mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.device], 1 shl 6 ; LBA mode |
||
826 | mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.lba3], bl |
||
827 | mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.lba4], bl |
||
828 | mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.lba5], bl |
||
829 | |||
9141 | rgimad | 830 | ; num sectors to read = 1 |
831 | mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.countl], 1 |
||
832 | mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.counth], 0 |
||
9140 | rgimad | 833 | |
9141 | rgimad | 834 | ;mov eax, [cmdheader] |
835 | ;DEBUGF 1, "PRDBC = %u\n", [eax + HBA_CMD_HDR.prdbc] |
||
836 | |||
9140 | rgimad | 837 | ; Wait on previous command to complete, before issuing new command. |
838 | stdcall ahci_port_wait, edi, AHCI_PORT_TIMEOUT |
||
839 | |||
840 | mov eax, [cmdslot] |
||
841 | bts [edi + HBA_PORT.command_issue], eax ; Issue the command |
||
842 | |||
9141 | rgimad | 843 | ; mov ebx, 20 |
844 | ; call delay_hs |
||
9140 | rgimad | 845 | ; Wait for command completion |
846 | stdcall ahci_port_cmd_wait, edi, eax;, AHCI_PORT_CMD_TIMEOUT |
||
847 | |||
848 | DEBUGF 1, "sata_error register = 0x%x\n", [edi + HBA_PORT.sata_error] |
||
849 | |||
850 | DEBUGF 1, "reading completed\n" |
||
851 | |||
9141 | rgimad | 852 | ;mov eax, [cmdheader] |
853 | ;DEBUGF 1, "PRDBC = %u\n", [eax + HBA_CMD_HDR.prdbc] |
||
854 | |||
9140 | rgimad | 855 | xor ecx, ecx |
9141 | rgimad | 856 | mov esi, [buf_virt] |
9140 | rgimad | 857 | .print_data: |
858 | cmp ecx, 512 |
||
859 | jae .end_print_data |
||
860 | |||
861 | mov al, byte [esi + ecx] |
||
9141 | rgimad | 862 | mov byte [tmpstr2], al |
863 | mov byte [tmpstr2 + 1], 0 |
||
864 | DEBUGF 1, "0x%x(%s) ", al:2, tmpstr2 |
||
9140 | rgimad | 865 | |
866 | inc ecx |
||
867 | jmp .print_data |
||
868 | .end_print_data: |
||
869 | DEBUGF 1, "\n" |
||
870 | |||
871 | .ret: |
||
872 | mov ecx, ahci_mutex |
||
873 | call mutex_unlock |
||
874 | |||
875 | popad |
||
876 | xor eax, eax |
||
877 | ret |
||
878 | endp |
||
9141 | rgimad | 879 | tmpstr2 rb 16 |
880 | ;---------------------------------------------------------- |
||
9140 | rgimad | 881 | |
9065 | rgimad | 882 | ; Start command engine |
883 | ; in: eax - address of HBA_PORT structure |
||
9068 | rgimad | 884 | ahci_start_cmd: |
9065 | rgimad | 885 | .wait_cr: ; Wait until CR (bit15) is cleared |
886 | bt [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_CR |
||
887 | jc .wait_cr |
||
888 | |||
889 | ; Set FRE (bit4) and ST (bit0) |
||
890 | bts [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_FRE |
||
891 | bts [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_ST |
||
9068 | rgimad | 892 | ; maybe here call ahci flush cmd ? TODO (see seakernel) |
9065 | rgimad | 893 | ret |
894 | |||
895 | ; Stop command engine |
||
896 | ; in: eax - address of HBA_PORT structure |
||
9068 | rgimad | 897 | ahci_stop_cmd: |
9065 | rgimad | 898 | btr [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_ST ; Clear ST (bit0) |
899 | btr [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_FRE ; Clear FRE (bit4) |
||
900 | .wait_fr_cr: ; Wait until FR (bit14), CR (bit15) are cleared |
||
901 | bt [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_FR |
||
902 | jc .wait_fr_cr |
||
903 | bt [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_CR |
||
904 | jc .wait_fr_cr |
||
905 | |||
906 | ret |
||
907 | |||
9139 | rgimad | 908 | ; waits until the port is no longer busy before issuing a new command |
909 | ; in: [port] - address of HBA_PORT structure |
||
910 | ; [timeout] - timeout (in iterations) |
||
911 | ; out: eax = 0 if success, 1 if timeout expired |
||
912 | proc ahci_port_wait stdcall, port: dword, timeout: dword |
||
913 | push ebx ecx |
||
914 | mov ebx, [port] |
||
915 | xor ecx, ecx |
||
916 | .wait: |
||
917 | cmp ecx, [timeout] |
||
918 | jae .wait_end |
||
919 | mov eax, [ebx + HBA_PORT.task_file_data] |
||
920 | and eax, ATA_DEV_BUSY or ATA_DEV_DRQ |
||
921 | test eax, eax |
||
922 | jz .wait_end |
||
923 | inc ecx |
||
924 | jmp .wait |
||
925 | .wait_end: |
||
926 | xor eax, eax |
||
927 | DEBUGF 1, "port wait counter = %u\n", ecx |
||
928 | cmp ecx, [timeout] ; if they equal it means port is hung |
||
929 | setz al |
||
930 | pop ecx ebx |
||
9068 | rgimad | 931 | ret |
9139 | rgimad | 932 | endp |
9065 | rgimad | 933 | |
934 | |||
9139 | rgimad | 935 | ; Wait for command completion |
936 | ; in: [port] - address of HBA_PORT structure |
||
937 | ; [cmdslot] - number of command slot |
||
938 | ; out: eax = 0 if success, 1 if error |
||
939 | proc ahci_port_cmd_wait stdcall, port: dword, cmdslot: dword ;, timeout: dword |
||
940 | push ebx ecx edx |
||
941 | mov ebx, [port] |
||
942 | mov edx, [cmdslot] |
||
943 | xor eax, eax |
||
944 | xor ecx, ecx |
||
945 | .wait: |
||
946 | bt [ebx + HBA_PORT.command_issue], edx |
||
947 | jnc .wait_end |
||
948 | bt [ebx + HBA_PORT.interrupt_status], bit_AHCI_HBA_PxIS_TFES ; check for Task File Error |
||
949 | jc .error |
||
950 | inc ecx |
||
951 | jmp .wait |
||
952 | .wait_end: |
||
953 | DEBUGF 1, "port cmd wait counter = %u\n", ecx |
||
954 | bt [ebx + HBA_PORT.interrupt_status], bit_AHCI_HBA_PxIS_TFES ; check for Task File Error |
||
955 | jc .error |
||
956 | jmp .ret |
||
957 | .error: |
||
958 | mov eax, 1 |
||
959 | .ret: |
||
960 | pop edx ecx ebx |
||
9068 | rgimad | 961 | ret |
9139 | rgimad | 962 | endp |
9065 | rgimad | 963 | |
9139 | rgimad | 964 | ; ; The commands may not take effect until the command |
965 | ; ; register is read again by software, because reasons. |
||
966 | ; ; in: eax - address of HBA_PORT structure |
||
967 | ; ; out: eax - command register value |
||
968 | ; ahci_flush_cmd: |
||
969 | ; mov eax, [eax + HBA_PORT.command] |
||
970 | ; ret |
||
971 | |||
972 | ; ; Send command to port |
||
973 | ; ; in: eax - address of HBA_PORT structure |
||
974 | ; ; ebx - index of command slot |
||
975 | ; ahci_send_cmd: |
||
976 | ; push ecx |
||
977 | ; mov [eax + HBA_PORT.interrupt_status], 0xFFFFFFFF |
||
978 | |||
979 | ; mov cl, bl |
||
980 | ; mov [eax + HBA_PORT.command_issue], 1 |
||
981 | ; shl [eax + HBA_PORT.command_issue], cl |
||
982 | |||
983 | ; call ahci_flush_cmd |
||
984 | ; pop ecx |
||
985 | ; ret |
||
986 | |||
9068 | rgimad | 987 | ; --------------------------------------------------------------------------- |
988 | ; in: port - address of HBA_PORT structure |
||
989 | ; portno - port index (0..31) |
||
990 | ; pdata - address of PORT_DATA structure |
||
991 | proc ahci_port_rebase stdcall, port: dword, portno: dword, pdata: dword |
||
992 | locals |
||
993 | phys_page1 dd ? |
||
994 | virt_page1 dd ? |
||
995 | phys_page23 dd ? |
||
996 | virt_page23 dd ? |
||
997 | tmp dd ? |
||
998 | endl |
||
999 | |||
1000 | pushad |
||
1001 | |||
1002 | DEBUGF 1, "Rebasing port %u\n", [portno] |
||
1003 | |||
1004 | mov eax, [port] |
||
1005 | call ahci_stop_cmd |
||
1006 | |||
1007 | ; Command list entry size = 32 |
||
1008 | ; Command list entry maxim count = 32 |
||
1009 | ; Command list maxim size = 32*32 = 1K per port |
||
1010 | call alloc_page |
||
1011 | mov [phys_page1], eax |
||
1012 | |||
1013 | stdcall map_io_mem, eax, 4096, PG_NOCACHE + PG_SWR ; map to virt memory so we can work with it |
||
1014 | mov [virt_page1], eax |
||
1015 | |||
1016 | mov esi, [port] |
||
1017 | mov ebx, [phys_page1] |
||
1018 | mov [esi + HBA_PORT.command_list_base_l], ebx ; set the command list base |
||
1019 | mov [esi + HBA_PORT.command_list_base_h], 0 ; zero upper 32 bits of addr cause we are 32 bit os |
||
1020 | |||
1021 | mov edi, [pdata] |
||
1022 | mov ebx, [virt_page1] |
||
1023 | mov [edi + PORT_DATA.clb], ebx ; set pdata->clb |
||
1024 | |||
1025 | mov eax, [port] |
||
1026 | mov [edi + PORT_DATA.port], eax ; set pdata->port |
||
9074 | rgimad | 1027 | mov eax, [portno] ; set pdata->portno |
1028 | mov [edi + PORT_DATA.portno], eax |
||
9068 | rgimad | 1029 | |
1030 | stdcall _memset, ebx, 0, 1024 ; zero out the command list |
||
1031 | |||
1032 | ; FIS entry size = 256 bytes per port |
||
1033 | mov eax, [phys_page1] |
||
1034 | add eax, 1024 |
||
1035 | mov [esi + HBA_PORT.fis_base_l], eax |
||
1036 | mov [esi + HBA_PORT.fis_base_h], 0 |
||
1037 | |||
1038 | mov eax, [virt_page1] |
||
1039 | add eax, 1024 |
||
1040 | mov [edi + PORT_DATA.fb], eax ; set pdata->fb |
||
1041 | stdcall _memset, eax, 0, 256 ; zero out |
||
1042 | |||
1043 | stdcall alloc_pages, 2 |
||
1044 | mov [phys_page23], eax |
||
1045 | stdcall map_io_mem, eax, 2*4096, PG_NOCACHE + PG_SWR |
||
1046 | mov [virt_page23], eax |
||
1047 | |||
1048 | ; Command table size = 256*32 = 8K per port |
||
1049 | mov edx, [edi + PORT_DATA.clb] ; cmdheader array base |
||
1050 | xor ecx, ecx |
||
1051 | |||
1052 | .for1: |
||
1053 | cmp ecx, 32 |
||
1054 | jae .for1_end |
||
1055 | |||
1056 | mov ebx, ecx |
||
1057 | shl ebx, BSF sizeof.HBA_CMD_HDR |
||
1058 | add ebx, edx ; ebx = cmdheader[ecx] |
||
1059 | |||
1060 | mov [ebx + HBA_CMD_HDR.prdtl], 8 ; 8 prdt entries per command table |
||
1061 | |||
1062 | ; 256 bytes per command table, 64+16+48+16*8 |
||
1063 | |||
1064 | push edx |
||
1065 | |||
1066 | ; cmdheader[ecx].ctba = phys_page23 + ecx*256 |
||
1067 | mov [ebx + HBA_CMD_HDR.ctba], ecx |
||
1068 | shl [ebx + HBA_CMD_HDR.ctba], BSF 256 ; *= 256 |
||
1069 | mov eax, [ebx + HBA_CMD_HDR.ctba] |
||
1070 | mov edx, [phys_page23] |
||
1071 | add [ebx + HBA_CMD_HDR.ctba], edx |
||
1072 | |||
1073 | add eax, [virt_page23] |
||
1074 | mov [tmp], eax ; tmp = virt_page23 + ecx*256 |
||
9069 | rgimad | 1075 | lea eax, [ecx*4 + edi + PORT_DATA.ctba_arr] ; eax = pdata->ctba_arr[ecx] |
9068 | rgimad | 1076 | mov edx, [tmp] |
1077 | mov [eax], edx ; pdata->ctba_arr[ecx] = virt_page23 + ecx*256 |
||
1078 | |||
1079 | pop edx |
||
1080 | |||
1081 | mov [ebx + HBA_CMD_HDR.ctbau], 0 |
||
1082 | stdcall _memset, [eax], 0, 256 ; zero out |
||
1083 | |||
1084 | inc ecx |
||
1085 | jmp .for1 |
||
1086 | .for1_end: |
||
1087 | |||
1088 | mov eax, [port] |
||
1089 | call ahci_start_cmd |
||
1090 | |||
1091 | DEBUGF 1, "End rebasing port %u\n", [portno] |
||
1092 | popad |
||
1093 | ret |
||
1094 | endp |
||
1095 | |||
9069 | rgimad | 1096 | ; ----------------------------------------------------------- ; TODO check |
1097 | ; Find a free command list slot |
||
1098 | ; in: eax - address of HBA_PORT structure |
||
1099 | ; out: eax - if not found -1, else slot index |
||
1100 | ahci_find_cmdslot: |
||
1101 | push ebx ecx edx esi |
||
1102 | ; If not set in SACT and CI, the slot is free |
||
1103 | mov ebx, [eax + HBA_PORT.sata_active] |
||
1104 | or ebx, [eax + HBA_PORT.command_issue] ; ebx = slots |
||
9068 | rgimad | 1105 | |
9069 | rgimad | 1106 | mov esi, [ahci_controller + AHCI_DATA.abar] |
1107 | mov edx, [esi + HBA_MEM.cap] |
||
1108 | shr edx, 8 |
||
1109 | and edx, 0xf |
||
9134 | rgimad | 1110 | ; DEBUGF 1, "Number of Command Slots on each port = %u\n", edx |
9069 | rgimad | 1111 | xor ecx, ecx |
1112 | .for1: |
||
1113 | cmp ecx, edx |
||
1114 | jae .for1_end |
||
9068 | rgimad | 1115 | |
9069 | rgimad | 1116 | ; if ((slots&1) == 0) return i; |
1117 | bt ebx, 0 |
||
1118 | jc .cont1 |
||
1119 | |||
1120 | mov eax, ecx |
||
1121 | jmp .ret |
||
1122 | |||
1123 | .cont1: |
||
1124 | shr ebx, 1 |
||
1125 | inc ecx |
||
1126 | jmp .for1 |
||
1127 | .for1_end: |
||
1128 | DEBUGF 1, "Cannot find free command list entry\n" |
||
1129 | mov eax, -1 |
||
1130 | .ret: |
||
1131 | pop esi edx ecx ebx |
||
1132 | ret |
||
1133 | |||
1134 | |||
9068 | rgimad | 1135 | proc _memset stdcall, dest:dword, val:byte, cnt:dword ; doesnt clobber any registers |
1136 | ;DEBUGF DBG_INFO, "memset(%x, %u, %u)\n", [dest], [val], [cnt] |
||
1137 | push eax ecx edi |
||
1138 | mov edi, dword [dest] |
||
1139 | mov al, byte [val] |
||
1140 | mov ecx, dword [cnt] |
||
9069 | rgimad | 1141 | rep stosb |
9068 | rgimad | 1142 | pop edi ecx eax |
1143 | ret |
||
1144 | endp |
||
9138 | rgimad | 1145 | |
1146 | ; Swaps byte order in words |
||
1147 | ; base - address of first word |
||
1148 | ; len - how many words to swap bytes in |
||
1149 | ; doesnt clobber any registers |
||
1150 | proc swap_bytes_in_words stdcall, base: dword, len: dword |
||
1151 | push eax ebx ecx |
||
1152 | xor ecx, ecx |
||
1153 | mov ebx, [base] |
||
1154 | .loop: |
||
1155 | cmp ecx, [len] |
||
1156 | jae .loop_end |
||
1157 | mov ax, word [ebx + ecx*2] |
||
1158 | xchg ah, al |
||
1159 | mov word [ebx + ecx*2], ax |
||
1160 | inc ecx |
||
1161 | jmp .loop |
||
1162 | .loop_end: |
||
1163 | pop ecx ebx eax |
||
1164 | ret |
||
1165 | endp |