WebSVN – Kolibri OS – Blame – /kernel/branches/kolibri-ahci/blkdev/ahci.inc

Rev	Author	Line No.	Line
9020	rgimad	1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		2	;; ;;
		3	;; Copyright (C) KolibriOS team 2004-2021. All rights reserved. ;;
		4	;; Distributed under terms of the GNU General Public License ;;
		5	;; ;;
		6	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		7
		8	$Revision$
		9
		10	PCI_REG_STATUS_COMMAND = 0x0004
		11	PCI_REG_BAR5 = 0x0024
		12
9134	rgimad	13	; different SATA device signatures
		14	SATA_SIG_ATA = 0x00000101 ; SATA drive
		15	SATA_SIG_ATAPI = 0xEB140101 ; SATAPI drive
		16	SATA_SIG_SEMB = 0xC33C0101 ; Enclosure management bridge
		17	SATA_SIG_PM = 0x96690101 ; Port multiplier
		18
		19	; Device type constants
		20	AHCI_DEV_NULL = 0
		21	AHCI_DEV_SATA = 1
		22	AHCI_DEV_SEMB = 2
		23	AHCI_DEV_PM = 3
		24	AHCI_DEV_SATAPI = 4
		25
		26	; ATA commands
9140	rgimad	27	ATA_IDENTIFY = 0xEC
		28	ATA_CMD_READ_DMA_EX = 0x25
9134	rgimad	29
9139	rgimad	30	; ATA constants
		31	ATA_DEV_BUSY = 0x80
		32	ATA_DEV_DRQ = 0x08
		33
9134	rgimad	34	; ATAPI commands
		35	ATAPI_IDENTIFY = 0xA1
		36
9023	rgimad	37	; bit_ prefix means that its index of bit
		38	; format: bit_AHCI_STR_REG_BIT
		39	bit_AHCI_HBA_CAP2_BOH = 0 ; Supports BIOS/OS Handoff
9020	rgimad	40
9023	rgimad	41	bit_AHCI_HBA_BOHC_BOS = 0 ; BIOS-Owned Semaphore (BIOS owns controller)
		42	bit_AHCI_HBA_BOHC_OOS = 1 ; OS-Owned Semaphore (OS owns controller)
		43	bit_AHCI_HBA_BOHC_BB = 4 ; BIOS Busy (polling bit while BIOS cleans up
9020	rgimad	44
9023	rgimad	45	bit_AHCI_HBA_GHC_AHCI_ENABLE = 31 ; Enable AHCI mode
		46	bit_AHCI_HBA_GHC_RESET = 0 ; Reset HBA
		47	bit_AHCI_HBA_GHC_INTERRUPT_ENABLE = 1 ; Enable interrupts from the HBA
		48
9065	rgimad	49	bit_AHCI_HBA_PxCMD_ST = 0
		50	bit_AHCI_HBA_PxCMD_FRE = 4
		51	bit_AHCI_HBA_PxCMD_FR = 14
		52	bit_AHCI_HBA_PxCMD_CR = 15
9139	rgimad	53	bit_AHCI_HBA_PxIS_TFES = 30
9065	rgimad	54
9130	rgimad	55	AHCI_HBA_PxCMD_ST = 1 shl 0
		56	AHCI_HBA_PxCMD_FRE = 1 shl 4
		57	AHCI_HBA_PxCMD_FR = 1 shl 14
		58	AHCI_HBA_PxCMD_CR = 1 shl 15
		59
9074	rgimad	60	bit_AHCI_H2D_FLAG_CMD = 7
		61
9037	rgimad	62	AHCI_HBA_PxSSTS_DET = 0xF
		63	AHCI_HBA_PORT_IPM_ACTIVE = 1
		64	AHCI_HBA_PxSSTS_DET_PRESENT = 3
		65
9023	rgimad	66	AHCI_MAX_PORTS = 32 ;
9064	rgimad	67	;HBA_MEMORY_SIZE = 0x1100
9020	rgimad	68
9139	rgimad	69	AHCI_PORT_TIMEOUT = 1000000
		70
9064	rgimad	71	; Frame Information Structure Types
		72	FIS_TYPE_REG_H2D = 0x27 ; Register FIS - host to device
		73	FIS_TYPE_REG_D2H = 0x34 ; Register FIS - device to host
		74	FIS_TYPE_DMA_ACT = 0x39 ; DMA activate FIS - device to host
		75	FIS_TYPE_DMA_SETUP = 0x41 ; DMA setup FIS - bidirectional
		76	FIS_TYPE_DATA = 0x46 ; Data FIS - bidirectional
		77	FIS_TYPE_BIST = 0x58 ; BIST activate FIS - bidirectional
		78	FIS_TYPE_PIO_SETUP = 0x5F ; PIO setup FIS - device to host
		79	FIS_TYPE_DEV_BITS = 0xA1 ; Set device bits FIS - device to host
		80
9020	rgimad	81	struct AHCI_DATA
		82	abar dd ? ; pointer to HBA Memory (BAR5) mapped to virtual kernelspace memory
		83	pcidev dd ? ; pointer to corresponding PCIDEV structure
		84	ends
		85
		86	; Generic Host Control registers
		87	struct HBA_MEM
9064	rgimad	88	cap dd ? ; 0x00, Host capabilities
		89	ghc dd ? ; 0x04, Global host control
		90	is dd ? ; 0x08, Interrupt status
		91	pi dd ? ; 0x0C, Port implemented
		92	version dd ? ; 0x10, Version
9020	rgimad	93	ccc_ctl dd ? ; 0x14, Command completion coalescing control
		94	ccc_pts dd ? ; 0x18, Command completion coalescing ports
		95	em_loc dd ? ; 0x1C, Enclosure management location
		96	em_ctl dd ? ; 0x20, Enclosure management control
9064	rgimad	97	cap2 dd ? ; 0x24, Host capabilities extended
9020	rgimad	98	bohc dd ? ; 0x28, BIOS/OS handoff control and status
9072	rgimad	99	reserved rb (0xA0-HBA_MEM.reserved) ; 0x2C - 0x9F, Reserved
		100	vendor rb (0x100-HBA_MEM.vendor) ; 0xA0 - 0xFF, Vendor specific
9023	rgimad	101	ports rb (sizeof.HBA_PORT*AHCI_MAX_PORTS) ; 0x100 - 0x10FF, Port control registers, max AHCI_MAX_PORTS
9020	rgimad	102	ends
		103
		104	; Port Control registers
		105	struct HBA_PORT
9064	rgimad	106	command_list_base_l dd ? ; 0x00, command list base address, 1K-byte aligned
		107	command_list_base_h dd ? ; 0x04, command list base address upper 32 bits, used on 64 bit systems
		108	fis_base_l dd ? ; 0x08, FIS base address, 256-byte aligned
		109	fis_base_h dd ? ; 0x0C, FIS base address upper 32 bits, used on 64 bit systems
		110	interrupt_status dd ? ; 0x10
		111	interrupt_enable dd ? ; 0x14
		112	command dd ? ; 0x18, command and status
		113	reserved0 dd ? ; 0x1C
		114	task_file_data dd ? ; 0x20
		115	signature dd ? ; 0x24
		116	sata_status dd ? ; 0x28, SATA status (SCR0:SStatus)
		117	sata_control dd ? ; 0x2C, SATA control (SCR2:SControl)
		118	sata_error dd ? ; 0x30, SATA error (SCR1:SError)
		119	sata_active dd ? ; 0x34, SATA active (SCR3:SActive)
		120	command_issue dd ? ; 0x38
		121	sata_notification dd ? ; 0x3C, SATA notification (SCR4:SNotification)
		122	fis_based_switch_control dd ? ; 0x40
		123	reserved1 rd 11 ; 0x44 - 0x6F
		124	vendor rd 4 ; 0x70 - 0x7F, vendor specific
9020	rgimad	125	ends
		126
9074	rgimad	127	; Command header structure, size = 32 bytes
9068	rgimad	128	struct HBA_CMD_HDR
9131	rgimad	129	flags1 db ? ; 0bPWACCCCC, P - Prefetchable, W - Write (1: H2D, 0: D2H)
9068	rgimad	130	; A - ATAPI, C - Command FIS length in DWORDS, 2 ~ 16
		131
9131	rgimad	132	flags2 db ? ; 0bPPPPRCB(Re), P - Port multiplier port, R - Reserved,
9068	rgimad	133	; C - Clear busy upon R_OK, B - BIST, Re - Reset
		134
		135	prdtl dw ? ; Physical region descriptor table length in entries
		136	prdbc dd ? ; Physical region descriptor byte count transferred
		137	ctba dd ? ; Command table descriptor base address
		138	ctbau dd ? ; Command table descriptor base address upper 32 bits
9072	rgimad	139	rd 4 ; Reserved
9068	rgimad	140	ends
		141
9074	rgimad	142	; Physical region descriptor table entry, size = 16 bytes
9069	rgimad	143	struct HBA_PRDT_ENTRY
		144	dba dd ? ; Data base address
		145	dbau dd ? ; Data base address upper 32 bits
9072	rgimad	146	dd ? ; Reserved
9131	rgimad	147	flags dd ? ; 0bIR..RD..D, I (1 bit) - Interrupt on completion,
9069	rgimad	148	; R (9 bits) - Reserved, D (22 bits) - Byte count, 4M max
		149	ends
		150
		151	struct HBA_CMD_TBL
		152	cfis rb 64 ; 0x00, Command FIS
		153	acmd rb 16 ; 0x40, ATAPI command, 12 or 16 bytes
9072	rgimad	154	rb 48 ; 0x50, Reserved
9069	rgimad	155	prdt_entry HBA_PRDT_ENTRY ; 0x80, Physical region descriptor table entries, 0 ~ 65535
		156	; so, this structure is variable-length
		157	ends
		158
9068	rgimad	159	; Contains virtual mappings for port phys memory regions
		160	struct PORT_DATA
		161	clb dd ? ; Command list base
		162	fb dd ? ; FIS base
		163	ctba_arr rd 32 ; ctba_arr[0] = clb[0].ctba, ... and so on.
		164	port dd ? ; address of correspoding HBA_PORT structure
9074	rgimad	165	portno dd ? ; port index, 0..31
9134	rgimad	166	drive_type db ? ; drive type
9140	rgimad	167	sector_count dq ? ; number of sectors
9068	rgimad	168	ends
		169
9064	rgimad	170	; Register FIS – Host to Device
		171	struct FIS_REG_H2D
		172	fis_type db ? ; FIS_TYPE_REG_H2D
9131	rgimad	173	flags db ? ; 0bCRRRPPPP, C - 1: Command, 0: Control
9064	rgimad	174	; R - Reserved, P - Port multiplier
		175
		176	command db ? ; Command register
		177	featurel db ? ; Feature register, 7:0
		178
		179	lba0 db ? ; LBA low register, 7:0
		180	lba1 db ? ; LBA mid register, 15:8
		181	lba2 db ? ; LBA high register, 23:16
		182	device db ? ; Device register
		183
		184	lba3 db ? ; LBA register, 31:24
		185	lba4 db ? ; LBA register, 39:32
		186	lba5 db ? ; LBA register, 47:40
		187	featureh db ? ; Feature register, 15:8
		188
		189	countl db ? ; Count register, 7:0
		190	counth db ? ; Count register, 15:8
		191	icc db ? ; Isochronous command completion
		192	control db ? ; Control register
		193
9072	rgimad	194	rb 4 ; Reserved
9064	rgimad	195	ends
		196
		197	; Register FIS – Device to Host
		198	struct FIS_REG_D2H
		199	fis_type db ? ; FIS_TYPE_REG_D2H
		200
9131	rgimad	201	flags db ? ; 0bRIRPPPP, P - Port multiplier, R - Reserved
9064	rgimad	202	; I - Interrupt bit
		203
		204	status db ? ; Status register
		205	error db ? ; Error register
		206
		207	lba0 db ? ; LBA low register, 7:0
		208	lba1 db ? ; LBA mid register, 15:8
		209	lba2 db ? ; LBA high register, 23:16
		210	device db ? ; Device register
		211
		212	lba3 db ? ; LBA register, 31:24
		213	lba4 db ? ; LBA register, 39:32
		214	lba5 db ? ; LBA register, 47:40
9072	rgimad	215	db ? ; Reserved
9064	rgimad	216
		217	countl db ? ; Count register, 7:0
		218	counth db ? ; Count register, 15:8
9072	rgimad	219	rb 2 ; Reserved
9064	rgimad	220
9072	rgimad	221	rb 4 ; Reserved
9064	rgimad	222	ends
		223
		224	; Data FIS – Bidirectional
		225	struct FIS_DATA
		226	fis_type db ? ; FIS_TYPE_DATA
9131	rgimad	227	flags db ? ; 0bRRRRPPPP, R - Reserved, P - Port multiplier
9072	rgimad	228	rb 2 ; Reserved
9064	rgimad	229	; DWORD 1 ~ N (?)
		230	data rd 1 ; Payload
		231	ends
		232
		233	; PIO Setup – Device to Host
		234	struct FIS_PIO_SETUP
		235	fis_type db ? ; FIS_TYPE_PIO_SETUP
		236
9131	rgimad	237	flags db ? ; 0bRIDRPPPP, P - Port multiplier, R - Reserved
9064	rgimad	238	; I - Interrupt bit, D - Data transfer direction, 1 - device to host
		239
		240	status db ? ; Status register
		241	error db ? ; Error register
		242
		243	lba0 db ? ; LBA low register, 7:0
		244	lba1 db ? ; LBA mid register, 15:8
		245	lba2 db ? ; LBA high register, 23:16
		246	device db ? ; Device register
		247
		248	lba3 db ? ; LBA register, 31:24
		249	lba4 db ? ; LBA register, 39:32
		250	lba5 db ? ; LBA register, 47:40
9072	rgimad	251	db ? ; Reserved
9064	rgimad	252
		253	countl db ? ; Count register, 7:0
		254	counth db ? ; Count register, 15:8
9072	rgimad	255	db ? ; Reserved
9064	rgimad	256	e_status db ? ; New value of status register
		257
		258	tc dw ? ; Transfer count
9072	rgimad	259	rb 2 ; Reserved
9064	rgimad	260	ends
		261
		262	; DMA Setup – Device to Host
		263	struct FIS_DMA_SETUP
		264	fis_type db ? ; FIS_TYPE_DMA_SETUP
9131	rgimad	265	flags db ? ; 0bAIDRPPPP, A - Auto-activate. Specifies if DMA Activate FIS is needed,
9064	rgimad	266	; I - Interrupt bit, D - Data transfer direction, 1 - device to host,
		267	; R - Reserved, P - Port multiplier
		268
9072	rgimad	269	rb 2 ; Reserved
9064	rgimad	270	DMAbufferID dq ? ; DMA Buffer Identifier.
		271	; Used to Identify DMA buffer in host memory.
		272	; SATA Spec says host specific and not in Spec.
		273	; Trying AHCI spec might work.
		274
9072	rgimad	275	dd ? ; Reserved
		276	DMAbufOffset dd ? ; Byte offset into buffer. First 2 bits must be 0
9064	rgimad	277	TransferCount dd ? ; Number of bytes to transfer. Bit 0 must be 0
9072	rgimad	278	dd ? ; Reserved
9064	rgimad	279	ends
		280
		281	; Set device bits FIS - device to host
		282	struct FIS_DEV_BITS
		283	fis_type db ? ; FIS_TYPE_DEV_BITS
9131	rgimad	284	flags db ? ; 0bNIRRPPPP, N - Notification, I - Interrupt,
9064	rgimad	285	; R - Reserved, P - Port multiplier
		286
		287	status db ? ; Status register
		288	error db ? ; Error register
		289
		290	protocol dd ? ; Protocol
		291	ends
		292
9069	rgimad	293	struct HBA_FIS
		294	dsfis FIS_DMA_SETUP ; 0x00, DMA Setup FIS
9072	rgimad	295	rb 4 ; padding
9069	rgimad	296
		297	psfis FIS_PIO_SETUP ; 0x20, PIO Setup FIS
9072	rgimad	298	rb 12 ; padding
9069	rgimad	299
		300	rfis FIS_REG_D2H ; 0x40, Register - Device to Host FIS
9072	rgimad	301	rb 4 ; padding
9069	rgimad	302
		303	sdbfis FIS_DEV_BITS ; 0x58, Set Device Bit FIS
		304
		305	ufis rb 64 ; 0x60
		306
9072	rgimad	307	rb (0x100 - 0xA0) ; 0xA0, Reserved
9069	rgimad	308	ends
		309
9064	rgimad	310	; --------------------------------------------------
9020	rgimad	311	uglobal
		312	align 4
		313	ahci_controller AHCI_DATA
9068	rgimad	314	port_data_arr rb (sizeof.PORT_DATA*AHCI_MAX_PORTS)
9140	rgimad	315	ahci_mutex MUTEX
9020	rgimad	316	endg
		317
9140	rgimad	318	iglobal
		319	align 4
		320	ahci_callbacks:
		321	dd ahci_callbacks.end - ahci_callbacks
		322	dd 0 ; no close function
		323	dd 0 ; no closemedia function
		324	dd ahci_querymedia
		325	dd ahci_read
		326	dd 0;ahci_write
		327	dd 0 ; no flush function
		328	dd 0 ; use default cache size
		329	.end:
		330	hd_name db 'hd', 0, 0, 0
		331	hd_counter dd 0
		332	endg
		333
9064	rgimad	334	; -----------------------------------------------------------------------
9020	rgimad	335	; detect ahci controller and initialize
		336	align 4
9068	rgimad	337	ahci_init:
9140	rgimad	338	mov ecx, ahci_mutex
		339	call mutex_init
		340
9020	rgimad	341	mov ecx, ahci_controller
		342	mov esi, pcidev_list
		343	.find_ahci_ctr:
		344	mov esi, [esi + PCIDEV.fd]
		345	cmp esi, pcidev_list
		346	jz .ahci_ctr_not_found
		347	mov eax, [esi + PCIDEV.class]
		348	;DEBUGF 1, "K: device class = %x\n", eax
		349	shr eax, 8 ; shift right because lowest 8 bits if ProgIf field
		350	cmp eax, 0x0106 ; 0x01 - Mass Storage Controller class, 0x06 - Serial ATA Controller subclass
		351	jz .ahci_ctr_found
		352	jmp .find_ahci_ctr
		353
		354	.ahci_ctr_not_found:
		355	DEBUGF 1, "K: AHCI controller not found\n"
		356	ret
		357
		358	.ahci_ctr_found:
		359	mov [ahci_controller + AHCI_DATA.pcidev], esi
		360
		361	mov eax, [esi+PCIDEV.class]
		362	movzx ebx, byte [esi+PCIDEV.bus]
		363	movzx ecx, byte [esi+PCIDEV.devfn]
		364	shr ecx, 3 ; get rid of 3 lowest bits (function code), the rest bits is device code
		365	movzx edx, byte [esi+PCIDEV.devfn]
		366	and edx, 00000111b ; get only 3 lowest bits (function code)
		367	DEBUGF 1, "K: found AHCI controller, (class, subcl, progif) = %x, bus = %x, device = %x, function = %x\n", eax, ebx, ecx, edx
		368
9023	rgimad	369	; get BAR5 value, it is physical address
9037	rgimad	370	movzx ebx, [esi + PCIDEV.bus]
		371	movzx ebp, [esi + PCIDEV.devfn]
		372	stdcall pci_read32, ebx, ebp, PCI_REG_BAR5
		373	DEBUGF 1, "K: AHCI controller MMIO = %x\n", eax
		374	mov edi, eax
9020	rgimad	375
9037	rgimad	376	; get the size of MMIO region
		377	stdcall pci_write32, ebx, ebp, PCI_REG_BAR5, 0xFFFFFFFF
		378	stdcall pci_read32, ebx, ebp, PCI_REG_BAR5
		379	not eax
		380	inc eax
		381	DEBUGF 1, "K: AHCI: MMIO region size = 0x%x bytes\n", eax
		382
		383	; Map MMIO region to virtual memory
		384	stdcall map_io_mem, edi, eax, PG_SWR + PG_NOCACHE
9020	rgimad	385	mov [ahci_controller + AHCI_DATA.abar], eax
		386	DEBUGF 1, "K: AHCI controller BAR5 mapped to virtual addr %x\n", eax
		387
9037	rgimad	388	; Restore the original BAR5 value
		389	stdcall pci_write32, ebx, ebp, PCI_REG_BAR5, edi
		390
9023	rgimad	391	; Enable dma bus mastering, memory space access, clear the "disable interrupts" bit
		392	; Usually, it is already done before us
9024	rgimad	393	movzx ebx, [esi + PCIDEV.bus]
		394	movzx ebp, [esi + PCIDEV.devfn]
		395	stdcall pci_read32, ebx, ebp, PCI_REG_STATUS_COMMAND
9020	rgimad	396	DEBUGF 1, "K: AHCI: pci_status_command = %x\nEnabling interrupts, DMA bus mastering and memory space access\n", eax
		397	or eax, 0x06 ; pci.command \|= 0x06 (dma bus mastering + memory space access)
		398	btr eax, 10 ; clear the "disable interrupts" bit
		399	DEBUGF 1, "K: AHCI: pci_status_command = %x\n", eax
9024	rgimad	400	stdcall pci_write32, ebx, ebp, PCI_REG_STATUS_COMMAND, eax
9020	rgimad	401
9023	rgimad	402	; ; Print some register values to debug board
		403	; mov esi, [ahci_controller + AHCI_DATA.abar]
9064	rgimad	404	; DEBUGF 1, "K: AHCI: HBA.cap = %x, HBA.ghc = %x, HBA_MEM.version = %x\n", [esi + HBA_MEM.cap], [esi + HBA_MEM.ghc], [esi + HBA_MEM.version]
9020	rgimad	405
9023	rgimad	406	;-------------------------------------------------------
		407	; Request BIOS/OS ownership handoff, if supported. (TODO check correctness)
		408	mov esi, [ahci_controller + AHCI_DATA.abar]
9064	rgimad	409	;mov ebx, [esi + HBA_MEM.cap2]
9023	rgimad	410	;DEBUGF 1, "K: AHCI: HBA_MEM.cap2 = %x\n", ebx
9064	rgimad	411	bt [esi + HBA_MEM.cap2], bit_AHCI_HBA_CAP2_BOH
9020	rgimad	412	jnc .end_handoff
9023	rgimad	413	DEBUGF 1, "K: AHCI: requesting AHCI ownership change...\n"
9024	rgimad	414	bts [esi + HBA_MEM.bohc], bit_AHCI_HBA_BOHC_OOS
9020	rgimad	415
		416	.wait_not_bos:
9024	rgimad	417	bt [esi + HBA_MEM.bohc], bit_AHCI_HBA_BOHC_BOS
9020	rgimad	418	jc .wait_not_bos
		419
		420	mov ebx, 3
		421	call delay_hs
		422
9023	rgimad	423	; if Bios Busy is still set after 30 mS, wait 2 seconds.
9024	rgimad	424	bt [esi + HBA_MEM.bohc], bit_AHCI_HBA_BOHC_BB
9020	rgimad	425	jnc @f
		426
		427	mov ebx, 200
		428	call delay_hs
		429	@@:
9023	rgimad	430	DEBUGF 1, "K: AHCI: ownership change completed.\n"
9020	rgimad	431
		432	.end_handoff:
9023	rgimad	433	;-------------------------------------------------------
9020	rgimad	434
9023	rgimad	435	; enable the AHCI and reset it
9064	rgimad	436	bts [esi + HBA_MEM.ghc], bit_AHCI_HBA_GHC_AHCI_ENABLE
		437	bts [esi + HBA_MEM.ghc], bit_AHCI_HBA_GHC_RESET
9020	rgimad	438
9023	rgimad	439	; wait for reset to complete
		440	.wait_reset:
9064	rgimad	441	bt [esi + HBA_MEM.ghc], bit_AHCI_HBA_GHC_RESET
9023	rgimad	442	jc .wait_reset
9020	rgimad	443
9023	rgimad	444	; enable the AHCI and interrupts
9064	rgimad	445	bts [esi + HBA_MEM.ghc], bit_AHCI_HBA_GHC_AHCI_ENABLE
		446	bts [esi + HBA_MEM.ghc], bit_AHCI_HBA_GHC_INTERRUPT_ENABLE
9023	rgimad	447	mov ebx, 2
		448	call delay_hs
		449
9064	rgimad	450	DEBUGF 1, "K: AHCI: caps: %x %x, ver: %x, ghc: %x, pi: %x\n", [esi + HBA_MEM.cap], [esi + HBA_MEM.cap2], [esi + HBA_MEM.version], [esi + HBA_MEM.ghc], [esi + HBA_MEM.pi]
9020	rgimad	451
9037	rgimad	452	; TODO:
		453	; calculate irq line
		454	; ahciHBA->ghc \|= AHCI_GHC_IE;
		455	; IDT::RegisterInterruptHandler(irq, InterruptHandler);
9064	rgimad	456	; ahciHBA->is = 0xffffffff;
9037	rgimad	457
9140	rgimad	458	mov [hd_counter], 0
9037	rgimad	459	xor ebx, ebx
		460	.detect_drives:
		461	cmp ebx, AHCI_MAX_PORTS
		462	jae .end_detect_drives
		463
		464	; if port with index ebx is not implemented then go to next
9064	rgimad	465	mov ecx, [esi + HBA_MEM.pi]
9037	rgimad	466	bt ecx, ebx
		467	jnc .continue_detect_drives
		468
		469	mov edi, ebx
9074	rgimad	470	imul edi, sizeof.HBA_PORT
9037	rgimad	471	add edi, HBA_MEM.ports
		472	add edi, esi
		473	; now edi - base of HBA_MEM.ports[ebx]
		474
9130	rgimad	475	DEBUGF 1, "K: AHCI: port %d, cmd = %x, ssts = %x\n", ebx, [edi + HBA_PORT.command], [edi + HBA_PORT.sata_status]
9037	rgimad	476
9130	rgimad	477	; If port is not idle force it to be idle
		478	mov eax, [edi + HBA_PORT.command]
		479	and eax, (AHCI_HBA_PxCMD_ST or AHCI_HBA_PxCMD_CR or AHCI_HBA_PxCMD_FRE or AHCI_HBA_PxCMD_FR)
		480	test eax, eax
		481	jz @f
		482
		483	mov eax, edi
		484	DEBUGF 1, "ahci_stop_cmd..\n"
		485	call ahci_stop_cmd
		486	@@:
		487	; TODO: what is purpose of this block of code ?
		488	; Reset port, disable slumber and partial state
		489	; mov [edi + HBA_PORT.sata_control], 0x301
		490	; push ebx
		491	; mov ebx, 5 ; wait 50 ms
		492	; call delay_hs
		493	; pop ebx
		494	; mov [edi + HBA_PORT.sata_control], 0x300
		495
		496	; if(abar->cap & HBA_MEM_CAP_SSS)
		497	; {
		498	; abar->ports[i].cmd \|= (HBA_PxCMD_SUD \| HBA_PxCMD_POD \| HBA_PxCMD_ICC);
		499	; Sleep(10);
		500	; }
		501	; rewritten to:
		502	bt [esi + HBA_MEM.cap], 27 ; check Supports Staggered Spin-up bit in capabilities
		503	jnc @f
9134	rgimad	504	DEBUGF 1, "Supports Staggered Spin-up, spinning up the port..\n"
9130	rgimad	505	or [edi + HBA_PORT.command], (0x0002 or 0x0004 or 0x10000000)
		506	push ebx
		507	mov ebx, 1 ; wait 10 ms
		508	call delay_hs
		509	pop ebx
		510	@@:
		511	; Clear interrupt status and error status
		512	mov [edi + HBA_PORT.sata_error], 0xFFFFFFFF
		513	mov [edi + HBA_PORT.interrupt_status], 0xFFFFFFFF
		514
		515	; ------------------------------------------
		516
9037	rgimad	517	mov ecx, [edi + HBA_PORT.sata_status]
		518	shr ecx, 8
		519	and ecx, 0x0F
		520	cmp ecx, AHCI_HBA_PORT_IPM_ACTIVE
		521	jne .continue_detect_drives
		522
		523	mov ecx, [edi + HBA_PORT.sata_status]
		524	and ecx, AHCI_HBA_PxSSTS_DET
		525	cmp ecx, AHCI_HBA_PxSSTS_DET_PRESENT
9068	rgimad	526	jne .continue_detect_drives
9037	rgimad	527
9134	rgimad	528	; DEBUGF 1, "K: AHCI: found drive at port %d, cmd = 0x%x, ssts = 0x%x, signature = 0x%x\n", ebx, [edi + HBA_PORT.command], [edi + HBA_PORT.sata_status], [edi + HBA_PORT.signature]
9037	rgimad	529
9068	rgimad	530	mov ecx, ebx
9074	rgimad	531	imul ecx, sizeof.PORT_DATA
9068	rgimad	532	add ecx, port_data_arr
		533	stdcall ahci_port_rebase, edi, ebx, ecx
		534
9134	rgimad	535	; DEBUGF 1, "K: AHCI: After REBASING, signature = 0x%x\n", [edi + HBA_PORT.signature]
		536
9135	rgimad	537	; Determine drive type by checking port signature
9134	rgimad	538	.switch_sig:
		539	cmp [edi + HBA_PORT.signature], SATA_SIG_ATA
9135	rgimad	540	mov eax, AHCI_DEV_SATA
		541	jz .end_switch_sig
		542
9134	rgimad	543	cmp [edi + HBA_PORT.signature], SATA_SIG_ATAPI
9135	rgimad	544	mov eax, AHCI_DEV_SATAPI
		545	jz .end_switch_sig
		546
9134	rgimad	547	cmp [edi + HBA_PORT.signature], SATA_SIG_SEMB
9135	rgimad	548	mov eax, AHCI_DEV_SEMB
		549	jz .end_switch_sig
		550
9134	rgimad	551	cmp [edi + HBA_PORT.signature], SATA_SIG_PM
9135	rgimad	552	mov eax, AHCI_DEV_PM
		553	jz .end_switch_sig
		554
9134	rgimad	555	DEBUGF 1, "Unknown device signature\n"
9135	rgimad	556	mov eax, AHCI_DEV_NULL
9134	rgimad	557	.end_switch_sig:
9136	rgimad	558	mov [ecx + PORT_DATA.drive_type], al
9134	rgimad	559
		560	DEBUGF 1, "K: AHCI: found drive on port %u: TYPE = %u\n", ebx, [ecx + PORT_DATA.drive_type]
		561
9074	rgimad	562	stdcall ahci_port_identify, ecx
		563
9140	rgimad	564	cmp [ecx + PORT_DATA.drive_type], AHCI_DEV_SATA
		565	jne .after_add_disk ; skip adding disk code
		566	; register disk in system:
		567	push ecx edx
		568	mov eax, [hd_counter]
		569	xor edx, edx
		570	mov ecx, 10
		571	div ecx ; eax = hd_counter / 10, edx = hd_counter % 10
		572	test eax, eax
		573	jz .concat_one
		574	add al, '0'
		575	mov byte [hd_name + 2], al
		576	add dl, '0'
		577	mov byte [hd_name + 3], dl
		578	jmp .endif1
		579	.concat_one:
		580	add dl, '0'
		581	mov byte [hd_name + 2], dl
		582	.endif1:
		583	pop edx ecx
		584
		585	DEBUGF 1, "adding '%s'\n", hd_name
		586
		587	stdcall disk_add, ahci_callbacks, hd_name, ecx, 0
		588	test eax, eax
		589	jz .disk_add_fail
		590	stdcall disk_media_changed, eax, 1 ; system will scan for partitions on disk
		591	jmp .after_add_disk
		592
		593	.disk_add_fail:
		594	DEBUGF 1, "Failed to add disk\n"
		595	.after_add_disk:
		596
9037	rgimad	597	.continue_detect_drives:
		598	inc ebx
		599	jmp .detect_drives
		600
9064	rgimad	601
9037	rgimad	602
		603	.end_detect_drives:
		604
		605
9020	rgimad	606	ret
9065	rgimad	607	; -------------------------------------------------
9020	rgimad	608
9074	rgimad	609	modelstr rb 42
		610	; Identify drive on port ; TODO check
		611	; in: pdata - address of PORT_DATA structure
		612	proc ahci_port_identify stdcall, pdata: dword
		613	locals
		614	cmdslot dd ?
		615	cmdheader dd ?
		616	cmdtable dd ?
		617	buf_phys dd ?
		618	buf_virt dd ?
		619	endl
		620
		621	pushad
		622
		623	mov esi, [pdata] ; esi - address of PORT_DATA struct of port
		624	mov edi, [esi + PORT_DATA.port] ; edi - address of HBA_PORT struct of port
		625
		626	mov eax, edi
		627	call ahci_find_cmdslot
		628
		629	cmp eax, -1
		630	jne .cmdslot_found
		631
		632	DEBUGF 1, "No free cmdslot on port %u\n", [esi + PORT_DATA.portno]
9140	rgimad	633	jmp .ret
9074	rgimad	634
		635	.cmdslot_found:
		636	mov [cmdslot], eax
9134	rgimad	637	; DEBUGF 1, "Found free cmdslot %u on port %u\n", [cmdslot], [esi + PORT_DATA.portno]
9074	rgimad	638
		639	shl eax, BSF sizeof.HBA_CMD_HDR
		640	add eax, [esi + PORT_DATA.clb]
		641	mov [cmdheader], eax ; address of virtual mapping of command header
		642	mov eax, [cmdslot]
		643	mov eax, [esi + eax*4 + PORT_DATA.ctba_arr]
		644	mov [cmdtable], eax ; address of virtual mapping of command table of command header
		645
		646	stdcall _memset, eax, 0, sizeof.HBA_CMD_TBL
		647
		648	call alloc_page
		649	mov [buf_phys], eax
		650
		651	stdcall map_io_mem, eax, 4096, PG_NOCACHE + PG_SWR ; map to virt memory so we can work with it
		652	mov [buf_virt], eax
		653
		654	mov eax, [cmdtable]
		655	mov ebx, [buf_phys]
		656	mov dword [eax + HBA_CMD_TBL.prdt_entry + HBA_PRDT_ENTRY.dba], ebx
		657	mov dword [eax + HBA_CMD_TBL.prdt_entry + HBA_PRDT_ENTRY.dbau], 0
9131	rgimad	658	and [eax + HBA_CMD_TBL.prdt_entry + HBA_PRDT_ENTRY.flags], not 0x3FFFFF ; zero out lower 22 bits, they used for byte count
		659	or [eax + HBA_CMD_TBL.prdt_entry + HBA_PRDT_ENTRY.flags], 512 - 1 ; reason why -1 see in spec on this field
		660	; or [eax + HBA_CMD_TBL.prdt_entry + HBA_PRDT_ENTRY.flags], 1 shl 31 ; enable interrupt on completion
		661
9074	rgimad	662	mov eax, [cmdheader]
9131	rgimad	663	and [eax + HBA_CMD_HDR.flags1], not 0x1F ; zero out lower 5 bits, they will be used for cfl
		664	or [eax + HBA_CMD_HDR.flags1], (sizeof.FIS_REG_H2D / 4) ; set command fis length in dwords
		665	movzx bx, [eax + HBA_CMD_HDR.flags1]
		666	btr bx, 6 ; flag W = 0
		667	mov [eax + HBA_CMD_HDR.flags1], bl
		668	movzx bx, [eax + HBA_CMD_HDR.flags2]
		669	btr bx, 2 ; flag C = 0
		670	mov [eax + HBA_CMD_HDR.flags2], bl
9074	rgimad	671	mov [eax + HBA_CMD_HDR.prdtl], 1
		672
		673	mov eax, [cmdtable]
		674	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.fis_type], FIS_TYPE_REG_H2D
9131	rgimad	675	movzx ebx, byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.flags]
9074	rgimad	676	bts ebx, bit_AHCI_H2D_FLAG_CMD ; Set Command bit in H2D FIS.
9131	rgimad	677	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.flags], bl
9134	rgimad	678
		679	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.command], ATA_IDENTIFY
		680	cmp [esi + PORT_DATA.drive_type], AHCI_DEV_SATAPI
		681	jne @f
		682	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.command], ATAPI_IDENTIFY
		683	@@:
9074	rgimad	684	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.device], 0
		685
9139	rgimad	686	; Wait on previous command to complete, before issuing new command.
		687	stdcall ahci_port_wait, edi, AHCI_PORT_TIMEOUT
		688	; DEBUGF 1, "eax = %x\n", eax
		689	; TODO check eax error value
9074	rgimad	690
		691	mov eax, [cmdslot]
		692	bts [edi + HBA_PORT.command_issue], eax ; Issue the command
		693
9139	rgimad	694	; Wait for command completion
		695	stdcall ahci_port_cmd_wait, edi, eax;, AHCI_PORT_CMD_TIMEOUT
		696	; DEBUGF 1, " eax = %x\n", eax
		697	; TODO check eax error value
9074	rgimad	698
9134	rgimad	699	; DEBUGF 1, "sata_error register = 0x%x\n", [edi + HBA_PORT.sata_error]
9130	rgimad	700
		701	mov esi, [buf_virt]
9074	rgimad	702	add esi, 27*2
		703	mov edi, modelstr
		704	mov ecx, ((46-27)+1)*2
		705	cld
		706	rep movsb
		707	mov byte [edi], 0
		708
9138	rgimad	709	stdcall swap_bytes_in_words, modelstr, (46-27)+1
9131	rgimad	710	DEBUGF 1, "IDENTIFICATION RESULT: MODEL = %s\n", modelstr
9074	rgimad	711
9138	rgimad	712	mov esi, [buf_virt]
		713	mov eax, [esi + 200]
		714	mov edx, [esi + 200 + 4]
		715	DEBUGF 1, "lba48 mode sector count = 0x%x:%x\n", edx, eax
		716
		717	shrd eax, edx, 11 ; i.e *512 / 1024 / 1024, 512 - sector size
		718	DEBUGF 1, "disk capacity = %u MiB ", eax
		719	shrd eax, edx, 10 ; / 1024
		720	DEBUGF 1, "= %u GiB\n", eax
9074	rgimad	721	.ret:
		722	popad
		723	ret
		724	endp
		725
9140	rgimad	726	proc ahci_querymedia stdcall, pdata, mediainfo
		727	push ecx edx
		728	mov eax, [mediainfo]
		729	mov edx, [pdata]
		730	mov [eax + DISKMEDIAINFO.Flags], 0
		731	mov [eax + DISKMEDIAINFO.SectorSize], 512
		732	mov ecx, dword[edx + PORT_DATA.sector_count]
		733	mov dword [eax + DISKMEDIAINFO.Capacity], ecx
		734	mov ecx, dword[edx + PORT_DATA.sector_count + 4]
		735	mov dword [eax + DISKMEDIAINFO.Capacity + 4], ecx
		736	pop edx ecx
		737	xor eax, eax
		738	ret
		739	endp
9134	rgimad	740
9140	rgimad	741	; Read sectors
		742	; return value: 0 = success, otherwise = error
		743	proc ahci_read stdcall pdata: dword, buffer: dword, startsector: qword, numsectors_ptr:dword
		744	locals
		745	cmdslot dd ?
		746	cmdheader dd ?
		747	cmdtable dd ?
		748	numsectors dd ?
		749	buffer_pos dd ?
		750	buffer_length dd ?
		751	endl
		752
		753	pushad
		754
		755	mov ecx, ahci_mutex
		756	call mutex_lock
		757
		758	; xor ecx, ecx
		759	; mov esi, [buffer]
		760	; .print_data:
		761	; cmp ecx, 512
		762	; jae .end_print_data
		763
		764	; mov al, byte [esi + ecx]
		765	; mov byte [tmpstr], al
		766	; mov byte [tmpstr + 1], 0
		767	; DEBUGF 1, "0x%x(%s) ", al:1, tmpstr
		768
		769	; inc ecx
		770	; jmp .print_data
		771	; .end_print_data:
		772	; DEBUGF 1, "\n"
		773
		774	mov eax, [numsectors_ptr]
		775	mov eax, [eax]
		776	mov [numsectors], eax
		777
		778	DEBUGF 1, " ahci_read: buffer = 0x%x, startsector = 0x%x:%x, numsectors = %u\n", [buffer], [startsector], [startsector + 4], eax
		779
		780	mov esi, [pdata] ; esi - address of PORT_DATA struct of port
		781	mov edi, [esi + PORT_DATA.port] ; edi - address of HBA_PORT struct of port
		782	mov eax, edi
		783	call ahci_find_cmdslot
		784	cmp eax, -1
		785	jne .cmdslot_found
		786
		787	DEBUGF 1, "No free cmdslot on port %u\n", [esi + PORT_DATA.portno]
		788	jmp .ret
		789
		790	.cmdslot_found:
		791	mov [cmdslot], eax
		792	; DEBUGF 1, "Found free cmdslot %u on port %u\n", [cmdslot], [esi + PORT_DATA.portno]
		793
		794	shl eax, BSF sizeof.HBA_CMD_HDR
		795	add eax, [esi + PORT_DATA.clb]
		796	mov [cmdheader], eax ; address of virtual mapping of command header
		797	mov eax, [cmdslot]
		798	mov eax, [esi + eax*4 + PORT_DATA.ctba_arr]
		799	mov [cmdtable], eax ; address of virtual mapping of command table of command header
		800
		801	mov eax, [cmdheader]
		802	and [eax + HBA_CMD_HDR.flags1], not 0x1F ; zero out lower 5 bits, they will be used for cfl
		803	or [eax + HBA_CMD_HDR.flags1], (sizeof.FIS_REG_H2D / 4) ; set command fis length in dwords
		804	movzx bx, [eax + HBA_CMD_HDR.flags1]
		805	btr bx, 6 ; flag W = 0
		806	mov [eax + HBA_CMD_HDR.flags1], bl
		807	movzx bx, [eax + HBA_CMD_HDR.flags2]
		808	btr bx, 2 ; flag C = 0
		809	mov [eax + HBA_CMD_HDR.flags2], bl
		810
		811	mov ebx, [numsectors]
		812	shl ebx, 9 ; *= 512
		813	mov [buffer_length], ebx
		814	dec ebx
		815	shr ebx, 12 ; /= 4096
		816	inc ebx
		817	mov [eax + HBA_CMD_HDR.prdtl], bx
		818	;DEBUGF 1, " prdtl = %u\n", [eax + HBA_CMD_HDR.prdtl]:2
		819
		820	; zero out the command table with its prdt entries
		821	dec ebx
		822	shl ebx, BSF sizeof.HBA_PRDT_ENTRY
		823	add ebx, sizeof.HBA_CMD_TBL
		824	stdcall _memset, [cmdtable], 0, ebx
		825
		826	DEBUGF 1, " prdtl = %u\n", [eax + HBA_CMD_HDR.prdtl]:2
		827	;jmp .ret
		828
		829	xor ecx, ecx
		830	movzx edx, [eax + HBA_CMD_HDR.prdtl]
		831	dec edx
		832	mov eax, [buffer]
		833	mov [buffer_pos], eax
		834
		835	.prdt_fill:
		836	cmp ecx, edx
		837	jae .prdt_fill_end
		838
		839	mov ebx, [buffer_pos]
		840	and ebx, 0xFFF
		841	call get_pg_addr ; eax = phys addr
		842	add eax, ebx
		843	DEBUGF 1, " PHYS = 0x%x\n", eax
		844	mov ebx, ecx
		845	shl ebx, BSF sizeof.HBA_PRDT_ENTRY
		846	add ebx, [cmdtable]
		847	add ebx, HBA_CMD_TBL.prdt_entry ; now ebx - address of ecx'th prdt_entry
		848
		849	mov [ebx + HBA_PRDT_ENTRY.dba], eax
		850	mov [ebx + HBA_PRDT_ENTRY.dbau], 0
		851	and [ebx + HBA_PRDT_ENTRY.flags], not 0x3FFFFF ; zero out lower 22 bits, they used for byte count
		852	or [ebx + HBA_PRDT_ENTRY.flags], 4096 - 1 ; reason why -1 see in spec on this field
		853	; or [eax + HBA_CMD_TBL.prdt_entry + HBA_PRDT_ENTRY.flags], 1 shl 31 ; enable interrupt on completion
		854
		855	add [buffer_pos], 4096
		856	sub [buffer_length], 4096
		857
		858	inc ecx
		859	jmp .prdt_fill
		860	.prdt_fill_end:
		861
		862	mov ebx, [buffer_pos]
		863	and ebx, 0xFFF
		864	call get_pg_addr ; eax = phys addr
		865	add eax, ebx
		866	DEBUGF 1, " PHYS. = 0x%x\n", eax
		867	mov ebx, ecx
		868	shl ebx, BSF sizeof.HBA_PRDT_ENTRY
		869	add ebx, [cmdtable]
		870	add ebx, HBA_CMD_TBL.prdt_entry ; now ebx - address of ecx'th prdt_entry
		871	mov [ebx + HBA_PRDT_ENTRY.dba], eax
		872	mov [ebx + HBA_PRDT_ENTRY.dbau], 0
		873	and [ebx + HBA_PRDT_ENTRY.flags], not 0x3FFFFF ; zero out lower 22 bits, they used for byte count
		874	mov eax, [buffer_length]
		875	dec eax
		876	DEBUGF 1, " DBC = %u\n", eax
		877	or [ebx + HBA_PRDT_ENTRY.flags], eax ; reason why -1 see in spec on this field
		878	; or [eax + HBA_CMD_TBL.prdt_entry + HBA_PRDT_ENTRY.flags], 1 shl 31 ; enable interrupt on completion
		879
		880	mov eax, [cmdtable]
		881	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.fis_type], FIS_TYPE_REG_H2D
		882	movzx ebx, byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.flags]
		883	bts ebx, bit_AHCI_H2D_FLAG_CMD ; Set Command bit in H2D FIS.
		884	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.flags], bl
		885
		886	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.command], ATA_CMD_READ_DMA_EX
		887
		888	mov ebx, dword [startsector]
		889	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.lba0], bl
		890	shr ebx, 8
		891	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.lba1], bl
		892	shr ebx, 8
		893	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.lba2], bl
		894	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.device], 1 shl 6 ; LBA mode
		895	shr ebx, 8
		896	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.lba3], bl
		897	mov ebx, dword [startsector + 4]
		898	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.lba4], bl
		899	shr ebx, 8
		900	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.lba5], bl
		901
		902	mov ebx, [numsectors]
		903	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.countl], bl
		904	shr ebx, 8
		905	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.counth], bl
		906
		907	; Wait on previous command to complete, before issuing new command.
		908	stdcall ahci_port_wait, edi, AHCI_PORT_TIMEOUT
		909
		910	mov eax, [cmdslot]
		911	bts [edi + HBA_PORT.command_issue], eax ; Issue the command
		912
		913	; Wait for command completion
		914	stdcall ahci_port_cmd_wait, edi, eax;, AHCI_PORT_CMD_TIMEOUT
		915
		916	DEBUGF 1, "sata_error register = 0x%x\n", [edi + HBA_PORT.sata_error]
		917
		918	DEBUGF 1, "reading completed\n"
		919
		920	xor ecx, ecx
		921	mov esi, [buffer]
		922	.print_data:
		923	cmp ecx, 512
		924	jae .end_print_data
		925
		926	mov al, byte [esi + ecx]
		927	mov byte [tmpstr], al
		928	mov byte [tmpstr + 1], 0
		929	DEBUGF 1, "0x%x(%s) ", al:1, tmpstr
		930
		931	inc ecx
		932	jmp .print_data
		933	.end_print_data:
		934	DEBUGF 1, "\n"
		935
		936	.ret:
		937	mov ecx, ahci_mutex
		938	call mutex_unlock
		939
		940	popad
		941	xor eax, eax
		942	ret
		943	endp
		944	tmpstr rb 16
		945
9065	rgimad	946	; Start command engine
		947	; in: eax - address of HBA_PORT structure
9068	rgimad	948	ahci_start_cmd:
9065	rgimad	949	.wait_cr: ; Wait until CR (bit15) is cleared
		950	bt [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_CR
		951	jc .wait_cr
		952
		953	; Set FRE (bit4) and ST (bit0)
		954	bts [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_FRE
		955	bts [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_ST
9068	rgimad	956	; maybe here call ahci flush cmd ? TODO (see seakernel)
9065	rgimad	957	ret
		958
		959	; Stop command engine
		960	; in: eax - address of HBA_PORT structure
9068	rgimad	961	ahci_stop_cmd:
9065	rgimad	962	btr [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_ST ; Clear ST (bit0)
		963	btr [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_FRE ; Clear FRE (bit4)
		964	.wait_fr_cr: ; Wait until FR (bit14), CR (bit15) are cleared
		965	bt [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_FR
		966	jc .wait_fr_cr
		967	bt [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_CR
		968	jc .wait_fr_cr
		969
		970	ret
		971
9139	rgimad	972	; waits until the port is no longer busy before issuing a new command
		973	; in: [port] - address of HBA_PORT structure
		974	; [timeout] - timeout (in iterations)
		975	; out: eax = 0 if success, 1 if timeout expired
		976	proc ahci_port_wait stdcall, port: dword, timeout: dword
		977	push ebx ecx
		978	mov ebx, [port]
		979	xor ecx, ecx
		980	.wait:
		981	cmp ecx, [timeout]
		982	jae .wait_end
		983	mov eax, [ebx + HBA_PORT.task_file_data]
		984	and eax, ATA_DEV_BUSY or ATA_DEV_DRQ
		985	test eax, eax
		986	jz .wait_end
		987	inc ecx
		988	jmp .wait
		989	.wait_end:
		990	xor eax, eax
		991	DEBUGF 1, "port wait counter = %u\n", ecx
		992	cmp ecx, [timeout] ; if they equal it means port is hung
		993	setz al
		994	pop ecx ebx
9068	rgimad	995	ret
9139	rgimad	996	endp
9065	rgimad	997
		998
9139	rgimad	999	; Wait for command completion
		1000	; in: [port] - address of HBA_PORT structure
		1001	; [cmdslot] - number of command slot
		1002	; out: eax = 0 if success, 1 if error
		1003	proc ahci_port_cmd_wait stdcall, port: dword, cmdslot: dword ;, timeout: dword
		1004	push ebx ecx edx
		1005	mov ebx, [port]
		1006	mov edx, [cmdslot]
		1007	xor eax, eax
		1008	xor ecx, ecx
		1009	.wait:
		1010	bt [ebx + HBA_PORT.command_issue], edx
		1011	jnc .wait_end
		1012	bt [ebx + HBA_PORT.interrupt_status], bit_AHCI_HBA_PxIS_TFES ; check for Task File Error
		1013	jc .error
		1014	inc ecx
		1015	jmp .wait
		1016	.wait_end:
		1017	DEBUGF 1, "port cmd wait counter = %u\n", ecx
		1018	bt [ebx + HBA_PORT.interrupt_status], bit_AHCI_HBA_PxIS_TFES ; check for Task File Error
		1019	jc .error
		1020	jmp .ret
		1021	.error:
		1022	mov eax, 1
		1023	.ret:
		1024	pop edx ecx ebx
9068	rgimad	1025	ret
9139	rgimad	1026	endp
9065	rgimad	1027
9139	rgimad	1028	; ; The commands may not take effect until the command
		1029	; ; register is read again by software, because reasons.
		1030	; ; in: eax - address of HBA_PORT structure
		1031	; ; out: eax - command register value
		1032	; ahci_flush_cmd:
		1033	; mov eax, [eax + HBA_PORT.command]
		1034	; ret
		1035
		1036	; ; Send command to port
		1037	; ; in: eax - address of HBA_PORT structure
		1038	; ; ebx - index of command slot
		1039	; ahci_send_cmd:
		1040	; push ecx
		1041	; mov [eax + HBA_PORT.interrupt_status], 0xFFFFFFFF
		1042
		1043	; mov cl, bl
		1044	; mov [eax + HBA_PORT.command_issue], 1
		1045	; shl [eax + HBA_PORT.command_issue], cl
		1046
		1047	; call ahci_flush_cmd
		1048	; pop ecx
		1049	; ret
		1050
9068	rgimad	1051	; ---------------------------------------------------------------------------
		1052	; in: port - address of HBA_PORT structure
		1053	; portno - port index (0..31)
		1054	; pdata - address of PORT_DATA structure
		1055	proc ahci_port_rebase stdcall, port: dword, portno: dword, pdata: dword
		1056	locals
		1057	phys_page1 dd ?
		1058	virt_page1 dd ?
		1059	phys_page23 dd ?
		1060	virt_page23 dd ?
		1061	tmp dd ?
		1062	endl
		1063
		1064	pushad
		1065
		1066	DEBUGF 1, "Rebasing port %u\n", [portno]
		1067
		1068	mov eax, [port]
		1069	call ahci_stop_cmd
		1070
		1071	; Command list entry size = 32
		1072	; Command list entry maxim count = 32
		1073	; Command list maxim size = 32*32 = 1K per port
		1074	call alloc_page
		1075	mov [phys_page1], eax
		1076
		1077	stdcall map_io_mem, eax, 4096, PG_NOCACHE + PG_SWR ; map to virt memory so we can work with it
		1078	mov [virt_page1], eax
		1079
		1080	mov esi, [port]
		1081	mov ebx, [phys_page1]
		1082	mov [esi + HBA_PORT.command_list_base_l], ebx ; set the command list base
		1083	mov [esi + HBA_PORT.command_list_base_h], 0 ; zero upper 32 bits of addr cause we are 32 bit os
		1084
		1085	mov edi, [pdata]
		1086	mov ebx, [virt_page1]
		1087	mov [edi + PORT_DATA.clb], ebx ; set pdata->clb
		1088
		1089	mov eax, [port]
		1090	mov [edi + PORT_DATA.port], eax ; set pdata->port
9074	rgimad	1091	mov eax, [portno] ; set pdata->portno
		1092	mov [edi + PORT_DATA.portno], eax
9068	rgimad	1093
		1094	stdcall _memset, ebx, 0, 1024 ; zero out the command list
		1095
		1096	; FIS entry size = 256 bytes per port
		1097	mov eax, [phys_page1]
		1098	add eax, 1024
		1099	mov [esi + HBA_PORT.fis_base_l], eax
		1100	mov [esi + HBA_PORT.fis_base_h], 0
		1101
		1102	mov eax, [virt_page1]
		1103	add eax, 1024
		1104	mov [edi + PORT_DATA.fb], eax ; set pdata->fb
		1105	stdcall _memset, eax, 0, 256 ; zero out
		1106
		1107	stdcall alloc_pages, 2
		1108	mov [phys_page23], eax
		1109	stdcall map_io_mem, eax, 2*4096, PG_NOCACHE + PG_SWR
		1110	mov [virt_page23], eax
		1111
		1112	; Command table size = 256*32 = 8K per port
		1113	mov edx, [edi + PORT_DATA.clb] ; cmdheader array base
		1114	xor ecx, ecx
		1115
		1116	.for1:
		1117	cmp ecx, 32
		1118	jae .for1_end
		1119
		1120	mov ebx, ecx
		1121	shl ebx, BSF sizeof.HBA_CMD_HDR
		1122	add ebx, edx ; ebx = cmdheader[ecx]
		1123
		1124	mov [ebx + HBA_CMD_HDR.prdtl], 8 ; 8 prdt entries per command table
		1125
		1126	; 256 bytes per command table, 64+16+48+16*8
		1127
		1128	push edx
		1129
		1130	; cmdheader[ecx].ctba = phys_page23 + ecx*256
		1131	mov [ebx + HBA_CMD_HDR.ctba], ecx
		1132	shl [ebx + HBA_CMD_HDR.ctba], BSF 256 ; *= 256
		1133	mov eax, [ebx + HBA_CMD_HDR.ctba]
		1134	mov edx, [phys_page23]
		1135	add [ebx + HBA_CMD_HDR.ctba], edx
		1136
		1137	add eax, [virt_page23]
		1138	mov [tmp], eax ; tmp = virt_page23 + ecx*256
9069	rgimad	1139	lea eax, [ecx*4 + edi + PORT_DATA.ctba_arr] ; eax = pdata->ctba_arr[ecx]
9068	rgimad	1140	mov edx, [tmp]
		1141	mov [eax], edx ; pdata->ctba_arr[ecx] = virt_page23 + ecx*256
		1142
		1143	pop edx
		1144
		1145	mov [ebx + HBA_CMD_HDR.ctbau], 0
		1146	stdcall _memset, [eax], 0, 256 ; zero out
		1147
		1148	inc ecx
		1149	jmp .for1
		1150	.for1_end:
		1151
		1152	mov eax, [port]
		1153	call ahci_start_cmd
		1154
		1155	DEBUGF 1, "End rebasing port %u\n", [portno]
		1156	popad
		1157	ret
		1158	endp
		1159
9069	rgimad	1160	; ----------------------------------------------------------- ; TODO check
		1161	; Find a free command list slot
		1162	; in: eax - address of HBA_PORT structure
		1163	; out: eax - if not found -1, else slot index
		1164	ahci_find_cmdslot:
		1165	push ebx ecx edx esi
		1166	; If not set in SACT and CI, the slot is free
		1167	mov ebx, [eax + HBA_PORT.sata_active]
		1168	or ebx, [eax + HBA_PORT.command_issue] ; ebx = slots
9068	rgimad	1169
9069	rgimad	1170	mov esi, [ahci_controller + AHCI_DATA.abar]
		1171	mov edx, [esi + HBA_MEM.cap]
		1172	shr edx, 8
		1173	and edx, 0xf
9134	rgimad	1174	; DEBUGF 1, "Number of Command Slots on each port = %u\n", edx
9069	rgimad	1175	xor ecx, ecx
		1176	.for1:
		1177	cmp ecx, edx
		1178	jae .for1_end
9068	rgimad	1179
9069	rgimad	1180	; if ((slots&1) == 0) return i;
		1181	bt ebx, 0
		1182	jc .cont1
		1183
		1184	mov eax, ecx
		1185	jmp .ret
		1186
		1187	.cont1:
		1188	shr ebx, 1
		1189	inc ecx
		1190	jmp .for1
		1191	.for1_end:
		1192	DEBUGF 1, "Cannot find free command list entry\n"
		1193	mov eax, -1
		1194	.ret:
		1195	pop esi edx ecx ebx
		1196	ret
		1197
		1198
9068	rgimad	1199	proc _memset stdcall, dest:dword, val:byte, cnt:dword ; doesnt clobber any registers
		1200	;DEBUGF DBG_INFO, "memset(%x, %u, %u)\n", [dest], [val], [cnt]
		1201	push eax ecx edi
		1202	mov edi, dword [dest]
		1203	mov al, byte [val]
		1204	mov ecx, dword [cnt]
9069	rgimad	1205	rep stosb
9068	rgimad	1206	pop edi ecx eax
		1207	ret
		1208	endp
9138	rgimad	1209
		1210	; Swaps byte order in words
		1211	; base - address of first word
		1212	; len - how many words to swap bytes in
		1213	; doesnt clobber any registers
		1214	proc swap_bytes_in_words stdcall, base: dword, len: dword
		1215	push eax ebx ecx
		1216	xor ecx, ecx
		1217	mov ebx, [base]
		1218	.loop:
		1219	cmp ecx, [len]
		1220	jae .loop_end
		1221	mov ax, word [ebx + ecx*2]
		1222	xchg ah, al
		1223	mov word [ebx + ecx*2], ax
		1224	inc ecx
		1225	jmp .loop
		1226	.loop_end:
		1227	pop ecx ebx eax
		1228	ret
		1229	endp

Subversion Repositories Kolibri OS

(root)/kernel/branches/kolibri-ahci/blkdev/ahci.inc – Rev 9140