WebSVN – Kolibri OS – Blame – /kernel/branches/kolibri-ahci/blkdev/ahci.inc

Rev	Author	Line No.	Line
9020	rgimad	1	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		2	;; ;;
		3	;; Copyright (C) KolibriOS team 2004-2021. All rights reserved. ;;
		4	;; Distributed under terms of the GNU General Public License ;;
		5	;; ;;
		6	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		7
		8	$Revision$
		9
		10	PCI_REG_STATUS_COMMAND = 0x0004
		11	PCI_REG_BAR5 = 0x0024
		12
9023	rgimad	13	; bit_ prefix means that its index of bit
		14	; format: bit_AHCI_STR_REG_BIT
		15	bit_AHCI_HBA_CAP2_BOH = 0 ; Supports BIOS/OS Handoff
9020	rgimad	16
9023	rgimad	17	bit_AHCI_HBA_BOHC_BOS = 0 ; BIOS-Owned Semaphore (BIOS owns controller)
		18	bit_AHCI_HBA_BOHC_OOS = 1 ; OS-Owned Semaphore (OS owns controller)
		19	bit_AHCI_HBA_BOHC_BB = 4 ; BIOS Busy (polling bit while BIOS cleans up
9020	rgimad	20
9023	rgimad	21	bit_AHCI_HBA_GHC_AHCI_ENABLE = 31 ; Enable AHCI mode
		22	bit_AHCI_HBA_GHC_RESET = 0 ; Reset HBA
		23	bit_AHCI_HBA_GHC_INTERRUPT_ENABLE = 1 ; Enable interrupts from the HBA
		24
9065	rgimad	25	bit_AHCI_HBA_PxCMD_ST = 0
		26	bit_AHCI_HBA_PxCMD_FRE = 4
		27	bit_AHCI_HBA_PxCMD_FR = 14
		28	bit_AHCI_HBA_PxCMD_CR = 15
		29
9074	rgimad	30	bit_AHCI_H2D_FLAG_CMD = 7
		31
9037	rgimad	32	AHCI_HBA_PxSSTS_DET = 0xF
		33	AHCI_HBA_PORT_IPM_ACTIVE = 1
		34	AHCI_HBA_PxSSTS_DET_PRESENT = 3
		35
9023	rgimad	36	AHCI_MAX_PORTS = 32 ;
9064	rgimad	37	;HBA_MEMORY_SIZE = 0x1100
9020	rgimad	38
9064	rgimad	39	; Frame Information Structure Types
		40	FIS_TYPE_REG_H2D = 0x27 ; Register FIS - host to device
		41	FIS_TYPE_REG_D2H = 0x34 ; Register FIS - device to host
		42	FIS_TYPE_DMA_ACT = 0x39 ; DMA activate FIS - device to host
		43	FIS_TYPE_DMA_SETUP = 0x41 ; DMA setup FIS - bidirectional
		44	FIS_TYPE_DATA = 0x46 ; Data FIS - bidirectional
		45	FIS_TYPE_BIST = 0x58 ; BIST activate FIS - bidirectional
		46	FIS_TYPE_PIO_SETUP = 0x5F ; PIO setup FIS - device to host
		47	FIS_TYPE_DEV_BITS = 0xA1 ; Set device bits FIS - device to host
		48
9020	rgimad	49	struct AHCI_DATA
		50	abar dd ? ; pointer to HBA Memory (BAR5) mapped to virtual kernelspace memory
		51	pcidev dd ? ; pointer to corresponding PCIDEV structure
		52	ends
		53
		54	; Generic Host Control registers
		55	struct HBA_MEM
9064	rgimad	56	cap dd ? ; 0x00, Host capabilities
		57	ghc dd ? ; 0x04, Global host control
		58	is dd ? ; 0x08, Interrupt status
		59	pi dd ? ; 0x0C, Port implemented
		60	version dd ? ; 0x10, Version
9020	rgimad	61	ccc_ctl dd ? ; 0x14, Command completion coalescing control
		62	ccc_pts dd ? ; 0x18, Command completion coalescing ports
		63	em_loc dd ? ; 0x1C, Enclosure management location
		64	em_ctl dd ? ; 0x20, Enclosure management control
9064	rgimad	65	cap2 dd ? ; 0x24, Host capabilities extended
9020	rgimad	66	bohc dd ? ; 0x28, BIOS/OS handoff control and status
9072	rgimad	67	reserved rb (0xA0-HBA_MEM.reserved) ; 0x2C - 0x9F, Reserved
		68	vendor rb (0x100-HBA_MEM.vendor) ; 0xA0 - 0xFF, Vendor specific
9023	rgimad	69	ports rb (sizeof.HBA_PORT*AHCI_MAX_PORTS) ; 0x100 - 0x10FF, Port control registers, max AHCI_MAX_PORTS
9020	rgimad	70	ends
		71
		72	; Port Control registers
		73	struct HBA_PORT
9064	rgimad	74	command_list_base_l dd ? ; 0x00, command list base address, 1K-byte aligned
		75	command_list_base_h dd ? ; 0x04, command list base address upper 32 bits, used on 64 bit systems
		76	fis_base_l dd ? ; 0x08, FIS base address, 256-byte aligned
		77	fis_base_h dd ? ; 0x0C, FIS base address upper 32 bits, used on 64 bit systems
		78	interrupt_status dd ? ; 0x10
		79	interrupt_enable dd ? ; 0x14
		80	command dd ? ; 0x18, command and status
		81	reserved0 dd ? ; 0x1C
		82	task_file_data dd ? ; 0x20
		83	signature dd ? ; 0x24
		84	sata_status dd ? ; 0x28, SATA status (SCR0:SStatus)
		85	sata_control dd ? ; 0x2C, SATA control (SCR2:SControl)
		86	sata_error dd ? ; 0x30, SATA error (SCR1:SError)
		87	sata_active dd ? ; 0x34, SATA active (SCR3:SActive)
		88	command_issue dd ? ; 0x38
		89	sata_notification dd ? ; 0x3C, SATA notification (SCR4:SNotification)
		90	fis_based_switch_control dd ? ; 0x40
		91	reserved1 rd 11 ; 0x44 - 0x6F
		92	vendor rd 4 ; 0x70 - 0x7F, vendor specific
9020	rgimad	93	ends
		94
9074	rgimad	95	; Command header structure, size = 32 bytes
9068	rgimad	96	struct HBA_CMD_HDR
		97	_flags1 db ? ; 0bPWACCCCC, P - Prefetchable, W - Write (1: H2D, 0: D2H)
		98	; A - ATAPI, C - Command FIS length in DWORDS, 2 ~ 16
		99
		100	_flags2 db ? ; 0bPPPPRCB(Re), P - Port multiplier port, R - Reserved,
		101	; C - Clear busy upon R_OK, B - BIST, Re - Reset
		102
		103	prdtl dw ? ; Physical region descriptor table length in entries
		104	prdbc dd ? ; Physical region descriptor byte count transferred
		105	ctba dd ? ; Command table descriptor base address
		106	ctbau dd ? ; Command table descriptor base address upper 32 bits
9072	rgimad	107	rd 4 ; Reserved
9068	rgimad	108	ends
		109
9074	rgimad	110	; Physical region descriptor table entry, size = 16 bytes
9069	rgimad	111	struct HBA_PRDT_ENTRY
		112	dba dd ? ; Data base address
		113	dbau dd ? ; Data base address upper 32 bits
9072	rgimad	114	dd ? ; Reserved
9069	rgimad	115	_flags dd ? ; 0bIR..RD..D, I (1 bit) - Interrupt on completion,
		116	; R (9 bits) - Reserved, D (22 bits) - Byte count, 4M max
		117	ends
		118
		119	struct HBA_CMD_TBL
		120	cfis rb 64 ; 0x00, Command FIS
		121	acmd rb 16 ; 0x40, ATAPI command, 12 or 16 bytes
9072	rgimad	122	rb 48 ; 0x50, Reserved
9069	rgimad	123	prdt_entry HBA_PRDT_ENTRY ; 0x80, Physical region descriptor table entries, 0 ~ 65535
		124	; so, this structure is variable-length
		125	ends
		126
9068	rgimad	127	; Contains virtual mappings for port phys memory regions
		128	struct PORT_DATA
		129	clb dd ? ; Command list base
		130	fb dd ? ; FIS base
		131	ctba_arr rd 32 ; ctba_arr[0] = clb[0].ctba, ... and so on.
		132	port dd ? ; address of correspoding HBA_PORT structure
9074	rgimad	133	portno dd ? ; port index, 0..31
9068	rgimad	134	ends
		135
9064	rgimad	136	; Register FIS – Host to Device
		137	struct FIS_REG_H2D
		138	fis_type db ? ; FIS_TYPE_REG_H2D
		139	_flags db ? ; 0bCRRRPPPP, C - 1: Command, 0: Control
		140	; R - Reserved, P - Port multiplier
		141
		142	command db ? ; Command register
		143	featurel db ? ; Feature register, 7:0
		144
		145	lba0 db ? ; LBA low register, 7:0
		146	lba1 db ? ; LBA mid register, 15:8
		147	lba2 db ? ; LBA high register, 23:16
		148	device db ? ; Device register
		149
		150	lba3 db ? ; LBA register, 31:24
		151	lba4 db ? ; LBA register, 39:32
		152	lba5 db ? ; LBA register, 47:40
		153	featureh db ? ; Feature register, 15:8
		154
		155	countl db ? ; Count register, 7:0
		156	counth db ? ; Count register, 15:8
		157	icc db ? ; Isochronous command completion
		158	control db ? ; Control register
		159
9072	rgimad	160	rb 4 ; Reserved
9064	rgimad	161	ends
		162
		163	; Register FIS – Device to Host
		164	struct FIS_REG_D2H
		165	fis_type db ? ; FIS_TYPE_REG_D2H
		166
		167	_flags db ? ; 0bRIRPPPP, P - Port multiplier, R - Reserved
		168	; I - Interrupt bit
		169
		170	status db ? ; Status register
		171	error db ? ; Error register
		172
		173	lba0 db ? ; LBA low register, 7:0
		174	lba1 db ? ; LBA mid register, 15:8
		175	lba2 db ? ; LBA high register, 23:16
		176	device db ? ; Device register
		177
		178	lba3 db ? ; LBA register, 31:24
		179	lba4 db ? ; LBA register, 39:32
		180	lba5 db ? ; LBA register, 47:40
9072	rgimad	181	db ? ; Reserved
9064	rgimad	182
		183	countl db ? ; Count register, 7:0
		184	counth db ? ; Count register, 15:8
9072	rgimad	185	rb 2 ; Reserved
9064	rgimad	186
9072	rgimad	187	rb 4 ; Reserved
9064	rgimad	188	ends
		189
		190	; Data FIS – Bidirectional
		191	struct FIS_DATA
		192	fis_type db ? ; FIS_TYPE_DATA
		193	_flags db ? ; 0bRRRRPPPP, R - Reserved, P - Port multiplier
9072	rgimad	194	rb 2 ; Reserved
9064	rgimad	195	; DWORD 1 ~ N (?)
		196	data rd 1 ; Payload
		197	ends
		198
		199	; PIO Setup – Device to Host
		200	struct FIS_PIO_SETUP
		201	fis_type db ? ; FIS_TYPE_PIO_SETUP
		202
		203	_flags db ? ; 0bRIDRPPPP, P - Port multiplier, R - Reserved
		204	; I - Interrupt bit, D - Data transfer direction, 1 - device to host
		205
		206	status db ? ; Status register
		207	error db ? ; Error register
		208
		209	lba0 db ? ; LBA low register, 7:0
		210	lba1 db ? ; LBA mid register, 15:8
		211	lba2 db ? ; LBA high register, 23:16
		212	device db ? ; Device register
		213
		214	lba3 db ? ; LBA register, 31:24
		215	lba4 db ? ; LBA register, 39:32
		216	lba5 db ? ; LBA register, 47:40
9072	rgimad	217	db ? ; Reserved
9064	rgimad	218
		219	countl db ? ; Count register, 7:0
		220	counth db ? ; Count register, 15:8
9072	rgimad	221	db ? ; Reserved
9064	rgimad	222	e_status db ? ; New value of status register
		223
		224	tc dw ? ; Transfer count
9072	rgimad	225	rb 2 ; Reserved
9064	rgimad	226	ends
		227
		228	; DMA Setup – Device to Host
		229	struct FIS_DMA_SETUP
		230	fis_type db ? ; FIS_TYPE_DMA_SETUP
		231	_flags db ? ; 0bAIDRPPPP, A - Auto-activate. Specifies if DMA Activate FIS is needed,
		232	; I - Interrupt bit, D - Data transfer direction, 1 - device to host,
		233	; R - Reserved, P - Port multiplier
		234
9072	rgimad	235	rb 2 ; Reserved
9064	rgimad	236	DMAbufferID dq ? ; DMA Buffer Identifier.
		237	; Used to Identify DMA buffer in host memory.
		238	; SATA Spec says host specific and not in Spec.
		239	; Trying AHCI spec might work.
		240
9072	rgimad	241	dd ? ; Reserved
		242	DMAbufOffset dd ? ; Byte offset into buffer. First 2 bits must be 0
9064	rgimad	243	TransferCount dd ? ; Number of bytes to transfer. Bit 0 must be 0
9072	rgimad	244	dd ? ; Reserved
9064	rgimad	245	ends
		246
		247	; Set device bits FIS - device to host
		248	struct FIS_DEV_BITS
		249	fis_type db ? ; FIS_TYPE_DEV_BITS
		250	_flags db ? ; 0bNIRRPPPP, N - Notification, I - Interrupt,
		251	; R - Reserved, P - Port multiplier
		252
		253	status db ? ; Status register
		254	error db ? ; Error register
		255
		256	protocol dd ? ; Protocol
		257	ends
		258
9069	rgimad	259	struct HBA_FIS
		260	dsfis FIS_DMA_SETUP ; 0x00, DMA Setup FIS
9072	rgimad	261	rb 4 ; padding
9069	rgimad	262
		263	psfis FIS_PIO_SETUP ; 0x20, PIO Setup FIS
9072	rgimad	264	rb 12 ; padding
9069	rgimad	265
		266	rfis FIS_REG_D2H ; 0x40, Register - Device to Host FIS
9072	rgimad	267	rb 4 ; padding
9069	rgimad	268
		269	sdbfis FIS_DEV_BITS ; 0x58, Set Device Bit FIS
		270
		271	ufis rb 64 ; 0x60
		272
9072	rgimad	273	rb (0x100 - 0xA0) ; 0xA0, Reserved
9069	rgimad	274	ends
		275
9064	rgimad	276	; --------------------------------------------------
9020	rgimad	277	uglobal
		278	align 4
		279	ahci_controller AHCI_DATA
9068	rgimad	280	port_data_arr rb (sizeof.PORT_DATA*AHCI_MAX_PORTS)
9020	rgimad	281	endg
		282
9064	rgimad	283	; -----------------------------------------------------------------------
9020	rgimad	284	; detect ahci controller and initialize
		285	align 4
9068	rgimad	286	ahci_init:
9020	rgimad	287	mov ecx, ahci_controller
		288	mov esi, pcidev_list
		289	.find_ahci_ctr:
		290	mov esi, [esi + PCIDEV.fd]
		291	cmp esi, pcidev_list
		292	jz .ahci_ctr_not_found
		293	mov eax, [esi + PCIDEV.class]
		294	;DEBUGF 1, "K: device class = %x\n", eax
		295	shr eax, 8 ; shift right because lowest 8 bits if ProgIf field
		296	cmp eax, 0x0106 ; 0x01 - Mass Storage Controller class, 0x06 - Serial ATA Controller subclass
		297	jz .ahci_ctr_found
		298	jmp .find_ahci_ctr
		299
		300	.ahci_ctr_not_found:
		301	DEBUGF 1, "K: AHCI controller not found\n"
		302	ret
		303
		304	.ahci_ctr_found:
		305	mov [ahci_controller + AHCI_DATA.pcidev], esi
		306
		307	mov eax, [esi+PCIDEV.class]
		308	movzx ebx, byte [esi+PCIDEV.bus]
		309	movzx ecx, byte [esi+PCIDEV.devfn]
		310	shr ecx, 3 ; get rid of 3 lowest bits (function code), the rest bits is device code
		311	movzx edx, byte [esi+PCIDEV.devfn]
		312	and edx, 00000111b ; get only 3 lowest bits (function code)
		313	DEBUGF 1, "K: found AHCI controller, (class, subcl, progif) = %x, bus = %x, device = %x, function = %x\n", eax, ebx, ecx, edx
		314
9023	rgimad	315	; get BAR5 value, it is physical address
9037	rgimad	316	movzx ebx, [esi + PCIDEV.bus]
		317	movzx ebp, [esi + PCIDEV.devfn]
		318	stdcall pci_read32, ebx, ebp, PCI_REG_BAR5
		319	DEBUGF 1, "K: AHCI controller MMIO = %x\n", eax
		320	mov edi, eax
9020	rgimad	321
9037	rgimad	322	; get the size of MMIO region
		323	stdcall pci_write32, ebx, ebp, PCI_REG_BAR5, 0xFFFFFFFF
		324	stdcall pci_read32, ebx, ebp, PCI_REG_BAR5
		325	not eax
		326	inc eax
		327	DEBUGF 1, "K: AHCI: MMIO region size = 0x%x bytes\n", eax
		328
		329	; Map MMIO region to virtual memory
		330	stdcall map_io_mem, edi, eax, PG_SWR + PG_NOCACHE
9020	rgimad	331	mov [ahci_controller + AHCI_DATA.abar], eax
		332	DEBUGF 1, "K: AHCI controller BAR5 mapped to virtual addr %x\n", eax
		333
9037	rgimad	334	; Restore the original BAR5 value
		335	stdcall pci_write32, ebx, ebp, PCI_REG_BAR5, edi
		336
9023	rgimad	337	; Enable dma bus mastering, memory space access, clear the "disable interrupts" bit
		338	; Usually, it is already done before us
9024	rgimad	339	movzx ebx, [esi + PCIDEV.bus]
		340	movzx ebp, [esi + PCIDEV.devfn]
		341	stdcall pci_read32, ebx, ebp, PCI_REG_STATUS_COMMAND
9020	rgimad	342	DEBUGF 1, "K: AHCI: pci_status_command = %x\nEnabling interrupts, DMA bus mastering and memory space access\n", eax
		343	or eax, 0x06 ; pci.command \|= 0x06 (dma bus mastering + memory space access)
		344	btr eax, 10 ; clear the "disable interrupts" bit
		345	DEBUGF 1, "K: AHCI: pci_status_command = %x\n", eax
9024	rgimad	346	stdcall pci_write32, ebx, ebp, PCI_REG_STATUS_COMMAND, eax
9020	rgimad	347
9023	rgimad	348	; ; Print some register values to debug board
		349	; mov esi, [ahci_controller + AHCI_DATA.abar]
9064	rgimad	350	; DEBUGF 1, "K: AHCI: HBA.cap = %x, HBA.ghc = %x, HBA_MEM.version = %x\n", [esi + HBA_MEM.cap], [esi + HBA_MEM.ghc], [esi + HBA_MEM.version]
9020	rgimad	351
9023	rgimad	352	;-------------------------------------------------------
		353	; Request BIOS/OS ownership handoff, if supported. (TODO check correctness)
		354	mov esi, [ahci_controller + AHCI_DATA.abar]
9064	rgimad	355	;mov ebx, [esi + HBA_MEM.cap2]
9023	rgimad	356	;DEBUGF 1, "K: AHCI: HBA_MEM.cap2 = %x\n", ebx
9064	rgimad	357	bt [esi + HBA_MEM.cap2], bit_AHCI_HBA_CAP2_BOH
9020	rgimad	358	jnc .end_handoff
9023	rgimad	359	DEBUGF 1, "K: AHCI: requesting AHCI ownership change...\n"
9024	rgimad	360	bts [esi + HBA_MEM.bohc], bit_AHCI_HBA_BOHC_OOS
9020	rgimad	361
		362	.wait_not_bos:
9024	rgimad	363	bt [esi + HBA_MEM.bohc], bit_AHCI_HBA_BOHC_BOS
9020	rgimad	364	jc .wait_not_bos
		365
		366	mov ebx, 3
		367	call delay_hs
		368
9023	rgimad	369	; if Bios Busy is still set after 30 mS, wait 2 seconds.
9024	rgimad	370	bt [esi + HBA_MEM.bohc], bit_AHCI_HBA_BOHC_BB
9020	rgimad	371	jnc @f
		372
		373	mov ebx, 200
		374	call delay_hs
		375	@@:
9023	rgimad	376	DEBUGF 1, "K: AHCI: ownership change completed.\n"
9020	rgimad	377
		378	.end_handoff:
9023	rgimad	379	;-------------------------------------------------------
9020	rgimad	380
9023	rgimad	381	; enable the AHCI and reset it
9064	rgimad	382	bts [esi + HBA_MEM.ghc], bit_AHCI_HBA_GHC_AHCI_ENABLE
		383	bts [esi + HBA_MEM.ghc], bit_AHCI_HBA_GHC_RESET
9020	rgimad	384
9023	rgimad	385	; wait for reset to complete
		386	.wait_reset:
9064	rgimad	387	bt [esi + HBA_MEM.ghc], bit_AHCI_HBA_GHC_RESET
9023	rgimad	388	jc .wait_reset
9020	rgimad	389
9023	rgimad	390	; enable the AHCI and interrupts
9064	rgimad	391	bts [esi + HBA_MEM.ghc], bit_AHCI_HBA_GHC_AHCI_ENABLE
		392	bts [esi + HBA_MEM.ghc], bit_AHCI_HBA_GHC_INTERRUPT_ENABLE
9023	rgimad	393	mov ebx, 2
		394	call delay_hs
		395
9064	rgimad	396	DEBUGF 1, "K: AHCI: caps: %x %x, ver: %x, ghc: %x, pi: %x\n", [esi + HBA_MEM.cap], [esi + HBA_MEM.cap2], [esi + HBA_MEM.version], [esi + HBA_MEM.ghc], [esi + HBA_MEM.pi]
9020	rgimad	397
9037	rgimad	398	; TODO:
		399	; calculate irq line
		400	; ahciHBA->ghc \|= AHCI_GHC_IE;
		401	; IDT::RegisterInterruptHandler(irq, InterruptHandler);
9064	rgimad	402	; ahciHBA->is = 0xffffffff;
9037	rgimad	403
		404	xor ebx, ebx
		405	.detect_drives:
		406	cmp ebx, AHCI_MAX_PORTS
		407	jae .end_detect_drives
		408
		409	; if port with index ebx is not implemented then go to next
9064	rgimad	410	mov ecx, [esi + HBA_MEM.pi]
9037	rgimad	411	bt ecx, ebx
		412	jnc .continue_detect_drives
		413
		414	mov edi, ebx
9074	rgimad	415	imul edi, sizeof.HBA_PORT
9037	rgimad	416	add edi, HBA_MEM.ports
		417	add edi, esi
		418	; now edi - base of HBA_MEM.ports[ebx]
		419
		420	DEBUGF 1, "K: AHCI: port %d, ssts = %x\n", ebx, [edi + HBA_PORT.sata_status]
		421
		422	mov ecx, [edi + HBA_PORT.sata_status]
		423	shr ecx, 8
		424	and ecx, 0x0F
		425	cmp ecx, AHCI_HBA_PORT_IPM_ACTIVE
		426	jne .continue_detect_drives
		427
		428	mov ecx, [edi + HBA_PORT.sata_status]
		429	and ecx, AHCI_HBA_PxSSTS_DET
		430	cmp ecx, AHCI_HBA_PxSSTS_DET_PRESENT
9068	rgimad	431	jne .continue_detect_drives
9037	rgimad	432
9068	rgimad	433	DEBUGF 1, "K: AHCI: found drive at port %d, signature = %x\n", ebx, [edi + HBA_PORT.signature]
9037	rgimad	434
9068	rgimad	435	mov ecx, ebx
9074	rgimad	436	imul ecx, sizeof.PORT_DATA
9068	rgimad	437	add ecx, port_data_arr
		438	stdcall ahci_port_rebase, edi, ebx, ecx
		439
9074	rgimad	440	stdcall ahci_port_identify, ecx
		441
9037	rgimad	442	.continue_detect_drives:
		443	inc ebx
		444	jmp .detect_drives
		445
9064	rgimad	446
9037	rgimad	447
		448	.end_detect_drives:
		449
		450
9020	rgimad	451	ret
9065	rgimad	452	; -------------------------------------------------
9020	rgimad	453
9074	rgimad	454	modelstr rb 42
		455	; Identify drive on port ; TODO check
		456	; in: pdata - address of PORT_DATA structure
		457	proc ahci_port_identify stdcall, pdata: dword
		458	locals
		459	cmdslot dd ?
		460	cmdheader dd ?
		461	cmdtable dd ?
		462	buf_phys dd ?
		463	buf_virt dd ?
		464	endl
		465
		466	pushad
		467
		468	mov esi, [pdata] ; esi - address of PORT_DATA struct of port
		469	mov edi, [esi + PORT_DATA.port] ; edi - address of HBA_PORT struct of port
		470
		471	mov eax, edi
		472	call ahci_find_cmdslot
		473
		474	cmp eax, -1
		475	jne .cmdslot_found
		476
		477	DEBUGF 1, "No free cmdslot on port %u\n", [esi + PORT_DATA.portno]
		478
		479	.cmdslot_found:
		480	mov [cmdslot], eax
		481	DEBUGF 1, "Found free cmdslot %u on port %u\n", [cmdslot], [esi + PORT_DATA.portno]
		482
		483	shl eax, BSF sizeof.HBA_CMD_HDR
		484	add eax, [esi + PORT_DATA.clb]
		485	mov [cmdheader], eax ; address of virtual mapping of command header
		486	mov eax, [cmdslot]
		487	mov eax, [esi + eax*4 + PORT_DATA.ctba_arr]
		488	mov [cmdtable], eax ; address of virtual mapping of command table of command header
		489
		490	stdcall _memset, eax, 0, sizeof.HBA_CMD_TBL
		491
		492	call alloc_page
		493	mov [buf_phys], eax
		494
		495	stdcall map_io_mem, eax, 4096, PG_NOCACHE + PG_SWR ; map to virt memory so we can work with it
		496	mov [buf_virt], eax
		497
		498	mov eax, [cmdtable]
		499	mov ebx, [buf_phys]
		500	mov dword [eax + HBA_CMD_TBL.prdt_entry + HBA_PRDT_ENTRY.dba], ebx
		501	mov dword [eax + HBA_CMD_TBL.prdt_entry + HBA_PRDT_ENTRY.dbau], 0
		502	mov dword [eax + HBA_CMD_TBL.prdt_entry + HBA_PRDT_ENTRY._flags], 512 - 1 ; why -1 ?
		503	mov eax, [cmdheader]
		504	mov [eax + HBA_CMD_HDR.prdtl], 1
		505
		506	mov eax, [cmdtable]
		507	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.fis_type], FIS_TYPE_REG_H2D
		508	movzx ebx, byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D._flags]
		509	bts ebx, bit_AHCI_H2D_FLAG_CMD ; Set Command bit in H2D FIS.
		510	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D._flags], bl
		511	; if (port->signature == AHCI_PxSIG_ATAPI) cmd_fis->command = ATA_IDENTIFY_PACKET;
		512	; else cmd_fis->command = ATA_IDENTIFY;
		513	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.command], 0xEC ;ATA_IDENTIFY ;
		514	mov byte [eax + HBA_CMD_TBL.cfis + FIS_REG_H2D.device], 0
		515
		516	; TODO Wait on previous command to complete. AHCIPortWait(bd->port_num, tS + 2);
		517	mov ebx, 20 ;;;
		518	call delay_hs ;;;
		519
		520	mov eax, [cmdslot]
		521	bts [edi + HBA_PORT.command_issue], eax ; Issue the command
		522
		523	; TODO AHCIPortCmdWait(bd->port_num, cmd_slot);
		524	mov ebx, 20 ;;;
		525	call delay_hs ;;;
		526
		527	mov esi, [buf_virt]
		528	add esi, 27*2
		529	mov edi, modelstr
		530	mov ecx, ((46-27)+1)*2
		531	cld
		532	rep movsb
		533	mov byte [edi], 0
		534
		535	xor ecx, ecx
		536	.reverse1:
		537	cmp ecx, ((46-27)+1)*2
		538	jae .reverse1_end
		539	mov bl, byte [modelstr + ecx]
		540	mov dl, byte [modelstr + ecx + 1]
		541	mov byte [modelstr + ecx], dl
		542	mov byte [modelstr + ecx + 1], bl
		543	add ecx, 2
		544	jmp .reverse1
		545	.reverse1_end:
		546	DEBUGF 1, "Ident data of port: model = %s\n", modelstr
		547
		548	.ret:
		549	popad
		550	ret
		551	endp
		552
9065	rgimad	553	; Start command engine
		554	; in: eax - address of HBA_PORT structure
9068	rgimad	555	ahci_start_cmd:
9065	rgimad	556	.wait_cr: ; Wait until CR (bit15) is cleared
		557	bt [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_CR
		558	jc .wait_cr
		559
		560	; Set FRE (bit4) and ST (bit0)
		561	bts [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_FRE
		562	bts [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_ST
9068	rgimad	563	; maybe here call ahci flush cmd ? TODO (see seakernel)
9065	rgimad	564	ret
		565
		566	; Stop command engine
		567	; in: eax - address of HBA_PORT structure
9068	rgimad	568	ahci_stop_cmd:
9065	rgimad	569	btr [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_ST ; Clear ST (bit0)
		570	btr [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_FRE ; Clear FRE (bit4)
		571	.wait_fr_cr: ; Wait until FR (bit14), CR (bit15) are cleared
		572	bt [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_FR
		573	jc .wait_fr_cr
		574	bt [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_CR
		575	jc .wait_fr_cr
		576
		577	ret
		578
9068	rgimad	579	; The commands may not take effect until the command
		580	; register is read again by software, because reasons.
		581	; in: eax - address of HBA_PORT structure
		582	; out: eax - command register value
		583	ahci_flush_cmd:
		584	mov eax, [eax + HBA_PORT.command]
		585	ret
9065	rgimad	586
9068	rgimad	587	; Send command to port
		588	; in: eax - address of HBA_PORT structure
		589	; ebx - index of command slot
		590	ahci_send_cmd:
		591	push ecx
		592	mov [eax + HBA_PORT.interrupt_status], 0xFFFFFFFF
		593
		594	mov cl, bl
		595	mov [eax + HBA_PORT.command_issue], 1
		596	shl [eax + HBA_PORT.command_issue], cl
9065	rgimad	597
9068	rgimad	598	call ahci_flush_cmd
		599	pop ecx
		600	ret
9065	rgimad	601
9068	rgimad	602	; ---------------------------------------------------------------------------
		603	; TODO: check correctness
		604	; in: port - address of HBA_PORT structure
		605	; portno - port index (0..31)
		606	; pdata - address of PORT_DATA structure
		607	proc ahci_port_rebase stdcall, port: dword, portno: dword, pdata: dword
		608	locals
		609	phys_page1 dd ?
		610	virt_page1 dd ?
		611	phys_page23 dd ?
		612	virt_page23 dd ?
		613	tmp dd ?
		614	endl
		615
		616	pushad
		617
		618	DEBUGF 1, "Rebasing port %u\n", [portno]
		619
		620	mov eax, [port]
		621	call ahci_stop_cmd
		622
		623	; Command list entry size = 32
		624	; Command list entry maxim count = 32
		625	; Command list maxim size = 32*32 = 1K per port
		626	call alloc_page
		627	mov [phys_page1], eax
		628
		629	stdcall map_io_mem, eax, 4096, PG_NOCACHE + PG_SWR ; map to virt memory so we can work with it
		630	mov [virt_page1], eax
		631
		632	mov esi, [port]
		633	mov ebx, [phys_page1]
		634	mov [esi + HBA_PORT.command_list_base_l], ebx ; set the command list base
		635	mov [esi + HBA_PORT.command_list_base_h], 0 ; zero upper 32 bits of addr cause we are 32 bit os
		636
		637	mov edi, [pdata]
		638	mov ebx, [virt_page1]
		639	mov [edi + PORT_DATA.clb], ebx ; set pdata->clb
		640
		641	mov eax, [port]
		642	mov [edi + PORT_DATA.port], eax ; set pdata->port
9074	rgimad	643	mov eax, [portno] ; set pdata->portno
		644	mov [edi + PORT_DATA.portno], eax
9068	rgimad	645
		646	stdcall _memset, ebx, 0, 1024 ; zero out the command list
		647
		648	; FIS entry size = 256 bytes per port
		649	mov eax, [phys_page1]
		650	add eax, 1024
		651	mov [esi + HBA_PORT.fis_base_l], eax
		652	mov [esi + HBA_PORT.fis_base_h], 0
		653
		654	mov eax, [virt_page1]
		655	add eax, 1024
		656	mov [edi + PORT_DATA.fb], eax ; set pdata->fb
		657	stdcall _memset, eax, 0, 256 ; zero out
		658
		659	stdcall alloc_pages, 2
		660	mov [phys_page23], eax
		661	stdcall map_io_mem, eax, 2*4096, PG_NOCACHE + PG_SWR
		662	mov [virt_page23], eax
		663
		664	; Command table size = 256*32 = 8K per port
		665	mov edx, [edi + PORT_DATA.clb] ; cmdheader array base
		666	xor ecx, ecx
		667
		668	.for1:
		669	cmp ecx, 32
		670	jae .for1_end
		671
		672	mov ebx, ecx
		673	shl ebx, BSF sizeof.HBA_CMD_HDR
		674	add ebx, edx ; ebx = cmdheader[ecx]
		675
		676	mov [ebx + HBA_CMD_HDR.prdtl], 8 ; 8 prdt entries per command table
		677
		678	; 256 bytes per command table, 64+16+48+16*8
		679
		680	push edx
		681
		682	; cmdheader[ecx].ctba = phys_page23 + ecx*256
		683	mov [ebx + HBA_CMD_HDR.ctba], ecx
		684	shl [ebx + HBA_CMD_HDR.ctba], BSF 256 ; *= 256
		685	mov eax, [ebx + HBA_CMD_HDR.ctba]
		686	mov edx, [phys_page23]
		687	add [ebx + HBA_CMD_HDR.ctba], edx
		688
		689	add eax, [virt_page23]
		690	mov [tmp], eax ; tmp = virt_page23 + ecx*256
9069	rgimad	691	lea eax, [ecx*4 + edi + PORT_DATA.ctba_arr] ; eax = pdata->ctba_arr[ecx]
9068	rgimad	692	mov edx, [tmp]
		693	mov [eax], edx ; pdata->ctba_arr[ecx] = virt_page23 + ecx*256
		694
		695	pop edx
		696
		697	mov [ebx + HBA_CMD_HDR.ctbau], 0
		698	stdcall _memset, [eax], 0, 256 ; zero out
		699
		700	inc ecx
		701	jmp .for1
		702	.for1_end:
		703
		704	mov eax, [port]
		705	call ahci_start_cmd
		706
		707	DEBUGF 1, "End rebasing port %u\n", [portno]
		708	popad
		709	ret
		710	endp
		711
9069	rgimad	712	; ----------------------------------------------------------- ; TODO check
		713	; Find a free command list slot
		714	; in: eax - address of HBA_PORT structure
		715	; out: eax - if not found -1, else slot index
		716	ahci_find_cmdslot:
		717	push ebx ecx edx esi
		718	; If not set in SACT and CI, the slot is free
		719	mov ebx, [eax + HBA_PORT.sata_active]
		720	or ebx, [eax + HBA_PORT.command_issue] ; ebx = slots
9068	rgimad	721
9069	rgimad	722	mov esi, [ahci_controller + AHCI_DATA.abar]
		723	mov edx, [esi + HBA_MEM.cap]
		724	shr edx, 8
		725	and edx, 0xf
		726	DEBUGF 1, "Number of Command Slots on each port = %u\n", edx
		727	xor ecx, ecx
		728	.for1:
		729	cmp ecx, edx
		730	jae .for1_end
9068	rgimad	731
9069	rgimad	732	; if ((slots&1) == 0) return i;
		733	bt ebx, 0
		734	jc .cont1
		735
		736	mov eax, ecx
		737	jmp .ret
		738
		739	.cont1:
		740	shr ebx, 1
		741	inc ecx
		742	jmp .for1
		743	.for1_end:
		744	DEBUGF 1, "Cannot find free command list entry\n"
		745	mov eax, -1
		746	.ret:
		747	pop esi edx ecx ebx
		748	ret
		749
		750
9068	rgimad	751	proc _memset stdcall, dest:dword, val:byte, cnt:dword ; doesnt clobber any registers
		752	;DEBUGF DBG_INFO, "memset(%x, %u, %u)\n", [dest], [val], [cnt]
		753	push eax ecx edi
		754	mov edi, dword [dest]
		755	mov al, byte [val]
		756	mov ecx, dword [cnt]
9069	rgimad	757	rep stosb
9068	rgimad	758	pop edi ecx eax
		759	ret
		760	endp

Subversion Repositories Kolibri OS

(root)/kernel/branches/kolibri-ahci/blkdev/ahci.inc @ 9417 – Rev 9074